From patchwork Thu Nov 2 15:11:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Duje_Mihanovi=C4=87?= X-Patchwork-Id: 741159 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38B16C001DD for ; Thu, 2 Nov 2023 15:12:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235151AbjKBPMS (ORCPT ); Thu, 2 Nov 2023 11:12:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234161AbjKBPMP (ORCPT ); Thu, 2 Nov 2023 11:12:15 -0400 Received: from mx.skole.hr (mx1.hosting.skole.hr [161.53.165.185]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33C0E184; Thu, 2 Nov 2023 08:12:05 -0700 (PDT) Received: from mx1.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id E136283668; Thu, 2 Nov 2023 16:12:03 +0100 (CET) From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Thu, 02 Nov 2023 16:11:07 +0100 Subject: [PATCH v7 01/10] clk: mmp: Switch to use struct u32_fract instead of custom one MIME-Version: 1.0 Message-Id: <20231102-pxa1908-lkml-v7-1-cabb1a0cb52b@skole.hr> References: <20231102-pxa1908-lkml-v7-0-cabb1a0cb52b@skole.hr> In-Reply-To: <20231102-pxa1908-lkml-v7-0-cabb1a0cb52b@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tony Lindgren , =?utf-8?q?Duje_Mihanovi=C4=87?= , Daniel Mack , Haojian Zhuang , Robert Jarzmik , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Leo Yan , Zhangfei Gao , Lubomir Rintel , Catalin Marinas , Will Deacon , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, alsa-devel@alsa-project.org, linux-hardening@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej , Andy Shevchenko X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=10456; i=duje.mihanovic@skole.hr; h=from:subject:message-id; bh=sqxBtjyINvn8G7N2wkQVSk/v1B3ysA2Koysxb18POPo=; b=owEBbQKS/ZANAwAIAZoRnrBCLZbhAcsmYgBlQ7w43Yv6bShtALLqUOTgGZ9xZ1XbQVL+J01Ms vZP5e/w5mCJAjMEAAEIAB0WIQRT351NnD/hEPs2LXiaEZ6wQi2W4QUCZUO8OAAKCRCaEZ6wQi2W 4RNHEACJpEbEwC7DEhsqO819dHKppa9ECj93d8A29xKR+vKQic/vuCi/2fjPpGcQ8ChwYaadBit n8oxARJbFSfymJGOgsXMTFAZRSrwmgViGWK9Yu/uTfXA9kkN05edf04x5Trt5JQwJhFjvfX5pxI gI/ByFnkYGZPQQ0diHt5TUmAD2XEvLYk+wMYL0zwGu/Poqakj8zi9YEoqXho2nnNvN1SuUEBrDe UUP4BG24CtRbk/x6yUmN6XJk7fMEtwNqModtsjuYBmGq9V8T0gqj3Yjf5BXTuR1EnyDlcYDIP8+ Gtbw3EfUgqlA+v1uFi4dTEuBckyoVssyRriYT0jlw1NQCg323TRCRCgG6LMt7gPQ2YDmW959qmF TqycEbJbFK6phdYbSkpgbeWR1VcKU1rugeJa4OApcO4JdUSJ2GohB/ZKx7IBzr2ERd5U7ef8fn1 Law71WiTYQzDI3zzZzzBXjlvs17wyvj7JJPFpa8QoEiJQzzyv3MBZ1U8i3/nhVDaGO/EoIamRNZ eRb+iBd1Ylb64uZPdQPeduRBFnQ+I4xLU6p/KwsUb5jD1D6xCHALGAlm0k2kZXBIu0NMHqnQIeA 7u/b40omg9P6w8F8VUsWfr/WkgjQqPEkNiiztByqk3lBx6Jvxvmg3T6cIsb/e4oTUSa6mmRL+TQ US1dFmMs/VoMnfA== X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=53DF9D4D9C3FE110FB362D789A119EB0422D96E1 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Andy Shevchenko The struct mmp_clk_factor_tbl repeats the generic struct u32_fract. Kill the custom one and use the generic one instead. Signed-off-by: Andy Shevchenko Tested-by: Duje Mihanović Reviewed-by: Linus Walleij Signed-off-by: Duje Mihanović --- drivers/clk/mmp/clk-frac.c | 57 ++++++++++++++++++++-------------------- drivers/clk/mmp/clk-of-mmp2.c | 26 +++++++++--------- drivers/clk/mmp/clk-of-pxa168.c | 4 +-- drivers/clk/mmp/clk-of-pxa1928.c | 6 ++--- drivers/clk/mmp/clk-of-pxa910.c | 4 +-- drivers/clk/mmp/clk.h | 10 +++---- 6 files changed, 51 insertions(+), 56 deletions(-) diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c index 1b90867b60c4..6556f6ada2e8 100644 --- a/drivers/clk/mmp/clk-frac.c +++ b/drivers/clk/mmp/clk-frac.c @@ -26,14 +26,15 @@ static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate, { struct mmp_clk_factor *factor = to_clk_factor(hw); u64 rate = 0, prev_rate; + struct u32_fract *d; int i; for (i = 0; i < factor->ftbl_cnt; i++) { - prev_rate = rate; - rate = *prate; - rate *= factor->ftbl[i].den; - do_div(rate, factor->ftbl[i].num * factor->masks->factor); + d = &factor->ftbl[i]; + prev_rate = rate; + rate = (u64)(*prate) * d->denominator; + do_div(rate, d->numerator * factor->masks->factor); if (rate > drate) break; } @@ -52,23 +53,22 @@ static unsigned long clk_factor_recalc_rate(struct clk_hw *hw, { struct mmp_clk_factor *factor = to_clk_factor(hw); struct mmp_clk_factor_masks *masks = factor->masks; - unsigned int val, num, den; + struct u32_fract d; + unsigned int val; u64 rate; val = readl_relaxed(factor->base); /* calculate numerator */ - num = (val >> masks->num_shift) & masks->num_mask; + d.numerator = (val >> masks->num_shift) & masks->num_mask; /* calculate denominator */ - den = (val >> masks->den_shift) & masks->den_mask; - - if (!den) + d.denominator = (val >> masks->den_shift) & masks->den_mask; + if (!d.denominator) return 0; - rate = parent_rate; - rate *= den; - do_div(rate, num * factor->masks->factor); + rate = (u64)parent_rate * d.denominator; + do_div(rate, d.numerator * factor->masks->factor); return rate; } @@ -82,18 +82,18 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate, int i; unsigned long val; unsigned long flags = 0; + struct u32_fract *d; u64 rate = 0; for (i = 0; i < factor->ftbl_cnt; i++) { - rate = prate; - rate *= factor->ftbl[i].den; - do_div(rate, factor->ftbl[i].num * factor->masks->factor); + d = &factor->ftbl[i]; + rate = (u64)prate * d->denominator; + do_div(rate, d->numerator * factor->masks->factor); if (rate > drate) break; } - if (i > 0) - i--; + d = i ? &factor->ftbl[i - 1] : &factor->ftbl[0]; if (factor->lock) spin_lock_irqsave(factor->lock, flags); @@ -101,10 +101,10 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate, val = readl_relaxed(factor->base); val &= ~(masks->num_mask << masks->num_shift); - val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift; + val |= (d->numerator & masks->num_mask) << masks->num_shift; val &= ~(masks->den_mask << masks->den_shift); - val |= (factor->ftbl[i].den & masks->den_mask) << masks->den_shift; + val |= (d->denominator & masks->den_mask) << masks->den_shift; writel_relaxed(val, factor->base); @@ -118,7 +118,8 @@ static int clk_factor_init(struct clk_hw *hw) { struct mmp_clk_factor *factor = to_clk_factor(hw); struct mmp_clk_factor_masks *masks = factor->masks; - u32 val, num, den; + struct u32_fract d; + u32 val; int i; unsigned long flags = 0; @@ -128,23 +129,22 @@ static int clk_factor_init(struct clk_hw *hw) val = readl(factor->base); /* calculate numerator */ - num = (val >> masks->num_shift) & masks->num_mask; + d.numerator = (val >> masks->num_shift) & masks->num_mask; /* calculate denominator */ - den = (val >> masks->den_shift) & masks->den_mask; + d.denominator = (val >> masks->den_shift) & masks->den_mask; for (i = 0; i < factor->ftbl_cnt; i++) - if (den == factor->ftbl[i].den && num == factor->ftbl[i].num) + if (d.denominator == factor->ftbl[i].denominator && + d.numerator == factor->ftbl[i].numerator) break; if (i >= factor->ftbl_cnt) { val &= ~(masks->num_mask << masks->num_shift); - val |= (factor->ftbl[0].num & masks->num_mask) << - masks->num_shift; + val |= (factor->ftbl[0].numerator & masks->num_mask) << masks->num_shift; val &= ~(masks->den_mask << masks->den_shift); - val |= (factor->ftbl[0].den & masks->den_mask) << - masks->den_shift; + val |= (factor->ftbl[0].denominator & masks->den_mask) << masks->den_shift; } if (!(val & masks->enable_mask) || i >= factor->ftbl_cnt) { @@ -168,8 +168,7 @@ static const struct clk_ops clk_factor_ops = { struct clk *mmp_clk_register_factor(const char *name, const char *parent_name, unsigned long flags, void __iomem *base, struct mmp_clk_factor_masks *masks, - struct mmp_clk_factor_tbl *ftbl, - unsigned int ftbl_cnt, spinlock_t *lock) + struct u32_fract *ftbl, unsigned int ftbl_cnt, spinlock_t *lock) { struct mmp_clk_factor *factor; struct clk_init_data init; diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c index eaad36ee323d..a4f15cee630e 100644 --- a/drivers/clk/mmp/clk-of-mmp2.c +++ b/drivers/clk/mmp/clk-of-mmp2.c @@ -143,9 +143,9 @@ static struct mmp_clk_factor_masks uart_factor_masks = { .den_shift = 0, }; -static struct mmp_clk_factor_tbl uart_factor_tbl[] = { - {.num = 8125, .den = 1536}, /*14.745MHZ */ - {.num = 3521, .den = 689}, /*19.23MHZ */ +static struct u32_fract uart_factor_tbl[] = { + { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */ + { .numerator = 3521, .denominator = 689 }, /* 19.23MHZ */ }; static struct mmp_clk_factor_masks i2s_factor_masks = { @@ -157,16 +157,16 @@ static struct mmp_clk_factor_masks i2s_factor_masks = { .enable_mask = 0xd0000000, }; -static struct mmp_clk_factor_tbl i2s_factor_tbl[] = { - {.num = 24868, .den = 511}, /* 2.0480 MHz */ - {.num = 28003, .den = 793}, /* 2.8224 MHz */ - {.num = 24941, .den = 1025}, /* 4.0960 MHz */ - {.num = 28003, .den = 1586}, /* 5.6448 MHz */ - {.num = 31158, .den = 2561}, /* 8.1920 MHz */ - {.num = 16288, .den = 1845}, /* 11.2896 MHz */ - {.num = 20772, .den = 2561}, /* 12.2880 MHz */ - {.num = 8144, .den = 1845}, /* 22.5792 MHz */ - {.num = 10386, .den = 2561}, /* 24.5760 MHz */ +static struct u32_fract i2s_factor_tbl[] = { + { .numerator = 24868, .denominator = 511 }, /* 2.0480 MHz */ + { .numerator = 28003, .denominator = 793 }, /* 2.8224 MHz */ + { .numerator = 24941, .denominator = 1025 }, /* 4.0960 MHz */ + { .numerator = 28003, .denominator = 1586 }, /* 5.6448 MHz */ + { .numerator = 31158, .denominator = 2561 }, /* 8.1920 MHz */ + { .numerator = 16288, .denominator = 1845 }, /* 11.2896 MHz */ + { .numerator = 20772, .denominator = 2561 }, /* 12.2880 MHz */ + { .numerator = 8144, .denominator = 1845 }, /* 22.5792 MHz */ + { .numerator = 10386, .denominator = 2561 }, /* 24.5760 MHz */ }; static DEFINE_SPINLOCK(acgr_lock); diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c index fb0df64cf053..ab5f83e77305 100644 --- a/drivers/clk/mmp/clk-of-pxa168.c +++ b/drivers/clk/mmp/clk-of-pxa168.c @@ -106,8 +106,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = { .den_shift = 0, }; -static struct mmp_clk_factor_tbl uart_factor_tbl[] = { - {.num = 8125, .den = 1536}, /*14.745MHZ */ +static struct u32_fract uart_factor_tbl[] = { + { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */ }; static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit) diff --git a/drivers/clk/mmp/clk-of-pxa1928.c b/drivers/clk/mmp/clk-of-pxa1928.c index 9def4b5f10e9..ebb6e278eda3 100644 --- a/drivers/clk/mmp/clk-of-pxa1928.c +++ b/drivers/clk/mmp/clk-of-pxa1928.c @@ -61,9 +61,9 @@ static struct mmp_clk_factor_masks uart_factor_masks = { .den_shift = 0, }; -static struct mmp_clk_factor_tbl uart_factor_tbl[] = { - {.num = 832, .den = 234}, /*58.5MHZ */ - {.num = 1, .den = 1}, /*26MHZ */ +static struct u32_fract uart_factor_tbl[] = { + { .numerator = 832, .denominator = 234 }, /* 58.5MHZ */ + { .numerator = 1, .denominator = 1 }, /* 26MHZ */ }; static void pxa1928_pll_init(struct pxa1928_clk_unit *pxa_unit) diff --git a/drivers/clk/mmp/clk-of-pxa910.c b/drivers/clk/mmp/clk-of-pxa910.c index 7a38c424782e..fe65e7bdb411 100644 --- a/drivers/clk/mmp/clk-of-pxa910.c +++ b/drivers/clk/mmp/clk-of-pxa910.c @@ -86,8 +86,8 @@ static struct mmp_clk_factor_masks uart_factor_masks = { .den_shift = 0, }; -static struct mmp_clk_factor_tbl uart_factor_tbl[] = { - {.num = 8125, .den = 1536}, /*14.745MHZ */ +static struct u32_fract uart_factor_tbl[] = { + { .numerator = 8125, .denominator = 1536 }, /* 14.745MHZ */ }; static void pxa910_pll_init(struct pxa910_clk_unit *pxa_unit) diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h index 55ac05379781..c83cec169ddc 100644 --- a/drivers/clk/mmp/clk.h +++ b/drivers/clk/mmp/clk.h @@ -3,6 +3,7 @@ #define __MACH_MMP_CLK_H #include +#include #include #include @@ -20,16 +21,11 @@ struct mmp_clk_factor_masks { unsigned int enable_mask; }; -struct mmp_clk_factor_tbl { - unsigned int num; - unsigned int den; -}; - struct mmp_clk_factor { struct clk_hw hw; void __iomem *base; struct mmp_clk_factor_masks *masks; - struct mmp_clk_factor_tbl *ftbl; + struct u32_fract *ftbl; unsigned int ftbl_cnt; spinlock_t *lock; }; @@ -37,7 +33,7 @@ struct mmp_clk_factor { extern struct clk *mmp_clk_register_factor(const char *name, const char *parent_name, unsigned long flags, void __iomem *base, struct mmp_clk_factor_masks *masks, - struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt, + struct u32_fract *ftbl, unsigned int ftbl_cnt, spinlock_t *lock); /* Clock type "mix" */ From patchwork Thu Nov 2 15:11:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Duje_Mihanovi=C4=87?= X-Patchwork-Id: 740579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95AFFC41535 for ; Thu, 2 Nov 2023 15:12:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344650AbjKBPMR (ORCPT ); Thu, 2 Nov 2023 11:12:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230205AbjKBPMP (ORCPT ); Thu, 2 Nov 2023 11:12:15 -0400 Received: from mx.skole.hr (mx2.hosting.skole.hr [161.53.165.186]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74531187; Thu, 2 Nov 2023 08:12:06 -0700 (PDT) Received: from mx2.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id D0760848D4; Thu, 2 Nov 2023 16:12:04 +0100 (CET) From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Thu, 02 Nov 2023 16:11:08 +0100 Subject: [PATCH v7 02/10] dt-bindings: pinctrl: pinctrl-single: add marvell,pxa1908-padconf compatible MIME-Version: 1.0 Message-Id: <20231102-pxa1908-lkml-v7-2-cabb1a0cb52b@skole.hr> References: <20231102-pxa1908-lkml-v7-0-cabb1a0cb52b@skole.hr> In-Reply-To: <20231102-pxa1908-lkml-v7-0-cabb1a0cb52b@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tony Lindgren , =?utf-8?q?Duje_Mihanovi=C4=87?= , Daniel Mack , Haojian Zhuang , Robert Jarzmik , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Leo Yan , Zhangfei Gao , Lubomir Rintel , Catalin Marinas , Will Deacon , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, alsa-devel@alsa-project.org, linux-hardening@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej , Rob Herring X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=937; i=duje.mihanovic@skole.hr; h=from:subject:message-id; bh=XB52xSkcW7DlpdxdsDrnjNPD7kW7z6MEd0cFXu6HRPY=; b=owEBbQKS/ZANAwAIAZoRnrBCLZbhAcsmYgBlQ7w4s0X/U4LfTPm+d3uM/f8sVLN8kU+aEvTP7 Uln5kwWiPGJAjMEAAEIAB0WIQRT351NnD/hEPs2LXiaEZ6wQi2W4QUCZUO8OAAKCRCaEZ6wQi2W 4UBOD/9XSrU6k/VpMh4t2ctpZgfmH9BIW4xIC/g7N2fLI3uAYchePaqWsjv/O2ZDBAQ9rKccpMf wzidE0AvYkJQhr/G2EiiDVr4u7b00b2IorTUGkIOkmX8a4tyFI/+KJsaBIVNiBD24va6gZq5Ew2 PoQsztYvv1p2t9RHpS/d0ceDb2GZX0cNq9SeGcBGlR4NZ7EneBmUuTjb2iUL7cN4ovIKyYhGPgJ scW07emNsENae6F/yqJbahnL2HXc4Gi3cDHL/iuNXLos0yzXILsXl7lvIEuhr9IXqhRtJYZ+H9v pUWuO7mt8Xg2QgJAi+qX3ZUuUFkdzLgaGz/AOeCQzxJ6PhMcfWrp51ElmRCqUHZgM08ZZ/NLWF7 PQ1kbIhMN6rgewJvmdr1FfhcXSiUGsAXRdBqvk41wODAjtr0p6u9T7I9IzqrjI0+0t0Bt8XIHIj 7/E8V/TrQ3mJDVAlrPSTeb30/si5QhEQRU7D0YPwnoHXi0EAS1V/VIdU76gUWYcLk3TE9OOQi95 ql5iEImrlQmY25Cxq0uR4GPzE4ya4pXjnkKF1ilnqmF0/5WlFTN3fXG0J0MN2qs+JZ8Z6cR1vjj 0BaJVwy1z8PNobG552NcH0MKhZqvheNQDfRcCaalw1uYiB37dQxAFkiH49UP/xArkEF/aq6Ey/D gGqZRowQytonoWA== X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=53DF9D4D9C3FE110FB362D789A119EB0422D96E1 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add the "marvell,pxa1908-padconf" compatible to allow migrating to a separate pinctrl driver later. Reviewed-by: Rob Herring Signed-off-by: Duje Mihanović --- Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml index 45a307d3ce16..0f7e16a28990 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml @@ -32,6 +32,10 @@ properties: - ti,omap4-padconf - ti,omap5-padconf - const: pinctrl-single + - items: + - enum: + - marvell,pxa1908-padconf + - const: pinconf-single reg: maxItems: 1 From patchwork Thu Nov 2 15:11:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Duje_Mihanovi=C4=87?= X-Patchwork-Id: 741160 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13FA6C0018A for ; Thu, 2 Nov 2023 15:12:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234575AbjKBPMQ (ORCPT ); Thu, 2 Nov 2023 11:12:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234149AbjKBPMP (ORCPT ); Thu, 2 Nov 2023 11:12:15 -0400 Received: from mx.skole.hr (mx1.hosting.skole.hr [161.53.165.185]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1B81DC; Thu, 2 Nov 2023 08:12:07 -0700 (PDT) Received: from mx1.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id 58B5C836CE; Thu, 2 Nov 2023 16:12:06 +0100 (CET) From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Thu, 02 Nov 2023 16:11:09 +0100 Subject: [PATCH v7 03/10] pinctrl: single: add marvell,pxa1908-padconf compatible MIME-Version: 1.0 Message-Id: <20231102-pxa1908-lkml-v7-3-cabb1a0cb52b@skole.hr> References: <20231102-pxa1908-lkml-v7-0-cabb1a0cb52b@skole.hr> In-Reply-To: <20231102-pxa1908-lkml-v7-0-cabb1a0cb52b@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tony Lindgren , =?utf-8?q?Duje_Mihanovi=C4=87?= , Daniel Mack , Haojian Zhuang , Robert Jarzmik , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Leo Yan , Zhangfei Gao , Lubomir Rintel , Catalin Marinas , Will Deacon , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, alsa-devel@alsa-project.org, linux-hardening@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=886; i=duje.mihanovic@skole.hr; h=from:subject:message-id; bh=3vMvyouTrSlTTv/1BlonUdvoKpdtri2jxGZJNXRvhAY=; b=owEBbQKS/ZANAwAIAZoRnrBCLZbhAcsmYgBlQ7w4R0WGAouL6TrH9chgMtCm0ZfVKWBiq89tl Dd9aHZwzXKJAjMEAAEIAB0WIQRT351NnD/hEPs2LXiaEZ6wQi2W4QUCZUO8OAAKCRCaEZ6wQi2W 4SsIEACRIEDbXydKjDCcaYpSifjIjFL7Gii4p2KLIUEwwf8DLR3hGlFL2XK3Mkf1OzluaRtlbns 99kOngBNHCviv0q71rWYiah0Ge4gWEW7tAG9hJbzPdtbTPkFLp27NmVahm+KfSpY48fuDg1Ud6M flhLAYaW61mObhsdXbbF7j5ch76+dAQhgztJJ/XFQw/FT/wuwstxos+FyfLIHPgwCegnAe1Im9J DX/mPZB5AsBVWEZyTGRfIbNA6ZiFeLfBvJUYPquuPtiNywJu7IYmmGIqdMxW9Uh7mNMq95Fgx4z KUN4K6hEozWfFDAtG7NZ6tPqgEzDTL/5Xkd1C+ZCI3244y61yhAJkw3alfHQjZhBR0VooZjWWBk J7pILsKh0H1UhbcGL0umo+/BXUPOWGzHpQp19pY2rqJatvAx+apYtPK9G2z6Cs4V7mE6QsHCv6Z oxNbC0jsYumBAbvXLIAWUxpNEW6RripDS37iwmRr1Xc7gHfB1WfVGn1rF73cDjlJISZgJqL/lTk X9y/t/JGj55a/s8qm8Ll/bixprzbDe+gknRthafU9xWdmtG9pKtItumjJGQpfIoLIXF9Gjb4lTj TnrJr/M/MO27shjg6VusjjJswjN1XxEDqP1qdq0IDW91U4hB8AfeIa4677WGAaXycrTnvBv5XsE KeLsd+RofQxj0mQ== X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=53DF9D4D9C3FE110FB362D789A119EB0422D96E1 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add the "marvell,pxa1908-padconf" compatible to allow migrating to a separate pinctrl driver later. Signed-off-by: Duje Mihanović --- drivers/pinctrl/pinctrl-single.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 461a7c02d4a3..a36f750cfe9f 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1968,6 +1968,7 @@ static const struct pcs_soc_data pinconf_single = { }; static const struct of_device_id pcs_of_match[] = { + { .compatible = "marvell,pxa1908-padconf", .data = &pinconf_single }, { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x }, { .compatible = "ti,am654-padconf", .data = &pinctrl_single_am654 }, { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 }, From patchwork Thu Nov 2 15:11:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Duje_Mihanovi=C4=87?= X-Patchwork-Id: 741158 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDF9DC4167B for ; Thu, 2 Nov 2023 15:12:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230205AbjKBPMU (ORCPT ); Thu, 2 Nov 2023 11:12:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235031AbjKBPMS (ORCPT ); Thu, 2 Nov 2023 11:12:18 -0400 Received: from mx.skole.hr (mx2.hosting.skole.hr [161.53.165.186]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E1681181; Thu, 2 Nov 2023 08:12:10 -0700 (PDT) Received: from mx2.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id 6ACBE84452; Thu, 2 Nov 2023 16:12:09 +0100 (CET) From: =?utf-8?q?Duje_Mihanovi=C4=87?= Date: Thu, 02 Nov 2023 16:11:10 +0100 Subject: [PATCH v7 04/10] dt-bindings: clock: Add Marvell PXA1908 clock bindings MIME-Version: 1.0 Message-Id: <20231102-pxa1908-lkml-v7-4-cabb1a0cb52b@skole.hr> References: <20231102-pxa1908-lkml-v7-0-cabb1a0cb52b@skole.hr> In-Reply-To: <20231102-pxa1908-lkml-v7-0-cabb1a0cb52b@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tony Lindgren , =?utf-8?q?Duje_Mihanovi=C4=87?= , Daniel Mack , Haojian Zhuang , Robert Jarzmik , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Leo Yan , Zhangfei Gao , Lubomir Rintel , Catalin Marinas , Will Deacon , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, alsa-devel@alsa-project.org, linux-hardening@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej , Conor Dooley X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=4927; i=duje.mihanovic@skole.hr; h=from:subject:message-id; bh=TlG0VLv0pzCYmcMvi3T5+D0/zIGO/YXSblFLjN8kznw=; b=owEBbQKS/ZANAwAIAZoRnrBCLZbhAcsmYgBlQ7w49xhaqTXOzdFt0gHzLNW1EexALikZSvwEq u9GVhEYMC6JAjMEAAEIAB0WIQRT351NnD/hEPs2LXiaEZ6wQi2W4QUCZUO8OAAKCRCaEZ6wQi2W 4d7cD/9moMFRvAhX1530vZzK1DRKlabdBeoUsNDun/qFcHII2bZ4+NYzsqpVmJtvQUF7v2o8obc l8OT5p17nZgYox6LbQ+TeLAYx4GFOKI4B2CSQ0hLfZxXLCO5yLn5/16TWEDX3zov2T5ieMoDLcy Okd1c8sCSo7z78f95ZbbGQrMsSehVHWQSrWgG+aqZB9s3ncO99LBao6epEwTlcL4e4vY0QkfRgs lBpfsY4fP7mStIRUhB0Ev+M0hxKcS38b8rzFoLopjq4U041S/7DzvO6GksouWZFAZtKBjZsJD4X jQK/RiiHd9qt6UKMEsciDOaJMRjDUsDb6RMCnSyKaXAlL2Ivs4hYzAU0m5vGwkcRZH/2WRA/UXm VllOeQKVWnMjIG+d4Rok9+i6I4mBVCOEy8n73HRYIiISsad4B22iEBJrRGhDPLdBH2AWFLaA/jZ DOscRYTPuxk2nLq/HjelBeFhvVJ+U3hcsdAPlIN4lkZPkOliR5/JLAdjB1EDz25ljix2jk4Ijzn NerBhg8fTC3wdMCHPSQ3dPFXlYn09aVcD+rKSMNojX441QiI946mT442SD4Ee+kZtfZnKhW/B8T spi8MIjInL2xB33fOp/fh+ekAcPAS2WxQSCWbg1sHQbBJXLHfzs+zERFe4QjLXOC0k4ayz2sJkV DkgpNARkVA8I80A== X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=53DF9D4D9C3FE110FB362D789A119EB0422D96E1 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add dt bindings and documentation for the Marvell PXA1908 clock controller. Reviewed-by: Conor Dooley Signed-off-by: Duje Mihanović --- .../devicetree/bindings/clock/marvell,pxa1908.yaml | 48 ++++++++++++ include/dt-bindings/clock/marvell,pxa1908.h | 88 ++++++++++++++++++++++ 2 files changed, 136 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml new file mode 100644 index 000000000000..4e78933232b6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell PXA1908 Clock Controllers + +maintainers: + - Duje Mihanović + +description: | + The PXA1908 clock subsystem generates and supplies clock to various + controllers within the PXA1908 SoC. The PXA1908 contains numerous clock + controller blocks, with the ones currently supported being APBC, APBCP, MPMU + and APMU roughly corresponding to internal buses. + + All these clock identifiers could be found in . + +properties: + compatible: + enum: + - marvell,pxa1908-apbc + - marvell,pxa1908-apbcp + - marvell,pxa1908-mpmu + - marvell,pxa1908-apmu + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # APMU block: + - | + clock-controller@d4282800 { + compatible = "marvell,pxa1908-apmu"; + reg = <0xd4282800 0x400>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindings/clock/marvell,pxa1908.h new file mode 100644 index 000000000000..fb15b0d0cd4c --- /dev/null +++ b/include/dt-bindings/clock/marvell,pxa1908.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +#ifndef __DTS_MARVELL_PXA1908_CLOCK_H +#define __DTS_MARVELL_PXA1908_CLOCK_H + +/* plls */ +#define PXA1908_CLK_CLK32 1 +#define PXA1908_CLK_VCTCXO 2 +#define PXA1908_CLK_PLL1_624 3 +#define PXA1908_CLK_PLL1_416 4 +#define PXA1908_CLK_PLL1_499 5 +#define PXA1908_CLK_PLL1_832 6 +#define PXA1908_CLK_PLL1_1248 7 +#define PXA1908_CLK_PLL1_D2 8 +#define PXA1908_CLK_PLL1_D4 9 +#define PXA1908_CLK_PLL1_D8 10 +#define PXA1908_CLK_PLL1_D16 11 +#define PXA1908_CLK_PLL1_D6 12 +#define PXA1908_CLK_PLL1_D12 13 +#define PXA1908_CLK_PLL1_D24 14 +#define PXA1908_CLK_PLL1_D48 15 +#define PXA1908_CLK_PLL1_D96 16 +#define PXA1908_CLK_PLL1_D13 17 +#define PXA1908_CLK_PLL1_32 18 +#define PXA1908_CLK_PLL1_208 19 +#define PXA1908_CLK_PLL1_117 20 +#define PXA1908_CLK_PLL1_416_GATE 21 +#define PXA1908_CLK_PLL1_624_GATE 22 +#define PXA1908_CLK_PLL1_832_GATE 23 +#define PXA1908_CLK_PLL1_1248_GATE 24 +#define PXA1908_CLK_PLL1_D2_GATE 25 +#define PXA1908_CLK_PLL1_499_EN 26 +#define PXA1908_CLK_PLL2VCO 27 +#define PXA1908_CLK_PLL2 28 +#define PXA1908_CLK_PLL2P 29 +#define PXA1908_CLK_PLL2VCODIV3 30 +#define PXA1908_CLK_PLL3VCO 31 +#define PXA1908_CLK_PLL3 32 +#define PXA1908_CLK_PLL3P 33 +#define PXA1908_CLK_PLL3VCODIV3 34 +#define PXA1908_CLK_PLL4VCO 35 +#define PXA1908_CLK_PLL4 36 +#define PXA1908_CLK_PLL4P 37 +#define PXA1908_CLK_PLL4VCODIV3 38 + +/* apb (apbc) peripherals */ +#define PXA1908_CLK_UART0 1 +#define PXA1908_CLK_UART1 2 +#define PXA1908_CLK_GPIO 3 +#define PXA1908_CLK_PWM0 4 +#define PXA1908_CLK_PWM1 5 +#define PXA1908_CLK_PWM2 6 +#define PXA1908_CLK_PWM3 7 +#define PXA1908_CLK_SSP0 8 +#define PXA1908_CLK_SSP1 9 +#define PXA1908_CLK_IPC_RST 10 +#define PXA1908_CLK_RTC 11 +#define PXA1908_CLK_TWSI0 12 +#define PXA1908_CLK_KPC 13 +#define PXA1908_CLK_SWJTAG 14 +#define PXA1908_CLK_SSP2 15 +#define PXA1908_CLK_TWSI1 16 +#define PXA1908_CLK_THERMAL 17 +#define PXA1908_CLK_TWSI3 18 + +/* apb (apbcp) peripherals */ +#define PXA1908_CLK_UART2 1 +#define PXA1908_CLK_TWSI2 2 +#define PXA1908_CLK_AICER 3 + +/* axi (apmu) peripherals */ +#define PXA1908_CLK_CCIC1 1 +#define PXA1908_CLK_ISP 2 +#define PXA1908_CLK_DSI1 3 +#define PXA1908_CLK_DISP1 4 +#define PXA1908_CLK_CCIC0 5 +#define PXA1908_CLK_SDH0 6 +#define PXA1908_CLK_SDH1 7 +#define PXA1908_CLK_USB 8 +#define PXA1908_CLK_NF 9 +#define PXA1908_CLK_CORE_DEBUG 10 +#define PXA1908_CLK_VPU 11 +#define PXA1908_CLK_GC 12 +#define PXA1908_CLK_SDH2 13 +#define PXA1908_CLK_GC2D 14 +#define PXA1908_CLK_TRACE 15 +#define PXA1908_CLK_DVC_DFC_DEBUG 16 + +#endif