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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id q8-20020a05600c46c800b0040776008abdsm11817395wmo.40.2023.11.06.03.03.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:03:45 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Akihiko Odaki , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Paolo Bonzini Subject: [PULL 01/60] vl: Free machine list Date: Mon, 6 Nov 2023 12:02:33 +0100 Message-ID: <20231106110336.358-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Akihiko Odaki Free machine list and make LeakSanitizer happy. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230722062641.18505-1-akihiko.odaki@daynix.com> Signed-off-by: Philippe Mathieu-Daudé --- system/vl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/system/vl.c b/system/vl.c index 3fb569254a..ff76eb0d07 100644 --- a/system/vl.c +++ b/system/vl.c @@ -1529,7 +1529,8 @@ static gint machine_class_cmp(gconstpointer a, gconstpointer b) static void machine_help_func(const QDict *qdict) { - GSList *machines, *el; + g_autoptr(GSList) machines = NULL; + GSList *el; const char *type = qdict_get_try_str(qdict, "type"); machines = object_class_get_list(TYPE_MACHINE, false); From patchwork Mon Nov 6 11:02:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741310 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1021370wrr; Mon, 6 Nov 2023 03:04:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IHvvmtJBJmvBim+uJ7H7ALZeGANUyF+6Q36MCFi+ermK0a9ORUuW1MINHFUr+JgB/RxQURg X-Received: by 2002:a0c:eb86:0:b0:66d:953e:226d with SMTP id x6-20020a0ceb86000000b0066d953e226dmr13834558qvo.26.1699268674796; Mon, 06 Nov 2023 03:04:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699268674; cv=none; d=google.com; s=arc-20160816; b=eB7dAi3U0bkkc4BHMvVatXm2DDmByMP4c7JZRGeQvu1d/JUADK6A8DGMJeQnV7ycSs xg3D7hPfRXGHR9z/OQHCqfASJ0vj3qiz6LgeMACv4msHSA+QbMzNJPh8ULMbpC97id3o F+9LI35rYr4/HgbfmYoMrDkWlBUHRKKW1FLyZhExnVuMIjq5rMjj98nVf7DoWxWgj5Q4 gq4Yncg762QLh+A/0kXRJYa29sOo65uG15VBiprI5jHQLv6sVwsMk3n6ANdH89P6dmWG wGPKfehTt+kcGFHlxqGwH+t/r0DseoQCLR3DCOcdTR7IdxzbnLS9eTZrK0AvBedPE8sx G/kA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=d9nIh4jZ3rUpsBw4LSZSNiaZI1TuJJRNoEVBCo+5kN8=; fh=cH6NZHz0vX/LCpLYO2a9Vsevc7oJ78/4JiVNewc1xN0=; b=coD8kxShQBDeO9fEakN814LfH/0OMiTpsIcdCC4Mo5pvHc95NUqrBRUA2CRdFsvtOC JJiz9beaqOC+l+sG74CdvjDJD8jRh5GD9B2h+sW+zuSZC9WlijLFOJan+TU/K1VwPqbl J1lusu03EI+ep5ILbo6GsDauuMmLhiqzU/xcywV5AXVEf7mI+/d2jSMkP35RB8UABFi7 8JlhJW1sAUfFa+O1iYb2riRrzhtjblBee6qHxtb2uKIxPGVjTCAnpojjkWxZjM0UI6K1 E3C/q3Nh74HgBgv/KGAmfZh4scfjESXkq7L3YNorMKWsASo2/zafCxeN5FpjlZBYvL5l x2tw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="EZIH/H0s"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id p12-20020adfce0c000000b0032dc1fc84f2sm9188671wrn.46.2023.11.06.03.03.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:03:53 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini Subject: [PULL 02/60] vl: constify default_list Date: Mon, 6 Nov 2023 12:02:34 +0100 Message-ID: <20231106110336.358-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=philmd@linaro.org; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Marc-André Lureau It's not modified, let's make it const. Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20231030101529.105266-1-marcandre.lureau@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- system/vl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/system/vl.c b/system/vl.c index ff76eb0d07..8c803228f4 100644 --- a/system/vl.c +++ b/system/vl.c @@ -194,7 +194,7 @@ static int default_sdcard = 1; static int default_vga = 1; static int default_net = 1; -static struct { +static const struct { const char *driver; int *flag; } default_list[] = { From patchwork Mon Nov 6 11:02:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741319 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1023436wrr; Mon, 6 Nov 2023 03:08:42 -0800 (PST) X-Google-Smtp-Source: AGHT+IFWIhd2gDyMP2No/yZkiGr2SlhGxeW/oaHOu7x8e9dhSLCh3PyZzdjlouwJCd6+otz+jvem X-Received: by 2002:a05:6214:401c:b0:66d:34a8:3ed0 with SMTP id kd28-20020a056214401c00b0066d34a83ed0mr31453892qvb.26.1699268922576; Mon, 06 Nov 2023 03:08:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699268922; cv=none; d=google.com; s=arc-20160816; b=NIybUIEm5DKJ3kYZfS54KJdpjKfQaAo718Paquyw6kZGy1x8ati9xy3keWp2kUC5Kc gq3gW+oPxI8NNwhSQiLwjl+U9JnTtkF3F6k32NrETJ0FTnbLnL/iD4GClshvCGOzvyDR 5L+7rkJeYjSofK5D3LBZhQB+nn2AxqwSri8Nsus1KyxlEDLSMquiwydwqBcLHJD94+Lo ZT0FnqIzUhp/a2JBxb29NZCNzTD/iJ9Q8NDoyXihYXaHyJKYR4I1f76GJsIGSVdxCkLd K45qpnuBWAL4csWsblshqLocyrPQ/6zviQuWVe/XGklDgFepXtPAu8bKp6y+IrdxE5eg 1VDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OPtEnXMJWXTavrW+hTGrjLz6IdGpJzROhuSvymabGIo=; fh=Jo/ucEdKrq0dSRmZHiojvQ6EZQCjhpZSt5vPHyvMZxA=; b=jOEdFJVlBjk8m53+K9bePvVrvJCGNIUbgDEU052xKHZ2DHneI/PUwpfqBNrLgEyHte 6sXXV0SSTJY7fhua+FWwDfionv5Ae1PryPNXB/nHJdYA4oA7jqzCyBaw7xrZfd58ptG9 h3s3WzicGUmvwKAs5hIocfqe4RWzq5PEGEKj2k5s1KyKUHifC0fZAJg9wobmoN+ca+P8 0pgkT9L8KWBWiroeDmipMHzaMAbXOTqjszaDgDZ2Cbs17eqiV6ZjIpsm01wFqnV2NZ8n bzWaKc8SVF1uggqzbWUOJU2Z8Kbyp/h4bmDxZCgaMrfwhtfdERblTZb/gWG9bVtvoReL SNzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=p9co09Ev; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id l10-20020adff48a000000b0032fdcbfb093sm19447wro.81.2023.11.06.03.03.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:04:00 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Alex?= =?utf-8?q?_Benn=C3=A9e?= , Richard Henderson , Thomas Huth , Wainer dos Santos Moschetta , Beraldo Leal Subject: [PULL 03/60] tests/vm/ubuntu.aarch64: Correct comment about TCG specific delay Date: Mon, 6 Nov 2023 12:02:35 +0100 Message-ID: <20231106110336.358-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=philmd@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Wether we use a software MMU or not to set the SSH timeout isn't really relevant. What we want to know is if we use a hardware or software accelerator (TCG). Replace the 'softmmu' mention by 'TCG'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20231002145104.52193-2-philmd@linaro.org> --- tests/vm/ubuntu.aarch64 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/vm/ubuntu.aarch64 b/tests/vm/ubuntu.aarch64 index 666947393b..eeda281f87 100755 --- a/tests/vm/ubuntu.aarch64 +++ b/tests/vm/ubuntu.aarch64 @@ -25,7 +25,7 @@ DEFAULT_CONFIG = { "apt-get install -y libfdt-dev pkg-config language-pack-en ninja-build", # We increase beyond the default time since during boot # it can take some time (many seconds) to log into the VM - # especially using softmmu. + # especially using TCG. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id k13-20020a5d6e8d000000b003196b1bb528sm9094731wrz.64.2023.11.06.03.04.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:04:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , =?utf-8?q?Daniel_P=2E_Ber?= =?utf-8?q?rang=C3=A9?= Subject: [PULL 04/60] tests/unit/test-seccomp: Remove mentions of softmmu in test names Date: Mon, 6 Nov 2023 12:02:36 +0100 Message-ID: <20231106110336.358-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Wether we are using a software MMU or not is irrelevant for the seccomp facility. The facility is restricted to system emulation, but such detail isn't really helpful, so directly drop the 'softmmu' mention from the test names. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231002145104.52193-3-philmd@linaro.org> --- tests/unit/test-seccomp.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/tests/unit/test-seccomp.c b/tests/unit/test-seccomp.c index f02c79cafd..bab93fd6da 100644 --- a/tests/unit/test-seccomp.c +++ b/tests/unit/test-seccomp.c @@ -229,26 +229,26 @@ int main(int argc, char **argv) g_test_init(&argc, &argv, NULL); if (can_play_with_seccomp()) { #ifdef SYS_fork - g_test_add_func("/softmmu/seccomp/sys-fork/on", + g_test_add_func("/seccomp/sys-fork/on", test_seccomp_sys_fork_on); - g_test_add_func("/softmmu/seccomp/sys-fork/on-nospawn", + g_test_add_func("/seccomp/sys-fork/on-nospawn", test_seccomp_sys_fork_on_nospawn); - g_test_add_func("/softmmu/seccomp/sys-fork/off", + g_test_add_func("/seccomp/sys-fork/off", test_seccomp_sys_fork_off); #endif - g_test_add_func("/softmmu/seccomp/fork/on", + g_test_add_func("/seccomp/fork/on", test_seccomp_fork_on); - g_test_add_func("/softmmu/seccomp/fork/on-nospawn", + g_test_add_func("/seccomp/fork/on-nospawn", test_seccomp_fork_on_nospawn); - g_test_add_func("/softmmu/seccomp/fork/off", + g_test_add_func("/seccomp/fork/off", test_seccomp_fork_off); - g_test_add_func("/softmmu/seccomp/thread/on", + g_test_add_func("/seccomp/thread/on", test_seccomp_thread_on); - g_test_add_func("/softmmu/seccomp/thread/on-nospawn", + g_test_add_func("/seccomp/thread/on-nospawn", test_seccomp_thread_on_nospawn); - g_test_add_func("/softmmu/seccomp/thread/off", + g_test_add_func("/seccomp/thread/off", test_seccomp_thread_off); if (doit_sched() == 0) { @@ -256,11 +256,11 @@ int main(int argc, char **argv) * musl doesn't impl sched_setscheduler, hence * we check above if it works first */ - g_test_add_func("/softmmu/seccomp/sched/on", + g_test_add_func("/seccomp/sched/on", test_seccomp_sched_on); - g_test_add_func("/softmmu/seccomp/sched/on-nores", + g_test_add_func("/seccomp/sched/on-nores", test_seccomp_sched_on_nores); - g_test_add_func("/softmmu/seccomp/sched/off", + g_test_add_func("/seccomp/sched/off", test_seccomp_sched_off); } } From patchwork Mon Nov 6 11:02:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741356 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1030208wrr; Mon, 6 Nov 2023 03:26:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IFC8oUJMMHGrcrCSoTIAE/gjc38OGurQfWo0yl4VafvVYQIUPlc0OcwS90xDwnJdwzOUZI7 X-Received: by 2002:a05:620a:2446:b0:76f:1614:577a with SMTP id h6-20020a05620a244600b0076f1614577amr13365085qkn.5.1699269969925; Mon, 06 Nov 2023 03:26:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269969; cv=none; d=google.com; s=arc-20160816; b=k8gULEYwGHErxu2MTKE/NchBtDqV8zFEzBsTTM1HvbOoW6J88AbDkcfxq4XhnpotJt tUgZbDaNoikBOUDV5IdIRlnDYbbBIl85Jju0BEX+QroxNr7I+f5TcE8tGpewPIMv7/4k PpGjrFD9orB1L66vUdO3aA4TrE06WfhiboxeGGPShG3L4SC2YTaAJpol9n0XRKCzBvLJ qdRhT+5wT/7x3/NG0GPRS81tcJylJha79yspm1/kwjpYrBwAE4OO2D2lZELv2G3Vjqx1 jkTzN5OrcMAh7jrEgnYIM+M2RHF3TDw01Fik+Q45UAlQIZsUzsvCGLTqZKNR9Cuz9+Mu tTQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=e2dhS3KlkYuIzlj4JyHbDi+Agmw3+gkCUCmK+83aHSA=; fh=HORlicMaqSt/rX9EVe6G+kP8BEdWajpTx2RDDSJwWhc=; b=PcBub5xkcwQBHNiXtTfqf46Jvif26BSG7L/p55xQq8X6Mn9wR0qko5A0hAeux/oNyc xjRvCUxBMUMm8k0BJQ44UNn8znAh3qGps6Q3EPUaSvBQmmPdPzcuSUE6jhmjYomLcInz zcCc4FQDfQfACTmbxmSKipp+AN9qwH7+Yyr8WNZQBD64w1Eu5qZEQgOmkeqtbyvBDzuq Ro9SY3Rtar4B5wjLxQg/ptxjssQ94vmmwelTpa50xRjqc8qk/mLWqUV0LMxfEqYcE6uG cGwIPSMFD6xVy6yT3nzO6ppgtL1jAfLj8zifYrgJhCtR+t7l3K8bdQ6z0CwSLO9oxp/q Wv7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="zM/lSLDJ"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id n26-20020a1c721a000000b0040849ce7116sm11652236wmc.43.2023.11.06.03.04.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:04:13 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Anton Johansson , Richard Henderson , Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Mahmoud Mandour Subject: [PULL 05/60] accel/tcg: Declare tcg_flush_jmp_cache() in 'exec/tb-flush.h' Date: Mon, 6 Nov 2023 12:02:37 +0100 Message-ID: <20231106110336.358-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "exec/cpu-common.h" is meant to contain the declarations related to CPU usable with any accelerator / target combination. tcg_flush_jmp_cache() is specific to TCG, so restrict its declaration by moving it to "exec/tb-flush.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Message-Id: <20230918104153.24433-2-philmd@linaro.org> --- include/exec/cpu-common.h | 1 - include/exec/tb-flush.h | 2 ++ accel/tcg/cputlb.c | 1 + accel/tcg/tcg-accel-ops.c | 1 + hw/core/cpu-common.c | 1 + plugins/core.c | 1 - 6 files changed, 5 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 30c376a4de..f700071d12 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -46,7 +46,6 @@ void cpu_list_unlock(void); unsigned int cpu_list_generation_id_get(void); void tcg_flush_softmmu_tlb(CPUState *cs); -void tcg_flush_jmp_cache(CPUState *cs); void tcg_iommu_init_notifier_list(CPUState *cpu); void tcg_iommu_free_notifier_list(CPUState *cpu); diff --git a/include/exec/tb-flush.h b/include/exec/tb-flush.h index d92d06565b..142c240d94 100644 --- a/include/exec/tb-flush.h +++ b/include/exec/tb-flush.h @@ -23,4 +23,6 @@ */ void tb_flush(CPUState *cs); +void tcg_flush_jmp_cache(CPUState *cs); + #endif /* _TB_FLUSH_H_ */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b8c5e345b8..6ea95ca03c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -24,6 +24,7 @@ #include "exec/memory.h" #include "exec/cpu_ldst.h" #include "exec/cputlb.h" +#include "exec/tb-flush.h" #include "exec/memory-internal.h" #include "exec/ram_addr.h" #include "tcg/tcg.h" diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index d885cc1d3c..7ddb05c332 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -34,6 +34,7 @@ #include "qemu/timer.h" #include "exec/exec-all.h" #include "exec/hwaddr.h" +#include "exec/tb-flush.h" #include "exec/gdbstub.h" #include "tcg-accel-ops.h" diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index bab8942c30..29c917c5dc 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -27,6 +27,7 @@ #include "qemu/main-loop.h" #include "exec/log.h" #include "exec/cpu-common.h" +#include "exec/tb-flush.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" #include "sysemu/tcg.h" diff --git a/plugins/core.c b/plugins/core.c index fcd33a2bff..49588285dd 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -21,7 +21,6 @@ #include "qemu/xxhash.h" #include "qemu/rcu.h" #include "hw/core/cpu.h" -#include "exec/cpu-common.h" #include "exec/exec-all.h" #include "exec/tb-flush.h" From patchwork Mon Nov 6 11:02:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741316 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1022614wrr; Mon, 6 Nov 2023 03:06:56 -0800 (PST) X-Google-Smtp-Source: AGHT+IHwFbxFt5OfVd4jooqpgamMmgn/OJ9Wvm3hHVEYaWG/OwdRw38crMELyBc4jbD1Q3TIuZft X-Received: by 2002:ac8:7e89:0:b0:41c:c588:b821 with SMTP id w9-20020ac87e89000000b0041cc588b821mr14261963qtj.25.1699268816192; Mon, 06 Nov 2023 03:06:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699268816; cv=none; d=google.com; s=arc-20160816; b=Gk2746kOZ2o/gKjhrvWxJQNOcaV7yDnQ9t/OGmskulO6wlAjxrm5JWAPGQ3rtiPNkf Tf+AzMTkQ4H54cxCqEoX/E1l+wU8/Dv2uX016oJeQ7eRk7fhcjcqWDDHlAmrBPI9cuBx taRpkcdM/HHXPpejna47hrawDd1tGhvM8kU39en7NeiDXxANbrNM1yFGUpXlUxtRvD0r A6dPOyJD+Z1ZTi08o2e8cx6fS2wV9ZtnKlTtRVPvSBK7vpfrA8LnZpqYcVruF03p9uMn qtN3YiikVAAf1ANMSgMCsbEJotPj8M1pBpca+n9AjD/K6OFfz8uKHPrctMyLeW0xyo4l m7KA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vBU4Pso0gSsGUJn6Y+tUxfBbchAwyEFBu11FifHIio4=; fh=OL+rgKfSk1cJBtILMSZyacaN6K7ZUVETDsu1eT6OjNI=; b=bO/e++M87IMYNTLtf9d8EX3lQEMu+TJUJhKOjDSZRy/8/kbgJ/99F2xItRwLDPuTlf AsbVA3cERRRA7TvMrbLmYP06XfMMzy0f6UDo69YMKU6LyYylgHnilLXPI220KOGO7Xh8 PKkgiIkzawHZXevJnnkMBASuvffPlTk5u4xz9BFU05gBC1VLoIVe3O0F7HD3BSKqZPTd vj65X3tHnINWCOTj4+LIhLa2rtS5O+Mo21ws4Uo3QZfAPwchvwFunJsrqHV78TergsfA QrOQO0ktT5bEXq5W0ZBFL9sRHibO+KXYf5OO+bJghV6icEZz1yAK/IwPZ2izUfpH3M32 ZctQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z8lKU3NJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id g20-20020a05600c4ed400b003fee8793911sm12010027wmq.44.2023.11.06.03.04.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:04:20 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Anton Johansson , Richard Henderson , Riku Voipio , Paolo Bonzini , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang Subject: [PULL 06/60] accel: Introduce cpu_exec_reset_hold() Date: Mon, 6 Nov 2023 12:02:38 +0100 Message-ID: <20231106110336.358-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Introduce cpu_exec_reset_hold() which call an accelerator specific AccelOpsClass::cpu_reset_hold() handler. Define a stub on TCG user emulation, because CPU reset is irrelevant there. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Message-Id: <20230918104153.24433-3-philmd@linaro.org> --- include/hw/core/cpu.h | 1 + include/sysemu/accel-ops.h | 1 + accel/tcg/user-exec-stub.c | 4 ++++ hw/core/cpu-common.c | 1 + system/cpus.c | 7 +++++++ 5 files changed, 14 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 18593db5b2..6373aa4501 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1153,6 +1153,7 @@ void cpu_class_init_props(DeviceClass *dc); void cpu_exec_initfn(CPUState *cpu); void cpu_exec_realizefn(CPUState *cpu, Error **errp); void cpu_exec_unrealizefn(CPUState *cpu); +void cpu_exec_reset_hold(CPUState *cpu); /** * target_words_bigendian: diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h index 3c1fab4b1e..ef91fc28bb 100644 --- a/include/sysemu/accel-ops.h +++ b/include/sysemu/accel-ops.h @@ -30,6 +30,7 @@ struct AccelOpsClass { void (*ops_init)(AccelOpsClass *ops); bool (*cpus_are_resettable)(void); + void (*cpu_reset_hold)(CPUState *cpu); void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY NON-NULL */ void (*kick_vcpu_thread)(CPUState *cpu); diff --git a/accel/tcg/user-exec-stub.c b/accel/tcg/user-exec-stub.c index 2dc6fd9c4e..4fbe2dbdc8 100644 --- a/accel/tcg/user-exec-stub.c +++ b/accel/tcg/user-exec-stub.c @@ -14,6 +14,10 @@ void qemu_init_vcpu(CPUState *cpu) { } +void cpu_exec_reset_hold(CPUState *cpu) +{ +} + /* User mode emulation does not support record/replay yet. */ bool replay_exception(void) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 29c917c5dc..7d266c36ac 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -137,6 +137,7 @@ static void cpu_common_reset_hold(Object *obj) cpu->crash_occurred = false; cpu->cflags_next_tb = -1; + cpu_exec_reset_hold(cpu); if (tcg_enabled()) { tcg_flush_jmp_cache(cpu); tcg_flush_softmmu_tlb(cpu); diff --git a/system/cpus.c b/system/cpus.c index 0848e0dbdb..952f15868c 100644 --- a/system/cpus.c +++ b/system/cpus.c @@ -201,6 +201,13 @@ bool cpus_are_resettable(void) return true; } +void cpu_exec_reset_hold(CPUState *cpu) +{ + if (cpus_accel->cpu_reset_hold) { + cpus_accel->cpu_reset_hold(cpu); + } +} + int64_t cpus_get_virtual_clock(void) { /* From patchwork Mon Nov 6 11:02:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741314 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1022440wrr; Mon, 6 Nov 2023 03:06:37 -0800 (PST) X-Google-Smtp-Source: AGHT+IENzUp9sBuX0P8KnMUM+orSlzaGtuZBlGKx5pleLd+DCWnL357EX4+0v83MLoz6NySJyuHD X-Received: by 2002:a67:ab04:0:b0:45f:1a97:e971 with SMTP id u4-20020a67ab04000000b0045f1a97e971mr2241883vse.20.1699268797268; Mon, 06 Nov 2023 03:06:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699268797; cv=none; d=google.com; s=arc-20160816; b=JRYXH9Mof+72hu/dsgEpDGEiygXnudPw9N53bbJ55R0XyNQcNRYYizWrY4cHNE8oSg ZxejsGpbUH9R54+pp859zPl0LxnV2+YTw+yBeW82mszq1BX9wdQw0cu71xXn/4XWh/+M JuLFSsGfVeWuyNN0xJlgje9ZjehUz7b9AyE/RpAS6zfD0Tczm+BQZO7ggQRz5qH+2rya FGMODllacMWOWancv0S/BaXQ6ih31o6BkNF8GT+wftSAD6yHSeTpDlxsoDjjL0pAbLy6 gjAggaRRD0AnVghoc9WJDaSXF3Wu1Ve3irhyorNctzSHj1tRFmFCUIxK1OqyhNZqpFW/ fmFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=599/Bj9mord/rWtxWCsNHAuRNbZVNvVu72yn9cQly6g=; fh=RyPJ+q8ZrjltNdlIdxCxAptKK4UXG24VhpBxSvmCLzU=; b=wkvIhTf4O99cLfusEj7t6nnjGXmUbB7sXaiI/+FwnkrRZKss0ZVtte2yH/0kaiv4mJ +hFc3qhfrP32jDkby48cM8mLa5d2uUykmlNyO3pDknGzOxxWsQcXSYwwVIEmvuuwLK2r Za1zgSAJepG/f4cVqs25B7IwCTIaLagy2+C7R6lpFAksPBxDGbQjnauCJQCjn1tD98lx BAggnvGkk2YWAfer1NPs2e8iQdpPpFDe8GrGM9oIE/8XHbgpQUSisRjrrK9mCih/sRwo k+4VczojgELT/iz+FCRTVYVmp6rmOUia0zgQCDxSDkn4bMbcOHUuOVzXnMqBaORW8/BE DK5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Yxgy1zQG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id s7-20020a05600c45c700b003fc16ee2864sm11816561wmo.48.2023.11.06.03.04.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:04:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Anton Johansson , Richard Henderson , Paolo Bonzini Subject: [PULL 07/60] accel/tcg: Factor tcg_cpu_reset_hold() out Date: Mon, 6 Nov 2023 12:02:39 +0100 Message-ID: <20231106110336.358-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Factor the TCG specific code from cpu_common_reset_hold() to tcg_cpu_reset_hold() within tcg-accel-ops.c. Since this file is sysemu specific, we can inline tcg_flush_softmmu_tlb(), removing its declaration in "exec/cpu-common.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Message-Id: <20230918104153.24433-4-philmd@linaro.org> --- include/exec/cpu-common.h | 2 -- accel/stubs/tcg-stub.c | 4 ---- accel/tcg/tcg-accel-ops.c | 8 ++++++++ accel/tcg/translate-all.c | 8 -------- hw/core/cpu-common.c | 5 ----- 5 files changed, 8 insertions(+), 19 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index f700071d12..41115d8919 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -45,8 +45,6 @@ void cpu_list_lock(void); void cpu_list_unlock(void); unsigned int cpu_list_generation_id_get(void); -void tcg_flush_softmmu_tlb(CPUState *cs); - void tcg_iommu_init_notifier_list(CPUState *cpu); void tcg_iommu_free_notifier_list(CPUState *cpu); diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index a9e7a2d5b4..8a496a2a6f 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -22,10 +22,6 @@ void tlb_set_dirty(CPUState *cpu, vaddr vaddr) { } -void tcg_flush_jmp_cache(CPUState *cpu) -{ -} - int probe_access_flags(CPUArchState *env, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr) diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 7ddb05c332..1b57290682 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -78,6 +78,13 @@ int tcg_cpus_exec(CPUState *cpu) return ret; } +static void tcg_cpu_reset_hold(CPUState *cpu) +{ + tcg_flush_jmp_cache(cpu); + + tlb_flush(cpu); +} + /* mask must never be zero, except for A20 change call */ void tcg_handle_interrupt(CPUState *cpu, int mask) { @@ -206,6 +213,7 @@ static void tcg_accel_ops_init(AccelOpsClass *ops) } } + ops->cpu_reset_hold = tcg_cpu_reset_hold; ops->supports_guest_debug = tcg_supports_guest_debug; ops->insert_breakpoint = tcg_insert_breakpoint; ops->remove_breakpoint = tcg_remove_breakpoint; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 8cb6ad3511..27e8152f0a 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -800,11 +800,3 @@ void tcg_flush_jmp_cache(CPUState *cpu) qatomic_set(&jc->array[i].tb, NULL); } } - -/* This is a wrapper for common code that can not use CONFIG_SOFTMMU */ -void tcg_flush_softmmu_tlb(CPUState *cs) -{ -#ifdef CONFIG_SOFTMMU - tlb_flush(cs); -#endif -} diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 7d266c36ac..baa6d28b64 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -27,7 +27,6 @@ #include "qemu/main-loop.h" #include "exec/log.h" #include "exec/cpu-common.h" -#include "exec/tb-flush.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" #include "sysemu/tcg.h" @@ -138,10 +137,6 @@ static void cpu_common_reset_hold(Object *obj) cpu->cflags_next_tb = -1; cpu_exec_reset_hold(cpu); - if (tcg_enabled()) { - tcg_flush_jmp_cache(cpu); - tcg_flush_softmmu_tlb(cpu); - } } static bool cpu_common_has_work(CPUState *cs) From patchwork Mon Nov 6 11:02:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741312 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1021686wrr; Mon, 6 Nov 2023 03:05:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IG/hTw6m64M6qks9Nth1LqEz4kYVfrStD489Wl8xYz20BCsz1696aWqNRdhuNqNhrrsdGAY X-Received: by 2002:a05:622a:41:b0:41c:e92a:c611 with SMTP id y1-20020a05622a004100b0041ce92ac611mr31887305qtw.38.1699268710300; Mon, 06 Nov 2023 03:05:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699268710; cv=none; d=google.com; s=arc-20160816; b=gjldLGBdd/sGyC8ntYtQB5ecB0kEWjVyAjsFgojqcbbJI51nt/n/BthTNmpapvZsud rEM3nFdq0GxB7eQzGZvJuThvDp0R8yJeGZgUA0sXZbQvaL92AWr/wlusl5Lg7AZyIzW5 p2OiZT66lZbWFW0d0f8smPVdWxYVNbMr5FdBWx8GP6lpqlHMtafJame75gBiKWbFTh3W xsyJMH+ZXEsHNvtbJAgYX7mhiy+HblUWqgQ36tUSUbBgr4EatKPodujzVC8d8GBzohES eazgurrOoqzWXYORqkZJiCtiR/Y7huvb9qsa5cq6vJHWQQ/sQ7BUpUsXoPeO1P6Vq1HN vtKA== ARC-Message-Signature: i=1; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id m9-20020adfe949000000b003253523d767sm120250wrn.109.2023.11.06.03.04.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:04:36 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Zhao Liu , Peter Maydell , Michael Rolnik , "Edgar E. Iglesias" , Brian Cain , Song Gao , Laurent Vivier , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Yoshinori Sato , Thomas Huth , David Hildenbrand , Ilya Leoshkevich , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov Subject: [PULL 08/60] target: Unify QOM style Date: Mon, 6 Nov 2023 12:02:40 +0100 Message-ID: <20231106110336.358-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Enforce the style described by commit 067109a11c ("docs/devel: mention the spacing requirement for QOM"): The first declaration of a storage or class structure should always be the parent and leave a visual space between that declaration and the new code. It is also useful to separate backing for properties (options driven by the user) and internal state to make navigation easier. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu Message-Id: <20231013140116.255-2-philmd@linaro.org> --- target/alpha/cpu-qom.h | 2 -- target/alpha/cpu.h | 2 -- target/arm/cpu-qom.h | 4 ---- target/arm/cpu.h | 2 -- target/avr/cpu-qom.h | 3 +-- target/avr/cpu.h | 2 -- target/cris/cpu-qom.h | 2 -- target/cris/cpu.h | 2 -- target/hexagon/cpu.h | 5 +---- target/hppa/cpu-qom.h | 2 -- target/hppa/cpu.h | 2 -- target/i386/cpu-qom.h | 2 -- target/i386/cpu.h | 2 -- target/loongarch/cpu.h | 4 ---- target/m68k/cpu-qom.h | 2 -- target/m68k/cpu.h | 2 -- target/microblaze/cpu-qom.h | 2 -- target/microblaze/cpu.h | 2 -- target/mips/cpu-qom.h | 2 -- target/mips/cpu.h | 2 -- target/nios2/cpu.h | 4 ---- target/openrisc/cpu.h | 4 ---- target/ppc/cpu.h | 2 -- target/riscv/cpu-qom.h | 3 +-- target/riscv/cpu.h | 2 -- target/rx/cpu-qom.h | 2 -- target/rx/cpu.h | 2 -- target/s390x/cpu-qom.h | 3 +-- target/s390x/cpu.h | 2 -- target/sh4/cpu-qom.h | 2 -- target/sh4/cpu.h | 2 -- target/sparc/cpu-qom.h | 2 -- target/sparc/cpu.h | 2 -- target/tricore/cpu-qom.h | 2 -- target/tricore/cpu.h | 2 -- target/xtensa/cpu-qom.h | 2 -- target/xtensa/cpu.h | 2 -- 37 files changed, 4 insertions(+), 84 deletions(-) diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h index 1f200724b6..c5fbd8f11a 100644 --- a/target/alpha/cpu-qom.h +++ b/target/alpha/cpu-qom.h @@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU) * An Alpha CPU model. */ struct AlphaCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; DeviceReset parent_reset; diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index e2a467ec17..c8d97ac27a 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -259,9 +259,7 @@ typedef struct CPUArchState { * An Alpha CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUAlphaState env; diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index d06c08a734..153865d1bb 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -46,9 +46,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info); * An ARM CPU model. */ struct ARMCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ const ARMCPUInfo *info; DeviceRealize parent_realize; @@ -62,9 +60,7 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, TYPE_AARCH64_CPU) struct AArch64CPUClass { - /*< private >*/ ARMCPUClass parent_class; - /*< public >*/ }; void register_cp_regs_for_features(ARMCPU *cpu); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d51dfe48db..2f7ab22169 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -852,9 +852,7 @@ typedef struct { * An ARM CPU core. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUARMState env; diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h index 01ea5f160b..d89be01e0f 100644 --- a/target/avr/cpu-qom.h +++ b/target/avr/cpu-qom.h @@ -36,9 +36,8 @@ OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU) * A AVR CPU model. */ struct AVRCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ + DeviceRealize parent_realize; ResettablePhases parent_phases; }; diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 4ce22d8e4f..f8b065ed79 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -144,9 +144,7 @@ typedef struct CPUArchState { * A AVR CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUAVRState env; }; diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h index 431a1d536a..c2fee242f4 100644 --- a/target/cris/cpu-qom.h +++ b/target/cris/cpu-qom.h @@ -36,9 +36,7 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU) * A CRIS CPU model. */ struct CRISCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 676b8e93ca..6aa445348f 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -174,9 +174,7 @@ typedef struct CPUArchState { * A CRIS CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUCRISState env; }; diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 10cd1efd57..035ac4fb6d 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -130,17 +130,14 @@ typedef struct CPUArchState { OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) typedef struct HexagonCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ + DeviceRealize parent_realize; ResettablePhases parent_phases; } HexagonCPUClass; struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUHexagonState env; diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h index b96e0318c7..67f12422c4 100644 --- a/target/hppa/cpu-qom.h +++ b/target/hppa/cpu-qom.h @@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU) * An HPPA CPU model. */ struct HPPACPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; DeviceReset parent_reset; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 798d0c26d7..518ea94f4f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -233,9 +233,7 @@ typedef struct CPUArchState { * An HPPA CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUHPPAState env; QEMUTimer *alarm_timer; diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h index 2350f4ae60..58145717ef 100644 --- a/target/i386/cpu-qom.h +++ b/target/i386/cpu-qom.h @@ -47,9 +47,7 @@ typedef struct X86CPUModel X86CPUModel; * An x86 CPU model or family. */ struct X86CPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ /* CPU definition, automatically loaded by instance_init if not NULL. * Should be eventually replaced by subclass-specific property defaults. diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 471e71dbc5..096f85483e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1897,9 +1897,7 @@ struct kvm_msrs; * An x86 CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUX86State env; VMChangeStateEntry *vmsentry; diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 8b54cf109c..8f0e9f0182 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -371,9 +371,7 @@ typedef struct CPUArchState { * A LoongArch CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPULoongArchState env; QEMUTimer timer; @@ -398,9 +396,7 @@ OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass, * A LoongArch CPU model. */ struct LoongArchCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h index 0ec7750a92..13d94c9fe3 100644 --- a/target/m68k/cpu-qom.h +++ b/target/m68k/cpu-qom.h @@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU) * A Motorola 68k CPU model. */ struct M68kCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 20afb0c94d..9ea18028ad 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -164,9 +164,7 @@ typedef struct CPUArchState { * A Motorola 68k CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUM68KState env; }; diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h index cda9220fa9..2a734e644d 100644 --- a/target/microblaze/cpu-qom.h +++ b/target/microblaze/cpu-qom.h @@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU) * A MicroBlaze CPU model. */ struct MicroBlazeCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e43c49d4af..e8000237d8 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -343,9 +343,7 @@ typedef struct { * A MicroBlaze CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUMBState env; diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index 0dffab453b..c70b4a34be 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -39,9 +39,7 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU) * A MIPS CPU model. */ struct MIPSCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 5fddceff3a..617c373797 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1209,9 +1209,7 @@ typedef struct CPUArchState { * A MIPS CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUMIPSState env; diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 70b6377a4f..ede1ba2140 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -42,9 +42,7 @@ OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU) * A Nios2 CPU model. */ struct Nios2CPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; @@ -214,9 +212,7 @@ typedef struct { * A Nios2 CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUNios2State env; diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 334997e9a1..29cda7279c 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -39,9 +39,7 @@ OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU) * A OpenRISC CPU model. */ struct OpenRISCCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; @@ -301,9 +299,7 @@ typedef struct CPUArchState { * A OpenRISC CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUOpenRISCState env; }; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 30392ebeee..24dd6b1b0a 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1313,9 +1313,7 @@ typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass; * A PowerPC CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUPPCState env; diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index f3fbe37a2c..b9164a8e5b 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -63,9 +63,8 @@ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) * A RISCV CPU model. */ struct RISCVCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ + DeviceRealize parent_realize; ResettablePhases parent_phases; }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f8ffa5ee38..f0dc257a75 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -389,9 +389,7 @@ struct CPUArchState { * A RISCV CPU. */ struct ArchCPU { - /* < private > */ CPUState parent_obj; - /* < public > */ CPURISCVState env; diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h index 1c8466a187..f4cd5664e5 100644 --- a/target/rx/cpu-qom.h +++ b/target/rx/cpu-qom.h @@ -36,9 +36,7 @@ OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU) * A RX CPU model. */ struct RXCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/rx/cpu.h b/target/rx/cpu.h index f66754eb8a..8379f4a150 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -107,9 +107,7 @@ typedef struct CPUArchState { * A RX CPU */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPURXState env; }; diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h index 00cae2b131..1088965fd5 100644 --- a/target/s390x/cpu-qom.h +++ b/target/s390x/cpu-qom.h @@ -49,9 +49,8 @@ typedef enum cpu_reset_type { * An S/390 CPU model. */ struct S390CPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ + const S390CPUDef *cpu_def; bool kvm_required; bool is_static; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 40c5cedd0e..4f366f9e4e 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -172,9 +172,7 @@ static inline uint64_t *get_freg(CPUS390XState *cs, int nr) * An S/390 CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUS390XState env; S390CPUModel *model; diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h index 89785a90f0..08fbebc996 100644 --- a/target/sh4/cpu-qom.h +++ b/target/sh4/cpu-qom.h @@ -42,9 +42,7 @@ OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU) * A SuperH CPU model. */ struct SuperHCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index f75a235973..dc0561b73b 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -204,9 +204,7 @@ typedef struct CPUArchState { * A SuperH CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUSH4State env; }; diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h index 78bf00b9a2..b4a0db84ce 100644 --- a/target/sparc/cpu-qom.h +++ b/target/sparc/cpu-qom.h @@ -40,9 +40,7 @@ typedef struct sparc_def_t sparc_def_t; * A SPARC CPU model. */ struct SPARCCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 758a4e8aaa..84a030e406 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -569,9 +569,7 @@ struct CPUArchState { * A SPARC CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUSPARCState env; }; diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h index 612731daa0..b3b6c75a3a 100644 --- a/target/tricore/cpu-qom.h +++ b/target/tricore/cpu-qom.h @@ -27,9 +27,7 @@ OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU) struct TriCoreCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index a357b573f2..b4a6ab141d 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -63,9 +63,7 @@ typedef struct CPUArchState { * A TriCore CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUTriCoreState env; }; diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h index 419c7d8e4a..424bcbd8dd 100644 --- a/target/xtensa/cpu-qom.h +++ b/target/xtensa/cpu-qom.h @@ -47,9 +47,7 @@ typedef struct XtensaConfig XtensaConfig; * An Xtensa CPU model. */ struct XtensaCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index c6bbef1e5d..85aab1bdf8 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -556,9 +556,7 @@ struct CPUArchState { * An Xtensa CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUXtensaState env; Clock *clock; From patchwork Mon Nov 6 11:02:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741313 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1021835wrr; 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Iglesias" Subject: [PULL 09/60] target: Mention 'cpu-qom.h' is target agnostic Date: Mon, 6 Nov 2023 12:02:41 +0100 Message-ID: <20231106110336.358-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu-qom.h" is supposed to be target agnostic (include-able by any target). Add such mention in the header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-3-philmd@linaro.org> --- target/arm/cpu-qom.h | 2 +- target/hppa/cpu-qom.h | 2 +- target/microblaze/cpu-qom.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 153865d1bb..dfb9d5b827 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU ARM CPU + * QEMU ARM CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h index 67f12422c4..4b1d48f7ca 100644 --- a/target/hppa/cpu-qom.h +++ b/target/hppa/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU HPPA CPU + * QEMU HPPA CPU QOM header (target agnostic) * * Copyright (c) 2016 Richard Henderson * diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h index 2a734e644d..78f549b57d 100644 --- a/target/microblaze/cpu-qom.h +++ b/target/microblaze/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU MicroBlaze CPU + * QEMU MicroBlaze CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * From patchwork Mon Nov 6 11:02:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741317 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1022840wrr; Mon, 6 Nov 2023 03:07:21 -0800 (PST) X-Google-Smtp-Source: AGHT+IFe2TqJNR2kH2FlgZpNJDECtYzDKyMGiEnldLZK1SZK/o82YcsQs9G0POeLicHF7f0aeMjr X-Received: by 2002:a25:2f8e:0:b0:da0:47d8:4659 with SMTP id v136-20020a252f8e000000b00da047d84659mr23631183ybv.52.1699268841465; Mon, 06 Nov 2023 03:07:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699268841; cv=none; d=google.com; s=arc-20160816; b=fziWhLLtHnqWojY0IWfBide553ZYlyK5w6fX6FmtEMRQU0gJd0mFuRGl+JALfO2s0R /6QfCMncrNPpD5P4Zakz36q4/5tT/LXfZZqraEGDRrrp4PV9QE1TMfBYlTVrb/mmBNfC g47/s6FhfIVWzzP3vdUuw9iimJdnofAG/r6FG4xdSE1VhI4aYo6tWvdQ5ccMAjiA0Bqe U87mD0Kpfc8ZUaV/be4BV9qfIADJLTyxvc7tGI4NTkb7Bxoc4x+dvzFgTBQfp/C8D46O UHiEf7Wkdksx8Rh1SPFJ9Q+C6ky0ppLQyf3VoqucQHnou6EJ8mTG035e0Bi9jkJlVwUq E2Dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5wOkrsA8z2Hole9awlJYsNuk4oh7gPmhIjtphAMJsw8=; fh=VKl5gk7jxaHt8Tg4zmPPFZx0DaBatpg0SVP+SHjL4SM=; b=cfPRCkSgWQwqlhKw5+EjE8jEAm5Z740KPPsrz94FmkCzXwKLgxo2qo86DyU+XNFJXY ZF3+Yt0HhRxx32cVd8nXZ05l4ffiM97nIVUF+5GxBn/aG27XO7+zLOggp50BtcMefGtV YhCrkBsop7WdwI4DmTPFnaHZCwQuPCUrY3dpKmqHr610NGnAHu3JmbCXEEH2rpUTkB5P sINDXD6onyGShUlNU1q05HraHxoMJQll/CUKmSwnOWmPKGjpDIchrAY5u+aTEE1YZwvF Z2DO2xxRNRw18df7m7PsvobQcdc6NqQgKkmCM45vNkKhlXPyWvj4ndKv58sHEtIHAoma dRhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=psKUUSqM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id z2-20020a5d6402000000b0032d9caeab0fsm9209526wru.77.2023.11.06.03.04.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:04:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Peter Maydell Subject: [PULL 10/60] target/arm: Move internal declarations from 'cpu-qom.h' to 'cpu.h' Date: Mon, 6 Nov 2023 12:02:42 +0100 Message-ID: <20231106110336.358-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org These definitions and declarations are only used by target/arm/, no need to expose them to generic hw/. Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-4-philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé Message-Id: --- target/arm/cpu-qom.h | 28 ---------------------------- target/arm/cpu.h | 22 ++++++++++++++++++++++ target/arm/internals.h | 6 ++++++ 3 files changed, 28 insertions(+), 28 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index dfb9d5b827..35c3b0924e 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -35,9 +35,6 @@ typedef struct ARMCPUInfo { void (*class_init)(ObjectClass *oc, void *data); } ARMCPUInfo; -void arm_cpu_register(const ARMCPUInfo *info); -void aarch64_cpu_register(const ARMCPUInfo *info); - /** * ARMCPUClass: * @parent_realize: The parent class' realize handler. @@ -63,29 +60,4 @@ struct AArch64CPUClass { ARMCPUClass parent_class; }; -void register_cp_regs_for_features(ARMCPU *cpu); -void init_cpreg_list(ARMCPU *cpu); - -/* Callback functions for the generic timer's timers. */ -void arm_gt_ptimer_cb(void *opaque); -void arm_gt_vtimer_cb(void *opaque); -void arm_gt_htimer_cb(void *opaque); -void arm_gt_stimer_cb(void *opaque); -void arm_gt_hvtimer_cb(void *opaque); - -#define ARM_AFF0_SHIFT 0 -#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) -#define ARM_AFF1_SHIFT 8 -#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) -#define ARM_AFF2_SHIFT 16 -#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) -#define ARM_AFF3_SHIFT 32 -#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) -#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 - -#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) -#define ARM64_AFFINITY_MASK \ - (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) -#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) - #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2f7ab22169..4a86c8f831 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1116,11 +1116,33 @@ struct ArchCPU { uint64_t gt_cntfrq_hz; }; +/* Callback functions for the generic timer's timers. */ +void arm_gt_ptimer_cb(void *opaque); +void arm_gt_vtimer_cb(void *opaque); +void arm_gt_htimer_cb(void *opaque); +void arm_gt_stimer_cb(void *opaque); +void arm_gt_hvtimer_cb(void *opaque); + unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); void arm_cpu_post_init(Object *obj); +#define ARM_AFF0_SHIFT 0 +#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) +#define ARM_AFF1_SHIFT 8 +#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) +#define ARM_AFF2_SHIFT 16 +#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) +#define ARM_AFF3_SHIFT 32 +#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) +#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 + +#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK) +#define ARM64_AFFINITY_MASK \ + (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) +#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) + uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); #ifndef CONFIG_USER_ONLY diff --git a/target/arm/internals.h b/target/arm/internals.h index c837506e44..143d57c0fe 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -183,6 +183,12 @@ static inline int r14_bank_number(int mode) return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode); } +void arm_cpu_register(const ARMCPUInfo *info); +void aarch64_cpu_register(const ARMCPUInfo *info); + +void register_cp_regs_for_features(ARMCPU *cpu); +void init_cpreg_list(ARMCPU *cpu); + void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); From patchwork Mon Nov 6 11:02:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741355 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1029570wrr; Mon, 6 Nov 2023 03:24:27 -0800 (PST) X-Google-Smtp-Source: AGHT+IGUSeofjPljxzT43eTYZb73Dc5vqYYq20i8T7efTG03UeE5x1kdwP0pJklP5f+Zn/xfiM1E X-Received: by 2002:a05:620a:640a:b0:778:9148:3c2c with SMTP id pz10-20020a05620a640a00b0077891483c2cmr28240396qkn.18.1699269867669; Mon, 06 Nov 2023 03:24:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269867; cv=none; d=google.com; s=arc-20160816; b=cZuAgGbl1jzApbONAS4eIjQpr3l8OPNjDULs4E+8/LJOQgDhAzwbCUZwjHgza32/Lr kckWy9+9P4k1pkfeH/8cPUPsMtS6MA6UGP9lm9ALJODHHOJpaFujX+UN79DNN/+DGw47 nYxm373wrQ61ySRhEB3nX95AvF/NUwUo9MF/UZgzfaVq8oow9qZZYje2GS2OmcWCahrp e9+nQzR5KHNS4xQP0qC1yTMhSGlu88+gO4VMzXkOy7JsaW0T/Ca7vuiph6drK8rFdUT3 QSdW481LHX2Bom6BkNv3Ncay0nRltJ2kxkuJ8gEGzAxBvgsJQCPoDii0km3ax7mN7zvP OA2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vePePWiaVFUAUv821iwYutEeShxemZReiuwQp7UFnAo=; fh=EAnNOTx5rrq8DPtFwGHdbtsF7iNCWNgVaP9w8twwXg0=; b=H55Lyx1qtgTUg1dbTM1xSaOge8DZ3VAj/gLZXPMg6RlMwORXPT0Ny0w3lYBlA6XGXv DMynms73Si+9HBpieMBtvAsYPsThQITQeFh9h9olgyCqsYFPe+I4VTZbXrCOBdHA2S+Y Xn24JqSd/Kyx1GI0cteoGmdPt/qI5y9LhslUvLBurQvJqX2ykU3D/NndeAtvfRagQrhH yRxFRunGFXxO+UbipV+aeTLu+ELC2+lDQPsPQLEK4mZEYBVyyVYj8zDe9UigNu3ZvnA7 aDoI46KF+uS8qPzkj5UWjpXGl8ifP6qpht4SHOFQjB4FqfPIACOxHaqnGGKDw/RdWJS3 lIXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="dRSL/hYu"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id p12-20020adfce0c000000b0032dc1fc84f2sm9191301wrn.46.2023.11.06.03.04.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:04:55 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Nicholas Piggin , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= Subject: [PULL 11/60] target/ppc: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h' Date: Mon, 6 Nov 2023 12:02:43 +0100 Message-ID: <20231106110336.358-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=philmd@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CPU_RESOLVING_TYPE is a per-target definition, and is irrelevant for other targets. Move it to "cpu.h". "target/ppc/cpu-qom.h" is supposed to be target agnostic (include-able by any target). Add such mention in the header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-5-philmd@linaro.org> --- target/ppc/cpu-qom.h | 3 +-- target/ppc/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index be33786bd8..41df51269b 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU PowerPC CPU + * QEMU PowerPC CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -33,7 +33,6 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU) #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX -#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU #define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host") diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 24dd6b1b0a..02619e5d54 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -27,6 +27,8 @@ #include "qom/object.h" #include "hw/registerfields.h" +#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU + #define TCG_GUEST_DEFAULT_MO 0 #define TARGET_PAGE_BITS_64K 16 From patchwork Mon Nov 6 11:02:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741362 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1032732wrr; Mon, 6 Nov 2023 03:32:45 -0800 (PST) X-Google-Smtp-Source: AGHT+IE1edCOk91NfL5lxXSzebqhJke44jDCSyurvV/lqbkGFgeOLLyesDqk1BF8jdzMAByeXTlJ X-Received: by 2002:a05:6214:20e3:b0:672:97ab:5670 with SMTP id 3-20020a05621420e300b0067297ab5670mr26439668qvk.56.1699270365625; Mon, 06 Nov 2023 03:32:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699270365; cv=none; d=google.com; s=arc-20160816; b=l3LqSbfcNsKAJYSY2tysSAixtaUAzkeEV7gefGqQqQHp5JizeD1u0RvAXhrEQLB6/d rdYl2vRiDmXJJlTO1Qq5L4VML1QVdAMwkogusnvow5sVgmVm5cxdNiv+H3xN5NMH8HGK KAgquS4TrQ27iONidGzlJsQwi/H65DfLFkkbJCYrnR7s/znatfSLHh4Tu1lqWwVxhMor DeDNdVHX6Md+qbv5w3cgwvD1M/1GngdjUC3Lz78UB4pcev9KAw/JdFSkYm/nrF1Mwzpo ygQ/rdQI/dazrRBMjS3Zl4tn3wMjOmotbm4IneGANr2FGn6YgmSvCOeOBEf9bavIIHcS jcSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RkZROkW3VJc36/l321YGkxp/mj9LkNXWejNsMfklYm4=; fh=UXczy+6vs2grPC0yFqJi3U97mL5Jb1ilDMzRjA+62t0=; b=p2n3D5/zAifjRJ9ranndM96l1XlnYxcq0N8mvS8TBKU6osjop734cBGwp19w+P6LYc s4y/IYcZZtaSJZmHCpFp68ffM76QoSYDNR1g8VOyVNDgX0lstBrtv2nZ2yki86l09mpm AjVH0w0+87knKjjNNM1ozAOVLNNuMMyzXyGtyu3qyBxP5W7QKeexTFqsa2No+N+/4yW9 +wTffzdVnwatL+mTxGxbAdfZ8+Ag2ZMyApSF6B9jpyKijpDZ0s+aDcM82YaRXyaWjVEn ZjLN9EbhnbKvvM9T20lncYgB5hZOXMsWRYIDGvK25SVvfz2qP+CqirG9BrXwNO9a9gzp kNqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M0jyDKDu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id k9-20020a056000004900b0032dbf26e7aesm8956250wrx.65.2023.11.06.03.05.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:02 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , LIU Zhiwei , Richard Henderson , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 12/60] target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h' Date: Mon, 6 Nov 2023 12:02:44 +0100 Message-ID: <20231106110336.358-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CPU_RESOLVING_TYPE is a per-target definition, and is irrelevant for other targets. Move it to "cpu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-6-philmd@linaro.org> --- target/riscv/cpu-qom.h | 1 - target/riscv/cpu.h | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index b9164a8e5b..b78169093f 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -27,7 +27,6 @@ #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) -#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") #define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max") diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f0dc257a75..144cc94cce 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -32,6 +32,8 @@ #include "qapi/qapi-types-common.h" #include "cpu-qom.h" +#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU + #define TCG_GUEST_DEFAULT_MO 0 /* From patchwork Mon Nov 6 11:02:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741322 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1023748wrr; Mon, 6 Nov 2023 03:09:26 -0800 (PST) X-Google-Smtp-Source: AGHT+IHHhw/srb0JrSTqoGJSveATZI4uOta8gIiqQu/W77JpRoi8tZ7iHZSKB2hRu082fB5ZqXKr X-Received: by 2002:ac8:5c0e:0:b0:410:842d:fc2f with SMTP id i14-20020ac85c0e000000b00410842dfc2fmr12798114qti.7.1699268966230; Mon, 06 Nov 2023 03:09:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699268966; cv=none; d=google.com; s=arc-20160816; b=owsuQK6q1h8qoQHcDDV4YlWXwPEzbpQta6ymfxo7AJgcu/kus3hPYxIygIEKObbLHN mTGn3cvVtvsyNYdhi8EaK+/6If0ICFmhIf9rQ1GoG9KUcbEd12+gyLLv7pCTIgFF/WS5 2AXFPjicdjpyZQzkPEMPHlPSrQWmoUX3ACTaOpgbG3gklnoNqGqQXImWmQotY0b5isE8 Ja4/RbYPozxMxew0jGZ/kUWjLecfAPhHGklqr2E9Nv2rQTQJdqAnSpWDhaB/Scp2DbjS dP/uoj7Cw5rPx3Q9CbmV+ZZ9jXESABTTxqdDUH6SBVLaPJDTZ9LMETD0kAq1dFoRsehw TqjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WxUmiCwPV5zJl3mXwLh1MUI3WD6xJyg5vO6bbT+CodM=; fh=I5vBD8P0nr8uM7ETIrFEUTJzMplqF/xlhegva2Mj09w=; b=dc6kkIPbU8WVHfCSqFS4CSf8OhDn+9Snf/CgOjFAN1Mh7U2VDDiQiHZuVuXxo3wwvd z0Lx5WWZ27H7fui6u6qNyjmrRB6W2LAyOp8i3PpjJdadrmPx0xZIoB8fxK+jZ9NZuL2V A5PJJsy19GR9ay9UOsH5ddgyFME0+LtnKwPiXfZKGNiXFz5be3qZs6UMZFtxRuSeoFbP 7s7341Q+QXFctp/wdh0VqzGAlRB0I9ytcvFBHw+KhpkFC6sp3TdVD9YqhcRNOESThXU/ PHz9ah2NjpDU4L1Rwel/0TL6Xh12gfkgpUIEByZxets2T+BNnm9H4I5L7cHkVkx8gYI9 fiRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kq0nTazu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id a11-20020a05600c2d4b00b00405c33a9a12sm6133016wmg.0.2023.11.06.03.05.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:10 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , LIU Zhiwei , Richard Henderson , Michael Rolnik , "Edgar E. Iglesias" , Laurent Vivier , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov Subject: [PULL 13/60] target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h' Date: Mon, 6 Nov 2023 12:02:45 +0100 Message-ID: <20231106110336.358-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=philmd@linaro.org; helo=mail-lj1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Hegerogeneous code needs access to the FOO_CPU_TYPE_NAME() macro to resolve target CPU types. Move the declaration (along with the required FOO_CPU_TYPE_SUFFIX) to "cpu-qom.h". "target/foo/cpu-qom.h" is supposed to be target agnostic (include-able by any target). Add such mention in the header. Signed-off-by: Philippe Mathieu-Daudé Acked-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-7-philmd@linaro.org> --- target/alpha/cpu-qom.h | 5 ++++- target/alpha/cpu.h | 2 -- target/avr/cpu-qom.h | 5 ++++- target/avr/cpu.h | 2 -- target/cris/cpu-qom.h | 5 ++++- target/cris/cpu.h | 2 -- target/i386/cpu-qom.h | 3 +++ target/i386/cpu.h | 2 -- target/m68k/cpu-qom.h | 5 ++++- target/m68k/cpu.h | 2 -- target/mips/cpu-qom.h | 3 +++ target/mips/cpu.h | 2 -- target/rx/cpu-qom.h | 5 ++++- target/rx/cpu.h | 2 -- target/s390x/cpu-qom.h | 5 ++++- target/s390x/cpu.h | 2 -- target/sh4/cpu-qom.h | 5 ++++- target/sh4/cpu.h | 2 -- target/sparc/cpu-qom.h | 5 ++++- target/sparc/cpu.h | 2 -- target/tricore/cpu-qom.h | 5 +++++ target/tricore/cpu.h | 2 -- target/xtensa/cpu-qom.h | 5 ++++- target/xtensa/cpu.h | 2 -- 24 files changed, 47 insertions(+), 33 deletions(-) diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h index c5fbd8f11a..c4a4523993 100644 --- a/target/alpha/cpu-qom.h +++ b/target/alpha/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU Alpha CPU + * QEMU Alpha CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -27,6 +27,9 @@ OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU) +#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU +#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX + /** * AlphaCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index c8d97ac27a..3bff56c565 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -426,8 +426,6 @@ enum { void alpha_translate_init(void); -#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU -#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU void alpha_cpu_list(void); diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h index d89be01e0f..75590cdd97 100644 --- a/target/avr/cpu-qom.h +++ b/target/avr/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU AVR CPU + * QEMU AVR CPU QOM header (target agnostic) * * Copyright (c) 2016-2020 Michael Rolnik * @@ -28,6 +28,9 @@ OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU) +#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU +#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX) + /** * AVRCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/avr/cpu.h b/target/avr/cpu.h index f8b065ed79..0487399cb2 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -28,8 +28,6 @@ #error "AVR 8-bit does not support user mode" #endif -#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU -#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_AVR_CPU #define TCG_GUEST_DEFAULT_MO 0 diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h index c2fee242f4..d7e5f33e62 100644 --- a/target/cris/cpu-qom.h +++ b/target/cris/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU CRIS CPU + * QEMU CRIS CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -27,6 +27,9 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU) +#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU +#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) + /** * CRISCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 6aa445348f..b821bb7983 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -240,8 +240,6 @@ enum { /* CRIS uses 8k pages. */ #define MMAP_SHIFT TARGET_PAGE_BITS -#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU -#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU /* MMU modes definitions */ diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h index 58145717ef..dffc74c1ce 100644 --- a/target/i386/cpu-qom.h +++ b/target/i386/cpu-qom.h @@ -32,6 +32,9 @@ OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU) +#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU +#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) + typedef struct X86CPUModel X86CPUModel; /** diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 096f85483e..6c6b066986 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2239,8 +2239,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); /* hw/pc.c */ uint64_t cpu_get_tsc(CPUX86State *env); -#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU -#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_X86_CPU #ifdef TARGET_X86_64 diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h index 13d94c9fe3..df0cc8b7a3 100644 --- a/target/m68k/cpu-qom.h +++ b/target/m68k/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU Motorola 68k CPU + * QEMU Motorola 68k CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -27,6 +27,9 @@ OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU) +#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU +#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX + /* * M68kCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 9ea18028ad..7f34686a6f 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -561,8 +561,6 @@ enum { ACCESS_DATA = 0x20, /* Data load/store access */ }; -#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU -#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_M68K_CPU #define cpu_list m68k_cpu_list diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index c70b4a34be..5822dfb1d2 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -31,6 +31,9 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU) +#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU +#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX + /** * MIPSCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 617c373797..12cc1bfafd 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1301,8 +1301,6 @@ enum { */ #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 -#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU -#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU bool cpu_type_supports_cps_smp(const char *cpu_type); diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h index f4cd5664e5..6213d877f7 100644 --- a/target/rx/cpu-qom.h +++ b/target/rx/cpu-qom.h @@ -1,5 +1,5 @@ /* - * RX CPU + * QEMU RX CPU QOM header (target agnostic) * * Copyright (c) 2019 Yoshinori Sato * @@ -28,6 +28,9 @@ OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU) +#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU +#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX + /* * RXCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 8379f4a150..c81613770c 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -112,8 +112,6 @@ struct ArchCPU { CPURXState env; }; -#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU -#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_RX_CPU const char *rx_crname(uint8_t cr); diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h index 1088965fd5..fcd70daddf 100644 --- a/target/s390x/cpu-qom.h +++ b/target/s390x/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU S/390 CPU + * QEMU S/390 CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -27,6 +27,9 @@ OBJECT_DECLARE_CPU_TYPE(S390CPU, S390CPUClass, S390_CPU) +#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU +#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) + typedef struct S390CPUModel S390CPUModel; typedef struct S390CPUDef S390CPUDef; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 4f366f9e4e..38d7197f4c 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -890,8 +890,6 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, /* helper.c */ -#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU -#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_S390_CPU /* interrupt.c */ diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h index 08fbebc996..bd0ef49fa1 100644 --- a/target/sh4/cpu-qom.h +++ b/target/sh4/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU SuperH CPU + * QEMU SuperH CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -31,6 +31,9 @@ OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU) +#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU +#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX + /** * SuperHCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index dc0561b73b..dbe00e29c2 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -250,8 +250,6 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr); void cpu_load_tlb(CPUSH4State * env); -#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU -#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU #define cpu_list sh4_cpu_list diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h index b4a0db84ce..aca29415b4 100644 --- a/target/sparc/cpu-qom.h +++ b/target/sparc/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU SPARC CPU + * QEMU SPARC CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -31,6 +31,9 @@ OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU) +#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU +#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX + typedef struct sparc_def_t sparc_def_t; /** * SPARCCPUClass: diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 84a030e406..8c567037cb 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -660,8 +660,6 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, #endif #endif -#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU -#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU #define cpu_list sparc_cpu_list diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h index b3b6c75a3a..2598651008 100644 --- a/target/tricore/cpu-qom.h +++ b/target/tricore/cpu-qom.h @@ -1,4 +1,6 @@ /* + * QEMU TriCore CPU QOM header (target agnostic) + * * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn * * This library is free software; you can redistribute it and/or @@ -26,6 +28,9 @@ OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU) +#define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU +#define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX + struct TriCoreCPUClass { CPUClass parent_class; diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index b4a6ab141d..c537a33ee8 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -268,8 +268,6 @@ static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, *flags = new_flags; } -#define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU -#define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU /* helpers.c */ diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h index 424bcbd8dd..03873ea50b 100644 --- a/target/xtensa/cpu-qom.h +++ b/target/xtensa/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU Xtensa CPU + * QEMU Xtensa CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * All rights reserved. @@ -36,6 +36,9 @@ OBJECT_DECLARE_CPU_TYPE(XtensaCPU, XtensaCPUClass, XTENSA_CPU) +#define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU +#define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX + typedef struct XtensaConfig XtensaConfig; /** diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 85aab1bdf8..d6d2fb1f4e 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -586,8 +586,6 @@ G_NORETURN void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, #define cpu_list xtensa_cpu_list -#define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU -#define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU #if TARGET_BIG_ENDIAN From patchwork Mon Nov 6 11:02:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741334 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1026493wrr; Mon, 6 Nov 2023 03:16:11 -0800 (PST) X-Google-Smtp-Source: AGHT+IFecSja1ihpJEgvCdN+xTlPAmma27Alh2zpLWNyDbIueg0Ab6EUxzyAcBZTG7g1kt6E4Mem X-Received: by 2002:ac8:7d15:0:b0:41c:bb5e:52a6 with SMTP id g21-20020ac87d15000000b0041cbb5e52a6mr39242383qtb.45.1699269371609; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id l9-20020adfe589000000b0032f7d7ec4adsm9108143wrm.92.2023.11.06.03.05.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:17 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Brian Cain Subject: [PULL 14/60] target/hexagon: Declare QOM definitions in 'cpu-qom.h' Date: Mon, 6 Nov 2023 12:02:46 +0100 Message-ID: <20231106110336.358-15-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Add a comment clarifying that in the header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Brian Cain Message-Id: <20231013140116.255-8-philmd@linaro.org> --- target/hexagon/cpu-qom.h | 28 ++++++++++++++++++++++++++++ target/hexagon/cpu.h | 15 +-------------- 2 files changed, 29 insertions(+), 14 deletions(-) create mode 100644 target/hexagon/cpu-qom.h diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h new file mode 100644 index 0000000000..f02df7ee6f --- /dev/null +++ b/target/hexagon/cpu-qom.h @@ -0,0 +1,28 @@ +/* + * QEMU Hexagon CPU QOM header (target agnostic) + * + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef QEMU_HEXAGON_CPU_QOM_H +#define QEMU_HEXAGON_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_HEXAGON_CPU "hexagon-cpu" + +#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU +#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX) + +#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") +#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68") +#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69") +#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71") +#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73") + +OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) + +#endif diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 035ac4fb6d..7d16083c6a 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -20,11 +20,10 @@ #include "fpu/softfloat-types.h" +#include "cpu-qom.h" #include "exec/cpu-defs.h" #include "hex_regs.h" #include "mmvec/mmvec.h" -#include "qom/object.h" -#include "hw/core/cpu.h" #include "hw/registerfields.h" #define NUM_PREGS 4 @@ -36,18 +35,8 @@ #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ #define VSTORES_MAX 2 -#define TYPE_HEXAGON_CPU "hexagon-cpu" - -#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU -#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU -#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") -#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68") -#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69") -#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71") -#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73") - void hexagon_cpu_list(void); #define cpu_list hexagon_cpu_list @@ -127,8 +116,6 @@ typedef struct CPUArchState { VTCMStoreLog vtcm_log; } CPUHexagonState; -OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) - typedef struct HexagonCPUClass { CPUClass parent_class; From patchwork Mon Nov 6 11:02:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741335 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1026533wrr; Mon, 6 Nov 2023 03:16:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IEcM2e5v6sG7T9EijbRopuDmMaaWFxwDT7QjyU9k4skRn0tAUlpP4XFxIiQaQ87Y9N+SH61 X-Received: by 2002:ac8:570e:0:b0:41c:bc89:9cf5 with SMTP id 14-20020ac8570e000000b0041cbc899cf5mr37697895qtw.56.1699269378459; Mon, 06 Nov 2023 03:16:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269378; cv=none; d=google.com; s=arc-20160816; b=TzMT4xBxbpeXIX0YR3KYhXxkOD9qAF6jBhVSVAjBizc/c62GNKYVOrneCOlBHrkLKi vN38rY5cAC45+mT9+aHu9NfF1gZ3CjPO1CTXD65g1wQWBSp1o0YN7cZp00P2Y5dxuZ++ 1q2cAbxW0xqQPi62NDQVCkhfqJz3Ir438dG6tIWU4khOEBpzSYGICufBKylc8wQ3dcUs k51N9oa9hSXb4LL7wcmI968A3NW0cylSWI1bksmv1frQQi7VU0bDDdB8fCiV7marQ9PV 1SBNGln8mKfG97KXwt7pVkl11tFnpsU4uMir8EgjW3wADkUvGyPk8LS5YAPSEprPQhSB rqFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=JXuP88BtphoINz4Bov6u/pkpdXdezQqYli4OVAIpAZI=; fh=HHDAOkkCMuf4E2bzSwt4ZIJtIt9dFVMuzjG7zjOPHak=; b=mpQNGyPvpVI7fH0HsUIbRwbdsj2tGfppBsC7ONKqpDPbyqi66pYKb/Vhg+N0tEYk08 Cd6pTM8p9cemIQ76rKDJThXjhr8nDKTftUKDXExqw7ll1u7cAqZ/5dW9oCbOjjmyVek8 xYpRvNtuwaYzN4Xchn1qDP0tVAMzCQiWuJof3I7DHbO1rV/B5ksBvKRU9X6xjOdQKTh/ 3wF4b0ZFfYpQ64nc+YWpZ6DvlvovhdFXzRNhsQWZQ+E7SRQPBK9YfpkDkRpw97hCLKGf b38nFqUIEK1uB/YGuhUbOgA2NpIhswGFgW3W8/HTokmytdXIEgvEBtVCjASPZsfmNdzj o0Uw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E6sFIdPb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id f6-20020a5d5686000000b0032f7eaa6e43sm9161653wrv.79.2023.11.06.03.05.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:23 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson Subject: [PULL 15/60] target/loongarch: Declare QOM definitions in 'cpu-qom.h' Date: Mon, 6 Nov 2023 12:02:47 +0100 Message-ID: <20231106110336.358-16-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Add a comment clarifying that in the header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Reviewed-by: Song Gao Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-9-philmd@linaro.org> --- target/loongarch/cpu-qom.h | 24 ++++++++++++++++++++++++ target/loongarch/cpu.h | 10 +--------- 2 files changed, 25 insertions(+), 9 deletions(-) create mode 100644 target/loongarch/cpu-qom.h diff --git a/target/loongarch/cpu-qom.h b/target/loongarch/cpu-qom.h new file mode 100644 index 0000000000..82c86d146d --- /dev/null +++ b/target/loongarch/cpu-qom.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU LoongArch CPU QOM header (target agnostic) + * + * Copyright (c) 2021 Loongson Technology Corporation Limited + */ + +#ifndef LOONGARCH_CPU_QOM_H +#define LOONGARCH_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_LOONGARCH_CPU "loongarch-cpu" +#define TYPE_LOONGARCH32_CPU "loongarch32-cpu" +#define TYPE_LOONGARCH64_CPU "loongarch64-cpu" + +OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass, + LOONGARCH_CPU) + +#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU +#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX + +#endif diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 8f0e9f0182..c8839f4cff 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -17,6 +17,7 @@ #include "exec/memory.h" #endif #include "cpu-csr.h" +#include "cpu-qom.h" #define IOCSRF_TEMP 0 #define IOCSRF_NODECNT 1 @@ -381,13 +382,6 @@ struct ArchCPU { const char *dtb_compatible; }; -#define TYPE_LOONGARCH_CPU "loongarch-cpu" -#define TYPE_LOONGARCH32_CPU "loongarch32-cpu" -#define TYPE_LOONGARCH64_CPU "loongarch64-cpu" - -OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass, - LOONGARCH_CPU) - /** * LoongArchCPUClass: * @parent_realize: The parent class' realize handler. @@ -478,8 +472,6 @@ void loongarch_cpu_list(void); #include "exec/cpu-all.h" -#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU -#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU #endif /* LOONGARCH_CPU_H */ From patchwork Mon Nov 6 11:02:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741358 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1031091wrr; Mon, 6 Nov 2023 03:28:30 -0800 (PST) X-Google-Smtp-Source: AGHT+IGhlnlCVPvjoEFPvaNI0z9ADER8SzJ2fmF75GpyyjYVpZMFD55VKRHyOrJJIpP7gvd/HSbv X-Received: by 2002:a05:620a:198f:b0:779:d4ef:5f1f with SMTP id bm15-20020a05620a198f00b00779d4ef5f1fmr33689672qkb.29.1699270109819; Mon, 06 Nov 2023 03:28:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699270109; cv=none; d=google.com; s=arc-20160816; b=WH1SriC8oaA3s5+bs3uofNcjmPprTmtDoPRSoHK21sGS8N/+IwAVmhvnQ8m0It7AxT zeRW4TlihXvKm2BSaMevZlGlKDYKrUW49NQ7HSCuBx+KPG5kX3gPL6NsKa8+upaz1K96 5+czsTgeOCPxGUdGHbyO4JY0x9C+MHDREvLgr2wriZ4hAebYlsQNVZbFehxAni5CG6uI RgLyx11UIBh9G40kbZlM6o7kxH9cn597MEK/ihu9egP5blN66HRlYNZ5NHSDZC6CDUvU S1IjW7h4u3xc9znIQdQF32Ngpc7RgzJG88P/uX4InprmxTAAqoTa2zU3R93x5YVJiThv u5kQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=q3038rtVd/3WYQydMHaBWtXOqOEbAhMugZOF+LS9h+c=; fh=m4edQD1MqY6GbTcsot+ufBdLSBHZvJyU3muag/FpPiU=; b=xBio5nIaNSVn8Au0zw8/5tppiVwyVcBm4bA4Lh4A6X9VUVGwfYiDhtNN5nRbp1V+bL 9qaNv6QGp7Rhnphu/VgSiP0GSHMqtX2LVHcVfanADaPOYjMOsAugi/1IfJRDEiHyDCDR 4US6VLeitknmmRwRrg/Ay6LlWSlfd8kxG+8OQxFSwc1H68zra3qI/o93JP8L7dn7sFXb Q9xqG/kbgvMlh6+kspzw89KRpRME/RQDu1NqFB1zQ35iaDzffTaEc4MLKfVgHiKzw2uc 1V/nVxYcV/RbFHujOvOdwO2nS+NF1eO1M4K4+LSCBdf4FWaJBc+vSyj7ADtKvs9Oqjdu FdPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tnXy+ljf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id o8-20020a05600c510800b00407752f5ab6sm12025312wms.6.2023.11.06.03.05.29 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:30 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Chris Wulff , Marek Vasut Subject: [PULL 16/60] target/nios2: Declare QOM definitions in 'cpu-qom.h' Date: Mon, 6 Nov 2023 12:02:48 +0100 Message-ID: <20231106110336.358-17-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Add a comment clarifying that in the header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-10-philmd@linaro.org> --- target/nios2/cpu-qom.h | 19 +++++++++++++++++++ target/nios2/cpu.h | 7 +------ 2 files changed, 20 insertions(+), 6 deletions(-) create mode 100644 target/nios2/cpu-qom.h diff --git a/target/nios2/cpu-qom.h b/target/nios2/cpu-qom.h new file mode 100644 index 0000000000..931bc69b10 --- /dev/null +++ b/target/nios2/cpu-qom.h @@ -0,0 +1,19 @@ +/* + * QEMU Nios II CPU QOM header (target agnostic) + * + * Copyright (c) 2012 Chris Wulff + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef QEMU_NIOS2_CPU_QOM_H +#define QEMU_NIOS2_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_NIOS2_CPU "nios2-cpu" + +OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU) + +#endif diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index ede1ba2140..2d79b5b298 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -21,20 +21,15 @@ #ifndef NIOS2_CPU_H #define NIOS2_CPU_H +#include "cpu-qom.h" #include "exec/cpu-defs.h" -#include "hw/core/cpu.h" #include "hw/registerfields.h" -#include "qom/object.h" typedef struct CPUArchState CPUNios2State; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" #endif -#define TYPE_NIOS2_CPU "nios2-cpu" - -OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU) - /** * Nios2CPUClass: * @parent_phases: The parent class' reset phase handlers. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0040588d85b3asm11817685wmq.15.2023.11.06.03.05.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Stafford Horne Subject: [PULL 17/60] target/openrisc: Declare QOM definitions in 'cpu-qom.h' Date: Mon, 6 Nov 2023 12:02:49 +0100 Message-ID: <20231106110336.358-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=philmd@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Add a comment clarifying that in the header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-11-philmd@linaro.org> --- target/openrisc/cpu-qom.h | 22 ++++++++++++++++++++++ target/openrisc/cpu.h | 10 +--------- 2 files changed, 23 insertions(+), 9 deletions(-) create mode 100644 target/openrisc/cpu-qom.h diff --git a/target/openrisc/cpu-qom.h b/target/openrisc/cpu-qom.h new file mode 100644 index 0000000000..1ba9fb0a4c --- /dev/null +++ b/target/openrisc/cpu-qom.h @@ -0,0 +1,22 @@ +/* + * QEMU OpenRISC CPU QOM header (target agnostic) + * + * Copyright (c) 2011-2012 Jia Liu + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef QEMU_OPENRISC_CPU_QOM_H +#define QEMU_OPENRISC_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_OPENRISC_CPU "or1k-cpu" + +OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU) + +#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU +#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX + +#endif diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 29cda7279c..dedeb89f8e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -20,17 +20,12 @@ #ifndef OPENRISC_CPU_H #define OPENRISC_CPU_H +#include "cpu-qom.h" #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" -#include "hw/core/cpu.h" -#include "qom/object.h" #define TCG_GUEST_DEFAULT_MO (0) -#define TYPE_OPENRISC_CPU "or1k-cpu" - -OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU) - /** * OpenRISCCPUClass: * @parent_realize: The parent class' realize handler. @@ -304,7 +299,6 @@ struct ArchCPU { CPUOpenRISCState env; }; - void cpu_openrisc_list(void); void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); @@ -339,8 +333,6 @@ void cpu_openrisc_count_start(OpenRISCCPU *cpu); void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #endif -#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU -#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU #include "exec/cpu-all.h" From patchwork Mon Nov 6 11:02:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741327 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1025741wrr; Mon, 6 Nov 2023 03:14:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IHsnE87PaA54yLnUnoMJNDx2Asg6hgs9SJyVDoikWwMZMWkkL9SwMwVRgfXwWbGbpDT/fP3 X-Received: by 2002:a05:6214:4019:b0:66d:bbfb:839b with SMTP id kd25-20020a056214401900b0066dbbfb839bmr33932982qvb.41.1699269249592; Mon, 06 Nov 2023 03:14:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269249; cv=none; d=google.com; s=arc-20160816; b=wXPGtv/5FwYrOFR3yoS8MNIIcWsFiB1RVb0I210apQvlj5ZuL4XSlYhYCgCF/e3P+O ub98t2F3fBOxbEAZpedJUUMlizK/cTh+5x/epuqFwR1+od29vyWTk3ZmDPLHy0cHwQSg QmYHJSv6oXhXwTlcc+Q641vaMN3o7IWyck5Dl7l41YvzKBGYxhRE2RcTRYYx/yPVXhLE 07Tjyxkt5jRO/+7FAiAgMVJmlnqBtK8YO2oLWdvJXeCwXKbM7HNP9URp4uZSGExARuNJ DYmrbVI2PtTBz13NRxyAhMrvw7mPm1X3oa/mHidr70yFV8U3mU6GNSl7Y1xJne59Wr60 tq2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9TEM4y15WADC11ywrbeYDwNqe54vVpabH+nFuXXR9vo=; fh=tqOgyMxMfuHA5GMhfAbYIPsQvE3AsNctCR2lr9PI8rE=; b=kWHv9xasKlf++A7WvHw708BbPoYQ2j3cRWjjHfEVgdBbgu/K4grOLtMRy4nMHN9nEa w/kPeLDFXIV9RfGc+Fhly/bXz6Kgm2+DdUvN+AA6pHXx4FHJxAR7z23dg28f4owBaixp fv2uAdKLsuFdFq9UT0dn8MQRwbS7P+pzULwV5cRCkxML3bCOB9O8w5aeW0fxcQibtwwv ofq+4XfrVJjr3K1gi9w+m68DvXc7fTPfLXKGbf8pRt5uFe3KfXZY3vmDnmopVXh5/+wH 6xC6mlJhsBGqtjKCjHlfpBpPHn0lg17C0Snpcarhx7uO4hWcvXGN3QR8Q/BmVUiwaLpl EIuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DDcTivuo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id c12-20020adffb0c000000b0032fc5f5abafsm6040847wrr.96.2023.11.06.03.05.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:44 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , LIU Zhiwei , Alistair Francis , Richard Henderson , Palmer Dabbelt , Bin Meng , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 18/60] target/riscv: Move TYPE_RISCV_CPU_BASE definition to 'cpu.h' Date: Mon, 6 Nov 2023 12:02:50 +0100 Message-ID: <20231106110336.358-19-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org TYPE_RISCV_CPU_BASE depends on the TARGET_RISCV32/TARGET_RISCV64 definitions which are target specific. Such target specific definition taints "cpu-qom.h". Since "cpu-qom.h" must be target agnostic, remove its target specific definition uses by moving TYPE_RISCV_CPU_BASE to "target/riscv/cpu.h". "target/riscv/cpu-qom.h" is now fully target agnostic. Add a comment clarifying that in the header. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-12-philmd@linaro.org> --- target/riscv/cpu-qom.h | 8 +------- target/riscv/cpu.h | 6 ++++++ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index b78169093f..76efb614a6 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU RISC-V CPU QOM header + * QEMU RISC-V CPU QOM header (target agnostic) * * Copyright (c) 2023 Ventana Micro Systems Inc. * @@ -44,12 +44,6 @@ #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") -#if defined(TARGET_RISCV32) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 -#endif - typedef struct CPUArchState CPURISCVState; OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 144cc94cce..d832696418 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -34,6 +34,12 @@ #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU +#if defined(TARGET_RISCV32) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 +#elif defined(TARGET_RISCV64) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 +#endif + #define TCG_GUEST_DEFAULT_MO 0 /* From patchwork Mon Nov 6 11:02:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741323 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1024090wrr; Mon, 6 Nov 2023 03:10:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IEWbXH30osgzPyQqZiNYunmiKSoRFyrzWz+VRrz7cFF7XKJDVbQwcs/EJ7UmgXZC94AVq8t X-Received: by 2002:a05:622a:28c:b0:41c:c045:3ed with SMTP id z12-20020a05622a028c00b0041cc04503edmr31083577qtw.68.1699269016046; Mon, 06 Nov 2023 03:10:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269016; cv=none; d=google.com; s=arc-20160816; b=MqQyZbX3uFmduuv5ltxcMm0gytsXOWZUQ2Xm4lNqMgHCTJul5ie9VQt2ot2f8QfQBa Qw0wFU7B8yZcdkm8pgK5SKFLg+/okSgwrM09IiP2wwIoMxXZtNDPKXla5XvUnEdGKQ4c 5KHfAXhNvFzjCRcz2qlyqd+6e4CW74BLovO0a9yDBbrjTeBDTYFHuhWuoi+ToOFMUIrq hCfyJfeCkz+kaKg7RXe3m20Et4nTvk7zX5/U9jh8a/BajRPUWyV5EHUAr2Af/hzALAkC zt5RiTRS++egjmMlLxZduGZbCSuX2q8TosbpaQ1u6t4NyFQweNy4YYzGixxeTxAqJ2W3 s0Yw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=oZ4xqFJalLvpzsW1bcHeUL/13mhLi/mzZSAy+mux2v0=; fh=HuX1rIYGmdZZgKe/JxI9BhGzQc/86yFuDGfJ/eSpZl0=; b=KxZHQjBVpzG81wsCkl6VnyuVwI46CJcnbgDID4QYttr8cgJU+GwBfBwASl/GcdSsgZ NqSh6zodZnbQUXPw8Aft16isZCcyFKVakFfPWXPt08ykU7FOe/9iiwTrAqil6NMxhekn 7jYq6EaWyuyb6sIquzCgGPfILqOi7YhtG/asjMf11puyb70OJhYSu26EK5tfvwJx4HeJ PzThGEWIShHJTuRhFXQeLQ1BWiK+gKDx0pSw65p/qUC/BnMxJWad5TCjG9yBYDLi7pVr KDLMzeD6uZEMBuzpkL88z5/+OKm2iiuMEY/KxB7e4NAG//5UOfzlO6JLjIlq4Pgd/4u9 1f4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QrGpKoJ+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id bh5-20020a05600c3d0500b004094e565e71sm12164949wmb.23.2023.11.06.03.05.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:51 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Daniel Henrique Barboza , Richard Henderson , Alistair Francis , Nicholas Piggin , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= Subject: [PULL 19/60] target/ppc: Use env_archcpu() in helper_book3s_msgsndp() Date: Mon, 6 Nov 2023 12:02:51 +0100 Message-ID: <20231106110336.358-20-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When CPUArchState* is available (here CPUPPCState*), we can use the fast env_archcpu() macro to get ArchCPU* (here PowerPCCPU*). The QOM cast POWERPC_CPU() macro will be slower when building with --enable-qom-cast-debug. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-Id: <20231009110239.66778-2-philmd@linaro.org> --- target/ppc/excp_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 7926114d5c..a42743a3e0 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -3136,7 +3136,7 @@ void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb) void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb) { CPUState *cs = env_cpu(env); - PowerPCCPU *cpu = POWERPC_CPU(cs); + PowerPCCPU *cpu = env_archcpu(env); CPUState *ccs; uint32_t nr_threads = cs->nr_threads; int ttir = rb & PPC_BITMASK(57, 63); From patchwork Mon Nov 6 11:02:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741325 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1024359wrr; Mon, 6 Nov 2023 03:10:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IEwyerpCIbhd0Own3ugWRQcnHK+/3lSccw2XYvRgioloFOa9+mo3EVgRUJ4GdbPtg1/nymF X-Received: by 2002:a25:aa47:0:b0:d9a:5895:2c74 with SMTP id s65-20020a25aa47000000b00d9a58952c74mr26886302ybi.42.1699269052928; Mon, 06 Nov 2023 03:10:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269052; cv=none; d=google.com; s=arc-20160816; b=AAyXjkryPyr6QeR63iIxeMhfrx2xYdFcto3ke4a0cwPlJUQmyIoNZCxMGt4Rx1gr4t X96H98OSEaS1vQuKNQELSZpoHQQ6C21o8JZ3q5HlEKX1Ic1ivTJ+JQVCzauijHsHFl6k 0B5KOs8stcCgAci+yulKt05/dEbOZW5FjlyP+CwIX56QIKt1bfxsbAlCziWrvFOTkuOW A8YCsDFMn8zn7Rnd4u6M23X74xWk5hSkH/nsRY+0BKTW/RT1JgLJNCe0KBOsBF4G+fgK qmGerX69c12GPYgazq+vbkvDqOjOgQWaf806HGEJNCvumDX7++lhoAEaA/nfArRybnEv tFPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WdevyuV5vDNMMgKGndHL1Lb3pKI2mM3BGOnKiVXcZMA=; fh=QkIcAbdeg7uT6FK914KQVPDd8FDc9hVDQgO9cPJGHCk=; b=AWIvsnnCq6wkVRDms0DNolCmSgXU6geuFJlaiYCGoanMZprZkK60a12P2n/8elSlMF KsuKOXr45itrlAjh143/hrGc525a6ff0crHhhKZr8R3sRZFh5+AYAoQkzb2338MWGkcf ckU6B0HgAeZVSI94EDNeFkx808Ih9jDncDG4SLIte846GG1JfCxFrToSiZ2CCqGXlVS2 sOsr7DHC7/MizXWMNAkK8aENf6uPD4MEvnLe+SOogpb6bknySzN6PXRhONWyxQGUlUJp rJvMk+14B4WGClKVZzpe8/H9O36cdYPCgvsy0nM/gdIxXX0rCdRxoO0YbfqcKXO5fv3S yugg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=n3lXasjQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id r13-20020a05600c458d00b00406443c8b4fsm11744176wmo.19.2023.11.06.03.05.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:58 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Richard W . M . Jones" , Daniel Henrique Barboza , LIU Zhiwei , Richard Henderson , Alistair Francis , Palmer Dabbelt , Bin Meng , Weiwei Li Subject: [PULL 20/60] target/riscv: Use env_archcpu() in [check_]nanbox() Date: Mon, 6 Nov 2023 12:02:52 +0100 Message-ID: <20231106110336.358-21-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When CPUArchState* is available (here CPURISCVState*), we can use the fast env_archcpu() macro to get ArchCPU* (here RISCVCPU*). The QOM cast RISCV_CPU() macro will be slower when building with --enable-qom-cast-debug. Inspired-by: Richard W.M. Jones Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Richard W.M. Jones Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20231009110239.66778-3-philmd@linaro.org> --- target/riscv/internals.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index b5f823c7ec..8239ae83cc 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -87,7 +87,7 @@ enum { static inline uint64_t nanbox_s(CPURISCVState *env, float32 f) { /* the value is sign-extended instead of NaN-boxing for zfinx */ - if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { + if (env_archcpu(env)->cfg.ext_zfinx) { return (int32_t)f; } else { return f | MAKE_64BIT_MASK(32, 32); @@ -97,7 +97,7 @@ static inline uint64_t nanbox_s(CPURISCVState *env, float32 f) static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f) { /* Disable NaN-boxing check when enable zfinx */ - if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { + if (env_archcpu(env)->cfg.ext_zfinx) { return (uint32_t)f; } @@ -113,7 +113,7 @@ static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f) static inline uint64_t nanbox_h(CPURISCVState *env, float16 f) { /* the value is sign-extended instead of NaN-boxing for zfinx */ - if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { + if (env_archcpu(env)->cfg.ext_zfinx) { return (int16_t)f; } else { return f | MAKE_64BIT_MASK(16, 48); @@ -123,7 +123,7 @@ static inline uint64_t nanbox_h(CPURISCVState *env, float16 f) static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f) { /* Disable nanbox check when enable zfinx */ - if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { + if (env_archcpu(env)->cfg.ext_zfinx) { return (uint16_t)f; } From patchwork Mon Nov 6 11:02:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741332 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1025978wrr; Mon, 6 Nov 2023 03:14:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IG8obWq5Wxe70Je3WejZBF62OmwwL2M1P2nh6IImqSE/W4lQPYIrqeWT9Rc8e5lO2FRdkkm X-Received: by 2002:a67:cc1d:0:b0:45e:9611:7b6e with SMTP id q29-20020a67cc1d000000b0045e96117b6emr3641798vsl.2.1699269295209; Mon, 06 Nov 2023 03:14:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269295; cv=none; d=google.com; s=arc-20160816; b=eK8pV2N3p07mivqKaHlg8jdJVpUkq4BePhaH7QlvB+PxNtNyKs8UlYTVWccQOLo6Vt foDuimF0cSjkTDGqs28zVetnkkiRxkkvy8pFklfjDlg0l+xMFP/YUDj9ngXBUKcjdcHP 6BtVnJOUvRXa9/T3H+0yFNcyCmMHjgA5zhK3hM8DVIwTLqM2kZREGj4kH3epymu5X5mf N9Bl8Ygetrsx+DLxQxqmPyawxxdFnujMtg4FOhi3zQObFkKqhutZh/JNSHCARBzzZMsZ EPkq8ihkLGksvDE6ihigFxiFRvI1kyxqPwHXVU3WEmD7MwrQl8i3/tnfAaJZs233Qv7z idtQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=R87QIdTSbuBFqtOuBBqCdN1J8XfSkpLJYhBFwzXT2iA=; fh=yyoSMMuczYczRB0qLOV9kKRdIs9IcHxKWkwG7vSWkvM=; b=iz2PlXb1d/ro5vmI5Z0GLhhI+OqrgaP1mt6CPTD28xFnouJQ67dsS5W2Pj9g3U8emu 1rhUD3NxqpSjvOVd8nlA7B/NU3AF/7E4E9kimQgpeT5RNgvTzSkxtXDIX02InaSSvoXU kJgdHdYrttSzE5idbUPrJH+OlPltLIBv2YCiDEYVfsDltKRME1laNDyAx0cGNONfSSZl +LvJmcu00dpEy019JcpS33pSbhTHD/yLLXmEtY3yOBTASeboqZFL+mNsKtGho1qntlFP uzNuUKt3GuBxMQ+tHrJgxuCULb96BUOazr0gPUK7e9iFmNNJdSavfTI+SrLZv2r+bwb7 qifg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Kj/1LaOC"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id i20-20020a05600c355400b0040839fcb217sm11896421wmq.8.2023.11.06.03.06.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:06:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Alistair Francis , David Hildenbrand , Ilya Leoshkevich , Thomas Huth Subject: [PULL 21/60] target/s390x: Use env_archcpu() in handle_diag_308() Date: Mon, 6 Nov 2023 12:02:53 +0100 Message-ID: <20231106110336.358-22-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When CPUArchState* is available (here CPUS390XState*), we can use the fast env_archcpu() macro to get ArchCPU* (here S390CPU*). The QOM cast S390_CPU() macro will be slower when building with --enable-qom-cast-debug. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-Id: <20231009110239.66778-4-philmd@linaro.org> --- target/s390x/diag.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/s390x/diag.c b/target/s390x/diag.c index 8ce18e08f3..27ffd48576 100644 --- a/target/s390x/diag.c +++ b/target/s390x/diag.c @@ -77,7 +77,7 @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra) { bool valid; CPUState *cs = env_cpu(env); - S390CPU *cpu = S390_CPU(cs); + S390CPU *cpu = env_archcpu(env); uint64_t addr = env->regs[r1]; uint64_t subcode = env->regs[r3]; IplParameterBlock *iplb; From patchwork Mon Nov 6 11:02:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741345 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1027984wrr; Mon, 6 Nov 2023 03:20:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IGYJHDBXQrfCVEUCZL0m37frKTFRcm6Fm8cB7tb9uKmxTHwI+X0tl5HS00amvYoEKsRbZr5 X-Received: by 2002:a25:c5c4:0:b0:d9c:1ef5:afb with SMTP id v187-20020a25c5c4000000b00d9c1ef50afbmr30580713ybe.25.1699269606296; Mon, 06 Nov 2023 03:20:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269606; cv=none; d=google.com; s=arc-20160816; b=umQrEdndUBFRBYfCRgmWvya8eYExnhy8c7+d03eP/725ES41V8ChmMn2IJKwGdP1E4 +b/QcdXB1ALbqWimpH5xcrj9s8aNLRr6+UIYg4VtQz1uwlvqMBi7e+aj2uTi9yGTvCvp EQG0iG1X9CU182SVYVfPVfAlrwOAj6NHGYWKv8CQs4demZNz4vESeWetaBEA4L+Wjb7q BuKV3MPTLAv3EddgrJc92GL3UAHFKGmU8y/ba7tYZmSu1HdZVExAtkSDBGHCFgvhB3rC UxK/xwRZmJsHyUIv5CnyHd6pSVVPr/m7xasYUaycKA+NtKf/rs5dZ1iG6Bp4mSidQsZ3 MGHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Kr5DULV07OwGLXl8unpIp7yrXhMhnI+29Dc5ljVlc2w=; fh=KsRs8T3mbLYMlyhqBIfasTAuo72nFePg8n4RIyLlRbA=; b=P4bbHDnsF2J3tslxIcpeu1dXXB94xVyT/piCBiB9hMP64Vj09vD4iw+uqz3u4uFqFc 2gcR9BsTOEMnlv1lS1/C1PhAhEuZ99/pIiBC6iBWXSanQM+ZBnLonS/Ikx73F5prL+4U 4cgsC8ZTULDy/ETyAAJu6G6sXYc51X+i+FFPvKsCIEI3sVzewVt7ad9AE2Pk3Ip/1nU/ sj5gu4lwpDFxgiey4Yw2mr/rEaOEIPWByvKVpeIW+XaDsqL+3pH+jdsOJmIxvCSJwMWR w0UcT6EeSOlDmxUJC53j3/VZKGLxMPxU9moogP0UMeTHDkyK8Vb2v+JVNmYYqDEfOS54 xpAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sOxXyZef; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id j11-20020a5d618b000000b0032db4825495sm9214037wru.22.2023.11.06.03.06.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:06:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Alistair Francis , Max Filippov Subject: [PULL 22/60] target/xtensa: Use env_archcpu() in update_c[compare|count]() Date: Mon, 6 Nov 2023 12:02:54 +0100 Message-ID: <20231106110336.358-23-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When CPUArchState* is available (here CPUXtensaState*), we can use the fast env_archcpu() macro to get ArchCPU* (here XtensaCPU*). The QOM cast XTENSA_CPU() macro will be slower when building with --enable-qom-cast-debug. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-Id: <20231009110239.66778-5-philmd@linaro.org> --- target/xtensa/op_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 7bb8cd6726..496754ba57 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -37,7 +37,7 @@ void HELPER(update_ccount)(CPUXtensaState *env) { - XtensaCPU *cpu = XTENSA_CPU(env_cpu(env)); + XtensaCPU *cpu = env_archcpu(env); uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); env->ccount_time = now; @@ -58,7 +58,7 @@ void HELPER(wsr_ccount)(CPUXtensaState *env, uint32_t v) void HELPER(update_ccompare)(CPUXtensaState *env, uint32_t i) { - XtensaCPU *cpu = XTENSA_CPU(env_cpu(env)); + XtensaCPU *cpu = env_archcpu(env); uint64_t dcc; qatomic_and(&env->sregs[INTSET], From patchwork Mon Nov 6 11:02:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741353 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1029115wrr; Mon, 6 Nov 2023 03:23:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IEBz4QOTkXOnFfCOZayPv+pKlAGvFmuHByGse5Qc8CCeiCMrSaM+4ctavZcGk3oRlzKc7DV X-Received: by 2002:a05:620a:c42:b0:77a:55b2:a125 with SMTP id u2-20020a05620a0c4200b0077a55b2a125mr16463582qki.65.1699269786306; Mon, 06 Nov 2023 03:23:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269786; cv=none; d=google.com; s=arc-20160816; b=wkjUZh8gQhd6HJ2qJOzs6Ez/c+55K0YpYajsauJRsEXdQQEoC6oNs6NMvYDI4c1f5P LiO7FZoCNa0f6/xHlLj2tmBHNUVrYmmL8RK9N4Df1eX6EacgauM6tfhSso11By6BG6ao +8/Copokbiz6otv2hhLuvDva4GgoKdsSXMEzGvZSPanKVYhLyjlgQG6qdik+AFrBib3m 9U5hdKEwcSFSAL3nFnApU5lCmxCPysQOGs3kxGhDU8seI1kYCpfXVc5a0Fg2BmFnZtjB hkZvUz2oBDMLTq2Do3eG4f+vsy/Xggi2VTAvdKdO1BcSuCjVCWKCz9fM6nRIeCItXJud XznA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9JKKmt1EY/kf3nircSCgd4NoTIWcG19r0u1T6OQDS20=; fh=sv0Y+dA/cU1Bgb/VBJogqin4Spf+R0vCWKmGl8Na7m0=; b=DLxRZiMTPYDpnieqR1dqCH+W1wk/PDDvOgK1jkRJaotR5aGETynbJ47OXRr7WMNBCY jZ2EnJlCaMlmEijE2+Yc0uegzQX31M+5gsIKfdfmgqnWSOYC2SeX3j2uSy5CvHOeUfUo GQX44k/OluyB3j89vX3gXQdaHv1RpfsYiLxcEEHtpn7jnfzZflP0Qv13lMgAQgT3yHln Z6ES0CLCuIM6XURNUcKLCfGhhvqkkYaXpz5EtWXrgRBRXvfCjY8wrobl6ZMkHlDACdQH cDxq9+mIVL7eADlprXHnxI5lbMcJ3Dx9BOzqGj/sTMX1TI/QxYbYA6ks33fuEzK+EAHP RjGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QVC1LiYW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id e22-20020a05600c109600b0040523bef620sm5449491wmd.0.2023.11.06.03.06.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:06:19 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Roman Bolshakov , Zhao Liu , Cameron Esfahani , Roman Bolshakov Subject: [PULL 23/60] target/i386/hvf: Use x86_cpu in simulate_[rdmsr|wrmsr]() Date: Mon, 6 Nov 2023 12:02:55 +0100 Message-ID: <20231106110336.358-24-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We already have 'x86_cpu = X86_CPU(cpu)'. Use the variable instead of doing another QOM cast with X86_CPU(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Roman Bolshakov Tested-by: Roman Bolshakov Reviewed-by: Zhao Liu Message-Id: <20231009110239.66778-6-philmd@linaro.org> --- target/i386/hvf/x86_emu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index ccda568478..af1f205ecf 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -676,7 +676,7 @@ void simulate_rdmsr(struct CPUState *cpu) val = rdtscp() + rvmcs(cpu->accel->fd, VMCS_TSC_OFFSET); break; case MSR_IA32_APICBASE: - val = cpu_get_apic_base(X86_CPU(cpu)->apic_state); + val = cpu_get_apic_base(x86_cpu->apic_state); break; case MSR_IA32_UCODE_REV: val = x86_cpu->ucode_rev; @@ -776,7 +776,7 @@ void simulate_wrmsr(struct CPUState *cpu) case MSR_IA32_TSC: break; case MSR_IA32_APICBASE: - cpu_set_apic_base(X86_CPU(cpu)->apic_state, data); + cpu_set_apic_base(x86_cpu->apic_state, data); break; case MSR_FSBASE: wvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE, data); From patchwork Mon Nov 6 11:02:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741350 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1028889wrr; Mon, 6 Nov 2023 03:22:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IE8EEipoBkZvuSDXP1SOjzrCna2fKLxq7a7ZypSnArz8M9XpgmatAN/bor8bM9DifP1X11v X-Received: by 2002:a05:622a:204:b0:41e:54b4:347c with SMTP id b4-20020a05622a020400b0041e54b4347cmr31303071qtx.43.1699269754635; Mon, 06 Nov 2023 03:22:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269754; cv=none; d=google.com; s=arc-20160816; b=bfwJtkpuhD8XVTnuyV81n+iArjsEayqHZ+CGWgw6w/Svl+7vaE1nqdL7N8ggREuXi0 D5M893MA4JebuKs20p89okaIiTDAlkxtCI7X0o4AvEE1iMWzj9YUN7ae5jYOqO82nEDV 6xoeK/4BLCJvCv/0sHZjiZgRZ+4OZl6tJp9Ze2VvFpVN2+5l9HAgKPBdru5zKIsLNJ9U KTpBfD24CyT76Tmh2jMTTYsBZPQ1EwiGshSzonaEWClb1i2MCR1lysodet2QMnjvZNoN mJRbRs0clElOOrIC9wLC5Ek8FR2YcUKpFOUOUz2UCCklv9TwoMY5lQ4fTkzEjfGIN94T 2pDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3KIslD3tBGe6rvvH4379K4CtN4FVJCslZLzDLuVWSbo=; fh=sv0Y+dA/cU1Bgb/VBJogqin4Spf+R0vCWKmGl8Na7m0=; b=bZJInezv2HXSOxitjHYVDkdBLZ8QVnmjiG8OdpNhkwqVsxYkHXLFLKMvV7xLoAAPP3 64OALELsIevX70yriu6M4dd8qo5jqK665mxcCReIPd5AXMS/8UK1vfYGm6EmstNd2AgC gprXSa7NXgXLdmP4GDdsyCDyNWiUx+DfsMfA5rNS1C/Bh1vRZJNgiRBzPITEdvoVTXjf jvUOSlps8B59MaflygGvZxkb/GjauoQbC6/240qyI1nOu8w8CGtMIuYNdg83t/MRyTlW loqyI9U3AX3acJkzeORFv4HdNSlSmfJH5I8UdUAGDyjKwROlCt/yT3Fj77Vv3IRNmcem 5i8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Rq+3HeA0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id j19-20020a05600c1c1300b004060f0a0fd5sm11856347wms.13.2023.11.06.03.06.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:06:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Roman Bolshakov , Zhao Liu , Cameron Esfahani , Roman Bolshakov Subject: [PULL 24/60] target/i386/hvf: Use env_archcpu() in simulate_[rdmsr/wrmsr]() Date: Mon, 6 Nov 2023 12:02:56 +0100 Message-ID: <20231106110336.358-25-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When CPUArchState* is available (here CPUX86State*), we can use the fast env_archcpu() macro to get ArchCPU* (here X86CPU*). The QOM cast X86_CPU() macro will be slower when building with --enable-qom-cast-debug. Pass CPUX86State* as argument to simulate_rdmsr / simulate_wrmsr instead of a CPUState* to avoid an extra cast. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Roman Bolshakov Tested-by: Roman Bolshakov Reviewed-by: Zhao Liu Message-Id: <20231009110239.66778-7-philmd@linaro.org> --- target/i386/hvf/x86_emu.h | 4 ++-- target/i386/hvf/hvf.c | 4 ++-- target/i386/hvf/x86_emu.c | 21 ++++++++++----------- 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/target/i386/hvf/x86_emu.h b/target/i386/hvf/x86_emu.h index 640da90b30..4b846ba80e 100644 --- a/target/i386/hvf/x86_emu.h +++ b/target/i386/hvf/x86_emu.h @@ -29,8 +29,8 @@ bool exec_instruction(CPUX86State *env, struct x86_decode *ins); void load_regs(struct CPUState *cpu); void store_regs(struct CPUState *cpu); -void simulate_rdmsr(struct CPUState *cpu); -void simulate_wrmsr(struct CPUState *cpu); +void simulate_rdmsr(CPUX86State *env); +void simulate_wrmsr(CPUX86State *env); target_ulong read_reg(CPUX86State *env, int reg, int size); void write_reg(CPUX86State *env, int reg, target_ulong val, int size); diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index cb2cd0b02f..20b9ca3ef5 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -591,9 +591,9 @@ int hvf_vcpu_exec(CPUState *cpu) { load_regs(cpu); if (exit_reason == EXIT_REASON_RDMSR) { - simulate_rdmsr(cpu); + simulate_rdmsr(env); } else { - simulate_wrmsr(cpu); + simulate_wrmsr(env); } env->eip += ins_len; store_regs(cpu); diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index af1f205ecf..b1f8a685d1 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -663,11 +663,10 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode) env->eip += decode->len; } -void simulate_rdmsr(struct CPUState *cpu) +void simulate_rdmsr(CPUX86State *env) { - X86CPU *x86_cpu = X86_CPU(cpu); - CPUX86State *env = &x86_cpu->env; - CPUState *cs = env_cpu(env); + X86CPU *x86_cpu = env_archcpu(env); + CPUState *cpu = env_cpu(env); uint32_t msr = ECX(env); uint64_t val = 0; @@ -746,8 +745,8 @@ void simulate_rdmsr(struct CPUState *cpu) val = env->mtrr_deftype; break; case MSR_CORE_THREAD_COUNT: - val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */ - val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */ + val = cpu->nr_threads * cpu->nr_cores; /* thread count, bits 15..0 */ + val |= ((uint32_t)cpu->nr_cores << 16); /* core count, bits 31..16 */ break; default: /* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */ @@ -761,14 +760,14 @@ void simulate_rdmsr(struct CPUState *cpu) static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode) { - simulate_rdmsr(env_cpu(env)); + simulate_rdmsr(env); env->eip += decode->len; } -void simulate_wrmsr(struct CPUState *cpu) +void simulate_wrmsr(CPUX86State *env) { - X86CPU *x86_cpu = X86_CPU(cpu); - CPUX86State *env = &x86_cpu->env; + X86CPU *x86_cpu = env_archcpu(env); + CPUState *cpu = env_cpu(env); uint32_t msr = ECX(env); uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env); @@ -856,7 +855,7 @@ void simulate_wrmsr(struct CPUState *cpu) static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode) { - simulate_wrmsr(env_cpu(env)); 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id iv12-20020a05600c548c00b0040641a9d49bsm11948176wmb.17.2023.11.06.03.06.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:06:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Zhao Liu , Cameron Esfahani , Roman Bolshakov Subject: [PULL 25/60] target/i386/hvf: Use CPUState typedef Date: Mon, 6 Nov 2023 12:02:57 +0100 Message-ID: <20231106110336.358-26-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=philmd@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Follow C style guidelines and use CPUState forward declaration from "qemu/typedefs.h". No functional changes. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Zhao Liu Message-Id: <20231020111136.44401-2-philmd@linaro.org> --- target/i386/hvf/x86_emu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index b1f8a685d1..cd7ef30126 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -45,7 +45,7 @@ #include "vmcs.h" #include "vmx.h" -void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data, +void hvf_handle_io(CPUState *cpu, uint16_t port, void *data, int direction, int size, uint32_t count); #define EXEC_2OP_FLAGS_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \ @@ -1417,7 +1417,7 @@ static void init_cmd_handler() } } -void load_regs(struct CPUState *cpu) +void load_regs(CPUState *cpu) { X86CPU *x86_cpu = X86_CPU(cpu); CPUX86State *env = &x86_cpu->env; @@ -1440,7 +1440,7 @@ void load_regs(struct CPUState *cpu) env->eip = rreg(cpu->accel->fd, HV_X86_RIP); } -void store_regs(struct CPUState *cpu) +void store_regs(CPUState *cpu) { X86CPU *x86_cpu = X86_CPU(cpu); CPUX86State *env = &x86_cpu->env; From patchwork Mon Nov 6 11:02:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741367 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1035007wrr; Mon, 6 Nov 2023 03:39:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IHq8zRzPpMD6QKsfSWK6eQQeoyzOi5VWoQPko5hRADay2FNMpd4KyASGwRSvmOCmLe7KM6s X-Received: by 2002:ac8:4e88:0:b0:419:8f42:8c45 with SMTP id 8-20020ac84e88000000b004198f428c45mr35264055qtp.8.1699270740720; Mon, 06 Nov 2023 03:39:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699270740; cv=none; d=google.com; s=arc-20160816; b=OU4CjWI/m+4vjEl7R6i+X+dgxDvCr7rljCRbDyKvh35hFEx9gqswaybH9skSvEYW5c Udr+qYQb6ITXj/G4QmI1iE5/mpVl/bJlVQR/o4mcvYt1vHlwReqS3fo3/rZnU4gwznmg zygDw8ZJnFnvq9/8VgKxoFGeL6XXIobc5Qs5++g41lCSlu5udh+L1raEfWx9QxfHTEbL pmRNh2c9z/ZlkjdXHAEdJ3TpgsBCVXlYqHnbbDuqRYfXxhgiUrA3AmErZueQw03i6J2r 55/OExy95irlshN71VSzVykljxoDRt4OyXEhrAxmMnajmEwLoGThJa8D6Ctqm0KsmIvW T3bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zvMSXcHtnsGDEEiq2Ygmmilt86JHxbxrpSYP17lWc2k=; fh=M7LpSu7Ta78I+2rWAN95QEp5TLITKFQ2uBdD4PuAGlE=; b=YVesDijjGl0jBS1eotc8CeoKTCIesOk4ntRvIblyONaEDTTw8ZmCAH088IYqn5HJlE m8Jjt55nVbXfPylp4h6o+tKUx06VY/mwPiPi5YPcnXyefAcx97LnBKsxYqnVKyfGgmxI 6BfTZqc6TPqEzL6DNhbH0vbzXcEvuEbxyVGRsx40LSkUv9z/82Zmyr5vjSrB7iJkxTqL 0zVonX8xDow+ns9C9ilBNLBDAnkH4+fDEKwvvfF6t1P4QhHSS1Z1faZWDDxEyL3QRIFI 6Metq8gHLwqyrf3EaSaVxPhwU1AAN3ha33T+ANZNpigVBv4slnD4HosiAhPN4CyzmTb6 rVIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="GDbc/Gdx"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id g20-20020a05600c4ed400b003fee8793911sm12017300wmq.44.2023.11.06.03.06.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:06:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Zhao Liu , Cameron Esfahani , Roman Bolshakov Subject: [PULL 26/60] target/i386/hvf: Rename 'CPUState *cpu' variable as 'cs' Date: Mon, 6 Nov 2023 12:02:58 +0100 Message-ID: <20231106110336.358-27-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=philmd@linaro.org; helo=mail-lj1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Follow the naming used by other files in target/i386/. No functional changes. Suggested-by: Zhao Liu Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Zhao Liu Message-Id: <20231020111136.44401-3-philmd@linaro.org> --- target/i386/hvf/x86_emu.c | 92 +++++++++++++++++++-------------------- 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index cd7ef30126..5b82e84778 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -45,7 +45,7 @@ #include "vmcs.h" #include "vmx.h" -void hvf_handle_io(CPUState *cpu, uint16_t port, void *data, +void hvf_handle_io(CPUState *cs, uint16_t port, void *data, int direction, int size, uint32_t count); #define EXEC_2OP_FLAGS_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \ @@ -666,13 +666,13 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode) void simulate_rdmsr(CPUX86State *env) { X86CPU *x86_cpu = env_archcpu(env); - CPUState *cpu = env_cpu(env); + CPUState *cs = env_cpu(env); uint32_t msr = ECX(env); uint64_t val = 0; switch (msr) { case MSR_IA32_TSC: - val = rdtscp() + rvmcs(cpu->accel->fd, VMCS_TSC_OFFSET); + val = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET); break; case MSR_IA32_APICBASE: val = cpu_get_apic_base(x86_cpu->apic_state); @@ -681,16 +681,16 @@ void simulate_rdmsr(CPUX86State *env) val = x86_cpu->ucode_rev; break; case MSR_EFER: - val = rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER); + val = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER); break; case MSR_FSBASE: - val = rvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE); + val = rvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE); break; case MSR_GSBASE: - val = rvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE); + val = rvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE); break; case MSR_KERNELGSBASE: - val = rvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE); + val = rvmcs(cs->accel->fd, VMCS_HOST_FS_BASE); break; case MSR_STAR: abort(); @@ -745,8 +745,8 @@ void simulate_rdmsr(CPUX86State *env) val = env->mtrr_deftype; break; case MSR_CORE_THREAD_COUNT: - val = cpu->nr_threads * cpu->nr_cores; /* thread count, bits 15..0 */ - val |= ((uint32_t)cpu->nr_cores << 16); /* core count, bits 31..16 */ + val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */ + val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */ break; default: /* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */ @@ -767,7 +767,7 @@ static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode) void simulate_wrmsr(CPUX86State *env) { X86CPU *x86_cpu = env_archcpu(env); - CPUState *cpu = env_cpu(env); + CPUState *cs = env_cpu(env); uint32_t msr = ECX(env); uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env); @@ -778,13 +778,13 @@ void simulate_wrmsr(CPUX86State *env) cpu_set_apic_base(x86_cpu->apic_state, data); break; case MSR_FSBASE: - wvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE, data); + wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data); break; case MSR_GSBASE: - wvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE, data); + wvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE, data); break; case MSR_KERNELGSBASE: - wvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE, data); + wvmcs(cs->accel->fd, VMCS_HOST_FS_BASE, data); break; case MSR_STAR: abort(); @@ -796,10 +796,10 @@ void simulate_wrmsr(CPUX86State *env) abort(); break; case MSR_EFER: - /*printf("new efer %llx\n", EFER(cpu));*/ - wvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER, data); + /*printf("new efer %llx\n", EFER(cs));*/ + wvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER, data); if (data & MSR_EFER_NXE) { - hv_vcpu_invalidate_tlb(cpu->accel->fd); + hv_vcpu_invalidate_tlb(cs->accel->fd); } break; case MSR_MTRRphysBase(0): @@ -848,9 +848,9 @@ void simulate_wrmsr(CPUX86State *env) /* Related to support known hypervisor interface */ /* if (g_hypervisor_iface) - g_hypervisor_iface->wrmsr_handler(cpu, msr, data); + g_hypervisor_iface->wrmsr_handler(cs, msr, data); - printf("write msr %llx\n", RCX(cpu));*/ + printf("write msr %llx\n", RCX(cs));*/ } static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode) @@ -1417,56 +1417,56 @@ static void init_cmd_handler() } } -void load_regs(CPUState *cpu) +void load_regs(CPUState *cs) { - X86CPU *x86_cpu = X86_CPU(cpu); + X86CPU *x86_cpu = X86_CPU(cs); CPUX86State *env = &x86_cpu->env; int i = 0; - RRX(env, R_EAX) = rreg(cpu->accel->fd, HV_X86_RAX); - RRX(env, R_EBX) = rreg(cpu->accel->fd, HV_X86_RBX); - RRX(env, R_ECX) = rreg(cpu->accel->fd, HV_X86_RCX); - RRX(env, R_EDX) = rreg(cpu->accel->fd, HV_X86_RDX); - RRX(env, R_ESI) = rreg(cpu->accel->fd, HV_X86_RSI); - RRX(env, R_EDI) = rreg(cpu->accel->fd, HV_X86_RDI); - RRX(env, R_ESP) = rreg(cpu->accel->fd, HV_X86_RSP); - RRX(env, R_EBP) = rreg(cpu->accel->fd, HV_X86_RBP); + RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX); + RRX(env, R_EBX) = rreg(cs->accel->fd, HV_X86_RBX); + RRX(env, R_ECX) = rreg(cs->accel->fd, HV_X86_RCX); + RRX(env, R_EDX) = rreg(cs->accel->fd, HV_X86_RDX); + RRX(env, R_ESI) = rreg(cs->accel->fd, HV_X86_RSI); + RRX(env, R_EDI) = rreg(cs->accel->fd, HV_X86_RDI); + RRX(env, R_ESP) = rreg(cs->accel->fd, HV_X86_RSP); + RRX(env, R_EBP) = rreg(cs->accel->fd, HV_X86_RBP); for (i = 8; i < 16; i++) { - RRX(env, i) = rreg(cpu->accel->fd, HV_X86_RAX + i); + RRX(env, i) = rreg(cs->accel->fd, HV_X86_RAX + i); } - env->eflags = rreg(cpu->accel->fd, HV_X86_RFLAGS); + env->eflags = rreg(cs->accel->fd, HV_X86_RFLAGS); rflags_to_lflags(env); - env->eip = rreg(cpu->accel->fd, HV_X86_RIP); + env->eip = rreg(cs->accel->fd, HV_X86_RIP); } -void store_regs(CPUState *cpu) +void store_regs(CPUState *cs) { - X86CPU *x86_cpu = X86_CPU(cpu); + X86CPU *x86_cpu = X86_CPU(cs); CPUX86State *env = &x86_cpu->env; int i = 0; - wreg(cpu->accel->fd, HV_X86_RAX, RAX(env)); - wreg(cpu->accel->fd, HV_X86_RBX, RBX(env)); - wreg(cpu->accel->fd, HV_X86_RCX, RCX(env)); - wreg(cpu->accel->fd, HV_X86_RDX, RDX(env)); - wreg(cpu->accel->fd, HV_X86_RSI, RSI(env)); - wreg(cpu->accel->fd, HV_X86_RDI, RDI(env)); - wreg(cpu->accel->fd, HV_X86_RBP, RBP(env)); - wreg(cpu->accel->fd, HV_X86_RSP, RSP(env)); + wreg(cs->accel->fd, HV_X86_RAX, RAX(env)); + wreg(cs->accel->fd, HV_X86_RBX, RBX(env)); + wreg(cs->accel->fd, HV_X86_RCX, RCX(env)); + wreg(cs->accel->fd, HV_X86_RDX, RDX(env)); + wreg(cs->accel->fd, HV_X86_RSI, RSI(env)); + wreg(cs->accel->fd, HV_X86_RDI, RDI(env)); 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id n3-20020a05600c4f8300b004064288597bsm11904145wmq.30.2023.11.06.03.06.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:06:45 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Zhao Liu , Cameron Esfahani , Roman Bolshakov Subject: [PULL 27/60] target/i386/hvf: Rename 'X86CPU *x86_cpu' variable as 'cpu' Date: Mon, 6 Nov 2023 12:02:59 +0100 Message-ID: <20231106110336.358-28-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Follow the naming used by other files in target/i386/. No functional changes. Suggested-by: Zhao Liu Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Zhao Liu Message-Id: <20231020111136.44401-4-philmd@linaro.org> --- target/i386/hvf/x86_emu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 5b82e84778..3a3f0a50d0 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -665,7 +665,7 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode) void simulate_rdmsr(CPUX86State *env) { - X86CPU *x86_cpu = env_archcpu(env); + X86CPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env); uint32_t msr = ECX(env); uint64_t val = 0; @@ -675,10 +675,10 @@ void simulate_rdmsr(CPUX86State *env) val = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET); break; case MSR_IA32_APICBASE: - val = cpu_get_apic_base(x86_cpu->apic_state); + val = cpu_get_apic_base(cpu->apic_state); break; case MSR_IA32_UCODE_REV: - val = x86_cpu->ucode_rev; + val = cpu->ucode_rev; break; case MSR_EFER: val = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER); @@ -766,7 +766,7 @@ static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode) void simulate_wrmsr(CPUX86State *env) { - X86CPU *x86_cpu = env_archcpu(env); + X86CPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env); uint32_t msr = ECX(env); uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env); @@ -775,7 +775,7 @@ void simulate_wrmsr(CPUX86State *env) case MSR_IA32_TSC: break; case MSR_IA32_APICBASE: - cpu_set_apic_base(x86_cpu->apic_state, data); + cpu_set_apic_base(cpu->apic_state, data); break; case MSR_FSBASE: wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data); @@ -1419,8 +1419,8 @@ static void init_cmd_handler() void load_regs(CPUState *cs) { - X86CPU *x86_cpu = X86_CPU(cs); - CPUX86State *env = &x86_cpu->env; + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; int i = 0; RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX); @@ -1442,8 +1442,8 @@ void load_regs(CPUState *cs) void store_regs(CPUState *cs) { - X86CPU *x86_cpu = X86_CPU(cs); - CPUX86State *env = &x86_cpu->env; + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; int i = 0; wreg(cs->accel->fd, HV_X86_RAX, RAX(env)); From patchwork Mon Nov 6 11:03:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741328 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1025742wrr; Mon, 6 Nov 2023 03:14:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IEXnRtS4wq/Lh3MqkxxTteV06SIYCpxMraZk8BSteW8R17DxfC0AuxN7C/JHvGzWrw3+mKL X-Received: by 2002:a05:620a:bd3:b0:77a:6498:70b5 with SMTP id s19-20020a05620a0bd300b0077a649870b5mr10795831qki.3.1699269249756; Mon, 06 Nov 2023 03:14:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269249; cv=none; d=google.com; s=arc-20160816; b=khCLDGo4pMxF/yiN8CfEtyXQ/6/p2swau4264izd9IXkDN0rH2NhOxXOKyVJa+fdlX w0uThKqf+uczsltDR7AFX6WJnVoFL1UX2Ym/4H39oEUm6UyHEnIkA+NZg7w7W7j3/YoU W4qIPe10fZ4QYW13vXY52XKtrESAVGCt3y72zDbq4SoJ859wnh0hKdSbZaDBRBxDGjMv cmXreRbkhHQ5wavyOoyZn5YRphgzidmZlrsScUg2zYAHW7ixEU/qpIEQPCoR/5H1pdc0 18aau+fSUttJqhjnAE26N8asCPvAb/P+VOZbOwvTpXrso4UUu7uVISpMewMaT9rWfZOc AInA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+6pej+XFgeNy8hwy7UMk7tmyBIA+j/BAJUFV7Aiq4os=; fh=hOa8Um5OIpU84n/0Evp6ZcM8QvTrGFXBRf9CRDOiwMw=; b=XxbJoUY7ImZiPVH1S3yGESPW5ezcrn/wRwnKhmd1u7yRzrAWt41rabI82zciHa2AKg i283OFodqxgzJPoJtGnVF95xHIel208auJe8f5r3dpI0HIXdcia3+rYA3qm5RBR5TMm/ 0R3atp9rL9Ch5Cec6trDbyWHoQ0X0AbyRGFvPbppoC3Ab/JWYTrbwVA33WKljkhgStm2 aJSANRudS2RTboZpaHXNXBGpQj7bDxc3KKVPulCMEmmbpC4J2JTomXbwlZOIQI+BAIWt h/4VpdXBppmFXx+auhU5bKgn9NnoJh97m1NDf8r8F3rB+PcNm2Q8P8amaNmrgjy1mS2S PhNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="BF/h/iH5"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id r16-20020a05600c459000b003fefaf299b6sm11914693wmo.38.2023.11.06.03.06.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:06:52 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini , Marcelo Tosatti Subject: [PULL 28/60] target/i386/kvm: Correct comment in kvm_cpu_realize() Date: Mon, 6 Nov 2023 12:03:00 +0100 Message-ID: <20231106110336.358-29-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22a; envelope-from=philmd@linaro.org; helo=mail-lj1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20230918160257.30127-4-philmd@linaro.org> --- target/i386/kvm/kvm-cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index 56c72f3c45..9c791b7b05 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -37,6 +37,7 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp) * -> cpu_exec_realizefn(): * -> accel_cpu_common_realize() * kvm_cpu_realizefn() -> host_cpu_realizefn() + * -> cpu_common_realizefn() * -> check/update ucode_rev, phys_bits, mwait */ if (cpu->max_features) { From patchwork Mon Nov 6 11:03:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741380 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1037569wrr; Mon, 6 Nov 2023 03:45:48 -0800 (PST) X-Google-Smtp-Source: AGHT+IGVBWNEI5Lsjfjt2lquAybRg9bvTiXXPoyBcl8jTuVlAUT80i2DgQF+N94Lvz48W7rXsey6 X-Received: by 2002:a05:620a:2446:b0:778:e431:3ef1 with SMTP id h6-20020a05620a244600b00778e4313ef1mr13176287qkn.32.1699271148362; Mon, 06 Nov 2023 03:45:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699271148; cv=none; d=google.com; s=arc-20160816; b=nFnRu3jH/tWFM8iJMtV9NoYIPqC0Sx9Lu5HUD1nwTwUVkpdX6RFCEDvAgjUGMzavsc yrgyhk2WwD9i8nvvCKKN1QZzFw76rZT9BhWigu6mzCqascv7WNejg2H5OD/OA/h1o13B NVfypWbaciQBUBRjNXYQXqCQkO5tdY1MPcG3+to8w7gPnZnNXm+DBjh7L1DFeQUayEV4 ZZUsEcl//5CbonqK/AcJxcvD6VuMkVqnuZ5BvASzUUmPkhzNDGWLaRFEePMptZhwyy5P yabpw61Zre1KC11T+HlBAsRJ1mSakeINLYuBZ4twqVSpFQI9Fe0eeXdeQxBzQDmYZjxx GRPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=W+HrE2ba95t1ooYtGszc36ebWNEUF8WT6p6gpPtPmuY=; fh=u2yVCK9cQSeTYJlnjxvfEJjFMQIf6oB8a58h6nNnrSY=; b=u8IR/9Tf84F0RiAgi6WfImK88aUMSCosj1MpJ+7Fd0HqCSqQeHgNwNIEEWZMR3LFWn sFFZBqgHmPUvm4D7XkMi/e63ehTsthpDY0REeDtzvOO/EtDFx5EqXBul/tEKBSz5Vjj6 QgLG264fnBo4W3+aNYRlH+Qma1jF6Fkl3zCgIraNyL3ddN6j9GflctZoCA3++bICuLKj ACWFdr7BnxoEGO828FNDBWSytYeRPypDLu44ZW4PYoU0HR8qinSTkaC9prn3cNhyjw1o g7ci8KeO6wVDqJPUrPGyL2sX6td9dENYlMuWanme6YH/hkcZRDfMPfvQcFXOsvOEOPB9 gdJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fzyOWbWY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id f4-20020a5d6644000000b0032da49e18fasm9178802wrw.23.2023.11.06.03.06.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:06:58 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Dongli Zhang , Joe Jin , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , David Woodhouse , Juan Quintela , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 29/60] target/i386/monitor: synchronize cpu state for lapic info Date: Mon, 6 Nov 2023 12:03:01 +0100 Message-ID: <20231106110336.358-30-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Dongli Zhang While the default "info lapic" always synchronizes cpu state ... mon_get_cpu() -> mon_get_cpu_sync(mon, true) -> cpu_synchronize_state(cpu) -> ioctl KVM_GET_LAPIC (taking KVM as example) ... the cpu state is not synchronized when the apic-id is available as argument. The cpu state should be synchronized when apic-id is available. Otherwise the "info lapic " always returns stale data. Reference: https://lore.kernel.org/all/20211028155457.967291-19-berrange@redhat.com/ Cc: Joe Jin Signed-off-by: Dongli Zhang Reviewed-by: Daniel P. Berrangé Reviewed-by: David Woodhouse Message-ID: <20231030085336.2681386-1-armbru@redhat.com> Reviewed-by: Juan Quintela Message-ID: <20231026211938.162815-1-dongli.zhang@oracle.com> Signed-off-by: Philippe Mathieu-Daudé --- target/i386/monitor.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/i386/monitor.c b/target/i386/monitor.c index 6512846327..950ff9ccbc 100644 --- a/target/i386/monitor.c +++ b/target/i386/monitor.c @@ -28,6 +28,7 @@ #include "monitor/hmp-target.h" #include "monitor/hmp.h" #include "qapi/qmp/qdict.h" +#include "sysemu/hw_accel.h" #include "sysemu/kvm.h" #include "qapi/error.h" #include "qapi/qapi-commands-misc-target.h" @@ -654,7 +655,11 @@ void hmp_info_local_apic(Monitor *mon, const QDict *qdict) if (qdict_haskey(qdict, "apic-id")) { int id = qdict_get_try_int(qdict, "apic-id", 0); + cs = cpu_by_arch_id(id); + if (cs) { + cpu_synchronize_state(cs); + } } else { cs = mon_get_cpu(mon); } From patchwork Mon Nov 6 11:03:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741370 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1035906wrr; Mon, 6 Nov 2023 03:41:28 -0800 (PST) X-Google-Smtp-Source: AGHT+IGrTWYC5VKnEXXXXfyJ/iiY4eKldcEgrA0tckYZCPSFFRMgzwsB0xV4OAT7sT+rG5sH01lP X-Received: by 2002:ad4:5dc2:0:b0:66d:59da:d225 with SMTP id m2-20020ad45dc2000000b0066d59dad225mr31380544qvh.15.1699270887974; Mon, 06 Nov 2023 03:41:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699270887; cv=none; d=google.com; s=arc-20160816; b=tofIKQpEk9G7RcrR0AJ5nyMf38dxoXKmYx77QqQS68qRZfprrSnLo+MxchmTzrrgzu Z2LO2k5s40MmvphXt/ypWDURNhmt4fBpqP/A0cS/I0qnf4x5mWZFm+LMr4v4auQLl3ib Nv7wmhhezAjrjUay5ZgySVAZXvvt5FtEc3X2tjJ1nlTKR3Df6lejfPzAs8GMrCvKJGvo 1PvXSKP/+hrF4KkgzC+o6ljudx4F/kKW4EhcWQ0UAxxVRkvsAOIZXqjPTNDkVC1/K3KS 9vng8exYRQxd1w9AGl6yqxSlBArgXhh4Q9p+pnan3FYo2DFEbX5Kjq9D8+coJELLcCSv +eXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GyckcOuF1Bcu5rrRcor+Uzyh2YOL0vEJEmdAm/ud3/A=; fh=eAVF8L3gTrzFcyR1c1M/CxpOQ1Uk60TAxSM/jvMgJbA=; b=ZjB6i3UXXB44Xku6daUp+i236zid55H8DYqmfJRrNZokUAwnmYqYDNupue0NXjzb2X PJcuHylBbie28QnCdEXixpmUKZ4cDHsPWwE8yDqU0hjgJipQlf9S3ClOGVxFwjYdpqQd GHGN9Gle0wRuv91uCdbD7lGccWVV77m/w9By3kBkrZCen8ObgQjVMlOnZHqDoZ+ID4pi TbTV4TYR7DG/LWdrEcTAKfogf6+JQHcSiJG11M71udKeIvOGz5ZDK9PQE7xHmkHKJ5q0 Vqke6KEjwjxrxjSp4E3a8zPmqZ/LJ89JgJHMv4MpnShH6VtjFMd3XYhaEkBEPw8br83j 4e/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XXchG9ui; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id k18-20020a5d6d52000000b0032da4f70756sm9120501wri.5.2023.11.06.03.07.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:07:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-stable@nongnu.org, Sergey Evlashev , Richard Henderson , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 30/60] target/mips: Fix MSA BZ/BNZ opcodes displacement Date: Mon, 6 Nov 2023 12:03:02 +0100 Message-ID: <20231106110336.358-31-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The PC offset is *signed*. Cc: qemu-stable@nongnu.org Reported-by: Sergey Evlashev Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1624 Fixes: c7a9ef7517 ("target/mips: Introduce decode tree bindings for MSA ASE") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20230914085807.12241-1-philmd@linaro.org> --- target/mips/tcg/msa.decode | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 9575289195..4410e2a02e 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -31,8 +31,8 @@ @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i -@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3 -@bz ...... ... df:2 wt:5 sa:16 &msa_bz +@bz_v ...... ... .. wt:5 sa:s16 &msa_bz df=3 +@bz ...... ... df:2 wt:5 sa:s16 &msa_bz @elm_df ...... .... ...... ws:5 wd:5 ...... &msa_elm_df df=%elm_df n=%elm_n @elm ...... .......... ws:5 wd:5 ...... &msa_elm @vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0 From patchwork Mon Nov 6 11:03:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741363 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1032931wrr; Mon, 6 Nov 2023 03:33:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IFzzA5E3GBsG1kfXkoaC81ndkXnb8p04wHeJZyAZsKbygIk+fjx4nYxEUCfqLBIQFMPXpm2 X-Received: by 2002:a05:620a:4512:b0:777:2ac8:b434 with SMTP id t18-20020a05620a451200b007772ac8b434mr34049879qkp.72.1699270392744; Mon, 06 Nov 2023 03:33:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699270392; cv=none; d=google.com; s=arc-20160816; b=smEHi9NAE3VLSIjoQumfeNHTtwop8XDlN8lB/VifhIi5EQh36EoaAkTPw7k8kn6Slu e3AzdwzxXyiLsh+0ECkW7W83KcJN+jG7191jh+vYiNYra0SRuRGxuipf+HbVbmEotWBp lA5WGE0lHZ7nc2/798Gam4NNOO8K/+XEXAtcnG0UMAMd3WoXHjg/y+Xb/lyAJvYWuDEa MNWpeMFQsGtBdFZxAZcXFQsRvA/nmRfjKwooxxyz6R0aFOGh2T13FKnX/w/LszhMGud5 lKCx5f4C+IxTQh3TE9WU3msnHNiJ4redC8dXAuzS+uzNl/f7Vw0c64l00ARkXA5Q7isL VSHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ysTm3sVa8NXK5p6adWouAn7jMZtjrRCTYZ5tPCHuc7A=; fh=+nirhdWwjf37I7y6I55Kr3EGOSidkOifemtOvznTsu8=; b=xSKDFV758JNGYOsWH7q5OCwKgxf/4Niu0WV6t/EeLnQ563Ap3goPP6emozXdXFP+Nf K5D+6cR8F0ZhxjwpmqMGMfhkvbWsWM99Hkkm7grwn+sh7PswUfHcGFPaoZ/9VVg9nqrd adyNYtsTMgADoIv59mZsYpMiTg2tin43v3Ysrth2yi9D+poyOVIoseNi31mmBtUhZjLE dWKQ2tb+nTMgtyR06tJJ8I/rEfXdaFKmnuTQAn5ty6+YJOetH6lpCRFT4Ph2VNm4HxJF Q0Wvq9rwYT+zncigcawihCrmazmiPSqpelYDHdwithiO/9n+ewwamVaCy7HBPXTvrANf 7s5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SK9E1JI1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id jg2-20020a05600ca00200b004065daba6casm11958500wmb.46.2023.11.06.03.07.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:07:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-stable@nongnu.org, Richard Henderson , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 31/60] target/mips: Fix TX79 LQ/SQ opcodes Date: Mon, 6 Nov 2023 12:03:03 +0100 Message-ID: <20231106110336.358-32-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The base register address offset is *signed*. Cc: qemu-stable@nongnu.org Fixes: aaaa82a9f9 ("target/mips/tx79: Introduce LQ opcode (Load Quadword)") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20230914090447.12557-1-philmd@linaro.org> --- target/mips/tcg/tx79.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/tcg/tx79.decode b/target/mips/tcg/tx79.decode index 57d87a2076..578b8c54c0 100644 --- a/target/mips/tcg/tx79.decode +++ b/target/mips/tcg/tx79.decode @@ -24,7 +24,7 @@ @rs ...... rs:5 ..... .......... ...... &r sa=0 rt=0 rd=0 @rd ...... .......... rd:5 ..... ...... &r sa=0 rs=0 rt=0 -@ldst ...... base:5 rt:5 offset:16 &i +@ldst ...... base:5 rt:5 offset:s16 &i ########################################################################### From patchwork Mon Nov 6 11:03:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741344 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1027819wrr; Mon, 6 Nov 2023 03:19:39 -0800 (PST) X-Google-Smtp-Source: AGHT+IHRxcJwY/O1t54PRzERM3b75mwCw/otp5fj/E4XsUdr0ub5gMSJYAOGtGdRpNT5FBvjktLu X-Received: by 2002:a05:620a:448b:b0:778:9a19:da98 with SMTP id x11-20020a05620a448b00b007789a19da98mr33894384qkp.8.1699269578885; Mon, 06 Nov 2023 03:19:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269578; cv=none; d=google.com; s=arc-20160816; b=rl9iG8t5PJFF6VKZqIX6JtGA9G/20jVH0XCeQYtfjJdDLEHjhaoFD0mmCtVZaQN6B4 K6999F4fc1JF3yKadcWOfCS5RfJLmoviYYCUha2gEn3gtGRl9lGYCGrwCwctlmFX54Dy ilGpHbneFb3KwsCCGFDqFHjlIrpGGqPIjZWzOoBSgAB3CUkninURhKMikwrc1bjI9/Sp ZDLuqsma4C4QfWP1vxeFR6uRxLx0wwA00U1F4UyKzWXrh0Zzew6lG4kxPKuWHKiM4nqU IVAWs744Vmf/8t4hZsj5b/zEQZbj1mLXs4HsYo9Vw2xWZ/8OQFC0kQSNMO77c3WIR/P+ apZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=S8/5vIGDLKMGAXYMu1UZsIS0RjKQzcO4h+Duvu/oNU4=; fh=q9b78AFgRM1O2or92wExPmoPEBaJapvt1WsXQwq6grY=; b=0RJ1//DmJE5cjN2PJGP++0qOnIQJnhE5pMl1l/h4XaiRyIZZeCvyu4YX5FqEH0MY+h Se9bNgZe0+WlhBTgdi8rKXeNFAnKHMgiQm+xPinU4EOVW41OZY+BqxoIAo4XPqtGYP08 2NT4q6BJilx94ALX7t7D3sTi9FZg5PuapLbkPH61CHrah3fW4HrLDARf4B7EokHgL3Rj 66+5U1UCaXAp4VPIyZd3O4qxzC2UFU6qQ1pouX4iYK4flQq05cyNdue2crOlhGTwbCBF huHAza/0iOD8CIo2qfFf+VcGR6rLh5TBju7N2B3DGMpJvZ0bOy3Zxu3kzuW5H7vTqg/p 5nEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="T/Wo+Xn8"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id v9-20020a05600c470900b003feea62440bsm11701095wmo.43.2023.11.06.03.07.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:07:18 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Michael Tokarev , Daniel Henrique Barboza , Paolo Bonzini , Nicholas Piggin , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PULL 32/60] sysemu/kvm: Restrict kvmppc_get_radix_page_info() to ppc targets Date: Mon, 6 Nov 2023 12:03:04 +0100 Message-ID: <20231106110336.358-33-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=philmd@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org kvm_get_radix_page_info() is only defined for ppc targets (in target/ppc/kvm.c). The declaration is not useful in other targets, reduce its scope. Rename using the 'kvmppc_' prefix following other declarations from target/ppc/kvm_ppc.h. Suggested-by: Michael Tokarev Reviewed-by: Daniel Henrique Barboza Message-Id: <20231003070427.69621-2-philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- include/sysemu/kvm.h | 1 - target/ppc/kvm.c | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 80b69d88f6..d614878164 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -521,7 +521,6 @@ int kvm_set_one_reg(CPUState *cs, uint64_t id, void *source); * Returns: 0 on success, or a negative errno on failure. */ int kvm_get_one_reg(CPUState *cs, uint64_t id, void *target); -struct ppc_radix_page_info *kvm_get_radix_page_info(void); /* Notify resamplefd for EOI of specific interrupts. */ void kvm_resample_fd_notify(int gsi); diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index d0e2dcdc77..9b1abe2fc4 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -268,7 +268,7 @@ static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp) "KVM failed to provide the MMU features it supports"); } -struct ppc_radix_page_info *kvm_get_radix_page_info(void) +static struct ppc_radix_page_info *kvmppc_get_radix_page_info(void) { KVMState *s = KVM_STATE(current_accel()); struct ppc_radix_page_info *radix_page_info; @@ -2368,7 +2368,7 @@ static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data) } #if defined(TARGET_PPC64) - pcc->radix_page_info = kvm_get_radix_page_info(); + pcc->radix_page_info = kvmppc_get_radix_page_info(); if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) { /* From patchwork Mon Nov 6 11:03:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741347 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1028141wrr; Mon, 6 Nov 2023 03:20:33 -0800 (PST) X-Google-Smtp-Source: AGHT+IHr42dRW0R5TI7K7XrAlnaY4kFSvrLU/MhaOmn4DhDs6qztPAKduz12kAMkDAjNZF5CZYjQ X-Received: by 2002:a05:622a:138a:b0:41c:f729:8032 with SMTP id o10-20020a05622a138a00b0041cf7298032mr40669432qtk.63.1699269632925; Mon, 06 Nov 2023 03:20:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269632; cv=none; d=google.com; s=arc-20160816; b=o+wsgs7jxewFvswyI7gBSGBnsThYs6XZkkNMMfIJCA6/e+zkcPdLOFiUy2T3Cg8Cn5 Wn4o8T1ITX2ISMyfkrbz9J+BOg0hH5b0gIFCAdKnIq0DUEOHO19NvtAGAnRGjonXhAQ8 V6353pxAvg+gc2HG4CPRp0JR0eGu6h3bYpt39hGSyWas+Nxyg+2KUBTCm0F6zLciFU2V P7fOzk3NSECsKV305sz1AmvubJjS4V3lrfGy2e68pTiYPN6kU2t31qO4QrJ6AYdM/lMj ZO2+0QswoyahTF2A32+sUBVyHbgl74OZyU6czhJPut1a1V/vXpTE8v5Po3cMSy7OA12B PJqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2OUN8qI3wvvK+6EjwaYybG9IZ1pKduK7zbEAWLMDuTw=; fh=kxtIBrwY7v58V0MwHpEoArvHEW6OKvCH9QYtBCkoxeY=; b=BYvPAYh3/5Y7ltX6YfijliYZqc+Gbj6No+tI3WJyPFCrWqFoJi5aQ8VFxitlA3O35K JpKDh3xJRtcVtPuwlBUR3XH4F7ZMi3i3IRpyrU80IFiaHWAcBmXGjVRg/PnAFjJU7gNx 45YlmjMQiVeHABjcaVA8T3A5xXgo0k8qLdlnsEDmPQFxPDnLnw8wdZAMubBYAH4p70tn ksUjk0xNXJYEIw3OybhTyJFWgeh2MlnV1fEvbKGN0OWsSvavgVeLwEthwgeW9r1ib+o7 qYgYVMflOMfDET7Zs1hX1P6aDt4J98De4XW2jAnublDBEUE58rVZ8dHkulVLub3aspia ftIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cMd584eR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id j8-20020a05600c1c0800b004063977eccesm11981849wms.42.2023.11.06.03.07.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:07:25 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Michael Tokarev , Nicholas Piggin , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= Subject: [PULL 33/60] hw/ppc/e500: Restrict ppce500_init_mpic_kvm() to KVM Date: Mon, 6 Nov 2023 12:03:05 +0100 Message-ID: <20231106110336.358-34-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=philmd@linaro.org; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Inline and guard the single call to kvm_openpic_connect_vcpu() allows to remove kvm-stub.c. Reviewed-by: Michael Tokarev Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231003070427.69621-3-philmd@linaro.org> --- hw/ppc/e500.c | 4 ++++ target/ppc/kvm-stub.c | 19 ------------------- target/ppc/meson.build | 2 +- 3 files changed, 5 insertions(+), 20 deletions(-) delete mode 100644 target/ppc/kvm-stub.c diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index e04114fb3c..384226296b 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -834,6 +834,7 @@ static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, IrqLines *irqs, Error **errp) { +#ifdef CONFIG_KVM DeviceState *dev; CPUState *cs; @@ -854,6 +855,9 @@ static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, } return dev; +#else + g_assert_not_reached(); +#endif } static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, diff --git a/target/ppc/kvm-stub.c b/target/ppc/kvm-stub.c deleted file mode 100644 index b98e1d404f..0000000000 --- a/target/ppc/kvm-stub.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * QEMU KVM PPC specific function stubs - * - * Copyright Freescale Inc. 2013 - * - * Author: Alexander Graf - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - * - */ -#include "qemu/osdep.h" -#include "cpu.h" -#include "hw/ppc/openpic_kvm.h" - -int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs) -{ - return -EINVAL; -} diff --git a/target/ppc/meson.build b/target/ppc/meson.build index 97ceb6e7c0..eab4e3e1b3 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -30,7 +30,7 @@ gen = [ ] ppc_ss.add(when: 'CONFIG_TCG', if_true: gen) -ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c')) +ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c')) ppc_system_ss = ss.source_set() From patchwork Mon Nov 6 11:03:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741357 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1030807wrr; Mon, 6 Nov 2023 03:27:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IGJGxo6FfX40dQDamvKeTseM8VSXdEVXp9wwXToy+bdZFQR4ddPI/+LwEselhVvefCy855x X-Received: by 2002:ac8:5982:0:b0:410:60a4:ffc7 with SMTP id e2-20020ac85982000000b0041060a4ffc7mr37773217qte.10.1699270064077; Mon, 06 Nov 2023 03:27:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699270064; cv=none; d=google.com; s=arc-20160816; b=tZl0G/KuNqWJZ0JiyrPC2uAtwxXUS1rgtmnaq9VPPR2wHBWOHigSW8rIZI+StbKpgI B72XuAZRJ2Z32KqTWMNvtX0ooveXxiEytKskL/yfdAFFsEzV7tFHkUzaRXZlBNbLMMRf mrCHtkj7u4bWXLsDW1yutK2nutHITkmu1lULDTqyx5Xt/f++2u7+jgD4pjuF++MXD0vX +h+1dPHHQJtE2vPd45UkBaW36QMeUgvQAwZw25P+XuuuA/Hlqy6hFRQy1MTwde6S1gf6 890FPz5A+o0ftqdfo6yUK3uVHSrY8gOVb8aLaHIf3yhzqdicmB8nwewqVV4mYlxl5NfJ x/TA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Cb2SoP+Kcg9QwI4B3FcAYm9BYCwnPa3WzQeoNeejBGE=; fh=kxtIBrwY7v58V0MwHpEoArvHEW6OKvCH9QYtBCkoxeY=; b=PYOWu06Y7dQvog6fiDAWkUmeu41bPGsMe3hDYDikRMCcdWCMjAp/44hiYMdv48Ncej kU3hC1bpc4It4QKpZwu1g1l9OZV5zfI77v3J/SF8d7gpdrk+0PrB+oSkrLYhk/LPL3OZ sJeBm1IDUC9YMXO1KsbMeHLOQkhZs8aMrxtSaPfaBIgDC/JnKwdk02T9Q9lNITCQngxK AFeUU9Unq7FPmLf/unuQTtz5BUZd/Q0rvRcennhWs3TzkPbmzMPhP7wwDcU88SCrC/kO uIWdSvJ1lFonGKUE/2OT0Yf7QzRETmfiWIh5UerCZTpggw0a6kA4lUOiNlqlZj4+VBHC mzCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sai4HMIy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id f13-20020a05600c4e8d00b0040596352951sm11677086wmq.5.2023.11.06.03.07.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:07:31 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Michael Tokarev , Nicholas Piggin , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= Subject: [PULL 34/60] target/ppc: Restrict KVM objects to system emulation Date: Mon, 6 Nov 2023 12:03:06 +0100 Message-ID: <20231106110336.358-35-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CONFIG_KVM is always FALSE on user emulation, so 'kvm.c' won't be added to ppc_ss[] source set; direcly use the system specific ppc_system_ss[] source set. Reviewed-by: Michael Tokarev Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231003070427.69621-4-philmd@linaro.org> --- target/ppc/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/meson.build b/target/ppc/meson.build index eab4e3e1b3..0b89f9b89f 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -30,7 +30,6 @@ gen = [ ] ppc_ss.add(when: 'CONFIG_TCG', if_true: gen) -ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c')) ppc_system_ss = ss.source_set() @@ -46,6 +45,7 @@ ppc_system_ss.add(when: 'CONFIG_TCG', if_true: files( ), if_false: files( 'tcg-stub.c', )) +ppc_system_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) ppc_system_ss.add(when: 'TARGET_PPC64', if_true: files( 'compat.c', From patchwork Mon Nov 6 11:03:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741333 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1026001wrr; Mon, 6 Nov 2023 03:15:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IFXph+w86gWF5k/Ihd4REf275aCNwWWADUZld/8aZSeV/xuzdHPx/0Z6KppAaqUdLF50u7q X-Received: by 2002:a05:622a:1789:b0:41c:cc6d:bba with SMTP id s9-20020a05622a178900b0041ccc6d0bbamr33079737qtk.44.1699269300183; Mon, 06 Nov 2023 03:15:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269300; cv=none; d=google.com; s=arc-20160816; b=oBULry+UiW5iGVM+aTZyGNKUny0v2meXkckeM1PT87rpCcdrpNWQRADW9jReNdJj5V zEvANe/XYv4nYb+CAToKMNXd5ECP3dUH7Dy+lU+2oS1ikLfAjkUx+PjBWSEfKz02wAmP jOir910214F76ta/VBxn97yq/Nu9FMkQU2lVZiGs4TmloWJL6lVpTdjAUIyKaa8D0R56 SwkbocKATbwSdV/OBR/s1bKBrfbtGm8B9kwSmBo/O2+fqw1Qizm9u66Za/tPy9iUAAdu Y/N+n4UmSormmX51VU1DgnZZ/mZEH4A0/79JY9pITusYO/2de08Wa3pf/C4QYisZNWsm T82w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/8FQLEYTqFB9Ro3y1RtUGoGmFmjKyGG2i99735loRZ8=; fh=l0VZqEXHjAOAoKxAjE4HjirxxtGQta0klXTKiczTXSE=; b=ahcal09hyKfVdd3t7P0JFjCddSvsK5XQ7SsDAhIBipQbO3ojVS1HvUyb913rQaw5mM +q68XOamAPdhRBZrF2/yMjwVsP9kz4g61W3Kgj1jI1a2r6cbotB8zNibPObFktoDha90 +UCSZdBhF8G4NBH1paRAyrbrzzhR9RrqppcQYZyzmGVBoQcZVx+N9W/dPxVwPvgQT4Sj l4y4y7wOZU9rzP7TTiIPDFK/GawTE6xTL0DPQ+jZSflol1fJZ50UHMoWmGOESgkWCIVC rkVU0GSTqJlwr07AZTDCMJcyRtkRwUxi2oKgmAFIv78cKusu3nHdiM+lTWRlMsN6DQPm oqsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WF6E+sNX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id z13-20020a5d4d0d000000b0031ad5fb5a0fsm9131295wrt.58.2023.11.06.03.07.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:07:38 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Kevin Wolf , Daniel Henrique Barboza , Nicholas Piggin , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini Subject: [PULL 35/60] target/ppc: Prohibit target specific KVM prototypes on user emulation Date: Mon, 6 Nov 2023 12:03:07 +0100 Message-ID: <20231106110336.358-36-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org None of these target-specific prototypes should be used by user emulation. Remove their declaration there, so we get a compile failure if ever used (instead of having to deal with linker and its possible optimizations, such dead code removal). Suggested-by: Kevin Wolf Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Message-Id: <20231003070427.69621-5-philmd@linaro.org> --- target/ppc/kvm_ppc.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h index 6a4dd9c560..1975fb5ee6 100644 --- a/target/ppc/kvm_ppc.h +++ b/target/ppc/kvm_ppc.h @@ -13,6 +13,10 @@ #include "exec/hwaddr.h" #include "cpu.h" +#ifdef CONFIG_USER_ONLY +#error Cannot include kvm_ppc.h from user emulation +#endif + #ifdef CONFIG_KVM uint32_t kvmppc_get_tbfreq(void); From patchwork Mon Nov 6 11:03:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741349 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1028877wrr; Mon, 6 Nov 2023 03:22:33 -0800 (PST) X-Google-Smtp-Source: AGHT+IEztT8+PBk9kiHNk4OoYhtldhWCBhwHpstor4CUrz5J0qG5cGM70l2kEZNJ++EWA7ydiwnt X-Received: by 2002:a81:84d6:0:b0:583:307d:41bc with SMTP id u205-20020a8184d6000000b00583307d41bcmr10182734ywf.27.1699269753230; Mon, 06 Nov 2023 03:22:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269753; cv=none; d=google.com; s=arc-20160816; b=XmJARkomrJnzYZ4AW8lQdjnhl9NaQqrp55sRuAOzzEnag+JKY4zZWVvc2zeqbmrXOL 2DVMA6vM6ClHWSfRn28dxLdtj82ebK6v0bI/kJduhi11c3VEF4pLdJ19qE7Z5wtvWxJX 9cxBNxX7ztKMvROO8h746Z6wNlSjo7RJtchi17p7v14IRTXIFUwdSouMXRRLNYddUhWV ZJmXcij1nV5aYBtEcHsHdiRjcgCREoX0UfTuo07WmwNR2s6/lDw4jrh2n/fGI1zLtvw0 f9XDiG6em3VoJUKHp7Ufgm7zkw2yAhKFwW/Z9mBuF8VTykx9iPF9j9HPFEWMljK/GoLP Fq7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=95fjXxwoCEM5MPpLzleCUNmgt+EGYy9i69c6BsnNRfk=; fh=m4edQD1MqY6GbTcsot+ufBdLSBHZvJyU3muag/FpPiU=; b=FcP/KxdabHQxlDt7Ytxdf2r7xIwYPGAtTpYVeVkkaz3O6WCijSwroQK8i9yRRAO3X5 24/qae/RjSwdpbcRVKEWKHjhrc3gHSZqxmD1RdCdFucl1cPMBdNqY4qMDnTMZGETXWyT Ogh04TTGUi897hzhNJDGKg3b+jSxjKHTJS838731xLBa98M0L+m7CsaWecuqXuCNXBcS wj7JDdH7hses1CKN8GL+658bcpIC6QQolpo6b8BtcRwtrlnxzlryFndGWnBGYhgqmLtl +IvicxWAcwsfcCLlbXmOONArvKbNsdox70HCp1VFrKk3sXQzvklHSOZhGMOvVnmL/y74 8ECA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kERgngPf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id f20-20020a05600c43d400b003fbe4cecc3bsm11518827wmn.16.2023.11.06.03.07.43 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:07:44 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Chris Wulff , Marek Vasut Subject: [PULL 36/60] target/nios2: Create IRQs *after* accelerator vCPU is realized Date: Mon, 6 Nov 2023 12:03:08 +0100 Message-ID: <20231106110336.358-37-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Architecture specific hardware doesn't have a particular dependency on the accelerator vCPU (created with cpu_exec_realizefn), and can be initialized *after* the vCPU is realized. Doing so allows further generic API simplification (in few commits). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20230918160257.30127-12-philmd@linaro.org> --- target/nios2/cpu.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 15e499f828..a27732bf2b 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -199,14 +199,6 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev); Error *local_err = NULL; -#ifndef CONFIG_USER_ONLY - if (cpu->eic_present) { - qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1); - } else { - qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32); - } -#endif - cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); @@ -220,6 +212,14 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) /* We have reserved storage for cpuid; might as well use it. */ cpu->env.ctrl[CR_CPUID] = cs->cpu_index; +#ifndef CONFIG_USER_ONLY + if (cpu->eic_present) { + qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1); + } else { + qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32); + } +#endif + ncc->parent_realize(dev, errp); } From patchwork Mon Nov 6 11:03:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741354 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1029508wrr; Mon, 6 Nov 2023 03:24:17 -0800 (PST) X-Google-Smtp-Source: AGHT+IHWLFArJj26gaGeztx6WdHurJAeEQT0EMNnaNCibzSCFuyIZTV0WMwnuXn6gfVAd9R0p2Rr X-Received: by 2002:a05:620a:6009:b0:76f:1f8c:cc1b with SMTP id dw9-20020a05620a600900b0076f1f8ccc1bmr27423497qkb.78.1699269857744; Mon, 06 Nov 2023 03:24:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269857; cv=none; d=google.com; s=arc-20160816; b=qFt/cT+P9xEOwu4SozWbRZBertSOzEtO2m47Z2nhJuM96Yrwp+fmgwPzekkpAAOpoR zjk7keYeroCHQqIqsdxqJTReaeBAiqtWzm7lg6EtA9TRivHh69QzgYIp5tVajK7B43x3 lvEXsbCV1gvg6r4yACTGI09UZzaiwoXUQ2UTw8EdVAXmZ9mAy1QZydhy4/u2lknnpUDR 0C8meE5Q1RTg3S6jsAs8CCWHR8+314QVlP4aDQp0bBP9JGK+KTDiMZEsha5PAIc65Pbs y8ezbtVCeBPWno0zINE6w+ziGdnmGZiepCZkgBHQ7n6Sm/Ik5WfGLGYS7UmkbJRfVuqY T9pw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=pDLz44pMnS6BY17PlhPlXPTDOUKf2M5E2FKcksHeUks=; fh=KOGce46xVxY80adwH+7HYjmhGoI2WcTe1iPe5JKSVig=; b=u6n42anUO0KU+LGputEZCvl8NC9yGI8QmLfOzb/vZ5tsdAMkXCMXNjIunfshaVxk39 KbPqEyjZJRn6sIp9oH2JNLBpwOvGS4kQOgMLLAKYvv6nKdg2cBIZAWl2ySa5f8OxcGzE GGUO3+05FUDjWad4bzni1tXKKYodZwG+W1t8IzayhHJjXI65wWcETsXy+zRl6fYZ6aaR 2Qm74HpRIzyuUApxHG45I87DL8NM5t/kOD6hpOevGKqFyIiRGap22uzyXnE1nIgLkNT+ WxvlIFTn34vwQuAmTZ9dU72MUOztHpTAzH8qq9U53wpOlq57RcLmyL8VydXdy04Dmuux MDYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kslP9F7o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id k18-20020a5d6d52000000b0032da4f70756sm9122296wri.5.2023.11.06.03.07.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:07:51 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Gavin Shan Subject: [PULL 37/60] target/alpha: Tidy up alpha_cpu_class_by_name() Date: Mon, 6 Nov 2023 12:03:09 +0100 Message-ID: <20231106110336.358-38-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philmd@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-Id: <20230908112235.75914-2-philmd@linaro.org> --- target/alpha/cpu.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 51b7d8d1bf..fae2cb6ec7 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -142,13 +142,10 @@ static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model) typename = g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model); oc = object_class_by_name(typename); g_free(typename); - if (oc != NULL && object_class_is_abstract(oc)) { - oc = NULL; - } /* TODO: remove match everything nonsense */ - /* Default to ev67; no reason not to emulate insns by default. */ - if (!oc) { + if (!oc || object_class_is_abstract(oc)) { + /* Default to ev67; no reason not to emulate insns by default. */ oc = object_class_by_name(ALPHA_CPU_TYPE_NAME("ev67")); } From patchwork Mon Nov 6 11:03:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741326 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1025143wrr; Mon, 6 Nov 2023 03:12:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IF/5f6fa/XM4K1wQhEHLSxZsHoT1ZtpbDjt906iqKqM2IiQkz9/kdrzoiBDxLLbrkTu2nb3 X-Received: by 2002:a81:92c3:0:b0:5a7:ccf3:7163 with SMTP id j186-20020a8192c3000000b005a7ccf37163mr9283189ywg.15.1699269164007; Mon, 06 Nov 2023 03:12:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269163; cv=none; d=google.com; s=arc-20160816; b=FSbeC2G7m/qK2Mv06fNwgU9LzorO9p+enavA1XsYoy+TvZe/foVqvIU9u6QCfZbH7h nhFQ1lgntADFXeQZVahpVNzfzx2YuQiX4uiPawAovmApwAf1uILAjOH1p00f2jZ/qjbS jNL8FIy+TkV61KGzfXmNG9Hvi0ZVVli++RniMsAOCzuI7LSXrV1bHAXxVMuxWuqk9ycd K2KwMoEMvLRnRTmgKv5vrI1xqAbVwG66VdjjD8tYAJhBQaqrMCCUoBv1pDHWlI+ymszM /ZDTun94JKW+oH2C2Wd5BmD3lSoidGJlt44UneD3eZuC/H9TiRAQR+09r+cr2NqRtpmv M7PA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KMjbC2xJWHxNTrhQC1HW/27kz6qe7U3LIUpfEfCgflY=; fh=/8GwaBZBYonrwrhLOxysHeJExRWGv6RJbU6SL2XCshQ=; b=gdRU0FtM5TCKOh7BJ4iKZPJZ1qGIHTyXnDOAJ9Pejn3lwkMA5d3ulfeyj+s6j3gdOk CtknRujVz0w0u1t1DEibGS7y7zi0A4BOUI+dE440wzRhENElu5LCm3nWuz3uk5l8xX0A w8waErhVt757AWqmG94bvIde83wn26hJoTqvLLNbVSfJLxwPnGlvEzUD+2z53qNy/aiC 4llEgadsnQnQUvcrdJ+T+Q6VCF/dbRS4Y0LRNHAHlF488xotHIh9fKUg6kT39kzpH/KU N+ykC6dJ9kYmlfuJyrO4G2FjEiFsaej7LvA968jNfONq3zXKXe+txQCY9deZU7Nv+oy7 G5ng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="wc/dWq27"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id l4-20020a5d5604000000b0032f78feb826sm9106145wrv.104.2023.11.06.03.07.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:07:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Peter Maydell , Michael Rolnik , "Edgar E. Iglesias" , Brian Cain , Song Gao , Laurent Vivier , Stafford Horne , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Yoshinori Sato , Bastian Koppelmann , Max Filippov Subject: [PULL 38/60] hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() Date: Mon, 6 Nov 2023 12:03:10 +0100 Message-ID: <20231106110336.358-39-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Let CPUClass::class_by_name() handlers to return abstract classes, and filter them once in the public cpu_class_by_name() method. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20230908112235.75914-3-philmd@linaro.org> --- include/hw/core/cpu.h | 7 ++++--- hw/core/cpu-common.c | 14 +++++++++++--- target/alpha/cpu.c | 3 +-- target/arm/cpu.c | 3 +-- target/avr/cpu.c | 3 +-- target/cris/cpu.c | 3 +-- target/hexagon/cpu.c | 3 +-- target/loongarch/cpu.c | 3 +-- target/m68k/cpu.c | 3 +-- target/openrisc/cpu.c | 3 +-- target/riscv/cpu.c | 3 +-- target/rx/cpu.c | 6 +----- target/sh4/cpu.c | 3 --- target/tricore/cpu.c | 3 +-- target/xtensa/cpu.c | 3 +-- 15 files changed, 27 insertions(+), 36 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 6373aa4501..5d6f8dca43 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -102,7 +102,7 @@ struct SysemuCPUOps; /** * CPUClass: * @class_by_name: Callback to map -cpu command line model name to an - * instantiatable CPU type. + * instantiatable CPU type. * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. @@ -772,9 +772,10 @@ void cpu_reset(CPUState *cpu); * @typename: The CPU base type. * @cpu_model: The model string without any parameters. * - * Looks up a CPU #ObjectClass matching name @cpu_model. + * Looks up a concrete CPU #ObjectClass matching name @cpu_model. * - * Returns: A #CPUClass or %NULL if not matching class is found. + * Returns: A concrete #CPUClass or %NULL if no matching class is found + * or if the matching class is abstract. */ ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index baa6d28b64..d4112b8919 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -146,10 +146,18 @@ static bool cpu_common_has_work(CPUState *cs) ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model) { - CPUClass *cc = CPU_CLASS(object_class_by_name(typename)); + ObjectClass *oc; + CPUClass *cc; - assert(cpu_model && cc->class_by_name); - return cc->class_by_name(cpu_model); + oc = object_class_by_name(typename); + cc = CPU_CLASS(oc); + assert(cc->class_by_name); + assert(cpu_model); + oc = cc->class_by_name(cpu_model); + if (oc == NULL || object_class_is_abstract(oc)) { + return NULL; + } + return oc; } static void cpu_common_parse_features(const char *typename, char *features, diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index fae2cb6ec7..39cf841b3e 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -126,8 +126,7 @@ static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model) int i; oc = object_class_by_name(cpu_model); - if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL && - !object_class_is_abstract(oc)) { + if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL) { return oc; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index df6496b019..25e9d2ae7b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2401,8 +2401,7 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) oc = object_class_by_name(typename); g_strfreev(cpuname); g_free(typename); - if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || - object_class_is_abstract(oc)) { + if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU)) { return NULL; } return oc; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 14d8b9d1f0..44de1e18d1 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -157,8 +157,7 @@ static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) ObjectClass *oc; oc = object_class_by_name(cpu_model); - if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL || - object_class_is_abstract(oc)) { + if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL) { oc = NULL; } return oc; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index be4a44c218..675b73ac04 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -95,8 +95,7 @@ static ObjectClass *cris_cpu_class_by_name(const char *cpu_model) typename = g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model); oc = object_class_by_name(typename); g_free(typename); - if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) || - object_class_is_abstract(oc))) { + if (oc != NULL && !object_class_dynamic_cast(oc, TYPE_CRIS_CPU)) { oc = NULL; } return oc; diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 1adc11b713..9d1ffc3b4b 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -63,8 +63,7 @@ static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model) oc = object_class_by_name(typename); g_strfreev(cpuname); g_free(typename); - if (!oc || !object_class_dynamic_cast(oc, TYPE_HEXAGON_CPU) || - object_class_is_abstract(oc)) { + if (!oc || !object_class_dynamic_cast(oc, TYPE_HEXAGON_CPU)) { return NULL; } return oc; diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index ef1bf89dac..06d1b9bb95 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -648,8 +648,7 @@ static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) } } - if (object_class_dynamic_cast(oc, TYPE_LOONGARCH_CPU) - && !object_class_is_abstract(oc)) { + if (object_class_dynamic_cast(oc, TYPE_LOONGARCH_CPU)) { return oc; } return NULL; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 538d9473c2..11c7e0a790 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -111,8 +111,7 @@ static ObjectClass *m68k_cpu_class_by_name(const char *cpu_model) typename = g_strdup_printf(M68K_CPU_TYPE_NAME("%s"), cpu_model); oc = object_class_by_name(typename); g_free(typename); - if (oc != NULL && (object_class_dynamic_cast(oc, TYPE_M68K_CPU) == NULL || - object_class_is_abstract(oc))) { + if (oc != NULL && object_class_dynamic_cast(oc, TYPE_M68K_CPU) == NULL) { return NULL; } return oc; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index f5a3d5273b..1173260017 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -164,8 +164,7 @@ static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model); oc = object_class_by_name(typename); g_free(typename); - if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) || - object_class_is_abstract(oc))) { + if (oc != NULL && !object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU)) { return NULL; } return oc; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac4a6c7eec..63624e8b76 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -636,8 +636,7 @@ static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) oc = object_class_by_name(typename); g_strfreev(cpuname); g_free(typename); - if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || - object_class_is_abstract(oc)) { + if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU)) { return NULL; } return oc; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 4d0d3a0c8c..9cc9d9d15e 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -111,16 +111,12 @@ static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) char *typename; oc = object_class_by_name(cpu_model); - if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL && - !object_class_is_abstract(oc)) { + if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL) { return oc; } typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model); oc = object_class_by_name(typename); g_free(typename); - if (oc != NULL && object_class_is_abstract(oc)) { - oc = NULL; - } return oc; } diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 788e41fea6..a8ec98b134 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -152,9 +152,6 @@ static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s); oc = object_class_by_name(typename); - if (oc != NULL && object_class_is_abstract(oc)) { - oc = NULL; - } out: g_free(s); diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 5ca666ee12..034e01c189 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -132,8 +132,7 @@ static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model) typename = g_strdup_printf(TRICORE_CPU_TYPE_NAME("%s"), cpu_model); oc = object_class_by_name(typename); g_free(typename); - if (!oc || !object_class_dynamic_cast(oc, TYPE_TRICORE_CPU) || - object_class_is_abstract(oc)) { + if (!oc || !object_class_dynamic_cast(oc, TYPE_TRICORE_CPU)) { return NULL; } return oc; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index ea1dae7390..e20fe87bf2 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -141,8 +141,7 @@ static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model); oc = object_class_by_name(typename); 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id a1-20020a05600c348100b003fe1fe56202sm12104665wmq.33.2023.11.06.03.08.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:08:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang Subject: [PULL 39/60] exec/cpu: Have cpu_exec_realize() return a boolean Date: Mon, 6 Nov 2023 12:03:11 +0100 Message-ID: <20231106110336.358-40-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::230; envelope-from=philmd@linaro.org; helo=mail-lj1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Following the example documented since commit e3fe3988d7 ("error: Document Error API usage rules"), have cpu_exec_realizefn() return a boolean indicating whether an error is set or not. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20230918160257.30127-22-philmd@linaro.org> --- include/hw/core/cpu.h | 2 +- cpu-target.c | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5d6f8dca43..eb943efb8f 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1152,7 +1152,7 @@ G_NORETURN void cpu_abort(CPUState *cpu, const char *fmt, ...) /* $(top_srcdir)/cpu.c */ void cpu_class_init_props(DeviceClass *dc); void cpu_exec_initfn(CPUState *cpu); -void cpu_exec_realizefn(CPUState *cpu, Error **errp); +bool cpu_exec_realizefn(CPUState *cpu, Error **errp); void cpu_exec_unrealizefn(CPUState *cpu); void cpu_exec_reset_hold(CPUState *cpu); diff --git a/cpu-target.c b/cpu-target.c index 79363ae370..f3e1ad8bcd 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -131,13 +131,13 @@ const VMStateDescription vmstate_cpu_common = { }; #endif -void cpu_exec_realizefn(CPUState *cpu, Error **errp) +bool cpu_exec_realizefn(CPUState *cpu, Error **errp) { /* cache the cpu class for the hotpath */ cpu->cc = CPU_GET_CLASS(cpu); if (!accel_cpu_common_realize(cpu, errp)) { - return; + return false; } /* Wait until cpu initialization complete before exposing cpu. */ @@ -159,6 +159,8 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu); } #endif /* CONFIG_USER_ONLY */ + + return true; } void cpu_exec_unrealizefn(CPUState *cpu) From patchwork Mon Nov 6 11:03:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741366 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1033619wrr; Mon, 6 Nov 2023 03:35:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IGv1/Ca65EaNHgIE7r50u69ErxbHh1NesroLtFeoepHhTCIu9yQu1d8V2QwqlYHBh5TQ1fM X-Received: by 2002:a05:6214:1d27:b0:66d:a1f8:38da with SMTP id f7-20020a0562141d2700b0066da1f838damr35262314qvd.33.1699270509330; Mon, 06 Nov 2023 03:35:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699270509; cv=none; d=google.com; s=arc-20160816; b=Vx8U91JXX83f/N6XEwU89ut3J/xVX1kh0W3jCxA143vM5e435gtes5rCoww1ttU+KQ MBkcK3tbogyVnFSDk6evA42r+4hN+CAdlyS6sqzy+L121rVLB9JZfmza1irHARu6F8jO vcgtAwrDBwIxT/yvOqDQk6qZ5fUYMIeClluUI804LW2lilkftR4GZJ2ktRS6Ycaz+562 0g7uTjf/8kNYpoXOUjzgL8eJlQKl+inskfG+UARtfwJhTjgqZRPbDHl0pU7YoYHHh1qM nbJLPYrYm1b0bXDG5nPlaFMbs5+mJPz/d3Nxiun+e2S3m2Ln7k8g7HsWQERSXNvjrZQE C1XA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1c+BV5Tpk9NJdk/9uGPTtpoehyOljryZgDubWA0xkSQ=; fh=NGV8uWnFsrZtmxILs5xalLPeZUcUP259BieRNCJqy3Q=; b=tDbT6MMBQBnz60wRXtubZo8lWPumpckGBmZe6VYGRObxYhszdRrIY/xTYT4tcWdZkp ElF0gRHyui+KD8HE9JLyYBZPjuKRKTLpKNMlDZcx785K5Jq4VHJ4KLrktCD2AdWbhILl Ls4tPTr6uUK3zb2sm9tHQg7NzHGw+J3yrp5JJHkSxUrywfnrabNO9ruXwEVRgGWUDVcI E9Zc9ExhqGsAsM1IEdtiSsokfYdzqlABBUQpksyRoik525Xi4KBrnsR5j/7NshJ1uKY8 sHBWXo7pekf4obaMORGT6eW163grDfD2+4dI7ox6JsI1AaXTaBmC8jDrJEU/Iw1S8TUS HHpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="zJKWiuj/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id h16-20020a05600004d000b0032dbf99bf4fsm9290025wri.89.2023.11.06.03.08.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:08:13 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Ani Sinha , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Laurent Vivier , David Hildenbrand , Thomas Huth , Ilya Leoshkevich Subject: [PULL 40/60] hw/cpu: Clean up global variable shadowing Date: Mon, 6 Nov 2023 12:03:12 +0100 Message-ID: <20231106110336.358-41-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Fix: hw/core/machine.c:1302:22: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] const CPUArchId *cpus = possible_cpus->cpus; ^ hw/core/numa.c:69:17: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] uint16List *cpus = NULL; ^ hw/acpi/aml-build.c:2005:20: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] CPUArchIdList *cpus = ms->possible_cpus; ^ hw/core/machine-smp.c:77:14: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] unsigned cpus = config->has_cpus ? config->cpus : 0; ^ include/hw/core/cpu.h:589:17: note: previous declaration is here extern CPUTailQ cpus; ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Ani Sinha Message-Id: <20231010115048.11856-2-philmd@linaro.org> --- include/hw/core/cpu.h | 8 ++++---- cpu-common.c | 6 +++--- linux-user/main.c | 2 +- target/s390x/cpu_models.c | 2 +- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index eb943efb8f..77893d7b81 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -586,13 +586,13 @@ static inline CPUArchState *cpu_env(CPUState *cpu) } typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; -extern CPUTailQ cpus; +extern CPUTailQ cpus_queue; -#define first_cpu QTAILQ_FIRST_RCU(&cpus) +#define first_cpu QTAILQ_FIRST_RCU(&cpus_queue) #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node) -#define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node) +#define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus_queue, node) #define CPU_FOREACH_SAFE(cpu, next_cpu) \ - QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu) + QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus_queue, node, next_cpu) extern __thread CPUState *current_cpu; diff --git a/cpu-common.c b/cpu-common.c index 45c745ecf6..c81fd72d16 100644 --- a/cpu-common.c +++ b/cpu-common.c @@ -73,7 +73,7 @@ static int cpu_get_free_index(void) return max_cpu_index; } -CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus); +CPUTailQ cpus_queue = QTAILQ_HEAD_INITIALIZER(cpus_queue); static unsigned int cpu_list_generation_id; unsigned int cpu_list_generation_id_get(void) @@ -90,7 +90,7 @@ void cpu_list_add(CPUState *cpu) } else { assert(!cpu_index_auto_assigned); } - QTAILQ_INSERT_TAIL_RCU(&cpus, cpu, node); + QTAILQ_INSERT_TAIL_RCU(&cpus_queue, cpu, node); cpu_list_generation_id++; } @@ -102,7 +102,7 @@ void cpu_list_remove(CPUState *cpu) return; } - QTAILQ_REMOVE_RCU(&cpus, cpu, node); + QTAILQ_REMOVE_RCU(&cpus_queue, cpu, node); cpu->cpu_index = UNASSIGNED_CPU_INDEX; cpu_list_generation_id++; } diff --git a/linux-user/main.c b/linux-user/main.c index 0c23584a96..0cdaf30d34 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -156,7 +156,7 @@ void fork_end(int child) Discard information about the parent threads. */ CPU_FOREACH_SAFE(cpu, next_cpu) { if (cpu != thread_cpu) { - QTAILQ_REMOVE_RCU(&cpus, cpu, node); + QTAILQ_REMOVE_RCU(&cpus_queue, cpu, node); } } qemu_init_cpu_list(); diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index 4dead48650..5c455d00c0 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -757,7 +757,7 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, const S390CPUDef *def = s390_find_cpu_def(type, gen, ec_ga, NULL); g_assert(def); - g_assert(QTAILQ_EMPTY_RCU(&cpus)); + g_assert(QTAILQ_EMPTY_RCU(&cpus_queue)); /* build the CPU model */ s390_qemu_cpu_model.def = def; From patchwork Mon Nov 6 11:03:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741330 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1025802wrr; Mon, 6 Nov 2023 03:14:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IFPZ15ehR6UQaTD09hYwWlwyA9LgabTszcdRuizF3KVnnBx4PSVteh2W5TAQJ7qpxo/asNS X-Received: by 2002:a67:a603:0:b0:45d:9d27:215c with SMTP id p3-20020a67a603000000b0045d9d27215cmr6535794vse.1.1699269260362; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id j19-20020a05600c1c1300b004060f0a0fd5sm11862251wms.13.2023.11.06.03.08.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:08:20 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Ani Sinha Subject: [PULL 41/60] hw/loader: Clean up global variable shadowing in rom_add_file() Date: Mon, 6 Nov 2023 12:03:13 +0100 Message-ID: <20231106110336.358-42-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Fix: hw/core/loader.c:1073:27: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] bool option_rom, MemoryRegion *mr, ^ include/sysemu/sysemu.h:57:22: note: previous declaration is here extern QEMUOptionRom option_rom[MAX_OPTION_ROMS]; ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Ani Sinha Message-Id: <20231010115048.11856-3-philmd@linaro.org> --- include/hw/loader.h | 2 +- hw/core/loader.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/hw/loader.h b/include/hw/loader.h index c4c14170ea..8685e27334 100644 --- a/include/hw/loader.h +++ b/include/hw/loader.h @@ -272,7 +272,7 @@ void pstrcpy_targphys(const char *name, ssize_t rom_add_file(const char *file, const char *fw_dir, hwaddr addr, int32_t bootindex, - bool option_rom, MemoryRegion *mr, AddressSpace *as); + bool has_option_rom, MemoryRegion *mr, AddressSpace *as); MemoryRegion *rom_add_blob(const char *name, const void *blob, size_t len, size_t max_len, hwaddr addr, const char *fw_file_name, diff --git a/hw/core/loader.c b/hw/core/loader.c index 4dd5a71fb7..7f0cbfb214 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -1070,7 +1070,7 @@ static void *rom_set_mr(Rom *rom, Object *owner, const char *name, bool ro) ssize_t rom_add_file(const char *file, const char *fw_dir, hwaddr addr, int32_t bootindex, - bool option_rom, MemoryRegion *mr, + bool has_option_rom, MemoryRegion *mr, AddressSpace *as) { MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); @@ -1139,7 +1139,7 @@ ssize_t rom_add_file(const char *file, const char *fw_dir, basename); snprintf(devpath, sizeof(devpath), "/rom@%s", fw_file_name); - if ((!option_rom || mc->option_rom_has_mr) && mc->rom_file_has_mr) { + if ((!has_option_rom || mc->option_rom_has_mr) && mc->rom_file_has_mr) { data = rom_set_mr(rom, OBJECT(fw_cfg), devpath, true); } else { data = rom->data; From patchwork Mon Nov 6 11:03:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741348 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1028512wrr; Mon, 6 Nov 2023 03:21:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IHmqRnGnRGmxdjrisuMpgTbJV8JalEWSoz4/KggBkLkS8FsQo1nMnkz6XOAslsGBemp76x1 X-Received: by 2002:a05:622a:cf:b0:418:111e:790f with SMTP id p15-20020a05622a00cf00b00418111e790fmr35797771qtw.65.1699269695801; Mon, 06 Nov 2023 03:21:35 -0800 (PST) ARC-Seal: i=1; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id m1-20020a056000180100b0031980783d78sm9136370wrh.54.2023.11.06.03.08.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:08:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Bernhard Beschow , Markus Armbruster , Richard Henderson , =?utf-8?q?Herv=C3=A9_Pous?= =?utf-8?q?sineau?= Subject: [PULL 42/60] hw/isa/i82378: Propagate error if PC_SPEAKER device creation failed Date: Mon, 6 Nov 2023 12:03:14 +0100 Message-ID: <20231106110336.358-43-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In commit 40f8214fcd ("hw/audio/pcspk: Inline pcspk_init()") we neglected to give a change to the caller to handle failed device creation cleanly. Respect the caller API contract and propagate the error if creating the PC_SPEAKER device ever failed. This avoid yet another bad API use to be taken as example and copy / pasted all over the code base. Reported-by: Bernhard Beschow Suggested-by: Markus Armbruster Reviewed-by: Richard Henderson Reviewed-by: Bernhard Beschow Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231020171509.87839-5-philmd@linaro.org> --- hw/isa/i82378.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/isa/i82378.c b/hw/isa/i82378.c index 79ffbb52a0..203b92c264 100644 --- a/hw/isa/i82378.c +++ b/hw/isa/i82378.c @@ -105,7 +105,9 @@ static void i82378_realize(PCIDevice *pci, Error **errp) /* speaker */ pcspk = isa_new(TYPE_PC_SPEAKER); object_property_set_link(OBJECT(pcspk), "pit", OBJECT(pit), &error_fatal); - isa_realize_and_unref(pcspk, isabus, &error_fatal); + if (!isa_realize_and_unref(pcspk, isabus, errp)) { + return; + } /* 2 82C37 (dma) */ isa_create_simple(isabus, "i82374"); From patchwork Mon Nov 6 11:03:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741343 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1027596wrr; Mon, 6 Nov 2023 03:19:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IHxgFVEKA6Z31ZuzgduMuEAiRQriX9YuIUyUF+qnvVzwRMpJ5msJG+jPctXCGw2CZSk4SOI X-Received: by 2002:a25:bf8c:0:b0:d9a:3c58:6ba9 with SMTP id l12-20020a25bf8c000000b00d9a3c586ba9mr25158509ybk.44.1699269540730; Mon, 06 Nov 2023 03:19:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269540; cv=none; d=google.com; s=arc-20160816; b=GwM5Ymx1S1C1JFln3y1/hjy4x89GQtsESBPTmnM7nJCd9sCFFDooCK5AHXKQu7mbCG dXW2yGHsb3L5nHLaVfMCdHe2LpEOCQjMIFB2Qxi3QgFk6NM/+OFZzJEwiS2PlJj/crMe W0AiTugjryhJZxmXuE/d3UKb+GRwQnTSvaWANv60wJTpCzolGiJ8wxNGuzby9sAJKvOb gfTcsz/hnHciHaXXyne8dRoa4N5o8pnzRll0mOQrhCkPqfr0PVu3+zh4rcXGwl3X3ao7 kQABE7iDQ/1QX/C2LKiBnhXV069ccNR1hM4OEiXh3eEl8cNJuSqChYWMj3InUX5O/ZGK Mv1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=pKMRzxqRYnKl/hVlIV0E2OCjWVD0Ib40S0FzpaLqDMw=; fh=L/qhuroVb3tR3NWg0+vDnGF1gMzkfjqMVSG/Df3vR+k=; b=egrUpBHrJj6whhplTYyt0NUB2tNx9DqPQlOvpaq3aKf/s/EAKArAIwHqFiJh5edHya 5vZkX8qPga+XCWK1tPGJPQQIaEb1jF8vrhzh81fBBmE9o1Z5N3iurt2AGPcT9VNYqYvF yBZ8mwhD6X/kp1UPXv40WXUPRiMvQZjwfTnSKTirZ2PobCP9Z2Z5sear6UEU484sSO2q LdMyw9P8c0vGL05lErwlvUM790Ad7dofEdeetqFsS9m5mI7neQ+fGF+RV0vOhEquB+x7 JmlYViygE0tSM2X0YIRF+IzHhLKcG76SvfNw4zaFP1ZTfaQr1KEFiTA1WcQLPq9/2eEy 5UCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NKSYDOvu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tsirkin" , Marcel Apfelbaum Subject: [PULL 43/60] hw/i386: Fix comment style in topology.h Date: Mon, 6 Nov 2023 12:03:15 +0100 Message-ID: <20231106110336.358-44-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=philmd@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Zhao Liu For function comments in this file, keep the comment style consistent with other files in the directory. Signed-off-by: Zhao Liu Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Yanan Wang Reviewed-by: Xiaoyao Li Reviewed-by: Babu Moger Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin Message-ID: <20231024090323.1859210-2-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/i386/topology.h | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 380cb27ded..d4eeb7ab82 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -24,7 +24,8 @@ #ifndef HW_I386_TOPOLOGY_H #define HW_I386_TOPOLOGY_H -/* This file implements the APIC-ID-based CPU topology enumeration logic, +/* + * This file implements the APIC-ID-based CPU topology enumeration logic, * documented at the following document: * Intel® 64 Architecture Processor Topology Enumeration * http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/ @@ -41,7 +42,8 @@ #include "qemu/bitops.h" -/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support +/* + * APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support */ typedef uint32_t apic_id_t; @@ -58,8 +60,7 @@ typedef struct X86CPUTopoInfo { unsigned threads_per_core; } X86CPUTopoInfo; -/* Return the bit width needed for 'count' IDs - */ +/* Return the bit width needed for 'count' IDs */ static unsigned apicid_bitwidth_for_count(unsigned count) { g_assert(count >= 1); @@ -67,15 +68,13 @@ static unsigned apicid_bitwidth_for_count(unsigned count) return count ? 32 - clz32(count) : 0; } -/* Bit width of the SMT_ID (thread ID) field on the APIC ID - */ +/* Bit width of the SMT_ID (thread ID) field on the APIC ID */ static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info) { return apicid_bitwidth_for_count(topo_info->threads_per_core); } -/* Bit width of the Core_ID field - */ +/* Bit width of the Core_ID field */ static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info) { return apicid_bitwidth_for_count(topo_info->cores_per_die); @@ -87,8 +86,7 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info) return apicid_bitwidth_for_count(topo_info->dies_per_pkg); } -/* Bit offset of the Core_ID field - */ +/* Bit offset of the Core_ID field */ static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info) { return apicid_smt_width(topo_info); @@ -100,14 +98,14 @@ static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info) return apicid_core_offset(topo_info) + apicid_core_width(topo_info); } -/* Bit offset of the Pkg_ID (socket ID) field - */ +/* Bit offset of the Pkg_ID (socket ID) field */ static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info) { return apicid_die_offset(topo_info) + apicid_die_width(topo_info); } -/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID +/* + * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID * * The caller must make sure core_id < nr_cores and smt_id < nr_threads. */ @@ -120,7 +118,8 @@ static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info, topo_ids->smt_id; } -/* Calculate thread/core/package IDs for a specific topology, +/* + * Calculate thread/core/package IDs for a specific topology, * based on (contiguous) CPU index */ static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info, @@ -137,7 +136,8 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info, topo_ids->smt_id = cpu_index % nr_threads; } -/* Calculate thread/core/package IDs for a specific topology, +/* + * Calculate thread/core/package IDs for a specific topology, * based on APIC ID */ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, @@ -155,7 +155,8 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, topo_ids->pkg_id = apicid >> apicid_pkg_offset(topo_info); } -/* Make APIC ID for the CPU 'cpu_index' +/* + * Make APIC ID for the CPU 'cpu_index' * * 'cpu_index' is a sequential, contiguous ID for the CPU. */ From patchwork Mon Nov 6 11:03:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741324 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1024169wrr; Mon, 6 Nov 2023 03:10:28 -0800 (PST) X-Google-Smtp-Source: AGHT+IEDWItBRJb7tUzTypWZP7pCrLfrWd//WmsHYhxKMwN+64KN+BRpDuarpv3Xlw9m/MRzFehh X-Received: by 2002:a05:622a:110e:b0:415:1804:d9ee with SMTP id e14-20020a05622a110e00b004151804d9eemr12932703qty.16.1699269028062; Mon, 06 Nov 2023 03:10:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269028; cv=none; d=google.com; s=arc-20160816; b=qI1yaPpQ1wupkJRveJ+qK6E8k055CR9r9jBNRlMMKOmQbns+OS4P9yD2y84OjB90Hj T8p0Y38roHbnfjOJy/ThSiOHgx2oz9npprzjzIfd5jx+wIcSqwC/ZRi4U35sXY8eAziW 5m5EulIH7+hU8QME78K7DlL95qaKQ9ZrZhPJ4dySdHy09ybGryQ1lC0/WbRQSAjgUQiM WXhecEn3cmH22VD1wJvp0FkpZpDhdf6u5L5ziwFgTVDtfdrEqmfkJER0MwSi2z0T6yY+ 8EOd7wDtFrY97NlxVEJExBFQb1F3cTW0E5H/WuLqUPJtu9x1HpU0/vRBMaNULxK2X+Bt k5lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Osm9Rqk6Yz1bOcmZt0pCvMMd/TH5Mg1H8su36lKkY04=; fh=peUR+mHhwMfdoRcAtzcFE11OaVaDPRqJWHoUvEpmNtA=; b=XR4Wal8rC4jkHQgZFzN1nNVRXebBPkuyKyiVmYxMfLsC3Rf36Im0riKRPewDfjha5G QJGc/6IYV1VPIOQF+t14fMOUImjw2Rh2ggFqsCQbgBHzlB651bZwvQR4BL9DcKUl0PMn RfuV/hx7FwUpGQiLNhlahkv9FZHmdoyHMPXHB6rdV2AgeUPT+g1Ce/u6AHhzWFeJELqu AUTrwF+aegOBmkG6KFs9hvsXcRzUcaw248rmKQL6KyhBnwf46pgrARs2OFrRUeltY58P lV1Svfjx96rP5ovn1QVQaXiK6PIFTUjyNygCdgWW6b/n264rpzhQjsj9Z9e2VTsGqfGx zqlA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iGOp2Xdk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id u7-20020a05600c138700b0040836519dd9sm11912962wmf.25.2023.11.06.03.08.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:08:40 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Zhao Liu , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Babu Moger , Yongwei Ma , "Michael S . Tsirkin" , Thomas Huth , Marcel Apfelbaum Subject: [PULL 44/60] tests/unit: Rename test-x86-cpuid.c to test-x86-topo.c Date: Mon, 6 Nov 2023 12:03:16 +0100 Message-ID: <20231106110336.358-45-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Zhao Liu The tests in this file actually test the APIC ID combinations. Rename to test-x86-topo.c to make its name more in line with its actual content. Signed-off-by: Zhao Liu Reviewed-by: Philippe Mathieu-Daudé Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin Reviewed-by: Thomas Huth Message-ID: <20231024090323.1859210-3-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 2 +- tests/unit/{test-x86-cpuid.c => test-x86-topo.c} | 2 +- tests/unit/meson.build | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) rename tests/unit/{test-x86-cpuid.c => test-x86-topo.c} (99%) diff --git a/MAINTAINERS b/MAINTAINERS index 8e8a7d5be5..126cddd285 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1772,7 +1772,7 @@ F: include/hw/southbridge/ich9.h F: include/hw/southbridge/piix.h F: hw/isa/apm.c F: include/hw/isa/apm.h -F: tests/unit/test-x86-cpuid.c +F: tests/unit/test-x86-topo.c F: tests/qtest/test-x86-cpuid-compat.c PC Chipset diff --git a/tests/unit/test-x86-cpuid.c b/tests/unit/test-x86-topo.c similarity index 99% rename from tests/unit/test-x86-cpuid.c rename to tests/unit/test-x86-topo.c index bfabc0403a..2b104f86d7 100644 --- a/tests/unit/test-x86-cpuid.c +++ b/tests/unit/test-x86-topo.c @@ -1,5 +1,5 @@ /* - * Test code for x86 CPUID and Topology functions + * Test code for x86 APIC ID and Topology functions * * Copyright (c) 2012 Red Hat Inc. * diff --git a/tests/unit/meson.build b/tests/unit/meson.build index f33ae64b8d..0dbe32ba9b 100644 --- a/tests/unit/meson.build +++ b/tests/unit/meson.build @@ -21,8 +21,8 @@ tests = { 'test-opts-visitor': [testqapi], 'test-visitor-serialization': [testqapi], 'test-bitmap': [], - # all code tested by test-x86-cpuid is inside topology.h - 'test-x86-cpuid': [], + # all code tested by test-x86-topo is inside topology.h + 'test-x86-topo': [], 'test-cutils': [], 'test-div128': [], 'test-shift128': [], From patchwork Mon Nov 6 11:03:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741352 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1029103wrr; Mon, 6 Nov 2023 03:23:05 -0800 (PST) X-Google-Smtp-Source: AGHT+IF52YeOsc7BXpmyH0GWyVF924mf9ybLuZTB2OOphNXzjIgrivqibV+OGmkDcwUpMFT/axgf X-Received: by 2002:a9d:6ac3:0:b0:6bb:1071:ea72 with SMTP id m3-20020a9d6ac3000000b006bb1071ea72mr27274221otq.36.1699269784767; Mon, 06 Nov 2023 03:23:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269784; cv=none; d=google.com; s=arc-20160816; b=uSq0iae1myc68Il+l/1j0nJk3KaY5rGY867zspDFEde2b4pPMre3OWbEVMmygHTZdI 4SLHWyIzO6pMUbPxO/ZquFdhoASvhBp0BINktN/yJQy4P+ySY4TCFMXxBh1Z/agU1wwp d6idwwgBMAXgP+NlsWfHWamK//0r9o4vflh+zcl0Bd30iIQQBGaIFVd7cIqh98HKCou7 RAxVFriqGC1U3WNUbloPtZZsgwvRNfHo1JaVJopvUU3tTfefPjq5NCD6a/S4SnL4gLuw WLAAX2HmX8du3DwfXhbnnEBf/GeI7R7rUseld3tXzOmro5WACC7ZJMeBD0OqYqT96v7F RgEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0yFelocR66jYXowauowrhR0mUeB3U99cidSOqtYw+Cg=; fh=uPeuKhg1mH9zdni2B1WgSqdekR1mTgg7x5s27WSu2zA=; b=MrlSw8iyDvRPRDCzjdNRjrUKp2vEIQKdLNvHOv8xvLbkZGTO+AHqYgfccoBO+F+mx6 +jZ7O0XdliUV4oYK+zGRtFA37lUy/61zEd9Zrwc8ejg0HV0oLd3QOO6vVzqFAvlxRNoe EPUU7mRY87QwvEHGVrUb9aDtnN8lvBOU8m+e6bE259jDVQDs5X7b89vQyscjB72B2O87 uxMbpvW2KQF8g96GU6gFdUmQeCypXl5dj74op5BSm0Lw2QVHAWgUa5P6zuMAqmX9UXsk UU08Z3XaNnyy7Xbd0RjN+hXyfYVIkPNu8gBFRJJ9VRFAI9kKRsCk2v1NNzD95YkL7LFH 9pBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VMAjPMAS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id g8-20020a5d4888000000b0032f7cc56509sm1544640wrq.98.2023.11.06.03.08.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:08:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Zhuocheng Ding , Zhao Liu , Babu Moger , Yongwei Ma , "Michael S . Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Paolo Bonzini , Richard Henderson Subject: [PULL 45/60] system/cpus: Fix CPUState.nr_cores' calculation Date: Mon, 6 Nov 2023 12:03:17 +0100 Message-ID: <20231106110336.358-46-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Zhuocheng Ding >From CPUState.nr_cores' comment, it represents "number of cores within this CPU package". After 003f230e37d7 ("machine: Tweak the order of topology members in struct CpuTopology"), the meaning of smp.cores changed to "the number of cores in one die", but this commit missed to change CPUState.nr_cores' calculation, so that CPUState.nr_cores became wrong and now it misses to consider numbers of clusters and dies. At present, only i386 is using CPUState.nr_cores. But as for i386, which supports die level, the uses of CPUState.nr_cores are very confusing: Early uses are based on the meaning of "cores per package" (before die is introduced into i386), and later uses are based on "cores per die" (after die's introduction). This difference is due to that commit a94e1428991f ("target/i386: Add CPUID.1F generation support for multi-dies PCMachine") misunderstood that CPUState.nr_cores means "cores per die" when calculated CPUID.1FH.01H:EBX. After that, the changes in i386 all followed this wrong understanding. With the influence of 003f230e37d7 and a94e1428991f, for i386 currently the result of CPUState.nr_cores is "cores per die", thus the original uses of CPUState.cores based on the meaning of "cores per package" are wrong when multiple dies exist: 1. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.01H:EBX[bits 23:16] is incorrect because it expects "cpus per package" but now the result is "cpus per die". 2. In cpu_x86_cpuid() of target/i386/cpu.c, for all leaves of CPUID.04H: EAX[bits 31:26] is incorrect because they expect "cpus per package" but now the result is "cpus per die". The error not only impacts the EAX calculation in cache_info_passthrough case, but also impacts other cases of setting cache topology for Intel CPU according to cpu topology (specifically, the incoming parameter "num_cores" expects "cores per package" in encode_cache_cpuid4()). 3. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.0BH.01H:EBX[bits 15:00] is incorrect because the EBX of 0BH.01H (core level) expects "cpus per package", which may be different with 1FH.01H (The reason is 1FH can support more levels. For QEMU, 1FH also supports die, 1FH.01H:EBX[bits 15:00] expects "cpus per die"). 4. In cpu_x86_cpuid() of target/i386/cpu.c, when CPUID.80000001H is calculated, here "cpus per package" is expected to be checked, but in fact, now it checks "cpus per die". Though "cpus per die" also works for this code logic, this isn't consistent with AMD's APM. 5. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.80000008H:ECX expects "cpus per package" but it obtains "cpus per die". 6. In simulate_rdmsr() of target/i386/hvf/x86_emu.c, in kvm_rdmsr_core_thread_count() of target/i386/kvm/kvm.c, and in helper_rdmsr() of target/i386/tcg/sysemu/misc_helper.c, MSR_CORE_THREAD_COUNT expects "cpus per package" and "cores per package", but in these functions, it obtains "cpus per die" and "cores per die". On the other hand, these uses are correct now (they are added in/after a94e1428991f): 1. In cpu_x86_cpuid() of target/i386/cpu.c, topo_info.cores_per_die meets the actual meaning of CPUState.nr_cores ("cores per die"). 2. In cpu_x86_cpuid() of target/i386/cpu.c, vcpus_per_socket (in CPUID. 04H's calculation) considers number of dies, so it's correct. 3. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.1FH.01H:EBX[bits 15:00] needs "cpus per die" and it gets the correct result, and CPUID.1FH.02H:EBX[bits 15:00] gets correct "cpus per package". When CPUState.nr_cores is correctly changed to "cores per package" again , the above errors will be fixed without extra work, but the "currently" correct cases will go wrong and need special handling to pass correct "cpus/cores per die" they want. Fix CPUState.nr_cores' calculation to fit the original meaning "cores per package", as well as changing calculation of topo_info.cores_per_die, vcpus_per_socket and CPUID.1FH. Fixes: a94e1428991f ("target/i386: Add CPUID.1F generation support for multi-dies PCMachine") Fixes: 003f230e37d7 ("machine: Tweak the order of topology members in struct CpuTopology") Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin Message-ID: <20231024090323.1859210-4-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé --- system/cpus.c | 2 +- target/i386/cpu.c | 9 ++++----- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/system/cpus.c b/system/cpus.c index 952f15868c..a444a747f0 100644 --- a/system/cpus.c +++ b/system/cpus.c @@ -631,7 +631,7 @@ void qemu_init_vcpu(CPUState *cpu) { MachineState *ms = MACHINE(qdev_get_machine()); - cpu->nr_cores = ms->smp.cores; + cpu->nr_cores = machine_topo_get_cores_per_socket(ms); cpu->nr_threads = ms->smp.threads; cpu->stopped = true; cpu->random_seed = qemu_guest_random_seed_thread_part1(); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fc8484cb5e..358d9c0a65 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6019,7 +6019,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, X86CPUTopoInfo topo_info; topo_info.dies_per_pkg = env->nr_dies; - topo_info.cores_per_die = cs->nr_cores; + topo_info.cores_per_die = cs->nr_cores / env->nr_dies; topo_info.threads_per_core = cs->nr_threads; /* Calculate & apply limits for different index ranges */ @@ -6095,8 +6095,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, */ if (*eax & 31) { int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); - int vcpus_per_socket = env->nr_dies * cs->nr_cores * - cs->nr_threads; + int vcpus_per_socket = cs->nr_cores * cs->nr_threads; if (cs->nr_cores > 1) { *eax &= ~0xFC000000; *eax |= (pow2ceil(cs->nr_cores) - 1) << 26; @@ -6273,12 +6272,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 1: *eax = apicid_die_offset(&topo_info); - *ebx = cs->nr_cores * cs->nr_threads; + *ebx = topo_info.cores_per_die * topo_info.threads_per_core; *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; break; case 2: *eax = apicid_pkg_offset(&topo_info); - *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; + *ebx = cs->nr_cores * cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; break; default: From patchwork Mon Nov 6 11:03:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741342 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1027591wrr; Mon, 6 Nov 2023 03:19:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IGLezhQKpMPXpI1N6dIDPBaB7eexKGr1fgjs0+QoU89ZtoCwFcIWIfy6GzHP0NePZ1AdqQ4 X-Received: by 2002:a05:622a:305:b0:418:1252:9e73 with SMTP id q5-20020a05622a030500b0041812529e73mr35714279qtw.30.1699269539906; Mon, 06 Nov 2023 03:18:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269539; cv=none; d=google.com; s=arc-20160816; b=UTDkZOUerL4lnGPD+Ap88NEYgjwt1h8sLdNOihUOyZciD3aR7TsooGfxDeIrToP8mT q0G0ZUi7/1MpmnMa3MSIlJ4JiTGfsRQl5xejaRsH7KisW7ywiU6DTapzvOrCA67n3rsS tvGRt6EP4pgkhfP5jEVVyauPVdwe6u/PooB2FvPeZE98fH9PEFXqALdU0g06+DhS5nDw DJygqiGuimSkYCejQ9YzEe9B32E5tEigLXD5l4WA7pVTRXv0dNEYI9+EyUpgeytm/Y9Q 8Asxq76Ok+I+4A+NqKQ1aRu7Gg/7DcWe4XMmvCrIuCFA2z/LjveLuwIcrQCQpWGeJu8t MEkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GYvSXfF+xbSSjVZB+VdYev9ZdU+Lgrd51drrmwgB968=; fh=CqydUC7z3m+1ZVgnQUk3DlZOYjanITV9J2t5qJRJPD4=; b=NV+KWazplEqLFbB9Hi8EaMaM82lB/D3W+fjAxCBWbhvXA/VmBAtoyWfdM5DRz+zSiA jR39/Vz2GEJkUIoBLlJB3G98nKUGSsjQYJRBD3lXiwimM5g1ybaN40vO4dxC6Io9/NrL zYbyjWYL0cAdAsDklurDSRkvTVMHgNDziX7gqXXUUu+dT3cHkAJiF5g8J7OLd8ARfiK2 zeseuvVHrGaeu5v/n6CT1aoBAqFZLiKEVj0Ixt5C44/+z1b8YJV/rh6tH+fO2Eg2IMqn 0sp5Q/bhBrsat2ZQQqYWUmftFgy7M80jraq2TLnLzR9ETeYIj0uACRtg22j3g2BPn8zL 6zeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kEqzA5vU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id h15-20020a5d688f000000b0032f9688ea48sm9121553wru.10.2023.11.06.03.08.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:08:53 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Zhao Liu , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Babu Moger , Yongwei Ma , "Michael S . Tsirkin" , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang Subject: [PULL 46/60] hw/cpu: Update the comments of nr_cores and nr_dies Date: Mon, 6 Nov 2023 12:03:18 +0100 Message-ID: <20231106110336.358-47-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=philmd@linaro.org; helo=mail-lj1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Zhao Liu In the nr_threads' comment, specify it represents the number of threads in the "core" to avoid confusion. Also add comment for nr_dies in CPUX86State. Signed-off-by: Zhao Liu Reviewed-by: Philippe Mathieu-Daudé Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin Message-ID: <20231024090323.1859210-5-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 77893d7b81..c0c8320413 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -408,7 +408,7 @@ struct qemu_work_item; * See TranslationBlock::TCG CF_CLUSTER_MASK. * @tcg_cflags: Pre-computed cflags for this cpu. * @nr_cores: Number of cores within this CPU package. - * @nr_threads: Number of threads within this CPU. + * @nr_threads: Number of threads within this CPU core. * @running: #true if CPU is currently running (lockless). * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end; * valid under cpu_list_lock. diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6c6b066986..b60a417074 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1882,6 +1882,7 @@ typedef struct CPUArchState { TPRAccess tpr_access_type; + /* Number of dies within this CPU package. */ unsigned nr_dies; } CPUX86State; From patchwork Mon Nov 6 11:03:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741360 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1032418wrr; Mon, 6 Nov 2023 03:31:57 -0800 (PST) X-Google-Smtp-Source: AGHT+IFssSroWM0VwshbWwq6O9qr+q7b2A+A/89OKAhx9pzxX1PFoel/4ozilZOhN8KYsRwoHEIx X-Received: by 2002:ac8:5f4d:0:b0:418:fab:2d31 with SMTP id y13-20020ac85f4d000000b004180fab2d31mr36529201qta.4.1699270317559; Mon, 06 Nov 2023 03:31:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699270317; cv=none; d=google.com; s=arc-20160816; b=kWlGqw7NAJAweoh9aZZXAGJlUv1TwiNt774a5IMBg0nHLXR/j0tGJzudAyzokeYmmi inNor79+afqs89CBAYvhyTTJu9+C0wQ/PwWnWjeYq8IL6+Lv6SYycp7M1stX9d77PGJy /OL/5YPnU+NZCabCi8PFmSy7lIsz4eluG0uqJm5PJWt5hN2wfttynelcAUBIh1RyomQh XUqTmDMKnO5f7ENl/mZ8cRCnDd2Xlb64vVMOCVa6nhrPpT8+bUlSbnvIx2hC7YHzwd0i 8bPZQIjj9h9EIomvKFZV8zLYa13GWnQmOQ1WEMCH//9bb1Q7SERzK1IwJz48FY20KHVp StHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=l0/vWnFHt+cyNHMvzu2dssx7xYyn6IEpyeIo7MQjzWQ=; fh=BVgvOOujLHbkB3i/tRO+FYFnqKZbE5hgS/5eNKJti18=; b=0p1I3f6r8i9kClRMvwJ+VXB/48DwRSJK7q6QtQ4EyHvDdsmHAJcSKrl5tRtMZqHAU5 K7/c9C5P1Gvu57YW0dWKrokvzeSwjLNSosW2fgF31pE55w7UJURgo0aAw/YZQwy9ULR8 ESEj93pVgh4JT3kJxilQsOQOS0pxx0R+IVt0RPVZLeNTWagMCEhH0PsTjzenwapoC9fI g0bbuAfowDfA/C6fmVKyWgpL8J2oTTCnguDcxBYn08UJUFrsqCwqvQ8Uf0vKv4GLbtEH t7RBRobYiF+5Qkzr8cBBkdlsBDRSBLYj86Xx4dWvlngm2UHYwTxjHKCx54rM4FbwjROE 6HVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ATOHgHNs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id z18-20020adfec92000000b0032da8fb0d05sm9132494wrn.110.2023.11.06.03.08.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:08:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Fiona Ebner , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , simon.rowe@nutanix.com, John Snow Subject: [PULL 47/60] hw/ide: reset: cancel async DMA operation before resetting state Date: Mon, 6 Nov 2023 12:03:19 +0100 Message-ID: <20231106110336.358-48-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Fiona Ebner If there is a pending DMA operation during ide_bus_reset(), the fact that the IDEState is already reset before the operation is canceled can be problematic. In particular, ide_dma_cb() might be called and then use the reset IDEState which contains the signature after the reset. When used to construct the IO operation this leads to ide_get_sector() returning 0 and nsector being 1. This is particularly bad, because a write command will thus destroy the first sector which often contains a partition table or similar. Traces showing the unsolicited write happening with IDEState 0x5595af6949d0 being used after reset: > ahci_port_write ahci(0x5595af6923f0)[0]: port write [reg:PxSCTL] @ 0x2c: 0x00000300 > ahci_reset_port ahci(0x5595af6923f0)[0]: reset port > ide_reset IDEstate 0x5595af6949d0 > ide_reset IDEstate 0x5595af694da8 > ide_bus_reset_aio aio_cancel > dma_aio_cancel dbs=0x7f64600089a0 > dma_blk_cb dbs=0x7f64600089a0 ret=0 > dma_complete dbs=0x7f64600089a0 ret=0 cb=0x5595acd40b30 > ahci_populate_sglist ahci(0x5595af6923f0)[0] > ahci_dma_prepare_buf ahci(0x5595af6923f0)[0]: prepare buf limit=512 prepared=512 > ide_dma_cb IDEState 0x5595af6949d0; sector_num=0 n=1 cmd=DMA WRITE > dma_blk_io dbs=0x7f6420802010 bs=0x5595ae2c6c30 offset=0 to_dev=1 > dma_blk_cb dbs=0x7f6420802010 ret=0 > (gdb) p *qiov > $11 = {iov = 0x7f647c76d840, niov = 1, {{nalloc = 1, local_iov = {iov_base = 0x0, > iov_len = 512}}, {__pad = "\001\000\000\000\000\000\000\000\000\000\000", > size = 512}}} > (gdb) bt > #0 blk_aio_pwritev (blk=0x5595ae2c6c30, offset=0, qiov=0x7f6420802070, flags=0, > cb=0x5595ace6f0b0 , opaque=0x7f6420802010) > at ../block/block-backend.c:1682 > #1 0x00005595ace6f185 in dma_blk_cb (opaque=0x7f6420802010, ret=) > at ../softmmu/dma-helpers.c:179 > #2 0x00005595ace6f778 in dma_blk_io (ctx=0x5595ae0609f0, > sg=sg@entry=0x5595af694d00, offset=offset@entry=0, align=align@entry=512, > io_func=io_func@entry=0x5595ace6ee30 , > io_func_opaque=io_func_opaque@entry=0x5595ae2c6c30, > cb=0x5595acd40b30 , opaque=0x5595af6949d0, > dir=DMA_DIRECTION_TO_DEVICE) at ../softmmu/dma-helpers.c:244 > #3 0x00005595ace6f90a in dma_blk_write (blk=0x5595ae2c6c30, > sg=sg@entry=0x5595af694d00, offset=offset@entry=0, align=align@entry=512, > cb=cb@entry=0x5595acd40b30 , opaque=opaque@entry=0x5595af6949d0) > at ../softmmu/dma-helpers.c:280 > #4 0x00005595acd40e18 in ide_dma_cb (opaque=0x5595af6949d0, ret=) > at ../hw/ide/core.c:953 > #5 0x00005595ace6f319 in dma_complete (ret=0, dbs=0x7f64600089a0) > at ../softmmu/dma-helpers.c:107 > #6 dma_blk_cb (opaque=0x7f64600089a0, ret=0) at ../softmmu/dma-helpers.c:127 > #7 0x00005595ad12227d in blk_aio_complete (acb=0x7f6460005b10) > at ../block/block-backend.c:1527 > #8 blk_aio_complete (acb=0x7f6460005b10) at ../block/block-backend.c:1524 > #9 blk_aio_write_entry (opaque=0x7f6460005b10) at ../block/block-backend.c:1594 > #10 0x00005595ad258cfb in coroutine_trampoline (i0=, > i1=) at ../util/coroutine-ucontext.c:177 Signed-off-by: Fiona Ebner Reviewed-by: Philippe Mathieu-Daudé Tested-by: simon.rowe@nutanix.com Message-ID: <20230906130922.142845-1-f.ebner@proxmox.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ide/core.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/ide/core.c b/hw/ide/core.c index b5e0dcd29b..63ba665f3d 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -2515,19 +2515,19 @@ static void ide_dummy_transfer_stop(IDEState *s) void ide_bus_reset(IDEBus *bus) { - bus->unit = 0; - bus->cmd = 0; - ide_reset(&bus->ifs[0]); - ide_reset(&bus->ifs[1]); - ide_clear_hob(bus); - - /* pending async DMA */ + /* pending async DMA - needs the IDEState before it is reset */ if (bus->dma->aiocb) { trace_ide_bus_reset_aio(); blk_aio_cancel(bus->dma->aiocb); bus->dma->aiocb = NULL; } + bus->unit = 0; + bus->cmd = 0; + ide_reset(&bus->ifs[0]); + ide_reset(&bus->ifs[1]); + ide_clear_hob(bus); + /* reset dma provider too */ if (bus->dma->ops->reset) { bus->dma->ops->reset(bus->dma); From patchwork Mon Nov 6 11:03:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741365 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1032946wrr; Mon, 6 Nov 2023 03:33:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IEUoupKsu3o6llQlEDlYBhXa4Q0oky7vPFU+/5rmR85qET6XGzcxjQKA/1VKQs7n0nOX8A0 X-Received: by 2002:a05:620a:4482:b0:779:db5e:6656 with SMTP id x2-20020a05620a448200b00779db5e6656mr35894117qkp.4.1699270396327; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id j19-20020a05600c191300b004090ca6d785sm11949457wmq.2.2023.11.06.03.09.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:09:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Fiona Ebner , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Thomas Huth , Laurent Vivier , Paolo Bonzini Subject: [PULL 48/60] tests/qtest: ahci-test: add test exposing reset issue with pending callback Date: Mon, 6 Nov 2023 12:03:20 +0100 Message-ID: <20231106110336.358-49-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=philmd@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Fiona Ebner Before commit "hw/ide: reset: cancel async DMA operation before resetting state", this test would fail, because a reset with a pending write operation would lead to an unsolicited write to the first sector of the disk. The test writes a pattern to the beginning of the disk and verifies that it is still intact after a reset with a pending operation. It also checks that the pending operation actually completes correctly. Signed-off-by: Fiona Ebner Message-ID: <20230906130922.142845-2-f.ebner@proxmox.com> Signed-off-by: Philippe Mathieu-Daudé --- tests/qtest/ahci-test.c | 86 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 1 deletion(-) diff --git a/tests/qtest/ahci-test.c b/tests/qtest/ahci-test.c index eea8b5f77b..5a1923f721 100644 --- a/tests/qtest/ahci-test.c +++ b/tests/qtest/ahci-test.c @@ -1424,6 +1424,89 @@ static void test_reset(void) ahci_shutdown(ahci); } +static void test_reset_pending_callback(void) +{ + AHCIQState *ahci; + AHCICommand *cmd; + uint8_t port; + uint64_t ptr1; + uint64_t ptr2; + + int bufsize = 4 * 1024; + int speed = bufsize + (bufsize / 2); + int offset1 = 0; + int offset2 = bufsize / AHCI_SECTOR_SIZE; + + g_autofree unsigned char *tx1 = g_malloc(bufsize); + g_autofree unsigned char *tx2 = g_malloc(bufsize); + g_autofree unsigned char *rx1 = g_malloc0(bufsize); + g_autofree unsigned char *rx2 = g_malloc0(bufsize); + + /* Uses throttling to make test independent of specific environment. */ + ahci = ahci_boot_and_enable("-drive if=none,id=drive0,file=%s," + "cache=writeback,format=%s," + "throttling.bps-write=%d " + "-M q35 " + "-device ide-hd,drive=drive0 ", + tmp_path, imgfmt, speed); + + port = ahci_port_select(ahci); + ahci_port_clear(ahci, port); + + ptr1 = ahci_alloc(ahci, bufsize); + ptr2 = ahci_alloc(ahci, bufsize); + + g_assert(ptr1 && ptr2); + + /* Need two different patterns. */ + do { + generate_pattern(tx1, bufsize, AHCI_SECTOR_SIZE); + generate_pattern(tx2, bufsize, AHCI_SECTOR_SIZE); + } while (memcmp(tx1, tx2, bufsize) == 0); + + qtest_bufwrite(ahci->parent->qts, ptr1, tx1, bufsize); + qtest_bufwrite(ahci->parent->qts, ptr2, tx2, bufsize); + + /* Write to beginning of disk to check it wasn't overwritten later. */ + ahci_guest_io(ahci, port, CMD_WRITE_DMA_EXT, ptr1, bufsize, offset1); + + /* Issue asynchronously to get a pending callback during reset. */ + cmd = ahci_command_create(CMD_WRITE_DMA_EXT); + ahci_command_adjust(cmd, offset2, ptr2, bufsize, 0); + ahci_command_commit(ahci, cmd, port); + ahci_command_issue_async(ahci, cmd); + + ahci_set(ahci, AHCI_GHC, AHCI_GHC_HR); + + ahci_command_free(cmd); + + /* Wait for throttled write to finish. */ + sleep(1); + + /* Start again. */ + ahci_clean_mem(ahci); + ahci_pci_enable(ahci); + ahci_hba_enable(ahci); + port = ahci_port_select(ahci); + ahci_port_clear(ahci, port); + + /* Read and verify. */ + ahci_guest_io(ahci, port, CMD_READ_DMA_EXT, ptr1, bufsize, offset1); + qtest_bufread(ahci->parent->qts, ptr1, rx1, bufsize); + g_assert_cmphex(memcmp(tx1, rx1, bufsize), ==, 0); + + ahci_guest_io(ahci, port, CMD_READ_DMA_EXT, ptr2, bufsize, offset2); + qtest_bufread(ahci->parent->qts, ptr2, rx2, bufsize); + g_assert_cmphex(memcmp(tx2, rx2, bufsize), ==, 0); + + ahci_free(ahci, ptr1); + ahci_free(ahci, ptr2); + + ahci_clean_mem(ahci); + + ahci_shutdown(ahci); +} + static void test_ncq_simple(void) { AHCIQState *ahci; @@ -1945,7 +2028,8 @@ int main(int argc, char **argv) qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma); qtest_add_func("/ahci/max", test_max); - qtest_add_func("/ahci/reset", test_reset); + qtest_add_func("/ahci/reset/simple", test_reset); + qtest_add_func("/ahci/reset/pending_callback", test_reset_pending_callback); qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple); qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq); From patchwork Mon Nov 6 11:03:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741386 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1039368wrr; Mon, 6 Nov 2023 03:50:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IHff0j4DartVWXAEyrqt6DZTQc8gTLuQVs5RbzQ+osTb8Q/mrfR3o3VzC7bWnU9p8QQ029X X-Received: by 2002:ac8:4e96:0:b0:41e:2b64:11f5 with SMTP id 22-20020ac84e96000000b0041e2b6411f5mr34912749qtp.68.1699271459384; Mon, 06 Nov 2023 03:50:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699271459; cv=none; d=google.com; s=arc-20160816; b=B0VkXNmHQH7b5/eTvUdOTbs7Qz4ioCVRBrsRftcR9aYDdnOev6JjfseatXkiwl/buh Era9JadXlHf/rT+XLwRzxJ1bJDquXYCEMqxnfFiSoeXFIPJKm0A57EXPhyB+XEv2kXs0 k8z0ZGXSvcRqt5kMQinda6gK3Dcppl3JN4O+UGF1uL2Kbhzf2GowaUFIwcOj7ARI9OAK Aun3XkKnbHaK7F1b+3+2lzLI+syqVUhq4lFyzW8H2zSpSYom2Qottjfcg3OykHT0rK7u YwQB0dR9r3tk9OLhb7PYcB0i0WXHuRh5ZInWURp/F7U2kb7rrfTD/bXpH0DPGLP0WZbD zM5Q== ARC-Message-Signature: i=1; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id j17-20020a056000125100b0032db4e660d9sm9181558wrx.56.2023.11.06.03.09.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:09:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Titus Rwantare , Hao Wu , Corey Minyard , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 49/60] hw/i2c: pmbus add support for block receive Date: Mon, 6 Nov 2023 12:03:21 +0100 Message-ID: <20231106110336.358-50-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Titus Rwantare PMBus devices can send and receive variable length data using the block read and write format, with the first byte in the payload denoting the length. This is mostly used for strings and on-device logs. Devices can respond to a block read with an empty string. Reviewed-by: Hao Wu Acked-by: Corey Minyard Signed-off-by: Titus Rwantare Message-ID: <20231023-staging-pmbus-v3-v4-1-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/i2c/pmbus_device.h | 7 +++++++ hw/i2c/pmbus_device.c | 30 +++++++++++++++++++++++++++++- 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/include/hw/i2c/pmbus_device.h b/include/hw/i2c/pmbus_device.h index 93f5d57c9d..7dc00cc4d9 100644 --- a/include/hw/i2c/pmbus_device.h +++ b/include/hw/i2c/pmbus_device.h @@ -501,6 +501,13 @@ void pmbus_send64(PMBusDevice *state, uint64_t data); */ void pmbus_send_string(PMBusDevice *state, const char *data); +/** + * @brief Receive data sent with Block Write. + * @param dest - memory with enough capacity to receive the write + * @param len - the capacity of dest + */ +uint8_t pmbus_receive_block(PMBusDevice *pmdev, uint8_t *dest, size_t len); + /** * @brief Receive data over PMBus * These methods help track how much data is being received over PMBus diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c index cef51663d0..ea15490720 100644 --- a/hw/i2c/pmbus_device.c +++ b/hw/i2c/pmbus_device.c @@ -102,7 +102,6 @@ void pmbus_send_string(PMBusDevice *pmdev, const char *data) } size_t len = strlen(data); - g_assert(len > 0); g_assert(len + pmdev->out_buf_len < SMBUS_DATA_MAX_LEN); pmdev->out_buf[len + pmdev->out_buf_len] = len; @@ -112,6 +111,35 @@ void pmbus_send_string(PMBusDevice *pmdev, const char *data) pmdev->out_buf_len += len + 1; } +uint8_t pmbus_receive_block(PMBusDevice *pmdev, uint8_t *dest, size_t len) +{ + /* dest may contain data from previous writes */ + memset(dest, 0, len); + + /* Exclude command code from return value */ + pmdev->in_buf++; + pmdev->in_buf_len--; + + /* The byte after the command code denotes the length */ + uint8_t sent_len = pmdev->in_buf[0]; + + if (sent_len != pmdev->in_buf_len - 1) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: length mismatch. Expected %d bytes, got %d bytes\n", + __func__, sent_len, pmdev->in_buf_len - 1); + } + + /* exclude length byte */ + pmdev->in_buf++; + pmdev->in_buf_len--; + + if (pmdev->in_buf_len < len) { + len = pmdev->in_buf_len; + } + memcpy(dest, pmdev->in_buf, len); + return len; +} + static uint64_t pmbus_receive_uint(PMBusDevice *pmdev) { From patchwork Mon Nov 6 11:03:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741346 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1028057wrr; Mon, 6 Nov 2023 03:20:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IEwwD2cJhkMlF+rIon2f188ui66j1Mop93DRURIP2tPLg+pX5H/tYgDPaJwksRJRyVoTqed X-Received: by 2002:a05:6214:2a8b:b0:64c:9d23:8f55 with SMTP id jr11-20020a0562142a8b00b0064c9d238f55mr31412127qvb.58.1699269620026; Mon, 06 Nov 2023 03:20:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269620; cv=none; d=google.com; s=arc-20160816; b=D5bUFr0iHGb7uLI1eIJLI0zeOpACqpTL1lJ4teMjcmISd5hllsApuVYIOa9lpLctTz iRrQmghlbozoCLKzMnuq8fCDdR7Ur4jGvDIuIVu3XuYA1REQAzj9SeXWUvxWSlvb0cc0 ot4unYwwEOzmLh9KfEaC+zQfM6CAUU+py0O5Vc0sqqQX32uKciF2cJvmhHMN5zw4m8m8 LhX3XRxexZ39oQr9ciowkgJFTQrrdL+13j3ILE8yu0wgQ1LEYjhIErzw1eKcKB4ZbFhm G9UPh1mhfnHFX3jcQbNDXb/Lnuvzt6hlno/UfZFYx574iKopSPs1v6qwB9R2cum4uO0j VlDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=X3TRJ7mvtWFdvHNvT+G6kpqIlBzXe7wSn3LOLdu3gVg=; fh=c1Hsd908U9PKLwue3PgIR6OEtkIdu11a71wsyXYOJoE=; b=PZdJ7vl2/5eENzzhuBA5qHiIg0hpyh8ssp8lUvVBzFVDrvuGSCySwh8O1DiDvqERb2 w1sV7C7CtVet7i1qdgTteYLgZ9gRdc4zV+U2G/2MRk7N5GWphm/JpDBlhkVHJ0TYPs75 BgWFQPNv64dYYCzsxIrqpFKJh05VFWqxiuavQE3PhL9L/VvHA5yi1b0EOxzrQFJn9Wkz j24Jf5laQAo87EPcgi3tW9h+NkxZmpQvRw+WX8PjSN+oaQIdtWp7XQHEzjoaxIEy0N+1 6M2/O0qm4J9QgR8EXC6fzm42Qpuod2oO3QH3osbQeOgJ4ZNDG6+i98esv021R6pdjHIp aL0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SQyhIko2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id t14-20020a05600c198e00b00405d9a950a2sm11977070wmq.28.2023.11.06.03.09.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:09:19 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Titus Rwantare , Hao Wu , Corey Minyard , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 50/60] hw/i2c: pmbus: add vout mode bitfields Date: Mon, 6 Nov 2023 12:03:22 +0100 Message-ID: <20231106110336.358-51-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Titus Rwantare The VOUT_MODE command is described in the PMBus Specification, Part II, Ver 1.3 Section 8.3 VOUT_MODE has a three bit mode and 4 bit parameter, the three bit mode determines whether voltages are formatted as uint16, uint16, VID, and Direct modes. VID and Direct modes use the remaining 5 bits to scale the voltage readings. Reviewed-by: Hao Wu Acked-by: Corey Minyard Signed-off-by: Titus Rwantare Message-ID: <20231023-staging-pmbus-v3-v4-2-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/i2c/pmbus_device.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/hw/i2c/pmbus_device.h b/include/hw/i2c/pmbus_device.h index 7dc00cc4d9..2e95164aa1 100644 --- a/include/hw/i2c/pmbus_device.h +++ b/include/hw/i2c/pmbus_device.h @@ -444,6 +444,14 @@ typedef struct PMBusCoefficients { int32_t R; /* exponent */ } PMBusCoefficients; +/** + * VOUT_Mode bit fields + */ +typedef struct PMBusVoutMode { + uint8_t mode:3; + int8_t exp:5; +} PMBusVoutMode; + /** * Convert sensor values to direct mode format * From patchwork Mon Nov 6 11:03:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741383 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1037826wrr; Mon, 6 Nov 2023 03:46:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IHBjieosXSBFkxWL4v0lCZ4f/Fi/ZMo/CL47gCzegY4Hj9wkSy/eoAJ4dsbPPkr/yUKStPx X-Received: by 2002:a05:6830:4386:b0:6d3:fb6:3f9c with SMTP id s6-20020a056830438600b006d30fb63f9cmr22307633otv.15.1699271194164; Mon, 06 Nov 2023 03:46:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699271194; cv=none; d=google.com; s=arc-20160816; b=ygEpuKx4EqGHwyOpGg6RKuZAOp2qkRVks+fYvpJGQjIFmxGCiVk7IlNZvW4tBrFWoV KdzP2Y2SrIkvsv8A6gqMUANqgyz5Aev7LW/r3jhbM4ehiiFm2XlVNJpAcoCH9PGv6uuq 773SQ38uqiJAGSrllmYejUsLDDS2/wI1o28ojrLWkfyi1SL9fmBJd4k0aHkf65Q461mN hxAgr8mLFt7TMTRVTlhVpcaqqCUDttifDgSkysiXefgHBTRllocW1XvmSBPyvCTr8t2B wW0PwxkWa+wBupXpoi41ho/4tZYO1QMNWVb+zl5A1cW9yo979Gi8JO6IC83uYqNlyovA zC4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=SjHtz+lPcIw6M6S7bcDq7sYVmI6jCo0hvfjVBU4M5Y0=; fh=f+gs2uUOwy1aaohSYhHU7Dp8Xo0RL3ov5eFKDyVFYsQ=; b=yiqEMETXH8uVe4gjIsjPC4vZPj/F3PImLbcIH496oVSQ/Km5jNkduZpAEEvqBCwIUY 1uVWD79eFwmUFoxLsz3tGBj5dnDDpuyc+i+P39JzfUgI3RmNkNG5QtgUKr2vjmLTf65O PdLgTgCH4DarhFHSat6nj02wzRyNk9Row7illbwhEsz/lrD++GF7EhgFP9hVIkVp96ce mC/mP3sogKqfeTpsvlarIOpAIri8UF38YNvjuhzDXiQ9Hd01IqggV3vW9ObBGdOSMHjf uSCOa7+UpfinX14TbkNLhVIDFDyKiGy5EQqpNSIObXTgX98Q9lu2w5Y9AU3Oerbln71D R2sw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dxRKLRxS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id j6-20020adfea46000000b0032fc609c118sm6076145wrn.66.2023.11.06.03.09.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:09:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Titus Rwantare , Stephen Longfield , Corey Minyard , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 51/60] hw/i2c: pmbus: add fan support Date: Mon, 6 Nov 2023 12:03:23 +0100 Message-ID: <20231106110336.358-52-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Titus Rwantare PMBus devices may integrate fans whose operation is configurable over PMBus. This commit allows the driver to read and write the fan control registers but does not model the operation of fans. Reviewed-by: Stephen Longfield Acked-by: Corey Minyard Signed-off-by: Titus Rwantare Message-ID: <20231023-staging-pmbus-v3-v4-3-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/i2c/pmbus_device.h | 1 + hw/i2c/pmbus_device.c | 176 ++++++++++++++++++++++++++++++++++ 2 files changed, 177 insertions(+) diff --git a/include/hw/i2c/pmbus_device.h b/include/hw/i2c/pmbus_device.h index 2e95164aa1..ad431bdc7c 100644 --- a/include/hw/i2c/pmbus_device.h +++ b/include/hw/i2c/pmbus_device.h @@ -258,6 +258,7 @@ OBJECT_DECLARE_TYPE(PMBusDevice, PMBusDeviceClass, #define PB_HAS_TEMP2 BIT_ULL(41) #define PB_HAS_TEMP3 BIT_ULL(42) #define PB_HAS_TEMP_RATING BIT_ULL(43) +#define PB_HAS_FAN BIT_ULL(44) #define PB_HAS_MFR_INFO BIT_ULL(50) #define PB_HAS_STATUS_MFR_SPECIFIC BIT_ULL(51) diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c index ea15490720..c1d8c93056 100644 --- a/hw/i2c/pmbus_device.c +++ b/hw/i2c/pmbus_device.c @@ -500,6 +500,54 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd) } break; + case PMBUS_FAN_CONFIG_1_2: /* R/W byte */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send8(pmdev, pmdev->pages[index].fan_config_1_2); + } else { + goto passthough; + } + break; + + case PMBUS_FAN_COMMAND_1: /* R/W word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].fan_command_1); + } else { + goto passthough; + } + break; + + case PMBUS_FAN_COMMAND_2: /* R/W word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].fan_command_2); + } else { + goto passthough; + } + break; + + case PMBUS_FAN_CONFIG_3_4: /* R/W byte */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send8(pmdev, pmdev->pages[index].fan_config_3_4); + } else { + goto passthough; + } + break; + + case PMBUS_FAN_COMMAND_3: /* R/W word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].fan_command_3); + } else { + goto passthough; + } + break; + + case PMBUS_FAN_COMMAND_4: /* R/W word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].fan_command_4); + } else { + goto passthough; + } + break; + case PMBUS_VOUT_OV_FAULT_LIMIT: /* R/W word */ if (pmdev->pages[index].page_flags & PB_HAS_VOUT) { pmbus_send16(pmdev, pmdev->pages[index].vout_ov_fault_limit); @@ -810,6 +858,22 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd) pmbus_send8(pmdev, pmdev->pages[index].status_mfr_specific); break; + case PMBUS_STATUS_FANS_1_2: /* R/W byte */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send8(pmdev, pmdev->pages[index].status_fans_1_2); + } else { + goto passthough; + } + break; + + case PMBUS_STATUS_FANS_3_4: /* R/W byte */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send8(pmdev, pmdev->pages[index].status_fans_3_4); + } else { + goto passthough; + } + break; + case PMBUS_READ_EIN: /* Read-Only block 5 bytes */ if (pmdev->pages[index].page_flags & PB_HAS_EIN) { pmbus_send(pmdev, pmdev->pages[index].read_ein, 5); @@ -882,6 +946,54 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd) } break; + case PMBUS_READ_FAN_SPEED_1: /* Read-Only word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].read_fan_speed_1); + } else { + goto passthough; + } + break; + + case PMBUS_READ_FAN_SPEED_2: /* Read-Only word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].read_fan_speed_2); + } else { + goto passthough; + } + break; + + case PMBUS_READ_FAN_SPEED_3: /* Read-Only word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].read_fan_speed_3); + } else { + goto passthough; + } + break; + + case PMBUS_READ_FAN_SPEED_4: /* Read-Only word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].read_fan_speed_4); + } else { + goto passthough; + } + break; + + case PMBUS_READ_DUTY_CYCLE: /* Read-Only word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].read_duty_cycle); + } else { + goto passthough; + } + break; + + case PMBUS_READ_FREQUENCY: /* Read-Only word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].read_frequency); + } else { + goto passthough; + } + break; + case PMBUS_READ_POUT: /* Read-Only word */ if (pmdev->pages[index].page_flags & PB_HAS_POUT) { pmbus_send16(pmdev, pmdev->pages[index].read_pout); @@ -1305,6 +1417,54 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len) } break; + case PMBUS_FAN_CONFIG_1_2: /* R/W byte */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmdev->pages[index].fan_config_1_2 = pmbus_receive8(pmdev); + } else { + goto passthrough; + } + break; + + case PMBUS_FAN_COMMAND_1: /* R/W word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmdev->pages[index].fan_command_1 = pmbus_receive16(pmdev); + } else { + goto passthrough; + } + break; + + case PMBUS_FAN_COMMAND_2: /* R/W word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmdev->pages[index].fan_command_2 = pmbus_receive16(pmdev); + } else { + goto passthrough; + } + break; + + case PMBUS_FAN_CONFIG_3_4: /* R/W byte */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmdev->pages[index].fan_config_3_4 = pmbus_receive8(pmdev); + } else { + goto passthrough; + } + break; + + case PMBUS_FAN_COMMAND_3: /* R/W word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmdev->pages[index].fan_command_3 = pmbus_receive16(pmdev); + } else { + goto passthrough; + } + break; + + case PMBUS_FAN_COMMAND_4: /* R/W word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmdev->pages[index].fan_command_4 = pmbus_receive16(pmdev); + } else { + goto passthrough; + } + break; + case PMBUS_VOUT_OV_FAULT_LIMIT: /* R/W word */ if (pmdev->pages[index].page_flags & PB_HAS_VOUT) { pmdev->pages[index].vout_ov_fault_limit = pmbus_receive16(pmdev); @@ -1610,6 +1770,22 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len) pmdev->pages[index].status_mfr_specific = pmbus_receive8(pmdev); break; + case PMBUS_STATUS_FANS_1_2: /* R/W byte */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send8(pmdev, pmdev->pages[index].status_fans_1_2); + } else { + goto passthrough; + } + break; + + case PMBUS_STATUS_FANS_3_4: /* R/W byte */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send8(pmdev, pmdev->pages[index].status_fans_3_4); + } else { + goto passthrough; + } + break; + case PMBUS_PAGE_PLUS_READ: /* Block Read-only */ case PMBUS_CAPABILITY: /* Read-Only byte */ case PMBUS_COEFFICIENTS: /* Read-only block 5 bytes */ From patchwork Mon Nov 6 11:03:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741329 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1025787wrr; Mon, 6 Nov 2023 03:14:19 -0800 (PST) X-Google-Smtp-Source: AGHT+IG5aH5YxgFxE518LftCCBMI4VqLFshzwtllFXlmFw6eIvu2TKBzf/va9HiKQDW+32NI8ebe X-Received: by 2002:a05:622a:138a:b0:41c:f729:8032 with SMTP id o10-20020a05622a138a00b0041cf7298032mr40654371qtk.63.1699269258819; Mon, 06 Nov 2023 03:14:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269258; cv=none; d=google.com; s=arc-20160816; b=MCO5w686fjjXPunExYfBEL8ue1/cLDTtvLfb8hKeMfcrvt02DrlLQ3N7j0VJFLQDi8 g5xZLhS2Pkwhsxeuay/L3/tkUvrBjQyyVibprzVlft/6+oE0SseM2vpwSX7rSdH5J2rM y3nhFg+l4L7IW7P3H4sclIWpdTymTvEJJvmbYidWnHTDMkm4tYZwfze3ZTvP6WlzWqH8 R0zMMBr7NunpsYbUaoMENi3AYzE12m/fUAHzPadmcDjcscJhlH5F55lcrLkxFsHMzr7k 49xCHXd8N0w202kv0AOoTJhPOjGDhRGI/LbZYZbONnmmAbfOygcNLJJcQyOie1KdXa16 9+IA== ARC-Message-Signature: i=1; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id y8-20020a5d4708000000b0032d2f09d991sm9141944wrq.33.2023.11.06.03.09.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:09:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Titus Rwantare , Benjamin Streb , Corey Minyard , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 52/60] hw/i2c: pmbus: add VCAP register Date: Mon, 6 Nov 2023 12:03:24 +0100 Message-ID: <20231106110336.358-53-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Titus Rwantare VCAP is a register for devices with energy storage capacitors. Reviewed-by: Benjamin Streb Acked-by: Corey Minyard Signed-off-by: Titus Rwantare Message-ID: <20231023-staging-pmbus-v3-v4-4-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/i2c/pmbus_device.h | 1 + hw/i2c/pmbus_device.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/include/hw/i2c/pmbus_device.h b/include/hw/i2c/pmbus_device.h index ad431bdc7c..f195c11384 100644 --- a/include/hw/i2c/pmbus_device.h +++ b/include/hw/i2c/pmbus_device.h @@ -243,6 +243,7 @@ OBJECT_DECLARE_TYPE(PMBusDevice, PMBusDeviceClass, #define PB_HAS_VIN_RATING BIT_ULL(13) #define PB_HAS_VOUT_RATING BIT_ULL(14) #define PB_HAS_VOUT_MODE BIT_ULL(15) +#define PB_HAS_VCAP BIT_ULL(16) #define PB_HAS_IOUT BIT_ULL(21) #define PB_HAS_IIN BIT_ULL(22) #define PB_HAS_IOUT_RATING BIT_ULL(23) diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c index c1d8c93056..3bce39e84e 100644 --- a/hw/i2c/pmbus_device.c +++ b/hw/i2c/pmbus_device.c @@ -906,6 +906,14 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd) } break; + case PMBUS_READ_VCAP: /* Read-Only word */ + if (pmdev->pages[index].page_flags & PB_HAS_VCAP) { + pmbus_send16(pmdev, pmdev->pages[index].read_vcap); + } else { + goto passthough; + } + break; + case PMBUS_READ_VOUT: /* Read-Only word */ if (pmdev->pages[index].page_flags & PB_HAS_VOUT) { pmbus_send16(pmdev, pmdev->pages[index].read_vout); From patchwork Mon Nov 6 11:03:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741381 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1037779wrr; Mon, 6 Nov 2023 03:46:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IFOH25lpz/nnygvmUg6wPHH+HzgvUIcf2/ol9GEZ08PWiXoHlROYjCMW+a2jhTGqGO6xN1K X-Received: by 2002:ac8:7d8e:0:b0:41e:1d15:69a6 with SMTP id c14-20020ac87d8e000000b0041e1d1569a6mr36923051qtd.31.1699271183111; Mon, 06 Nov 2023 03:46:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699271183; cv=none; d=google.com; s=arc-20160816; b=Oso51hWsiZ82IM8fpBecBuZSJTK69IKph/5+dkb6oixC9e0HreaiXvEQ+FAZifdX+t wvaThuA/dPSmV957fT+YAzlV3D1sNA3IZmDbayaQyLh5ealoKBuy+QLySknVvDmh0MO8 RdTbmHA5y0yxxsayrjrioJcqR0RFT+YbD2D9e8fpnLgHwwRyqYCt08eupqtioI2Xcx9O n9V2OyNq3wIuMQ09/x/Aiard4XVT4XmrO34DpFd9qgJIo9J3/4V0GXH8C/qBc7TwgfLe YYzMlbKqf9JzwyWELYH+senU8nVH/I85T/61EE25s62dZIDVGgL+Ws6t6Imf3M1H+XhR bt0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=iac5EYIzrukJRvlyPwy92lw3bSASiGn2WGuusjle2eY=; fh=YMRhrMWAR9/faX65YwAcG8XlRMo3woI0wkjUL7OfoXc=; b=cxB1MtGiMNkUSCIobFJDTe+Nw+XZoVEdfcqXgplJNepAORNUkkJWvPgwQzrbH/uMkT 6/RCQohXwx+FOd8AZZWIoE7BXIIrAF/HyO6CrGiMRK21gsyShL8C8V/AdiwVsVR3HuUh 6fbH7sq5TNhJhE1w5JlMZGoocBLWO+N32WZW499N8YFUootza6r70Jt2GC7GVK4bhtk+ qDiIIfMjpm0L5w8ieSMXQbk2zcfQH9NwRPeYr0Su7TqnOGZakw9JNjnyH99VVAi/P5gq lZ4uHuKMf9Db+xaLi+qWFXCqZCd6cLjTDPenIw8zID916hoqprBvs/qUU21ndIM2T2k5 /+Uw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=koNfP1vg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id ew3-20020a05600c808300b004054dcbf92asm11515737wmb.20.2023.11.06.03.09.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:09:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Titus Rwantare , Hao Wu , Corey Minyard , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Tyrone Ting Subject: [PULL 53/60] hw/sensor: add ADM1266 device model Date: Mon, 6 Nov 2023 12:03:25 +0100 Message-ID: <20231106110336.358-54-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22c; envelope-from=philmd@linaro.org; helo=mail-lj1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Titus Rwantare The ADM1266 is a cascadable super sequencer with margin control and fault recording. This commit adds basic support for its PMBus commands and models the identification registers that can be modified in a firmware update. Reviewed-by: Hao Wu Acked-by: Corey Minyard Signed-off-by: Titus Rwantare [PMD: Cover file in MAINTAINERS] Message-ID: <20231023-staging-pmbus-v3-v4-5-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + hw/sensor/adm1266.c | 254 ++++++++++++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + hw/sensor/Kconfig | 5 + hw/sensor/meson.build | 1 + 5 files changed, 262 insertions(+) create mode 100644 hw/sensor/adm1266.c diff --git a/MAINTAINERS b/MAINTAINERS index 126cddd285..e6a2f57442 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -859,6 +859,7 @@ M: Hao Wu L: qemu-arm@nongnu.org S: Supported F: hw/*/npcm* +F: hw/sensor/adm1266.c F: include/hw/*/npcm* F: tests/qtest/npcm* F: pc-bios/npcm7xx_bootrom.bin diff --git a/hw/sensor/adm1266.c b/hw/sensor/adm1266.c new file mode 100644 index 0000000000..5ae4f82ba1 --- /dev/null +++ b/hw/sensor/adm1266.c @@ -0,0 +1,254 @@ +/* + * Analog Devices ADM1266 Cascadable Super Sequencer with Margin Control and + * Fault Recording with PMBus + * + * https://www.analog.com/media/en/technical-documentation/data-sheets/adm1266.pdf + * + * Copyright 2023 Google LLC + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/i2c/pmbus_device.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "qemu/log.h" +#include "qemu/module.h" + +#define TYPE_ADM1266 "adm1266" +OBJECT_DECLARE_SIMPLE_TYPE(ADM1266State, ADM1266) + +#define ADM1266_BLACKBOX_CONFIG 0xD3 +#define ADM1266_PDIO_CONFIG 0xD4 +#define ADM1266_READ_STATE 0xD9 +#define ADM1266_READ_BLACKBOX 0xDE +#define ADM1266_SET_RTC 0xDF +#define ADM1266_GPIO_SYNC_CONFIGURATION 0xE1 +#define ADM1266_BLACKBOX_INFORMATION 0xE6 +#define ADM1266_PDIO_STATUS 0xE9 +#define ADM1266_GPIO_STATUS 0xEA + +/* Defaults */ +#define ADM1266_OPERATION_DEFAULT 0x80 +#define ADM1266_CAPABILITY_DEFAULT 0xA0 +#define ADM1266_CAPABILITY_NO_PEC 0x20 +#define ADM1266_PMBUS_REVISION_DEFAULT 0x22 +#define ADM1266_MFR_ID_DEFAULT "ADI" +#define ADM1266_MFR_ID_DEFAULT_LEN 32 +#define ADM1266_MFR_MODEL_DEFAULT "ADM1266-A1" +#define ADM1266_MFR_MODEL_DEFAULT_LEN 32 +#define ADM1266_MFR_REVISION_DEFAULT "25" +#define ADM1266_MFR_REVISION_DEFAULT_LEN 8 + +#define ADM1266_NUM_PAGES 17 +/** + * PAGE Index + * Page 0 VH1. + * Page 1 VH2. + * Page 2 VH3. + * Page 3 VH4. + * Page 4 VP1. + * Page 5 VP2. + * Page 6 VP3. + * Page 7 VP4. + * Page 8 VP5. + * Page 9 VP6. + * Page 10 VP7. + * Page 11 VP8. + * Page 12 VP9. + * Page 13 VP10. + * Page 14 VP11. + * Page 15 VP12. + * Page 16 VP13. + */ +typedef struct ADM1266State { + PMBusDevice parent; + + char mfr_id[32]; + char mfr_model[32]; + char mfr_rev[8]; +} ADM1266State; + +static const uint8_t adm1266_ic_device_id[] = {0x03, 0x41, 0x12, 0x66}; +static const uint8_t adm1266_ic_device_rev[] = {0x08, 0x01, 0x08, 0x07, 0x0, + 0x0, 0x07, 0x41, 0x30}; + +static void adm1266_exit_reset(Object *obj) +{ + ADM1266State *s = ADM1266(obj); + PMBusDevice *pmdev = PMBUS_DEVICE(obj); + + pmdev->page = 0; + pmdev->capability = ADM1266_CAPABILITY_NO_PEC; + + for (int i = 0; i < ADM1266_NUM_PAGES; i++) { + pmdev->pages[i].operation = ADM1266_OPERATION_DEFAULT; + pmdev->pages[i].revision = ADM1266_PMBUS_REVISION_DEFAULT; + pmdev->pages[i].vout_mode = 0; + pmdev->pages[i].read_vout = pmbus_data2linear_mode(12, 0); + pmdev->pages[i].vout_margin_high = pmbus_data2linear_mode(15, 0); + pmdev->pages[i].vout_margin_low = pmbus_data2linear_mode(3, 0); + pmdev->pages[i].vout_ov_fault_limit = pmbus_data2linear_mode(16, 0); + pmdev->pages[i].revision = ADM1266_PMBUS_REVISION_DEFAULT; + } + + strncpy(s->mfr_id, ADM1266_MFR_ID_DEFAULT, 4); + strncpy(s->mfr_model, ADM1266_MFR_MODEL_DEFAULT, 11); + strncpy(s->mfr_rev, ADM1266_MFR_REVISION_DEFAULT, 3); +} + +static uint8_t adm1266_read_byte(PMBusDevice *pmdev) +{ + ADM1266State *s = ADM1266(pmdev); + + switch (pmdev->code) { + case PMBUS_MFR_ID: /* R/W block */ + pmbus_send_string(pmdev, s->mfr_id); + break; + + case PMBUS_MFR_MODEL: /* R/W block */ + pmbus_send_string(pmdev, s->mfr_model); + break; + + case PMBUS_MFR_REVISION: /* R/W block */ + pmbus_send_string(pmdev, s->mfr_rev); + break; + + case PMBUS_IC_DEVICE_ID: + pmbus_send(pmdev, adm1266_ic_device_id, sizeof(adm1266_ic_device_id)); + break; + + case PMBUS_IC_DEVICE_REV: + pmbus_send(pmdev, adm1266_ic_device_rev, sizeof(adm1266_ic_device_rev)); + break; + + default: + qemu_log_mask(LOG_UNIMP, + "%s: reading from unimplemented register: 0x%02x\n", + __func__, pmdev->code); + return 0xFF; + } + + return 0; +} + +static int adm1266_write_data(PMBusDevice *pmdev, const uint8_t *buf, + uint8_t len) +{ + ADM1266State *s = ADM1266(pmdev); + + switch (pmdev->code) { + case PMBUS_MFR_ID: /* R/W block */ + pmbus_receive_block(pmdev, (uint8_t *)s->mfr_id, sizeof(s->mfr_id)); + break; + + case PMBUS_MFR_MODEL: /* R/W block */ + pmbus_receive_block(pmdev, (uint8_t *)s->mfr_model, + sizeof(s->mfr_model)); + break; + + case PMBUS_MFR_REVISION: /* R/W block*/ + pmbus_receive_block(pmdev, (uint8_t *)s->mfr_rev, sizeof(s->mfr_rev)); + break; + + case ADM1266_SET_RTC: /* do nothing */ + break; + + default: + qemu_log_mask(LOG_UNIMP, + "%s: writing to unimplemented register: 0x%02x\n", + __func__, pmdev->code); + break; + } + return 0; +} + +static void adm1266_get(Object *obj, Visitor *v, const char *name, void *opaque, + Error **errp) +{ + uint16_t value; + PMBusDevice *pmdev = PMBUS_DEVICE(obj); + PMBusVoutMode *mode = (PMBusVoutMode *)&pmdev->pages[0].vout_mode; + + if (strcmp(name, "vout") == 0) { + value = pmbus_linear_mode2data(*(uint16_t *)opaque, mode->exp); + } else { + value = *(uint16_t *)opaque; + } + + visit_type_uint16(v, name, &value, errp); +} + +static void adm1266_set(Object *obj, Visitor *v, const char *name, void *opaque, + Error **errp) +{ + uint16_t *internal = opaque; + uint16_t value; + PMBusDevice *pmdev = PMBUS_DEVICE(obj); + PMBusVoutMode *mode = (PMBusVoutMode *)&pmdev->pages[0].vout_mode; + + if (!visit_type_uint16(v, name, &value, errp)) { + return; + } + + *internal = pmbus_data2linear_mode(value, mode->exp); + pmbus_check_limits(pmdev); +} + +static const VMStateDescription vmstate_adm1266 = { + .name = "ADM1266", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]){ + VMSTATE_PMBUS_DEVICE(parent, ADM1266State), + VMSTATE_END_OF_LIST() + } +}; + +static void adm1266_init(Object *obj) +{ + PMBusDevice *pmdev = PMBUS_DEVICE(obj); + uint64_t flags = PB_HAS_VOUT_MODE | PB_HAS_VOUT | PB_HAS_VOUT_MARGIN | + PB_HAS_VOUT_RATING | PB_HAS_STATUS_MFR_SPECIFIC; + + for (int i = 0; i < ADM1266_NUM_PAGES; i++) { + pmbus_page_config(pmdev, i, flags); + + object_property_add(obj, "vout[*]", "uint16", + adm1266_get, + adm1266_set, NULL, &pmdev->pages[i].read_vout); + } +} + +static void adm1266_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc = RESETTABLE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + PMBusDeviceClass *k = PMBUS_DEVICE_CLASS(klass); + + dc->desc = "Analog Devices ADM1266 Hot Swap controller"; + dc->vmsd = &vmstate_adm1266; + k->write_data = adm1266_write_data; + k->receive_byte = adm1266_read_byte; + k->device_num_pages = 17; + + rc->phases.exit = adm1266_exit_reset; +} + +static const TypeInfo adm1266_info = { + .name = TYPE_ADM1266, + .parent = TYPE_PMBUS_DEVICE, + .instance_size = sizeof(ADM1266State), + .instance_init = adm1266_init, + .class_init = adm1266_class_init, +}; + +static void adm1266_register_types(void) +{ + type_register_static(&adm1266_info); +} + +type_init(adm1266_register_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e35007ed41..0f22aee24b 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -489,6 +489,7 @@ config NPCM7XX default y depends on TCG && ARM select A9MPCORE + select ADM1266 select ADM1272 select ARM_GIC select SMBUS diff --git a/hw/sensor/Kconfig b/hw/sensor/Kconfig index e03bd09b50..bc6331b4ab 100644 --- a/hw/sensor/Kconfig +++ b/hw/sensor/Kconfig @@ -22,6 +22,11 @@ config ADM1272 bool depends on I2C +config ADM1266 + bool + depends on PMBUS + default y if PMBUS + config MAX34451 bool depends on I2C diff --git a/hw/sensor/meson.build b/hw/sensor/meson.build index 30e20e27b8..420fdc3359 100644 --- a/hw/sensor/meson.build +++ b/hw/sensor/meson.build @@ -2,6 +2,7 @@ system_ss.add(when: 'CONFIG_TMP105', if_true: files('tmp105.c')) system_ss.add(when: 'CONFIG_TMP421', if_true: files('tmp421.c')) system_ss.add(when: 'CONFIG_DPS310', if_true: files('dps310.c')) system_ss.add(when: 'CONFIG_EMC141X', if_true: files('emc141x.c')) +system_ss.add(when: 'CONFIG_ADM1266', if_true: files('adm1266.c')) system_ss.add(when: 'CONFIG_ADM1272', if_true: files('adm1272.c')) system_ss.add(when: 'CONFIG_MAX34451', if_true: files('max34451.c')) system_ss.add(when: 'CONFIG_LSM303DLHC_MAG', if_true: files('lsm303dlhc_mag.c')) From patchwork Mon Nov 6 11:03:26 2023 Content-Type: text/plain; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id l4-20020adfa384000000b0032d2489a399sm9245951wrb.49.2023.11.06.03.09.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:09:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Titus Rwantare , Hao Wu , Corey Minyard , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Tyrone Ting , Thomas Huth , Laurent Vivier , Paolo Bonzini Subject: [PULL 54/60] tests/qtest: add tests for ADM1266 Date: Mon, 6 Nov 2023 12:03:26 +0100 Message-ID: <20231106110336.358-55-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=philmd@linaro.org; helo=mail-lj1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Titus Rwantare The ADM1266 can have string fields written by the driver, so it's worth specifically testing. Reviewed-by: Hao Wu Acked-by: Corey Minyard Signed-off-by: Titus Rwantare [PMD: Cover file in MAINTAINERS] Message-ID: <20231023-staging-pmbus-v3-v4-6-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + tests/qtest/adm1266-test.c | 122 +++++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 3 files changed, 124 insertions(+) create mode 100644 tests/qtest/adm1266-test.c diff --git a/MAINTAINERS b/MAINTAINERS index e6a2f57442..c01c2e6ec0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -862,6 +862,7 @@ F: hw/*/npcm* F: hw/sensor/adm1266.c F: include/hw/*/npcm* F: tests/qtest/npcm* +F: tests/qtest/adm1266-test.c F: pc-bios/npcm7xx_bootrom.bin F: roms/vbootrom F: docs/system/arm/nuvoton.rst diff --git a/tests/qtest/adm1266-test.c b/tests/qtest/adm1266-test.c new file mode 100644 index 0000000000..6c312c499f --- /dev/null +++ b/tests/qtest/adm1266-test.c @@ -0,0 +1,122 @@ +/* + * Analog Devices ADM1266 Cascadable Super Sequencer with Margin Control and + * Fault Recording with PMBus + * + * Copyright 2022 Google LLC + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include +#include "hw/i2c/pmbus_device.h" +#include "libqtest-single.h" +#include "libqos/qgraph.h" +#include "libqos/i2c.h" +#include "qapi/qmp/qdict.h" +#include "qapi/qmp/qnum.h" +#include "qemu/bitops.h" + +#define TEST_ID "adm1266-test" +#define TEST_ADDR (0x12) + +#define ADM1266_BLACKBOX_CONFIG 0xD3 +#define ADM1266_PDIO_CONFIG 0xD4 +#define ADM1266_READ_STATE 0xD9 +#define ADM1266_READ_BLACKBOX 0xDE +#define ADM1266_SET_RTC 0xDF +#define ADM1266_GPIO_SYNC_CONFIGURATION 0xE1 +#define ADM1266_BLACKBOX_INFORMATION 0xE6 +#define ADM1266_PDIO_STATUS 0xE9 +#define ADM1266_GPIO_STATUS 0xEA + +/* Defaults */ +#define ADM1266_OPERATION_DEFAULT 0x80 +#define ADM1266_CAPABILITY_DEFAULT 0xA0 +#define ADM1266_CAPABILITY_NO_PEC 0x20 +#define ADM1266_PMBUS_REVISION_DEFAULT 0x22 +#define ADM1266_MFR_ID_DEFAULT "ADI" +#define ADM1266_MFR_ID_DEFAULT_LEN 32 +#define ADM1266_MFR_MODEL_DEFAULT "ADM1266-A1" +#define ADM1266_MFR_MODEL_DEFAULT_LEN 32 +#define ADM1266_MFR_REVISION_DEFAULT "25" +#define ADM1266_MFR_REVISION_DEFAULT_LEN 8 +#define TEST_STRING_A "a sample" +#define TEST_STRING_B "b sample" +#define TEST_STRING_C "rev c" + +static void compare_string(QI2CDevice *i2cdev, uint8_t reg, + const char *test_str) +{ + uint8_t len = i2c_get8(i2cdev, reg); + char i2c_str[SMBUS_DATA_MAX_LEN] = {0}; + + i2c_read_block(i2cdev, reg, (uint8_t *)i2c_str, len); + g_assert_cmpstr(i2c_str, ==, test_str); +} + +static void write_and_compare_string(QI2CDevice *i2cdev, uint8_t reg, + const char *test_str, uint8_t len) +{ + char buf[SMBUS_DATA_MAX_LEN] = {0}; + buf[0] = len; + strncpy(buf + 1, test_str, len); + i2c_write_block(i2cdev, reg, (uint8_t *)buf, len + 1); + compare_string(i2cdev, reg, test_str); +} + +static void test_defaults(void *obj, void *data, QGuestAllocator *alloc) +{ + uint16_t i2c_value; + QI2CDevice *i2cdev = (QI2CDevice *)obj; + + i2c_value = i2c_get8(i2cdev, PMBUS_OPERATION); + g_assert_cmphex(i2c_value, ==, ADM1266_OPERATION_DEFAULT); + + i2c_value = i2c_get8(i2cdev, PMBUS_REVISION); + g_assert_cmphex(i2c_value, ==, ADM1266_PMBUS_REVISION_DEFAULT); + + compare_string(i2cdev, PMBUS_MFR_ID, ADM1266_MFR_ID_DEFAULT); + compare_string(i2cdev, PMBUS_MFR_MODEL, ADM1266_MFR_MODEL_DEFAULT); + compare_string(i2cdev, PMBUS_MFR_REVISION, ADM1266_MFR_REVISION_DEFAULT); +} + +/* test r/w registers */ +static void test_rw_regs(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev = (QI2CDevice *)obj; + + /* empty strings */ + i2c_set8(i2cdev, PMBUS_MFR_ID, 0); + compare_string(i2cdev, PMBUS_MFR_ID, ""); + + i2c_set8(i2cdev, PMBUS_MFR_MODEL, 0); + compare_string(i2cdev, PMBUS_MFR_MODEL, ""); + + i2c_set8(i2cdev, PMBUS_MFR_REVISION, 0); + compare_string(i2cdev, PMBUS_MFR_REVISION, ""); + + /* test strings */ + write_and_compare_string(i2cdev, PMBUS_MFR_ID, TEST_STRING_A, + sizeof(TEST_STRING_A)); + write_and_compare_string(i2cdev, PMBUS_MFR_ID, TEST_STRING_B, + sizeof(TEST_STRING_B)); + write_and_compare_string(i2cdev, PMBUS_MFR_ID, TEST_STRING_C, + sizeof(TEST_STRING_C)); +} + +static void adm1266_register_nodes(void) +{ + QOSGraphEdgeOptions opts = { + .extra_device_opts = "id=" TEST_ID ",address=0x12" + }; + add_qi2c_address(&opts, &(QI2CAddress) { TEST_ADDR }); + + qos_node_create_driver("adm1266", i2c_device_create); + qos_node_consumes("adm1266", "i2c-bus", &opts); + + qos_add_test("test_defaults", "adm1266", test_defaults, NULL); + qos_add_test("test_rw_regs", "adm1266", test_rw_regs, NULL); +} + +libqos_init(adm1266_register_nodes); diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index c9945e69b1..47dabf91d0 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -241,6 +241,7 @@ qos_test_ss = ss.source_set() qos_test_ss.add( 'ac97-test.c', 'adm1272-test.c', + 'adm1266-test.c', 'ds1338-test.c', 'e1000-test.c', 'eepro100-test.c', From patchwork Mon Nov 6 11:03:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741339 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1026938wrr; Mon, 6 Nov 2023 03:17:26 -0800 (PST) X-Google-Smtp-Source: AGHT+IEnO577azcCuv46QYCQVWoU+swsvkpPtxW6k5OpFX8/U/OHxOjkj3sgIxWG1ZISE/efkdQ1 X-Received: by 2002:a05:620a:4d8f:b0:777:6d:b877 with SMTP id uw15-20020a05620a4d8f00b00777006db877mr24456911qkn.68.1699269446395; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id f18-20020a5d58f2000000b0032da4c98ab2sm9102932wrd.35.2023.11.06.03.09.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:09:52 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Titus Rwantare , Patrick Venture , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 55/60] hw/i2c: pmbus: immediately clear faults on request Date: Mon, 6 Nov 2023 12:03:27 +0100 Message-ID: <20231106110336.358-56-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Titus Rwantare The probing process of the generic pmbus driver generates faults to determine if functions are available. These faults were not always cleared resulting in probe failures. Reviewed-by: Patrick Venture Signed-off-by: Titus Rwantare Message-ID: <20231023-staging-pmbus-v3-v4-7-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/i2c/pmbus_device.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c index 3bce39e84e..481e158380 100644 --- a/hw/i2c/pmbus_device.c +++ b/hw/i2c/pmbus_device.c @@ -1244,6 +1244,11 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len) pmdev->in_buf = buf; pmdev->code = buf[0]; /* PMBus command code */ + + if (pmdev->code == PMBUS_CLEAR_FAULTS) { + pmbus_clear_faults(pmdev); + } + if (len == 1) { /* Single length writes are command codes only */ return 0; } From patchwork Mon Nov 6 11:03:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741364 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1032944wrr; Mon, 6 Nov 2023 03:33:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IHW4k9r95NkmFYEqfprtSAwk4Ya8SggGotQ0xQgWYlqG+pkYlKsy0AW8RlN2QMo8QHw+YOr X-Received: by 2002:a05:622a:10f:b0:41c:e702:4df7 with SMTP id u15-20020a05622a010f00b0041ce7024df7mr35572781qtw.63.1699270395881; Mon, 06 Nov 2023 03:33:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699270395; cv=none; d=google.com; s=arc-20160816; b=ygYn2mU3y8/KowF934n2u0w8xdDXVLxr7jXNORSYnZXYFDbNT2n3XGsBSX7F4TNXch cb3C3EhewIMgOOOM+KFx+xt+9rrfRLG9O9zFtu7l/aEeMBhvq7M6M/GemhAqC4AMsBR4 y98UvkdPszxF84/uUocdO1yprB27+EFmY57ABefZpeE/49U8YiDpvrmmss45eu/4uBFe PTMGxoRdqKL9eDTm9lFZ9QxDVyC2kyYuC2eggXcuVNufsIR3U6ADmC8vlRjMj36u7nQ5 NGgQ+bJFOlh8obhhY8Lcwg+RQDv3OKjbCXVCjI2pABrgv5XX1tPe1ECGuOd0gw0WQVzV ilAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MGUqOvUDBSiuVjcJL6HNGd3FosLBI9RMurHd3wgpnc0=; fh=aRIPeX+s2DDBTipkT3PFTnr+paXxUdjkxZpQDuA7k4Q=; b=C3XIIV9iMVhQ2U7b6ce3wzMjKBnwPt0ixx6Hw3mJrSRixx6P1gdHMK8qSPIv3or0Fc 9yw+3NjS7c6Hi0U2YaE+8nsmhfqnTjyzisrHEWjgQJICVTUyFrO74Lm33JXBhK9GDxEi 2wDgfUxva7zA1SAh3UZxvp7UqDrNZ+Z/CnOAOxlOx4iR+/pEPOnSgkoct2Tu6WGbLyVl YbatJyVq5tiSNQQDu8pJ2MIaXmXZPRhhFvCJylV8nKthX8yvO4BUYlxtzncnF9a2wzeJ oZ2wuQaAX6feXxdCR8GnnUtPnGWalxHACXXfwXwCb+Tk5saNiBro6RNx4u8r4LH2jYFW eaZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="UM/kvCtl"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id f13-20020a05600c4e8d00b0040596352951sm11684422wmq.5.2023.11.06.03.09.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:09:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Titus Rwantare , Hao Wu , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , Laurent Vivier , Paolo Bonzini Subject: [PULL 56/60] hw/i2c: pmbus: reset page register for out of range reads Date: Mon, 6 Nov 2023 12:03:28 +0100 Message-ID: <20231106110336.358-57-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::232; envelope-from=philmd@linaro.org; helo=mail-lj1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Titus Rwantare The linux pmbus driver scans all possible pages and does not reset the current page after the scan, making all future page reads fail as out of range on devices with a single page. This change resets out of range pages immediately on write. Also added a qtest for simultaneous writes to all pages. Reviewed-by: Hao Wu Signed-off-by: Titus Rwantare Message-ID: <20231023-staging-pmbus-v3-v4-8-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/i2c/pmbus_device.c | 18 +++++++++--------- tests/qtest/max34451-test.c | 24 ++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 9 deletions(-) diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c index 481e158380..1b978e588f 100644 --- a/hw/i2c/pmbus_device.c +++ b/hw/i2c/pmbus_device.c @@ -1255,6 +1255,15 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len) if (pmdev->code == PMBUS_PAGE) { pmdev->page = pmbus_receive8(pmdev); + + if (pmdev->page > pmdev->num_pages - 1 && pmdev->page != PB_ALL_PAGES) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: page %u is out of range\n", + __func__, pmdev->page); + pmdev->page = 0; /* undefined behaviour - reset to page 0 */ + pmbus_cml_error(pmdev); + return PMBUS_ERR_BYTE; + } return 0; } @@ -1268,15 +1277,6 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len) return 0; } - if (pmdev->page > pmdev->num_pages - 1) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: page %u is out of range\n", - __func__, pmdev->page); - pmdev->page = 0; /* undefined behaviour - reset to page 0 */ - pmbus_cml_error(pmdev); - return PMBUS_ERR_BYTE; - } - index = pmdev->page; switch (pmdev->code) { diff --git a/tests/qtest/max34451-test.c b/tests/qtest/max34451-test.c index 0c98d0764c..dbf6ddc829 100644 --- a/tests/qtest/max34451-test.c +++ b/tests/qtest/max34451-test.c @@ -18,6 +18,7 @@ #define TEST_ID "max34451-test" #define TEST_ADDR (0x4e) +#define MAX34451_MFR_MODE 0xD1 #define MAX34451_MFR_VOUT_PEAK 0xD4 #define MAX34451_MFR_IOUT_PEAK 0xD5 #define MAX34451_MFR_TEMPERATURE_PEAK 0xD6 @@ -315,6 +316,28 @@ static void test_ot_faults(void *obj, void *data, QGuestAllocator *alloc) } } +#define RAND_ON_OFF_CONFIG 0x12 +#define RAND_MFR_MODE 0x3456 + +/* test writes to all pages */ +static void test_all_pages(void *obj, void *data, QGuestAllocator *alloc) +{ + uint16_t i2c_value; + QI2CDevice *i2cdev = (QI2CDevice *)obj; + + i2c_set8(i2cdev, PMBUS_PAGE, PB_ALL_PAGES); + i2c_set8(i2cdev, PMBUS_ON_OFF_CONFIG, RAND_ON_OFF_CONFIG); + max34451_i2c_set16(i2cdev, MAX34451_MFR_MODE, RAND_MFR_MODE); + + for (int i = 0; i < MAX34451_NUM_TEMP_DEVICES + MAX34451_NUM_PWR_DEVICES; + i++) { + i2c_value = i2c_get8(i2cdev, PMBUS_ON_OFF_CONFIG); + g_assert_cmphex(i2c_value, ==, RAND_ON_OFF_CONFIG); + i2c_value = max34451_i2c_get16(i2cdev, MAX34451_MFR_MODE); + g_assert_cmphex(i2c_value, ==, RAND_MFR_MODE); + } +} + static void max34451_register_nodes(void) { QOSGraphEdgeOptions opts = { @@ -332,5 +355,6 @@ static void max34451_register_nodes(void) qos_add_test("test_ro_regs", "max34451", test_ro_regs, NULL); qos_add_test("test_ov_faults", "max34451", test_ov_faults, NULL); qos_add_test("test_ot_faults", "max34451", test_ot_faults, NULL); + qos_add_test("test_all_pages", "max34451", test_all_pages, NULL); } libqos_init(max34451_register_nodes); From patchwork Mon Nov 6 11:03:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741351 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1028905wrr; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id l9-20020adfe589000000b0032f7d7ec4adsm9119404wrm.92.2023.11.06.03.10.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:10:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Yoshinori Sato Subject: [PULL 57/60] MAINTAINERS: Add include/hw/timer/tmu012.h to the SH4 R2D section Date: Mon, 6 Nov 2023 12:03:29 +0100 Message-ID: <20231106110336.358-58-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philmd@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Thomas Huth tmu012.h is the header that belongs to hw/timer/sh_timer.c, so we should list it in the same section as sh_timer.c. Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Yoshinori Sato Message-ID: <20231026080011.156325-1-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index c01c2e6ec0..3014e768f7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1617,6 +1617,7 @@ F: hw/intc/sh_intc.c F: hw/pci-host/sh_pci.c F: hw/timer/sh_timer.c F: include/hw/sh4/sh_intc.h +F: include/hw/timer/tmu012.h Shix R: Yoshinori Sato From patchwork Mon Nov 6 11:03:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741361 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1032424wrr; Mon, 6 Nov 2023 03:31:58 -0800 (PST) X-Google-Smtp-Source: AGHT+IEnGWTsORuaRS1rbWz4rTxkRJZQ+o36CJY2F9X5Gc8D5jrST8tswpm4OsWDHO58BYFYub6+ X-Received: by 2002:a05:620a:6288:b0:774:d3f:c78c with SMTP id ov8-20020a05620a628800b007740d3fc78cmr28996711qkn.72.1699270317858; Mon, 06 Nov 2023 03:31:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699270317; cv=none; d=google.com; s=arc-20160816; b=Z2KlKX6YMNck29I/qtSFB2hn40nEvWOpiu62yJGvZM9dEp9flh7JlE9ipZYKZC3Hvi REVi4hx7Vkg/JX4C4UlGaKXKhTLw1zgNasbvN01MFxGMUQ6RNIEyuzuo2+e3KqfiakYk L5NogSsKX/Lmp3lM2IzkQ0wnjpuKgzwkgV+YQ1Adhxi6E2xrPEGvdcNngldrpWY2ps2s SeIKxYHraeOF7PGnjNqDDkb5xiMXFZmvHUXiNd8JUnTPhjEgvmRhryOcIikaREMcUwdu nGT92vx1IbRnDfo/KifMvZX+KVnu1JKMA8KUHe3mxbCvTL0DEwtZrrrRE2UkhZksPJVN Z8og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cyEPFd8qKgVauKHH+mzQW+99WSkPGmQyoZYgi3VA9Vc=; fh=yO6v8ZuR57jRYfBphwzdURjVQfp6dLbVuOS/xm2Ocxw=; b=U+KTRJNQL9mtbx8TZm1A/+CuylK8n0bEd30qFC6/Q7LWuGZCqjAQ1sn7Gb27Hhe0l2 Ct2ghu/PC6HYNOjkotDMbLaiwcpgC2pFH97JpqaK2gOI+2LbbuxGNxom1eGzkQK1xVPZ tx2QMnJVtq206bpEYswKX1WwnxKjY2NJxpgW7RqbddoexicjOgr26ZjhLpwGIy/mN4bB EQKpRf1M/fwNMJLIkye0GhgVnqLwRa0nBKlB2virV/qUG2ku1IC4JEHLLQER59UKmdh6 zeMmz0m7vv1jwHzeceQpQSZJCRoBPwcDs04uqHgyV/UfiWyDks9ite/9PCz7RSB31bl3 2DcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IyR6jb3K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id j5-20020adfe505000000b0031fd849e797sm8761303wrm.105.2023.11.06.03.10.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:10:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Thomas Huth , Vikram Garhwal , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pavel Pisa Subject: [PULL 58/60] MAINTAINERS: Add the CAN documentation file to the CAN section Date: Mon, 6 Nov 2023 12:03:30 +0100 Message-ID: <20231106110336.358-59-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Thomas Huth Add can.rst to the corresponding section in MAINTAINERS, so that the maintainers get CC:-ed on corresponding patches. Signed-off-by: Thomas Huth Reviewed-by: Vikram Garhwal Reviewed-by: Philippe Mathieu-Daudé Acked-by: Pavel Pisa Message-ID: <20231027060931.242491-1-thuth@redhat.com> [PMD: Fixed typo in subject] Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3014e768f7..c57868c94c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2588,6 +2588,7 @@ W: https://canbus.pages.fel.cvut.cz/ F: net/can/* F: hw/net/can/* F: include/net/can_*.h +F: docs/system/devices/can.rst OpenPIC interrupt controller M: Mark Cave-Ayland From patchwork Mon Nov 6 11:03:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741341 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1027109wrr; Mon, 6 Nov 2023 03:17:50 -0800 (PST) X-Google-Smtp-Source: AGHT+IENa6whG8ScYPdp7egsuv4x5cY0wuCVt+/dBfN3w6VzAVGi0mqWYyeYo+Ki0chLyaGZHL3V X-Received: by 2002:a05:620a:254e:b0:77a:43a6:1183 with SMTP id s14-20020a05620a254e00b0077a43a61183mr18772457qko.45.1699269470450; Mon, 06 Nov 2023 03:17:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699269470; cv=none; d=google.com; s=arc-20160816; b=Itb68ZZb6U4SMNYuxV35L/vlB2OHPrsdv7SXV4yIWH6zs9/v4Wqn3jphgCMoa5MzpM Gr3TAIz4KE0MS9s0uQcNc52XGtfEFnUA9nGmTeQc+YZ8UjJ2i5eEnyzkewlCACe7pox0 XcHlTQX7Il4DVDTnDjKb/XxGznAtOFHZEHRrpZO0qDJ34mZwirbFz4QTcCOIKj2gkRuO qo39cOy1+UTHjjVG+I1Y+uqyeS4JDkOrxj3XYHpekP3ZLrLTmXLQA6BsDTxO/aRaKNj+ dJH4m45d/CesV/ZJYIVwO0Vf4J41wYvf27xfo7lTLW1p0q6oeatnTqNyDDx8ckFjQeIH bGAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RacUCXaZM0ryRlMszwI6IYYuk8+9tjRt89OkiSY3LIw=; fh=oweprlIPI+Wl0nooSfyV1b8Ww9lY57oEY/HLFECOUGE=; b=wIxF28EyUIhvMHNDsSSw5ZeHO8tDH9QOoSXy4V51NS634eS+lg2XAf3gUsGXrGZGAO YYAGuBypDT++5Y/FxBU4FC2JQFWOSqSy85oKvmxFi+W4wfcveEqGOYqPNz9XPcB44YmJ eO9cbAvg0P3CNWw4kXAcEQ0V3aREcSyahSEGayUxiEkHllvDkzHt6GTHeABaBZrjRmOn QzBWa8B9KQda8p2NYrBsHChNGloUqN9HJFlYJCUHE1fsmJh9oIL8Q9d/ZTbGeqMV88cb jZlCFPyULWIW8LlTCJwqdAkJZVtsdd7GxjP1Ysu2u0zp4LEeOXrQWQI2NoUIVaEOElnA lHSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EzBOi4Pf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id c12-20020a05600c0a4c00b0040775501256sm12046304wmq.16.2023.11.06.03.10.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:10:18 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PULL 59/60] MAINTAINERS: update libvirt devel mailing list address Date: Mon, 6 Nov 2023 12:03:31 +0100 Message-ID: <20231106110336.358-60-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Daniel P. Berrangé Effective immediately, the libvirt project has moved its list off libvir-list@redhat.com, to devel@lists.libvirt.org Signed-off-by: Daniel P. Berrangé Message-ID: <20231027095643.2842382-1-berrange@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index c57868c94c..3582e2a71a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4049,7 +4049,7 @@ F: gitdm.config F: contrib/gitdm/* Incompatible changes -R: libvir-list@redhat.com +R: devel@lists.libvirt.org F: docs/about/deprecated.rst Build System From patchwork Mon Nov 6 11:03:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 741359 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1032146wrr; Mon, 6 Nov 2023 03:31:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IGLIWSNW7nQx3MAnanP6P72GMcUIzM+YzBbrImOI8QF1Llou/P4QuX1qPx9VB4mvWMqc4FQ X-Received: by 2002:a05:6808:1a13:b0:3b2:ea7c:c402 with SMTP id bk19-20020a0568081a1300b003b2ea7cc402mr38518133oib.25.1699270278172; Mon, 06 Nov 2023 03:31:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699270278; cv=none; d=google.com; s=arc-20160816; b=empz9YZQGEv63k/qN1ejZjHUE4ac6VscVqXmk6jXfoCuZXIdsQB4YfY1qpd96Ru+rY P3o01dTA+b1MUylqBVVMZ751SCkOf7IiqlM672GH2UkBbvvDru+I2tbfalPvlo6B9FO8 7Px/RqF+4ipr5dYr39OGdpNiNB8FsJka3bN2HcFxseiUzfWiM1yJATL+nzUuOAM+JwzJ FuxxUX8x1feVUFvSmaXR6MCRQ3fasmf/Uqu//4Io+d8piwJ+tRsAIlpWyjpL2mhuPnpV vPvp8DkBRaPnQTY40q4ft8SWoEb9g5vKZaHqJJzcpw1etvB/GvErwNK6IU8qsNE1e1/W KbGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xBR3Oh8zClbS1YQ62m6eKxWZ4Ons8qsU0E4Liv4Rvg0=; fh=n+HI8/qt2hcAyDbOPUJmovNrVwvQ8IAB0JpjjDffKak=; b=H5GpptIvR7tUMEKAAXPF98NUGUKh08zK7rbQCIxe7EEqYDME38Mdg1ZPZt+Hv/9nSl lIGtLccE3HmJpNgIWZBTr4PF7lwaH1YuVoEjHEF8Gd+6sO7y08EREK+VGpvvVQEIQDKm 6IGbvkJEahmM/8nCoJ7jfVpZxZJgw/KjaeITnBIJrJ0xBWIZu9xGw0fAfYF205yOqnuQ GQFpG6bsiiWeKeq6O68wqRcRoyAqS0gX3LCBMibryBzEb3IrT2IPWjgq6SRAIR8RYe/1 /0bgmBTEh/TIxzKgUS24PyRxQGejJcfrTNX/B5n4mvU1cvn9SoPXL8pHFwQQ2T1bMaqt +fNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zDz4nNo5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id bh7-20020a05600c3d0700b00401b242e2e6sm11965729wmb.47.2023.11.06.03.10.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:10:24 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Adrian Wowk , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Gerd Hoffmann Subject: [PULL 60/60] ui/sdl2: use correct key names in win title on mac Date: Mon, 6 Nov 2023 12:03:32 +0100 Message-ID: <20231106110336.358-61-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12f; envelope-from=philmd@linaro.org; helo=mail-lf1-x12f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Adrian Wowk Previously, when using the SDL2 UI on MacOS, the title bar uses incorrect key names (such as Ctrl and Alt instead of the standard MacOS key symbols like ⌃ and ⌥). This commit changes sdl_update_caption in ui/sdl2.c to use the correct symbols when compiling for MacOS (CONFIG_DARWIN is defined). Unfortunately, standard Mac keyboards do not include a "Right-Ctrl" key, so in the case that the SDL grab mode is set to HOT_KEY_MOD_RCTRL, the default text is still used. Signed-off-by: Adrian Wowk Acked-by: Marc-André Lureau Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20231030024119.28342-1-dev@adrianwowk.com> Signed-off-by: Philippe Mathieu-Daudé --- ui/sdl2.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/ui/sdl2.c b/ui/sdl2.c index fbfdb64e90..4971963f00 100644 --- a/ui/sdl2.c +++ b/ui/sdl2.c @@ -172,11 +172,19 @@ static void sdl_update_caption(struct sdl2_console *scon) status = " [Stopped]"; } else if (gui_grab) { if (alt_grab) { +#ifdef CONFIG_DARWIN + status = " - Press ⌃⌥⇧G to exit grab"; +#else status = " - Press Ctrl-Alt-Shift-G to exit grab"; +#endif } else if (ctrl_grab) { status = " - Press Right-Ctrl-G to exit grab"; } else { +#ifdef CONFIG_DARWIN + status = " - Press ⌃⌥G to exit grab"; +#else status = " - Press Ctrl-Alt-G to exit grab"; +#endif } }