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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d5-20020adff2c5000000b0032da6f17ffdsm9752176wrp.38.2023.11.06.07.32.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 07:32:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/12] hw/arm/virt: fix PMU IRQ registration Date: Mon, 6 Nov 2023 15:32:27 +0000 Message-Id: <20231106153238.1426649-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106153238.1426649-1-peter.maydell@linaro.org> References: <20231106153238.1426649-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Sebastian Ott Since commit 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic") PMU IRQ registration fails for arm64 guests: [ 0.563689] hw perfevents: unable to request IRQ14 for ARM PMU counters [ 0.565160] armv8-pmu: probe of pmu failed with error -22 That commit re-defined VIRTUAL_PMU_IRQ to be a INTID but missed a case where the PMU IRQ is actually referred by its PPI index. Fix that by using INTID_TO_PPI() in that case. Fixes: 9036e917f8 ("{include/}hw/arm: refactor virt PPI logic") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1960 Signed-off-by: Sebastian Ott Reviewed-by: Peter Maydell Message-id: 475d918d-ab0e-f717-7206-57a5beb28c7b@redhat.com Signed-off-by: Peter Maydell --- hw/arm/virt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 92085d2d8fb..0a16ab30958 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -631,7 +631,8 @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms) qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", compat, sizeof(compat)); qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", - GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); + GIC_FDT_IRQ_TYPE_PPI, + INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags); } } From patchwork Mon Nov 6 15:32:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 741409 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1151581wrr; Mon, 6 Nov 2023 07:33:49 -0800 (PST) X-Google-Smtp-Source: AGHT+IFCOrRegbu/FR38K6pHCxmRk8sT4Uu9xDXvvcW56zUgIYpa+rR/ZqRjqjYTI/JEHR/KfJvw X-Received: by 2002:a05:620a:45a2:b0:775:9f94:16f1 with SMTP id bp34-20020a05620a45a200b007759f9416f1mr15760922qkb.22.1699284829110; Mon, 06 Nov 2023 07:33:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699284829; cv=none; d=google.com; s=arc-20160816; b=stUwD701WiFfSnO/6ydlE1SySFOHR+Vk8nn/vIKpS/VL8fvsPV8G3PBHHZ757cIyFO TM602kwixMp0bGyW+bOnRv738Iehk/Q6F03aXdyd1QDtzNRMQQvj5Ed+gK8Vphfb75WX tn6Yvy2I1/kHgK8Bnm4DlRWp8pgUKs4MwnojOwjMb6aPjBEvEkHWBrDxFPes5hWtJaRD NhfxOytJe4y/giEsGr8d8/9Z3JI4yioEudx3Qlq5gNESBzm+GcKDNB67xpc0EKXT+y73 /MmUhqsaVTENlcQMzSGnplJ14tVpiNFQZ4Iw1rJwarLqwn9xIKzaSXyqMw02hMUi65Y9 A+uQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=96tTRZzTo5lzHBefnnTujQF6PrCnnI8GATKXvxfKeEQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=zY3Lai0cfv4W3HypdF6QpiIccAvoifw5vYjrzgYN0E9WSUdEEdfYbkxotA4Fq8YlCa t+owTrebEsr8LPz05DFWzKYjQ+XOUw7ifkD8/ZjlDhEzhab/MdpQOmnsyjMPmt3AKutW uPna1sP6ew/ccfkopBcYpUwmzXXXrk9keMQDpG0XVzi+Z4yF4461Yx+XNMd2NBQJuk/F i2oyZ/y/s7Iu9Ho/sk8Y8nP1bpEIo1Dl6Eq7cS3hBuQXmwtz6n7Dm+GlcMkWckwDnb9m 9pWzNhZWW3bHcZCpxQGtc9MmY+9loB5wZV7hqoQIsueZfidt5pM6FgqNv5Skr0BdBsWa UE+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zWqjR1dd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d5-20020adff2c5000000b0032da6f17ffdsm9752176wrp.38.2023.11.06.07.32.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 07:32:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/12] tests/qtest/bios-tables-test: Allow changes to virt SPCR and DBG2 Date: Mon, 6 Nov 2023 15:32:28 +0000 Message-Id: <20231106153238.1426649-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106153238.1426649-1-peter.maydell@linaro.org> References: <20231106153238.1426649-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Allow changes to the virt board SPCR and DBG2 -- we are going to fix an error in the UART descriptions there. Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8bf..6673e2c4c13 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,3 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/SPCR", +"tests/data/acpi/virt/DBG2", From patchwork Mon Nov 6 15:32:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 741411 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1151846wrr; Mon, 6 Nov 2023 07:34:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IGOOWKyUlSIcIJiQ0feHFVMYXW/4Pr/RN9GNqmUCy4cwGxpU3XyfprK5JbPkxcYFtu50bzH X-Received: by 2002:a05:6214:f6c:b0:671:9c02:cbaa with SMTP id iy12-20020a0562140f6c00b006719c02cbaamr26462002qvb.39.1699284860224; Mon, 06 Nov 2023 07:34:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699284860; cv=none; d=google.com; s=arc-20160816; b=VPTQC3ub8uEFQPql+6hT/cvi2CvhC6/F0V3usvzrMre61cxdPRnxhhBj5AizCzkEeS YaX7JeF8s2jt7PBKFxy8JzDPxz7zX+4wgS+H2qLI2XW4RbE9qwKVWXzrJfIZ9zcn5kG9 SuUB06QuhL8pHk3oqpO3lv8MJb8qGRUXZXdmBCqJXTxkEFzYUMLTOFRiFsORn1mYHV17 D6Ub8wtFfjAPzb3cwV84A8Ncf407BUEAusCB/7g3SkdOUhoOgTdbveNhbWB8U9Ij83pR 02CWFWAODyNtmKzEniICLIFN4nAtSHYMd/oTjIp9IPzw7FTd479ibLJHGLM+wnYk8MN+ u4bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=o46GjiNGnFh5PFXpDP7cZHY+Rtqpr/iySpofJQGEQas=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=CvZizdY9OTWFhxr79GfKMTKQn3eXfIjK377Pd9IUYNdtIE7nOA5Nf5laV7dx9qPur4 Fx9VJyJR1pj9CVe0G/uhyCfFyDTJ7lsRaTjqK3PLzBkvFLKtaLH9xpNHQVDCTu1kvUeh /Lvn6+27P94pIgomgqQnS1B7AlLQ7/DUAPCBRFYjswRM1cgidVGNIKstTrhx4QH3+G0X dxmLkNrkQgeRbxFovlUyb5OcLUw9OHF6+FgpP0Neu92f8gCFf7jMAElU2mw8YbFyP8DP /pr0GhIA3Mc+zGDv5osG710NleKq9PowF3oVAL0tGn3xds6Z5pHpEhUlVhMo97P03p2w Hfqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Mp17wgKJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d5-20020adff2c5000000b0032da6f17ffdsm9752176wrp.38.2023.11.06.07.32.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 07:32:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/12] hw/arm/virt: Report correct register sizes in ACPI DBG2/SPCR tables. Date: Mon, 6 Nov 2023 15:32:29 +0000 Message-Id: <20231106153238.1426649-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106153238.1426649-1-peter.maydell@linaro.org> References: <20231106153238.1426649-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Udo Steinberg Documentation for using the GAS in ACPI tables to report debug UART addresses at https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table states the following: - The Register Bit Width field contains the register stride and must be a power of 2 that is at least as large as the access size. On 32-bit platforms this value cannot exceed 32. On 64-bit platforms this value cannot exceed 64. - The Access Size field is used to determine whether byte, WORD, DWORD, or QWORD accesses are to be used. QWORD accesses are only valid on 64-bit architectures. Documentation for the ARM PL011 at https://developer.arm.com/documentation/ddi0183/latest/ states that the registers are: - spaced 4 bytes apart (see Table 3-2), so register stride must be 32. - 16 bits in size in some cases (see individual registers), so access size must be at least 2. Linux doesn't seem to care about this error in the table, but it does affect at least the NOVA microhypervisor. In theory we therefore have a choice between reporting the access size as 2 (16 bit accesses) or 3 (32-bit accesses). In practice, Linux does not correctly handle the case where the table reports the access size as 2: as of kernel commit 750b95887e5678, the code in acpi_parse_spcr() tries to tell the serial driver to use 16 bit accesses by passing "mmio16" in the option string, but the PL011 driver code in pl011_console_match() only recognizes "mmio" or "mmio32". The result is that unless the user has enabled 'earlycon' there is no console output from the guest kernel. We therefore choose to report the access size as 32 bits; this works for NOVA and also for Linux. It is also what the UEFI firmware on a Raspberry Pi 4 reports, so we're in line with existing real-world practice. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1938 Signed-off-by: Udo Steinberg Reviewed-by: Peter Maydell [PMM: minor commit message tweaks; use 32 bit accesses] Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 9ce136cd88c..8bc35a483c9 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -482,7 +482,7 @@ build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) build_append_int_noprefix(table_data, 3, 1); /* ARM PL011 UART */ build_append_int_noprefix(table_data, 0, 3); /* Reserved */ /* Base Address */ - build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1, + build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3, vms->memmap[VIRT_UART].base); /* Interrupt Type */ build_append_int_noprefix(table_data, @@ -673,7 +673,7 @@ build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) build_append_int_noprefix(table_data, 34, 2); /* BaseAddressRegister[] */ - build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1, + build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3, vms->memmap[VIRT_UART].base); /* AddressSize[] */ From patchwork Mon Nov 6 15:32:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 741414 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1152126wrr; Mon, 6 Nov 2023 07:34:51 -0800 (PST) X-Google-Smtp-Source: AGHT+IGbZkMMSBJ+Ev0T4O8fXUeH75bQC98toBK3YOSsbMbsnFBrxTy+d9eCDBDYo0RHUnp2wLHu X-Received: by 2002:a05:6830:25c1:b0:6bc:f6d0:87d9 with SMTP id d1-20020a05683025c100b006bcf6d087d9mr37750532otu.5.1699284890812; Mon, 06 Nov 2023 07:34:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699284890; cv=none; d=google.com; s=arc-20160816; b=i0EsbBsV/e18H23pBcy46gtoF4rdHekx1FARcJKGaYtIo4jQAVErmT5kX5NQSNkzoS +iwGxAKzkwcTktRh7k/S49bkfVuRB4QjJXJ2GxsaUBNfsZWkV6fu40gRTcSQdwF6Fjam aCx0Q6oE5hhGwR1XWqd9iuwnuppxt5tHsuwEe6aJUxYd3sUFAo9eNxsjSwvWlYtv0hdM Q922b4Adymn9AIZSyRQnKEn2YVJhU0Q05dnjbTXEZ+C07pSgwP1jsXjlZKpzaCS08P7/ JjVjn/iqL3bWaYSG+Yv9+H3uZFW76BkUWWTJaP59Rf92aZ/IOflJNHf/GjvaSzJhwdzR FAUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=2rKfc6wYyTa7eaGHPKOB3cQ0P9rjkcJ/4gZBc+bTbwo=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=X625bv9cztSeDQRMZa9rsRCQ65tnPNY594Zp6kwIfcjCfIqMM+/Lv4oJgsSLt3K8wn B6/d/9A2dW4X0kZIjAfBmtVATXrwOj3BmeBSHNmnI7Mc5ctI6uPLiMvvSS97InsPf9Sh TOBvG8ycwp6VXA6qiAxaFWWHDQiFU1An+8mP7a408IRM737H7NSIchkMvx/ztkQqo5rl QnVEy5H34X+bar9reRuQN4Na4fxeWluknsaqh+o05uA6+29SuzKqrHb/2lJ8ALa6uuX0 zS8QV+4c5hWnRmlVcdQsXAD5Ug1+hIqO92hWHySZ33BH4Ntzw20e1P034pUcRfSWjCTn A29Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Y3G7Jy3Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d5-20020adff2c5000000b0032da6f17ffdsm9752176wrp.38.2023.11.06.07.32.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 07:32:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/12] tests/qtest/bios-tables-test: Update virt SPCR and DBG2 golden references Date: Mon, 6 Nov 2023 15:32:30 +0000 Message-Id: <20231106153238.1426649-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106153238.1426649-1-peter.maydell@linaro.org> References: <20231106153238.1426649-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Update the virt SPCR and DBG2 golden reference files to have the fix for the description of the UART. Diffs from iasl: @@ -1,57 +1,57 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/SPCR, Fri Nov 3 14:12:06 2023 + * Disassembly of /tmp/aml-E6YUD2, Fri Nov 3 14:12:06 2023 * * ACPI Data Table [SPCR] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table] [004h 0004 4] Table Length : 00000050 [008h 0008 1] Revision : 02 -[009h 0009 1] Checksum : CB +[009h 0009 1] Checksum : B1 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 1] Interface Type : 03 [025h 0037 3] Reserved : 000000 [028h 0040 12] Serial Port Register : [Generic Address Structure] [028h 0040 1] Space ID : 00 [SystemMemory] -[029h 0041 1] Bit Width : 08 +[029h 0041 1] Bit Width : 20 [02Ah 0042 1] Bit Offset : 00 -[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8] +[02Bh 0043 1] Encoded Access Width : 03 [DWord Access:32] [02Ch 0044 8] Address : 0000000009000000 [034h 0052 1] Interrupt Type : 08 [035h 0053 1] PCAT-compatible IRQ : 00 [036h 0054 4] Interrupt : 00000021 [03Ah 0058 1] Baud Rate : 03 [03Bh 0059 1] Parity : 00 [03Ch 0060 1] Stop Bits : 01 [03Dh 0061 1] Flow Control : 02 [03Eh 0062 1] Terminal Type : 00 [04Ch 0076 1] Reserved : 00 [040h 0064 2] PCI Device ID : FFFF [042h 0066 2] PCI Vendor ID : FFFF [044h 0068 1] PCI Bus : 00 [045h 0069 1] PCI Device : 00 [046h 0070 1] PCI Function : 00 [047h 0071 4] PCI Flags : 00000000 [04Bh 0075 1] PCI Segment : 00 [04Ch 0076 4] Reserved : 00000000 Raw Table Data: Length 80 (0x50) - 0000: 53 50 43 52 50 00 00 00 02 CB 42 4F 43 48 53 20 // SPCRP.....BOCHS + 0000: 53 50 43 52 50 00 00 00 02 B1 42 4F 43 48 53 20 // SPCRP.....BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC - 0020: 01 00 00 00 03 00 00 00 00 08 00 01 00 00 00 09 // ................ + 0020: 01 00 00 00 03 00 00 00 00 20 00 03 00 00 00 09 // ......... ...... 0030: 00 00 00 00 08 00 21 00 00 00 03 00 01 02 00 00 // ......!......... 0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ................ @@ -1,57 +1,57 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/DBG2, Fri Nov 3 14:12:06 2023 + * Disassembly of /tmp/aml-V1YUD2, Fri Nov 3 14:12:06 2023 * * ACPI Data Table [DBG2] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "DBG2" [Debug Port table type 2] [004h 0004 4] Table Length : 00000057 [008h 0008 1] Revision : 00 -[009h 0009 1] Checksum : CF +[009h 0009 1] Checksum : B5 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 002B [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 0005 [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [Optional field not present] [036h 0054 2] OEM Data Offset : 0000 [Optional field not present] [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0003 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 0066 12] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] -[043h 0067 1] Bit Width : 08 +[043h 0067 1] Bit Width : 20 [044h 0068 1] Bit Offset : 00 -[045h 0069 1] Encoded Access Width : 01 [Byte Access:8] +[045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 0000000009000000 [04Eh 0078 4] Address Size : 00001000 [052h 0082 5] Namepath : "COM0" Raw Table Data: Length 87 (0x57) - 0000: 44 42 47 32 57 00 00 00 00 CF 42 4F 43 48 53 20 // DBG2W.....BOCHS + 0000: 44 42 47 32 57 00 00 00 00 B5 42 4F 43 48 53 20 // DBG2W.....BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC 0020: 01 00 00 00 2C 00 00 00 01 00 00 00 00 2B 00 01 // ....,........+.. 0030: 05 00 26 00 00 00 00 00 00 80 03 00 00 00 16 00 // ..&............. - 0040: 22 00 00 08 00 01 00 00 00 09 00 00 00 00 00 10 // "............... + 0040: 22 00 00 20 00 03 00 00 00 09 00 00 00 00 00 10 // ".. ............ 0050: 00 00 43 4F 4D 30 00 // ..COM0. Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test-allowed-diff.h | 2 -- tests/data/acpi/virt/DBG2 | Bin 87 -> 87 bytes tests/data/acpi/virt/SPCR | Bin 80 -> 80 bytes 3 files changed, 2 deletions(-) diff --git a/tests/data/acpi/virt/DBG2 b/tests/data/acpi/virt/DBG2 index 86e6314f7b0235ef8ed3e0221e09f996c41f5e98..0a05e1a47f9c303c6a6c9ca8414c62ec4ac90f98 100644 GIT binary patch delta 37 ncmWF!=W=m!HwtF}f~^y|EJYL;n1M`A5T8MSfx+3|*MI>4b2kL{ delta 37 ncmWF!=W=m!HwtF}g7Xu(EJZjN7=cVq5T8MSfx+3|*MI>4bG-!j diff --git a/tests/data/acpi/virt/SPCR b/tests/data/acpi/virt/SPCR index 24e0a579e7d73f432a614380e29aa95113344186..cf0f2b75226515097c08d2e2016a83a4f08812ba 100644 GIT binary patch delta 23 ecmWFt;0g|K4hmpkU|`xfkxQOgfq{9VjtT%gOa!L@ delta 23 ecmWFt;0g|K4hmpkU|>2ukxQPLgMo3PjtT%g(gddf diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index 6673e2c4c13..dfb8523c8bf 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,3 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/virt/SPCR", -"tests/data/acpi/virt/DBG2", From patchwork Mon Nov 6 15:32:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 741413 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1152032wrr; Mon, 6 Nov 2023 07:34:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IETiVhBW3fP1rak8DLBC6T1Rkm9EWIdx9hzRd2C7cNktXHvuVzJtbv07Bsz4P+ewL/QsgXa X-Received: by 2002:a05:6808:308c:b0:3af:709c:1b2b with SMTP id bl12-20020a056808308c00b003af709c1b2bmr36227141oib.32.1699284879933; Mon, 06 Nov 2023 07:34:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699284879; cv=none; d=google.com; s=arc-20160816; b=EWzEFTAS7oZl8VtB3tp46oMpaKSy9yU8WRYS2TPe4hva79ePA5Odq5QHE/Cq0++OuP CKdngvd/q3PLidqP8AtYwCbQw12Hn+AW0jz7lLUV4SFNyU17KxJecTDvTegD/2l3XPxn fiAZSEttHZZAC4KAt7TaT1OXhzUO546TxPTrF5nvYb1VyVzEJgV/kY+wPrbeUrU2ebCT FehRJh6c++tJguRS4LtS3xRMoAtaZIJQCZMBKmvmaj7Dm45GMFqAxBMiaWhoOMSHPEPY 4xu4CjQMi41RraKKqSqAN37Zlp56ZRrndbinzGyh/2RXFIpBcmAOpsR2d+W2do30XZF5 wxaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DvzbelZcKlKoxbHp/373o+tGsWe8jUUsQB+BUCk9XSw=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=cQbCtl/ion3zCjKHUj0C93aDnumIfF584MHpHVSk6v+yaufg5HtP25fbiOvSvxCJd+ Rl1vmc5I99Okncbld/bkVTvDiBWa45thr+1eP47izepOCic1j4MAooxu8hI7hx7rnRpF rrNcvhL+NopprMaaUF+oD/Imd39BGNEvDkLxJNVSiVuGfblPbKYiNRi/GRWeIPiC4TCq nx/iV3xhPYwdHvTrB9MlAh2P7cvxKHNbhCxCTOeMe1/pwg3NOocsXx2EYV6ym2QvPoeT BvWu6l4aUzcYU9Dh8Mwvuzr/LaAeL4PTYAmSr7kYO92FRecWvmimjOdmnScCEC4E4njR NnBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FffpuVr2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d5-20020adff2c5000000b0032da6f17ffdsm9752176wrp.38.2023.11.06.07.32.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 07:32:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/12] hw/i386/intel_iommu: vtd_slpte_nonzero_rsvd(): assert no overflow Date: Mon, 6 Nov 2023 15:32:31 +0000 Message-Id: <20231106153238.1426649-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106153238.1426649-1-peter.maydell@linaro.org> References: <20231106153238.1426649-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Vladimir Sementsov-Ogievskiy We support only 3- and 4-level page-tables, which is firstly checked in vtd_decide_config(), then setup in vtd_init(). Than level fields are checked by vtd_is_level_supported(). So here we can't have level out from 1..4 inclusive range. Let's assert it. That also explains Coverity that we are not going to overflow the array. CID: 1487158, 1487186 Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Peter Maydell Reviewed-by: Maksim Davydov Message-id: 20231017125941.810461-2-vsementsov@yandex-team.ru Signed-off-by: Peter Maydell --- hw/i386/intel_iommu.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 1c6c18622fd..1a44ef696c3 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1045,18 +1045,35 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s, * Rsvd field masks for spte: * vtd_spte_rsvd 4k pages * vtd_spte_rsvd_large large pages + * + * We support only 3-level and 4-level page tables (see vtd_init() which + * sets only VTD_CAP_SAGAW_39bit and maybe VTD_CAP_SAGAW_48bit bits in s->cap). */ -static uint64_t vtd_spte_rsvd[5]; -static uint64_t vtd_spte_rsvd_large[5]; +#define VTD_SPTE_RSVD_LEN 5 +static uint64_t vtd_spte_rsvd[VTD_SPTE_RSVD_LEN]; +static uint64_t vtd_spte_rsvd_large[VTD_SPTE_RSVD_LEN]; static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level) { - uint64_t rsvd_mask = vtd_spte_rsvd[level]; + uint64_t rsvd_mask; + + /* + * We should have caught a guest-mis-programmed level earlier, + * via vtd_is_level_supported. + */ + assert(level < VTD_SPTE_RSVD_LEN); + /* + * Zero level doesn't exist. The smallest level is VTD_SL_PT_LEVEL=1 and + * checked by vtd_is_last_slpte(). + */ + assert(level); if ((level == VTD_SL_PD_LEVEL || level == VTD_SL_PDP_LEVEL) && (slpte & VTD_SL_PT_PAGE_SIZE_MASK)) { /* large page */ rsvd_mask = vtd_spte_rsvd_large[level]; + } else { + rsvd_mask = vtd_spte_rsvd[level]; } return slpte & rsvd_mask; From patchwork Mon Nov 6 15:32:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 741406 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1151480wrr; Mon, 6 Nov 2023 07:33:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IE7Rbb56loOokvvddn5lRaQr4HtOOudk4616W1My19zNggQFV6zAEQwfc7tSDKKrXDGKu8d X-Received: by 2002:a05:622a:1a05:b0:41e:26a1:7b3e with SMTP id f5-20020a05622a1a0500b0041e26a17b3emr36130500qtb.29.1699284818179; Mon, 06 Nov 2023 07:33:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699284818; cv=none; d=google.com; s=arc-20160816; b=GR4bFcqgMLGOv50B4LbRZVJXEDo4ROC+9Qa1sdHKyQKYscextKh+qMzswaKR4DZhh+ asjEDcvJt54hW8oIlDJkr6uQFUda4IpWVk+Ei62tmPjwkRztzqTMhLz1KmOeptD78r42 4MIduwNQDNBVxYqwdXGvHXwdt2k5H5/W0imO2HSasg6kD0q6/tfmKIuaLi9Y10A/xJpH UE6DA7cTeI+yDJSKIDDn7IktnHCMp12ThknLrF8Mqe/8x0VQnfsWJVqsIeu+xlFEFC4V kY6eSiw9qV9HHNfRKNnVHWdBi7lujNLTIih42KKnDgc5FFnN2+bYfliLKRmafhZEqZob zFNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8uZpTC7vfc/gISeKzm+ZO3nrKEzBmGcZTgy+gByZUp0=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=MjnZL2uOjLg6lDfVuL1dE51cF6L0KmOiQdug1uJ6S+5UT6WbrvsZRdMDt7p5qtYhkz wuELGDySUFFnkCqqpktOW1slEMyNi/g5Zy/KyJsLM7u6O1Q+n9pvkty87MdelahJEcI3 V0KRxwev74XXsMcApiR8iaJd0FHD3h6Q5sxQF1iGUlFr5VCulqkO7qfy3eYrM59ietAj PUbovq6dEyhqbK8sBolkx0aG0/x+5BRSGarGGC/TKSJzk268ZE0CDR6IOtgbOZCAZLvw J8YFWXlkUCypHX8nDfzbO1/MHN9dWLizaH8KMHNat9/4ATWs4neWDg5ctjKaFGLX/b36 RNTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=n9sgcm9Q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d5-20020adff2c5000000b0032da6f17ffdsm9752176wrp.38.2023.11.06.07.32.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 07:32:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/12] util/filemonitor-inotify: qemu_file_monitor_watch(): assert no overflow Date: Mon, 6 Nov 2023 15:32:32 +0000 Message-Id: <20231106153238.1426649-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106153238.1426649-1-peter.maydell@linaro.org> References: <20231106153238.1426649-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Vladimir Sementsov-Ogievskiy Prefer clear assertions instead of [im]possible array overflow. Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Peter Maydell Reviewed-by: Maksim Davydov Message-id: 20231017125941.810461-3-vsementsov@yandex-team.ru Signed-off-by: Peter Maydell --- util/filemonitor-inotify.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/util/filemonitor-inotify.c b/util/filemonitor-inotify.c index 2c45f7f1764..2121111f38b 100644 --- a/util/filemonitor-inotify.c +++ b/util/filemonitor-inotify.c @@ -81,16 +81,25 @@ static void qemu_file_monitor_watch(void *arg) /* Loop over all events in the buffer */ while (used < len) { - struct inotify_event *ev = - (struct inotify_event *)(buf + used); - const char *name = ev->len ? ev->name : ""; - QFileMonitorDir *dir = g_hash_table_lookup(mon->idmap, - GINT_TO_POINTER(ev->wd)); - uint32_t iev = ev->mask & - (IN_CREATE | IN_MODIFY | IN_DELETE | IN_IGNORED | - IN_MOVED_TO | IN_MOVED_FROM | IN_ATTRIB); + const char *name; + QFileMonitorDir *dir; + uint32_t iev; int qev; gsize i; + struct inotify_event *ev = (struct inotify_event *)(buf + used); + + /* + * We trust the kenel to provide valid buffer with complete event + * records. + */ + assert(len - used >= sizeof(struct inotify_event)); + assert(len - used - sizeof(struct inotify_event) >= ev->len); + + name = ev->len ? ev->name : ""; + dir = g_hash_table_lookup(mon->idmap, GINT_TO_POINTER(ev->wd)); + iev = ev->mask & + (IN_CREATE | IN_MODIFY | IN_DELETE | IN_IGNORED | + IN_MOVED_TO | IN_MOVED_FROM | IN_ATTRIB); used += sizeof(struct inotify_event) + ev->len; From patchwork Mon Nov 6 15:32:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 741417 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1152912wrr; Mon, 6 Nov 2023 07:36:30 -0800 (PST) X-Google-Smtp-Source: AGHT+IHIDdmUiSehQ+WrCIR4+S0Jbp90UyYu2TI94evkCOZ2ksKrWf3ap4zlgXONjoyA4xEXfNzi X-Received: by 2002:a05:6214:1d23:b0:66d:994b:8703 with SMTP id f3-20020a0562141d2300b0066d994b8703mr38012964qvd.7.1699284990676; Mon, 06 Nov 2023 07:36:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699284990; cv=none; d=google.com; s=arc-20160816; b=0jOLgVbUXgUZc5mhMMeoZmUejVLOZdpIldUfQIVWWyT1iBqhYDgDXWA7VamS3KLtWf PFsAIAk36mgmrKizUFHhNbnBIDzlochr8LyGNl/Rrc6hyt45TFs9Y7PIxwJa4uY6WRNP 7KU+yINLmygB7CHp/4tYGH2iFm44OhqwEFzLbEyVGQp2Q3PaA5TgkAaY4XZPJPHZv9iZ 6rqaC+ZYL7zBxiXwZk2qNZuuki2HAt/IuAho8iQ47gwt4DRIrhJD1cBakeO5DXuCcUMx 9cRVX0LT9ci4yER9z+fNj97kXKKbBYIcClO5hvSbs/UISdbcLPVyQDlW8wWkTTGO1z6p WASQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FyfVKDCKSbX1qCn7TkWmEojEjptuQVtP+7ASpyyGWlA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=qJhdTJoykxXn3Vghj2EAOCGP2NM2QMOE+ydw4B4hbxhGkNNnTVCQNHElvsUoID9Tjm AdfAZ5lfa4ny+GpWnzSbOJHbunINAnlN6fmuoWydCmG/dwWbg9OvPuHsPXm6j5HT8Znh QK7/NJd98n7ckV/vHwpjzZZge1P03fnJ5AvMJHr5HoIpEV0qTPiFOXqAeVYyNRgB4D77 tVBURl8UiCe76R16UGxV9jaia/RIaUe0dwhpadPchVkLhoOc+ABFbXqz9oUS1QBrq587 56VmbxoD3gnKYB42Eb59PqeH0BOCys2HTarpaAMbg/nojq81u1OMohd2CDjFphu8tH+C pfww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UeTsLrCn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d5-20020adff2c5000000b0032da6f17ffdsm9752176wrp.38.2023.11.06.07.32.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 07:32:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/12] mc146818rtc: rtc_set_time(): initialize tm to zeroes Date: Mon, 6 Nov 2023 15:32:33 +0000 Message-Id: <20231106153238.1426649-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106153238.1426649-1-peter.maydell@linaro.org> References: <20231106153238.1426649-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Vladimir Sementsov-Ogievskiy set_time() function doesn't set all the fields, so it's better to initialize tm structure. And Coverity will be happier about it. Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Peter Maydell Reviewed-by: Maksim Davydov Message-id: 20231017125941.810461-4-vsementsov@yandex-team.ru Signed-off-by: Peter Maydell --- hw/rtc/mc146818rtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c index c27c362db9e..2d391a83969 100644 --- a/hw/rtc/mc146818rtc.c +++ b/hw/rtc/mc146818rtc.c @@ -599,7 +599,7 @@ static void rtc_get_time(MC146818RtcState *s, struct tm *tm) static void rtc_set_time(MC146818RtcState *s) { - struct tm tm; + struct tm tm = {}; g_autofree const char *qom_path = object_get_canonical_path(OBJECT(s)); rtc_get_time(s, &tm); From patchwork Mon Nov 6 15:32:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 741412 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1152003wrr; Mon, 6 Nov 2023 07:34:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IHkoGR+qi9MmhzE/wYrArdaR8UXy59bh2uQ3keSJEwuHu6koN95JjAEKgQe5x6zvS717Gc5 X-Received: by 2002:a05:6102:1042:b0:45d:91b2:99c7 with SMTP id h2-20020a056102104200b0045d91b299c7mr7636435vsq.32.1699284875738; Mon, 06 Nov 2023 07:34:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699284875; cv=none; d=google.com; s=arc-20160816; b=b4eLfeRuT7cDsOvISDZApdfuC8kh0Bjd4w4pG6t/nBT1QgnojKeMvv3jvl5suXCDDJ 3uAx9N7CW9h6ZtA4JXxlGJjcPNQCraDFbW73GvFAJaJBJXQQxM3dFot3O3NCSNW7Feh4 AFJu9LDmlUnEhBflHIccnRJNbSenuclsWAghtiLU+Qne46OXm4KDwegKmOva4McYDVzB 8oQtp/ZxdLc/dzfzPnfnPCYx2RUD4hmUqU/lKB+LkRTEuWtZHkHYBxOaW5sIoVaD6LcF fGApGXdpL4XyxlCe5tddXhF2fT/tnk+Jk6YQA1865oc933pV7Go9t6FnNpXiNDAarK8F wRCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nlNPCN/IoODLnyMcuMdcFvSi7ZKXsxk62aEPG2/TY9M=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=HtGZOLfVts+f6/BWY6BMLgxoymKDEe/YdhRXFcJmpvw7yvhXEHco7JR4Lg1hrgAduY qA7BKMkphR0lk6e0dyM5yEXr79fsXB9t1NbAUHH/F/mxYra5Mk9sXYGKKOcdHjCVoA5A 7sdz+VJMoQ6V2z2DgVMxbP0LSJ8B7mQvttHj6Prd4fi/EquCWgvdE0ok28r9QTih6fXq NKfhtUMFZsCB03rfNkkosEQWzQg0mOuSJkKbauB3zU1Vm1BuxEVfVJKFq440LyEApDON WbSqTegr7+ocqFD1EcTQ5/zQ1XCqdrfIn9F0QeOqpYfFPrg+noFSfPS5XkD6qAkI1nqV GYCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ObA0z+6v; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d5-20020adff2c5000000b0032da6f17ffdsm9752176wrp.38.2023.11.06.07.32.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 07:32:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/12] block/nvme: nvme_process_completion() fix bound for cid Date: Mon, 6 Nov 2023 15:32:34 +0000 Message-Id: <20231106153238.1426649-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106153238.1426649-1-peter.maydell@linaro.org> References: <20231106153238.1426649-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Vladimir Sementsov-Ogievskiy NVMeQueuePair::reqs has length NVME_NUM_REQS, which less than NVME_QUEUE_SIZE by 1. Fixes: 1086e95da17050 ("block/nvme: switch to a NVMeRequest freelist") Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Stefan Hajnoczi Reviewed-by: Maksim Davydov Message-id: 20231017125941.810461-5-vsementsov@yandex-team.ru Signed-off-by: Peter Maydell --- block/nvme.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/block/nvme.c b/block/nvme.c index 96b3f8f2fa1..0a0a0a6b36c 100644 --- a/block/nvme.c +++ b/block/nvme.c @@ -417,9 +417,10 @@ static bool nvme_process_completion(NVMeQueuePair *q) q->cq_phase = !q->cq_phase; } cid = le16_to_cpu(c->cid); - if (cid == 0 || cid > NVME_QUEUE_SIZE) { - warn_report("NVMe: Unexpected CID in completion queue: %"PRIu32", " - "queue size: %u", cid, NVME_QUEUE_SIZE); + if (cid == 0 || cid > NVME_NUM_REQS) { + warn_report("NVMe: Unexpected CID in completion queue: %" PRIu32 + ", should be within: 1..%u inclusively", cid, + NVME_NUM_REQS); continue; } trace_nvme_complete_command(s, q->index, cid); From patchwork Mon Nov 6 15:32:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 741416 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1152742wrr; Mon, 6 Nov 2023 07:36:05 -0800 (PST) X-Google-Smtp-Source: AGHT+IFAKybDLU3JcDMYRyJsLXPC4ebDSYU95N0jEBNJWtOQ+NAgS360LXYdw7kNPJHTmGy94k4o X-Received: by 2002:a05:6830:168c:b0:6c4:cda6:ff31 with SMTP id k12-20020a056830168c00b006c4cda6ff31mr25522961otr.15.1699284965180; Mon, 06 Nov 2023 07:36:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699284965; cv=none; d=google.com; s=arc-20160816; b=QXnRHqPqeIt4cwWhQcdx+V5UmyKvUOKIZxpkEfmqS+vncXixnYCnfTgh0F4XDaDhAV lgj2Cyq4GkjRfNFLIUh//7mZA5EJUuobBpeyHXNGidyGjjswbnV6EMLb7HUleF27sG+1 6wm4GalOuztLkTrTaoGScnxAjyOxzJeaTVKLdfrtBVu/zO1uMwg8FcfNfRtzbwi2uzV5 2gk/qo2UYa1oiKlB7ycK8DSnHhRKOOw0iyAEQB2gptVWmi3TAoKPdk/po0hmZjWbfWDA NZ7Q79oLiqvbeHva5JXBmxB9U2xV3sdjv3XSRRbu7yFytsqOJ+dv8LKkw59cFMbCbjWW IwQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wE3VrpMqQ5iO8rOEAjV8Na1iX3YBEUPnu4z7701xXsQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Hmm09W8GrItJU36tHzksKmIP3swVkKACfFlEAaI3NmmO6SeKZ+RnncQb911EAG1o9M vzPpYcUAEJC/GwYxmPqtancEJmOwdAfZaMeu4TotudEjbIK4UGG2Al5lBoQCPUXuD/3u Puj26hXEC7m9eDcp4jyMCsRGLd8MMem5cK9d6XEAeFSlDnAz7jI9yh8HE6U9cGNttfXY eUJF80hJi7aeqMHaPj5kZkwkyFHdtVtIJmhE6rQjPw3u6y5hJut6ez5Qlaz2FFfbkEWs myEIVpliqJ+eBw08Wr9Ql0JZ3/qckPUrw14G5UxINc5g6yUVUPJUDEDu2/bLJIQMtCnO 5yFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s7bd05mj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d5-20020adff2c5000000b0032da6f17ffdsm9752176wrp.38.2023.11.06.07.32.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 07:32:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/12] hw/core/loader: gunzip(): initialize z_stream Date: Mon, 6 Nov 2023 15:32:35 +0000 Message-Id: <20231106153238.1426649-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106153238.1426649-1-peter.maydell@linaro.org> References: <20231106153238.1426649-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Vladimir Sementsov-Ogievskiy Coverity signals that variable as being used uninitialized. And really, when work with external APIs that's better to zero out the structure, where we set some fields by hand. Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Peter Maydell Reviewed-by: Maksim Davydov Message-id: 20231017125941.810461-6-vsementsov@yandex-team.ru Signed-off-by: Peter Maydell --- hw/core/loader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/core/loader.c b/hw/core/loader.c index 4dd5a71fb79..b7bb44b7f7c 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -558,7 +558,7 @@ static void zfree(void *x, void *addr) ssize_t gunzip(void *dst, size_t dstlen, uint8_t *src, size_t srclen) { - z_stream s; + z_stream s = {}; ssize_t dstbytes; int r, i, flags; From patchwork Mon Nov 6 15:32:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 741408 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1151580wrr; Mon, 6 Nov 2023 07:33:49 -0800 (PST) X-Google-Smtp-Source: AGHT+IEko5F9mhd50RDain5oOpDDaqxuzomDtQ5L8jm17l5Hy5OVmEBEjDkO7ZR+rFGUPSJ60znr X-Received: by 2002:a05:620a:4686:b0:76f:2f7b:cf61 with SMTP id bq6-20020a05620a468600b0076f2f7bcf61mr34304773qkb.61.1699284829093; Mon, 06 Nov 2023 07:33:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699284829; cv=none; d=google.com; s=arc-20160816; b=boShB8JTKEvgYzEk3xIndcW511jCBK1PnfG0OeE+5tXdnD/Px9SH+1W9ehCIJRZGWy orgfmrqyQUevr5FxT0aU+n+CjFFPF1psvY0GlpsnvS6kgNbqH2VFI/TAXTEg3SP2LQTL NSeCAcZmYnO7Wfc0/97sxKUUqEHk1aTZ9sQ+T/4fRnIQioZJGVAZdrnqY9nwlnV9JReF RHOMXdKZjSg/70jK7i9kXGAx59yOmV7SKT0MLwcr9oi/r3WVu0WpHZD3koUCNenMg+PH r8uqzWn9qYnsZmAkEUyX2MpI/UNaB5cHau9/UN3sDsbqDuYzbftBqGs1a9+w7QhCvesk aidg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QiKPJfj6026HtJyHgqnn8HlAlq2ojaeDiEbXyPDrg7Y=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=pHeooxjC8KspiJcqUnXp0FgdyIDNCxvBcuthQqdS2eI00cAC+sAIaIXbzU/DdsxLz/ zMCCGY0Ae5V25A64xDUCa2QJVhx9N7GWbWCqVLV/hRwrwUwU53UvMZITizjlUbZpLKGK oqEopfb9sF+yZPNl9h3JM2pHiP25zhWINxbIxAkHFsOb5+cLpmNibVCkIWTKDFAM5ml/ QkKlTwSQc0Op+GYpdqzP7XY/LCdGxMzQdUwqlRTaxRbkm9JDJV69CCoVKlvOKXFP+8yJ 8yYLWOa6z38Vzjyu3wkkvd779HPYAAxP9ASd4ZTUQyNv2Ut5rpuVfCOxrXYDqA0/5eU9 4oQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HFVPB0TM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h14-20020a37de0e000000b0076da64decfbsi5584039qkj.63.2023.11.06.07.33.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 Nov 2023 07:33:49 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HFVPB0TM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r01b9-00007O-GR; Mon, 06 Nov 2023 10:33:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r01aw-00082U-RE for qemu-devel@nongnu.org; Mon, 06 Nov 2023 10:32:57 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r01ao-0004OU-Km for qemu-devel@nongnu.org; Mon, 06 Nov 2023 10:32:53 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-40837ebba42so29055415e9.0 for ; Mon, 06 Nov 2023 07:32:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699284764; x=1699889564; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=QiKPJfj6026HtJyHgqnn8HlAlq2ojaeDiEbXyPDrg7Y=; b=HFVPB0TMFU74PbywsMIr4XgMECKYpELpb1YXdtqsFqjzl6+kiiVwIYPV1DPfvUvn7T aQpmRTLECJwoT8RVcLfZhBBrBeDdabUxYpIyJ1lWLI+NaNi5v8EakMTvzEcDHbTlbQmA dqeVJXBBx4cjPVtgwigC8txWMiWGuU+xV4qWD496apX8Nw2l7PV1VWZHEeX8idK2bD7N kxZ3tge2o22k1zYxNW0eGLqEOlee2CZcpDN7uiWO6mlOTrs6yM83Q/RmbI6qkZIhl9F3 dFiB+KVQqinAS/ufwblB5JJIf0N1n1/bcYxBhlK69WmFUIEWXV8fOj9NRu+uXf7sKc+U Ma3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699284764; x=1699889564; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QiKPJfj6026HtJyHgqnn8HlAlq2ojaeDiEbXyPDrg7Y=; b=ejWOov+5mGef1L9b1uRytiwSkzueFRIpaUIPtI7V4slvgKHYgSv5yxv0Kqm5SyLyIl 0KenYAjtZUNEPq++vAU1mzdQun9/8nOgeFNpMZcZblR4Y1pTQ6712pi/RM/ZTtVR0DLr w8VVTQJfVNr/sv3I9e4wjYdK26DH868MnMpxsjYx/XW0xNQlZ4AARRPhQ60zOmGO/g1+ s8XiuKH36DMhPcAyZY1+ikfPTsvsVgGcxAH2qAywj4oIU7iWMs9o9IpXeOOUoxVK680R U4QmJk0q+FU6FbIseZtXcJdTsugUlLDLwU3FTbYxI4xbcff36S6DulWjHuMobcwssMnc tTNw== X-Gm-Message-State: AOJu0YwcBGHUKpOtRyIlM5GITueE2y7komq7/i8Szvr3DNG33IvMPWcv wBclW2dBRX/QDqOvJAo3o4CcFqohDMiTYsZYI24= X-Received: by 2002:a05:6000:4020:b0:32d:b06c:80b2 with SMTP id cp32-20020a056000402000b0032db06c80b2mr23849710wrb.0.1699284763905; Mon, 06 Nov 2023 07:32:43 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d5-20020adff2c5000000b0032da6f17ffdsm9752176wrp.38.2023.11.06.07.32.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 07:32:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/12] io/channel-socket: qio_channel_socket_flush(): improve msg validation Date: Mon, 6 Nov 2023 15:32:36 +0000 Message-Id: <20231106153238.1426649-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106153238.1426649-1-peter.maydell@linaro.org> References: <20231106153238.1426649-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Vladimir Sementsov-Ogievskiy For SO_EE_ORIGIN_ZEROCOPY the 32-bit notification range is encoded as [ee_info, ee_data] inclusively, so ee_info should be less or equal to ee_data. Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Maksim Davydov Message-id: 20231017125941.810461-7-vsementsov@yandex-team.ru Signed-off-by: Peter Maydell --- io/channel-socket.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/io/channel-socket.c b/io/channel-socket.c index 02ffb51e995..3a899b06085 100644 --- a/io/channel-socket.c +++ b/io/channel-socket.c @@ -782,6 +782,11 @@ static int qio_channel_socket_flush(QIOChannel *ioc, "Error not from zero copy"); return -1; } + if (serr->ee_data < serr->ee_info) { + error_setg_errno(errp, serr->ee_origin, + "Wrong notification bounds"); + return -1; + } /* No errors, count successfully finished sendmsg()*/ sioc->zero_copy_sent += serr->ee_data - serr->ee_info + 1; From patchwork Mon Nov 6 15:32:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 741415 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1152301wrr; Mon, 6 Nov 2023 07:35:11 -0800 (PST) X-Google-Smtp-Source: AGHT+IE9ulgUvTRxiRcUITL/RHlWXVhD6TxZThj9l9qloU9al2gbiKUsBQJTLd5v9KuPS0rMCoov X-Received: by 2002:a05:622a:306:b0:41e:20f4:c07a with SMTP id q6-20020a05622a030600b0041e20f4c07amr33925849qtw.51.1699284911511; Mon, 06 Nov 2023 07:35:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699284911; cv=none; d=google.com; s=arc-20160816; b=HsSJoh6bYKLUZ27uJFfVB27ph2qZcmeF+DHDTeqDz7nXjM3DKhYw42S3Hy6yov4rTO q5g42RsZgviYB46XaONti/O76dTO8Ffcml/tTrTtsVmNvcp6NtcNoHbfRntJpQf+2i0e 2CzxoYfTOMv1jOzGoCELjiOLzBt2S19ww+iIzSKImESmgC0/xXlf0ByJ2PrMKu+Rd18V 4zEL+zTPAIFjJqIkr7+QAEtxM1sw4uBNX9br4q3GKr00T9OM1sBdNocBNJjoOW96S32U gXZHt0SLVoTETHEyJhH8Gdjjo2C3mifpVBNwtVR4E9kPNmMxiRre2M5foZJmaegUlp70 PuCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=813QsleyMqyhS0dbJ++cZmaNQq8ezRMtCTKDgM9WCS0=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=u/+7RAlYNxSdor/9g8ZoOSDMsycJogmWMAcUjCcguSJVfLhyqot5CqA0nMORM/Obh8 Zc1XM65W0yTho8IeaL9D7BESXl8sIpBfn/8Anq7vaoCRxa+tzy1UYuZsapz1hjc4D1aR M277zrjwzzbo6jzZNa8FhaKr257LRS0IVCRzBuefKXY7ql9gfG3QgiSUunIGZ9WqBmWs +d3ZgyWX1j4hV91M9XLu1vYTNzcrMgmPsP9AO6oKm1GF0f/SEhVopCfc2gxC0UNXmGDT b6+ZEfsUq53Zx6D57yaf4DWJEWQwn49O8c1GnIC8nmp4hXIQFgHAdtYTCR0+FKgi3da3 iWnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v1mEVIvU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d5-20020adff2c5000000b0032da6f17ffdsm9752176wrp.38.2023.11.06.07.32.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 07:32:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/12] hw/arm/vexpress-a9: Remove useless mapping of RAM at address 0 Date: Mon, 6 Nov 2023 15:32:37 +0000 Message-Id: <20231106153238.1426649-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106153238.1426649-1-peter.maydell@linaro.org> References: <20231106153238.1426649-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org On the vexpress-a9 board we try to map both RAM and flash to address 0, as seen in "info mtree": address-space: memory 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-0000000003ffffff (prio 0, romd): alias vexpress.flashalias @vexpress.flash0 0000000000000000-0000000003ffffff 0000000000000000-0000000003ffffff (prio 0, ram): alias vexpress.lowmem @vexpress.highmem 0000000000000000-0000000003ffffff 0000000010000000-0000000010000fff (prio 0, i/o): arm-sysctl 0000000010004000-0000000010004fff (prio 0, i/o): pl041 (etc) The flash "wins" and the RAM mapping is useless (but also harmless). This happened as a result of commit 6ec1588e in 2014, which changed "we always map the RAM to the low addresses for vexpress-a9" to "we always map flash in the low addresses", but forgot to stop mapping the RAM. In real hardware, this low part of memory is remappable, both at runtime by the guest writing to a control register, and configurably as to what you get out of reset -- you can have the first flash device, or the second, or the DDR2 RAM, or the external AXI bus (which for QEMU means "nothing there"). In an ideal world we would support that remapping both at runtime and via a machine property to select the out-of-reset behaviour. Pending anybody caring enough to implement the full remapping behaviour: * remove the useless mapped-but-inaccessible lowram MR * document that QEMU doesn't support remapping of low memory Fixes: 6ec1588e ("hw/arm/vexpress: Alias NOR flash at 0 for vexpress-a9") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1761 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20231103185602.875849-1-peter.maydell@linaro.org --- docs/system/arm/vexpress.rst | 3 +++ hw/arm/vexpress.c | 14 +++----------- 2 files changed, 6 insertions(+), 11 deletions(-) diff --git a/docs/system/arm/vexpress.rst b/docs/system/arm/vexpress.rst index 3e3839e9231..38f29c73e71 100644 --- a/docs/system/arm/vexpress.rst +++ b/docs/system/arm/vexpress.rst @@ -58,6 +58,9 @@ Other differences between the hardware and the QEMU model: ``vexpress-a15``, and have IRQs from 40 upwards. If a dtb is provided on the command line then QEMU will edit it to include suitable entries describing these transports for the guest. +- QEMU does not currently support either dynamic or static remapping + of the area of memory at address 0: it is always mapped to alias + the first flash bank Booting a Linux kernel ---------------------- diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 8ff37f52ca1..c08ea34e924 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -177,7 +177,6 @@ struct VexpressMachineState { MemoryRegion vram; MemoryRegion sram; MemoryRegion flashalias; - MemoryRegion lowram; MemoryRegion a15sram; bool secure; bool virt; @@ -276,7 +275,6 @@ static void a9_daughterboard_init(VexpressMachineState *vms, { MachineState *machine = MACHINE(vms); MemoryRegion *sysmem = get_system_memory(); - ram_addr_t low_ram_size; if (ram_size > 0x40000000) { /* 1GB is the maximum the address space permits */ @@ -284,17 +282,11 @@ static void a9_daughterboard_init(VexpressMachineState *vms, exit(1); } - low_ram_size = ram_size; - if (low_ram_size > 0x4000000) { - low_ram_size = 0x4000000; - } - /* RAM is from 0x60000000 upwards. The bottom 64MB of the + /* + * RAM is from 0x60000000 upwards. The bottom 64MB of the * address space should in theory be remappable to various - * things including ROM or RAM; we always map the RAM there. + * things including ROM or RAM; we always map the flash there. */ - memory_region_init_alias(&vms->lowram, NULL, "vexpress.lowmem", - machine->ram, 0, low_ram_size); - memory_region_add_subregion(sysmem, 0x0, &vms->lowram); memory_region_add_subregion(sysmem, 0x60000000, machine->ram); /* 0x1e000000 A9MPCore (SCU) private memory region */ From patchwork Mon Nov 6 15:32:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 741410 Delivered-To: patch@linaro.org Received: by 2002:adf:fd90:0:b0:32d:baff:b0ca with SMTP id d16csp1151740wrr; Mon, 6 Nov 2023 07:34:08 -0800 (PST) X-Google-Smtp-Source: AGHT+IHOxfvpffErTvEzN85jCIPhTh4BmmukJFFn9uJn+hh8x9pPqrtr3FtW7+Aqqiv3gxiY88W+ X-Received: by 2002:a05:6808:1919:b0:3b5:e67a:7cd2 with SMTP id bf25-20020a056808191900b003b5e67a7cd2mr1372169oib.8.1699284847483; Mon, 06 Nov 2023 07:34:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699284847; cv=none; d=google.com; s=arc-20160816; b=CCzZX3CvB2f5a86W9C7DRwSpRdfWa4e+5pjtSHrxWHOdTv6Uvv/tlNasgUurpRshuh Y8ZwF+DpSyRYbnIebEQo4WlVUKW1QwkpQMc1HDelBtca26uD03s1nopn5+TeOHb+owki qUedq4kLbUfPCvk2LtIPW16IwQO7qqyzm2naisi0GOyGX/9WWLbXO7vCDoN4PGBI69Ki /0aqoU595DleO4q7ge2dfQHv94081coYOFuCAFFCPDYUlw1oe4ln8bIuW92WSt1C4GEP Z2Q5i72ZZ76nUAmT+mfzSqjuVfhob/YnvgUi0YxLEa0XhqtPOI0EQ3gl8nyNGLLARMf6 IUbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vMqWcAj2Ns99kW52JXRa7w6ZQQ9Cpo0DKoDdAGV1Fl4=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=blmSFjUxiAeF94P5DKpXnLr3CsLIp1d20QbSjh23Eq1jnoOJUlhqdpkdiPGaSENqNA GneacOpiABdo2CXnsaTzmDOF6BbPUa/cydyvhd+pPmQuEFTY4XAUiIDhtY4B1hOy6Alw Ae05SfBLk/JW4Vk0JMx/FaWOvN+v2XJnSMH2jRApvIvh/hIFyxN3qIf+o9dL1RcaT/EU 2rPYZNqpjdmhZjJ3y7fWzzEEj1WSPfTy/MaNgsKsRqrpHqRxG0Qj4lkLWSHb+yHTgTeg lfWSfPmLUxr33R3fdkAdV0M70ko8St2iAPQtsdf/QOtt3I2bTdVXfalKpTDvhoEfx0dh Xl+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ncWML9Qg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d5-20020adff2c5000000b0032da6f17ffdsm9752176wrp.38.2023.11.06.07.32.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 07:32:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/12] target/arm: Fix A64 LDRA immediate decode Date: Mon, 6 Nov 2023 15:32:38 +0000 Message-Id: <20231106153238.1426649-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231106153238.1426649-1-peter.maydell@linaro.org> References: <20231106153238.1426649-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In commit be23a049 in the conversion to decodetree we broke the decoding of the immediate value in the LDRA instruction. This should be a 10 bit signed value that is scaled by 8, but in the conversion we incorrectly ended up scaling it only by 2. Fix the scaling factor. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1970 Fixes: be23a049 ("target/arm: Convert load (pointer auth) insns to decodetree") Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20231106113445.1163063-1-peter.maydell@linaro.org --- target/arm/tcg/translate.h | 5 +++++ target/arm/tcg/a64.decode | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 9efe00cf6ca..3c3bb3431ad 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -205,6 +205,11 @@ static inline int times_4(DisasContext *s, int x) return x * 4; } +static inline int times_8(DisasContext *s, int x) +{ + return x * 8; +} + static inline int times_2_plus_1(DisasContext *s, int x) { return x * 2 + 1; diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 0cf11470741..8a20dce3c8f 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -462,7 +462,7 @@ LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 # Load/store register (pointer authentication) # LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous -%ldra_imm 22:s1 12:9 !function=times_2 +%ldra_imm 22:s1 12:9 !function=times_8 LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm