From patchwork Tue Nov 14 21:29:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 743840 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B9792FC4B for ; Tue, 14 Nov 2023 21:29:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="TcPyRMGL" Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F53F9D; Tue, 14 Nov 2023 13:29:23 -0800 (PST) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3AELTIEg075117; Tue, 14 Nov 2023 15:29:18 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1699997358; bh=qlJleWEtN0/MdcN3nmgasTh8mkJEXMI2ZAg8qTNFdQA=; h=From:To:CC:Subject:Date; b=TcPyRMGLJt+jYAgsd+OdQbmMQayRfUv82rzBRkRz13hd+DmbzWzHogIv/dNeNrWCC zEzYvQYxKUWytcqYeyrh7velTfvk/x2+V/Szskk9uDLQYV8Nvv7QuzjyJxdbT+FLN6 R0w+9lZnHgx1+Bnt7695nIrnD8fnsBH/O7A8vVQM= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3AELTIZx010609 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 14 Nov 2023 15:29:18 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 14 Nov 2023 15:29:18 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 14 Nov 2023 15:29:18 -0600 Received: from fllv0039.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3AELTIwn088933; Tue, 14 Nov 2023 15:29:18 -0600 From: Andrew Davis To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra CC: , , Andrew Davis Subject: [PATCH v2 1/4] dt-bindings: spi: Convert spi-davinci.txt to YAML Date: Tue, 14 Nov 2023 15:29:08 -0600 Message-ID: <20231114212911.429951-1-afd@ti.com> X-Mailer: git-send-email 2.39.2 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Convert spi-davinci.txt to ti,dm6441-spi.yaml. Signed-off-by: Andrew Davis Reviewed-by: Rob Herring --- Changes for v2: - Fix typo s/dm6446/dm6441 .../devicetree/bindings/spi/spi-davinci.txt | 100 ------------------ .../bindings/spi/ti,dm6441-spi.yaml | 76 +++++++++++++ 2 files changed, 76 insertions(+), 100 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/spi-davinci.txt create mode 100644 Documentation/devicetree/bindings/spi/ti,dm6441-spi.yaml diff --git a/Documentation/devicetree/bindings/spi/spi-davinci.txt b/Documentation/devicetree/bindings/spi/spi-davinci.txt deleted file mode 100644 index f012888656eca..0000000000000 --- a/Documentation/devicetree/bindings/spi/spi-davinci.txt +++ /dev/null @@ -1,100 +0,0 @@ -Davinci SPI controller device bindings - -Links on DM: -Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf -dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf -OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf - -Required properties: -- #address-cells: number of cells required to define a chip select - address on the SPI bus. Should be set to 1. -- #size-cells: should be zero. -- compatible: - - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family - - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family - - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC - family -- reg: Offset and length of SPI controller register space -- num-cs: Number of chip selects. This includes internal as well as - GPIO chip selects. -- ti,davinci-spi-intr-line: interrupt line used to connect the SPI - IP to the interrupt controller within the SoC. Possible values - are 0 and 1. Manual says one of the two possible interrupt - lines can be tied to the interrupt controller. Set this - based on a specific SoC configuration. -- interrupts: interrupt number mapped to CPU. -- clocks: spi clk phandle - For 66AK2G this property should be set per binding, - Documentation/devicetree/bindings/clock/ti,sci-clk.yaml - -SoC-specific Required Properties: - -The following are mandatory properties for Keystone 2 66AK2G SoCs only: - -- power-domains: Should contain a phandle to a PM domain provider node - and an args specifier containing the SPI device id - value. This property is as per the binding, - -Optional: -- cs-gpios: gpio chip selects - For example to have 3 internal CS and 2 GPIO CS, user could define - cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>; - where first three are internal CS and last two are GPIO CS. - -Optional properties for slave devices: -SPI slave nodes can contain the following properties. -Not all SPI Peripherals from Texas Instruments support this. -Please check SPI peripheral documentation for a device before using these. - -- ti,spi-wdelay : delay between transmission of words - (SPIFMTn.WDELAY, SPIDAT1.WDEL) must be specified in number of SPI module - clock periods. - - delay = WDELAY * SPI_module_clock_period + 2 * SPI_module_clock_period - -Below is timing diagram which shows functional meaning of -"ti,spi-wdelay" parameter. - - +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ -SPI_CLK | | | | | | | | | | | | | | | | - +----------+ +-+ +-+ +-+ +-+ +---------------------------+ +-+ +-+ +- - -SPI_SOMI/SIMO+-----------------+ +----------- - +----------+ word1 +---------------------------+word2 - +-----------------+ +----------- - WDELAY - <--------------------------> - -Example of a NOR flash slave device (n25q032) connected to DaVinci -SPI controller device over the SPI bus. - -spi0:spi@20bf0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,dm6446-spi"; - reg = <0x20BF0000 0x1000>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = <338>; - clocks = <&clkspi>; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p32"; - spi-max-frequency = <25000000>; - reg = <0>; - ti,spi-wdelay = <8>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "test"; - reg = <0x80000 0x380000>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/spi/ti,dm6441-spi.yaml b/Documentation/devicetree/bindings/spi/ti,dm6441-spi.yaml new file mode 100644 index 0000000000000..a71e51fb87e4f --- /dev/null +++ b/Documentation/devicetree/bindings/spi/ti,dm6441-spi.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/ti,dm6441-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Davinci SPI Controller + +description: + SPI controllers on TI Davinci, OMAP-L138, and Keystone2 SoCs. + +maintainers: + - Andrew Davis + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + items: + - enum: + - ti,dm6441-spi # for SPI used on DM644x SoC family + - ti,da830-spi # for SPI used on DA8xx SoC family + - ti,keystone-spi # for SPI used on Keystone2 SoC family + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + ti,davinci-spi-intr-line: + description: + Interrupt line used to connect the SPI IP to the interrupt controller + within the SoC. Possible values are 0 and 1. Manual says one of the + two possible interrupt lines can be tied to the interrupt controller. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + spi@20bf0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,dm6441-spi"; + reg = <0x20bf0000 0x1000>; + interrupts = <338>; + clocks = <&clkspi>; + + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + + flash@0 { + compatible = "st,m25p32"; + spi-max-frequency = <50000000>; + reg = <0>; + ti,spi-wdelay = <8>; + }; + }; From patchwork Tue Nov 14 21:29:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 743839 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5ECC92FC5E for ; Tue, 14 Nov 2023 21:29:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="jwj/1rQT" Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E6F29D; Tue, 14 Nov 2023 13:29:28 -0800 (PST) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3AELTJTj027685; Tue, 14 Nov 2023 15:29:19 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1699997359; bh=ypr6vGkBC/3AODq+QcC3UhtxTdbE5y0FftzmS/g9kt8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jwj/1rQTRpjuMC4qUJvkOc9JVi7doWwYqrgHhWhfeZI5eWzY8Vs/FFq15r3Q25Dli CexwBwGimZiPeoO/Sl2rjuC8JAgSPPggkrOqryqlnVnc1MGBHK1E4ZrHRfSUmVPVrA 6l1wlQhOm93uAqITaKrn1lksWjAapmmbbF9Jj408= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3AELTJXF010613 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 14 Nov 2023 15:29:19 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 14 Nov 2023 15:29:19 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 14 Nov 2023 15:29:19 -0600 Received: from fllv0039.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3AELTIwo088933; Tue, 14 Nov 2023 15:29:18 -0600 From: Andrew Davis To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra CC: , , Andrew Davis Subject: [PATCH v2 2/4] dt-bindings: clock: Convert keystone-gate.txt to YAML Date: Tue, 14 Nov 2023 15:29:09 -0600 Message-ID: <20231114212911.429951-2-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231114212911.429951-1-afd@ti.com> References: <20231114212911.429951-1-afd@ti.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Convert keystone-gate.txt to ti,keystone,psc-clock.yaml. Signed-off-by: Andrew Davis --- Changes for v2: - Fix dt_binding_check warning .../bindings/clock/keystone-gate.txt | 29 --------- .../bindings/clock/ti,keystone,psc-clock.yaml | 59 +++++++++++++++++++ 2 files changed, 59 insertions(+), 29 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/keystone-gate.txt create mode 100644 Documentation/devicetree/bindings/clock/ti,keystone,psc-clock.yaml diff --git a/Documentation/devicetree/bindings/clock/keystone-gate.txt b/Documentation/devicetree/bindings/clock/keystone-gate.txt deleted file mode 100644 index c5aa187026e3a..0000000000000 --- a/Documentation/devicetree/bindings/clock/keystone-gate.txt +++ /dev/null @@ -1,29 +0,0 @@ -Status: Unstable - ABI compatibility may be broken in the future - -Binding for Keystone gate control driver which uses PSC controller IP. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "ti,keystone,psc-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : parent clock phandle -- reg : psc control and domain address address space -- reg-names : psc control and domain registers -- domain-id : psc domain id needed to check the transition state register - -Optional properties: -- clock-output-names : From common clock binding to override the - default output clock name -Example: - clkusb: clkusb { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "usb"; - reg = <0x02350008 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; diff --git a/Documentation/devicetree/bindings/clock/ti,keystone,psc-clock.yaml b/Documentation/devicetree/bindings/clock/ti,keystone,psc-clock.yaml new file mode 100644 index 0000000000000..e65b7383ca4a0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,keystone,psc-clock.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,keystone,psc-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Keystone gate control driver which uses PSC controller IP + +maintainers: + - Andrew Davis + +properties: + compatible: + const: ti,keystone,psc-clock + + reg: + items: + - description: PSC control registers + - description: Domain registers + + reg-names: + items: + - const: control + - const: domain + + domain-id: + description: PSC domain id needed to check the transition state register + $ref: /schemas/types.yaml#/definitions/uint32 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + + "#clock-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - domain-id + - clocks + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clkusb@2350008 { + compatible = "ti,keystone,psc-clock"; + reg = <0x02350008 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + clocks = <&chipclk16>; + clock-output-names = "usb"; + #clock-cells = <0>; + }; From patchwork Tue Nov 14 21:29:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 744154 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B45B2FC4D for ; Tue, 14 Nov 2023 21:29:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="iaoBoPkq" Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19552C8; Tue, 14 Nov 2023 13:29:24 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3AELTJCS126721; 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Tue, 14 Nov 2023 15:29:19 -0600 Received: from fllv0039.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3AELTIwp088933; Tue, 14 Nov 2023 15:29:19 -0600 From: Andrew Davis To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra CC: , , Andrew Davis Subject: [PATCH v2 3/4] dt-bindings: arm: keystone: Convert keystone.txt to YAML Date: Tue, 14 Nov 2023 15:29:10 -0600 Message-ID: <20231114212911.429951-3-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231114212911.429951-1-afd@ti.com> References: <20231114212911.429951-1-afd@ti.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Convert keystone.txt to ti,keystone.yaml. Signed-off-by: Andrew Davis Reviewed-by: Rob Herring --- Documentation/arch/arm/keystone/overview.rst | 2 +- .../bindings/arm/keystone/keystone.txt | 42 --------------- .../bindings/arm/keystone/ti,keystone.yaml | 53 +++++++++++++++++++ 3 files changed, 54 insertions(+), 43 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/keystone/keystone.txt create mode 100644 Documentation/devicetree/bindings/arm/keystone/ti,keystone.yaml diff --git a/Documentation/arch/arm/keystone/overview.rst b/Documentation/arch/arm/keystone/overview.rst index cd90298c493c7..6d8896ba9a6e2 100644 --- a/Documentation/arch/arm/keystone/overview.rst +++ b/Documentation/arch/arm/keystone/overview.rst @@ -65,7 +65,7 @@ specified through DTS. Following are the DTS used: The device tree documentation for the keystone machines are located at - Documentation/devicetree/bindings/arm/keystone/keystone.txt + Documentation/devicetree/bindings/arm/keystone/ti,keystone.yaml Document Author --------------- diff --git a/Documentation/devicetree/bindings/arm/keystone/keystone.txt b/Documentation/devicetree/bindings/arm/keystone/keystone.txt deleted file mode 100644 index f310bad044830..0000000000000 --- a/Documentation/devicetree/bindings/arm/keystone/keystone.txt +++ /dev/null @@ -1,42 +0,0 @@ -TI Keystone Platforms Device Tree Bindings ------------------------------------------------ - -Boards with Keystone2 based devices (TCI66xxK2H) SOC shall have the -following properties. - -Required properties: - - compatible: All TI specific devices present in Keystone SOC should be in - the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550 - type UART should use the specified compatible for those devices. - -SoC families: - -- Keystone 2 generic SoC: - compatible = "ti,keystone" - -SoCs: - -- Keystone 2 Hawking/Kepler - compatible = "ti,k2hk", "ti,keystone" -- Keystone 2 Lamarr - compatible = "ti,k2l", "ti,keystone" -- Keystone 2 Edison - compatible = "ti,k2e", "ti,keystone" -- K2G - compatible = "ti,k2g", "ti,keystone" - -Boards: -- Keystone 2 Hawking/Kepler EVM - compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone" - -- Keystone 2 Lamarr EVM - compatible = "ti,k2l-evm", "ti, k2l", "ti,keystone" - -- Keystone 2 Edison EVM - compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone" - -- K2G EVM - compatible = "ti,k2g-evm", "ti,k2g", "ti-keystone" - -- K2G Industrial Communication Engine EVM - compatible = "ti,k2g-ice", "ti,k2g", "ti-keystone" diff --git a/Documentation/devicetree/bindings/arm/keystone/ti,keystone.yaml b/Documentation/devicetree/bindings/arm/keystone/ti,keystone.yaml new file mode 100644 index 0000000000000..60af461af5ff9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/keystone/ti,keystone.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/keystone/ti,keystone.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments Keystone SoC architecture + +maintainers: + - Andrew Davis + +description: | + Platforms based on Texas Instruments Keystone2 Multicore SoC architecture + shall have the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: Keystone 2 Hawking/Kepler + items: + - enum: + - ti,k2hk-evm # Keystone 2 Hawking/Kepler EVM + - const: ti,k2hk + - const: ti,keystone + + - description: Keystone 2 Lamarr + items: + - enum: + - ti,k2l-evm # Keystone 2 Lamarr EVM + - const: ti,k2l + - const: ti,keystone + + - description: Keystone 2 Edison + items: + - enum: + - ti,k2e-evm # Keystone 2 Edison EVM + - const: ti,k2e + - const: ti,keystone + + - description: K2G + items: + - enum: + - ti,k2g-evm # K2G EVM + - ti,k2g-ice # K2G Industrial Communication Engine EVM + - const: ti,k2g + - const: ti,keystone + +additionalProperties: true + +... From patchwork Tue Nov 14 21:29:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 744153 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 929282FC5D for ; Tue, 14 Nov 2023 21:29:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="QZZAdOcC" Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 42D32C4; Tue, 14 Nov 2023 13:29:26 -0800 (PST) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3AELTKg9021540; Tue, 14 Nov 2023 15:29:20 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1699997360; bh=h/ZosiAC/9rRWiVF21d/F0mkMc5jJK9KEzk3JPu0e1s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=QZZAdOcCCwRRyoCIisJFzQNCWGz7Eksals1I2wGOYtGP1WKpi2gZOstRkl6jA7OTH rwznJG84gOyufgXOxV6UjAY09MbE+GT+DuOQmaWIpInd2Q9NFhuWopxa6ko9Px57Jh v1fXpW61wlV4/fUL0jRgPfo1Mj1HTZGVsdyZzgJg= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3AELTKsL010621 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 14 Nov 2023 15:29:20 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 14 Nov 2023 15:29:20 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 14 Nov 2023 15:29:20 -0600 Received: from fllv0039.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3AELTIwq088933; Tue, 14 Nov 2023 15:29:19 -0600 From: Andrew Davis To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra CC: , , Andrew Davis Subject: [PATCH v2 4/4] dt-bindings: dma: Convert ti-edma.txt to YAML Date: Tue, 14 Nov 2023 15:29:11 -0600 Message-ID: <20231114212911.429951-4-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231114212911.429951-1-afd@ti.com> References: <20231114212911.429951-1-afd@ti.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Convert ti-edma.txt to ti/ti,edma3-tpcc.yaml and ti/ti,edma3-tptc.yaml. Signed-off-by: Andrew Davis --- Changes for v2: - Fix dt_binding_check warning .../devicetree/bindings/dma/ti-edma.txt | 238 ------------------ .../bindings/dma/ti/ti,edma3-tpcc.yaml | 128 ++++++++++ .../bindings/dma/ti/ti,edma3-tptc.yaml | 63 +++++ MAINTAINERS | 1 - 4 files changed, 191 insertions(+), 239 deletions(-) delete mode 100644 Documentation/devicetree/bindings/dma/ti-edma.txt create mode 100644 Documentation/devicetree/bindings/dma/ti/ti,edma3-tpcc.yaml create mode 100644 Documentation/devicetree/bindings/dma/ti/ti,edma3-tptc.yaml diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt deleted file mode 100644 index f719e1612b0a5..0000000000000 --- a/Documentation/devicetree/bindings/dma/ti-edma.txt +++ /dev/null @@ -1,238 +0,0 @@ -Texas Instruments eDMA - -The eDMA3 consists of two components: Channel controller (CC) and Transfer -Controller(s) (TC). The CC is the main entry for DMA users since it is -responsible for the DMA channel handling, while the TCs are responsible to -execute the actual DMA tansfer. - ------------------------------------------------------------------------------- -eDMA3 Channel Controller - -Required properties: --------------------- -- compatible: Should be: - - "ti,edma3-tpcc" for the channel controller(s) on OMAP, - AM33xx and AM43xx SoCs. - - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the - channel controller(s) on 66AK2G. -- #dma-cells: Should be set to <2>. The first number is the DMA request - number and the second is the TC the channel is serviced on. -- reg: Memory map of eDMA CC -- reg-names: "edma3_cc" -- interrupts: Interrupt lines for CCINT, MPERR and CCERRINT. -- interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint" -- ti,tptcs: List of TPTCs associated with the eDMA in the following form: - <&tptc_phandle TC_priority_number>. The highest priority is 0. - -SoC-specific Required properties: --------------------------------- -The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only: -- ti,hwmods: Name of the hwmods associated to the eDMA CC. - -The following are mandatory properties for 66AK2G SoCs only: -- power-domains:Should contain a phandle to a PM domain provider node - and an args specifier containing the device id - value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml - -Optional properties: -------------------- -- ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow - these channels will be SW triggered channels. See example. -- ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by - the driver, they are allocated to be used by for example the - DSP. See example. -- dma-channel-mask: Mask of usable channels. - Single uint32 for EDMA with 32 channels, array of two uint32 for - EDMA with 64 channels. See example and - Documentation/devicetree/bindings/dma/dma-common.yaml - - ------------------------------------------------------------------------------- -eDMA3 Transfer Controller - -Required properties: --------------------- -- compatible: Should be: - - "ti,edma3-tptc" for the transfer controller(s) on OMAP, - AM33xx and AM43xx SoCs. - - "ti,k2g-edma3-tptc", "ti,edma3-tptc" for the - transfer controller(s) on 66AK2G. -- reg: Memory map of eDMA TC -- interrupts: Interrupt number for TCerrint. - -SoC-specific Required properties: --------------------------------- -The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only: -- ti,hwmods: Name of the hwmods associated to the eDMA TC. - -The following are mandatory properties for 66AK2G SoCs only: -- power-domains:Should contain a phandle to a PM domain provider node - and an args specifier containing the device id - value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml - -Optional properties: -------------------- -- interrupt-names: "edma3_tcerrint" - ------------------------------------------------------------------------------- -Examples: - -1. -edma: edma@49000000 { - compatible = "ti,edma3-tpcc"; - ti,hwmods = "tpcc"; - reg = <0x49000000 0x10000>; - reg-names = "edma3_cc"; - interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>; - - /* Channel 20 and 21 is allocated for memcpy */ - ti,edma-memcpy-channels = <20 21>; - /* The following PaRAM slots are reserved: 35-44 and 100-109 */ - ti,edma-reserved-slot-ranges = <35 10>, <100 10>; - /* The following channels are reserved: 35-44 */ - dma-channel-mask = <0xffffffff /* Channel 0-31 */ - 0xffffe007>; /* Channel 32-63 */ -}; - -edma_tptc0: tptc@49800000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc0"; - reg = <0x49800000 0x100000>; - interrupts = <112>; - interrupt-names = "edm3_tcerrint"; -}; - -edma_tptc1: tptc@49900000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc1"; - reg = <0x49900000 0x100000>; - interrupts = <113>; - interrupt-names = "edm3_tcerrint"; -}; - -edma_tptc2: tptc@49a00000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc2"; - reg = <0x49a00000 0x100000>; - interrupts = <114>; - interrupt-names = "edm3_tcerrint"; -}; - -sham: sham@53100000 { - compatible = "ti,omap4-sham"; - ti,hwmods = "sham"; - reg = <0x53100000 0x200>; - interrupts = <109>; - /* DMA channel 36 executed on eDMA TC0 - low priority queue */ - dmas = <&edma 36 0>; - dma-names = "rx"; -}; - -mcasp0: mcasp@48038000 { - compatible = "ti,am33xx-mcasp-audio"; - ti,hwmods = "mcasp0"; - reg = <0x48038000 0x2000>, - <0x46000000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <80>, <81>; - interrupt-names = "tx", "rx"; - /* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */ - dmas = <&edma 8 2>, - <&edma 9 2>; - dma-names = "tx", "rx"; -}; - -2. -edma1: edma@2728000 { - compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; - reg = <0x02728000 0x8000>; - reg-names = "edma3_cc"; - interrupts = , - , - ; - interrupt-names = "edma3_ccint", "emda3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>; - - /* - * memcpy is disabled, can be enabled with: - * ti,edma-memcpy-channels = <12 13 14 15>; - * for example. - */ - - power-domains = <&k2g_pds 0x4f>; -}; - -edma1_tptc0: tptc@27b0000 { - compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x027b0000 0x400>; - power-domains = <&k2g_pds 0x4f>; -}; - -edma1_tptc1: tptc@27b8000 { - compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; - reg = <0x027b8000 0x400>; - power-domains = <&k2g_pds 0x4f>; -}; - -mmc0: mmc@23000000 { - compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc"; - reg = <0x23000000 0x400>; - interrupts = ; - dmas = <&edma1 24 0>, <&edma1 25 0>; - dma-names = "tx", "rx"; - bus-width = <4>; - ti,needs-special-reset; - no-1-8-v; - max-frequency = <96000000>; - power-domains = <&k2g_pds 0xb>; - clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>; - clock-names = "fck", "mmchsdb_fck"; -}; - ------------------------------------------------------------------------------- -DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc -binding. - -Required properties: -- compatible : "ti,edma3" -- #dma-cells: Should be set to <1> - Clients should use a single channel number per DMA request. -- reg: Memory map for accessing module -- interrupts: Exactly 3 interrupts need to be specified in the order: - 1. Transfer completion interrupt. - 2. Memory protection interrupt. - 3. Error interrupt. -Optional properties: -- ti,hwmods: Name of the hwmods associated to the EDMA -- ti,edma-xbar-event-map: Crossbar event to channel map - -Deprecated properties: -Listed here in case one wants to boot an old kernel with new DTB. These -properties might need to be added to the new DTS files. -- ti,edma-regions: Number of regions -- ti,edma-slots: Number of slots -- dma-channels: Specify total DMA channels per CC - -Example: - -edma: edma@49000000 { - reg = <0x49000000 0x10000>; - interrupt-parent = <&intc>; - interrupts = <12 13 14>; - compatible = "ti,edma3"; - ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; - #dma-cells = <1>; - ti,edma-xbar-event-map = /bits/ 16 <1 12 - 2 13>; -}; diff --git a/Documentation/devicetree/bindings/dma/ti/ti,edma3-tpcc.yaml b/Documentation/devicetree/bindings/dma/ti/ti,edma3-tpcc.yaml new file mode 100644 index 0000000000000..c44dcfad31a10 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/ti/ti,edma3-tpcc.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/ti/ti,edma3-tpcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments eDMA3 Channel Controller + +description: | + The eDMA3 consists of two components, Channel controller (CC) and Transfer + Controller(s) (TC). The CC is the main entry for DMA users since it is + responsible for the DMA channel handling, while the TCs are responsible to + execute the actual DMA tansfer. This documents the Channel Controller. + +maintainers: + - Andrew Davis + +allOf: + - $ref: /schemas/dma/dma-controller.yaml# + +properties: + compatible: + oneOf: + - const: ti,edma3-tpcc # OMAP, AM33xx, and AM43xx + - items: + - const: ti,k2g-edma3-tpcc # 66AK2G + - const: ti,edma3-tpcc + + reg: + maxItems: 1 + + reg-names: + const: edma3_cc + + interrupts: + items: + - description: CCINT Interrupt + - description: MPERR Interrupt + - description: CCERRINT Interrupt + + interrupt-names: + items: + - const: edma3_ccint + - const: edma3_mperr + - const: edma3_ccerrint + + "#dma-cells": + const: 2 + description: | + The first cell is the DMA request number. + The second cell is the TC the channel is serviced on. + + ti,tptcs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of TPTCs associated with the eDMA in the following form, + <&tptc_phandle TC_priority_number>. The highest priority is 0. + + power-domains: + maxItems: 1 + + ti,edma-memcpy-channels: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + List of channels allocated to be used for memcpy, iow + these channels will be SW triggered channels. + + ti,edma-reserved-slot-ranges: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + PaRAM slot ranges which should not be used by the driver, + they are allocated to be used by for example the DSP. + + dma-channel-mask: + description: | + Mask of usable channels. Single uint32 for EDMA with 32 channels, + array of two uint32 for EDMA with 64 channels. + + dma-requests: + const: 64 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - "#dma-cells" + - ti,tptcs + +if: + properties: + compatible: + contains: + enum: + - ti,k2g-edma3-tptc +then: + required: + - power-domains + +additionalProperties: false + +examples: + - | + #include + dma-controller@49000000 { + compatible = "ti,edma3-tpcc"; + reg = <0x49000000 0x10000>; + reg-names = "edma3_cc"; + interrupts = , + , + ; + interrupt-names = "edma3_ccint", + "edma3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>; + + /* Channel 20 and 21 is allocated for memcpy */ + ti,edma-memcpy-channels = <20 21>; + /* The following PaRAM slots are reserved: 35-44 and 100-109 */ + ti,edma-reserved-slot-ranges = <35 10>, <100 10>; + /* The following channels are reserved: 35-44 */ + dma-channel-mask = <0xffffffff /* Channel 0-31 */ + 0xffffe007>; /* Channel 32-63 */ + }; diff --git a/Documentation/devicetree/bindings/dma/ti/ti,edma3-tptc.yaml b/Documentation/devicetree/bindings/dma/ti/ti,edma3-tptc.yaml new file mode 100644 index 0000000000000..1d3a1af63c9b4 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/ti/ti,edma3-tptc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/ti/ti,edma3-tptc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments eDMA3 Transfer Controller + +description: | + The eDMA3 consists of two components, Channel controller (CC) and Transfer + Controller(s) (TC). The CC is the main entry for DMA users since it is + responsible for the DMA channel handling, while the TCs are responsible to + execute the actual DMA tansfer. This documents the Transfer Controller. + +maintainers: + - Andrew Davis + +properties: + compatible: + oneOf: + - const: ti,edma3-tptc # OMAP, AM33xx, and AM43xx + - items: + - const: ti,k2g-edma3-tptc # 66AK2G + - const: ti,edma3-tptc + + reg: + maxItems: 1 + + interrupts: + description: Interrupt number for TCerrint + maxItems: 1 + + interrupt-names: + const: edma3_tcerrint + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + +if: + properties: + compatible: + contains: + enum: + - ti,k2g-edma3-tptc +then: + required: + - power-domains + +additionalProperties: false + +examples: + - | + tptc@49800000 { + compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; + reg = <0x49800000 0x100000>; + interrupts = <112>; + interrupt-names = "edma3_tcerrint"; + power-domains = <&k2g_pds 0xb>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 97f51d5ec1cfd..b19cfac762b42 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21515,7 +21515,6 @@ M: Peter Ujfalusi L: dmaengine@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt -F: Documentation/devicetree/bindings/dma/ti-edma.txt F: Documentation/devicetree/bindings/dma/ti/ F: drivers/dma/ti/ F: include/linux/dma/k3-psil.h