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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.37.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:37:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:48 -0700 Message-Id: <20190819213755.26175-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v2 01/68] target/arm: Use store_reg_from_load in thumb2 code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function already includes the test for an interworking write to PC from a load. Change the T32 LDM implementation to match the A32 LDM implementation. For LDM, the reordering of the tests does not change valid behaviour because the only case that differs is has rn == 15, which is UNPREDICTABLE. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index d948757131..db69d998eb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9714,13 +9714,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) /* Load. */ tmp = tcg_temp_new_i32(); gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i == 15) { - gen_bx_excret(s, tmp); - } else if (i == rn) { + if (i == rn) { loaded_var = tmp; loaded_base = 1; } else { - store_reg(s, i, tmp); + store_reg_from_load(s, i, tmp); } } else { /* Store. */ @@ -10854,11 +10852,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(addr); goto illegal_op; } - if (rs == 15) { - gen_bx_excret(s, tmp); - } else { - store_reg(s, rs, tmp); - } + store_reg_from_load(s, rs, tmp); } else { /* Store. */ tmp = load_reg(s, rs); From patchwork Mon Aug 19 21:36:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171664 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3531845ily; Mon, 19 Aug 2019 14:41:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqxU949yFbDtiSXdJx6Wb1oye9yXQ3BWlY9AIsKrwt4621GCWsVQKs8AGu7GfywgCReVEfbr X-Received: by 2002:a0c:86ca:: with SMTP id 10mr12194766qvg.227.1566250912323; Mon, 19 Aug 2019 14:41:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566250912; cv=none; d=google.com; s=arc-20160816; b=uVgYu+isFcqkserwvn1Da12cqurXCJh2dTxFcME3cN0XSPNvR83mDbW7PPYpP6m72N 4wqk3r2YrQc5oi9dK+ZAHgGfBivU73xc74kNJeq3+Cufyn4rMK7QkngCdtBUf/ib8U70 BzQLJCR7E6aXxB4lFMJTGzNLGbPVFWTlErKrvgi2s7mvUgE9PX8I/ASosrtYhhz+EpqS Dbg0Xq3MCf/Dj7ocyBxtHvWc+vAwm6Tm0fxzQ62pNhxOB0ytvS2zzhrPdWJrsWZUt4gm fMc66GLtKj22AzCGQkAK7DQX/SGshYamTrOQ6qMsL0Vc+9FRRQtELywnYQSSbTgEk+aU Y9yA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Lk8BfvHlK27e0gTYQ9ZvQ9xJX5SjXjlYlXz2Xz9pa/E=; b=s5Ua5chyRw4idDr9ZUmybOg+Mx8j3T7nWID+f9+QzUfIlIQyxBdd4vnSiAM5Vphakb 3XixnWfadBhTW59P4+P/+PjTqzLZSBghda6ZREW1VmAapjJWMd+R+oiwLluW2fuUapO/ KkS7ox5w8ZAGfEuaATugJXBw71y2QUw9b3VFp+c3xyUUvsEsWtLQiHV/Ac01LmdLvKUj VUDtHJTtMZB/d7Fpa43DOxVShLQasNXqp91doC4xQoAyWGhwxwBB72xjFons8UvPgavx 3Tn1QI7DRRn1Sc44Pro5hYzCu6o1RcIr7ynbQF+/zFlDZo2lkRLoJZe63YyS5UnWinh/ rteg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jUNWfg2J; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.37.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:37:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:49 -0700 Message-Id: <20190819213755.26175-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v2 02/68] target/arm: Add stubs for aa32 decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add the infrastructure that will become the new decoder. No instructions adjusted so far. Signed-off-by: Richard Henderson --- target/arm/translate.c | 31 ++++++++++++++++++++++++++++++- target/arm/Makefile.objs | 18 ++++++++++++++++++ target/arm/a32-uncond.decode | 23 +++++++++++++++++++++++ target/arm/a32.decode | 23 +++++++++++++++++++++++ target/arm/t32.decode | 20 ++++++++++++++++++++ 5 files changed, 114 insertions(+), 1 deletion(-) create mode 100644 target/arm/a32-uncond.decode create mode 100644 target/arm/a32.decode create mode 100644 target/arm/t32.decode -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index db69d998eb..c759fe0797 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7661,6 +7661,18 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond) arm_gen_test_cc(cond ^ 1, s->condlabel); } +/* + * Include the generated decoders. + */ + +#include "decode-a32.inc.c" +#include "decode-a32-uncond.inc.c" +#include "decode-t32.inc.c" + +/* + * Legacy decoder. + */ + static void disas_arm_insn(DisasContext *s, unsigned int insn) { unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh; @@ -7679,7 +7691,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) return; } cond = insn >> 28; - if (cond == 0xf){ + + if (cond == 0xf) { /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we * choose to UNDEF. In ARMv5 and above the space is used * for miscellaneous unconditional instructions. @@ -7687,6 +7700,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) ARCH(5); /* Unconditional instructions. */ + if (disas_a32_uncond(s, insn)) { + return; + } + /* fall back to legacy decoder */ + if (((insn >> 25) & 7) == 1) { /* NEON Data processing. */ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { @@ -7901,6 +7919,12 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) next instruction */ arm_skip_unless(s, cond); } + + if (disas_a32(s, insn)) { + return; + } + /* fall back to legacy decoder */ + if ((insn & 0x0f900000) == 0x03000000) { if ((insn & (1 << 21)) == 0) { ARCH(6T2); @@ -9386,6 +9410,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) ARCH(6T2); } + if (disas_t32(s, insn)) { + return; + } + /* fall back to legacy decoder */ + rn = (insn >> 16) & 0xf; rs = (insn >> 12) & 0xf; rd = (insn >> 8) & 0xf; diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 5cafc1eb6c..7806b4dac0 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -28,9 +28,27 @@ target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/arm/vfp-uncond.decode $(D $(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\ "GEN", $(TARGET_DIR)$@) +target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/decode-a32-uncond.inc.c: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + target/arm/translate-sve.o: target/arm/decode-sve.inc.c target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c +target/arm/translate.o: target/arm/decode-a32.inc.c +target/arm/translate.o: target/arm/decode-a32-uncond.inc.c +target/arm/translate.o: target/arm/decode-t32.inc.c obj-y += tlb_helper.o debug_helper.o obj-y += translate.o op_helper.o diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode new file mode 100644 index 0000000000..8dee26d3b6 --- /dev/null +++ b/target/arm/a32-uncond.decode @@ -0,0 +1,23 @@ +# A32 unconditional instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# +# All insns that have 0xf in insn[31:28] are decoded here. +# All of those that have a COND field in insn[31:28] are in a32.decode +# diff --git a/target/arm/a32.decode b/target/arm/a32.decode new file mode 100644 index 0000000000..a3e6e8c1c2 --- /dev/null +++ b/target/arm/a32.decode @@ -0,0 +1,23 @@ +# A32 conditional instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# +# All of the insn that have a COND field in insn[31:28] are here. +# All insns that have 0xf in insn[31:28] are in a32-uncond.decode. +# diff --git a/target/arm/t32.decode b/target/arm/t32.decode new file mode 100644 index 0000000000..ac01fb6958 --- /dev/null +++ b/target/arm/t32.decode @@ -0,0 +1,20 @@ +# Thumb2 instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# From patchwork Mon Aug 19 21:36:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171662 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3530157ily; Mon, 19 Aug 2019 14:39:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqzGYEWmGa1D0xTrTzGnaDtUY8TTzqOP314LZlpEUxoWECyUOGTzIMAibTLcFwvlx7Qwrm1q X-Received: by 2002:a37:6905:: with SMTP id e5mr22619604qkc.121.1566250769666; Mon, 19 Aug 2019 14:39:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566250769; cv=none; d=google.com; s=arc-20160816; b=M6owGA4NzfuQPc+2MFmmoGYyr2GVxBSG+NOUZtTCmuCagYrBK9vShauNGkWwuFbf50 8cWUABsQI3dktYS3Mv7zFLdCCtt35/y34/zn58Kdj1sogXrXJGi0LBKgdd+saAgmW1ya YxFpkcm47rWoIgAoJ9BqxcuOcniUZA46CY5xH1ej8xBC13geTBnNErPQoamZsp7nX1T+ Gsvnx00WZDSVz98XI43nCMQ5xD1x8nbHcF1czTFmQfm+y3MwhSqBqyNomWHrHYY6PV96 lSzUXCEvWyk9H+lBnuW41sFA0oVB7uqF7Szzf98A8W+RfykbKxWT1wIoANibXXXwYy4i qpYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=QIkenGimVRi/Plae7Rw1++VDbOCShjtnkN1KcI6L2k4=; b=qQEr6j7yhguJBG5N/3aCd0wbrtAB42fVfJMguRC4KsDMxrU60YMQlq9+eYqzUhTHFt qp6/xlJ6GuIC7Jo6er2Nzv593Ni7zEz44kaGuKHofv1aFhFT1FzqjCBM/QbpXR4IxmDs 7JKnARINI5g7TXPYd0P0MI3PitCUOakS3Z4OWzxjAiKLYhJVxx9i/HFSuLC7XeCiECmM Us81Vae+Au6DEtiN9ZtLgDf6kdNSIfDt23+9o8W1qgNO/5Y0jM27qcbD4VfAycu1UybM 7Lfao0QGoanliMdtyRfMLFXpDLnSVczR4n4DAetSXTBr3Li8x56m9E9ljf07ui5j/0bT 5b8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ma302CXn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:50 -0700 Message-Id: <20190819213755.26175-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v2 03/68] target/arm: Convert Data Processing (register) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the register shifted by immediate form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the reg-shifted-reg and immediate forms. Signed-off-by: Richard Henderson --- target/arm/translate.c | 229 ++++++++++++++++++++++++++++++++++------- target/arm/a32.decode | 28 +++++ target/arm/t32.decode | 43 ++++++++ 3 files changed, 264 insertions(+), 36 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index c759fe0797..be8e7685e3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7669,6 +7669,197 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond) #include "decode-a32-uncond.inc.c" #include "decode-t32.inc.c" +/* Helpers to swap operands for reverse-subtract. */ +static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_sub_i32(dst, b, a); +} + +static void gen_rsb_CC(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) +{ + gen_sub_CC(dst, b, a); +} + +static void gen_rsc(TCGv_i32 dest, TCGv_i32 a, TCGv_i32 b) +{ + gen_sub_carry(dest, b, a); +} + +static void gen_rsc_CC(TCGv_i32 dest, TCGv_i32 a, TCGv_i32 b) +{ + gen_sbc_CC(dest, b, a); +} + +/* + * Helpers for the data processing routines. + * + * After the computation store the results back. + * This may be suppressed altogether (STREG_NONE), require a runtime + * check against the stack limits (STREG_SP_CHECK), or generate an + * exception return. Oh, or store into a register. + * + * Always return true, indicating success for a trans_* function. + */ +typedef enum { + STREG_NONE, + STREG_NORMAL, + STREG_SP_CHECK, + STREG_EXC_RET, +} StoreRegKind; + +static bool store_reg_kind(DisasContext *s, int rd, + TCGv_i32 val, StoreRegKind kind) +{ + switch (kind) { + case STREG_NONE: + tcg_temp_free_i32(val); + return true; + case STREG_NORMAL: + /* See ALUWritePC: Interworking only from a32 mode. */ + if (s->thumb) { + store_reg(s, rd, val); + } else { + store_reg_bx(s, rd, val); + } + return true; + case STREG_SP_CHECK: + store_sp_checked(s, val); + return true; + case STREG_EXC_RET: + gen_exception_return(s, val); + return true; + } + g_assert_not_reached(); +} + +/* + * Data Processing (register) + * + * Operate, with set flags, one register source, + * one immediate shifted register source, and a destination. + */ +static bool op_s_rrr_shi(DisasContext *s, arg_s_rrr_shi *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + + tmp2 = load_reg(s, a->rm); + gen_arm_shift_im(tmp2, a->shty, a->shim, logic_cc); + tmp1 = load_reg(s, a->rn); + + gen(tmp1, tmp1, tmp2); + tcg_temp_free_i32(tmp2); + + if (logic_cc) { + gen_logic_CC(tmp1); + } + return store_reg_kind(s, a->rd, tmp1, kind); +} + +static bool op_s_rxr_shi(DisasContext *s, arg_s_rrr_shi *a, + void (*gen)(TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp; + + tmp = load_reg(s, a->rm); + gen_arm_shift_im(tmp, a->shty, a->shim, logic_cc); + + gen(tmp, tmp); + if (logic_cc) { + gen_logic_CC(tmp); + } + return store_reg_kind(s, a->rd, tmp, kind); +} + +#define DO_ANY3(NAME, OP, L, K) \ + static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \ + { StoreRegKind k = (K); return op_s_rrr_shi(s, a, OP, L, k); } + +#define DO_ANY2(NAME, OP, L, K) \ + static bool trans_##NAME##_rxri(DisasContext *s, arg_s_rrr_shi *a) \ + { StoreRegKind k = (K); return op_s_rxr_shi(s, a, OP, L, k); } + +#define DO_CMP2(NAME, OP, L) \ + static bool trans_##NAME##_xrri(DisasContext *s, arg_s_rrr_shi *a) \ + { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } + +DO_ANY3(AND, tcg_gen_and_i32, a->s, STREG_NORMAL) +DO_ANY3(EOR, tcg_gen_xor_i32, a->s, STREG_NORMAL) +DO_ANY3(ORR, tcg_gen_or_i32, a->s, STREG_NORMAL) +DO_ANY3(BIC, tcg_gen_andc_i32, a->s, STREG_NORMAL) + +DO_ANY3(RSB, a->s ? gen_rsb_CC : gen_rsb, false, STREG_NORMAL) +DO_ANY3(ADC, a->s ? gen_adc_CC : gen_add_carry, false, STREG_NORMAL) +DO_ANY3(SBC, a->s ? gen_sbc_CC : gen_sub_carry, false, STREG_NORMAL) +DO_ANY3(RSC, a->s ? gen_rsc_CC : gen_rsc, false, STREG_NORMAL) + +DO_CMP2(TST, tcg_gen_and_i32, true) +DO_CMP2(TEQ, tcg_gen_xor_i32, true) +DO_CMP2(CMN, gen_add_CC, false) +DO_CMP2(CMP, gen_sub_CC, false) + +DO_ANY3(ADD, a->s ? gen_add_CC : tcg_gen_add_i32, false, + a->rd == 13 && a->rn == 13 ? STREG_SP_CHECK : STREG_NORMAL) + +DO_ANY3(SUB, a->s ? gen_sub_CC : tcg_gen_sub_i32, false, + ({ + StoreRegKind ret = STREG_NORMAL; + if (a->rd == 15 && a->s) { + /* + * See ALUExceptionReturn: + * In User mode, UNPREDICTABLE; we choose UNDEF. + * In Hyp mode, UNDEFINED. + */ + if (IS_USER(s) || s->current_el == 2) { + return false; + } + /* There is no writeback of nzcv to PSTATE. */ + a->s = 0; + ret = STREG_EXC_RET; + } else if (a->rd == 13 && a->rn == 13) { + ret = STREG_SP_CHECK; + } + ret; + })) + +DO_ANY2(MOV, tcg_gen_mov_i32, a->s, + ({ + StoreRegKind ret = STREG_NORMAL; + if (a->rd == 15 && a->s) { + /* + * See ALUExceptionReturn: + * In User mode, UNPREDICTABLE; we choose UNDEF. + * In Hyp mode, UNDEFINED. + */ + if (IS_USER(s) || s->current_el == 2) { + return false; + } + /* There is no writeback of nzcv to PSTATE. */ + a->s = 0; + ret = STREG_EXC_RET; + } else if (a->rd == 13) { + ret = STREG_SP_CHECK; + } + ret; + })) + +DO_ANY2(MVN, tcg_gen_not_i32, a->s, STREG_NORMAL) + +/* + * ORN is only available with T32, so there is no register-shifted-register + * form of the insn. Using the DO_ANY3 macro would create an unused function. + */ +static bool trans_ORN_rrri(DisasContext *s, arg_s_rrr_shi *a) +{ + return op_s_rrr_shi(s, a, tcg_gen_orc_i32, a->s, STREG_NORMAL); +} + +#undef DO_ANY3 +#undef DO_ANY2 +#undef DO_CMP2 + /* * Legacy decoder. */ @@ -9277,13 +9468,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn) return true; } -/* Return true if this is a Thumb-2 logical op. */ -static int -thumb2_logic_op(int op) -{ - return (op < 8); -} - /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero then set condition code flags based on the result of the operation. If SHIFTER_OUT is nonzero then set the carry flag for logical operations @@ -9371,8 +9555,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) TCGv_i32 addr; TCGv_i64 tmp64; int op; - int shiftop; - int conds; int logic_cc; /* @@ -9802,33 +9984,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) store_reg(s, rd, tmp); } else { /* Data processing register constant shift. */ - if (rn == 15) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp = load_reg(s, rn); - } - tmp2 = load_reg(s, rm); - - shiftop = (insn >> 4) & 3; - shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); - conds = (insn & (1 << 20)) != 0; - logic_cc = (conds && thumb2_logic_op(op)); - gen_arm_shift_im(tmp2, shiftop, shift, logic_cc); - if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2)) - goto illegal_op; - tcg_temp_free_i32(tmp2); - if (rd == 13 && - ((op == 2 && rn == 15) || - (op == 8 && rn == 13) || - (op == 13 && rn == 13))) { - /* MOV SP, ... or ADD SP, SP, ... or SUB SP, SP, ... */ - store_sp_checked(s, tmp); - } else if (rd != 15) { - store_reg(s, rd, tmp); - } else { - tcg_temp_free_i32(tmp); - } + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } break; case 13: /* Misc data processing. */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index a3e6e8c1c2..b23e83f17c 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -21,3 +21,31 @@ # All of the insn that have a COND field in insn[31:28] are here. # All insns that have 0xf in insn[31:28] are in a32-uncond.decode. # + +&s_rrr_shi s rd rn rm shim shty + +# Data-processing (register) + +@s_rrr_shi ---- ... .... s:1 rn:4 rd:4 shim:5 shty:2 . rm:4 \ + &s_rrr_shi +@s_rxr_shi ---- ... .... s:1 .... rd:4 shim:5 shty:2 . rm:4 \ + &s_rrr_shi rn=0 +@S_xrr_shi ---- ... .... . rn:4 .... shim:5 shty:2 . rm:4 \ + &s_rrr_shi s=1 rd=0 + +AND_rrri .... 000 0000 . .... .... ..... .. 0 .... @s_rrr_shi +EOR_rrri .... 000 0001 . .... .... ..... .. 0 .... @s_rrr_shi +SUB_rrri .... 000 0010 . .... .... ..... .. 0 .... @s_rrr_shi +RSB_rrri .... 000 0011 . .... .... ..... .. 0 .... @s_rrr_shi +ADD_rrri .... 000 0100 . .... .... ..... .. 0 .... @s_rrr_shi +ADC_rrri .... 000 0101 . .... .... ..... .. 0 .... @s_rrr_shi +SBC_rrri .... 000 0110 . .... .... ..... .. 0 .... @s_rrr_shi +RSC_rrri .... 000 0111 . .... .... ..... .. 0 .... @s_rrr_shi +TST_xrri .... 000 1000 1 .... 0000 ..... .. 0 .... @S_xrr_shi +TEQ_xrri .... 000 1001 1 .... 0000 ..... .. 0 .... @S_xrr_shi +CMP_xrri .... 000 1010 1 .... 0000 ..... .. 0 .... @S_xrr_shi +CMN_xrri .... 000 1011 1 .... 0000 ..... .. 0 .... @S_xrr_shi +ORR_rrri .... 000 1100 . .... .... ..... .. 0 .... @s_rrr_shi +MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi +BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi +MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ac01fb6958..7068596b99 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -18,3 +18,46 @@ # # This file is processed by scripts/decodetree.py # + +&s_rrr_shi !extern s rd rn rm shim shty + +# Data-processing (register) + +%imm5_12_6 12:3 6:2 + +@s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \ + &s_rrr_shi shim=%imm5_12_6 +@s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \ + &s_rrr_shi shim=%imm5_12_6 rn=0 +@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \ + &s_rrr_shi shim=%imm5_12_6 s=1 rd=0 + +{ + TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi + AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi +} +BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi +{ + MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi + ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi +} +{ + MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi + ORN_rrri 1110101 0011 . .... 0 ... .... .... .... @s_rrr_shi +} +{ + TEQ_xrri 1110101 0100 1 .... 0 ... 1111 .... .... @S_xrr_shi + EOR_rrri 1110101 0100 . .... 0 ... .... .... .... @s_rrr_shi +} +# PKHBT, PKHTB at opc1 = 0110 +{ + CMN_xrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi + ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi +} +ADC_rrri 1110101 1010 . .... 0 ... .... .... .... @s_rrr_shi +SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi +{ + CMP_xrri 1110101 1101 1 .... 0 ... 1111 .... .... @S_xrr_shi + SUB_rrri 1110101 1101 . .... 0 ... .... .... .... @s_rrr_shi +} +RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi From patchwork Mon Aug 19 21:36:51 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:51 -0700 Message-Id: <20190819213755.26175-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v2 04/68] target/arm: Convert Data Processing (reg-shifted-reg) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the register shifted by register form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the immediate form. Signed-off-by: Richard Henderson --- target/arm/translate.c | 74 ++++++++++++++++++++++++++++++------------ target/arm/a32.decode | 27 +++++++++++++++ target/arm/t32.decode | 6 ++++ 3 files changed, 87 insertions(+), 20 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index be8e7685e3..a32fe4b222 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7773,17 +7773,66 @@ static bool op_s_rxr_shi(DisasContext *s, arg_s_rrr_shi *a, return store_reg_kind(s, a->rd, tmp, kind); } +/* + * Data-processing (register-shifted register) + * + * Operate, with set flags, one register source, + * one register shifted register source, and a destination. + */ +static bool op_s_rrr_shr(DisasContext *s, arg_s_rrr_shr *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + + tmp1 = load_reg(s, a->rs); + tmp2 = load_reg(s, a->rm); + gen_arm_shift_reg(tmp2, a->shty, tmp1, logic_cc); + tmp1 = load_reg(s, a->rn); + + gen(tmp1, tmp1, tmp2); + tcg_temp_free_i32(tmp2); + + if (logic_cc) { + gen_logic_CC(tmp1); + } + return store_reg_kind(s, a->rd, tmp1, kind); +} + +static bool op_s_rxr_shr(DisasContext *s, arg_s_rrr_shr *a, + void (*gen)(TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + + tmp1 = load_reg(s, a->rs); + tmp2 = load_reg(s, a->rm); + gen_arm_shift_reg(tmp2, a->shty, tmp1, logic_cc); + + gen(tmp2, tmp2); + if (logic_cc) { + gen_logic_CC(tmp2); + } + return store_reg_kind(s, a->rd, tmp2, kind); +} + #define DO_ANY3(NAME, OP, L, K) \ static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \ - { StoreRegKind k = (K); return op_s_rrr_shi(s, a, OP, L, k); } + { StoreRegKind k = (K); return op_s_rrr_shi(s, a, OP, L, k); } \ + static bool trans_##NAME##_rrrr(DisasContext *s, arg_s_rrr_shr *a) \ + { StoreRegKind k = (K); return op_s_rrr_shr(s, a, OP, L, k); } #define DO_ANY2(NAME, OP, L, K) \ static bool trans_##NAME##_rxri(DisasContext *s, arg_s_rrr_shi *a) \ - { StoreRegKind k = (K); return op_s_rxr_shi(s, a, OP, L, k); } + { StoreRegKind k = (K); return op_s_rxr_shi(s, a, OP, L, k); } \ + static bool trans_##NAME##_rxrr(DisasContext *s, arg_s_rrr_shr *a) \ + { StoreRegKind k = (K); return op_s_rxr_shr(s, a, OP, L, k); } #define DO_CMP2(NAME, OP, L) \ static bool trans_##NAME##_xrri(DisasContext *s, arg_s_rrr_shi *a) \ - { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } + { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } \ + static bool trans_##NAME##_xrrr(DisasContext *s, arg_s_rrr_shr *a) \ + { return op_s_rrr_shr(s, a, OP, L, STREG_NONE); } DO_ANY3(AND, tcg_gen_and_i32, a->s, STREG_NORMAL) DO_ANY3(EOR, tcg_gen_xor_i32, a->s, STREG_NORMAL) @@ -9555,7 +9604,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) TCGv_i32 addr; TCGv_i64 tmp64; int op; - int logic_cc; /* * ARMv6-M supports a limited subset of Thumb2 instructions. @@ -9993,22 +10041,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) if (op < 4 && (insn & 0xf000) != 0xf000) goto illegal_op; switch (op) { - case 0: /* Register controlled shift. */ - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - if ((insn & 0x70) != 0) - goto illegal_op; - /* - * 0b1111_1010_0xxx_xxxx_1111_xxxx_0000_xxxx: - * - MOV, MOVS (register-shifted register), flagsetting - */ - op = (insn >> 21) & 3; - logic_cc = (insn & (1 << 20)) != 0; - gen_arm_shift_reg(tmp, op, tmp2, logic_cc); - if (logic_cc) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - break; + case 0: /* Register controlled shift, in decodetree */ + goto illegal_op; case 1: /* Sign/zero extend. */ op = (insn >> 20) & 7; switch (op) { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index b23e83f17c..8e0fb06d05 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -23,6 +23,7 @@ # &s_rrr_shi s rd rn rm shim shty +&s_rrr_shr s rn rd rm rs shty # Data-processing (register) @@ -49,3 +50,29 @@ ORR_rrri .... 000 1100 . .... .... ..... .. 0 .... @s_rrr_shi MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi + +# Data-processing (register-shifted register) + +@s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \ + &s_rrr_shr +@s_rxr_shr ---- ... .... s:1 .... rd:4 rs:4 . shty:2 . rm:4 \ + &s_rrr_shr rn=0 +@S_xrr_shr ---- ... .... . rn:4 .... rs:4 . shty:2 . rm:4 \ + &s_rrr_shr rd=0 s=1 + +AND_rrrr .... 000 0000 . .... .... .... 0 .. 1 .... @s_rrr_shr +EOR_rrrr .... 000 0001 . .... .... .... 0 .. 1 .... @s_rrr_shr +SUB_rrrr .... 000 0010 . .... .... .... 0 .. 1 .... @s_rrr_shr +RSB_rrrr .... 000 0011 . .... .... .... 0 .. 1 .... @s_rrr_shr +ADD_rrrr .... 000 0100 . .... .... .... 0 .. 1 .... @s_rrr_shr +ADC_rrrr .... 000 0101 . .... .... .... 0 .. 1 .... @s_rrr_shr +SBC_rrrr .... 000 0110 . .... .... .... 0 .. 1 .... @s_rrr_shr +RSC_rrrr .... 000 0111 . .... .... .... 0 .. 1 .... @s_rrr_shr +TST_xrrr .... 000 1000 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +TEQ_xrrr .... 000 1001 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +CMP_xrrr .... 000 1010 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +CMN_xrrr .... 000 1011 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +ORR_rrrr .... 000 1100 . .... .... .... 0 .. 1 .... @s_rrr_shr +MOV_rxrr .... 000 1101 . 0000 .... .... 0 .. 1 .... @s_rxr_shr +BIC_rrrr .... 000 1110 . .... .... .... 0 .. 1 .... @s_rrr_shr +MVN_rxrr .... 000 1111 . 0000 .... .... 0 .. 1 .... @s_rxr_shr diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 7068596b99..f0a73fa003 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -20,6 +20,7 @@ # &s_rrr_shi !extern s rd rn rm shim shty +&s_rrr_shr !extern s rn rd rm rs shty # Data-processing (register) @@ -61,3 +62,8 @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi SUB_rrri 1110101 1101 . .... 0 ... .... .... .... @s_rrr_shi } RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi + +# Data-processing (register-shifted register) + +MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \ + &s_rrr_shr rn=0 From patchwork Mon Aug 19 21:36:52 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:52 -0700 Message-Id: <20190819213755.26175-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::432 Subject: [Qemu-devel] [PATCH v2 05/68] target/arm: Convert Data Processing (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the modified immediate form of the data processing insns. For A32, we can finally remove any code that was intertwined with the register and register-shifted-register forms. Signed-off-by: Richard Henderson --- target/arm/translate.c | 449 +++++++++++------------------------------ target/arm/a32.decode | 29 +++ target/arm/t32.decode | 42 ++++ 3 files changed, 186 insertions(+), 334 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index a32fe4b222..b5af38bf84 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -439,12 +439,6 @@ static void gen_add16(TCGv_i32 t0, TCGv_i32 t1) tcg_temp_free_i32(t1); } -/* Set CF to the top bit of var. */ -static void gen_set_CF_bit31(TCGv_i32 var) -{ - tcg_gen_shri_i32(cpu_CF, var, 31); -} - /* Set N and Z flags from var. */ static inline void gen_logic_CC(TCGv_i32 var) { @@ -857,25 +851,6 @@ void arm_gen_test_cc(int cc, TCGLabel *label) arm_free_cc(&cmp); } -static const uint8_t table_logic_cc[16] = { - 1, /* and */ - 1, /* xor */ - 0, /* sub */ - 0, /* rsb */ - 0, /* add */ - 0, /* adc */ - 0, /* sbc */ - 0, /* rsc */ - 1, /* andl */ - 1, /* xorl */ - 0, /* cmp */ - 0, /* cmn */ - 1, /* orr */ - 1, /* mov */ - 1, /* bic */ - 1, /* mvn */ -}; - static inline void gen_set_condexec(DisasContext *s) { if (s->condexec_mask) { @@ -7661,6 +7636,48 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond) arm_gen_test_cc(cond ^ 1, s->condlabel); } + +/* + * Constant expanders for the decoders. + */ + +static int times_2(DisasContext *s, int x) +{ + return x * 2; +} + +/* Return only the rotation part of T32ExpandImm. */ +static int t32_expandimm_rot(DisasContext *s, int x) +{ + return x & 0xc00 ? extract32(x, 7, 5) : 0; +} + +/* Return the unrotated immediate from T32ExpandImm. */ +static int t32_expandimm_imm(DisasContext *s, int x) +{ + int imm = extract32(x, 0, 8); + + switch (extract32(x, 8, 4)) { + case 0: /* XY */ + /* Nothing to do. */ + break; + case 1: /* 00XY00XY */ + imm *= 0x00010001; + break; + case 2: /* XY00XY00 */ + imm *= 0x01000100; + break; + case 3: /* XYXYXYXY */ + imm *= 0x01010101; + break; + default: + /* Rotated constant. */ + imm |= 0x80; + break; + } + return imm; +} + /* * Include the generated decoders. */ @@ -7816,23 +7833,82 @@ static bool op_s_rxr_shr(DisasContext *s, arg_s_rrr_shr *a, return store_reg_kind(s, a->rd, tmp2, kind); } +/* + * Data-processing (immediate) + * + * Operate, with set flags, one register source, + * one rotated immediate, and a destination. + * + * Note that logic_cc && a->rot setting CF based on the msb of the + * immediate is the reason why we must pass in the unrotated form + * of the immediate. + */ +static bool op_s_rri_rot(DisasContext *s, arg_s_rri_rot *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + uint32_t imm; + + imm = ror32(a->imm, a->rot); + if (logic_cc && a->rot) { + tcg_gen_movi_i32(cpu_CF, imm >> 31); + } + tmp2 = tcg_const_i32(imm); + tmp1 = load_reg(s, a->rn); + + gen(tmp1, tmp1, tmp2); + tcg_temp_free_i32(tmp2); + + if (logic_cc) { + gen_logic_CC(tmp1); + } + return store_reg_kind(s, a->rd, tmp1, kind); +} + +static bool op_s_rxi_rot(DisasContext *s, arg_s_rri_rot *a, + void (*gen)(TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp; + uint32_t imm; + + imm = ror32(a->imm, a->rot); + if (logic_cc && a->rot) { + tcg_gen_movi_i32(cpu_CF, imm >> 31); + } + tmp = tcg_const_i32(imm); + + gen(tmp, tmp); + if (logic_cc) { + gen_logic_CC(tmp); + } + return store_reg_kind(s, a->rd, tmp, kind); +} + #define DO_ANY3(NAME, OP, L, K) \ static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \ { StoreRegKind k = (K); return op_s_rrr_shi(s, a, OP, L, k); } \ static bool trans_##NAME##_rrrr(DisasContext *s, arg_s_rrr_shr *a) \ - { StoreRegKind k = (K); return op_s_rrr_shr(s, a, OP, L, k); } + { StoreRegKind k = (K); return op_s_rrr_shr(s, a, OP, L, k); } \ + static bool trans_##NAME##_rri(DisasContext *s, arg_s_rri_rot *a) \ + { StoreRegKind k = (K); return op_s_rri_rot(s, a, OP, L, k); } #define DO_ANY2(NAME, OP, L, K) \ static bool trans_##NAME##_rxri(DisasContext *s, arg_s_rrr_shi *a) \ { StoreRegKind k = (K); return op_s_rxr_shi(s, a, OP, L, k); } \ static bool trans_##NAME##_rxrr(DisasContext *s, arg_s_rrr_shr *a) \ - { StoreRegKind k = (K); return op_s_rxr_shr(s, a, OP, L, k); } + { StoreRegKind k = (K); return op_s_rxr_shr(s, a, OP, L, k); } \ + static bool trans_##NAME##_rxi(DisasContext *s, arg_s_rri_rot *a) \ + { StoreRegKind k = (K); return op_s_rxi_rot(s, a, OP, L, k); } #define DO_CMP2(NAME, OP, L) \ static bool trans_##NAME##_xrri(DisasContext *s, arg_s_rrr_shi *a) \ { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } \ static bool trans_##NAME##_xrrr(DisasContext *s, arg_s_rrr_shr *a) \ - { return op_s_rrr_shr(s, a, OP, L, STREG_NONE); } + { return op_s_rrr_shr(s, a, OP, L, STREG_NONE); } \ + static bool trans_##NAME##_xri(DisasContext *s, arg_s_rri_rot *a) \ + { return op_s_rri_rot(s, a, OP, L, STREG_NONE); } DO_ANY3(AND, tcg_gen_and_i32, a->s, STREG_NORMAL) DO_ANY3(EOR, tcg_gen_xor_i32, a->s, STREG_NORMAL) @@ -7905,6 +7981,11 @@ static bool trans_ORN_rrri(DisasContext *s, arg_s_rrr_shi *a) return op_s_rrr_shi(s, a, tcg_gen_orc_i32, a->s, STREG_NORMAL); } +static bool trans_ORN_rri(DisasContext *s, arg_s_rri_rot *a) +{ + return op_s_rri_rot(s, a, tcg_gen_orc_i32, a->s, STREG_NORMAL); +} + #undef DO_ANY3 #undef DO_ANY2 #undef DO_CMP2 @@ -8442,182 +8523,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } else if (((insn & 0x0e000000) == 0 && (insn & 0x00000090) != 0x90) || ((insn & 0x0e000000) == (1 << 25))) { - int set_cc, logic_cc, shiftop; - - op1 = (insn >> 21) & 0xf; - set_cc = (insn >> 20) & 1; - logic_cc = table_logic_cc[op1] & set_cc; - - /* data processing instruction */ - if (insn & (1 << 25)) { - /* immediate operand */ - val = insn & 0xff; - shift = ((insn >> 8) & 0xf) * 2; - val = ror32(val, shift); - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, val); - if (logic_cc && shift) { - gen_set_CF_bit31(tmp2); - } - } else { - /* register */ - rm = (insn) & 0xf; - tmp2 = load_reg(s, rm); - shiftop = (insn >> 5) & 3; - if (!(insn & (1 << 4))) { - shift = (insn >> 7) & 0x1f; - gen_arm_shift_im(tmp2, shiftop, shift, logic_cc); - } else { - rs = (insn >> 8) & 0xf; - tmp = load_reg(s, rs); - gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc); - } - } - if (op1 != 0x0f && op1 != 0x0d) { - rn = (insn >> 16) & 0xf; - tmp = load_reg(s, rn); - } else { - tmp = NULL; - } - rd = (insn >> 12) & 0xf; - switch(op1) { - case 0x00: - tcg_gen_and_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x01: - tcg_gen_xor_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x02: - if (set_cc && rd == 15) { - /* SUBS r15, ... is used for exception return. */ - if (IS_USER(s)) { - goto illegal_op; - } - gen_sub_CC(tmp, tmp, tmp2); - gen_exception_return(s, tmp); - } else { - if (set_cc) { - gen_sub_CC(tmp, tmp, tmp2); - } else { - tcg_gen_sub_i32(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - } - break; - case 0x03: - if (set_cc) { - gen_sub_CC(tmp, tmp2, tmp); - } else { - tcg_gen_sub_i32(tmp, tmp2, tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x04: - if (set_cc) { - gen_add_CC(tmp, tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - break; - case 0x05: - if (set_cc) { - gen_adc_CC(tmp, tmp, tmp2); - } else { - gen_add_carry(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - break; - case 0x06: - if (set_cc) { - gen_sbc_CC(tmp, tmp, tmp2); - } else { - gen_sub_carry(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - break; - case 0x07: - if (set_cc) { - gen_sbc_CC(tmp, tmp2, tmp); - } else { - gen_sub_carry(tmp, tmp2, tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x08: - if (set_cc) { - tcg_gen_and_i32(tmp, tmp, tmp2); - gen_logic_CC(tmp); - } - tcg_temp_free_i32(tmp); - break; - case 0x09: - if (set_cc) { - tcg_gen_xor_i32(tmp, tmp, tmp2); - gen_logic_CC(tmp); - } - tcg_temp_free_i32(tmp); - break; - case 0x0a: - if (set_cc) { - gen_sub_CC(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp); - break; - case 0x0b: - if (set_cc) { - gen_add_CC(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp); - break; - case 0x0c: - tcg_gen_or_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x0d: - if (logic_cc && rd == 15) { - /* MOVS r15, ... is used for exception return. */ - if (IS_USER(s)) { - goto illegal_op; - } - gen_exception_return(s, tmp2); - } else { - if (logic_cc) { - gen_logic_CC(tmp2); - } - store_reg_bx(s, rd, tmp2); - } - break; - case 0x0e: - tcg_gen_andc_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - default: - case 0x0f: - tcg_gen_not_i32(tmp2, tmp2); - if (logic_cc) { - gen_logic_CC(tmp2); - } - store_reg_bx(s, rd, tmp2); - break; - } - if (op1 != 0x0f && op1 != 0x0d) { - tcg_temp_free_i32(tmp2); - } + /* Data-processing (reg, reg-shift-reg, imm). */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } else { /* other instructions */ op1 = (insn >> 24) & 0xf; @@ -9517,82 +9425,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn) return true; } -/* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero - then set condition code flags based on the result of the operation. - If SHIFTER_OUT is nonzero then set the carry flag for logical operations - to the high bit of T1. - Returns zero if the opcode is valid. */ - -static int -gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, - TCGv_i32 t0, TCGv_i32 t1) -{ - int logic_cc; - - logic_cc = 0; - switch (op) { - case 0: /* and */ - tcg_gen_and_i32(t0, t0, t1); - logic_cc = conds; - break; - case 1: /* bic */ - tcg_gen_andc_i32(t0, t0, t1); - logic_cc = conds; - break; - case 2: /* orr */ - tcg_gen_or_i32(t0, t0, t1); - logic_cc = conds; - break; - case 3: /* orn */ - tcg_gen_orc_i32(t0, t0, t1); - logic_cc = conds; - break; - case 4: /* eor */ - tcg_gen_xor_i32(t0, t0, t1); - logic_cc = conds; - break; - case 8: /* add */ - if (conds) - gen_add_CC(t0, t0, t1); - else - tcg_gen_add_i32(t0, t0, t1); - break; - case 10: /* adc */ - if (conds) - gen_adc_CC(t0, t0, t1); - else - gen_adc(t0, t1); - break; - case 11: /* sbc */ - if (conds) { - gen_sbc_CC(t0, t0, t1); - } else { - gen_sub_carry(t0, t0, t1); - } - break; - case 13: /* sub */ - if (conds) - gen_sub_CC(t0, t0, t1); - else - tcg_gen_sub_i32(t0, t0, t1); - break; - case 14: /* rsb */ - if (conds) - gen_sub_CC(t0, t1, t0); - else - tcg_gen_sub_i32(t0, t1, t0); - break; - default: /* 5, 6, 7, 9, 12, 15. */ - return 1; - } - if (logic_cc) { - gen_logic_CC(t0); - if (shifter_out) - gen_set_CF_bit31(t1); - } - return 0; -} - /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { @@ -10867,60 +10699,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } } } else { - /* - * 0b1111_0x0x_xxxx_0xxx_xxxx_xxxx - * - Data-processing (modified immediate) - */ - int shifter_out = 0; - /* modified 12-bit immediate. */ - shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12); - imm = (insn & 0xff); - switch (shift) { - case 0: /* XY */ - /* Nothing to do. */ - break; - case 1: /* 00XY00XY */ - imm |= imm << 16; - break; - case 2: /* XY00XY00 */ - imm |= imm << 16; - imm <<= 8; - break; - case 3: /* XYXYXYXY */ - imm |= imm << 16; - imm |= imm << 8; - break; - default: /* Rotated constant. */ - shift = (shift << 1) | (imm >> 7); - imm |= 0x80; - imm = imm << (32 - shift); - shifter_out = 1; - break; - } - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, imm); - rn = (insn >> 16) & 0xf; - if (rn == 15) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp = load_reg(s, rn); - } - op = (insn >> 21) & 0xf; - if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0, - shifter_out, tmp, tmp2)) - goto illegal_op; - tcg_temp_free_i32(tmp2); - rd = (insn >> 8) & 0xf; - if (rd == 13 && rn == 13 - && (op == 8 || op == 13)) { - /* ADD(S) SP, SP, imm or SUB(S) SP, SP, imm */ - store_sp_checked(s, tmp); - } else if (rd != 15) { - store_reg(s, rd, tmp); - } else { - tcg_temp_free_i32(tmp); - } + /* Data-processing (modified immediate) */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } } break; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 8e0fb06d05..286adcbf89 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -24,6 +24,7 @@ &s_rrr_shi s rd rn rm shim shty &s_rrr_shr s rn rd rm rs shty +&s_rri_rot s rn rd imm rot # Data-processing (register) @@ -76,3 +77,31 @@ ORR_rrrr .... 000 1100 . .... .... .... 0 .. 1 .... @s_rrr_shr MOV_rxrr .... 000 1101 . 0000 .... .... 0 .. 1 .... @s_rxr_shr BIC_rrrr .... 000 1110 . .... .... .... 0 .. 1 .... @s_rrr_shr MVN_rxrr .... 000 1111 . 0000 .... .... 0 .. 1 .... @s_rxr_shr + +# Data-processing (immediate) + +%a32extrot 8:4 !function=times_2 + +@s_rri_rot ---- ... .... s:1 rn:4 rd:4 .... imm:8 \ + &s_rri_rot rot=%a32extrot +@s_rxi_rot ---- ... .... s:1 .... rd:4 .... imm:8 \ + &s_rri_rot rot=%a32extrot rn=0 +@S_xri_rot ---- ... .... . rn:4 .... .... imm:8 \ + &s_rri_rot rot=%a32extrot rd=0 s=1 + +AND_rri .... 001 0000 . .... .... ............ @s_rri_rot +EOR_rri .... 001 0001 . .... .... ............ @s_rri_rot +SUB_rri .... 001 0010 . .... .... ............ @s_rri_rot +RSB_rri .... 001 0011 . .... .... ............ @s_rri_rot +ADD_rri .... 001 0100 . .... .... ............ @s_rri_rot +ADC_rri .... 001 0101 . .... .... ............ @s_rri_rot +SBC_rri .... 001 0110 . .... .... ............ @s_rri_rot +RSC_rri .... 001 0111 . .... .... ............ @s_rri_rot +TST_xri .... 001 1000 1 .... 0000 ............ @S_xri_rot +TEQ_xri .... 001 1001 1 .... 0000 ............ @S_xri_rot +CMP_xri .... 001 1010 1 .... 0000 ............ @S_xri_rot +CMN_xri .... 001 1011 1 .... 0000 ............ @S_xri_rot +ORR_rri .... 001 1100 . .... .... ............ @s_rri_rot +MOV_rxi .... 001 1101 . 0000 .... ............ @s_rxi_rot +BIC_rri .... 001 1110 . .... .... ............ @s_rri_rot +MVN_rxi .... 001 1111 . 0000 .... ............ @s_rxi_rot diff --git a/target/arm/t32.decode b/target/arm/t32.decode index f0a73fa003..50cbe48cc8 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -21,6 +21,7 @@ &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty +&s_rri_rot !extern s rn rd imm rot # Data-processing (register) @@ -67,3 +68,44 @@ RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \ &s_rrr_shr rn=0 + +# Data-processing (immediate) + +%t32extrot 26:1 12:3 0:8 !function=t32_expandimm_rot +%t32extimm 26:1 12:3 0:8 !function=t32_expandimm_imm + +@s_rri_rot ....... .... s:1 rn:4 . ... rd:4 ........ \ + &s_rri_rot imm=%t32extimm rot=%t32extrot +@s_rxi_rot ....... .... s:1 .... . ... rd:4 ........ \ + &s_rri_rot imm=%t32extimm rot=%t32extrot rn=0 +@S_xri_rot ....... .... . rn:4 . ... .... ........ \ + &s_rri_rot imm=%t32extimm rot=%t32extrot s=1 rd=0 + +{ + TST_xri 1111 0.0 0000 1 .... 0 ... 1111 ........ @S_xri_rot + AND_rri 1111 0.0 0000 . .... 0 ... .... ........ @s_rri_rot +} +BIC_rri 1111 0.0 0001 . .... 0 ... .... ........ @s_rri_rot +{ + MOV_rxi 1111 0.0 0010 . 1111 0 ... .... ........ @s_rxi_rot + ORR_rri 1111 0.0 0010 . .... 0 ... .... ........ @s_rri_rot +} +{ + MVN_rxi 1111 0.0 0011 . 1111 0 ... .... ........ @s_rxi_rot + ORN_rri 1111 0.0 0011 . .... 0 ... .... ........ @s_rri_rot +} +{ + TEQ_xri 1111 0.0 0100 1 .... 0 ... 1111 ........ @S_xri_rot + EOR_rri 1111 0.0 0100 . .... 0 ... .... ........ @s_rri_rot +} +{ + CMN_xri 1111 0.0 1000 1 .... 0 ... 1111 ........ @S_xri_rot + ADD_rri 1111 0.0 1000 . .... 0 ... .... ........ @s_rri_rot +} +ADC_rri 1111 0.0 1010 . .... 0 ... .... ........ @s_rri_rot +SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot +{ + CMP_xri 1111 0.0 1101 1 .... 0 ... 1111 ........ @S_xri_rot + SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot +} +RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot From patchwork Mon Aug 19 21:36:53 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:53 -0700 Message-Id: <20190819213755.26175-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v2 06/68] target/arm: Convert multiply and multiply accumulate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 248 +++++++++++++++++++++++------------------ target/arm/a32.decode | 17 +++ target/arm/t32.decode | 19 ++++ 3 files changed, 177 insertions(+), 107 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index b5af38bf84..94659086c0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7990,6 +7990,125 @@ static bool trans_ORN_rri(DisasContext *s, arg_s_rri_rot *a) #undef DO_ANY2 #undef DO_CMP2 +/* + * Multiply and multiply accumulate + */ + +static bool op_mla(DisasContext *s, arg_s_rrrr *a, bool add) +{ + TCGv_i32 t1, t2; + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + tcg_gen_mul_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + if (add) { + t2 = load_reg(s, a->ra); + tcg_gen_add_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + } + if (a->s) { + gen_logic_CC(t1); + } + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_MUL(DisasContext *s, arg_MUL *a) +{ + return op_mla(s, a, false); +} + +static bool trans_MLA(DisasContext *s, arg_MLA *a) +{ + return op_mla(s, a, true); +} + +static bool trans_MLS(DisasContext *s, arg_MLS *a) +{ + TCGv_i32 t1, t2; + + if (!ENABLE_ARCH_6T2) { + return false; + } + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + tcg_gen_mul_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + t2 = load_reg(s, a->ra); + tcg_gen_sub_i32(t1, t2, t1); + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool op_mlal(DisasContext *s, arg_s_rrrr *a, bool uns, bool add) +{ + TCGv_i32 t0, t1, t2, t3; + + t0 = load_reg(s, a->rm); + t1 = load_reg(s, a->rn); + if (uns) { + tcg_gen_mulu2_i32(t0, t1, t0, t1); + } else { + tcg_gen_muls2_i32(t0, t1, t0, t1); + } + if (add) { + t2 = load_reg(s, a->ra); + t3 = load_reg(s, a->rd); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, t3); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + } + if (a->s) { + gen_logicq_cc(t0, t1); + } + store_reg(s, a->ra, t0); + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_UMULL(DisasContext *s, arg_UMULL *a) +{ + return op_mlal(s, a, true, false); +} + +static bool trans_SMULL(DisasContext *s, arg_SMULL *a) +{ + return op_mlal(s, a, false, false); +} + +static bool trans_UMLAL(DisasContext *s, arg_UMLAL *a) +{ + return op_mlal(s, a, true, true); +} + +static bool trans_SMLAL(DisasContext *s, arg_SMLAL *a) +{ + return op_mlal(s, a, false, true); +} + +static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) +{ + TCGv_i32 t0, t1; + TCGv_i64 t64; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t0 = load_reg(s, a->rm); + t1 = load_reg(s, a->rn); + t64 = gen_mulu_i64_i32(t0, t1); + gen_addq_lo(s, t64, a->ra); + gen_addq_lo(s, t64, a->rd); + gen_storeq_reg(s, a->ra, a->rd, t64); + tcg_temp_free_i64(t64); + return true; +} + /* * Legacy decoder. */ @@ -8536,71 +8655,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) sh = (insn >> 5) & 3; if (sh == 0) { if (op1 == 0x0) { - rd = (insn >> 16) & 0xf; - rn = (insn >> 12) & 0xf; - rs = (insn >> 8) & 0xf; - rm = (insn) & 0xf; - op1 = (insn >> 20) & 0xf; - switch (op1) { - case 0: case 1: case 2: case 3: case 6: - /* 32 bit mul */ - tmp = load_reg(s, rs); - tmp2 = load_reg(s, rm); - tcg_gen_mul_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (insn & (1 << 22)) { - /* Subtract (mls) */ - ARCH(6T2); - tmp2 = load_reg(s, rn); - tcg_gen_sub_i32(tmp, tmp2, tmp); - tcg_temp_free_i32(tmp2); - } else if (insn & (1 << 21)) { - /* Add */ - tmp2 = load_reg(s, rn); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - if (insn & (1 << 20)) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - break; - case 4: - /* 64 bit mul double accumulate (UMAAL) */ - ARCH(6); - tmp = load_reg(s, rs); - tmp2 = load_reg(s, rm); - tmp64 = gen_mulu_i64_i32(tmp, tmp2); - gen_addq_lo(s, tmp64, rn); - gen_addq_lo(s, tmp64, rd); - gen_storeq_reg(s, rn, rd, tmp64); - tcg_temp_free_i64(tmp64); - break; - case 8: case 9: case 10: case 11: - case 12: case 13: case 14: case 15: - /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */ - tmp = load_reg(s, rs); - tmp2 = load_reg(s, rm); - if (insn & (1 << 22)) { - tcg_gen_muls2_i32(tmp, tmp2, tmp, tmp2); - } else { - tcg_gen_mulu2_i32(tmp, tmp2, tmp, tmp2); - } - if (insn & (1 << 21)) { /* mult accumulate */ - TCGv_i32 al = load_reg(s, rn); - TCGv_i32 ah = load_reg(s, rd); - tcg_gen_add2_i32(tmp, tmp2, tmp, tmp2, al, ah); - tcg_temp_free_i32(al); - tcg_temp_free_i32(ah); - } - if (insn & (1 << 20)) { - gen_logicq_cc(tmp, tmp2); - } - store_reg(s, rn, tmp); - store_reg(s, rd, tmp2); - break; - default: - goto illegal_op; - } + /* Multiply and multiply accumulate. */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } else { rn = (insn >> 16) & 0xf; rd = (insn >> 12) & 0xf; @@ -10040,7 +10097,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) break; case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */ switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32 */ + case 0: /* 32 x 32 -> 32, in decodetree */ + goto illegal_op; case 7: /* Unsigned sum of absolute differences. */ break; case 1: /* 16 x 16 -> 32 */ @@ -10057,18 +10115,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tmp = load_reg(s, rn); tmp2 = load_reg(s, rm); switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32 */ - tcg_gen_mul_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rs != 15) { - tmp2 = load_reg(s, rs); - if (op) - tcg_gen_sub_i32(tmp, tmp2, tmp); - else - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; case 1: /* 16 x 16 -> 32 */ gen_mulxy(tmp, tmp2, op & 2, op & 1); tcg_temp_free_i32(tmp2); @@ -10191,36 +10237,24 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) gen_storeq_reg(s, rs, rd, tmp64); tcg_temp_free_i64(tmp64); } else { - if (op & 0x20) { - /* Unsigned 64-bit multiply */ - tmp64 = gen_mulu_i64_i32(tmp, tmp2); - } else { - if (op & 8) { - /* smlalxy */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - gen_mulxy(tmp, tmp2, op & 2, op & 1); - tcg_temp_free_i32(tmp2); - tmp64 = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_temp_free_i32(tmp); - } else { - /* Signed 64-bit multiply */ - tmp64 = gen_muls_i64_i32(tmp, tmp2); - } + if ((op & 0x20) || !(op & 8)) { + /* Signed/unsigned 64-bit multiply, in decodetree */ + tcg_temp_free_i32(tmp2); + tcg_temp_free_i32(tmp); + goto illegal_op; } - if (op & 4) { - /* umaal */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i64(tmp64); - goto illegal_op; - } - gen_addq_lo(s, tmp64, rs); - gen_addq_lo(s, tmp64, rd); - } else if (op & 0x40) { + /* smlalxy */ + if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + tcg_temp_free_i32(tmp2); + tcg_temp_free_i32(tmp); + goto illegal_op; + } + gen_mulxy(tmp, tmp2, op & 2, op & 1); + tcg_temp_free_i32(tmp2); + tmp64 = tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(tmp64, tmp); + tcg_temp_free_i32(tmp); + if (op & 0x40) { /* 64-bit accumulate. */ gen_addq(s, tmp64, rs, rd); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 286adcbf89..87bbb2eec2 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -25,6 +25,8 @@ &s_rrr_shi s rd rn rm shim shty &s_rrr_shr s rn rd rm rs shty &s_rri_rot s rn rd imm rot +&s_rrrr s rd rn rm ra +&rrrr rd rn rm ra # Data-processing (register) @@ -105,3 +107,18 @@ ORR_rri .... 001 1100 . .... .... ............ @s_rri_rot MOV_rxi .... 001 1101 . 0000 .... ............ @s_rxi_rot BIC_rri .... 001 1110 . .... .... ............ @s_rri_rot MVN_rxi .... 001 1111 . 0000 .... ............ @s_rxi_rot + +# Multiply and multiply accumulate + +@s_rdamn ---- .... ... s:1 rd:4 ra:4 rm:4 .... rn:4 &s_rrrr +@s_rd0mn ---- .... ... s:1 rd:4 .... rm:4 .... rn:4 &s_rrrr ra=0 +@rdamn ---- .... ... . rd:4 ra:4 rm:4 .... rn:4 &rrrr + +MUL .... 0000 000 . .... 0000 .... 1001 .... @s_rd0mn +MLA .... 0000 001 . .... .... .... 1001 .... @s_rdamn +UMAAL .... 0000 010 0 .... .... .... 1001 .... @rdamn +MLS .... 0000 011 0 .... .... .... 1001 .... @rdamn +UMULL .... 0000 100 . .... .... .... 1001 .... @s_rdamn +UMLAL .... 0000 101 . .... .... .... 1001 .... @s_rdamn +SMULL .... 0000 110 . .... .... .... 1001 .... @s_rdamn +SMLAL .... 0000 111 . .... .... .... 1001 .... @s_rdamn diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 50cbe48cc8..40cc69aee3 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -22,6 +22,8 @@ &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot +&s_rrrr !extern s rd rn rm ra +&rrrr !extern rd rn rm ra # Data-processing (register) @@ -109,3 +111,20 @@ SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot } RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot + +# Multiply and multiply accumulate + +@s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0 +@s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra=0 s=0 +@rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr + +{ + MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm + MLA 1111 1011 0000 .... .... .... 0000 .... @s0_rnadm +} +MLS 1111 1011 0000 .... .... .... 0001 .... @rnadm +SMULL 1111 1011 1000 .... .... .... 0000 .... @s0_rnadm +UMULL 1111 1011 1010 .... .... .... 0000 .... @s0_rnadm +SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm +UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm +UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm From patchwork Mon Aug 19 21:36:54 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:54 -0700 Message-Id: <20190819213755.26175-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 07/68] target/arm: Simplify UMAAL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since all of the inputs and outputs are i32, dispense with the intermediate promotion to i64 and use tcg_gen_mulu2_i32 and tcg_gen_add2_i32. Signed-off-by: Richard Henderson --- target/arm/translate.c | 34 ++++++++++++---------------------- 1 file changed, 12 insertions(+), 22 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 94659086c0..82bd207799 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7324,21 +7324,6 @@ static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val) store_reg(s, rhigh, tmp); } -/* load a 32-bit value from a register and perform a 64-bit accumulate. */ -static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow) -{ - TCGv_i64 tmp; - TCGv_i32 tmp2; - - /* Load value and extend to 64 bits. */ - tmp = tcg_temp_new_i64(); - tmp2 = load_reg(s, rlow); - tcg_gen_extu_i32_i64(tmp, tmp2); - tcg_temp_free_i32(tmp2); - tcg_gen_add_i64(val, val, tmp); - tcg_temp_free_i64(tmp); -} - /* load and add a 64-bit value from a register pair. */ static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh) { @@ -8090,8 +8075,7 @@ static bool trans_SMLAL(DisasContext *s, arg_SMLAL *a) static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) { - TCGv_i32 t0, t1; - TCGv_i64 t64; + TCGv_i32 t0, t1, t2, zero; if (s->thumb ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) @@ -8101,11 +8085,17 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) t0 = load_reg(s, a->rm); t1 = load_reg(s, a->rn); - t64 = gen_mulu_i64_i32(t0, t1); - gen_addq_lo(s, t64, a->ra); - gen_addq_lo(s, t64, a->rd); - gen_storeq_reg(s, a->ra, a->rd, t64); - tcg_temp_free_i64(t64); + tcg_gen_mulu2_i32(t0, t1, t0, t1); + zero = tcg_const_i32(0); + t2 = load_reg(s, a->ra); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); + tcg_temp_free_i32(t2); + t2 = load_reg(s, a->rd); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(zero); + store_reg(s, a->ra, t0); + store_reg(s, a->rd, t1); return true; } From patchwork Mon Aug 19 21:36:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171670 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3534865ily; Mon, 19 Aug 2019 14:45:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqyf7POVxdpttq+W4tma9XVxl6KXslmJ0TtlGf5rjjBYsJXBehtrUPOmRq93KJUDmkCC7VU+ X-Received: by 2002:a17:906:b29a:: with SMTP id q26mr23080125ejz.144.1566251157006; Mon, 19 Aug 2019 14:45:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566251157; cv=none; d=google.com; s=arc-20160816; b=f55Tk0hFLKV+lHrqzO1sIodXNeGKizLAr9TfEVNMmBpNfY8h9+kjLQOPE7h59KbMD2 l9c8xS5aKuDyXul5Mze4k1ijuL9OCK8dQTELeZJnRVFEtF+ceY5rw6rcq1vRfz5DehZK /pQ7EPYEup8yJhGktEvUekDRgAhFRyKCRDr+uzzpXJhn47KwZ8h1gUqefI+J8NhPGtkA Inso5aRvaB9ahyUDpr1YiErEz7Z/E3EaBtr2/nZxcVKsTQObxQ6J3nMQKHIydoyLHXSJ rY0ef2y1FP9b2pLWM1cJNLpBzMPk/7a0y3tqOsW7IAfdefMcZh63gEvznRHlwyH0E1qc DNyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=4Nawwn1CWQIrW/uHwTKLseXI15oBdHOjRF/v0JlzLb8=; b=Po234RzFF2S0LplYd+1DHAZVRtlFrb150VpDTZ0UdAdwggTGXSkRss5W+w7zn19g3f WiPDCIaCKgu0HkfBw3RhRz6QhrxKc52U72qgA2N2nKu7lhZm/65HtyPSZYR1Nv9ihXVX lyz7XVHHl7opgnfErLmHn+mf2q0gkXQKKCjiL22HTnCvzKiBUAv1aQDGw9XDY1Kgkdzw FI9bjBgMN69xphfok+JM3UOYzg2PPB3/ViwY1juY0aSjj3pO8GBw8XuPEZ1RJzfnKprT +Puyf7Ix8FTBcvDyxsyeeFlRCfcPO+WMda0FkTvVcf1wG8pzCSBj4riHNTjwEKMdxSzq XQcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=oRigrk3o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:55 -0700 Message-Id: <20190819213755.26175-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 08/68] target/arm: Convert Saturating addition and subtraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 75 +++++++++++++++++++++++++++--------------- target/arm/a32.decode | 10 ++++++ target/arm/t32.decode | 9 +++++ 3 files changed, 67 insertions(+), 27 deletions(-) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/translate.c b/target/arm/translate.c index 82bd207799..b731e08fe4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8099,6 +8099,48 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) return true; } +/* + * Saturating addition and subtraction + */ + +static bool op_qaddsub(DisasContext *s, arg_rrr *a, bool add, bool doub) +{ + TCGv_i32 t0, t1; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_5TE) { + return false; + } + + t0 = load_reg(s, a->rm); + t1 = load_reg(s, a->rn); + if (doub) { + gen_helper_add_saturate(t1, cpu_env, t1, t1); + } + if (add) { + gen_helper_add_saturate(t0, cpu_env, t0, t1); + } else { + gen_helper_sub_saturate(t0, cpu_env, t0, t1); + } + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +#define DO_QADDSUB(NAME, ADD, DOUB) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_qaddsub(s, a, ADD, DOUB); \ +} + +DO_QADDSUB(QADD, true, false) +DO_QADDSUB(QSUB, false, false) +DO_QADDSUB(QDADD, true, true) +DO_QADDSUB(QDSUB, false, true) + +#undef DO_QADDSUB + /* * Legacy decoder. */ @@ -8508,21 +8550,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) store_reg(s, rd, tmp); break; } - case 0x5: /* saturating add/subtract */ - ARCH(5TE); - rd = (insn >> 12) & 0xf; - rn = (insn >> 16) & 0xf; - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rn); - if (op1 & 2) - gen_helper_add_saturate(tmp2, cpu_env, tmp2, tmp2); - if (op1 & 1) - gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2); - else - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + case 0x5: + /* Saturating addition and subtraction. */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0x6: /* ERET */ if (op1 != 3) { goto illegal_op; @@ -9989,18 +10020,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7); if (op < 4) { /* Saturating add/subtract. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - if (op & 1) - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp); - if (op & 2) - gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp); - else - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } else { switch (op) { case 0x0a: /* rbit */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 87bbb2eec2..7791be5590 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -27,6 +27,7 @@ &s_rri_rot s rn rd imm rot &s_rrrr s rd rn rm ra &rrrr rd rn rm ra +&rrr rd rn rm # Data-processing (register) @@ -122,3 +123,12 @@ UMULL .... 0000 100 . .... .... .... 1001 .... @s_rdamn UMLAL .... 0000 101 . .... .... .... 1001 .... @s_rdamn SMULL .... 0000 110 . .... .... .... 1001 .... @s_rdamn SMLAL .... 0000 111 . .... .... .... 1001 .... @s_rdamn + +# Saturating addition and subtraction + +@rndm ---- .... .... rn:4 rd:4 .... .... rm:4 &rrr + +QADD .... 0001 0000 .... .... 0000 0101 .... @rndm +QSUB .... 0001 0010 .... .... 0000 0101 .... @rndm +QDADD .... 0001 0100 .... .... 0000 0101 .... @rndm +QDSUB .... 0001 0110 .... .... 0000 0101 .... @rndm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 40cc69aee3..7c6226e0af 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra +&rrr !extern rd rn rm # Data-processing (register) @@ -117,6 +118,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0 @s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra=0 s=0 @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr +@rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr { MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm @@ -128,3 +130,10 @@ UMULL 1111 1011 1010 .... .... .... 0000 .... @s0_rnadm SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm + +# Data-processing (two source registers) + +QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm +QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm +QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm +QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm From patchwork Mon Aug 19 21:36:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171669 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3534622ily; Mon, 19 Aug 2019 14:45:39 -0700 (PDT) X-Google-Smtp-Source: APXvYqzGF6tx5snvunt1DAKrsROOM4guqzVdGSsJZqW81gJ5+ZWWDKf1AwFG+GdE1iPHHNw5iBVc X-Received: by 2002:a17:906:8143:: with SMTP id z3mr22931810ejw.4.1566251139728; Mon, 19 Aug 2019 14:45:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566251139; cv=none; d=google.com; s=arc-20160816; b=uwOBdlwcWUY3KR1LwEWItAB80OcLXaP960SHUz6+gYTBwp7m0Y1x9RSsa3T7s8itwE A+45HmrsbWHz/CBdgBYK80buuvaYCjy5sSfjHo22gBDdeHVQN5OfYH2SnoG7SV1tHXrp zlFSnQaAplKnN5Yg1wYhJwFdlhEpQKvGjAu4Adg6DxFm4aEz4Ycx1qwhKUANE5x5BmQy Xbq+1yrEckmXwwWHwvJ2J7vsB/yJ3bjaI4UPYRwBWuPElD9X6Hi2p/9MuAFDRxT3C3Yc yhmr61n8oIc17+E0schqOmmOXHOnk4XT80n8ExnJzCwxDX9N4J4zHNEY4tOavF5RqeHx Fa8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=FEq/15vwK0NtvonTorhtMB0UzZJdmnn/K7430AdfD8A=; b=nLrldY6/Y14WbxHiV+guGUfpNQFDOFXAqAphkqTZBIzT/69UczP/WdX0GtODUi/Sp+ pvf2pdxzgJGKgdeC/dW5WlxxU4zCJiujju5267JKAcliuUCPW6lKcOhHy7rwSzSruKii tHNcxXcnS26bx7VEd6GnbaoGWfbBO4ZcRe2h9/x7OkDphxQT/Vgbz0OW4N2YcYAJtxDs 8O9QsTDmr2OX/Nwd+vC8VtsIx6AGjwbiGBr00qNVT5o50kNm97AQOqlkdwcoJ0jX2hXK tI2wLLC/DVtLx6MEGo1r7oOs2c4eEBOSNe2YMHnKT7KX7A7cQDPj4DKK9e7/Ct4Ji3QQ Wq+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pDgHGQTv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 09/68] target/arm: Convert Halfword multiply and multiply accumulate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 218 +++++++++++++++++++++++------------------ target/arm/a32.decode | 20 ++++ target/arm/t32.decode | 29 ++++++ 3 files changed, 170 insertions(+), 97 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index b731e08fe4..56ae83a7d0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8141,6 +8141,117 @@ DO_QADDSUB(QDSUB, false, true) #undef DO_QADDSUB +/* + * Halfword multiply and multiply accumulate + */ + +static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, + int add_long, bool nt, bool mt) +{ + TCGv_i32 t0, t1; + TCGv_i64 t64; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_5TE) { + return false; + } + + t0 = load_reg(s, a->rn); + t1 = load_reg(s, a->rm); + gen_mulxy(t0, t1, nt, mt); + tcg_temp_free_i32(t1); + + switch (add_long) { + case 0: + store_reg(s, a->rd, t0); + break; + case 1: + t1 = load_reg(s, a->ra); + gen_helper_add_setq(t0, cpu_env, t0, t1); + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + break; + case 2: + t64 = tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(t64, t0); + tcg_temp_free_i32(t0); + gen_addq(s, t64, a->ra, a->rd); + gen_storeq_reg(s, a->ra, a->rd, t64); + tcg_temp_free_i64(t64); + break; + default: + g_assert_not_reached(); + } + return true; +} + +#define DO_SMLAX(NAME, add, nt, mt) \ +static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \ +{ \ + return op_smlaxxx(s, a, add, nt, mt); \ +} + +DO_SMLAX(SMULBB, 0, 0, 0) +DO_SMLAX(SMULBT, 0, 0, 1) +DO_SMLAX(SMULTB, 0, 1, 0) +DO_SMLAX(SMULTT, 0, 1, 1) + +DO_SMLAX(SMLABB, 1, 0, 0) +DO_SMLAX(SMLABT, 1, 0, 1) +DO_SMLAX(SMLATB, 1, 1, 0) +DO_SMLAX(SMLATT, 1, 1, 1) + +DO_SMLAX(SMLALBB, 2, 0, 0) +DO_SMLAX(SMLALBT, 2, 0, 1) +DO_SMLAX(SMLALTB, 2, 1, 0) +DO_SMLAX(SMLALTT, 2, 1, 1) + +#undef DO_SMLAX + +static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt) +{ + TCGv_i32 t0, t1; + TCGv_i64 t64; + + if (!ENABLE_ARCH_5TE) { + return false; + } + + t0 = load_reg(s, a->rn); + t1 = load_reg(s, a->rm); + if (mt) { + tcg_gen_sari_i32(t1, t1, 16); + } else { + gen_sxth(t1); + } + t64 = gen_muls_i64_i32(t0, t1); + tcg_gen_shri_i64(t64, t64, 16); + t1 = tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(t1, t64); + tcg_temp_free_i64(t64); + if (add) { + t0 = load_reg(s, a->ra); + gen_helper_add_setq(t1, cpu_env, t1, t0); + tcg_temp_free_i32(t0); + } + store_reg(s, a->rd, t1); + return true; +} + +#define DO_SMLAWX(NAME, add, mt) \ +static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \ +{ \ + return op_smlawx(s, a, add, mt); \ +} + +DO_SMLAWX(SMULWB, 0, 0) +DO_SMLAWX(SMULWT, 0, 1) +DO_SMLAWX(SMLAWB, 1, 0) +DO_SMLAWX(SMLAWT, 1, 1) + +#undef DO_SMLAWX + /* * Legacy decoder. */ @@ -8607,56 +8718,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } break; } - case 0x8: /* signed multiply */ + case 0x8: case 0xa: case 0xc: case 0xe: - ARCH(5TE); - rs = (insn >> 8) & 0xf; - rn = (insn >> 12) & 0xf; - rd = (insn >> 16) & 0xf; - if (op1 == 1) { - /* (32 * 16) >> 16 */ - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rs); - if (sh & 4) - tcg_gen_sari_i32(tmp2, tmp2, 16); - else - gen_sxth(tmp2); - tmp64 = gen_muls_i64_i32(tmp, tmp2); - tcg_gen_shri_i64(tmp64, tmp64, 16); - tmp = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tmp64); - tcg_temp_free_i64(tmp64); - if ((sh & 2) == 0) { - tmp2 = load_reg(s, rn); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rd, tmp); - } else { - /* 16 * 16 */ - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rs); - gen_mulxy(tmp, tmp2, sh & 2, sh & 4); - tcg_temp_free_i32(tmp2); - if (op1 == 2) { - tmp64 = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_temp_free_i32(tmp); - gen_addq(s, tmp64, rn, rd); - gen_storeq_reg(s, rn, rd, tmp64); - tcg_temp_free_i64(tmp64); - } else { - if (op1 == 0) { - tmp2 = load_reg(s, rn); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rd, tmp); - } - } - break; + /* Halfword multiply and multiply accumulate. */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; default: goto illegal_op; } @@ -10108,13 +10176,14 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) break; case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */ switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32, in decodetree */ + case 0: /* 32 x 32 -> 32 */ + case 1: /* 16 x 16 -> 32 */ + case 3: /* 32 * 16 -> 32msb */ + /* in decodetree */ goto illegal_op; case 7: /* Unsigned sum of absolute differences. */ break; - case 1: /* 16 x 16 -> 32 */ case 2: /* Dual multiply add. */ - case 3: /* 32 * 16 -> 32msb */ case 4: /* Dual multiply subtract. */ case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { @@ -10126,15 +10195,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tmp = load_reg(s, rn); tmp2 = load_reg(s, rm); switch ((insn >> 20) & 7) { - case 1: /* 16 x 16 -> 32 */ - gen_mulxy(tmp, tmp2, op & 2, op & 1); - tcg_temp_free_i32(tmp2); - if (rs != 15) { - tmp2 = load_reg(s, rs); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; case 2: /* Dual multiply add. */ case 4: /* Dual multiply subtract. */ if (op) @@ -10158,23 +10218,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(tmp2); } break; - case 3: /* 32 * 16 -> 32msb */ - if (op) - tcg_gen_sari_i32(tmp2, tmp2, 16); - else - gen_sxth(tmp2); - tmp64 = gen_muls_i64_i32(tmp, tmp2); - tcg_gen_shri_i64(tmp64, tmp64, 16); - tmp = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tmp64); - tcg_temp_free_i64(tmp64); - if (rs != 15) - { - tmp2 = load_reg(s, rs); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2); if (rs != 15) { @@ -10248,29 +10291,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) gen_storeq_reg(s, rs, rd, tmp64); tcg_temp_free_i64(tmp64); } else { - if ((op & 0x20) || !(op & 8)) { - /* Signed/unsigned 64-bit multiply, in decodetree */ - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - /* smlalxy */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - gen_mulxy(tmp, tmp2, op & 2, op & 1); + /* Signed/unsigned 64-bit multiply, in decodetree */ tcg_temp_free_i32(tmp2); - tmp64 = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); tcg_temp_free_i32(tmp); - if (op & 0x40) { - /* 64-bit accumulate. */ - gen_addq(s, tmp64, rs, rd); - } - gen_storeq_reg(s, rs, rd, tmp64); - tcg_temp_free_i64(tmp64); + goto illegal_op; } break; } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 7791be5590..19d12e726b 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -114,6 +114,7 @@ MVN_rxi .... 001 1111 . 0000 .... ............ @s_rxi_rot @s_rdamn ---- .... ... s:1 rd:4 ra:4 rm:4 .... rn:4 &s_rrrr @s_rd0mn ---- .... ... s:1 rd:4 .... rm:4 .... rn:4 &s_rrrr ra=0 @rdamn ---- .... ... . rd:4 ra:4 rm:4 .... rn:4 &rrrr +@rd0mn ---- .... ... . rd:4 .... rm:4 .... rn:4 &rrrr ra=0 MUL .... 0000 000 . .... 0000 .... 1001 .... @s_rd0mn MLA .... 0000 001 . .... .... .... 1001 .... @s_rdamn @@ -132,3 +133,22 @@ QADD .... 0001 0000 .... .... 0000 0101 .... @rndm QSUB .... 0001 0010 .... .... 0000 0101 .... @rndm QDADD .... 0001 0100 .... .... 0000 0101 .... @rndm QDSUB .... 0001 0110 .... .... 0000 0101 .... @rndm + +# Halfword multiply and multiply accumulate + +SMLABB .... 0001 0000 .... .... .... 1000 .... @rdamn +SMLABT .... 0001 0000 .... .... .... 1100 .... @rdamn +SMLATB .... 0001 0000 .... .... .... 1010 .... @rdamn +SMLATT .... 0001 0000 .... .... .... 1110 .... @rdamn +SMLAWB .... 0001 0010 .... .... .... 1000 .... @rdamn +SMULWB .... 0001 0010 .... 0000 .... 1010 .... @rd0mn +SMLAWT .... 0001 0010 .... .... .... 1100 .... @rdamn +SMULWT .... 0001 0010 .... 0000 .... 1110 .... @rd0mn +SMLALBB .... 0001 0100 .... .... .... 1000 .... @rdamn +SMLALBT .... 0001 0100 .... .... .... 1100 .... @rdamn +SMLALTB .... 0001 0100 .... .... .... 1010 .... @rdamn +SMLALTT .... 0001 0100 .... .... .... 1110 .... @rdamn +SMULBB .... 0001 0110 .... 0000 .... 1000 .... @rd0mn +SMULBT .... 0001 0110 .... 0000 .... 1100 .... @rd0mn +SMULTB .... 0001 0110 .... 0000 .... 1010 .... @rd0mn +SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 7c6226e0af..122a0537ed 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -118,6 +118,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0 @s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra=0 s=0 @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr +@rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &rrrr ra=0 @rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr { @@ -130,6 +131,34 @@ UMULL 1111 1011 1010 .... .... .... 0000 .... @s0_rnadm SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm +{ + SMULWB 1111 1011 0011 .... 1111 .... 0000 .... @rn0dm + SMLAWB 1111 1011 0011 .... .... .... 0000 .... @rnadm +} +{ + SMULWT 1111 1011 0011 .... 1111 .... 0001 .... @rn0dm + SMLAWT 1111 1011 0011 .... .... .... 0001 .... @rnadm +} +{ + SMULBB 1111 1011 0001 .... 1111 .... 0000 .... @rn0dm + SMLABB 1111 1011 0001 .... .... .... 0000 .... @rnadm +} +{ + SMULBT 1111 1011 0001 .... 1111 .... 0001 .... @rn0dm + SMLABT 1111 1011 0001 .... .... .... 0001 .... @rnadm +} +{ + SMULTB 1111 1011 0001 .... 1111 .... 0010 .... @rn0dm + SMLATB 1111 1011 0001 .... .... .... 0010 .... @rnadm +} +{ + SMULTT 1111 1011 0001 .... 1111 .... 0011 .... @rn0dm + SMLATT 1111 1011 0001 .... .... .... 0011 .... @rnadm +} +SMLALBB 1111 1011 1100 .... .... .... 1000 .... @rnadm +SMLALBT 1111 1011 1100 .... .... .... 1001 .... @rnadm +SMLALTB 1111 1011 1100 .... .... .... 1010 .... @rnadm +SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm # Data-processing (two source registers) From patchwork Mon Aug 19 21:36:57 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:57 -0700 Message-Id: <20190819213755.26175-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v2 10/68] target/arm: Simplify op_smlaxxx for SMLAL* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since all of the inputs and outputs are i32, dispense with the intermediate promotion to i64 and use tcg_gen_add2_i32. Signed-off-by: Richard Henderson --- target/arm/translate.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 56ae83a7d0..8557ef831f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8148,8 +8148,7 @@ DO_QADDSUB(QDSUB, false, true) static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, int add_long, bool nt, bool mt) { - TCGv_i32 t0, t1; - TCGv_i64 t64; + TCGv_i32 t0, t1, tl, th; if (s->thumb ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) @@ -8173,12 +8172,14 @@ static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, store_reg(s, a->rd, t0); break; case 2: - t64 = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(t64, t0); + tl = load_reg(s, a->ra); + th = load_reg(s, a->rd); + t1 = tcg_const_i32(0); + tcg_gen_add2_i32(tl, th, tl, th, t0, t1); tcg_temp_free_i32(t0); - gen_addq(s, t64, a->ra, a->rd); - gen_storeq_reg(s, a->ra, a->rd, t64); - tcg_temp_free_i64(t64); + tcg_temp_free_i32(t1); + store_reg(s, a->ra, tl); + store_reg(s, a->rd, th); break; default: g_assert_not_reached(); From patchwork Mon Aug 19 21:36:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171671 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3534952ily; Mon, 19 Aug 2019 14:46:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqypOKQZNHQKWS5SWYGB2k3CMbTw3HtYCE2FXRMUo7eVNK7BeV+N45YaAZBfiPv/pV8Nh3ur X-Received: by 2002:a0c:e64d:: with SMTP id c13mr12379140qvn.80.1566251163583; Mon, 19 Aug 2019 14:46:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566251163; cv=none; d=google.com; s=arc-20160816; b=VHJsvJZ6l7CL1351Mi8Wri5dQ2yFcuswVFs1JLCPaJgAehK3VuDrB6YcpzZDOL5tQt HRv4rQCNNgz5Ure6CO/Y4I+5zIjwhk1y3ziNlZnrKpL1nrFdFhzxpLlRXh6ftllEGXWN w8pJkSjt52WCC/WSbAztbTn/lj1Z+H+qLBg630rN0XukgeBfEEQTZvCAsmGLS0w0Bix3 N6gfZV2/8oytGEiWLv0NsJIZChLBsAVtfSNXszfXdeVYiX7+0yAoDgI14LifEfZFcPpz adr84IOLFiKVyATHrai7lzGX8v20bXem1l5UZK3gklY21BKVNCkw/vRL76wb66izdKd3 k+aA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=z6bTZIJUuD2Rb2udZZO8tN325lpohcam+cQYkXY7q0k=; b=U3NTIGy4cKa149vxGy/Vgz67sCtj1PwG1qqOW4ziJL3OIkl0w7L0jkXHVzNffC5pfd eGFmKz0BVuwBwqfEl+ikHnRTvsGQ+dxMF94kKI21nGfNr4qKBUNg+ffxpmOUs0NNCbGQ fFVcbhY2PVh7HJPoHSNhsJi1gQHbH8nqHIFHWrJQe2ZwiH8qe26Rx6BmxR8zFGpGTRZa WbQTiVf+maKCJnXsuVDXjFjBt+9Qe300OzOyV1znF9OC8Qst0loYYOBRXe2fTvYHKzgA ZKzvmPGYN0QBgNCVqaWIOuw1mHLrY5pAGkhiSYJsLpGRg9+xrxcm+33f1WA2Y6RKnmVl jeEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YZ0YyngK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:58 -0700 Message-Id: <20190819213755.26175-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 11/68] target/arm: Simplify op_smlawx for SMLAW* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" By shifting the 16-bit input left by 16, we can align the desired portion of the 48-bit product and use tcg_gen_muls2_i32. Signed-off-by: Richard Henderson --- target/arm/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 8557ef831f..9a2fb7d3aa 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8213,7 +8213,6 @@ DO_SMLAX(SMLALTT, 2, 1, 1) static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt) { TCGv_i32 t0, t1; - TCGv_i64 t64; if (!ENABLE_ARCH_5TE) { return false; @@ -8221,16 +8220,17 @@ static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt) t0 = load_reg(s, a->rn); t1 = load_reg(s, a->rm); + /* + * Since the nominal result is product<47:16>, shift the 16-bit + * input up by 16 bits, so that the result is at product<63:32>. + */ if (mt) { - tcg_gen_sari_i32(t1, t1, 16); + tcg_gen_andi_i32(t1, t1, 0xffff0000); } else { - gen_sxth(t1); + tcg_gen_shli_i32(t1, t1, 16); } - t64 = gen_muls_i64_i32(t0, t1); - tcg_gen_shri_i64(t64, t64, 16); - t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, t64); - tcg_temp_free_i64(t64); + tcg_gen_muls2_i32(t0, t1, t0, t1); + tcg_temp_free_i32(t0); if (add) { t0 = load_reg(s, a->ra); gen_helper_add_setq(t1, cpu_env, t1, t0); From patchwork Mon Aug 19 21:36:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171674 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3538091ily; Mon, 19 Aug 2019 14:50:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqwl/g31akfSqslmYLPVrESVqstXfgQdzm+N99x6LRTZIyM3timb9Sk0NlOKR4UPWiGvquVY X-Received: by 2002:a17:906:852:: with SMTP id f18mr23381262ejd.18.1566251423017; Mon, 19 Aug 2019 14:50:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566251423; cv=none; d=google.com; s=arc-20160816; b=BgGlRlXk6LpMxQ4K0B9gcr901K995Nflw4QH3g3mWY5jQpm2BHO2w3PLXT24j2zncA Gl5viQd0sHCMvD9wGkYAFsgPFtot3A5NCCRSIKlrDNiNF4n76CCz7iAfL7l3y0/dcTMQ aa5l0pV4TxZ1mhzXsZFeaj3X79J+5PUPSqiuJEGnV3kzMcFQDiR6VqLnBDOBQRSdDu30 MYfSFlQD09jesJyzNtYiXCiSSL5JAfn97zqim3U85jnRmQ5bowTMVUQCWRCVYven55S5 QR1uIUvjX6+BPQ7nZYuTa4vNqIvT4En47Yj9fdyJbRN7p7Vm9RE0E13CsGyQFmWLSY00 HFYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=aKVuzxBlVmXAfmZOcitSo8oovzmAL9rVEMNxLaYaWGo=; b=HGTYmaUPTHRFe9Xfch4FjXrain6tiK0xCT1irVL1VmYx1NRrMnC4vmQ69ABThH687p 6pn1QAV4IIFW6JvksznQb6jWR7kvBAn6/QN0kbKeLqoxitNNzM7bgynWeHhsBpVGfnJB lvufQ7jSTtfzBsEdLjELd1iz0JLj2dhhSKx/KhbOGAy06xtClXjOA8ZKHXkCpZeNhIHi TG+kNSXv2QSqbgGiqdYk1rC+Yv7NKFwKTqn++6m26JGtdOp0wIjoGWp0Dlyi9xKfF7bg piObZONbomqQ0IiCF/c7zlFO+/530EyXF7GZ0igo3wXVEe0nOBv1tmvNx8asllUqizFp By3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bMhxjcUT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:59 -0700 Message-Id: <20190819213755.26175-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v2 12/68] target/arm: Convert MSR (immediate) and hints X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 60 +++++++++++++++++++++++++++++------------- target/arm/a32.decode | 25 ++++++++++++++++++ target/arm/t32.decode | 17 ++++++++++++ 3 files changed, 84 insertions(+), 18 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 9a2fb7d3aa..ee485b1cbd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8253,6 +8253,44 @@ DO_SMLAWX(SMLAWT, 1, 1) #undef DO_SMLAWX +/* + * MSR (immediate) and hints + */ + +static bool trans_YIELD(DisasContext *s, arg_YIELD *a) +{ + gen_nop_hint(s, 1); + return true; +} + +static bool trans_WFE(DisasContext *s, arg_WFE *a) +{ + gen_nop_hint(s, 2); + return true; +} + +static bool trans_WFI(DisasContext *s, arg_WFI *a) +{ + gen_nop_hint(s, 3); + return true; +} + +static bool trans_NOP(DisasContext *s, arg_NOP *a) +{ + return true; +} + +static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a) +{ + uint32_t val = ror32(a->imm, a->rot * 2); + uint32_t mask = msr_mask(s, a->mask, a->r); + + if (gen_set_psr_im(s, mask, a->r, val)) { + unallocated_encoding(s); + } + return true; +} + /* * Legacy decoder. */ @@ -8526,21 +8564,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } store_reg(s, rd, tmp); } else { - if (((insn >> 12) & 0xf) != 0xf) - goto illegal_op; - if (((insn >> 16) & 0xf) == 0) { - gen_nop_hint(s, insn & 0xff); - } else { - /* CPSR = immediate */ - val = insn & 0xff; - shift = ((insn >> 8) & 0xf) * 2; - val = ror32(val, shift); - i = ((insn & (1 << 22)) != 0); - if (gen_set_psr_im(s, msr_mask(s, (insn >> 16) & 0xf, i), - i, val)) { - goto illegal_op; - } - } + /* MSR (immediate) and hints */ + /* All done in decodetree. Illegal ops already signalled. */ + g_assert_not_reached(); } } else if ((insn & 0x0f900000) == 0x01000000 && (insn & 0x00000090) != 0x00000090) { @@ -10480,9 +10506,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; break; case 2: /* cps, nop-hint. */ - if (((insn >> 8) & 7) == 0) { - gen_nop_hint(s, insn & 0xff); - } + /* nop hints in decodetree */ /* Implemented as NOP in user mode. */ if (IS_USER(s)) break; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 19d12e726b..3d5c5408f9 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -22,6 +22,7 @@ # All insns that have 0xf in insn[31:28] are in a32-uncond.decode. # +&empty &s_rrr_shi s rd rn rm shim shty &s_rrr_shr s rn rd rm rs shty &s_rri_rot s rn rd imm rot @@ -152,3 +153,27 @@ SMULBB .... 0001 0110 .... 0000 .... 1000 .... @rd0mn SMULBT .... 0001 0110 .... 0000 .... 1100 .... @rd0mn SMULTB .... 0001 0110 .... 0000 .... 1010 .... @rd0mn SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn + +# MSR (immediate) and hints + +&msr_i r mask rot imm +@msr_i ---- .... .... mask:4 .... rot:4 imm:8 &msr_i + +{ + { + YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 + WFE ---- 0011 0010 0000 1111 ---- 0000 0010 + WFI ---- 0011 0010 0000 1111 ---- 0000 0011 + + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 + # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + + # The canonical nop ends in 00000000, but the whole of the + # rest of the space executes as nop if otherwise unsupported. + NOP ---- 0011 0010 0000 1111 ---- ---- ---- + } + # Note mask = 0 is covered by NOP + MSR_imm .... 0011 0010 .... 1111 .... .... .... @msr_i r=0 +} +MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=1 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 122a0537ed..ccb7cdd4ef 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -19,6 +19,7 @@ # This file is processed by scripts/decodetree.py # +&empty !extern &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot @@ -166,3 +167,19 @@ QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm + +# Branches and miscellaneous control + +{ + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 + + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + + # The canonical nop ends in 0000 0000, but the whole rest + # of the space is "reserved hint, behaves as nop". + NOP 1111 0011 1010 1111 1000 0000 ---- ---- +} From patchwork Mon Aug 19 21:37:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171679 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3540374ily; Mon, 19 Aug 2019 14:53:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqynwPIJjrtHcXeZ31Fh2+i0WgcklGUaEZQlbxqgyb1NsfBsQ6gPLrYwtXJ/tdx2OXmBOCwN X-Received: by 2002:a50:ac1a:: with SMTP id v26mr27602472edc.131.1566251612174; Mon, 19 Aug 2019 14:53:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566251612; cv=none; d=google.com; s=arc-20160816; b=LBv2Se3JArZ6amaFiq6FFAzUficrzbCSYekpW7voC+C9R+//Xm5L69HygB1avc124X snDFBNZwswfMQAa7pu13syFLlLx1XvJ5G/oduTg76yyqVdOnvmo+DrIDipa30FG+fNTS AG4IF0GazWwQw3MxPXDNh582lp7jyfbxtYWrUaL2pbeI2azn4llTGKPRajnKYgdGgOGA kup7bkjEUOadJHTCPaYSQ1JwPMzmGOMZCVB/gJI8Y+Z3Rt/rVHh/xY9yi1/5zYewZCmG R6gKob7K2bg6pywozujRG8D4/cZG7TXH5ZCdjpeH/qavIv7s++9eDuBvm0VktLjprf7r 8i/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=yfBEnFsdiAgak7aUP03KjpvGrVpxR8pw6hwr0KfqOzQ=; b=D08528owWzBgvvlWeLFZKzoF1jQk5WkQIVQWhr0jsGYcr8WaQX5On80pAvM1Vn81rN CmPjQj5ilXRLVTLK0J8zg36vfjj+y4PNTj7bCezIG6oD75f7KbvZlvhGZn59tPuLuZO0 3Kluk/r9yC92KI162PXzh7btisNdCZ9WLUIje0WZ18SYKirsiVHwCZVn/aN5uGZcL0/d qxJjl4W5bcZCnbZ2hP64DVQL5ZL0AkbhZG4hS28CJY4e87jiX5J7asZQqy8HSXOWnsqp FHqxMk6x/q8NB/gGeNOXY/8SfhXSuc1bh4Y3Oha74KnFRz1t88WkDBjQEOMVoB28EiZe u1iQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RkcDuxzr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:00 -0700 Message-Id: <20190819213755.26175-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 13/68] target/arm: Convert MRS/MSR (banked, register) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The m-profile and a-profile, decodings overlap. Only return false for the case of wrong profile; handle UNDEFINED for permission failure directly. This ensures that we don't accidentally pass an insn that applies to the wrong profile. Signed-off-by: Richard Henderson --- target/arm/translate.c | 226 ++++++++++++++++++----------------------- target/arm/a32.decode | 14 +++ target/arm/t32.decode | 40 ++++++-- 3 files changed, 142 insertions(+), 138 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index ee485b1cbd..026abcaa9c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8291,6 +8291,93 @@ static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a) return true; } +/* + * Miscellaneous instructions + */ + +static bool trans_MRS_bank(DisasContext *s, arg_MRS_bank *a) +{ + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_mrs_banked(s, a->r, a->sysm, a->rd); + return true; +} + +static bool trans_MSR_bank(DisasContext *s, arg_MSR_bank *a) +{ + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_msr_banked(s, a->r, a->sysm, a->rn); + return true; +} + +static bool trans_MRS_reg(DisasContext *s, arg_MRS_reg *a) +{ + TCGv_i32 tmp; + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (a->r) { + if (IS_USER(s)) { + unallocated_encoding(s); + return true; + } + tmp = load_cpu_field(spsr); + } else { + tmp = tcg_temp_new_i32(); + gen_helper_cpsr_read(tmp, cpu_env); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_MSR_reg(DisasContext *s, arg_MSR_reg *a) +{ + TCGv_i32 tmp; + uint32_t mask = msr_mask(s, a->mask, a->r); + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + tmp = load_reg(s, a->rn); + if (gen_set_psr(s, mask, a->r, tmp)) { + unallocated_encoding(s); + } + return true; +} + +static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a) +{ + TCGv_i32 tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + tmp = tcg_const_i32(a->sysm); + gen_helper_v7m_mrs(tmp, cpu_env, tmp); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) +{ + TCGv_i32 addr, reg; + + if (!arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + addr = tcg_const_i32((a->mask << 10) | a->sysm); + reg = load_reg(s, a->rn); + gen_helper_v7m_msr(cpu_env, addr, reg); + tcg_temp_free_i32(addr); + tcg_temp_free_i32(reg); + gen_lookup_tb(s); + return true; +} + /* * Legacy decoder. */ @@ -8575,46 +8662,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) sh = (insn >> 4) & 0xf; rm = insn & 0xf; switch (sh) { - case 0x0: /* MSR, MRS */ - if (insn & (1 << 9)) { - /* MSR (banked) and MRS (banked) */ - int sysm = extract32(insn, 16, 4) | - (extract32(insn, 8, 1) << 4); - int r = extract32(insn, 22, 1); - - if (op1 & 1) { - /* MSR (banked) */ - gen_msr_banked(s, r, sysm, rm); - } else { - /* MRS (banked) */ - int rd = extract32(insn, 12, 4); - - gen_mrs_banked(s, r, sysm, rd); - } - break; - } - - /* MSR, MRS (for PSRs) */ - if (op1 & 1) { - /* PSR = reg */ - tmp = load_reg(s, rm); - i = ((op1 & 2) != 0); - if (gen_set_psr(s, msr_mask(s, (insn >> 16) & 0xf, i), i, tmp)) - goto illegal_op; - } else { - /* reg = PSR */ - rd = (insn >> 12) & 0xf; - if (op1 & 2) { - if (IS_USER(s)) - goto illegal_op; - tmp = load_cpu_field(spsr); - } else { - tmp = tcg_temp_new_i32(); - gen_helper_cpsr_read(tmp, cpu_env); - } - store_reg(s, rd, tmp); - } - break; + case 0x0: + /* MSR/MRS (banked/register) */ + /* All done in decodetree. Illegal ops already signalled. */ + g_assert_not_reached(); case 0x1: if (op1 == 1) { /* branch/exchange thumb (bx). */ @@ -10471,40 +10522,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } else { op = (insn >> 20) & 7; switch (op) { - case 0: /* msr cpsr. */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - tmp = load_reg(s, rn); - /* the constant is the mask and SYSm fields */ - addr = tcg_const_i32(insn & 0xfff); - gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); - tcg_temp_free_i32(tmp); - gen_lookup_tb(s); - break; - } - /* fall through */ - case 1: /* msr spsr. */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - - if (extract32(insn, 5, 1)) { - /* MSR (banked) */ - int sysm = extract32(insn, 8, 4) | - (extract32(insn, 4, 1) << 4); - int r = op & 1; - - gen_msr_banked(s, r, sysm, rm); - break; - } - - /* MSR (for PSRs) */ - tmp = load_reg(s, rn); - if (gen_set_psr(s, - msr_mask(s, (insn >> 8) & 0xf, op == 1), - op == 1, tmp)) - goto illegal_op; - break; + case 0: /* msr cpsr, in decodetree */ + case 1: /* msr spsr, in decodetree */ + goto illegal_op; case 2: /* cps, nop-hint. */ /* nop hints in decodetree */ /* Implemented as NOP in user mode. */ @@ -10596,61 +10616,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } gen_exception_return(s, tmp); break; - case 6: /* MRS */ - if (extract32(insn, 5, 1) && - !arm_dc_feature(s, ARM_FEATURE_M)) { - /* MRS (banked) */ - int sysm = extract32(insn, 16, 4) | - (extract32(insn, 4, 1) << 4); - - gen_mrs_banked(s, 0, sysm, rd); - break; - } - - if (extract32(insn, 16, 4) != 0xf) { - goto illegal_op; - } - if (!arm_dc_feature(s, ARM_FEATURE_M) && - extract32(insn, 0, 8) != 0) { - goto illegal_op; - } - - /* mrs cpsr */ - tmp = tcg_temp_new_i32(); - if (arm_dc_feature(s, ARM_FEATURE_M)) { - addr = tcg_const_i32(insn & 0xff); - gen_helper_v7m_mrs(tmp, cpu_env, addr); - tcg_temp_free_i32(addr); - } else { - gen_helper_cpsr_read(tmp, cpu_env); - } - store_reg(s, rd, tmp); - break; - case 7: /* MRS */ - if (extract32(insn, 5, 1) && - !arm_dc_feature(s, ARM_FEATURE_M)) { - /* MRS (banked) */ - int sysm = extract32(insn, 16, 4) | - (extract32(insn, 4, 1) << 4); - - gen_mrs_banked(s, 1, sysm, rd); - break; - } - - /* mrs spsr. */ - /* Not accessible in user mode. */ - if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - - if (extract32(insn, 16, 4) != 0xf || - extract32(insn, 0, 8) != 0) { - goto illegal_op; - } - - tmp = load_cpu_field(spsr); - store_reg(s, rd, tmp); - break; + case 6: /* MRS, in decodetree */ + case 7: /* MSR, in decodetree */ + goto illegal_op; } } } else { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 3d5c5408f9..6ee12c1140 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -29,6 +29,10 @@ &s_rrrr s rd rn rm ra &rrrr rd rn rm ra &rrr rd rn rm +&msr_reg rn r mask +&mrs_reg rd r +&msr_bank rn r sysm +&mrs_bank rd r sysm # Data-processing (register) @@ -177,3 +181,13 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn MSR_imm .... 0011 0010 .... 1111 .... .... .... @msr_i r=0 } MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=1 + +# Miscellaneous instructions + +%sysm 8:1 16:4 + +MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %sysm +MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %sysm + +MRS_reg ---- 0001 0 r:1 00 1111 rd:4 0000 0000 0000 &mrs_reg +MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ccb7cdd4ef..98b682e7ec 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -26,6 +26,10 @@ &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra &rrr !extern rd rn rm +&msr_reg !extern rn r mask +&mrs_reg !extern rd r +&msr_bank !extern rn r sysm +&mrs_bank !extern rd r sysm # Data-processing (register) @@ -170,16 +174,34 @@ QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm # Branches and miscellaneous control +%msr_sysm 4:1 8:4 +%mrs_sysm 4:1 16:4 + { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + { + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 - # The canonical nop ends in 0000 0000, but the whole rest - # of the space is "reserved hint, behaves as nop". - NOP 1111 0011 1010 1111 1000 0000 ---- ---- + # The canonical nop ends in 0000 0000, but the whole rest + # of the space is "reserved hint, behaves as nop". + NOP 1111 0011 1010 1111 1000 0000 ---- ---- + } + # Note that the v7m insn overlaps both the normal and banked insn. + { + MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ + &mrs_bank sysm=%mrs_sysm + MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg + MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8 + } + { + MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \ + &msr_bank sysm=%msr_sysm + MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg + MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 + } } From patchwork Mon Aug 19 21:37:01 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:01 -0700 Message-Id: <20190819213755.26175-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 14/68] target/arm: Convert Cyclic Redundancy Check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 121 +++++++++++++++++++---------------------- target/arm/a32.decode | 9 +++ target/arm/t32.decode | 7 +++ 3 files changed, 72 insertions(+), 65 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 026abcaa9c..f390656ce9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8291,6 +8291,57 @@ static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a) return true; } +/* + * Cyclic Redundancy Check + */ + +static bool op_crc32(DisasContext *s, arg_rrr *a, bool c, TCGMemOp sz) +{ + TCGv_i32 t1, t2, t3; + + if (!dc_isar_feature(aa32_crc32, s)) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + switch (sz) { + case MO_8: + gen_uxtb(t2); + break; + case MO_16: + gen_uxth(t2); + break; + case MO_32: + break; + default: + g_assert_not_reached(); + } + t3 = tcg_const_i32(1 << sz); + if (c) { + gen_helper_crc32c(t1, t1, t2, t3); + } else { + gen_helper_crc32(t1, t1, t2, t3); + } + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + store_reg(s, a->rd, t1); + return true; +} + +#define DO_CRC32(NAME, c, sz) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ + { return op_crc32(s, a, c, sz); } + +DO_CRC32(CRC32B, false, MO_8) +DO_CRC32(CRC32H, false, MO_16) +DO_CRC32(CRC32W, false, MO_32) +DO_CRC32(CRC32CB, true, MO_8) +DO_CRC32(CRC32CH, true, MO_16) +DO_CRC32(CRC32CW, true, MO_32) + +#undef DO_CRC32 + /* * Miscellaneous instructions */ @@ -8706,39 +8757,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) gen_bx(s, tmp); break; case 0x4: - { - /* crc32/crc32c */ - uint32_t c = extract32(insn, 8, 4); - - /* Check this CPU supports ARMv8 CRC instructions. - * op1 == 3 is UNPREDICTABLE but handle as UNDEFINED. - * Bits 8, 10 and 11 should be zero. - */ - if (!dc_isar_feature(aa32_crc32, s) || op1 == 0x3 || (c & 0xd) != 0) { - goto illegal_op; - } - - rn = extract32(insn, 16, 4); - rd = extract32(insn, 12, 4); - - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - if (op1 == 0) { - tcg_gen_andi_i32(tmp2, tmp2, 0xff); - } else if (op1 == 1) { - tcg_gen_andi_i32(tmp2, tmp2, 0xffff); - } - tmp3 = tcg_const_i32(1 << op1); - if (c & 0x2) { - gen_helper_crc32c(tmp, tmp, tmp2, tmp3); - } else { - gen_helper_crc32(tmp, tmp, tmp2, tmp3); - } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); - store_reg(s, rd, tmp); - break; - } + /* crc32 */ + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; case 0x5: /* Saturating addition and subtraction. */ /* All done in decodetree. Reach here for illegal ops. */ @@ -10181,16 +10202,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; } break; - case 0x20: /* crc32/crc32c */ + case 0x20: /* crc32/crc32c, in decodetree */ case 0x21: case 0x22: case 0x28: case 0x29: case 0x2a: - if (!dc_isar_feature(aa32_crc32, s)) { - goto illegal_op; - } - break; + goto illegal_op; default: goto illegal_op; } @@ -10219,33 +10237,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 0x18: /* clz */ tcg_gen_clzi_i32(tmp, tmp, 32); break; - case 0x20: - case 0x21: - case 0x22: - case 0x28: - case 0x29: - case 0x2a: - { - /* crc32/crc32c */ - uint32_t sz = op & 0x3; - uint32_t c = op & 0x8; - - tmp2 = load_reg(s, rm); - if (sz == 0) { - tcg_gen_andi_i32(tmp2, tmp2, 0xff); - } else if (sz == 1) { - tcg_gen_andi_i32(tmp2, tmp2, 0xffff); - } - tmp3 = tcg_const_i32(1 << sz); - if (c) { - gen_helper_crc32c(tmp, tmp, tmp2, tmp3); - } else { - gen_helper_crc32(tmp, tmp, tmp2, tmp3); - } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); - break; - } default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 6ee12c1140..a8ef435b15 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -182,6 +182,15 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn } MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=1 +# Cyclic Redundancy Check + +CRC32B .... 0001 0000 .... .... 0000 0100 .... @rndm +CRC32H .... 0001 0010 .... .... 0000 0100 .... @rndm +CRC32W .... 0001 0100 .... .... 0000 0100 .... @rndm +CRC32CB .... 0001 0000 .... .... 0010 0100 .... @rndm +CRC32CH .... 0001 0010 .... .... 0010 0100 .... @rndm +CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm + # Miscellaneous instructions %sysm 8:1 16:4 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 98b682e7ec..261db100ff 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -172,6 +172,13 @@ QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm +CRC32B 1111 1010 1100 .... 1111 .... 1000 .... @rndm +CRC32H 1111 1010 1100 .... 1111 .... 1001 .... @rndm +CRC32W 1111 1010 1100 .... 1111 .... 1010 .... @rndm +CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm +CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm +CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm + # Branches and miscellaneous control %msr_sysm 4:1 8:4 From patchwork Mon Aug 19 21:37:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171675 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3538530ily; Mon, 19 Aug 2019 14:50:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqyLF3Oz83RwAEJss06SHdm+xZhRQJE0gW/cKPUy5R2hSNuSncWsZJMsaO9zCrnWJMO+18dp X-Received: by 2002:a05:6402:170f:: with SMTP id y15mr10020672edu.55.1566251456206; Mon, 19 Aug 2019 14:50:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566251456; cv=none; d=google.com; s=arc-20160816; b=Vr526oLhfXORyhtexAtHSiipvbpzqZ3edbmGOFV+oNBX0JqzNpPupjWO8vZgVQBH/D sqZvOM3+4ZHY1dwbZhHQtIxAE3SMRnPljMIY0LVmcH+Lb4rrjFxC2fbjkAQMircOJLf2 92ZjQw6C0e83/h/Dkf8dJS/nQWMBGQRZSVLgcmxfgOTPDhPR8aYx4fwTAMOaeeYAvq9n oCwwJiLIZZy1J+LjqRulcchUIgUNQRvX9Ra+WDIjuG4d+ryKfQ6Ch95azqCdgnjLwvVV LVirmeVMlKuuh4Gkf1w436shIIhl+UvAJ/F+GtHfR8CmNeQWVkKr2d3HSZlLj96WK4c/ WHGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=F/upwaanfqXSt3Hk/7WIkT0U11Hn2bkl0Zsc2jcodB0=; b=eD6bJEnnJDMjvwNdEv5rU0cbaU2jBhx2c+fppbTX8tkdXZiPJ4NO3wOFs6ILUQkc8I PRycA+fuyapod2B/gIQTqgEYxc+NDo3zXt5ybzWqyeJAMHurHN8U4hg0BJ70+1mjJWPz kfIZHScclajIizeV0Zcp53Y7YfGu5kY2KrmIaz9dixyKr1/+r7Hk3OZyHU1BwNL48pqd +aDWdOL6VGkv7bTsRII1iCkfEHAFDwvy2oYB0wg/VStw2s8r7I/T7eVbYF9PJ+lh5trs mzIvRRkxOohWSzNRCl/qW5n7q53DXkRSgzxVFRhpU+UXqRDWL+lFxEUyttchut+x1jrq Yucg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=s7d7yvxy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:02 -0700 Message-Id: <20190819213755.26175-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v2 15/68] target/arm: Convert BX, BXJ, BLX (register) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 78 ++++++++++++++++++++---------------------- target/arm/a32.decode | 7 ++++ target/arm/t32.decode | 2 ++ 3 files changed, 47 insertions(+), 40 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index f390656ce9..ef26ed7b57 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8429,6 +8429,38 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) return true; } +static bool trans_BX(DisasContext *s, arg_BX *a) +{ + if (!ENABLE_ARCH_4T) { + return false; + } + gen_bx(s, load_reg(s, a->rm)); + return true; +} + +static bool trans_BXJ(DisasContext *s, arg_BXJ *a) +{ + if (!ENABLE_ARCH_5J || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + /* Trivial implementation equivalent to bx. */ + gen_bx(s, load_reg(s, a->rm)); + return true; +} + +static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_5) { + return false; + } + tmp = load_reg(s, a->rm); + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_bx(s, tmp); + return true; +} + /* * Legacy decoder. */ @@ -8718,12 +8750,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* All done in decodetree. Illegal ops already signalled. */ g_assert_not_reached(); case 0x1: - if (op1 == 1) { - /* branch/exchange thumb (bx). */ - ARCH(4T); - tmp = load_reg(s, rm); - gen_bx(s, tmp); - } else if (op1 == 3) { + if (op1 == 3) { /* clz */ ARCH(5); rd = (insn >> 12) & 0xf; @@ -8734,30 +8761,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) goto illegal_op; } break; - case 0x2: - if (op1 == 1) { - ARCH(5J); /* bxj */ - /* Trivial implementation equivalent to bx. */ - tmp = load_reg(s, rm); - gen_bx(s, tmp); - } else { - goto illegal_op; - } - break; - case 0x3: - if (op1 != 1) - goto illegal_op; - - ARCH(5); - /* branch link/exchange thumb (blx) */ - tmp = load_reg(s, rm); - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, s->base.pc_next); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - break; - case 0x4: - /* crc32 */ + case 0x2: /* bxj */ + case 0x3: /* blx */ + case 0x4: /* crc32 */ /* All done in decodetree. Illegal ops reach here. */ goto illegal_op; case 0x5: @@ -10578,16 +10584,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; } break; - case 4: /* bxj */ - /* Trivial implementation equivalent to bx. - * This instruction doesn't exist at all for M-profile. - */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - tmp = load_reg(s, rn); - gen_bx(s, tmp); - break; + case 4: /* bxj, in decodetree */ + goto illegal_op; case 5: /* Exception return. */ if (IS_USER(s)) { goto illegal_op; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index a8ef435b15..6cb9c16e2f 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -29,6 +29,7 @@ &s_rrrr s rd rn rm ra &rrrr rd rn rm ra &rrr rd rn rm +&r rm &msr_reg rn r mask &mrs_reg rd r &msr_bank rn r sysm @@ -195,8 +196,14 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm %sysm 8:1 16:4 +@rm ---- .... .... .... .... .... .... rm:4 &r + MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %sysm MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %sysm MRS_reg ---- 0001 0 r:1 00 1111 rd:4 0000 0000 0000 &mrs_reg MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg + +BX .... 0001 0010 1111 1111 1111 0001 .... @rm +BXJ .... 0001 0010 1111 1111 1111 0010 .... @rm +BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 261db100ff..337706ebbe 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -26,6 +26,7 @@ &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra &rrr !extern rd rn rm +&r !extern rm &msr_reg !extern rn r mask &mrs_reg !extern rd r &msr_bank !extern rn r sysm @@ -211,4 +212,5 @@ CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 } + BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r } From patchwork Mon Aug 19 21:37:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171683 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3542212ily; Mon, 19 Aug 2019 14:56:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqyqgRq61ufPeU7bcLVadXnyBtRfO5SEw4pNXlyMJzHjpSY4G8ZU00zmjhN3bfgU91cMHPEA X-Received: by 2002:a50:ac1a:: with SMTP id v26mr27610635edc.131.1566251787023; Mon, 19 Aug 2019 14:56:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566251787; cv=none; d=google.com; s=arc-20160816; b=Ep4xsPDKPigBdeVcqx270hpr1wEWpKKP4siSsZyjI3MAl7avxSeFAKUIJyCBSYxGWM S6tKVFsZqbfjGJdx+Cq2iFvxCpYLFMvUPXGl19kn2plL/8hL9NJ3RRHwXM5kaVFh9w1L JOWVLWA95c9ZzrNxCZE5dTr+mfFoU9EyWlR2rs4d0bB9MLmsQTiAl3c8Ob60HFcyTguO 5Idt8SIpmhlJ8fDQbdYT0okG/U9IvJudjrv2dWtgXKjO6YW1tI4tl7kH/Ag1wzKzSH01 aG5CGR3z7w+TSp2fTkuhyyDwZie5ttzdLtDD/DR/OPqasIQELw9uUQivPtczYDut8wSz RI6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=zZYWccT7CCrzOlrmxHsfHjAEIVHw6UJ7WILoC7VO3SU=; b=dYAwpvqyR+1PBo7Js81d775kfH/m7Vrxqx9OTeRuYzX9aXG0XYGf+maVwr/CRsUDKy B5Se6Ib0dxzn2FujJx9P8HZlgrWG//jnscMAJoIVYZu69sqq4m/7pkuWyxxeypH7vp2G BPE7EZoTHVf9cMaBYE0+p2l+IkepR1+6ddlSfCoJO6dmTe2XEVPHbsUbyAq8sOhMnxE2 7zvETAByUvFwD5x0ffE5XECz0V0+JHHA/jd8l8G85vfeT6WMytOv++vr2Z/r1oWhne3Y x+OfPv6b7cYTdw69ycMMZtbPM1r5Tl72gkdVVNd4y44Ewx4M7fKirKmP17qffmouIk09 z+4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PPb1t8l9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:03 -0700 Message-Id: <20190819213755.26175-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 16/68] target/arm: Convert CLZ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Document our choice about the T32 CONSTRAINED UNPREDICTABLE behaviour. This matches the undocumented choice made by the legacy decoder. Signed-off-by: Richard Henderson --- target/arm/translate.c | 31 +++++++++++++++---------------- target/arm/a32.decode | 4 ++++ target/arm/t32.decode | 5 +++++ 3 files changed, 24 insertions(+), 16 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index ef26ed7b57..f0fa5253b6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8461,6 +8461,19 @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a) return true; } +static bool trans_CLZ(DisasContext *s, arg_CLZ *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_5) { + return false; + } + tmp = load_reg(s, a->rm); + tcg_gen_clzi_i32(tmp, tmp, 32); + store_reg(s, a->rd, tmp); + return true; +} + /* * Legacy decoder. */ @@ -8749,18 +8762,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* MSR/MRS (banked/register) */ /* All done in decodetree. Illegal ops already signalled. */ g_assert_not_reached(); - case 0x1: - if (op1 == 3) { - /* clz */ - ARCH(5); - rd = (insn >> 12) & 0xf; - tmp = load_reg(s, rm); - tcg_gen_clzi_i32(tmp, tmp, 32); - store_reg(s, rd, tmp); - } else { - goto illegal_op; - } - break; + case 0x1: /* bx, clz */ case 0x2: /* bxj */ case 0x3: /* blx */ case 0x4: /* crc32 */ @@ -10201,13 +10203,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 0x08: /* rev */ case 0x09: /* rev16 */ case 0x0b: /* revsh */ - case 0x18: /* clz */ break; case 0x10: /* sel */ if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { goto illegal_op; } break; + case 0x18: /* clz, in decodetree */ case 0x20: /* crc32/crc32c, in decodetree */ case 0x21: case 0x22: @@ -10240,9 +10242,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(tmp3); tcg_temp_free_i32(tmp2); break; - case 0x18: /* clz */ - tcg_gen_clzi_i32(tmp, tmp, 32); - break; default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 6cb9c16e2f..182f2b6725 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -29,6 +29,7 @@ &s_rrrr s rd rn rm ra &rrrr rd rn rm ra &rrr rd rn rm +&rr rd rm &r rm &msr_reg rn r mask &mrs_reg rd r @@ -197,6 +198,7 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm %sysm 8:1 16:4 @rm ---- .... .... .... .... .... .... rm:4 &r +@rdm ---- .... .... .... rd:4 .... .... rm:4 &rr MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %sysm MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %sysm @@ -207,3 +209,5 @@ MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg BX .... 0001 0010 1111 1111 1111 0001 .... @rm BXJ .... 0001 0010 1111 1111 1111 0010 .... @rm BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm + +CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 337706ebbe..67724efe4b 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -26,6 +26,7 @@ &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra &rrr !extern rd rn rm +&rr !extern rd rm &r !extern rm &msr_reg !extern rn r mask &mrs_reg !extern rd r @@ -126,6 +127,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr @rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &rrrr ra=0 @rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr +@rdm .... .... .... .... .... rd:4 .... rm:4 &rr { MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm @@ -180,6 +182,9 @@ CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm +# Note rn != rm is CONSTRAINED UNPREDICTABLE; we choose to ignore rn. +CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm + # Branches and miscellaneous control %msr_sysm 4:1 8:4 From patchwork Mon Aug 19 21:37:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171687 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3544721ily; Mon, 19 Aug 2019 15:00:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqxfuRmBT4GWKC47IJdKrBorMeEbZjWxGgDbtSLHca73/hcXodqPxnfIblCsXSLLs9W58VQQ X-Received: by 2002:a0c:f150:: with SMTP id y16mr12117755qvl.220.1566252013228; Mon, 19 Aug 2019 15:00:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566252013; cv=none; d=google.com; s=arc-20160816; b=yfpz8HrAO71bby6sIXmmzhUnlvyua4j53FDvugcGat3vlewjlh+zjJ78uftHqoC5fK dmfwVwCEmvOIwgF2B3wPWOQDhbv9PIdy6KHXxURjGMKX2Sz/R2qoB7C0M44GSx9rr/cP TSqznfIC5eutI+FUYe9k26G0jvS7IzWbBBlJ5pfdAlpgl5TAjuDEE5KCYvf9SB0D9hUm P9pWZqzr0saltQa/hGOqvAQiyeH3nkdJG6zrSwT7nr++oLyc0YmxDf/Z2u9VJBQUEysp scRMRKz6hdUeLqQfvtH7/BIjNt2JnBKa3heXFVKeRSkL+gU6rtU3Bh4Y6sLpu/tXRekD 753g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=e+H++wAKyA1U/1YuB/2iGYEbH8KDD+Sy3cPPJBo/ztc=; b=Tq8rZk4xvXWQHR+pWLv1LcclOi+qRu/uf4xHItMy/vQqJr7PnGTZEggTenbGo92d+M 2iz2ApPpQ8v83cY6X9QSTtJV3aIWyYMIQdpJQrfbkIkCQqraMWz5u/6+twkfP45xRGA7 MWdDkzvmvBIxmKmhLvY7WA+9owEJclFJ64d2U3/DFP+S1C0yMK5k1lsHfQY7jKPCXdXp 0FYu+b3LNzl0zwPNEKd0+6dRUoVMIcytJSN+fj9Al+VDkRQw/5dyad2H+Y9QtjaoDkcM zIlhEPXosRONUgR41kuIIOFzEO9ZrfHETN4qgBge/IGqY5rP6pIPYr7wFgC8EnEnkvCa vSKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BPkzu9Vf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:04 -0700 Message-Id: <20190819213755.26175-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 17/68] target/arm: Convert ERET X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Pass the T5 encoding of SUBS PC, LR, #IMM through the normal SUBS path to make it clear exactly what's happening -- we hit ALUExceptionReturn along that path. Signed-off-by: Richard Henderson --- target/arm/translate.c | 58 ++++++++++++++---------------------------- target/arm/a32.decode | 2 ++ target/arm/t32.decode | 8 ++++++ 3 files changed, 29 insertions(+), 39 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index f0fa5253b6..cb7b35489f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8474,6 +8474,23 @@ static bool trans_CLZ(DisasContext *s, arg_CLZ *a) return true; } +static bool trans_ERET(DisasContext *s, arg_ERET *a) +{ + TCGv_i32 tmp; + + if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_V7VE)) { + return false; + } + if (s->current_el == 2) { + /* ERET from Hyp uses ELR_Hyp, not LR */ + tmp = load_cpu_field(elr_el[2]); + } else { + tmp = load_reg(s, 14); + } + gen_exception_return(s, tmp); + return true; +} + /* * Legacy decoder. */ @@ -8768,29 +8785,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) case 0x4: /* crc32 */ /* All done in decodetree. Illegal ops reach here. */ goto illegal_op; - case 0x5: - /* Saturating addition and subtraction. */ + case 0x5: /* Saturating addition and subtraction. */ + case 0x6: /* ERET */ /* All done in decodetree. Reach here for illegal ops. */ goto illegal_op; - case 0x6: /* ERET */ - if (op1 != 3) { - goto illegal_op; - } - if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) { - goto illegal_op; - } - if ((insn & 0x000fff0f) != 0x0000000e) { - /* UNPREDICTABLE; we choose to UNDEF */ - goto illegal_op; - } - - if (s->current_el == 2) { - tmp = load_cpu_field(elr_el[2]); - } else { - tmp = load_reg(s, 14); - } - gen_exception_return(s, tmp); - break; case 7: { int imm16 = extract32(insn, 0, 4) | (extract32(insn, 8, 12) << 4); @@ -10586,24 +10584,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 4: /* bxj, in decodetree */ goto illegal_op; case 5: /* Exception return. */ - if (IS_USER(s)) { - goto illegal_op; - } - if (rn != 14 || rd != 15) { - goto illegal_op; - } - if (s->current_el == 2) { - /* ERET from Hyp uses ELR_Hyp, not LR */ - if (insn & 0xff) { - goto illegal_op; - } - tmp = load_cpu_field(elr_el[2]); - } else { - tmp = load_reg(s, rn); - tcg_gen_subi_i32(tmp, tmp, insn & 0xff); - } - gen_exception_return(s, tmp); - break; case 6: /* MRS, in decodetree */ case 7: /* MSR, in decodetree */ goto illegal_op; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 182f2b6725..52a66dd1d5 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -211,3 +211,5 @@ BXJ .... 0001 0010 1111 1111 1111 0010 .... @rm BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm + +ERET ---- 0001 0110 0000 0000 0000 0110 1110 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 67724efe4b..6236d28b99 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -218,4 +218,12 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 } BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r + { + # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as for + # every other encoding of SUBS. With v7VE, IMM=0 is redefined as ERET. + # The distinction between the two only matters for Hyp mode. + ERET 1111 0011 1101 1110 1000 1111 0000 0000 + SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ + &s_rri_rot rot=0 s=1 rd=15 rn=14 + } } From patchwork Mon Aug 19 21:37:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171676 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3539212ily; Mon, 19 Aug 2019 14:51:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqw42Y8sTZXx5KRflPCAw/WcQ8BneCg9IGfZQVnQ/M68uwWSIQrm2qa85ui0qvgY2RhooiJ5 X-Received: by 2002:a50:ce5a:: with SMTP id k26mr27653134edj.218.1566251511189; Mon, 19 Aug 2019 14:51:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566251511; cv=none; d=google.com; s=arc-20160816; b=0+3auU45Iu+Ltpw8ArjJ0ac3mDs4lTP5hyGKWU4cTJ8xaIp+zOkJt5nwoSo+oatpFD 3RKcTw4MfQCrws+WpllJ3u4MqJEm1VSDv32xJqbMEjXdaaeeSnp/ypBm8CpbyCh54bkC R37T/rTghaX94tb+gePszX/NkXM6Qb0hWM6C3rk42jMDhb8ogA4CWy1qUIRcYgAu8r0d kWXGU7KNuxdDMVG8qPVtn8wdjYhR1uOxjRXcQerLGmH89Jz0irpP9grElUZnIB1ZkFU9 FXbV/DgoAgrcqN5xmNI3OMM5PumI76db8/QSbneM1H6WCgAxy9f3NI1u+cFAxtcPjQFn v27g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=meGInlCcNAs08b5g91xBiKJHgrSzZAc6MsZg23QrFBY=; b=qMPugCzN+WEbxQpV72VnnubZSDgjNtBz9wUlEQNh4zCuOScrlpGtiawC5VkvbYtKqd ednx4utj1zC8qxDOQcFEZrifIU4PCS6YTwnOS1JteYnxcdyxnHl6f0f3U9ObzlE2qA12 rfxJ4HoZ5P/rrNVeiMaQsQ234wyIoEZNy8C+LR+pFFzO9FdTOFPfdMUL+Pe7pRYpuG52 EUC2S7JQ3ScdIZs0zR1bCcGfyoD6RdxctEdGp8mJyGNGde6XCyFIhegRYpNZMer7K5fY ZRgzx5hixOc1e7OqXDb5P2gRb5XhM2KRjRl7yhtbz9MqvS2uxxzVPrSemSXcM/uJQiUa VJzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cGOujrt0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:05 -0700 Message-Id: <20190819213755.26175-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 18/68] target/arm: Convert the rest of A32 Miscelaneous instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This fixes an exiting bug with the T5 encoding of SUBS PC, LR, #IMM, in that it may be executed from user mode as with any other encoding of SUBS, not as ERET. Signed-off-by: Richard Henderson --- target/arm/translate.c | 119 +++++++++++++---------------------------- target/arm/a32.decode | 8 +++ target/arm/t32.decode | 5 ++ 3 files changed, 50 insertions(+), 82 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index cb7b35489f..cb6296dc12 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8491,6 +8491,39 @@ static bool trans_ERET(DisasContext *s, arg_ERET *a) return true; } +static bool trans_HLT(DisasContext *s, arg_HLT *a) +{ + gen_hlt(s, a->imm); + return true; +} + +static bool trans_BKPT(DisasContext *s, arg_BKPT *a) +{ + if (!ENABLE_ARCH_5) { + return false; + } + gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); + return true; +} + +static bool trans_HVC(DisasContext *s, arg_HVC *a) +{ + if (!ENABLE_ARCH_7 || IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_hvc(s, a->imm); + return true; +} + +static bool trans_SMC(DisasContext *s, arg_SMC *a) +{ + if (!ENABLE_ARCH_6K || IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_smc(s); + return true; +} + /* * Legacy decoder. */ @@ -8771,68 +8804,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } else if ((insn & 0x0f900000) == 0x01000000 && (insn & 0x00000090) != 0x00000090) { /* miscellaneous instructions */ - op1 = (insn >> 21) & 3; - sh = (insn >> 4) & 0xf; - rm = insn & 0xf; - switch (sh) { - case 0x0: - /* MSR/MRS (banked/register) */ - /* All done in decodetree. Illegal ops already signalled. */ - g_assert_not_reached(); - case 0x1: /* bx, clz */ - case 0x2: /* bxj */ - case 0x3: /* blx */ - case 0x4: /* crc32 */ - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - case 0x5: /* Saturating addition and subtraction. */ - case 0x6: /* ERET */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - case 7: - { - int imm16 = extract32(insn, 0, 4) | (extract32(insn, 8, 12) << 4); - switch (op1) { - case 0: - /* HLT */ - gen_hlt(s, imm16); - break; - case 1: - /* bkpt */ - ARCH(5); - gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm16, false)); - break; - case 2: - /* Hypervisor call (v7) */ - ARCH(7); - if (IS_USER(s)) { - goto illegal_op; - } - gen_hvc(s, imm16); - break; - case 3: - /* Secure monitor call (v6+) */ - ARCH(6K); - if (IS_USER(s)) { - goto illegal_op; - } - gen_smc(s); - break; - default: - g_assert_not_reached(); - } - break; - } - case 0x8: - case 0xa: - case 0xc: - case 0xe: - /* Halfword multiply and multiply accumulate. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - default: - goto illegal_op; - } + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; } else if (((insn & 0x0e000000) == 0 && (insn & 0x00000090) != 0x90) || ((insn & 0x0e000000) == (1 << 25))) { @@ -10493,26 +10466,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; if (insn & (1 << 26)) { - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - if (!(insn & (1 << 20))) { - /* Hypervisor call (v7) */ - int imm16 = extract32(insn, 16, 4) << 12 - | extract32(insn, 0, 12); - ARCH(7); - if (IS_USER(s)) { - goto illegal_op; - } - gen_hvc(s, imm16); - } else { - /* Secure monitor call (v6+) */ - ARCH(6K); - if (IS_USER(s)) { - goto illegal_op; - } - gen_smc(s); - } + /* hvc, smc, in decodetree */ + goto illegal_op; } else { op = (insn >> 20) & 7; switch (op) { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 52a66dd1d5..c7f156be6d 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -31,6 +31,7 @@ &rrr rd rn rm &rr rd rm &r rm +&i imm &msr_reg rn r mask &mrs_reg rd r &msr_bank rn r sysm @@ -196,9 +197,11 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm # Miscellaneous instructions %sysm 8:1 16:4 +%imm16_8_0 8:12 0:4 @rm ---- .... .... .... .... .... .... rm:4 &r @rdm ---- .... .... .... rd:4 .... .... rm:4 &rr +@i16 ---- .... .... .... .... .... .... .... &i imm=%imm16_8_0 MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %sysm MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %sysm @@ -213,3 +216,8 @@ BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm ERET ---- 0001 0110 0000 0000 0000 0110 1110 + +HLT .... 0001 0000 .... .... .... 0111 .... @i16 +BKPT .... 0001 0010 .... .... .... 0111 .... @i16 +HVC .... 0001 0100 .... .... .... 0111 .... @i16 +SMC ---- 0001 0110 0000 0000 0000 0111 imm:4 &i diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 6236d28b99..5116c6165a 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -28,6 +28,7 @@ &rrr !extern rd rn rm &rr !extern rd rm &r !extern rm +&i !extern imm &msr_reg !extern rn r mask &mrs_reg !extern rd r &msr_bank !extern rn r sysm @@ -189,6 +190,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm %msr_sysm 4:1 8:4 %mrs_sysm 4:1 16:4 +%imm16_16_0 16:4 0:12 { { @@ -226,4 +228,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ &s_rri_rot rot=0 s=1 rd=15 rn=14 } + SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i + HVC 1111 0111 1110 .... 1000 .... .... .... \ + &i imm=%imm16_16_0 } From patchwork Mon Aug 19 21:37:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171690 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3548325ily; Mon, 19 Aug 2019 15:03:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqxEJENKj/yy1dwWgo0ZglexLkcCZhPWUs4LSphLuMSOc8hmvKUidO0XzfsUuH23Tph+LDzs X-Received: by 2002:aed:3b30:: with SMTP id p45mr22552545qte.84.1566252207523; Mon, 19 Aug 2019 15:03:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566252207; cv=none; d=google.com; s=arc-20160816; b=Mp1/buJ/PzUDk6ZUc3PQjfNPWYyOoNxhfym/wHFBv8gz24xRXNkt3nYBGaV3M0I6YD djNtTXU/88cWce+QrIZAS7rYfUEiHFJ9y/cr4UBO7IUsfMRiTK3p/ggkgB454/27/EC+ bPdIzfCpegEjNNy0895ur7FLwYBzKOsFdpWep3en/qiZODoSJoXa+93PUPVpcQWwzdR9 uYEFcDpjJaD/xJX1OZA/XicSvf4+Ol/QGKyVOx5BO1SULXE+T57Qydxr5G61EdtnuU2x 9xWkzKRKgjNZwY7A//VLqhc8pNs+34evVi5F3vQLpCrnQJ+LZEgy2EjrzmfGv6/0N5TZ OPWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=lmni/76O+knM0gbFh8KJGT9HS18kVAz/Vke5rjDhrnk=; b=X3tG+iHN3PT/KH1PfMslEGSAhC6i4BAeyILlk83rehi4/J87nT2PL09128/Yd2HzZ8 XT2+4sMos9gY3x86KfeDPgf1/D+JN8HghZMJ1jbgYnfB8oOcaxyrI1JGClB77LQIycUG Ray43eKo5GNeS4Q2v6uTpYb28AbmIOdedxCa8iMlXEfprb3JBYwYnTAfW4KeyC+Nlr+r 7uf4O/zlCB1/cN6/lPduDGXjbjIT8Qb0D5lCWKLc8UU5BJH99bsBECffK3Vwe7jy2q4Y aCYx5ytKGCBBPGMIYcuI4kXeING7um972FOH0kFR3Ihjsf8KOyAPVeHlloYGXjDBEvRm Wg/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hCX45omn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 19/68] target/arm: Convert T32 ADDW/SUBW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 24 +++++++++++++----------- target/arm/a32.decode | 1 + target/arm/t32.decode | 19 +++++++++++++++++++ 3 files changed, 33 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index cb6296dc12..0e51289928 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7626,6 +7626,11 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond) * Constant expanders for the decoders. */ +static int negate(DisasContext *s, int x) +{ + return -x; +} + static int times_2(DisasContext *s, int x) { return x * 2; @@ -7975,6 +7980,12 @@ static bool trans_ORN_rri(DisasContext *s, arg_s_rri_rot *a) #undef DO_ANY2 #undef DO_CMP2 +static bool trans_ADR(DisasContext *s, arg_ri *a) +{ + store_reg_bx(s, a->rd, add_reg_for_lit(s, 15, a->imm)); + return true; +} + /* * Multiply and multiply accumulate */ @@ -10670,17 +10681,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } store_reg(s, rd, tmp); } else { - /* Add/sub 12-bit immediate. */ - if (insn & (1 << 23)) { - imm = -imm; - } - tmp = add_reg_for_lit(s, rn, imm); - if (rn == 13 && rd == 13) { - /* ADD SP, SP, imm or SUB SP, SP, imm */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } + /* Add/sub 12-bit immediate, in decodetree */ + goto illegal_op; } } } else { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index c7f156be6d..aac991664d 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -30,6 +30,7 @@ &rrrr rd rn rm ra &rrr rd rn rm &rr rd rm +&ri rd imm &r rm &i imm &msr_reg rn r mask diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 5116c6165a..be4e5f087c 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -27,6 +27,7 @@ &rrrr !extern rd rn rm ra &rrr !extern rd rn rm &rr !extern rd rm +&ri !extern rd imm &r !extern rm &i !extern imm &msr_reg !extern rn r mask @@ -121,6 +122,24 @@ SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot } RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot +# Data processing (plain binary immediate) + +%imm12_26_12_0 26:1 12:3 0:8 +%neg12_26_12_0 26:1 12:3 0:8 !function=negate +@s0_rri_12 .... ... .... . rn:4 . ... rd:4 ........ \ + &s_rri_rot imm=%imm12_26_12_0 rot=0 s=0 + +{ + ADR 1111 0.1 0000 0 1111 0 ... rd:4 ........ \ + &ri imm=%imm12_26_12_0 + ADD_rri 1111 0.1 0000 0 .... 0 ... .... ........ @s0_rri_12 +} +{ + ADR 1111 0.1 0101 0 1111 0 ... rd:4 ........ \ + &ri imm=%neg12_26_12_0 + SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12 +} + # Multiply and multiply accumulate @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0 From patchwork Mon Aug 19 21:37:07 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:07 -0700 Message-Id: <20190819213755.26175-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 20/68] target/arm: Convert load/store (register, immediate, literal) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 797 ++++++++++++++++++----------------------- target/arm/a32.decode | 120 +++++++ target/arm/t32.decode | 141 ++++++++ 3 files changed, 615 insertions(+), 443 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 0e51289928..f7c4db872c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1246,62 +1246,6 @@ static inline void gen_hlt(DisasContext *s, int imm) unallocated_encoding(s); } -static inline void gen_add_data_offset(DisasContext *s, unsigned int insn, - TCGv_i32 var) -{ - int val, rm, shift, shiftop; - TCGv_i32 offset; - - if (!(insn & (1 << 25))) { - /* immediate */ - val = insn & 0xfff; - if (!(insn & (1 << 23))) - val = -val; - if (val != 0) - tcg_gen_addi_i32(var, var, val); - } else { - /* shift/register */ - rm = (insn) & 0xf; - shift = (insn >> 7) & 0x1f; - shiftop = (insn >> 5) & 3; - offset = load_reg(s, rm); - gen_arm_shift_im(offset, shiftop, shift, 0); - if (!(insn & (1 << 23))) - tcg_gen_sub_i32(var, var, offset); - else - tcg_gen_add_i32(var, var, offset); - tcg_temp_free_i32(offset); - } -} - -static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn, - int extra, TCGv_i32 var) -{ - int val, rm; - TCGv_i32 offset; - - if (insn & (1 << 22)) { - /* immediate */ - val = (insn & 0xf) | ((insn >> 4) & 0xf0); - if (!(insn & (1 << 23))) - val = -val; - val += extra; - if (val != 0) - tcg_gen_addi_i32(var, var, val); - } else { - /* register */ - if (extra) - tcg_gen_addi_i32(var, var, extra); - rm = (insn) & 0xf; - offset = load_reg(s, rm); - if (!(insn & (1 << 23))) - tcg_gen_sub_i32(var, var, offset); - else - tcg_gen_add_i32(var, var, offset); - tcg_temp_free_i32(offset); - } -} - static TCGv_ptr get_fpstatus_ptr(int neon) { TCGv_ptr statusptr = tcg_temp_new_ptr(); @@ -7636,6 +7580,11 @@ static int times_2(DisasContext *s, int x) return x * 2; } +static int times_4(DisasContext *s, int x) +{ + return x * 4; +} + /* Return only the rotation part of T32ExpandImm. */ static int t32_expandimm_rot(DisasContext *s, int x) { @@ -8535,6 +8484,345 @@ static bool trans_SMC(DisasContext *s, arg_SMC *a) return true; } +/* + * Load/store register index + */ + +static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w) +{ + ISSInfo ret; + + /* ISS not valid if writeback */ + if (p && !w) { + ret = rd; + } else { + ret = ISSInvalid; + } + return ret; +} + +static TCGv_i32 op_addr_rr_pre(DisasContext *s, arg_ldst_rr *a) +{ + TCGv_i32 addr = load_reg(s, a->rn); + + if (s->v8m_stackcheck && a->rn == 13 && a->w) { + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + if (a->p) { + TCGv_i32 ofs = load_reg(s, a->rm); + gen_arm_shift_im(ofs, a->shtype, a->shimm, 0); + if (a->u) { + tcg_gen_add_i32(addr, addr, ofs); + } else { + tcg_gen_sub_i32(addr, addr, ofs); + } + tcg_temp_free_i32(ofs); + } + return addr; +} + +static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a, + TCGv_i32 addr, int address_offset) +{ + if (!a->p) { + TCGv_i32 ofs = load_reg(s, a->rm); + gen_arm_shift_im(ofs, a->shtype, a->shimm, 0); + if (a->u) { + tcg_gen_add_i32(addr, addr, ofs); + } else { + tcg_gen_sub_i32(addr, addr, ofs); + } + tcg_temp_free_i32(ofs); + } else if (!a->w) { + tcg_temp_free_i32(addr); + return; + } + tcg_gen_addi_i32(addr, addr, address_offset); + store_reg(s, a->rn, addr); +} + +static bool op_load_rr(DisasContext *s, arg_ldst_rr *a, + TCGMemOp mop, int mem_idx) +{ + ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w); + TCGv_i32 addr, tmp; + + addr = op_addr_rr_pre(s, a); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + + /* + * Perform base writeback before the loaded value to + * ensure correct behavior with overlapping index registers. + */ + op_addr_rr_post(s, a, addr, 0); + store_reg_from_load(s, a->rt, tmp); + return true; +} + +static bool op_store_rr(DisasContext *s, arg_ldst_rr *a, + TCGMemOp mop, int mem_idx) +{ + ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite; + TCGv_i32 addr, tmp; + + addr = op_addr_rr_pre(s, a); + + tmp = load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + tcg_temp_free_i32(tmp); + + op_addr_rr_post(s, a, addr, 0); + return true; +} + +static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) +{ + int mem_idx = get_mem_index(s); + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_5TE || (a->rt & 1)) { + return false; + } + addr = op_addr_rr_pre(s, a); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, a->rt, tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, a->rt + 1, tmp); + + /* LDRD w/ base writeback is undefined if the registers overlap. */ + op_addr_rr_post(s, a, addr, -4); + return true; +} + +static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a) +{ + int mem_idx = get_mem_index(s); + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_5TE || (a->rt & 1)) { + return false; + } + addr = op_addr_rr_pre(s, a); + + tmp = load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp = load_reg(s, a->rt + 1); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + op_addr_rr_post(s, a, addr, -4); + return true; +} + +/* + * Load/store immediate index + */ + +static TCGv_i32 op_addr_ri_pre(DisasContext *s, arg_ldst_ri *a) +{ + int ofs = a->imm; + + if (!a->u) { + ofs = -ofs; + } + + if (s->v8m_stackcheck && a->rn == 13 && a->w) { + /* + * Stackcheck. Here we know 'addr' is the current SP; + * U is set if we're moving SP up, else down. It is + * UNKNOWN whether the limit check triggers when SP starts + * below the limit and ends up above it; we chose to do so. + */ + if (!a->u) { + TCGv_i32 newsp = tcg_temp_new_i32(); + tcg_gen_addi_i32(newsp, cpu_R[13], ofs); + gen_helper_v8m_stackcheck(cpu_env, newsp); + tcg_temp_free_i32(newsp); + } else { + gen_helper_v8m_stackcheck(cpu_env, cpu_R[13]); + } + } + + return add_reg_for_lit(s, a->rn, a->p ? ofs : 0); +} + +static void op_addr_ri_post(DisasContext *s, arg_ldst_ri *a, + TCGv_i32 addr, int address_offset) +{ + if (!a->p) { + if (a->u) { + address_offset += a->imm; + } else { + address_offset -= a->imm; + } + } else if (!a->w) { + tcg_temp_free_i32(addr); + return; + } + tcg_gen_addi_i32(addr, addr, address_offset); + store_reg(s, a->rn, addr); +} + +static bool op_load_ri(DisasContext *s, arg_ldst_ri *a, + TCGMemOp mop, int mem_idx) +{ + ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w); + TCGv_i32 addr, tmp; + + addr = op_addr_ri_pre(s, a); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + + /* + * Perform base writeback before the loaded value to + * ensure correct behavior with overlapping index registers. + */ + op_addr_ri_post(s, a, addr, 0); + store_reg_from_load(s, a->rt, tmp); + return true; +} + +static bool op_store_ri(DisasContext *s, arg_ldst_ri *a, + TCGMemOp mop, int mem_idx) +{ + ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite; + TCGv_i32 addr, tmp; + + addr = op_addr_ri_pre(s, a); + + tmp = load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + tcg_temp_free_i32(tmp); + + op_addr_ri_post(s, a, addr, 0); + return true; +} + +static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) +{ + int mem_idx = get_mem_index(s); + TCGv_i32 addr, tmp; + + addr = op_addr_ri_pre(s, a); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, a->rt, tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, rt2, tmp); + + /* LDRD w/ base writeback is undefined if the registers overlap. */ + op_addr_ri_post(s, a, addr, -4); + return true; +} + +static bool trans_LDRD_ri_a32(DisasContext *s, arg_ldst_ri *a) +{ + if (!ENABLE_ARCH_5TE || (a->rt & 1)) { + return false; + } + return op_ldrd_ri(s, a, a->rt + 1); +} + +static bool trans_LDRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a) +{ + arg_ldst_ri b = { + .u = a->u, .w = a->w, .p = a->p, + .rn = a->rn, .rt = a->rt, .imm = a->imm + }; + return op_ldrd_ri(s, &b, a->rt2); +} + +static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) +{ + int mem_idx = get_mem_index(s); + TCGv_i32 addr, tmp; + + addr = op_addr_ri_pre(s, a); + + tmp = load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp = load_reg(s, rt2); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + op_addr_ri_post(s, a, addr, -4); + return true; +} + +static bool trans_STRD_ri_a32(DisasContext *s, arg_ldst_ri *a) +{ + if (!ENABLE_ARCH_5TE || (a->rt & 1)) { + return false; + } + return op_strd_ri(s, a, a->rt + 1); +} + +static bool trans_STRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a) +{ + arg_ldst_ri b = { + .u = a->u, .w = a->w, .p = a->p, + .rn = a->rn, .rt = a->rt, .imm = a->imm + }; + return op_strd_ri(s, &b, a->rt2); +} + +#define DO_LDST(NAME, WHICH, MEMOP) \ +static bool trans_##NAME##_ri(DisasContext *s, arg_ldst_ri *a) \ +{ \ + return op_##WHICH##_ri(s, a, MEMOP, get_mem_index(s)); \ +} \ +static bool trans_##NAME##T_ri(DisasContext *s, arg_ldst_ri *a) \ +{ \ + return op_##WHICH##_ri(s, a, MEMOP, get_a32_user_mem_index(s)); \ +} \ +static bool trans_##NAME##_rr(DisasContext *s, arg_ldst_rr *a) \ +{ \ + return op_##WHICH##_rr(s, a, MEMOP, get_mem_index(s)); \ +} \ +static bool trans_##NAME##T_rr(DisasContext *s, arg_ldst_rr *a) \ +{ \ + return op_##WHICH##_rr(s, a, MEMOP, get_a32_user_mem_index(s)); \ +} + +DO_LDST(LDR, load, MO_UL) +DO_LDST(LDRB, load, MO_UB) +DO_LDST(LDRH, load, MO_UW) +DO_LDST(LDRSB, load, MO_SB) +DO_LDST(LDRSH, load, MO_SW) + +DO_LDST(STR, store, MO_UL) +DO_LDST(STRB, store, MO_UB) +DO_LDST(STRH, store, MO_UW) + +#undef DO_LDST + /* * Legacy decoder. */ @@ -8992,100 +9280,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } } } else { - int address_offset; - bool load = insn & (1 << 20); - bool wbit = insn & (1 << 21); - bool pbit = insn & (1 << 24); - bool doubleword = false; - ISSInfo issinfo; - - /* Misc load/store */ - rn = (insn >> 16) & 0xf; - rd = (insn >> 12) & 0xf; - - /* ISS not valid if writeback */ - issinfo = (pbit & !wbit) ? rd : ISSInvalid; - - if (!load && (sh & 2)) { - /* doubleword */ - ARCH(5TE); - if (rd & 1) { - /* UNPREDICTABLE; we choose to UNDEF */ - goto illegal_op; - } - load = (sh & 1) == 0; - doubleword = true; - } - - addr = load_reg(s, rn); - if (pbit) { - gen_add_datah_offset(s, insn, 0, addr); - } - address_offset = 0; - - if (doubleword) { - if (!load) { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp = load_reg(s, rd + 1); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } else { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - rd++; - } - address_offset = -4; - } else if (load) { - /* load */ - tmp = tcg_temp_new_i32(); - switch (sh) { - case 1: - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), - issinfo); - break; - case 2: - gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), - issinfo); - break; - default: - case 3: - gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), - issinfo); - break; - } - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), issinfo); - tcg_temp_free_i32(tmp); - } - /* Perform base writeback before the loaded value to - ensure correct behavior with overlapping index registers. - ldrd with base writeback is undefined if the - destination and index registers overlap. */ - if (!pbit) { - gen_add_datah_offset(s, insn, address_offset, addr); - store_reg(s, rn, addr); - } else if (wbit) { - if (address_offset) - tcg_gen_addi_i32(addr, addr, address_offset); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - if (load) { - /* Complete the load. */ - store_reg(s, rd, tmp); - } + /* Extra load/store (register) instructions */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } break; case 0x4: @@ -9393,58 +9590,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) break; } do_ldst: - /* Check for undefined extension instructions - * per the ARM Bible IE: - * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx - */ - sh = (0xf << 20) | (0xf << 4); - if (op1 == 0x7 && ((insn & sh) == sh)) - { - goto illegal_op; - } - /* load/store byte/word */ - rn = (insn >> 16) & 0xf; - rd = (insn >> 12) & 0xf; - tmp2 = load_reg(s, rn); - if ((insn & 0x01200000) == 0x00200000) { - /* ldrt/strt */ - i = get_a32_user_mem_index(s); - } else { - i = get_mem_index(s); - } - if (insn & (1 << 24)) - gen_add_data_offset(s, insn, tmp2); - if (insn & (1 << 20)) { - /* load */ - tmp = tcg_temp_new_i32(); - if (insn & (1 << 22)) { - gen_aa32_ld8u_iss(s, tmp, tmp2, i, rd); - } else { - gen_aa32_ld32u_iss(s, tmp, tmp2, i, rd); - } - } else { - /* store */ - tmp = load_reg(s, rd); - if (insn & (1 << 22)) { - gen_aa32_st8_iss(s, tmp, tmp2, i, rd); - } else { - gen_aa32_st32_iss(s, tmp, tmp2, i, rd); - } - tcg_temp_free_i32(tmp); - } - if (!(insn & (1 << 24))) { - gen_add_data_offset(s, insn, tmp2); - store_reg(s, rn, tmp2); - } else if (insn & (1 << 21)) { - store_reg(s, rn, tmp2); - } else { - tcg_temp_free_i32(tmp2); - } - if (insn & (1 << 20)) { - /* Complete the load. */ - store_reg_from_load(s, rd, tmp); - } - break; + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0x08: case 0x09: { @@ -9748,75 +9895,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) s->condexec_mask = 0; } } else if (insn & 0x01200000) { - /* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store dual (post-indexed) - * 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store dual (literal and immediate) - * 0b1111_1001_x11x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store dual (pre-indexed) - */ - bool wback = extract32(insn, 21, 1); - - if (rn == 15 && (insn & (1 << 21))) { - /* UNPREDICTABLE */ - goto illegal_op; - } - - addr = add_reg_for_lit(s, rn, 0); - offset = (insn & 0xff) * 4; - if ((insn & (1 << 23)) == 0) { - offset = -offset; - } - - if (s->v8m_stackcheck && rn == 13 && wback) { - /* - * Here 'addr' is the current SP; if offset is +ve we're - * moving SP up, else down. It is UNKNOWN whether the limit - * check triggers when SP starts below the limit and ends - * up above it; check whichever of the current and final - * SP is lower, so QEMU will trigger in that situation. - */ - if ((int32_t)offset < 0) { - TCGv_i32 newsp = tcg_temp_new_i32(); - - tcg_gen_addi_i32(newsp, addr, offset); - gen_helper_v8m_stackcheck(cpu_env, newsp); - tcg_temp_free_i32(newsp); - } else { - gen_helper_v8m_stackcheck(cpu_env, addr); - } - } - - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, offset); - offset = 0; - } - if (insn & (1 << 20)) { - /* ldrd */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rs, tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - } else { - /* strd */ - tmp = load_reg(s, rs); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp = load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - if (wback) { - /* Base writeback. */ - tcg_gen_addi_i32(addr, addr, offset - 4); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } + /* load/store dual, in decodetree */ + goto illegal_op; } else if ((insn & (1 << 23)) == 0) { /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx * - load/store exclusive word @@ -10692,184 +10772,15 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } } break; - case 12: /* Load/store single data item. */ - { - int postinc = 0; - int writeback = 0; - int memidx; - ISSInfo issinfo; - + case 12: if ((insn & 0x01100000) == 0x01000000) { if (disas_neon_ls_insn(s, insn)) { goto illegal_op; } break; } - op = ((insn >> 21) & 3) | ((insn >> 22) & 4); - if (rs == 15) { - if (!(insn & (1 << 20))) { - goto illegal_op; - } - if (op != 2) { - /* Byte or halfword load space with dest == r15 : memory hints. - * Catch them early so we don't emit pointless addressing code. - * This space is a mix of: - * PLD/PLDW/PLI, which we implement as NOPs (note that unlike - * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP - * cores) - * unallocated hints, which must be treated as NOPs - * UNPREDICTABLE space, which we NOP or UNDEF depending on - * which is easiest for the decoding logic - * Some space which must UNDEF - */ - int op1 = (insn >> 23) & 3; - int op2 = (insn >> 6) & 0x3f; - if (op & 2) { - goto illegal_op; - } - if (rn == 15) { - /* UNPREDICTABLE, unallocated hint or - * PLD/PLDW/PLI (literal) - */ - return; - } - if (op1 & 1) { - return; /* PLD/PLDW/PLI or unallocated hint */ - } - if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) { - return; /* PLD/PLDW/PLI or unallocated hint */ - } - /* UNDEF space, or an UNPREDICTABLE */ - goto illegal_op; - } - } - memidx = get_mem_index(s); - imm = insn & 0xfff; - if (insn & (1 << 23)) { - /* PC relative or Positive offset. */ - addr = add_reg_for_lit(s, rn, imm); - } else if (rn == 15) { - /* PC relative with negative offset. */ - addr = add_reg_for_lit(s, rn, -imm); - } else { - addr = load_reg(s, rn); - imm = insn & 0xff; - switch ((insn >> 8) & 0xf) { - case 0x0: /* Shifted Register. */ - shift = (insn >> 4) & 0xf; - if (shift > 3) { - tcg_temp_free_i32(addr); - goto illegal_op; - } - tmp = load_reg(s, rm); - tcg_gen_shli_i32(tmp, tmp, shift); - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - break; - case 0xc: /* Negative offset. */ - tcg_gen_addi_i32(addr, addr, -imm); - break; - case 0xe: /* User privilege. */ - tcg_gen_addi_i32(addr, addr, imm); - memidx = get_a32_user_mem_index(s); - break; - case 0x9: /* Post-decrement. */ - imm = -imm; - /* Fall through. */ - case 0xb: /* Post-increment. */ - postinc = 1; - writeback = 1; - break; - case 0xd: /* Pre-decrement. */ - imm = -imm; - /* Fall through. */ - case 0xf: /* Pre-increment. */ - writeback = 1; - break; - default: - tcg_temp_free_i32(addr); - goto illegal_op; - } - } - - issinfo = writeback ? ISSInvalid : rs; - - if (s->v8m_stackcheck && rn == 13 && writeback) { - /* - * Stackcheck. Here we know 'addr' is the current SP; - * if imm is +ve we're moving SP up, else down. It is - * UNKNOWN whether the limit check triggers when SP starts - * below the limit and ends up above it; we chose to do so. - */ - if ((int32_t)imm < 0) { - TCGv_i32 newsp = tcg_temp_new_i32(); - - tcg_gen_addi_i32(newsp, addr, imm); - gen_helper_v8m_stackcheck(cpu_env, newsp); - tcg_temp_free_i32(newsp); - } else { - gen_helper_v8m_stackcheck(cpu_env, addr); - } - } - - if (writeback && !postinc) { - tcg_gen_addi_i32(addr, addr, imm); - } - - if (insn & (1 << 20)) { - /* Load. */ - tmp = tcg_temp_new_i32(); - switch (op) { - case 0: - gen_aa32_ld8u_iss(s, tmp, addr, memidx, issinfo); - break; - case 4: - gen_aa32_ld8s_iss(s, tmp, addr, memidx, issinfo); - break; - case 1: - gen_aa32_ld16u_iss(s, tmp, addr, memidx, issinfo); - break; - case 5: - gen_aa32_ld16s_iss(s, tmp, addr, memidx, issinfo); - break; - case 2: - gen_aa32_ld32u_iss(s, tmp, addr, memidx, issinfo); - break; - default: - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(addr); - goto illegal_op; - } - store_reg_from_load(s, rs, tmp); - } else { - /* Store. */ - tmp = load_reg(s, rs); - switch (op) { - case 0: - gen_aa32_st8_iss(s, tmp, addr, memidx, issinfo); - break; - case 1: - gen_aa32_st16_iss(s, tmp, addr, memidx, issinfo); - break; - case 2: - gen_aa32_st32_iss(s, tmp, addr, memidx, issinfo); - break; - default: - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(addr); - goto illegal_op; - } - tcg_temp_free_i32(tmp); - } - if (postinc) - tcg_gen_addi_i32(addr, addr, imm); - if (writeback) { - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - } - break; + /* Load/store single data item, in decodetree */ + goto illegal_op; default: goto illegal_op; } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index aac991664d..f7742deaee 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -37,6 +37,8 @@ &mrs_reg rd r &msr_bank rn r sysm &mrs_bank rd r sysm +&ldst_rr p w u rn rt rm shimm shtype +&ldst_ri p w u rn rt imm # Data-processing (register) @@ -222,3 +224,121 @@ HLT .... 0001 0000 .... .... .... 0111 .... @i16 BKPT .... 0001 0010 .... .... .... 0111 .... @i16 HVC .... 0001 0100 .... .... .... 0111 .... @i16 SMC ---- 0001 0110 0000 0000 0000 0111 imm:4 &i + +# Load/Store Dual, Half, Signed Byte (register) + +@ldst_rr_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 .... .... rm:4 \ + &ldst_rr p=1 shimm=0 shtype=0 +@ldst_rr_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 .... .... rm:4 \ + &ldst_rr p=0 w=0 shimm=0 shtype=0 + +STRH_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_pw0 +STRH_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_p1w + +LDRD_rr .... 000. .0.0 .... .... 0000 1101 .... @ldst_rr_pw0 +LDRD_rr .... 000. .0.0 .... .... 0000 1101 .... @ldst_rr_p1w + +STRD_rr .... 000. .0.0 .... .... 0000 1111 .... @ldst_rr_pw0 +STRD_rr .... 000. .0.0 .... .... 0000 1111 .... @ldst_rr_p1w + +LDRH_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_pw0 +LDRH_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_p1w + +LDRSB_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_pw0 +LDRSB_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_p1w + +LDRSH_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_pw0 +LDRSH_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_p1w + +# Note the unpriv load/stores use the previously invalid P=0, W=1 encoding, +# and act as normal post-indexed (P=0, W=0). +@ldst_rr_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 .... .... rm:4 \ + &ldst_rr p=0 w=0 shimm=0 shtype=0 + +STRHT_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_p0w1 +LDRHT_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_p0w1 +LDRSBT_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_p0w1 +LDRSHT_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_p0w1 + +# Load/Store word and unsigned byte (register) + +@ldst_rs_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \ + &ldst_rr p=1 +@ldst_rs_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \ + &ldst_rr p=0 w=0 + +STR_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_pw0 +STR_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_p1w +STRB_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_pw0 +STRB_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_p1w + +LDR_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_pw0 +LDR_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_p1w +LDRB_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_pw0 +LDRB_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_p1w + +@ldst_rs_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \ + &ldst_rr p=0 w=0 + +STRT_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_p0w1 +STRBT_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_p0w1 +LDRT_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_p0w1 +LDRBT_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_p0w1 + +# Load/Store Dual, Half, Signed Byte (immediate) + +%imm8s_8_0 8:4 0:4 +@ldst_ri8_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 .... .... .... \ + &ldst_ri imm=%imm8s_8_0 p=1 +@ldst_ri8_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 .... .... .... \ + &ldst_ri imm=%imm8s_8_0 p=0 w=0 + +STRH_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_pw0 +STRH_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_p1w + +LDRD_ri_a32 .... 000. .1.0 .... .... .... 1101 .... @ldst_ri8_pw0 +LDRD_ri_a32 .... 000. .1.0 .... .... .... 1101 .... @ldst_ri8_p1w + +STRD_ri_a32 .... 000. .1.0 .... .... .... 1111 .... @ldst_ri8_pw0 +STRD_ri_a32 .... 000. .1.0 .... .... .... 1111 .... @ldst_ri8_p1w + +LDRH_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_pw0 +LDRH_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_p1w + +LDRSB_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_pw0 +LDRSB_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_p1w + +LDRSH_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_pw0 +LDRSH_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_p1w + +# Note the unpriv load/stores use the previously invalid P=0, W=1 encoding, +# and act as normal post-indexed (P=0, W=0). +@ldst_ri8_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 .... .... .... \ + &ldst_ri imm=%imm8s_8_0 p=0 w=0 + +STRHT_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_p0w1 +LDRHT_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_p0w1 +LDRSBT_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_p0w1 +LDRSHT_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_p0w1 + +# Load/Store word and unsigned byte (immediate) + +@ldst_ri12_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 imm:12 &ldst_ri p=1 +@ldst_ri12_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 imm:12 &ldst_ri p=0 w=0 + +STR_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p1w +STR_ri .... 010. .0.0 .... .... ............ @ldst_ri12_pw0 +STRB_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p1w +STRB_ri .... 010. .1.0 .... .... ............ @ldst_ri12_pw0 + +LDR_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p1w +LDR_ri .... 010. .0.1 .... .... ............ @ldst_ri12_pw0 +LDRB_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p1w +LDRB_ri .... 010. .1.1 .... .... ............ @ldst_ri12_pw0 + +@ldst_ri12_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 imm:12 &ldst_ri p=0 w=0 + +STRT_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p0w1 +STRBT_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p0w1 +LDRT_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p0w1 +LDRBT_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p0w1 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index be4e5f087c..a86597562b 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -34,6 +34,8 @@ &mrs_reg !extern rd r &msr_bank !extern rn r sysm &mrs_bank !extern rd r sysm +&ldst_rr !extern p w u rn rt rm shimm shtype +&ldst_ri !extern p w u rn rt imm # Data-processing (register) @@ -251,3 +253,142 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=%imm16_16_0 } + +# Load/store (register, immediate, literal) + +@ldst_rr .... .... .... rn:4 rt:4 ...... shimm:2 rm:4 \ + &ldst_rr p=1 w=0 u=1 shtype=0 +@ldst_ri_idx .... .... .... rn:4 rt:4 . p:1 u:1 . imm:8 \ + &ldst_ri w=1 +@ldst_ri_neg .... .... .... rn:4 rt:4 .... imm:8 \ + &ldst_ri p=1 w=0 u=0 +@ldst_ri_unp .... .... .... rn:4 rt:4 .... imm:8 \ + &ldst_ri p=1 w=0 u=1 +@ldst_ri_pos .... .... .... rn:4 rt:4 imm:12 \ + &ldst_ri p=1 w=0 u=1 +@ldst_ri_lit .... .... u:1 ... .... rt:4 imm:12 \ + &ldst_ri p=1 w=0 rn=15 + +STRB_rr 1111 1000 0000 .... .... 000000 .. .... @ldst_rr +STRB_ri 1111 1000 0000 .... .... 1..1 ........ @ldst_ri_idx +STRB_ri 1111 1000 0000 .... .... 1100 ........ @ldst_ri_neg +STRBT_ri 1111 1000 0000 .... .... 1110 ........ @ldst_ri_unp +STRB_ri 1111 1000 1000 .... .... ............ @ldst_ri_pos + +STRH_rr 1111 1000 0010 .... .... 000000 .. .... @ldst_rr +STRH_ri 1111 1000 0010 .... .... 1..1 ........ @ldst_ri_idx +STRH_ri 1111 1000 0010 .... .... 1100 ........ @ldst_ri_neg +STRHT_ri 1111 1000 0010 .... .... 1110 ........ @ldst_ri_unp +STRH_ri 1111 1000 1010 .... .... ............ @ldst_ri_pos + +STR_rr 1111 1000 0100 .... .... 000000 .. .... @ldst_rr +STR_ri 1111 1000 0100 .... .... 1..1 ........ @ldst_ri_idx +STR_ri 1111 1000 0100 .... .... 1100 ........ @ldst_ri_neg +STRT_ri 1111 1000 0100 .... .... 1110 ........ @ldst_ri_unp +STR_ri 1111 1000 1100 .... .... ............ @ldst_ri_pos + +# Note that Load, unsigned (literal) overlaps all other load encodings. +{ + { + NOP 1111 1000 -001 1111 1111 ------------ # PLD + LDRB_ri 1111 1000 .001 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1000 1001 ---- 1111 ------------ # PLD + LDRB_ri 1111 1000 1001 .... .... ............ @ldst_ri_pos + } + LDRB_ri 1111 1000 0001 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1000 0001 ---- 1111 1100 -------- # PLD + LDRB_ri 1111 1000 0001 .... .... 1100 ........ @ldst_ri_neg + } + LDRBT_ri 1111 1000 0001 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1000 0001 ---- 1111 000000 -- ---- # PLD + LDRB_rr 1111 1000 0001 .... .... 000000 .. .... @ldst_rr + } +} +{ + { + NOP 1111 1000 -011 1111 1111 ------------ # PLD + LDRH_ri 1111 1000 .011 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1000 1011 ---- 1111 ------------ # PLDW + LDRH_ri 1111 1000 1011 .... .... ............ @ldst_ri_pos + } + LDRH_ri 1111 1000 0011 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1000 0011 ---- 1111 1100 -------- # PLDW + LDRH_ri 1111 1000 0011 .... .... 1100 ........ @ldst_ri_neg + } + LDRHT_ri 1111 1000 0011 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1000 0011 ---- 1111 000000 -- ---- # PLDW + LDRH_rr 1111 1000 0011 .... .... 000000 .. .... @ldst_rr + } +} +{ + LDR_ri 1111 1000 .101 1111 .... ............ @ldst_ri_lit + LDR_ri 1111 1000 1101 .... .... ............ @ldst_ri_pos + LDR_ri 1111 1000 0101 .... .... 1..1 ........ @ldst_ri_idx + LDR_ri 1111 1000 0101 .... .... 1100 ........ @ldst_ri_neg + LDRT_ri 1111 1000 0101 .... .... 1110 ........ @ldst_ri_unp + LDR_rr 1111 1000 0101 .... .... 000000 .. .... @ldst_rr +} +# NOPs here are PLI. +{ + { + NOP 1111 1001 -001 1111 1111 ------------ + LDRSB_ri 1111 1001 .001 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1001 1001 ---- 1111 ------------ + LDRSB_ri 1111 1001 1001 .... .... ............ @ldst_ri_pos + } + LDRSB_ri 1111 1001 0001 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1001 0001 ---- 1111 1100 -------- + LDRSB_ri 1111 1001 0001 .... .... 1100 ........ @ldst_ri_neg + } + LDRSBT_ri 1111 1001 0001 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1001 0001 ---- 1111 000000 -- ---- + LDRSB_rr 1111 1001 0001 .... .... 000000 .. .... @ldst_rr + } +} +# NOPs here are unallocated memory hints, treated as NOP. +{ + { + NOP 1111 1001 -011 1111 1111 ------------ + LDRSH_ri 1111 1001 .011 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1001 1011 ---- 1111 ------------ + LDRSH_ri 1111 1001 1011 .... .... ............ @ldst_ri_pos + } + LDRSH_ri 1111 1001 0011 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1001 0011 ---- 1111 1100 -------- + LDRSH_ri 1111 1001 0011 .... .... 1100 ........ @ldst_ri_neg + } + LDRSHT_ri 1111 1001 0011 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1001 0011 ---- 1111 000000 -- ---- + LDRSH_rr 1111 1001 0011 .... .... 000000 .. .... @ldst_rr + } +} + +%imm8x4 0:8 !function=times_4 +&ldst_ri2 p w u rn rt rt2 imm +@ldstd_ri8 .... .... u:1 ... rn:4 rt:4 rt2:4 ........ \ + &ldst_ri2 imm=%imm8x4 + +STRD_ri_t32 1110 1000 .110 .... .... .... ........ @ldstd_ri8 w=1 p=0 +LDRD_ri_t32 1110 1000 .111 .... .... .... ........ @ldstd_ri8 w=1 p=0 + +STRD_ri_t32 1110 1001 .100 .... .... .... ........ @ldstd_ri8 w=0 p=1 +LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1 + +STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1 +LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1 From patchwork Mon Aug 19 21:37:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171673 Delivered-To: patch@linaro.org Received: by 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:08 -0700 Message-Id: <20190819213755.26175-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 21/68] target/arm: Convert Synchronization primitives X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 560 ++++++++++++++++++++++------------------- target/arm/a32.decode | 48 ++++ target/arm/t32.decode | 46 ++++ 3 files changed, 396 insertions(+), 258 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index f7c4db872c..3b0998444d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8823,6 +8823,302 @@ DO_LDST(STRH, store, MO_UW) #undef DO_LDST +/* + * Synchronization primitives + */ + +static bool op_swp(DisasContext *s, arg_SWP *a, TCGMemOp opc) +{ + TCGv_i32 addr, tmp; + TCGv taddr; + + opc |= s->be_data; + addr = load_reg(s, a->rn); + taddr = gen_aa32_addr(s, addr, opc); + tcg_temp_free_i32(addr); + + tmp = load_reg(s, a->rt2); + tcg_gen_atomic_xchg_i32(tmp, taddr, tmp, get_mem_index(s), opc); + tcg_temp_free(taddr); + + store_reg(s, a->rt, tmp); + return true; +} + +static bool trans_SWP(DisasContext *s, arg_SWP *a) +{ + return op_swp(s, a, MO_UL | MO_ALIGN); +} + +static bool trans_SWPB(DisasContext *s, arg_SWP *a) +{ + return op_swp(s, a, MO_UB); +} + +/* + * Load/Store Exclusive and Load-Acquire/Store-Release + */ + +static bool op_strex(DisasContext *s, arg_STREX *a, TCGMemOp mop, bool rel) +{ + TCGv_i32 addr; + + if (rel) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + + addr = tcg_temp_local_new_i32(); + load_reg_var(s, addr, a->rn); + tcg_gen_addi_i32(addr, addr, a->imm); + + gen_store_exclusive(s, a->rd, a->rt, a->rt2, addr, mop); + tcg_temp_free_i32(addr); + return true; +} + +static bool trans_STREX(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_strex(s, a, MO_32, false); +} + +static bool trans_STREXD_a32(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_6K || (a->rt & 1)) { + return false; + } + a->rt2 = a->rt + 1; + return op_strex(s, a, MO_64, false); +} + +static bool trans_STREXD_t32(DisasContext *s, arg_STREX *a) +{ + return op_strex(s, a, MO_64, false); +} + +static bool trans_STREXB(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + return op_strex(s, a, MO_8, false); +} + +static bool trans_STREXH(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + return op_strex(s, a, MO_16, false); +} + +static bool trans_STLEX(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_32, true); +} + +static bool trans_STLEXD_a32(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8 || (a->rt & 1)) { + return false; + } + a->rt2 = a->rt + 1; + return op_strex(s, a, MO_64, true); +} + +static bool trans_STLEXD_t32(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_64, true); +} + +static bool trans_STLEXB(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_8, true); +} + +static bool trans_STLEXH(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_16, true); +} + +static bool op_stl(DisasContext *s, arg_STL *a, TCGMemOp mop) +{ + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_8) { + return false; + } + addr = load_reg(s, a->rn); + + tmp = load_reg(s, a->rt); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite); + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(addr); + return true; +} + +static bool trans_STL(DisasContext *s, arg_STL *a) +{ + return op_stl(s, a, MO_UL); +} + +static bool trans_STLB(DisasContext *s, arg_STL *a) +{ + return op_stl(s, a, MO_UB); +} + +static bool trans_STLH(DisasContext *s, arg_STL *a) +{ + return op_stl(s, a, MO_UW); +} + +static bool op_ldrex(DisasContext *s, arg_LDREX *a, TCGMemOp mop, bool acq) +{ + TCGv_i32 addr; + + addr = tcg_temp_local_new_i32(); + load_reg_var(s, addr, a->rn); + tcg_gen_addi_i32(addr, addr, a->imm); + + gen_load_exclusive(s, a->rt, a->rt2, addr, mop); + tcg_temp_free_i32(addr); + + if (acq) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } + return true; +} + +static bool trans_LDREX(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_ldrex(s, a, MO_32, false); +} + +static bool trans_LDREXD_a32(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_6K || (a->rt & 1)) { + return false; + } + a->rt2 = a->rt + 1; + return op_ldrex(s, a, MO_64, false); +} + +static bool trans_LDREXD_t32(DisasContext *s, arg_LDREX *a) +{ + return op_ldrex(s, a, MO_64, false); +} + +static bool trans_LDREXB(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + return op_ldrex(s, a, MO_8, false); +} + +static bool trans_LDREXH(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + return op_ldrex(s, a, MO_16, false); +} + +static bool trans_LDAEX(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_32, true); +} + +static bool trans_LDAEXD_a32(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8 || (a->rt & 1)) { + return false; + } + a->rt2 = a->rt + 1; + return op_ldrex(s, a, MO_64, true); +} + +static bool trans_LDAEXD_t32(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_64, true); +} + +static bool trans_LDAEXB(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_8, true); +} + +static bool trans_LDAEXH(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_16, true); +} + +static bool op_lda(DisasContext *s, arg_LDA *a, TCGMemOp mop) +{ + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_8) { + return false; + } + addr = load_reg(s, a->rn); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel); + tcg_temp_free_i32(addr); + + store_reg(s, a->rt, tmp); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + return true; +} + +static bool trans_LDA(DisasContext *s, arg_LDA *a) +{ + return op_lda(s, a, MO_UL); +} + +static bool trans_LDAB(DisasContext *s, arg_LDA *a) +{ + return op_lda(s, a, MO_UB); +} + +static bool trans_LDAH(DisasContext *s, arg_LDA *a) +{ + return op_lda(s, a, MO_UW); +} + /* * Legacy decoder. */ @@ -9118,172 +9414,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) case 0x0: case 0x1: /* multiplies, extra load/stores */ - sh = (insn >> 5) & 3; - if (sh == 0) { - if (op1 == 0x0) { - /* Multiply and multiply accumulate. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } else { - rn = (insn >> 16) & 0xf; - rd = (insn >> 12) & 0xf; - if (insn & (1 << 23)) { - /* load/store exclusive */ - bool is_ld = extract32(insn, 20, 1); - bool is_lasr = !extract32(insn, 8, 1); - int op2 = (insn >> 8) & 3; - op1 = (insn >> 21) & 0x3; - - switch (op2) { - case 0: /* lda/stl */ - if (op1 == 1) { - goto illegal_op; - } - ARCH(8); - break; - case 1: /* reserved */ - goto illegal_op; - case 2: /* ldaex/stlex */ - ARCH(8); - break; - case 3: /* ldrex/strex */ - if (op1) { - ARCH(6K); - } else { - ARCH(6); - } - break; - } - - addr = tcg_temp_local_new_i32(); - load_reg_var(s, addr, rn); - - if (is_lasr && !is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - - if (op2 == 0) { - if (is_ld) { - tmp = tcg_temp_new_i32(); - switch (op1) { - case 0: /* lda */ - gen_aa32_ld32u_iss(s, tmp, addr, - get_mem_index(s), - rd | ISSIsAcqRel); - break; - case 2: /* ldab */ - gen_aa32_ld8u_iss(s, tmp, addr, - get_mem_index(s), - rd | ISSIsAcqRel); - break; - case 3: /* ldah */ - gen_aa32_ld16u_iss(s, tmp, addr, - get_mem_index(s), - rd | ISSIsAcqRel); - break; - default: - abort(); - } - store_reg(s, rd, tmp); - } else { - rm = insn & 0xf; - tmp = load_reg(s, rm); - switch (op1) { - case 0: /* stl */ - gen_aa32_st32_iss(s, tmp, addr, - get_mem_index(s), - rm | ISSIsAcqRel); - break; - case 2: /* stlb */ - gen_aa32_st8_iss(s, tmp, addr, - get_mem_index(s), - rm | ISSIsAcqRel); - break; - case 3: /* stlh */ - gen_aa32_st16_iss(s, tmp, addr, - get_mem_index(s), - rm | ISSIsAcqRel); - break; - default: - abort(); - } - tcg_temp_free_i32(tmp); - } - } else if (is_ld) { - switch (op1) { - case 0: /* ldrex */ - gen_load_exclusive(s, rd, 15, addr, 2); - break; - case 1: /* ldrexd */ - gen_load_exclusive(s, rd, rd + 1, addr, 3); - break; - case 2: /* ldrexb */ - gen_load_exclusive(s, rd, 15, addr, 0); - break; - case 3: /* ldrexh */ - gen_load_exclusive(s, rd, 15, addr, 1); - break; - default: - abort(); - } - } else { - rm = insn & 0xf; - switch (op1) { - case 0: /* strex */ - gen_store_exclusive(s, rd, rm, 15, addr, 2); - break; - case 1: /* strexd */ - gen_store_exclusive(s, rd, rm, rm + 1, addr, 3); - break; - case 2: /* strexb */ - gen_store_exclusive(s, rd, rm, 15, addr, 0); - break; - case 3: /* strexh */ - gen_store_exclusive(s, rd, rm, 15, addr, 1); - break; - default: - abort(); - } - } - tcg_temp_free_i32(addr); - - if (is_lasr && is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } - } else if ((insn & 0x00300f00) == 0) { - /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx - * - SWP, SWPB - */ - - TCGv taddr; - TCGMemOp opc = s->be_data; - - rm = (insn) & 0xf; - - if (insn & (1 << 22)) { - opc |= MO_UB; - } else { - opc |= MO_UL | MO_ALIGN; - } - - addr = load_reg(s, rn); - taddr = gen_aa32_addr(s, addr, opc); - tcg_temp_free_i32(addr); - - tmp = load_reg(s, rm); - tcg_gen_atomic_xchg_i32(tmp, taddr, tmp, - get_mem_index(s), opc); - tcg_temp_free(taddr); - store_reg(s, rd, tmp); - } else { - goto illegal_op; - } - } - } else { - /* Extra load/store (register) instructions */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; break; case 0x4: case 0x5: @@ -9932,15 +10064,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } goto illegal_op; } - addr = tcg_temp_local_new_i32(); - load_reg_var(s, addr, rn); - tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2); - if (insn & (1 << 20)) { - gen_load_exclusive(s, rs, 15, addr, 2); - } else { - gen_store_exclusive(s, rd, rs, 15, addr, 2); - } - tcg_temp_free_i32(addr); + /* Load/store exclusive, in decodetree */ + goto illegal_op; } else if ((insn & (7 << 5)) == 0) { /* Table Branch. */ addr = load_reg(s, rn); @@ -9962,89 +10087,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_gen_addi_i32(tmp, tmp, read_pc(s)); store_reg(s, 15, tmp); } else { - bool is_lasr = false; - bool is_ld = extract32(insn, 20, 1); - int op2 = (insn >> 6) & 0x3; - op = (insn >> 4) & 0x3; - switch (op2) { - case 0: - goto illegal_op; - case 1: - /* Load/store exclusive byte/halfword/doubleword */ - if (op == 2) { - goto illegal_op; - } - ARCH(7); - break; - case 2: - /* Load-acquire/store-release */ - if (op == 3) { - goto illegal_op; - } - /* Fall through */ - case 3: - /* Load-acquire/store-release exclusive */ - ARCH(8); - is_lasr = true; - break; - } - - if (is_lasr && !is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - - addr = tcg_temp_local_new_i32(); - load_reg_var(s, addr, rn); - if (!(op2 & 1)) { - if (is_ld) { - tmp = tcg_temp_new_i32(); - switch (op) { - case 0: /* ldab */ - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), - rs | ISSIsAcqRel); - break; - case 1: /* ldah */ - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), - rs | ISSIsAcqRel); - break; - case 2: /* lda */ - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), - rs | ISSIsAcqRel); - break; - default: - abort(); - } - store_reg(s, rs, tmp); - } else { - tmp = load_reg(s, rs); - switch (op) { - case 0: /* stlb */ - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), - rs | ISSIsAcqRel); - break; - case 1: /* stlh */ - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), - rs | ISSIsAcqRel); - break; - case 2: /* stl */ - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), - rs | ISSIsAcqRel); - break; - default: - abort(); - } - tcg_temp_free_i32(tmp); - } - } else if (is_ld) { - gen_load_exclusive(s, rs, rd, addr, op); - } else { - gen_store_exclusive(s, rm, rs, rd, addr, op); - } - tcg_temp_free_i32(addr); - - if (is_lasr && is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } + /* Load/store exclusive, load-acq/store-rel, in decodetree */ + goto illegal_op; } } else { /* Load/store multiple, RFE, SRS. */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index f7742deaee..c76cbad569 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -39,6 +39,8 @@ &mrs_bank rd r sysm &ldst_rr p w u rn rt rm shimm shtype &ldst_ri p w u rn rt imm +&strex rn rd rt rt2 imm +&ldrex rn rt rt2 imm # Data-processing (register) @@ -342,3 +344,49 @@ STRT_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p0w1 STRBT_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p0w1 LDRT_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p0w1 LDRBT_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p0w1 + +# Synchronization primitives + +@swp ---- .... .... rn:4 rt:4 .... .... rt2:4 + +SWP .... 0001 0000 .... .... 0000 1001 .... @swp +SWPB .... 0001 0100 .... .... 0000 1001 .... @swp + +# Load/Store Exclusive and Load-Acquire/Store-Release +# +# Note rt2 for STREXD/LDREXD is set by the helper after checking rt is even. + +@strex ---- .... .... rn:4 rd:4 .... .... rt:4 \ + &strex imm=0 rt2=15 +@ldrex ---- .... .... rn:4 rt:4 .... .... .... \ + &ldrex imm=0 rt2=15 +@stl ---- .... .... rn:4 .... .... .... rt:4 \ + &ldrex imm=0 rt2=15 + +STREX .... 0001 1000 .... .... 1111 1001 .... @strex +STREXD_a32 .... 0001 1010 .... .... 1111 1001 .... @strex +STREXB .... 0001 1100 .... .... 1111 1001 .... @strex +STREXH .... 0001 1110 .... .... 1111 1001 .... @strex + +STLEX .... 0001 1000 .... .... 1110 1001 .... @strex +STLEXD_a32 .... 0001 1010 .... .... 1110 1001 .... @strex +STLEXB .... 0001 1100 .... .... 1110 1001 .... @strex +STLEXH .... 0001 1110 .... .... 1110 1001 .... @strex + +STL .... 0001 1000 .... 1111 1100 1001 .... @stl +STLB .... 0001 1100 .... 1111 1100 1001 .... @stl +STLH .... 0001 1110 .... 1111 1100 1001 .... @stl + +LDREX .... 0001 1001 .... .... 1111 1001 1111 @ldrex +LDREXD_a32 .... 0001 1011 .... .... 1111 1001 1111 @ldrex +LDREXB .... 0001 1101 .... .... 1111 1001 1111 @ldrex +LDREXH .... 0001 1111 .... .... 1111 1001 1111 @ldrex + +LDAEX .... 0001 1001 .... .... 1110 1001 1111 @ldrex +LDAEXD_a32 .... 0001 1011 .... .... 1110 1001 1111 @ldrex +LDAEXB .... 0001 1101 .... .... 1110 1001 1111 @ldrex +LDAEXH .... 0001 1111 .... .... 1110 1001 1111 @ldrex + +LDA .... 0001 1001 .... .... 1100 1001 1111 @ldrex +LDAB .... 0001 1101 .... .... 1100 1001 1111 @ldrex +LDAH .... 0001 1111 .... .... 1100 1001 1111 @ldrex diff --git a/target/arm/t32.decode b/target/arm/t32.decode index a86597562b..70cf8039d7 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -36,6 +36,8 @@ &mrs_bank !extern rd r sysm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm +&strex !extern rn rd rt rt2 imm +&ldrex !extern rn rt rt2 imm # Data-processing (register) @@ -392,3 +394,47 @@ LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1 LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1 + +# Load/Store Exclusive and Load-Acquire/Store-Release + +@strex_i .... .... .... rn:4 rt:4 rd:4 .... .... \ + &strex rt2=15 imm=%imm8x4 +@strex_0 .... .... .... rn:4 rt:4 .... .... rd:4 \ + &strex rt2=15 imm=0 +@strex_d .... .... .... rn:4 rt:4 rt2:4 .... rd:4 \ + &strex imm=0 + +@ldrex_i .... .... .... rn:4 rt:4 .... .... .... \ + &ldrex rt2=15 imm=%imm8x4 +@ldrex_0 .... .... .... rn:4 rt:4 .... .... .... \ + &ldrex rt2=15 imm=0 +@ldrex_d .... .... .... rn:4 rt:4 rt2:4 .... .... \ + &ldrex imm=0 + +STREX 1110 1000 0100 .... .... .... .... .... @strex_i +STREXB 1110 1000 1100 .... .... 1111 0100 .... @strex_0 +STREXH 1110 1000 1100 .... .... 1111 0101 .... @strex_0 +STREXD_t32 1110 1000 1100 .... .... .... 0111 .... @strex_d + +STLEX 1110 1000 1100 .... .... 1111 1110 .... @strex_0 +STLEXB 1110 1000 1100 .... .... 1111 1100 .... @strex_0 +STLEXH 1110 1000 1100 .... .... 1111 1101 .... @strex_0 +STLEXD_t32 1110 1000 1100 .... .... .... 1111 .... @strex_d + +STL 1110 1000 1100 .... .... 1111 1010 1111 @ldrex_0 +STLB 1110 1000 1100 .... .... 1111 1000 1111 @ldrex_0 +STLH 1110 1000 1100 .... .... 1111 1001 1111 @ldrex_0 + +LDREX 1110 1000 0101 .... .... 1111 .... .... @ldrex_i +LDREXB 1110 1000 1101 .... .... 1111 0100 1111 @ldrex_0 +LDREXH 1110 1000 1101 .... .... 1111 0101 1111 @ldrex_0 +LDREXD_t32 1110 1000 1101 .... .... .... 0111 1111 @ldrex_d + +LDAEX 1110 1000 1101 .... .... 1111 1110 1111 @ldrex_0 +LDAEXB 1110 1000 1101 .... .... 1111 1100 1111 @ldrex_0 +LDAEXH 1110 1000 1101 .... .... 1111 1101 1111 @ldrex_0 +LDAEXD_t32 1110 1000 1101 .... .... .... 1111 1111 @ldrex_d + +LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0 +LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0 +LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0 From patchwork Mon Aug 19 21:37:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171678 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3540230ily; Mon, 19 Aug 2019 14:53:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqz8uWG4m0YFnREekGBnz/OqtVsGeWJSvCNgDSg5lLQslDbZ3OWKT3D3cMs9PdzvMNMgQCwN X-Received: by 2002:a05:6402:295:: with SMTP id l21mr27412943edv.13.1566251600746; Mon, 19 Aug 2019 14:53:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566251600; cv=none; d=google.com; s=arc-20160816; b=BsHXZwbfyp4AA0s685FRtwwdHfWHsIoiK8EAA0UcYIUbbRDtiYRe59VLjGLoV6n4e+ +0g2VRMaYFc/46BPbwKWItYjgPWFrbDvbzbGUpyMQ6OeSgTdqZ1J9AcZXx//2z3x5HP6 15yQj7a6S73V6E5+lO+h7ia3xbcC25Tiv+lxbb9bdib6YAkyaJeJ50R8oW4LXgZzw1nr s489slNxLRaTz5WxvdHZdHRHZChemBn3gIvxY/zyC37Cub10DtNOiXko9bAq9IVwP+77 UsmbWVq/3KGr10i0Up7usOya88d58u8FHOgo/LnqodexA9XykSCde2SPABx3ZfPbUSxW Va0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=0nkhvFNWh9JA2E6GDxXbIzz/FtBFCfF30Q7P+QipECs=; b=sg3jinmQLod2MENWwx8i0yD6O3iEwE0SvACEcz7vCuj5F7tKAZlBZfbtGeJPjUCCSh trczFvkLjHiJX9oeZfqQFhhoARPoRMS62D4+TqG05eQ67gYNpQXQ24nwDWzYu1oA1YGT H/hXw4/XdZqhTG5S3YFDfCJdeNeGc5YBxawqoY+VHphPFcXzS+mN09o1kdAx273RSLFu XrOUYUeJevM8e7SLEO952nBhdwtb88xv+gORk3Vhg14+Sef12OjF9h79nkyegiwg2DTU gIVVQOi/pPIAdtHPD6KQtI9RSbrMvQOP9QaQzL06AlohNMcUR9NX2thSDL72R44spb3J eLOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Z0kiOylE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:09 -0700 Message-Id: <20190819213755.26175-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 22/68] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 200 +++++++++++++++++++++-------------------- target/arm/a32.decode | 20 +++++ target/arm/t32.decode | 19 ++++ 3 files changed, 143 insertions(+), 96 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 3b0998444d..2764a1a637 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9119,6 +9119,103 @@ static bool trans_LDAH(DisasContext *s, arg_LDA *a) return op_lda(s, a, MO_UW); } +/* + * Media instructions + */ + +static bool trans_USADA8(DisasContext *s, arg_USADA8 *a) +{ + TCGv_i32 t1, t2; + + if (!ENABLE_ARCH_6) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + gen_helper_usad8(t1, t1, t2); + tcg_temp_free_i32(t2); + if (a->ra != 15) { + t2 = load_reg(s, a->ra); + tcg_gen_add_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + } + store_reg(s, a->rd, t1); + return true; +} + +static bool op_bfx(DisasContext *s, arg_UBFX *a, bool u) +{ + TCGv_i32 tmp; + int width = a->widthm1 + 1; + int shift = a->lsb; + + if (!ENABLE_ARCH_6T2) { + return false; + } + + tmp = load_reg(s, a->rn); + if (shift + width > 32) { + return false; + } else if (width < 32) { + if (u) { + tcg_gen_extract_i32(tmp, tmp, shift, width); + } else { + tcg_gen_sextract_i32(tmp, tmp, shift, width); + } + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_SBFX(DisasContext *s, arg_SBFX *a) +{ + return op_bfx(s, a, false); +} + +static bool trans_UBFX(DisasContext *s, arg_UBFX *a) +{ + return op_bfx(s, a, true); +} + +static bool trans_BFCI(DisasContext *s, arg_BFCI *a) +{ + TCGv_i32 tmp; + int msb = a->msb, lsb = a->lsb; + int width; + + if (!ENABLE_ARCH_6T2) { + return false; + } + + if (msb < lsb) { + /* UNPREDICTABLE; we choose to UNDEF */ + return false; + } + + width = msb + 1 - lsb; + if (a->rn == 15) { + /* BFC */ + tmp = tcg_const_i32(0); + } else { + /* BFI */ + tmp = load_reg(s, a->rn); + } + if (width != 32) { + TCGv_i32 tmp2 = load_reg(s, a->rd); + tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width); + tcg_temp_free_i32(tmp2); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_UDF(DisasContext *s, arg_UDF *a) +{ + unallocated_encoding(s); + return true; +} + /* * Legacy decoder. */ @@ -9659,65 +9756,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } break; case 3: - op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7); - switch (op1) { - case 0: /* Unsigned sum of absolute differences. */ - ARCH(6); - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rs); - gen_helper_usad8(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rd != 15) { - tmp2 = load_reg(s, rd); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rn, tmp); - break; - case 0x20: case 0x24: case 0x28: case 0x2c: - /* Bitfield insert/clear. */ - ARCH(6T2); - shift = (insn >> 7) & 0x1f; - i = (insn >> 16) & 0x1f; - if (i < shift) { - /* UNPREDICTABLE; we choose to UNDEF */ - goto illegal_op; - } - i = i + 1 - shift; - if (rm == 15) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp = load_reg(s, rm); - } - if (i != 32) { - tmp2 = load_reg(s, rd); - tcg_gen_deposit_i32(tmp, tmp2, tmp, shift, i); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rd, tmp); - break; - case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */ - case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */ - ARCH(6T2); - tmp = load_reg(s, rm); - shift = (insn >> 7) & 0x1f; - i = ((insn >> 16) & 0x1f) + 1; - if (shift + i > 32) - goto illegal_op; - if (i < 32) { - if (op1 & 0x20) { - tcg_gen_extract_i32(tmp, tmp, shift, i); - } else { - tcg_gen_sextract_i32(tmp, tmp, shift, i); - } - } - store_reg(s, rd, tmp); - break; - default: - goto illegal_op; - } - break; + /* USAD, BFI, BFC, SBFX, UBFX */ + /* Done by decodetree */ + goto illegal_op; } break; } @@ -10359,10 +10400,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 0: /* 32 x 32 -> 32 */ case 1: /* 16 x 16 -> 32 */ case 3: /* 32 * 16 -> 32msb */ + case 7: /* Unsigned sum of absolute differences. */ /* in decodetree */ goto illegal_op; - case 7: /* Unsigned sum of absolute differences. */ - break; case 2: /* Dual multiply add. */ case 4: /* Dual multiply subtract. */ case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ @@ -10420,15 +10460,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } tcg_temp_free_i32(tmp2); break; - case 7: /* Unsigned sum of absolute differences. */ - gen_helper_usad8(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rs != 15) { - tmp2 = load_reg(s, rs); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; } store_reg(s, rd, tmp); break; @@ -10723,32 +10754,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tmp = load_reg(s, rn); } switch (op) { - case 2: /* Signed bitfield extract. */ - imm++; - if (shift + imm > 32) - goto illegal_op; - if (imm < 32) { - tcg_gen_sextract_i32(tmp, tmp, shift, imm); - } - break; - case 6: /* Unsigned bitfield extract. */ - imm++; - if (shift + imm > 32) - goto illegal_op; - if (imm < 32) { - tcg_gen_extract_i32(tmp, tmp, shift, imm); - } - break; - case 3: /* Bitfield insert/clear. */ - if (imm < shift) - goto illegal_op; - imm = imm + 1 - shift; - if (imm != 32) { - tmp2 = load_reg(s, rd); - tcg_gen_deposit_i32(tmp, tmp2, tmp, shift, imm); - tcg_temp_free_i32(tmp2); - } - break; + case 2: /* Signed bitfield extract, in decodetree */ + case 6: /* Unsigned bitfield extract, in decodetree */ + case 3: /* Bitfield insert/clear, in decodetree */ case 7: goto illegal_op; default: /* Saturate. */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index c76cbad569..285c08ca22 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -41,6 +41,8 @@ &ldst_ri p w u rn rt imm &strex rn rd rt rt2 imm &ldrex rn rt rt2 imm +&bfx rd rn lsb widthm1 +&bfi rd rn lsb msb # Data-processing (register) @@ -390,3 +392,21 @@ LDAEXH .... 0001 1111 .... .... 1110 1001 1111 @ldrex LDA .... 0001 1001 .... .... 1100 1001 1111 @ldrex LDAB .... 0001 1101 .... .... 1100 1001 1111 @ldrex LDAH .... 0001 1111 .... .... 1100 1001 1111 @ldrex + +# Media instructions + +# usad8 is usada8 w/ ra=15 +USADA8 ---- 0111 1000 rd:4 ra:4 rm:4 0001 rn:4 + +# ubfx and sbfx +@bfx ---- .... ... widthm1:5 rd:4 lsb:5 ... rn:4 &bfx + +SBFX .... 0111 101 ..... .... ..... 101 .... @bfx +UBFX .... 0111 111 ..... .... ..... 101 .... @bfx + +# bfc is bfi w/ rn=15 +BFCI ---- 0111 110 msb:5 rd:4 lsb:5 001 rn:4 &bfi + +# While we could get UDEF by not including this, add the pattern for +# documentation and to conflict with any other typos in this file. +UDF 1110 0111 1111 ---- ---- ---- 1111 ---- diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 70cf8039d7..682fc5c2c4 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -38,6 +38,8 @@ &ldst_ri !extern p w u rn rt imm &strex !extern rn rd rt rt2 imm &ldrex !extern rn rt rt2 imm +&bfx !extern rd rn lsb widthm1 +&bfi !extern rd rn lsb msb # Data-processing (register) @@ -144,6 +146,19 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12 } +# Saturate, bitfield + +@bfx .... .... ... . rn:4 . ... rd:4 .. . widthm1:5 \ + &bfx lsb=%imm5_12_6 +@bfi .... .... ... . rn:4 . ... rd:4 .. . msb:5 \ + &bfi lsb=%imm5_12_6 + +SBFX 1111 0011 010 0 .... 0 ... .... ..0..... @bfx +UBFX 1111 0011 110 0 .... 0 ... .... ..0..... @bfx + +# bfc is bfi w/ rn=15 +BFCI 1111 0011 011 0 .... 0 ... .... ..0..... @bfi + # Multiply and multiply accumulate @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0 @@ -192,6 +207,9 @@ SMLALBT 1111 1011 1100 .... .... .... 1001 .... @rnadm SMLALTB 1111 1011 1100 .... .... .... 1010 .... @rnadm SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm +# usad8 is usada8 w/ ra=15 +USADA8 1111 1011 0111 .... .... .... 0000 .... @rnadm + # Data-processing (two source registers) QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm @@ -254,6 +272,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=%imm16_16_0 + UDF 1111 0111 1111 ---- 1010 ---- ---- ---- } # Load/store (register, immediate, literal) From patchwork Mon Aug 19 21:37:10 2019 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 23/68] target/arm: Convert Parallel addition and subtraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 229 ++++++++++++++++++++--------------------- target/arm/a32.decode | 44 ++++++++ target/arm/t32.decode | 44 ++++++++ 3 files changed, 200 insertions(+), 117 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 2764a1a637..cf03527afc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -648,99 +648,6 @@ static inline void gen_arm_shift_reg(TCGv_i32 var, int shiftop, tcg_temp_free_i32(shift); } -#define PAS_OP(pfx) \ - switch (op2) { \ - case 0: gen_pas_helper(glue(pfx,add16)); break; \ - case 1: gen_pas_helper(glue(pfx,addsubx)); break; \ - case 2: gen_pas_helper(glue(pfx,subaddx)); break; \ - case 3: gen_pas_helper(glue(pfx,sub16)); break; \ - case 4: gen_pas_helper(glue(pfx,add8)); break; \ - case 7: gen_pas_helper(glue(pfx,sub8)); break; \ - } -static void gen_arm_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b) -{ - TCGv_ptr tmp; - - switch (op1) { -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) - case 1: - tmp = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(s) - tcg_temp_free_ptr(tmp); - break; - case 5: - tmp = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(u) - tcg_temp_free_ptr(tmp); - break; -#undef gen_pas_helper -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) - case 2: - PAS_OP(q); - break; - case 3: - PAS_OP(sh); - break; - case 6: - PAS_OP(uq); - break; - case 7: - PAS_OP(uh); - break; -#undef gen_pas_helper - } -} -#undef PAS_OP - -/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */ -#define PAS_OP(pfx) \ - switch (op1) { \ - case 0: gen_pas_helper(glue(pfx,add8)); break; \ - case 1: gen_pas_helper(glue(pfx,add16)); break; \ - case 2: gen_pas_helper(glue(pfx,addsubx)); break; \ - case 4: gen_pas_helper(glue(pfx,sub8)); break; \ - case 5: gen_pas_helper(glue(pfx,sub16)); break; \ - case 6: gen_pas_helper(glue(pfx,subaddx)); break; \ - } -static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b) -{ - TCGv_ptr tmp; - - switch (op2) { -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) - case 0: - tmp = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(s) - tcg_temp_free_ptr(tmp); - break; - case 4: - tmp = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(u) - tcg_temp_free_ptr(tmp); - break; -#undef gen_pas_helper -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) - case 1: - PAS_OP(q); - break; - case 2: - PAS_OP(sh); - break; - case 5: - PAS_OP(uq); - break; - case 6: - PAS_OP(uh); - break; -#undef gen_pas_helper - } -} -#undef PAS_OP - /* * Generate a conditional based on ARM condition code cc. * This is common between ARM and Aarch64 targets. @@ -9216,6 +9123,114 @@ static bool trans_UDF(DisasContext *s, arg_UDF *a) return true; } +/* + * Parallel addition and subtraction + */ + +static bool op_par_addsub(DisasContext *s, arg_rrr *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 t0, t1; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t0 = load_reg(s, a->rn); + t1 = load_reg(s, a->rm); + + gen(t0, t0, t1); + + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +static bool op_par_addsub_ge(DisasContext *s, arg_rrr *a, + void (*gen)(TCGv_i32, TCGv_i32, + TCGv_i32, TCGv_ptr)) +{ + TCGv_i32 t0, t1; + TCGv_ptr ge; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t0 = load_reg(s, a->rn); + t1 = load_reg(s, a->rm); + + ge = tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ge, cpu_env, offsetof(CPUARMState, GE)); + gen(t0, t0, t1, ge); + + tcg_temp_free_ptr(ge); + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +#define DO_PAR_ADDSUB(NAME, helper) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_par_addsub(s, a, helper); \ +} + +#define DO_PAR_ADDSUB_GE(NAME, helper) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_par_addsub_ge(s, a, helper); \ +} + +DO_PAR_ADDSUB_GE(SADD16, gen_helper_sadd16) +DO_PAR_ADDSUB_GE(SASX, gen_helper_saddsubx) +DO_PAR_ADDSUB_GE(SSAX, gen_helper_ssubaddx) +DO_PAR_ADDSUB_GE(SSUB16, gen_helper_ssub16) +DO_PAR_ADDSUB_GE(SADD8, gen_helper_sadd8) +DO_PAR_ADDSUB_GE(SSUB8, gen_helper_ssub8) + +DO_PAR_ADDSUB_GE(UADD16, gen_helper_uadd16) +DO_PAR_ADDSUB_GE(UASX, gen_helper_uaddsubx) +DO_PAR_ADDSUB_GE(USAX, gen_helper_usubaddx) +DO_PAR_ADDSUB_GE(USUB16, gen_helper_usub16) +DO_PAR_ADDSUB_GE(UADD8, gen_helper_uadd8) +DO_PAR_ADDSUB_GE(USUB8, gen_helper_usub8) + +DO_PAR_ADDSUB(QADD16, gen_helper_qadd16) +DO_PAR_ADDSUB(QASX, gen_helper_qaddsubx) +DO_PAR_ADDSUB(QSAX, gen_helper_qsubaddx) +DO_PAR_ADDSUB(QSUB16, gen_helper_qsub16) +DO_PAR_ADDSUB(QADD8, gen_helper_qadd8) +DO_PAR_ADDSUB(QSUB8, gen_helper_qsub8) + +DO_PAR_ADDSUB(UQADD16, gen_helper_uqadd16) +DO_PAR_ADDSUB(UQASX, gen_helper_uqaddsubx) +DO_PAR_ADDSUB(UQSAX, gen_helper_uqsubaddx) +DO_PAR_ADDSUB(UQSUB16, gen_helper_uqsub16) +DO_PAR_ADDSUB(UQADD8, gen_helper_uqadd8) +DO_PAR_ADDSUB(UQSUB8, gen_helper_uqsub8) + +DO_PAR_ADDSUB(SHADD16, gen_helper_shadd16) +DO_PAR_ADDSUB(SHASX, gen_helper_shaddsubx) +DO_PAR_ADDSUB(SHSAX, gen_helper_shsubaddx) +DO_PAR_ADDSUB(SHSUB16, gen_helper_shsub16) +DO_PAR_ADDSUB(SHADD8, gen_helper_shadd8) +DO_PAR_ADDSUB(SHSUB8, gen_helper_shsub8) + +DO_PAR_ADDSUB(UHADD16, gen_helper_uhadd16) +DO_PAR_ADDSUB(UHASX, gen_helper_uhaddsubx) +DO_PAR_ADDSUB(UHSAX, gen_helper_uhsubaddx) +DO_PAR_ADDSUB(UHSUB16, gen_helper_uhsub16) +DO_PAR_ADDSUB(UHADD8, gen_helper_uhadd8) +DO_PAR_ADDSUB(UHSUB8, gen_helper_uhsub8) + +#undef DO_PAR_ADDSUB +#undef DO_PAR_ADDSUB_GE + /* * Legacy decoder. */ @@ -9528,16 +9543,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) rs = (insn >> 8) & 0xf; switch ((insn >> 23) & 3) { case 0: /* Parallel add/subtract. */ - op1 = (insn >> 20) & 7; - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - sh = (insn >> 5) & 7; - if ((op1 & 3) == 0 || sh == 5 || sh == 6) - goto illegal_op; - gen_arm_parallel_addsub(op1, sh, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + /* Done by decodetree */ + goto illegal_op; case 1: if ((insn & 0x00700020) == 0) { /* Halfword pack. */ @@ -10324,20 +10331,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } store_reg(s, rd, tmp); break; - case 2: /* SIMD add/subtract. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - op = (insn >> 20) & 7; - shift = (insn >> 4) & 7; - if ((op & 3) == 3 || (shift & 3) == 3) - goto illegal_op; - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - gen_thumb2_parallel_addsub(op, shift, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + case 2: /* SIMD add/subtract, in decodetree */ + goto illegal_op; case 3: /* Other data processing. */ op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7); if (op < 4) { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 285c08ca22..4dfd8133f7 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -410,3 +410,47 @@ BFCI ---- 0111 110 msb:5 rd:4 lsb:5 001 rn:4 &bfi # While we could get UDEF by not including this, add the pattern for # documentation and to conflict with any other typos in this file. UDF 1110 0111 1111 ---- ---- ---- 1111 ---- + +# Parallel addition and subtraction + +SADD16 .... 0110 0001 .... .... 1111 0001 .... @rndm +SASX .... 0110 0001 .... .... 1111 0011 .... @rndm +SSAX .... 0110 0001 .... .... 1111 0101 .... @rndm +SSUB16 .... 0110 0001 .... .... 1111 0111 .... @rndm +SADD8 .... 0110 0001 .... .... 1111 1001 .... @rndm +SSUB8 .... 0110 0001 .... .... 1111 1111 .... @rndm + +QADD16 .... 0110 0010 .... .... 1111 0001 .... @rndm +QASX .... 0110 0010 .... .... 1111 0011 .... @rndm +QSAX .... 0110 0010 .... .... 1111 0101 .... @rndm +QSUB16 .... 0110 0010 .... .... 1111 0111 .... @rndm +QADD8 .... 0110 0010 .... .... 1111 1001 .... @rndm +QSUB8 .... 0110 0010 .... .... 1111 1111 .... @rndm + +SHADD16 .... 0110 0011 .... .... 1111 0001 .... @rndm +SHASX .... 0110 0011 .... .... 1111 0011 .... @rndm +SHSAX .... 0110 0011 .... .... 1111 0101 .... @rndm +SHSUB16 .... 0110 0011 .... .... 1111 0111 .... @rndm +SHADD8 .... 0110 0011 .... .... 1111 1001 .... @rndm +SHSUB8 .... 0110 0011 .... .... 1111 1111 .... @rndm + +UADD16 .... 0110 0101 .... .... 1111 0001 .... @rndm +UASX .... 0110 0101 .... .... 1111 0011 .... @rndm +USAX .... 0110 0101 .... .... 1111 0101 .... @rndm +USUB16 .... 0110 0101 .... .... 1111 0111 .... @rndm +UADD8 .... 0110 0101 .... .... 1111 1001 .... @rndm +USUB8 .... 0110 0101 .... .... 1111 1111 .... @rndm + +UQADD16 .... 0110 0110 .... .... 1111 0001 .... @rndm +UQASX .... 0110 0110 .... .... 1111 0011 .... @rndm +UQSAX .... 0110 0110 .... .... 1111 0101 .... @rndm +UQSUB16 .... 0110 0110 .... .... 1111 0111 .... @rndm +UQADD8 .... 0110 0110 .... .... 1111 1001 .... @rndm +UQSUB8 .... 0110 0110 .... .... 1111 1111 .... @rndm + +UHADD16 .... 0110 0111 .... .... 1111 0001 .... @rndm +UHASX .... 0110 0111 .... .... 1111 0011 .... @rndm +UHSAX .... 0110 0111 .... .... 1111 0101 .... @rndm +UHSUB16 .... 0110 0111 .... .... 1111 0111 .... @rndm +UHADD8 .... 0110 0111 .... .... 1111 1001 .... @rndm +UHSUB8 .... 0110 0111 .... .... 1111 1111 .... @rndm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 682fc5c2c4..c899c56766 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -457,3 +457,47 @@ LDAEXD_t32 1110 1000 1101 .... .... .... 1111 1111 @ldrex_d LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0 LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0 LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0 + +# Parallel addition and subtraction + +SADD8 1111 1010 1000 .... 1111 .... 0000 .... @rndm +QADD8 1111 1010 1000 .... 1111 .... 0001 .... @rndm +SHADD8 1111 1010 1000 .... 1111 .... 0010 .... @rndm +UADD8 1111 1010 1000 .... 1111 .... 0100 .... @rndm +UQADD8 1111 1010 1000 .... 1111 .... 0101 .... @rndm +UHADD8 1111 1010 1000 .... 1111 .... 0110 .... @rndm + +SADD16 1111 1010 1001 .... 1111 .... 0000 .... @rndm +QADD16 1111 1010 1001 .... 1111 .... 0001 .... @rndm +SHADD16 1111 1010 1001 .... 1111 .... 0010 .... @rndm +UADD16 1111 1010 1001 .... 1111 .... 0100 .... @rndm +UQADD16 1111 1010 1001 .... 1111 .... 0101 .... @rndm +UHADD16 1111 1010 1001 .... 1111 .... 0110 .... @rndm + +SASX 1111 1010 1010 .... 1111 .... 0000 .... @rndm +QASX 1111 1010 1010 .... 1111 .... 0001 .... @rndm +SHASX 1111 1010 1010 .... 1111 .... 0010 .... @rndm +UASX 1111 1010 1010 .... 1111 .... 0100 .... @rndm +UQASX 1111 1010 1010 .... 1111 .... 0101 .... @rndm +UHASX 1111 1010 1010 .... 1111 .... 0110 .... @rndm + +SSUB8 1111 1010 1100 .... 1111 .... 0000 .... @rndm +QSUB8 1111 1010 1100 .... 1111 .... 0001 .... @rndm +SHSUB8 1111 1010 1100 .... 1111 .... 0010 .... @rndm +USUB8 1111 1010 1100 .... 1111 .... 0100 .... @rndm +UQSUB8 1111 1010 1100 .... 1111 .... 0101 .... @rndm +UHSUB8 1111 1010 1100 .... 1111 .... 0110 .... @rndm + +SSUB16 1111 1010 1101 .... 1111 .... 0000 .... @rndm +QSUB16 1111 1010 1101 .... 1111 .... 0001 .... @rndm +SHSUB16 1111 1010 1101 .... 1111 .... 0010 .... @rndm +USUB16 1111 1010 1101 .... 1111 .... 0100 .... @rndm +UQSUB16 1111 1010 1101 .... 1111 .... 0101 .... @rndm +UHSUB16 1111 1010 1101 .... 1111 .... 0110 .... @rndm + +SSAX 1111 1010 1110 .... 1111 .... 0000 .... @rndm +QSAX 1111 1010 1110 .... 1111 .... 0001 .... @rndm +SHSAX 1111 1010 1110 .... 1111 .... 0010 .... @rndm +USAX 1111 1010 1110 .... 1111 .... 0100 .... @rndm +UQSAX 1111 1010 1110 .... 1111 .... 0101 .... @rndm +UHSAX 1111 1010 1110 .... 1111 .... 0110 .... @rndm From patchwork Mon Aug 19 21:37:11 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:11 -0700 Message-Id: <20190819213755.26175-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v2 24/68] target/arm: Convert Packing, unpacking, saturation, and reversal X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 541 ++++++++++++++++++----------------------- target/arm/a32.decode | 32 +++ target/arm/t32.decode | 37 ++- 3 files changed, 300 insertions(+), 310 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index cf03527afc..d31e89f308 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -355,7 +355,7 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) } /* Byteswap each halfword. */ -static void gen_rev16(TCGv_i32 var) +static void gen_rev16(TCGv_i32 dest, TCGv_i32 var) { TCGv_i32 tmp = tcg_temp_new_i32(); TCGv_i32 mask = tcg_const_i32(0x00ff00ff); @@ -363,17 +363,17 @@ static void gen_rev16(TCGv_i32 var) tcg_gen_and_i32(tmp, tmp, mask); tcg_gen_and_i32(var, var, mask); tcg_gen_shli_i32(var, var, 8); - tcg_gen_or_i32(var, var, tmp); + tcg_gen_or_i32(dest, var, tmp); tcg_temp_free_i32(mask); tcg_temp_free_i32(tmp); } /* Byteswap low halfword and sign extend. */ -static void gen_revsh(TCGv_i32 var) +static void gen_revsh(TCGv_i32 dest, TCGv_i32 var) { tcg_gen_ext16u_i32(var, var); tcg_gen_bswap16_i32(var, var); - tcg_gen_ext16s_i32(var, var); + tcg_gen_ext16s_i32(dest, var); } /* 32x32->64 multiply. Marks inputs as dead. */ @@ -426,7 +426,7 @@ static void gen_swap_half(TCGv_i32 var) t0 = (t0 + t1) ^ tmp; */ -static void gen_add16(TCGv_i32 t0, TCGv_i32 t1) +static void gen_add16(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) { TCGv_i32 tmp = tcg_temp_new_i32(); tcg_gen_xor_i32(tmp, t0, t1); @@ -434,9 +434,8 @@ static void gen_add16(TCGv_i32 t0, TCGv_i32 t1) tcg_gen_andi_i32(t0, t0, ~0x8000); tcg_gen_andi_i32(t1, t1, ~0x8000); tcg_gen_add_i32(t0, t0, t1); - tcg_gen_xor_i32(t0, t0, tmp); + tcg_gen_xor_i32(dest, t0, tmp); tcg_temp_free_i32(tmp); - tcg_temp_free_i32(t1); } /* Set N and Z flags from var. */ @@ -6340,7 +6339,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } break; case NEON_2RM_VREV16: - gen_rev16(tmp); + gen_rev16(tmp, tmp); break; case NEON_2RM_VCLS: switch (size) { @@ -9231,13 +9230,225 @@ DO_PAR_ADDSUB(UHSUB8, gen_helper_uhsub8) #undef DO_PAR_ADDSUB #undef DO_PAR_ADDSUB_GE +/* + * Packing, unpacking, saturation, and reversal + */ + +static bool trans_PKH(DisasContext *s, arg_PKH *a) +{ + TCGv_i32 tn, tm; + int shift = a->imm; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + tn = load_reg(s, a->rn); + tm = load_reg(s, a->rm); + if (a->tb) { + /* PKHTB */ + if (shift == 0) { + shift = 31; + } + tcg_gen_sari_i32(tm, tm, shift); + tcg_gen_deposit_i32(tn, tn, tm, 0, 16); + } else { + /* PKHBT */ + tcg_gen_shli_i32(tm, tm, shift); + tcg_gen_deposit_i32(tn, tm, tn, 0, 16); + } + tcg_temp_free_i32(tm); + store_reg(s, a->rd, tn); + return true; +} + +static bool op_sat(DisasContext *s, arg_sat *a, + void (*gen)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp, satimm; + int shift = a->imm; + + if (!ENABLE_ARCH_6) { + return false; + } + + tmp = load_reg(s, a->rn); + if (a->sh) { + tcg_gen_sari_i32(tmp, tmp, shift ? shift : 31); + } else { + tcg_gen_shli_i32(tmp, tmp, shift); + } + + satimm = tcg_const_i32(a->satimm); + gen(tmp, cpu_env, tmp, satimm); + tcg_temp_free_i32(satimm); + + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_SSAT(DisasContext *s, arg_sat *a) +{ + return op_sat(s, a, gen_helper_ssat); +} + +static bool trans_USAT(DisasContext *s, arg_sat *a) +{ + return op_sat(s, a, gen_helper_usat); +} + +static bool trans_SSAT16(DisasContext *s, arg_sat *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_sat(s, a, gen_helper_ssat16); +} + +static bool trans_USAT16(DisasContext *s, arg_sat *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_sat(s, a, gen_helper_usat16); +} + +static bool op_xta(DisasContext *s, arg_rrr_rot *a, + void (*gen_extract)(TCGv_i32, TCGv_i32), + void (*gen_add)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_6) { + return false; + } + + tmp = load_reg(s, a->rm); + /* + * TODO: In many cases we could do a shift instead of a rotate. + * Combined with a simple extend, that becomes an extract. + */ + tcg_gen_rotri_i32(tmp, tmp, a->rot * 8); + gen_extract(tmp, tmp); + + if (a->rn != 15) { + TCGv_i32 tmp2 = load_reg(s, a->rn); + gen_add(tmp, tmp, tmp2); + tcg_temp_free_i32(tmp2); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_SXTAB(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext8s_i32, tcg_gen_add_i32); +} + +static bool trans_SXTAH(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext16s_i32, tcg_gen_add_i32); +} + +static bool trans_SXTAB16(DisasContext *s, arg_rrr_rot *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_xta(s, a, gen_helper_sxtb16, gen_add16); +} + +static bool trans_UXTAB(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext8u_i32, tcg_gen_add_i32); +} + +static bool trans_UXTAH(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext16u_i32, tcg_gen_add_i32); +} + +static bool trans_UXTAB16(DisasContext *s, arg_rrr_rot *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_xta(s, a, gen_helper_uxtb16, gen_add16); +} + +static bool trans_SEL(DisasContext *s, arg_rrr *a) +{ + TCGv_i32 t1, t2, t3; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + t3 = tcg_temp_new_i32(); + tcg_gen_ld_i32(t3, cpu_env, offsetof(CPUARMState, GE)); + gen_helper_sel_flags(t1, t3, t1, t2); + tcg_temp_free_i32(t3); + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool op_rr(DisasContext *s, arg_rr *a, + void (*gen)(TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp; + + tmp = load_reg(s, a->rm); + gen(tmp, tmp); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_REV(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_rr(s, a, tcg_gen_bswap32_i32); +} + +static bool trans_REV16(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_rr(s, a, gen_rev16); +} + +static bool trans_REVSH(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_rr(s, a, gen_revsh); +} + +static bool trans_RBIT(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6T2) { + return false; + } + return op_rr(s, a, gen_helper_rbit); +} + /* * Legacy decoder. */ static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh; + unsigned int cond, val, op1, i, rm, rs, rn, rd; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 tmp3; @@ -9546,112 +9757,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* Done by decodetree */ goto illegal_op; case 1: - if ((insn & 0x00700020) == 0) { - /* Halfword pack. */ - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - shift = (insn >> 7) & 0x1f; - if (insn & (1 << 6)) { - /* pkhtb */ - if (shift == 0) { - shift = 31; - } - tcg_gen_sari_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16); - } else { - /* pkhbt */ - tcg_gen_shli_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x00200020) == 0x00200000) { - /* [us]sat */ - tmp = load_reg(s, rm); - shift = (insn >> 7) & 0x1f; - if (insn & (1 << 6)) { - if (shift == 0) - shift = 31; - tcg_gen_sari_i32(tmp, tmp, shift); - } else { - tcg_gen_shli_i32(tmp, tmp, shift); - } - sh = (insn >> 16) & 0x1f; - tmp2 = tcg_const_i32(sh); - if (insn & (1 << 22)) - gen_helper_usat(tmp, cpu_env, tmp, tmp2); - else - gen_helper_ssat(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x00300fe0) == 0x00200f20) { - /* [us]sat16 */ - tmp = load_reg(s, rm); - sh = (insn >> 16) & 0x1f; - tmp2 = tcg_const_i32(sh); - if (insn & (1 << 22)) - gen_helper_usat16(tmp, cpu_env, tmp, tmp2); - else - gen_helper_ssat16(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x00700fe0) == 0x00000fa0) { - /* Select bytes. */ - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - tmp3 = tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE)); - gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); - tcg_temp_free_i32(tmp3); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x000003e0) == 0x00000060) { - tmp = load_reg(s, rm); - shift = (insn >> 10) & 3; - /* ??? In many cases it's not necessary to do a - rotate, a shift is sufficient. */ - tcg_gen_rotri_i32(tmp, tmp, shift * 8); - op1 = (insn >> 20) & 7; - switch (op1) { - case 0: gen_sxtb16(tmp); break; - case 2: gen_sxtb(tmp); break; - case 3: gen_sxth(tmp); break; - case 4: gen_uxtb16(tmp); break; - case 6: gen_uxtb(tmp); break; - case 7: gen_uxth(tmp); break; - default: goto illegal_op; - } - if (rn != 15) { - tmp2 = load_reg(s, rn); - if ((op1 & 3) == 0) { - gen_add16(tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - } - store_reg(s, rd, tmp); - } else if ((insn & 0x003f0f60) == 0x003f0f20) { - /* rev */ - tmp = load_reg(s, rm); - if (insn & (1 << 22)) { - if (insn & (1 << 7)) { - gen_revsh(tmp); - } else { - ARCH(6T2); - gen_helper_rbit(tmp, tmp); - } - } else { - if (insn & (1 << 7)) - gen_rev16(tmp); - else - tcg_gen_bswap32_i32(tmp, tmp); - } - store_reg(s, rd, tmp); - } else { - goto illegal_op; - } - break; + /* Halfword pack, [US]SAT, [US]SAT16, SEL, REV et al */ + /* Done by decodetree */ + goto illegal_op; case 2: /* Multiplies (Type 3). */ switch ((insn >> 20) & 0x7) { case 5: @@ -9990,7 +10098,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t imm, shift, offset; + uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10245,151 +10353,18 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } break; case 5: - - op = (insn >> 21) & 0xf; - if (op == 6) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - /* Halfword pack. */ - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3); - if (insn & (1 << 5)) { - /* pkhtb */ - if (shift == 0) { - shift = 31; - } - tcg_gen_sari_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16); - } else { - /* pkhbt */ - tcg_gen_shli_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else { - /* Data processing register constant shift. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } - break; + /* All in decodetree */ + goto illegal_op; case 13: /* Misc data processing. */ op = ((insn >> 22) & 6) | ((insn >> 7) & 1); if (op < 4 && (insn & 0xf000) != 0xf000) goto illegal_op; switch (op) { case 0: /* Register controlled shift, in decodetree */ - goto illegal_op; - case 1: /* Sign/zero extend. */ - op = (insn >> 20) & 7; - switch (op) { - case 0: /* SXTAH, SXTH */ - case 1: /* UXTAH, UXTH */ - case 4: /* SXTAB, SXTB */ - case 5: /* UXTAB, UXTB */ - break; - case 2: /* SXTAB16, SXTB16 */ - case 3: /* UXTAB16, UXTB16 */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - break; - default: - goto illegal_op; - } - if (rn != 15) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - } - tmp = load_reg(s, rm); - shift = (insn >> 4) & 3; - /* ??? In many cases it's not necessary to do a - rotate, a shift is sufficient. */ - tcg_gen_rotri_i32(tmp, tmp, shift * 8); - op = (insn >> 20) & 7; - switch (op) { - case 0: gen_sxth(tmp); break; - case 1: gen_uxth(tmp); break; - case 2: gen_sxtb16(tmp); break; - case 3: gen_uxtb16(tmp); break; - case 4: gen_sxtb(tmp); break; - case 5: gen_uxtb(tmp); break; - default: - g_assert_not_reached(); - } - if (rn != 15) { - tmp2 = load_reg(s, rn); - if ((op >> 1) == 1) { - gen_add16(tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - } - store_reg(s, rd, tmp); - break; + case 1: /* Sign/zero extend, in decodetree */ case 2: /* SIMD add/subtract, in decodetree */ + case 3: /* Other data processing, in decodetree */ goto illegal_op; - case 3: /* Other data processing. */ - op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7); - if (op < 4) { - /* Saturating add/subtract. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } else { - switch (op) { - case 0x0a: /* rbit */ - case 0x08: /* rev */ - case 0x09: /* rev16 */ - case 0x0b: /* revsh */ - break; - case 0x10: /* sel */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - break; - case 0x18: /* clz, in decodetree */ - case 0x20: /* crc32/crc32c, in decodetree */ - case 0x21: - case 0x22: - case 0x28: - case 0x29: - case 0x2a: - goto illegal_op; - default: - goto illegal_op; - } - tmp = load_reg(s, rn); - switch (op) { - case 0x0a: /* rbit */ - gen_helper_rbit(tmp, tmp); - break; - case 0x08: /* rev */ - tcg_gen_bswap32_i32(tmp, tmp); - break; - case 0x09: /* rev16 */ - gen_rev16(tmp); - break; - case 0x0b: /* revsh */ - gen_revsh(tmp); - break; - case 0x10: /* sel */ - tmp2 = load_reg(s, rm); - tmp3 = tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE)); - gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); - tcg_temp_free_i32(tmp3); - tcg_temp_free_i32(tmp2); - break; - default: - g_assert_not_reached(); - } - } - store_reg(s, rd, tmp); - break; case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */ switch ((insn >> 20) & 7) { case 0: /* 32 x 32 -> 32 */ @@ -10736,60 +10711,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) * - Data-processing (plain binary immediate) */ if (insn & (1 << 24)) { - if (insn & (1 << 20)) - goto illegal_op; - /* Bitfield/Saturate. */ - op = (insn >> 21) & 7; - imm = insn & 0x1f; - shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); - if (rn == 15) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp = load_reg(s, rn); - } - switch (op) { - case 2: /* Signed bitfield extract, in decodetree */ - case 6: /* Unsigned bitfield extract, in decodetree */ - case 3: /* Bitfield insert/clear, in decodetree */ - case 7: - goto illegal_op; - default: /* Saturate. */ - if (op & 1) { - tcg_gen_sari_i32(tmp, tmp, shift); - } else { - tcg_gen_shli_i32(tmp, tmp, shift); - } - tmp2 = tcg_const_i32(imm); - if (op & 4) { - /* Unsigned. */ - if ((op & 1) && shift == 0) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - goto illegal_op; - } - gen_helper_usat16(tmp, cpu_env, tmp, tmp2); - } else { - gen_helper_usat(tmp, cpu_env, tmp, tmp2); - } - } else { - /* Signed. */ - if ((op & 1) && shift == 0) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - goto illegal_op; - } - gen_helper_ssat16(tmp, cpu_env, tmp, tmp2); - } else { - gen_helper_ssat(tmp, cpu_env, tmp, tmp2); - } - } - tcg_temp_free_i32(tmp2); - break; - } - store_reg(s, rd, tmp); + /* Bitfield/Saturate, in decodetree */ + goto illegal_op; } else { imm = ((insn & 0x04000000) >> 15) | ((insn & 0x7000) >> 4) | (insn & 0xff); @@ -11481,8 +11404,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) tmp = load_reg(s, rn); switch (op1) { case 0: tcg_gen_bswap32_i32(tmp, tmp); break; - case 1: gen_rev16(tmp); break; - case 3: gen_revsh(tmp); break; + case 1: gen_rev16(tmp, tmp); break; + case 3: gen_revsh(tmp, tmp); break; default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 4dfd8133f7..4990eb3839 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -28,6 +28,7 @@ &s_rri_rot s rn rd imm rot &s_rrrr s rd rn rm ra &rrrr rd rn rm ra +&rrr_rot rd rn rm rot &rrr rd rn rm &rr rd rm &ri rd imm @@ -43,6 +44,8 @@ &ldrex rn rt rt2 imm &bfx rd rn lsb widthm1 &bfi rd rn lsb msb +&sat rd rn satimm imm sh +&pkh rd rn rm imm tb # Data-processing (register) @@ -454,3 +457,32 @@ UHSAX .... 0110 0111 .... .... 1111 0101 .... @rndm UHSUB16 .... 0110 0111 .... .... 1111 0111 .... @rndm UHADD8 .... 0110 0111 .... .... 1111 1001 .... @rndm UHSUB8 .... 0110 0111 .... .... 1111 1111 .... @rndm + +# Packing, unpacking, saturation, and reversal + +PKH ---- 0110 1000 rn:4 rd:4 imm:5 tb:1 01 rm:4 &pkh + +@sat ---- .... ... satimm:5 rd:4 imm:5 sh:1 .. rn:4 &sat +@sat16 ---- .... .... satimm:4 rd:4 .... .... rn:4 \ + &sat imm=0 sh=0 + +SSAT .... 0110 101. .... .... .... ..01 .... @sat +USAT .... 0110 111. .... .... .... ..01 .... @sat + +SSAT16 .... 0110 1010 .... .... 1111 0011 .... @sat16 +USAT16 .... 0110 1110 .... .... 1111 0011 .... @sat16 + +@rrr_rot ---- .... .... rn:4 rd:4 rot:2 ...... rm:4 &rrr_rot + +SXTAB16 .... 0110 1000 .... .... ..00 0111 .... @rrr_rot +SXTAB .... 0110 1010 .... .... ..00 0111 .... @rrr_rot +SXTAH .... 0110 1011 .... .... ..00 0111 .... @rrr_rot +UXTAB16 .... 0110 1100 .... .... ..00 0111 .... @rrr_rot +UXTAB .... 0110 1110 .... .... ..00 0111 .... @rrr_rot +UXTAH .... 0110 1111 .... .... ..00 0111 .... @rrr_rot + +SEL .... 0110 1000 .... .... 1111 1011 .... @rndm +REV .... 0110 1011 1111 .... 1111 0011 .... @rdm +REV16 .... 0110 1011 1111 .... 1111 1011 .... @rdm +REVSH .... 0110 1111 1111 .... 1111 1011 .... @rdm +RBIT .... 0110 1111 1111 .... 1111 0011 .... @rdm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index c899c56766..71f6d728f2 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -25,6 +25,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra +&rrr_rot !extern rd rn rm rot &rrr !extern rd rn rm &rr !extern rd rm &ri !extern rd imm @@ -40,6 +41,8 @@ &ldrex !extern rn rt rt2 imm &bfx !extern rd rn lsb widthm1 &bfi !extern rd rn lsb msb +&sat !extern rd rn satimm imm sh +&pkh !extern rd rn rm imm tb # Data-processing (register) @@ -69,7 +72,8 @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi TEQ_xrri 1110101 0100 1 .... 0 ... 1111 .... .... @S_xrr_shi EOR_rrri 1110101 0100 . .... 0 ... .... .... .... @s_rrr_shi } -# PKHBT, PKHTB at opc1 = 0110 +PKH 1110101 0110 0 rn:4 0 ... rd:4 .. tb:1 0 rm:4 \ + &pkh imm=%imm5_12_6 { CMN_xrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi @@ -148,6 +152,20 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot # Saturate, bitfield +@sat .... .... .. sh:1 . rn:4 . ... rd:4 .. . satimm:5 \ + &sat imm=%imm5_12_6 +@sat16 .... .... .. . . rn:4 . ... rd:4 .. . satimm:5 \ + &sat sh=0 imm=0 + +{ + SSAT16 1111 0011 001 0 .... 0 000 .... 00 0 ..... @sat16 + SSAT 1111 0011 00. 0 .... 0 ... .... .. 0 ..... @sat +} +{ + USAT16 1111 0011 101 0 .... 0 000 .... 00 0 ..... @sat16 + USAT 1111 0011 10. 0 .... 0 ... .... .. 0 ..... @sat +} + @bfx .... .... ... . rn:4 . ... rd:4 .. . widthm1:5 \ &bfx lsb=%imm5_12_6 @bfi .... .... ... . rn:4 . ... rd:4 .. . msb:5 \ @@ -224,7 +242,13 @@ CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm +SEL 1111 1010 1010 .... 1111 .... 1000 .... @rndm + # Note rn != rm is CONSTRAINED UNPREDICTABLE; we choose to ignore rn. +REV 1111 1010 1001 ---- 1111 .... 1000 .... @rdm +REV16 1111 1010 1001 ---- 1111 .... 1001 .... @rdm +RBIT 1111 1010 1001 ---- 1111 .... 1010 .... @rdm +REVSH 1111 1010 1001 ---- 1111 .... 1011 .... @rdm CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm # Branches and miscellaneous control @@ -501,3 +525,14 @@ SHSAX 1111 1010 1110 .... 1111 .... 0010 .... @rndm USAX 1111 1010 1110 .... 1111 .... 0100 .... @rndm UQSAX 1111 1010 1110 .... 1111 .... 0101 .... @rndm UHSAX 1111 1010 1110 .... 1111 .... 0110 .... @rndm + +# Register extends + +@rrr_rot .... .... .... rn:4 .... rd:4 .. rot:2 rm:4 &rrr_rot + +SXTAH 1111 1010 0000 .... 1111 .... 10.. .... @rrr_rot +UXTAH 1111 1010 0001 .... 1111 .... 10.. .... @rrr_rot +SXTAB16 1111 1010 0010 .... 1111 .... 10.. .... @rrr_rot +UXTAB16 1111 1010 0011 .... 1111 .... 10.. .... @rrr_rot +SXTAB 1111 1010 0100 .... 1111 .... 10.. .... @rrr_rot +UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot From patchwork Mon Aug 19 21:37:12 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:12 -0700 Message-Id: <20190819213755.26175-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 25/68] target/arm: Convert Signed multiply, signed and unsigned divide X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 463 ++++++++++++++++++----------------------- target/arm/a32.decode | 22 ++ target/arm/t32.decode | 18 ++ 3 files changed, 247 insertions(+), 256 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index d31e89f308..7962ac49e6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9442,18 +9442,217 @@ static bool trans_RBIT(DisasContext *s, arg_rr *a) return op_rr(s, a, gen_helper_rbit); } +/* + * Signed multiply, signed and unsigned divide + */ + +static bool op_smlad(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub) +{ + TCGv_i32 t1, t2; + + if (!ENABLE_ARCH_6) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + if (m_swap) { + gen_swap_half(t2); + } + gen_smul_dual(t1, t2); + + if (sub) { + /* This subtraction cannot overflow. */ + tcg_gen_sub_i32(t1, t1, t2); + } else { + /* + * This addition cannot overflow 32 bits; however it may + * overflow considered as a signed operation, in which case + * we must set the Q flag. + */ + gen_helper_add_setq(t1, cpu_env, t1, t2); + } + tcg_temp_free_i32(t2); + + if (a->ra != 15) { + t2 = load_reg(s, a->ra); + gen_helper_add_setq(t1, cpu_env, t1, t2); + tcg_temp_free_i32(t2); + } + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_SMLAD(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, false, false); +} + +static bool trans_SMLADX(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, true, false); +} + +static bool trans_SMLSD(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, false, true); +} + +static bool trans_SMLSDX(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, true, true); +} + +static bool op_smlald(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub) +{ + TCGv_i32 t1, t2; + TCGv_i64 l1, l2; + + if (!ENABLE_ARCH_6) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + if (m_swap) { + gen_swap_half(t2); + } + gen_smul_dual(t1, t2); + + l1 = tcg_temp_new_i64(); + l2 = tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(l1, t1); + tcg_gen_ext_i32_i64(l2, t2); + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); + + if (sub) { + tcg_gen_sub_i64(l1, l1, l2); + } else { + tcg_gen_add_i64(l1, l1, l2); + } + tcg_temp_free_i64(l2); + + gen_addq(s, l1, a->ra, a->rd); + gen_storeq_reg(s, a->ra, a->rd, l1); + tcg_temp_free_i64(l1); + return true; +} + +static bool trans_SMLALD(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, false, false); +} + +static bool trans_SMLALDX(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, true, false); +} + +static bool trans_SMLSLD(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, false, true); +} + +static bool trans_SMLSLDX(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, true, true); +} + +static bool op_smmla(DisasContext *s, arg_rrrr *a, bool round, bool sub) +{ + TCGv_i32 t1, t2; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + tcg_gen_muls2_i32(t2, t1, t1, t2); + + if (a->ra != 15) { + TCGv_i32 t3 = load_reg(s, a->ra); + if (sub) { + tcg_gen_sub_i32(t1, t1, t3); + } else { + tcg_gen_add_i32(t1, t1, t3); + } + tcg_temp_free_i32(t3); + } + if (round) { + tcg_gen_shri_i32(t2, t2, 31); + tcg_gen_add_i32(t1, t1, t2); + } + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_SMMLA(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, false, false); +} + +static bool trans_SMMLAR(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, true, false); +} + +static bool trans_SMMLS(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, false, true); +} + +static bool trans_SMMLSR(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, true, true); +} + +static bool op_div(DisasContext *s, arg_rrr *a, bool u) +{ + TCGv_i32 t1, t2; + + if (s->thumb + ? !dc_isar_feature(thumb_div, s) + : !dc_isar_feature(arm_div, s)) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + if (u) { + gen_helper_udiv(t1, t1, t2); + } else { + gen_helper_sdiv(t1, t1, t2); + } + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_SDIV(DisasContext *s, arg_rrr *a) +{ + return op_div(s, a, false); +} + +static bool trans_UDIV(DisasContext *s, arg_rrr *a) +{ + return op_div(s, a, true); +} + /* * Legacy decoder. */ static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, rm, rs, rn, rd; + unsigned int cond, val, op1, i, rn, rd; TCGv_i32 tmp; TCGv_i32 tmp2; - TCGv_i32 tmp3; TCGv_i32 addr; - TCGv_i64 tmp64; /* M variants do not implement ARM mode; this must raise the INVSTATE * UsageFault exception. @@ -9736,148 +9935,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) switch(op1) { case 0x0: case 0x1: - /* multiplies, extra load/stores */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - break; case 0x4: case 0x5: - goto do_ldst; case 0x6: case 0x7: - if (insn & (1 << 4)) { - ARCH(6); - /* Armv6 Media instructions. */ - rm = insn & 0xf; - rn = (insn >> 16) & 0xf; - rd = (insn >> 12) & 0xf; - rs = (insn >> 8) & 0xf; - switch ((insn >> 23) & 3) { - case 0: /* Parallel add/subtract. */ - /* Done by decodetree */ - goto illegal_op; - case 1: - /* Halfword pack, [US]SAT, [US]SAT16, SEL, REV et al */ - /* Done by decodetree */ - goto illegal_op; - case 2: /* Multiplies (Type 3). */ - switch ((insn >> 20) & 0x7) { - case 5: - if (((insn >> 6) ^ (insn >> 7)) & 1) { - /* op2 not 00x or 11x : UNDEF */ - goto illegal_op; - } - /* Signed multiply most significant [accumulate]. - (SMMUL, SMMLA, SMMLS) */ - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rs); - tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2); - - if (rd != 15) { - tmp3 = load_reg(s, rd); - if (insn & (1 << 6)) { - tcg_gen_sub_i32(tmp, tmp, tmp3); - } else { - tcg_gen_add_i32(tmp, tmp, tmp3); - } - tcg_temp_free_i32(tmp3); - } - if (insn & (1 << 5)) { - /* - * Adding 0x80000000 to the 64-bit quantity - * means that we have carry in to the high - * word when the low word has the high bit set. - */ - tcg_gen_shri_i32(tmp2, tmp2, 31); - tcg_gen_add_i32(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rn, tmp); - break; - case 0: - case 4: - /* SMLAD, SMUAD, SMLSD, SMUSD, SMLALD, SMLSLD */ - if (insn & (1 << 7)) { - goto illegal_op; - } - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rs); - if (insn & (1 << 5)) - gen_swap_half(tmp2); - gen_smul_dual(tmp, tmp2); - if (insn & (1 << 22)) { - /* smlald, smlsld */ - TCGv_i64 tmp64_2; - - tmp64 = tcg_temp_new_i64(); - tmp64_2 = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_gen_ext_i32_i64(tmp64_2, tmp2); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - if (insn & (1 << 6)) { - tcg_gen_sub_i64(tmp64, tmp64, tmp64_2); - } else { - tcg_gen_add_i64(tmp64, tmp64, tmp64_2); - } - tcg_temp_free_i64(tmp64_2); - gen_addq(s, tmp64, rd, rn); - gen_storeq_reg(s, rd, rn, tmp64); - tcg_temp_free_i64(tmp64); - } else { - /* smuad, smusd, smlad, smlsd */ - if (insn & (1 << 6)) { - /* This subtraction cannot overflow. */ - tcg_gen_sub_i32(tmp, tmp, tmp2); - } else { - /* This addition cannot overflow 32 bits; - * however it may overflow considered as a - * signed operation, in which case we must set - * the Q flag. - */ - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - if (rd != 15) - { - tmp2 = load_reg(s, rd); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rn, tmp); - } - break; - case 1: - case 3: - /* SDIV, UDIV */ - if (!dc_isar_feature(arm_div, s)) { - goto illegal_op; - } - if (((insn >> 5) & 7) || (rd != 15)) { - goto illegal_op; - } - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rs); - if (insn & (1 << 21)) { - gen_helper_udiv(tmp, tmp, tmp2); - } else { - gen_helper_sdiv(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rn, tmp); - break; - default: - goto illegal_op; - } - break; - case 3: - /* USAD, BFI, BFC, SBFX, UBFX */ - /* Done by decodetree */ - goto illegal_op; - } - break; - } - do_ldst: /* All done in decodetree. Reach here for illegal ops. */ goto illegal_op; case 0x08: @@ -10102,9 +10163,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) uint32_t rd, rn, rm, rs; TCGv_i32 tmp; TCGv_i32 tmp2; - TCGv_i32 tmp3; TCGv_i32 addr; - TCGv_i64 tmp64; int op; /* @@ -10365,119 +10424,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 2: /* SIMD add/subtract, in decodetree */ case 3: /* Other data processing, in decodetree */ goto illegal_op; - case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */ - switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32 */ - case 1: /* 16 x 16 -> 32 */ - case 3: /* 32 * 16 -> 32msb */ - case 7: /* Unsigned sum of absolute differences. */ - /* in decodetree */ - goto illegal_op; - case 2: /* Dual multiply add. */ - case 4: /* Dual multiply subtract. */ - case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - break; - } - op = (insn >> 4) & 0xf; - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - switch ((insn >> 20) & 7) { - case 2: /* Dual multiply add. */ - case 4: /* Dual multiply subtract. */ - if (op) - gen_swap_half(tmp2); - gen_smul_dual(tmp, tmp2); - if (insn & (1 << 22)) { - /* This subtraction cannot overflow. */ - tcg_gen_sub_i32(tmp, tmp, tmp2); - } else { - /* This addition cannot overflow 32 bits; - * however it may overflow considered as a signed - * operation, in which case we must set the Q flag. - */ - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - if (rs != 15) - { - tmp2 = load_reg(s, rs); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; - case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ - tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2); - if (rs != 15) { - tmp3 = load_reg(s, rs); - if (insn & (1 << 20)) { - tcg_gen_add_i32(tmp, tmp, tmp3); - } else { - tcg_gen_sub_i32(tmp, tmp, tmp3); - } - tcg_temp_free_i32(tmp3); - } - if (insn & (1 << 4)) { - /* - * Adding 0x80000000 to the 64-bit quantity - * means that we have carry in to the high - * word when the low word has the high bit set. - */ - tcg_gen_shri_i32(tmp2, tmp2, 31); - tcg_gen_add_i32(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - break; - } - store_reg(s, rd, tmp); - break; - case 6: case 7: /* 64-bit multiply, Divide. */ - op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70); - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - if ((op & 0x50) == 0x10) { - /* sdiv, udiv */ - if (!dc_isar_feature(thumb_div, s)) { - goto illegal_op; - } - if (op & 0x20) - gen_helper_udiv(tmp, tmp, tmp2); - else - gen_helper_sdiv(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((op & 0xe) == 0xc) { - /* Dual multiply accumulate long. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - goto illegal_op; - } - if (op & 1) - gen_swap_half(tmp2); - gen_smul_dual(tmp, tmp2); - if (op & 0x10) { - tcg_gen_sub_i32(tmp, tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - /* BUGFIX */ - tmp64 = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_temp_free_i32(tmp); - gen_addq(s, tmp64, rs, rd); - gen_storeq_reg(s, rs, rd, tmp64); - tcg_temp_free_i64(tmp64); - } else { - /* Signed/unsigned 64-bit multiply, in decodetree */ - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - break; + case 4: case 5: + /* 32-bit multiply. Sum of absolute differences, in decodetree */ + goto illegal_op; + case 6: case 7: /* 64-bit multiply, Divide, in decodetree */ + goto illegal_op; } break; case 6: case 7: case 14: case 15: diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 4990eb3839..d7a333b90b 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -486,3 +486,25 @@ REV .... 0110 1011 1111 .... 1111 0011 .... @rdm REV16 .... 0110 1011 1111 .... 1111 1011 .... @rdm REVSH .... 0110 1111 1111 .... 1111 1011 .... @rdm RBIT .... 0110 1111 1111 .... 1111 0011 .... @rdm + +# Signed multiply, signed and unsigned divide + +@rdmn ---- .... .... rd:4 .... rm:4 .... rn:4 &rrr + +SMLAD .... 0111 0000 .... .... .... 0001 .... @rdamn +SMLADX .... 0111 0000 .... .... .... 0011 .... @rdamn +SMLSD .... 0111 0000 .... .... .... 0101 .... @rdamn +SMLSDX .... 0111 0000 .... .... .... 0111 .... @rdamn + +SDIV .... 0111 0001 .... 1111 .... 0001 .... @rdmn +UDIV .... 0111 0011 .... 1111 .... 0001 .... @rdmn + +SMLALD .... 0111 0100 .... .... .... 0001 .... @rdamn +SMLALDX .... 0111 0100 .... .... .... 0011 .... @rdamn +SMLSLD .... 0111 0100 .... .... .... 0101 .... @rdamn +SMLSLDX .... 0111 0100 .... .... .... 0111 .... @rdamn + +SMMLA .... 0111 0101 .... .... .... 0001 .... @rdamn +SMMLAR .... 0111 0101 .... .... .... 0011 .... @rdamn +SMMLS .... 0111 0101 .... .... .... 1101 .... @rdamn +SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 71f6d728f2..677acb698d 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -228,6 +228,24 @@ SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm # usad8 is usada8 w/ ra=15 USADA8 1111 1011 0111 .... .... .... 0000 .... @rnadm +SMLAD 1111 1011 0010 .... .... .... 0000 .... @rnadm +SMLADX 1111 1011 0010 .... .... .... 0001 .... @rnadm +SMLSD 1111 1011 0100 .... .... .... 0000 .... @rnadm +SMLSDX 1111 1011 0100 .... .... .... 0001 .... @rnadm + +SMLALD 1111 1011 1100 .... .... .... 1100 .... @rnadm +SMLALDX 1111 1011 1100 .... .... .... 1101 .... @rnadm +SMLSLD 1111 1011 1101 .... .... .... 1100 .... @rnadm +SMLSLDX 1111 1011 1101 .... .... .... 1101 .... @rnadm + +SMMLA 1111 1011 0101 .... .... .... 0000 .... @rnadm +SMMLAR 1111 1011 0101 .... .... .... 0001 .... @rnadm +SMMLS 1111 1011 0110 .... .... .... 0000 .... @rnadm +SMMLSR 1111 1011 0110 .... .... .... 0001 .... @rnadm + +SDIV 1111 1011 1001 .... 1111 .... 1111 .... @rndm +UDIV 1111 1011 1011 .... 1111 .... 1111 .... @rndm + # Data-processing (two source registers) QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm From patchwork Mon Aug 19 21:37:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171698 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3553751ily; Mon, 19 Aug 2019 15:08:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqzPi/V0qcGVfQY0jKj21EC+6pqR96+oR1O1wvcRT08cglZBMVOzMVrUp20FyCtUGh1TgnUI X-Received: by 2002:a50:89b4:: with SMTP id g49mr27641580edg.39.1566252530698; Mon, 19 Aug 2019 15:08:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566252530; cv=none; d=google.com; s=arc-20160816; b=Ibe59mtBryB9xKClFtDTXcsICQSQiwSxZOYOObTSQSXtvI1S1kDZnlQb6u3dAjY8od RZ3hnM+AQdIKwTIUIGM3i6WsFGDfQEMyPzsL9DiZVTc5Zd7S5+sG6jiZpawYQqp+KpMB 8HSHoeHwaKohhMbHY+pwHT29ng+fa7gwqLn0L2IRqMo+g3yaZkrmN63PbfDD973SL8VB lUu2xCqJEan2oLPR8Q7Sgn1J2mIZGNNO0+i8XSdCf7mHcjUKuuCoLTGtWV0fuag9ejgZ iEsD98+ygB0u+neX8be/btnTCI2IzEE14KPm0JBIAUD841AIA2nFdtLwiTuzO8YCm8+k MVSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=VezSzLCtFs9kY3Fe5wLKu5xLpiNSXhDdz7VdFtZV8bc=; b=aAwvoIHHrA1a/Dl9isjeLhoTgAJBJ5l9to3/3CtWeVUH0H5CHrAr63VZ6ZL9/4WKcG Z13WGDNKEBlPsvW7EO2BW3TRMtX+5QLH3vA9ykGrZEtz6qQpWZ2HHMJRkliZ7fwpOEPs yN8bhpt8rpS08axFjbvQG3HarNz0H7QHql6aM1xjAcrLCUmApxHs+rAEurxPUzHRxNAW 4hBLG0s4FTUwXvljKYBmqDhevoc0YNGS7cA7RR81mF2nHLlWdmRwikiIci81NVtPPAsU qbiLoMXjDck0eVIOjHTCnAXVlOZe+43/AA5JTOAU3pHovPjU9Kylk4GuFQLXXwb+Teqj WpDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ulv9UWqo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 26/68] target/arm: Convert MOVW, MOVT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 89 ++++++++++++++++-------------------------- target/arm/a32.decode | 6 +++ target/arm/t32.decode | 9 +++++ 3 files changed, 48 insertions(+), 56 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 7962ac49e6..81eae286e8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7841,6 +7841,34 @@ static bool trans_ADR(DisasContext *s, arg_ri *a) return true; } +static bool trans_MOVW(DisasContext *s, arg_MOVW *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_6T2) { + return false; + } + + tmp = tcg_const_i32(a->imm); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_MOVT(DisasContext *s, arg_MOVW *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_6T2) { + return false; + } + + tmp = load_reg(s, a->rd); + tcg_gen_ext16u_i32(tmp, tmp); + tcg_gen_ori_i32(tmp, tmp, a->imm << 16); + store_reg(s, a->rd, tmp); + return true; +} + /* * Multiply and multiply accumulate */ @@ -9649,7 +9677,7 @@ static bool trans_UDIV(DisasContext *s, arg_rrr *a) static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, rn, rd; + unsigned int cond, val, op1, i, rn; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -9898,26 +9926,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* fall back to legacy decoder */ if ((insn & 0x0f900000) == 0x03000000) { - if ((insn & (1 << 21)) == 0) { - ARCH(6T2); - rd = (insn >> 12) & 0xf; - val = ((insn >> 4) & 0xf000) | (insn & 0xfff); - if ((insn & (1 << 22)) == 0) { - /* MOVW */ - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, val); - } else { - /* MOVT */ - tmp = load_reg(s, rd); - tcg_gen_ext16u_i32(tmp, tmp); - tcg_gen_ori_i32(tmp, tmp, val << 16); - } - store_reg(s, rd, tmp); - } else { - /* MSR (immediate) and hints */ - /* All done in decodetree. Illegal ops already signalled. */ - g_assert_not_reached(); - } + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; } else if ((insn & 0x0f900000) == 0x01000000 && (insn & 0x00000090) != 0x00000090) { /* miscellaneous instructions */ @@ -10655,42 +10665,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) /* * 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx * - Data-processing (modified immediate, plain binary immediate) + * All in decodetree. */ - if (insn & (1 << 25)) { - /* - * 0b1111_0x1x_xxxx_0xxx_xxxx_xxxx - * - Data-processing (plain binary immediate) - */ - if (insn & (1 << 24)) { - /* Bitfield/Saturate, in decodetree */ - goto illegal_op; - } else { - imm = ((insn & 0x04000000) >> 15) - | ((insn & 0x7000) >> 4) | (insn & 0xff); - if (insn & (1 << 22)) { - /* 16-bit immediate. */ - imm |= (insn >> 4) & 0xf000; - if (insn & (1 << 23)) { - /* movt */ - tmp = load_reg(s, rd); - tcg_gen_ext16u_i32(tmp, tmp); - tcg_gen_ori_i32(tmp, tmp, imm << 16); - } else { - /* movw */ - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, imm); - } - store_reg(s, rd, tmp); - } else { - /* Add/sub 12-bit immediate, in decodetree */ - goto illegal_op; - } - } - } else { - /* Data-processing (modified immediate) */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } + goto illegal_op; } break; case 12: diff --git a/target/arm/a32.decode b/target/arm/a32.decode index d7a333b90b..341882e637 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -73,6 +73,12 @@ MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi +%imm16 16:4 0:12 +@mov16 ---- .... .... .... rd:4 ............ &ri imm=%imm16 + +MOVW .... 0011 0000 .... .... ............ @mov16 +MOVT .... 0011 0100 .... .... ............ @mov16 + # Data-processing (register-shifted register) @s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \ diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 677acb698d..f315fde0f4 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -150,6 +150,15 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12 } +# Move Wide + +%imm16_26_16_12_0 16:4 26:1 12:3 0:8 +@mov16 .... .... .... .... .... rd:4 .... .... \ + &ri imm=%imm16_26_16_12_0 + +MOVW 1111 0.10 0100 .... 0 ... .... ........ @mov16 +MOVT 1111 0.10 1100 .... 0 ... .... ........ @mov16 + # Saturate, bitfield @sat .... .... .. sh:1 . rn:4 . ... rd:4 .. . satimm:5 \ From patchwork Mon Aug 19 21:37:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171684 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3543101ily; Mon, 19 Aug 2019 14:57:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqxyGNnTt0ek5PWJId1IbB0fYt4YKY9Q83YnmDxovaPXBP8mKkAeblIlA7Wx+wz7vNFYNjwE X-Received: by 2002:a37:4b49:: with SMTP id y70mr21335199qka.447.1566251873997; Mon, 19 Aug 2019 14:57:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566251873; cv=none; d=google.com; s=arc-20160816; b=bidWWU202mv6iCP/ky/Q68LpHtBe6ZDgZ0Z9s//e3tm3NfuOYFTnYQZEfCAauRsWs+ /QajGHAyZJ13TFbDBawCX3G/Dnt3SYL4UHRsjT+9Y82yVdObsxwhoZvJ3sLp16z8HD8L ieYyyHP7NbZlKCuAUkPr7i2yHevYVKyi7K8pLuaE18SKEwjEomI1RonjKQoEw2+okmQ9 dnYJU4wyIRY2y2q67EpQnLWuwpbRHtzx8epfLmY99JSsFP6cP9la6IXcOsxwPMK+7be6 05pdB8c8ySS1Ql/FvGJ8Qq+qY3bQxiieDDP9K2Fl43N7aiGbtfXyTFGU0gljPD+65pwS HikA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=E5jCqhd4j782M1OXjBueNYjMszsPuCY448GdoglEKE4=; b=ECWPfg7JBQkV2a5wEDc56e0JG0qV0Z+jsiyvkuZhjYKxEmR55iIaOtWbsfawRQmFwS am6guUr9HJxT8zf+YLIyoB/X5lMMEd/ipdmQZy4zYHuzL4UrVLZ/pzObK0acAk9STLe5 ilHeaut0KegpYl+DHkYkxGD2gZQfZxDqs363d04hktzhBU/RJt/2FYD1/5hcM+HEBPoc XkjQYorsaHcewxsOMHn2SihtUcn/SXayxxJcEm2LJVwJg6koWPbwDVyJDpL/oIna5Mfq VrXxOIdkpmo5nEwv0iya04bQb4gyUgc+Y7al/fN/jlaQJeDWsdj4MvfDGooIm/tImZfy 1+Iw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SrpWT4l3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:14 -0700 Message-Id: <20190819213755.26175-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v2 27/68] target/arm: Convert LDM, STM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This includes a minor bug fix to LDM (user), which requires bit 21 to be 0, which means no writeback. Signed-off-by: Richard Henderson --- target/arm/translate.c | 426 ++++++++++++++++++++++------------------- target/arm/a32.decode | 6 + target/arm/t32.decode | 10 + 3 files changed, 241 insertions(+), 201 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 81eae286e8..4451adbb97 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9671,6 +9671,227 @@ static bool trans_UDIV(DisasContext *s, arg_rrr *a) return op_div(s, a, true); } +/* + * Block data transfer + */ + +static TCGv_i32 op_addr_block_pre(DisasContext *s, arg_ldst_block *a, int n) +{ + TCGv_i32 addr = load_reg(s, a->rn); + + if (a->b) { + if (a->i) { + /* pre increment */ + tcg_gen_addi_i32(addr, addr, 4); + } else { + /* pre decrement */ + tcg_gen_addi_i32(addr, addr, -(n * 4)); + } + } else if (!a->i && n != 1) { + /* post decrement */ + tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); + } + + if (s->v8m_stackcheck && a->rn == 13 && a->w) { + /* + * If the writeback is incrementing SP rather than + * decrementing it, and the initial SP is below the + * stack limit but the final written-back SP would + * be above, then then we must not perform any memory + * accesses, but it is IMPDEF whether we generate + * an exception. We choose to do so in this case. + * At this point 'addr' is the lowest address, so + * either the original SP (if incrementing) or our + * final SP (if decrementing), so that's what we check. + */ + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + return addr; +} + +static void op_addr_block_post(DisasContext *s, arg_ldst_block *a, + TCGv_i32 addr, int n) +{ + if (a->w) { + /* write back */ + if (!a->b) { + if (a->i) { + /* post increment */ + tcg_gen_addi_i32(addr, addr, 4); + } else { + /* post decrement */ + tcg_gen_addi_i32(addr, addr, -(n * 4)); + } + } else if (!a->i && n != 1) { + /* pre decrement */ + tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); + } + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } +} + +static bool op_stm(DisasContext *s, arg_ldst_block *a) +{ + int i, j, n, list, mem_idx; + bool user = a->u; + TCGv_i32 addr, tmp, tmp2; + + if (user) { + /* STM (user) */ + if (IS_USER(s)) { + /* Only usable in supervisor mode. */ + return false; + } + } + + list = a->list; + n = ctpop16(list); + /* TODO: test invalid n == 0 case */ + + addr = op_addr_block_pre(s, a, n); + mem_idx = get_mem_index(s); + + for (i = j = 0; i < 16; i++) { + if (!(list & (1 << i))) { + continue; + } + + if (user && i != 15) { + tmp = tcg_temp_new_i32(); + tmp2 = tcg_const_i32(i); + gen_helper_get_user_reg(tmp, cpu_env, tmp2); + tcg_temp_free_i32(tmp2); + } else { + tmp = load_reg(s, i); + } + gen_aa32_st32(s, tmp, addr, mem_idx); + tcg_temp_free_i32(tmp); + + /* No need to add after the last transfer. */ + if (++j != n) { + tcg_gen_addi_i32(addr, addr, 4); + } + } + + op_addr_block_post(s, a, addr, n); + return true; +} + +static bool trans_STM(DisasContext *s, arg_ldst_block *a) +{ + return op_stm(s, a); +} + +static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a) +{ + /* Writeback register in register list is UNPREDICATABLE for T32. */ + if (a->w && (a->list & (1 << a->rn))) { + return false; + } + return op_stm(s, a); +} + +static bool do_ldm(DisasContext *s, arg_ldst_block *a) +{ + int i, j, n, list, mem_idx; + bool loaded_base; + bool user = a->u; + bool exc_return = false; + TCGv_i32 addr, tmp, tmp2, loaded_var; + + if (user) { + /* LDM (user), LDM (exception return) */ + if (IS_USER(s)) { + /* Only usable in supervisor mode. */ + return false; + } + if (extract32(a->list, 15, 1)) { + exc_return = true; + user = false; + } else { + /* LDM (user) does not allow writeback. */ + if (a->w) { + return false; + } + } + } + + list = a->list; + n = ctpop16(list); + /* TODO: test invalid n == 0 case */ + + addr = op_addr_block_pre(s, a, n); + mem_idx = get_mem_index(s); + loaded_base = false; + loaded_var = NULL; + + for (i = j = 0; i < 16; i++) { + if (!(list & (1 << i))) { + continue; + } + + tmp = tcg_temp_new_i32(); + gen_aa32_ld32u(s, tmp, addr, mem_idx); + if (user) { + tmp2 = tcg_const_i32(i); + gen_helper_set_user_reg(cpu_env, tmp2, tmp); + tcg_temp_free_i32(tmp2); + tcg_temp_free_i32(tmp); + } else if (i == a->rn) { + loaded_var = tmp; + loaded_base = true; + } else if (i == 15 && exc_return) { + store_pc_exc_ret(s, tmp); + } else { + store_reg_from_load(s, i, tmp); + } + + /* No need to add after the last transfer. */ + if (++j != n) { + tcg_gen_addi_i32(addr, addr, 4); + } + } + + op_addr_block_post(s, a, addr, n); + + if (loaded_base) { + store_reg(s, a->rn, loaded_var); + } + + if (exc_return) { + /* Restore CPSR from SPSR. */ + tmp = load_cpu_field(spsr); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_cpsr_write_eret(cpu_env, tmp); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } + tcg_temp_free_i32(tmp); + /* Must exit loop to check un-masked IRQs */ + s->base.is_jmp = DISAS_EXIT; + } + return true; +} + +static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a) +{ + return do_ldm(s, a); +} + +static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) +{ + /* Writeback register in register list is UNPREDICATABLE for T32. */ + if (a->w && (a->list & (1 << a->rn))) { + return false; + } + return do_ldm(s, a); +} + /* * Legacy decoder. */ @@ -9949,142 +10170,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) case 0x5: case 0x6: case 0x7: - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; case 0x08: case 0x09: - { - int j, n, loaded_base; - bool exc_return = false; - bool is_load = extract32(insn, 20, 1); - bool user = false; - TCGv_i32 loaded_var; - /* load/store multiple words */ - /* XXX: store correct base if write back */ - if (insn & (1 << 22)) { - /* LDM (user), LDM (exception return) and STM (user) */ - if (IS_USER(s)) - goto illegal_op; /* only usable in supervisor mode */ - - if (is_load && extract32(insn, 15, 1)) { - exc_return = true; - } else { - user = true; - } - } - rn = (insn >> 16) & 0xf; - addr = load_reg(s, rn); - - /* compute total size */ - loaded_base = 0; - loaded_var = NULL; - n = 0; - for (i = 0; i < 16; i++) { - if (insn & (1 << i)) - n++; - } - /* XXX: test invalid n == 0 case ? */ - if (insn & (1 << 23)) { - if (insn & (1 << 24)) { - /* pre increment */ - tcg_gen_addi_i32(addr, addr, 4); - } else { - /* post increment */ - } - } else { - if (insn & (1 << 24)) { - /* pre decrement */ - tcg_gen_addi_i32(addr, addr, -(n * 4)); - } else { - /* post decrement */ - if (n != 1) - tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); - } - } - j = 0; - for (i = 0; i < 16; i++) { - if (insn & (1 << i)) { - if (is_load) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (user) { - tmp2 = tcg_const_i32(i); - gen_helper_set_user_reg(cpu_env, tmp2, tmp); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - } else if (i == rn) { - loaded_var = tmp; - loaded_base = 1; - } else if (i == 15 && exc_return) { - store_pc_exc_ret(s, tmp); - } else { - store_reg_from_load(s, i, tmp); - } - } else { - /* store */ - if (i == 15) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, read_pc(s)); - } else if (user) { - tmp = tcg_temp_new_i32(); - tmp2 = tcg_const_i32(i); - gen_helper_get_user_reg(tmp, cpu_env, tmp2); - tcg_temp_free_i32(tmp2); - } else { - tmp = load_reg(s, i); - } - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - j++; - /* no need to add after the last transfer */ - if (j != n) - tcg_gen_addi_i32(addr, addr, 4); - } - } - if (insn & (1 << 21)) { - /* write back */ - if (insn & (1 << 23)) { - if (insn & (1 << 24)) { - /* pre increment */ - } else { - /* post increment */ - tcg_gen_addi_i32(addr, addr, 4); - } - } else { - if (insn & (1 << 24)) { - /* pre decrement */ - if (n != 1) - tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); - } else { - /* post decrement */ - tcg_gen_addi_i32(addr, addr, -(n * 4)); - } - } - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - if (loaded_base) { - store_reg(s, rn, loaded_var); - } - if (exc_return) { - /* Restore CPSR from SPSR. */ - tmp = load_cpu_field(spsr); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_cpsr_write_eret(cpu_env, tmp); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); - } - tcg_temp_free_i32(tmp); - /* Must exit loop to check un-masked IRQs */ - s->base.is_jmp = DISAS_EXIT; - } - } - break; + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0xa: case 0xb: { @@ -10351,73 +10440,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) insn & (1 << 21)); } } else { - int i, loaded_base = 0; - TCGv_i32 loaded_var; - bool wback = extract32(insn, 21, 1); - /* Load/store multiple. */ - addr = load_reg(s, rn); - offset = 0; - for (i = 0; i < 16; i++) { - if (insn & (1 << i)) - offset += 4; - } - - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, -offset); - } - - if (s->v8m_stackcheck && rn == 13 && wback) { - /* - * If the writeback is incrementing SP rather than - * decrementing it, and the initial SP is below the - * stack limit but the final written-back SP would - * be above, then then we must not perform any memory - * accesses, but it is IMPDEF whether we generate - * an exception. We choose to do so in this case. - * At this point 'addr' is the lowest address, so - * either the original SP (if incrementing) or our - * final SP (if decrementing), so that's what we check. - */ - gen_helper_v8m_stackcheck(cpu_env, addr); - } - - loaded_var = NULL; - for (i = 0; i < 16; i++) { - if ((insn & (1 << i)) == 0) - continue; - if (insn & (1 << 20)) { - /* Load. */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i == rn) { - loaded_var = tmp; - loaded_base = 1; - } else { - store_reg_from_load(s, i, tmp); - } - } else { - /* Store. */ - tmp = load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_gen_addi_i32(addr, addr, 4); - } - if (loaded_base) { - store_reg(s, rn, loaded_var); - } - if (wback) { - /* Base register writeback. */ - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, -offset); - } - /* Fault if writeback register is in register list. */ - if (insn & (1 << rn)) - goto illegal_op; - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } + /* Load/store multiple, in decodetree */ + goto illegal_op; } } break; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 341882e637..1267a689e2 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -40,6 +40,7 @@ &mrs_bank rd r sysm &ldst_rr p w u rn rt rm shimm shtype &ldst_ri p w u rn rt imm +&ldst_block rn i b u w list &strex rn rd rt rt2 imm &ldrex rn rt rt2 imm &bfx rd rn lsb widthm1 @@ -514,3 +515,8 @@ SMMLA .... 0111 0101 .... .... .... 0001 .... @rdamn SMMLAR .... 0111 0101 .... .... .... 0011 .... @rdamn SMMLS .... 0111 0101 .... .... .... 1101 .... @rdamn SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn + +# Block data transfer + +STM ---- 100 b:1 i:1 u:1 w:1 0 rn:4 list:16 &ldst_block +LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block diff --git a/target/arm/t32.decode b/target/arm/t32.decode index f315fde0f4..f1e2b934f8 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -37,6 +37,7 @@ &mrs_bank !extern rd r sysm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm +&ldst_block !extern rn i b u w list &strex !extern rn rd rt rt2 imm &ldrex !extern rn rt rt2 imm &bfx !extern rd rn lsb widthm1 @@ -563,3 +564,12 @@ SXTAB16 1111 1010 0010 .... 1111 .... 10.. .... @rrr_rot UXTAB16 1111 1010 0011 .... 1111 .... 10.. .... @rrr_rot SXTAB 1111 1010 0100 .... 1111 .... 10.. .... @rrr_rot UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot + +# Load/store multiple + +@ldstm .... .... .. w:1 . rn:4 list:16 &ldst_block u=0 + +STM_t32 1110 1000 10.0 .... ................ @ldstm i=1 b=0 +STM_t32 1110 1001 00.0 .... ................ @ldstm i=0 b=1 +LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0 +LDM_t32 1110 1001 00.1 .... ................ @ldstm i=0 b=1 From patchwork Mon Aug 19 21:37:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171681 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3542032ily; Mon, 19 Aug 2019 14:56:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqyFUUfjck92UvBWLFxB2tgyh2NrJwIzv/HIHB+bWhcpv2381ddC5UclDVXj7xx3HXtH3vI4 X-Received: by 2002:a17:906:504e:: with SMTP id e14mr20227146ejk.204.1566251771544; Mon, 19 Aug 2019 14:56:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566251771; cv=none; d=google.com; s=arc-20160816; b=b8O0VJGkBABqFpe5iu5w2q35dskXW7Mg42EYVrcxfJw4XP+LdLmYqoEtkezAJ3+5Ne CWt5VnJtTNNE7LC7G2CUTzNNG44DRA1UmnATkLnv1hwfNIp+HraUPUPh/b9RO6BprJSP ficXQ4RtYP4KNAeLiMdRw4fzKyxzK37fQKNtVoWoEKi/TOtPaUOnkfL2kKG2AIPSqaP6 /RKRTPDYjIhkESoFrCcecUub3RaAnIkpcFeSorzqMh+olrFmbxtiRqzBXku9xBjhunpO v5V3ls5MsDimbNtPpueKw5uwYgDNE/UoGfsqlafurNfT+x/Gzpc9sajhudVRGIp0xpQ9 vSkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=cT5iUCtc/TpahCb9mQHDGpDMCKYLz7wFvW1IJP8R1rM=; b=VcZx99SawAe/ap4mhRTRPat8p2KzkCHYW+mXGppmNMFVj0NE5i7qZYgmzyXh5S+QTS 1Jvgk97fRdmHT+jyR83eqwRLmEe1h4e7Ne/qja5hQ4voYmMlL3yGKKE6rUlxM0vTXAvH VCHyeAG8+ev4z8nswNKCav62z7QUlcuKgVXv3hMJ1pe91m/J1HGsjXrXnY3SaeApR08T MtIoPQ51iguXadHQFEEYRP8GensoljVhjJbnu1lZFR5VQSqH+dFWJhSz5UXP2oF/FRIM K/Y77JBgb7frabPEZyz4krbqz7PKclbupttrluzDwDq3+duq63PM7uJUCt3G319Vt32H 13NQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Lt6jyPRX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:15 -0700 Message-Id: <20190819213755.26175-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v2 28/68] target/arm: Diagnose writeback register in list for LDM for v7 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Prior to v7, for the A32 encoding, this operation wrote an UNKNOWN value back to the base register. Starting in v7 this is UNPREDICTABLE. Signed-off-by: Richard Henderson --- target/arm/translate.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 4451adbb97..29e2eae441 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9880,6 +9880,14 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a) static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a) { + /* + * Writeback register in register list is UNPREDICATABLE + * for ArchVersion() >= 7. Prior to v7, A32 would write + * an UNKNOWN value to the base register. + */ + if (ENABLE_ARCH_7 && a->w && (a->list & (1 << a->rn))) { + return false; + } return do_ldm(s, a); } From patchwork Mon Aug 19 21:37:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171680 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3541075ily; Mon, 19 Aug 2019 14:54:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqyo2aOUOGEuxDWmWLhKNMlkxiah1RxIAscZGEiOImpcnoj4jeI3Rg2Mh3kWgAuSRAn0/w/2 X-Received: by 2002:a05:620a:78f:: with SMTP id 15mr21764735qka.441.1566251685226; Mon, 19 Aug 2019 14:54:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566251685; cv=none; d=google.com; s=arc-20160816; b=InHErY7bB6WHbZRsKR16KfA3YhnQz2ggAMa8jhyrPrRc1UTVpeGHiA9AUj3srrGVcN sOGH7EZJ499tRApTT6Q6w6WDlIJAFV/fYhyOzGCvD1mjpy5d+wRjor9JYniafDBfq85I 5oRZZIxMSgE3Wgh2OY856x552/aYkwLY0OSBxAjBBGlSjX/OEfTk9WKpIq6wVNk9H5+4 VuD7cNRnNIM7Uxr7M7YXFN5mnJ5iU76ycEUFiLyOXuJJTX/EMckELgqJikK+9HZCoo5O kJmaKEND/50XG+OSdMAfCR2SmYFnJm+7yibn1BeX2vEH7mgPtndxZ+8BOcBN/OXPf3l+ zMMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=PE2YkC2uYnkrGF/f+RQwnN2RH8jlq2MEkPtJdHa8VHQ=; b=BAhTEtgf7uqjrBQ4UPHZnX9N46CxytfsBM1fpLXUbqdOs6AW9LOrbBQvGxh9oLpyv8 HmvVidq9Sj0kxmuyDQhAKdqXiWqbQ1HhWjW4H9/YGkibIfuGqAddGDB0BGWMSWY7P1Jq 2SkyeCKraPtB+5yNDwKryfbLBS4m1ZESlFpJoPMIooNEDcY0loWUChKUcTI0vFVis1jY /ztZmeetIC63elSsEGoCYc8CK2A2ibsP38ldGIoxlfWKL19R1EriB9q2l104bk9/HyxK Zbm+P0FxoVybT60ASzN0ldboUVDXc3JGspL9umuq/1/v5n5Y4NGDaHKKiYZbif/ntLjT g31g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=t8oNyn9Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:16 -0700 Message-Id: <20190819213755.26175-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v2 29/68] target/arm: Diagnose too few registers in list for LDM/STM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This has been a TODO item for quite a while. The minimum bit count for A32 and T16 is 1, and for T32 is 2. Signed-off-by: Richard Henderson --- target/arm/translate.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 29e2eae441..1792bb7abd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9733,7 +9733,7 @@ static void op_addr_block_post(DisasContext *s, arg_ldst_block *a, } } -static bool op_stm(DisasContext *s, arg_ldst_block *a) +static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n) { int i, j, n, list, mem_idx; bool user = a->u; @@ -9749,7 +9749,9 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a) list = a->list; n = ctpop16(list); - /* TODO: test invalid n == 0 case */ + if (n < min_n) { + return false; + } addr = op_addr_block_pre(s, a, n); mem_idx = get_mem_index(s); @@ -9782,7 +9784,8 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a) static bool trans_STM(DisasContext *s, arg_ldst_block *a) { - return op_stm(s, a); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return op_stm(s, a, 1); } static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a) @@ -9791,10 +9794,11 @@ static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a) if (a->w && (a->list & (1 << a->rn))) { return false; } - return op_stm(s, a); + /* BitCount(list) < 2 is UNPREDICTABLE */ + return op_stm(s, a, 2); } -static bool do_ldm(DisasContext *s, arg_ldst_block *a) +static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) { int i, j, n, list, mem_idx; bool loaded_base; @@ -9821,7 +9825,9 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a) list = a->list; n = ctpop16(list); - /* TODO: test invalid n == 0 case */ + if (n < min_n) { + return false; + } addr = op_addr_block_pre(s, a, n); mem_idx = get_mem_index(s); @@ -9888,7 +9894,8 @@ static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a) if (ENABLE_ARCH_7 && a->w && (a->list & (1 << a->rn))) { return false; } - return do_ldm(s, a); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return do_ldm(s, a, 1); } static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) @@ -9897,7 +9904,8 @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) if (a->w && (a->list & (1 << a->rn))) { return false; } - return do_ldm(s, a); + /* BitCount(list) < 2 is UNPREDICTABLE */ + return do_ldm(s, a, 2); } /* From patchwork Mon Aug 19 21:37:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171686 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3544520ily; Mon, 19 Aug 2019 15:00:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqw1hiSFL+LF5SqnfNz+0W53UzwFnYCFbezbT4E9jEt3LJtWWqp3cwN85YTPNisIRzo3VCqy X-Received: by 2002:aed:2b01:: with SMTP id p1mr23368200qtd.33.1566252003941; Mon, 19 Aug 2019 15:00:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566252003; cv=none; d=google.com; s=arc-20160816; b=oWhhcuzV8CljEE4Zk1FRX15QGKOPK7OSyR544Z1VBqiKqzZ+oCItIGRd4+akxO58KR gKICNwWzUKPeICvZ0DPa2gAJgDNyTKRNs54ZTss8fiLkwOZ4wamno1vgUC+2AyH/hW4t 3vFU54QQvw/y52J4js8UZPrXvGhj4kpdWnyo8EGSJuBqYrYMcOkxwt8i0KUNC+q2qaRL fLbz4Bqw4UQyWX1OZi8Gw2il8glAKyjnWb5ZtdjDvNI6aOCYpABgi+xeCAHq034cO6nO D5HUAgpPKDmQEv3PRqyKlUiG/bRxV5guw+YpLZcXjzlYH8XXlT9289X3m/NyRHOZSGbY p2Zg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=VR7o5gOGgy8kJ+DLCf8SWN2RwI2Evgg2aslGYIJEmas=; b=MIez/daH1QwQT93IuY+Im76HQmaQWSVr1LmAJ7+cE1RupyssOPjJt3zFATqPy3Q3pM O777ekKvTlpc/QBRajI99MtGPjv/Ew66haGZGMGthl9ES89k6ueK5+TReqvXai/zS7bc LT4vLqUi7kZ3lK83K97FjRuis0XjK9fQqRZhaGQbrxK+5imvfLqmv/oFEtyVgBYpYsSp Tzu88DQXvEq3hL/cGgpGVP0eMWXI+kyeHsnUCskaFoTlIPaqDA9aYqpFn34L3OOr+b5L 41/V3um9nFoc43Oo5SWeJm4XGDjf+cVcatEBII9ecn3wxvaLnenX8zhJqs0OV5T8Woc/ M4fw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zoOabdEN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:17 -0700 Message-Id: <20190819213755.26175-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v2 30/68] target/arm: Diagnose base == pc for LDM/STM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have been using store_reg and not store_reg_for_load when writing back a loaded value into the base register. At first glance this is incorrect when base == pc, however that case is UNPREDICTABLE. Signed-off-by: Richard Henderson --- target/arm/translate.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 1792bb7abd..09636aab4e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9752,6 +9752,10 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n) if (n < min_n) { return false; } + /* Using PC as the base register is UNPREDICTABLE. */ + if (a->rn == 15) { + return false; + } addr = op_addr_block_pre(s, a, n); mem_idx = get_mem_index(s); @@ -9828,6 +9832,10 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) if (n < min_n) { return false; } + /* Using PC as the base register is UNPREDICTABLE. */ + if (a->rn == 15) { + return false; + } addr = op_addr_block_pre(s, a, n); mem_idx = get_mem_index(s); @@ -9864,6 +9872,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) op_addr_block_post(s, a, addr, n); if (loaded_base) { + /* Note that we reject base == pc above. */ store_reg(s, a->rn, loaded_var); } From patchwork Mon Aug 19 21:37:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171685 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3543767ily; Mon, 19 Aug 2019 14:58:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqz5aDKFedaXtZGV804tMMioFGFXG6vc9fA9pkEp2L+ld/WFIT8DlZAkYYa3ulurHTLx3H3t X-Received: by 2002:a05:6402:1450:: with SMTP id d16mr27794147edx.198.1566251936785; Mon, 19 Aug 2019 14:58:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566251936; cv=none; d=google.com; s=arc-20160816; b=PAloW8/v9aXgAPQi13Ts6yTqI4QQ+tUw42v03z7k0AeaHhWPyRs9IhtVOgetICstZP pQJDnKJUK92Z6HAUqlIuXW383w9q35EslC2c0UePpv/BeEWtZR+UPMPhFwqE0qtBa0Zu cyUi74nXVK4VNJzRGsS7Ej4PjKdv1eWigEzWD/SmnipX6/mcewH03phuyiefwGXcXBrP Va1MI07YtYpd5Z5tCHcvMYVtIXGyOUATe9VI/+2OayhbUuNtvdwKRpdVpAoQAblIXJ7d 88RU1WpxXT+Tnav8TiWSMGJovQ1g2MlognmPN8OKVPncfnJX06oiaqPFvnKS/YRHHVIz 5qzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=v9AR5e2vTyYPnkVwbheCeAc1mDx0MtVRV+9wSe0MQcA=; b=1DQsXFIxAGJZscooeCBVDXvBhRd1spDWlTaw12OWD/n1lYPbMC1QX7S/ErdnhcHswC SnzcsQss+yTsukBqmYEAn3mub3PjRwD5nuH57gpw1ejTjc2iGGmHfUflkmhTN1Srs8jB ZOgJX5oZr87b45sJJdDsSUFs+VVrR5O1D8DpWTyXeY0d2wzAkd8U9hyefBMagrqwhet5 Gh8obmWSgnbcJoq5CR3/aQgq/fpQcZqGIfuGKLeWAMUOGPqy2hMDXVByz1WHX9tq9qOC tj7etKEAn79WfOk4cEnfjOZ2jBdZ9/zqrMsqmWUV7msL5RSn4DOzBwevsBkG3d+VjN0d 62bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=wV4Onl44; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:18 -0700 Message-Id: <20190819213755.26175-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::531 Subject: [Qemu-devel] [PATCH v2 31/68] target/arm: Convert B, BL, BLX (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 133 +++++++++++++++-------------------- target/arm/a32-uncond.decode | 8 +++ target/arm/a32.decode | 8 +++ target/arm/t32.decode | 81 ++++++++++++--------- 4 files changed, 123 insertions(+), 107 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 09636aab4e..6b7b3df685 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7523,6 +7523,14 @@ static int t32_expandimm_imm(DisasContext *s, int x) return imm; } +static int t32_branch24(DisasContext *s, int x) +{ + /* Convert J1:J2 at x[22:21] to I2:I1, which involves I=J^~S. */ + x ^= !(x < 0) * (3 << 21); + /* Append the final zero. */ + return x << 1; +} + /* * Include the generated decoders. */ @@ -9917,13 +9925,56 @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) return do_ldm(s, a, 2); } +/* + * Branch, branch with link + */ + +static bool trans_B(DisasContext *s, arg_i *a) +{ + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + +static bool trans_B_cond_thumb(DisasContext *s, arg_ci *a) +{ + /* This has cond from encoding, required to be outside IT block. */ + if (a->cond >= 0xe) { + return false; + } + if (s->condexec_mask) { + unallocated_encoding(s); + return true; + } + arm_skip_unless(s, a->cond); + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + +static bool trans_BL(DisasContext *s, arg_i *a) +{ + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + +static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) +{ + /* For A32, ARCH(5) is checked near the start of the uncond block. */ + if (s->thumb && (a->imm & 2)) { + return false; + } + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_bx_im(s, (read_pc(s) & ~3) + a->imm + !s->thumb); + return true; +} + /* * Legacy decoder. */ static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, rn; + unsigned int cond, op1, i, rn; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -10091,21 +10142,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } gen_rfe(s, tmp, tmp2); return; - } else if ((insn & 0x0e000000) == 0x0a000000) { - /* branch link and change to thumb (blx ) */ - int32_t offset; - - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, s->base.pc_next); - store_reg(s, 14, tmp); - /* Sign-extend the 24-bit offset */ - offset = (((int32_t)insn) << 8) >> 8; - val = read_pc(s); - /* offset * 4 + bit24 * 2 + (thumb bit) */ - val += (offset << 2) | ((insn >> 23) & 2) | 1; - /* protected by ARCH(5); above, near the start of uncond block */ - gen_bx_im(s, val); - return; } else if ((insn & 0x0e000f00) == 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10197,23 +10233,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) case 0x7: case 0x08: case 0x09: - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; case 0xa: case 0xb: - { - int32_t offset; - - /* branch (and link) */ - if (insn & (1 << 24)) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, s->base.pc_next); - store_reg(s, 14, tmp); - } - offset = sextract32(insn << 2, 0, 26); - gen_jmp(s, read_pc(s) + offset); - } - break; + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0xc: case 0xd: case 0xe: @@ -10580,32 +10603,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) if (insn & (1 << 15)) { /* Branches, misc control. */ if (insn & 0x5000) { - /* Unconditional branch. */ - /* signextend(hw1[10:0]) -> offset[:12]. */ - offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff; - /* hw1[10:0] -> offset[11:1]. */ - offset |= (insn & 0x7ff) << 1; - /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22] - offset[24:22] already have the same value because of the - sign extension above. */ - offset ^= ((~insn) & (1 << 13)) << 10; - offset ^= ((~insn) & (1 << 11)) << 11; - - if (insn & (1 << 14)) { - /* Branch and link. */ - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); - } - - offset += read_pc(s); - if (insn & (1 << 12)) { - /* b/bl */ - gen_jmp(s, offset); - } else { - /* blx */ - offset &= ~(uint32_t)2; - /* thumb2 bx, no need to check */ - gen_bx_im(s, offset); - } + /* Unconditional branch, in decodetree */ + goto illegal_op; } else if (((insn >> 23) & 7) == 7) { /* Misc control */ if (insn & (1 << 13)) @@ -10691,24 +10690,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } } } else { - /* Conditional branch. */ - op = (insn >> 22) & 0xf; - /* Generate a conditional jump to next instruction. */ - arm_skip_unless(s, op); - - /* offset[11:1] = insn[10:0] */ - offset = (insn & 0x7ff) << 1; - /* offset[17:12] = insn[21:16]. */ - offset |= (insn & 0x003f0000) >> 4; - /* offset[31:20] = insn[26]. */ - offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11; - /* offset[18] = insn[13]. */ - offset |= (insn & (1 << 13)) << 5; - /* offset[19] = insn[11]. */ - offset |= (insn & (1 << 11)) << 8; - - /* jump to the offset */ - gen_jmp(s, read_pc(s) + offset); + /* Conditional branch, in decodetree */ + goto illegal_op; } } else { /* diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 8dee26d3b6..573ac2cf8e 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -21,3 +21,11 @@ # All insns that have 0xf in insn[31:28] are decoded here. # All of those that have a COND field in insn[31:28] are in a32.decode # + +&i !extern imm + +# Branch with Link and Exchange + +%imm24h 0:s24 24:1 !function=times_2 + +BLX_i 1111 101 . ........................ &i imm=%imm24h diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 1267a689e2..62c6f8562e 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -520,3 +520,11 @@ SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn STM ---- 100 b:1 i:1 u:1 w:1 0 rn:4 list:16 &ldst_block LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block + +# Branch, branch with link + +%imm26 0:s24 !function=times_4 +@branch ---- .... ........................ &i imm=%imm26 + +B .... 1010 ........................ @branch +BL .... 1011 ........................ @branch diff --git a/target/arm/t32.decode b/target/arm/t32.decode index f1e2b934f8..ebc92f2c28 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -284,47 +284,55 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm %msr_sysm 4:1 8:4 %mrs_sysm 4:1 16:4 %imm16_16_0 16:4 0:12 +%imm21 26:s1 11:1 13:1 16:6 0:11 !function=times_2 +&ci cond imm { + # Group insn[25:23] = 111, which is cond=111x for the branch below, + # or unconditional, which would be illegal for the branch. { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + # Hints + { + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 - # The canonical nop ends in 0000 0000, but the whole rest - # of the space is "reserved hint, behaves as nop". - NOP 1111 0011 1010 1111 1000 0000 ---- ---- - } - # Note that the v7m insn overlaps both the normal and banked insn. - { - MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ + # The canonical nop ends in 0000 0000, but the whole rest + # of the space is "reserved hint, behaves as nop". + NOP 1111 0011 1010 1111 1000 0000 ---- ---- + } + # Note that the v7m insn overlaps both the normal and banked insn. + { + MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ &mrs_bank sysm=%mrs_sysm - MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg - MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8 - } - { - MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \ + MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg + MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8 + } + { + MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \ &msr_bank sysm=%msr_sysm - MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg - MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 - } - BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r - { - # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as for - # every other encoding of SUBS. With v7VE, IMM=0 is redefined as ERET. - # The distinction between the two only matters for Hyp mode. - ERET 1111 0011 1101 1110 1000 1111 0000 0000 - SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ + MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg + MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 + } + BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r + { + # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as for + # every other encoding of SUBS. With v7VE, IMM=0 is redefined as ERET. + # The distinction between the two only matters for Hyp mode. + ERET 1111 0011 1101 1110 1000 1111 0000 0000 + SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ &s_rri_rot rot=0 s=1 rd=15 rn=14 - } - SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i - HVC 1111 0111 1110 .... 1000 .... .... .... \ + } + SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i + HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=%imm16_16_0 - UDF 1111 0111 1111 ---- 1010 ---- ---- ---- + UDF 1111 0111 1111 ---- 1010 ---- ---- ---- + } + B_cond_thumb 1111 0. cond:4 ...... 10.0 ............ &ci imm=%imm21 } # Load/store (register, immediate, literal) @@ -573,3 +581,12 @@ STM_t32 1110 1000 10.0 .... ................ @ldstm i=1 b=0 STM_t32 1110 1001 00.0 .... ................ @ldstm i=0 b=1 LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0 LDM_t32 1110 1001 00.1 .... ................ @ldstm i=0 b=1 + +# Branches + +%imm24 26:s1 13:1 11:1 16:10 0:11 !function=t32_branch24 +@branch24 ................................ &i imm=%imm24 + +B 1111 0. .......... 10.1 ............ @branch24 +BL 1111 0. .......... 11.1 ............ @branch24 +BLX_i 1111 0. .......... 11.0 ............ @branch24 From patchwork Mon Aug 19 21:37:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171691 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3548398ily; Mon, 19 Aug 2019 15:03:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqwnQw9mTW+igjvpLCHYP81rpdqVDACEcVUIzl1FB0Hs2hXvcTbbw3wcTl88hIy8bcaQPJOY X-Received: by 2002:aed:2b01:: with SMTP id p1mr23385756qtd.33.1566252211176; Mon, 19 Aug 2019 15:03:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566252211; cv=none; d=google.com; s=arc-20160816; b=JTr3Ph3Tc2P+CLHe0GWJrq0MQEqUx4FJE0TsV5NX+eWjaYNlkoNu6T7pLv5eA5fe9H 1WdDkMyceSpdGZR34YLJfunljrFHjJ7VwirRufuI3acNK60hVlEf0MPGpFK8xTwuFntH dK3tSlJSjyJOP1KHY0q/dAweglv81Q6lGQfRpKnbsjeaMxn6EV/sVocOoeuLkASvYLam ru2LWGMqTrfz/9657v1h0nCEK52CkJMGutrmectqWn1ldBSXW6T4yagjgm0j/LVK1lcD OV5ISQk39cV/KCR5ErJTBD8e1M2Men5XdYu6hcPTdgOuDizOF2GDFXuX9Zas0sRZCY3n dRww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=PQ+LqO+lz8aRvDtiE1Qc+qi0l6DF2tSTKskus1LdpN4=; b=HD10B5R10uwJu9+Vyvz4LH0plFUgugG/FEFZ95eXQZeAdfsESGaETzTVhks3sTYgbQ HfBWZbmiBrQfjPUsPTqNjbEyLx4o9XgEgGh5GGdlTT3fptxlUDMn61yQktaGFjplEDiO ZVPRRV6UKkPzyKRHR4zPF73LMaWeKkVFY2asN7HcwEAwAqLd1OgZkUrt4Paq/SvNNh36 wH2Ef7Mq+xA967ZE0e//6TGpTXWQcsdq2+fy5AmI3cWAkyZO+YATXEAXfFr4/J6o4+2o 3H3Iu9LE3tYBf8rLdVcWCLUtJnCJiynxoF6xvh45LARYLhsRJnwXV3kAn43S/o7qbE5T 9ddg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yJtSnyCn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 32/68] target/arm: Convert SVC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 19 +++++++++++++------ target/arm/a32.decode | 4 ++++ 2 files changed, 17 insertions(+), 6 deletions(-) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/translate.c b/target/arm/translate.c index 6b7b3df685..b6d8b7be8c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9968,6 +9968,18 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) return true; } +/* + * Supervisor call + */ + +static bool trans_SVC(DisasContext *s, arg_SVC *a) +{ + gen_set_pc_im(s, s->base.pc_next); + s->svc_imm = a->imm; + s->base.is_jmp = DISAS_SWI; + return true; +} + /* * Legacy decoder. */ @@ -10235,6 +10247,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) case 0x09: case 0xa: case 0xb: + case 0xf: /* All done in decodetree. Reach here for illegal ops. */ goto illegal_op; case 0xc: @@ -10250,12 +10263,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) goto illegal_op; } break; - case 0xf: - /* swi */ - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm = extract32(insn, 0, 24); - s->base.is_jmp = DISAS_SWI; - break; default: illegal_op: unallocated_encoding(s); diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 62c6f8562e..0bd952c069 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -528,3 +528,7 @@ LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block B .... 1010 ........................ @branch BL .... 1011 ........................ @branch + +# Supervisor call + +SVC ---- 1111 imm:24 &i From patchwork Mon Aug 19 21:37:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171696 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3551974ily; Mon, 19 Aug 2019 15:07:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqzSigcGYUteYSjdxKbJGH7TeBMduKtBvuQsPNfJTpL2nC+EHKdqpcijw2OoIxk5vLcj9l6K X-Received: by 2002:a37:4e4c:: with SMTP id c73mr23518042qkb.309.1566252423325; Mon, 19 Aug 2019 15:07:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566252423; cv=none; d=google.com; s=arc-20160816; b=HoLewYpvCK7Jr+6tZYyil5KoO0aZy/vg4axeXKwteYykorEC+Doh9344+hSezO6Vs8 k32nLtDltCIDSajCmCblOiKy1vhW2VEYjKVG6EO1LsiT3a7chbT6Jjz6yJmxEXu4B9aT cSruYWZ5BASByVKOFFjfsmvuHOgg/HguG1lV1CO/DgaJuwwnSj4Uo7++YF3GN92Lq8fv 4+2M0yoHGNW2A6+sVAOMml1KNdeFQVelHFIaiAQTw0BgIWYmUTKe/pks0xpUJ3wfcGie wV6oqS8VJOqT6wiWDjFjTnE+7iV/ZfYp4u71i1JSG1yCOC4bath9dlcr/fu8RE4MQ9rJ ulOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=sBLN1mbpyRVW7i8qjZto4S2aiB09EK81j9lCJDX6kUc=; b=Pvcxb7Yk2GY1tw2VDBHcHYHiCmUeMQrh+rKFzCKfPcDP7Px9Ts4rENVXriwCCmxa43 krdcqbfVKVIiTtd4QDOKqvmzdaNdwcrfLMvGhsN1srKf9yGrg71+kgb1pXVXnNvsKfqd 4buftnhA51TjOPelAHnGqc6uB3u8bljNqyKkQoC0xMhymoqVzalN/4cZsIGBgsTBMhRT dnUL8w098x1HdZahTufl5p8zL4gA3KZAbFBRh/sY70bZp1xUlDEfnXSf5QqwNno/GC5P hOwmw4bGKO+97MSFwoM1jFDS+PSSREHiNMQX7/zgQMbUcVuL49cdlw6mHMg/+ID4eQ8f i8lQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=upuuasOx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:20 -0700 Message-Id: <20190819213755.26175-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 33/68] target/arm: Convert RFE and SRS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 150 ++++++++++++++--------------------- target/arm/a32-uncond.decode | 8 ++ target/arm/t32.decode | 12 +++ 3 files changed, 81 insertions(+), 89 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index b6d8b7be8c..e268c5168d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9980,16 +9980,71 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) return true; } +/* + * Unconditional system instructions + */ + +static bool trans_RFE(DisasContext *s, arg_RFE *a) +{ + int32_t offset; + TCGv_i32 addr, t1, t2; + + if (IS_USER(s) || !ENABLE_ARCH_6) { + return false; + } + + addr = load_reg(s, a->rn); + + switch (a->pu) { + case 0: offset = -4; break; /* DA */ + case 1: offset = 0; break; /* IA */ + case 2: offset = -8; break; /* DB */ + case 3: offset = 4; break; /* IB */ + default: + g_assert_not_reached(); + } + tcg_gen_addi_i32(addr, addr, offset); + + /* Load PC into tmp and CPSR into tmp2. */ + t1 = tcg_temp_new_i32(); + gen_aa32_ld32u(s, t1, addr, get_mem_index(s)); + tcg_gen_addi_i32(addr, addr, 4); + t2 = tcg_temp_new_i32(); + gen_aa32_ld32u(s, t2, addr, get_mem_index(s)); + + if (a->w) { + /* Base writeback. */ + switch (a->pu) { + case 0: offset = -8; break; + case 1: offset = 4; break; + case 2: offset = -4; break; + case 3: offset = 0; break; + } + tcg_gen_addi_i32(addr, addr, offset); + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } + gen_rfe(s, t1, t2); + return true; +} + +static bool trans_SRS(DisasContext *s, arg_SRS *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + gen_srs(s, a->mode, a->pu, a->w); + return true; +} + /* * Legacy decoder. */ static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, op1, i, rn; - TCGv_i32 tmp; - TCGv_i32 tmp2; - TCGv_i32 addr; + unsigned int cond, op1; /* M variants do not implement ARM mode; this must raise the INVSTATE * UsageFault exception. @@ -10108,52 +10163,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) default: goto illegal_op; } - } else if ((insn & 0x0e5fffe0) == 0x084d0500) { - /* srs */ - ARCH(6); - gen_srs(s, (insn & 0x1f), (insn >> 23) & 3, insn & (1 << 21)); - return; - } else if ((insn & 0x0e50ffe0) == 0x08100a00) { - /* rfe */ - int32_t offset; - if (IS_USER(s)) - goto illegal_op; - ARCH(6); - rn = (insn >> 16) & 0xf; - addr = load_reg(s, rn); - i = (insn >> 23) & 3; - switch (i) { - case 0: offset = -4; break; /* DA */ - case 1: offset = 0; break; /* IA */ - case 2: offset = -8; break; /* DB */ - case 3: offset = 4; break; /* IB */ - default: abort(); - } - if (offset) - tcg_gen_addi_i32(addr, addr, offset); - /* Load PC into tmp and CPSR into tmp2. */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - tcg_gen_addi_i32(addr, addr, 4); - tmp2 = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s)); - if (insn & (1 << 21)) { - /* Base writeback. */ - switch (i) { - case 0: offset = -8; break; - case 1: offset = 4; break; - case 2: offset = -4; break; - case 3: offset = 0; break; - default: abort(); - } - if (offset) - tcg_gen_addi_i32(addr, addr, offset); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - gen_rfe(s, tmp, tmp2); - return; } else if ((insn & 0x0e000f00) == 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10316,7 +10325,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; - TCGv_i32 tmp2; TCGv_i32 addr; int op; @@ -10460,44 +10468,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; } } else { - /* Load/store multiple, RFE, SRS. */ - if (((insn >> 23) & 1) == ((insn >> 24) & 1)) { - /* RFE, SRS: not available in user mode or on M profile */ - if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - if (insn & (1 << 20)) { - /* rfe */ - addr = load_reg(s, rn); - if ((insn & (1 << 24)) == 0) - tcg_gen_addi_i32(addr, addr, -8); - /* Load PC into tmp and CPSR into tmp2. */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - tcg_gen_addi_i32(addr, addr, 4); - tmp2 = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s)); - if (insn & (1 << 21)) { - /* Base writeback. */ - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, 4); - } else { - tcg_gen_addi_i32(addr, addr, -4); - } - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - gen_rfe(s, tmp, tmp2); - } else { - /* srs */ - gen_srs(s, (insn & 0x1f), (insn & (1 << 24)) ? 1 : 2, - insn & (1 << 21)); - } - } else { - /* Load/store multiple, in decodetree */ - goto illegal_op; - } + /* Load/store multiple, RFE, SRS, in decodetree */ + goto illegal_op; } break; case 5: diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 573ac2cf8e..3b961233e5 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -29,3 +29,11 @@ %imm24h 0:s24 24:1 !function=times_2 BLX_i 1111 101 . ........................ &i imm=%imm24h + +# System Instructions + +&rfe rn w pu +&srs mode w pu + +RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe +SRS 1111 110 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ebc92f2c28..c8a8aeceee 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -582,6 +582,18 @@ STM_t32 1110 1001 00.0 .... ................ @ldstm i=0 b=1 LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0 LDM_t32 1110 1001 00.1 .... ................ @ldstm i=0 b=1 +&rfe !extern rn w pu +@rfe .... .... .. w:1 . rn:4 ................ &rfe + +RFE 1110 1000 00.1 .... 1100000000000000 @rfe pu=2 +RFE 1110 1001 10.1 .... 1100000000000000 @rfe pu=1 + +&srs !extern mode w pu +@srs .... .... .. w:1 . .... ........... mode:5 &srs + +SRS 1110 1000 00.0 1101 1100 0000 000. .... @srs pu=2 +SRS 1110 1001 10.0 1101 1100 0000 000. .... @srs pu=1 + # Branches %imm24 26:s1 13:1 11:1 16:10 0:11 !function=t32_branch24 From patchwork Mon Aug 19 21:37:21 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:21 -0700 Message-Id: <20190819213755.26175-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v2 34/68] target/arm: Convert Clear-Exclusive, Barriers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 122 +++++++++++++++-------------------- target/arm/a32-uncond.decode | 10 +++ target/arm/t32.decode | 10 +++ 3 files changed, 73 insertions(+), 69 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index e268c5168d..6489bbc09c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10038,6 +10038,58 @@ static bool trans_SRS(DisasContext *s, arg_SRS *a) return true; } +/* + * Clear-Exclusive, Barriers + */ + +static bool trans_CLREX(DisasContext *s, arg_CLREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + gen_clrex(s); + return true; +} + +static bool trans_DSB(DisasContext *s, arg_DSB *a) +{ + if (!s->thumb && !ENABLE_ARCH_7) { + return false; + } + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + return true; +} + +static bool trans_DMB(DisasContext *s, arg_DMB *a) +{ + return trans_DSB(s, NULL); +} + +static bool trans_ISB(DisasContext *s, arg_ISB *a) +{ + /* + * We need to break the TB after this insn to execute + * self-modifying code correctly and also to take + * any pending interrupts immediately. + */ + gen_goto_tb(s, 0, s->base.pc_next); + return true; +} + +static bool trans_SB(DisasContext *s, arg_SB *a) +{ + if (!dc_isar_feature(aa32_sb, s)) { + return false; + } + /* + * TODO: There is no speculation barrier opcode + * for TCG; MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, s->base.pc_next); + return true; +} + /* * Legacy decoder. */ @@ -10131,38 +10183,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) s->base.is_jmp = DISAS_UPDATE; } return; - } else if ((insn & 0x0fffff00) == 0x057ff000) { - switch ((insn >> 4) & 0xf) { - case 1: /* clrex */ - ARCH(6K); - gen_clrex(s); - return; - case 4: /* dsb */ - case 5: /* dmb */ - ARCH(7); - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - return; - case 6: /* isb */ - /* We need to break the TB after this insn to execute - * self-modifying code correctly and also to take - * any pending interrupts immediately. - */ - gen_goto_tb(s, 0, s->base.pc_next); - return; - case 7: /* sb */ - if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) { - goto illegal_op; - } - /* - * TODO: There is no speculation barrier opcode - * for TCG; MB and end the TB instead. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, s->base.pc_next); - return; - default: - goto illegal_op; - } } else if ((insn & 0x0e000f00) == 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10623,43 +10643,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) gen_set_psr_im(s, offset, 0, imm); } break; - case 3: /* Special control operations. */ - if (!arm_dc_feature(s, ARM_FEATURE_V7) && - !arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - op = (insn >> 4) & 0xf; - switch (op) { - case 2: /* clrex */ - gen_clrex(s); - break; - case 4: /* dsb */ - case 5: /* dmb */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - break; - case 6: /* isb */ - /* We need to break the TB after this insn - * to execute self-modifying code correctly - * and also to take any pending interrupts - * immediately. - */ - gen_goto_tb(s, 0, s->base.pc_next); - break; - case 7: /* sb */ - if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) { - goto illegal_op; - } - /* - * TODO: There is no speculation barrier opcode - * for TCG; MB and end the TB instead. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, s->base.pc_next); - break; - default: - goto illegal_op; - } - break; + case 3: /* Special control operations, in decodetree */ case 4: /* bxj, in decodetree */ goto illegal_op; case 5: /* Exception return. */ diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 3b961233e5..b077958cec 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -22,6 +22,7 @@ # All of those that have a COND field in insn[31:28] are in a32.decode # +&empty !extern &i !extern imm # Branch with Link and Exchange @@ -37,3 +38,12 @@ BLX_i 1111 101 . ........................ &i imm=%imm24h RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe SRS 1111 110 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs + +# Clear-Exclusive, Barriers + +# QEMU does not require the option field for the barriers. +CLREX 1111 0101 0111 1111 1111 0000 0001 1111 +DSB 1111 0101 0111 1111 1111 0000 0100 ---- +DMB 1111 0101 0111 1111 1111 0000 0101 ---- +ISB 1111 0101 0111 1111 1111 0000 0110 ---- +SB 1111 0101 0111 1111 1111 0000 0111 0000 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index c8a8aeceee..18c268e712 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -305,6 +305,16 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm # of the space is "reserved hint, behaves as nop". NOP 1111 0011 1010 1111 1000 0000 ---- ---- } + + # Miscelaneous control + { + CLREX 1111 0011 1011 1111 1000 1111 0010 1111 + DSB 1111 0011 1011 1111 1000 1111 0100 ---- + DMB 1111 0011 1011 1111 1000 1111 0101 ---- + ISB 1111 0011 1011 1111 1000 1111 0110 ---- + SB 1111 0011 1011 1111 1000 1111 0111 0000 + } + # Note that the v7m insn overlaps both the normal and banked insn. { MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ From patchwork Mon Aug 19 21:37:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171697 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3553713ily; Mon, 19 Aug 2019 15:08:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqzy+KVJ68yrdu4UPZUcW821ae+WoOAO0xCAV2qmF2CfqLQMAh2kXtoIRtQrfarvr4oUN8Jv X-Received: by 2002:a17:906:4c81:: with SMTP id q1mr12121772eju.185.1566252527511; Mon, 19 Aug 2019 15:08:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566252527; cv=none; d=google.com; s=arc-20160816; b=jw3B0oJlWFazF1Tnl9mOU+yImenrDeAkC5sCpJDyrywpyEdK9KDSoe8rTFdIzvoj9r 2UXr/BwVwMa/L0arMPVBfIK2uqhhfZ92SWUllirvVGNqWk+BxcD+k5EGS7q18fo/7nmw yMZzKRwZGd5ja7iILShZs6FXG3N/Sh10TCh0CQPGNRnhD2fYW1HrNUTwUHfgxJ7PniDU xhTg2+ir9LgDgJpfuooU8ybkvA5JEEb6ywLJUDsp0UKhDEu6NO5GvkBYhx0nmFFjK3Ym NZ4xYwaTZhry0QtiLaHVQmGXT3I4I7Q2uH5rSy3H5E5A9J6ZFhLw6zc9B8BvBcW8+14E dHHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=hd9oAYsJN/ILLc4tSsxONdbYI/SdPS1ZDtg8ggp1IIQ=; b=di9qevHoils1LAtzEgBj/p/y08S8xYs6fenlR/+YfTZPnBQlJ/RnFV6oz++8DsNm8W OSmvyDSZqgYNQd17dn1qFmSwVjjyYWHcAXkOgpNkhCrfAQUHAArXKIsU38kqjSzeEy9F ra1MMYUDoSGdFll+uAh2b42IcPBRTLBuoflsYIK03cBAU2ukrbT0xX7wRt6bnR2AnkpP YKx7WaNt/XC49z3T2/6HKWif0HF+sSFUzla5XQsTGxAveKMWurcYttOAFkvtNr3q1OMs 0TKub7krZgljJ7zMT3XuggO89RWpCQemgc/vasjjGcAxXLTw0OtCop+AYtfiIFtNdnVw lx1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rs+aVxya; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 35/68] target/arm: Convert CPS (privileged) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 87 +++++++++++++++--------------------- target/arm/a32-uncond.decode | 3 ++ target/arm/t32.decode | 3 ++ 3 files changed, 42 insertions(+), 51 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 6489bbc09c..928205d993 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10038,6 +10038,40 @@ static bool trans_SRS(DisasContext *s, arg_SRS *a) return true; } +static bool trans_CPS(DisasContext *s, arg_CPS *a) +{ + uint32_t mask, val; + + if (IS_USER(s)) { + /* Implemented as NOP in user mode. */ + return true; + } + + mask = val = 0; + if (a->imod & 2) { + if (a->A) { + mask |= CPSR_A; + } + if (a->I) { + mask |= CPSR_I; + } + if (a->F) { + mask |= CPSR_F; + } + if (a->imod & 1) { + val |= mask; + } + } + if (a->M) { + mask |= CPSR_M; + val |= a->mode; + } + if (mask) { + gen_set_psr_im(s, mask, 0, val); + } + return true; +} + /* * Clear-Exclusive, Barriers */ @@ -10209,31 +10243,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) ARCH(5TE); } else if ((insn & 0x0f000010) == 0x0e000010) { /* Additional coprocessor register transfer. */ - } else if ((insn & 0x0ff10020) == 0x01000000) { - uint32_t mask; - uint32_t val; - /* cps (privileged) */ - if (IS_USER(s)) - return; - mask = val = 0; - if (insn & (1 << 19)) { - if (insn & (1 << 8)) - mask |= CPSR_A; - if (insn & (1 << 7)) - mask |= CPSR_I; - if (insn & (1 << 6)) - mask |= CPSR_F; - if (insn & (1 << 18)) - val |= mask; - } - if (insn & (1 << 17)) { - mask |= CPSR_M; - val |= (insn & 0x1f); - } - if (mask) { - gen_set_psr_im(s, mask, 0, val); - } - return; } goto illegal_op; } @@ -10342,7 +10351,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; TCGv_i32 addr; @@ -10618,31 +10626,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 0: /* msr cpsr, in decodetree */ case 1: /* msr spsr, in decodetree */ goto illegal_op; - case 2: /* cps, nop-hint. */ - /* nop hints in decodetree */ - /* Implemented as NOP in user mode. */ - if (IS_USER(s)) - break; - offset = 0; - imm = 0; - if (insn & (1 << 10)) { - if (insn & (1 << 7)) - offset |= CPSR_A; - if (insn & (1 << 6)) - offset |= CPSR_I; - if (insn & (1 << 5)) - offset |= CPSR_F; - if (insn & (1 << 9)) - imm = CPSR_A | CPSR_I | CPSR_F; - } - if (insn & (1 << 8)) { - offset |= 0x1f; - imm |= (insn & 0x1f); - } - if (offset) { - gen_set_psr_im(s, offset, 0, imm); - } - break; + case 2: /* cps, nop-hint, in decodetree */ + goto illegal_op; case 3: /* Special control operations, in decodetree */ case 4: /* bxj, in decodetree */ goto illegal_op; diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index b077958cec..eb1c55b330 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -35,9 +35,12 @@ BLX_i 1111 101 . ........................ &i imm=%imm24h &rfe rn w pu &srs mode w pu +&cps mode imod M A I F RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe SRS 1111 110 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs +CPS 1111 0001 0000 imod:2 M:1 0 0000 000 A:1 I:1 F:1 0 mode:5 \ + &cps # Clear-Exclusive, Barriers diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 18c268e712..354ad77fe6 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -44,6 +44,7 @@ &bfi !extern rd rn lsb msb &sat !extern rd rn satimm imm sh &pkh !extern rd rn rm imm tb +&cps !extern mode imod M A I F # Data-processing (register) @@ -340,6 +341,8 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=%imm16_16_0 + CPS 1111 0011 1010 1111 1000 0 imod:2 M:1 A:1 I:1 F:1 mode:5 \ + &cps UDF 1111 0111 1111 ---- 1010 ---- ---- ---- } B_cond_thumb 1111 0. cond:4 ...... 10.0 ............ &ci imm=%imm21 From patchwork Mon Aug 19 21:37:23 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:23 -0700 Message-Id: <20190819213755.26175-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 36/68] target/arm: Convert SETEND X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 22 +++++++++++++--------- target/arm/a32-uncond.decode | 4 ++++ 2 files changed, 17 insertions(+), 9 deletions(-) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/translate.c b/target/arm/translate.c index 928205d993..46e88d1d17 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10124,6 +10124,18 @@ static bool trans_SB(DisasContext *s, arg_SB *a) return true; } +static bool trans_SETEND(DisasContext *s, arg_SETEND *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + if (a->E != (s->be_data == MO_BE)) { + gen_helper_setend(cpu_env); + s->base.is_jmp = DISAS_UPDATE; + } + return true; +} + /* * Legacy decoder. */ @@ -10209,15 +10221,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) return; /* v7MP: Unallocated memory hint: must NOP */ } - if ((insn & 0x0ffffdff) == 0x01010000) { - ARCH(6); - /* setend */ - if (((insn >> 9) & 1) != !!(s->be_data == MO_BE)) { - gen_helper_setend(cpu_env); - s->base.is_jmp = DISAS_UPDATE; - } - return; - } else if ((insn & 0x0e000f00) == 0x0c000100) { + if ((insn & 0x0e000f00) == 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ if (extract32(s->c15_cpar, 1, 1)) { diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index eb1c55b330..d5ed48f0fd 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -24,6 +24,7 @@ &empty !extern &i !extern imm +&setend E # Branch with Link and Exchange @@ -50,3 +51,6 @@ DSB 1111 0101 0111 1111 1111 0000 0100 ---- DMB 1111 0101 0111 1111 1111 0000 0101 ---- ISB 1111 0101 0111 1111 1111 0000 0110 ---- SB 1111 0101 0111 1111 1111 0000 0111 0000 + +# Set Endianness +SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend From patchwork Mon Aug 19 21:37:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171705 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3558835ily; Mon, 19 Aug 2019 15:14:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqyqyb1siUu+M5xfs5UEiWE1/6ngK//vvJmIyc7UdqVQhX8EfVT3/oQHdFI+os9OGk0ulOxI X-Received: by 2002:a37:61c3:: with SMTP id v186mr21829781qkb.158.1566252884770; Mon, 19 Aug 2019 15:14:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566252884; cv=none; d=google.com; s=arc-20160816; b=Zy90Z/B+ACp8I6XVYXPZhkVe1rdZeJDjHYOUgli7ofWyRgvGO/AwLl/JV1rUJA+vaT rmsnjOFLYvjnzm3T5or/6gn6mqGxSGBpwmh+t0qjB/SxLaWSLOCmuuBWYdgOnWdvBG92 MiyyQkUjbsooQQ3h+dvBttzP8OMFvaFlvhDjLHIvp+jEG8JNRnn8JDQe7m1jWEdZOrXi XXefxojjlZkvzfTFlEpnEsu2p6ghFpHDOg2GGK1mYgag+IFx8kguxFEkJKWPWjk1JvoO 0z4qfv18XCJWJI4pRKzMrwKHVspsxtEtiNshV8fnuaTNtywDZhP6f/BvSOznW2lFpjpc rHWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=JhmaAGzRoow6PV3mD1aboEwUvmsUrSNHW6vrm01q9UA=; b=jWeT+YL1ahUmkNbDDqk7KT0Ol7EyODB+qJHCkVQuyIIlmNPcCjrWTXRhTDNd7jfkg7 dSlyMR2tbMplOHpM1/YiB1sHH5dskVL2D5VOosDM6d+kjwkWzCHhDOhxfvJLau7+GVD5 CHvMA6WgqAZwdAlWfE0KXdGzrbRAuZ3A3Ju5cnOnUIXG0HvAFdzq1yeYPWiDDtIyHOkF Zn3XO70ixt5GRg9aTKMN0p7sE9dF11bRk8iNcHwxvONYAFJe5U4Ue8lAyiCRI/EB6bGb MxlzmHUiTk3yrAoO02RI/odxY4x9vFekHF4If29Y1uMW+yv6/4r6u0REd7R4ccvYSy0Z iaDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eNhhBEL5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v2 37/68] target/arm: Convert PLI, PLD, PLDW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 37 +++++++++++++++++++----------------- target/arm/a32-uncond.decode | 10 ++++++++++ 2 files changed, 30 insertions(+), 17 deletions(-) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/translate.c b/target/arm/translate.c index 46e88d1d17..a30a9bb4e0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10136,6 +10136,26 @@ static bool trans_SETEND(DisasContext *s, arg_SETEND *a) return true; } +/* + * Preload instructions + * All are nops, contingent on the appropriate arch level. + */ + +static bool trans_PLD(DisasContext *s, arg_PLD *a) +{ + return ENABLE_ARCH_5TE; +} + +static bool trans_PLDW(DisasContext *s, arg_PLD *a) +{ + return arm_dc_feature(s, ARM_FEATURE_V7MP); +} + +static bool trans_PLI(DisasContext *s, arg_PLD *a) +{ + return ENABLE_ARCH_7; +} + /* * Legacy decoder. */ @@ -10196,23 +10216,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } return; } - if (((insn & 0x0f30f000) == 0x0510f000) || - ((insn & 0x0f30f010) == 0x0710f000)) { - if ((insn & (1 << 22)) == 0) { - /* PLDW; v7MP */ - if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { - goto illegal_op; - } - } - /* Otherwise PLD; v5TE+ */ - ARCH(5TE); - return; - } - if (((insn & 0x0f70f000) == 0x0450f000) || - ((insn & 0x0f70f010) == 0x0650f000)) { - ARCH(7); - return; /* PLI; V7 */ - } if (((insn & 0x0f700000) == 0x04100000) || ((insn & 0x0f700010) == 0x06100000)) { if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index d5ed48f0fd..aed381cb8e 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -54,3 +54,13 @@ SB 1111 0101 0111 1111 1111 0000 0111 0000 # Set Endianness SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend + +# Preload instructions + +PLD 1111 0101 -101 ---- 1111 ---- ---- ---- # (imm, lit) 5te +PLDW 1111 0101 -001 ---- 1111 ---- ---- ---- # (imm, lit) 7mp +PLI 1111 0100 -101 ---- 1111 ---- ---- ---- # (imm, lit) 7 + +PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5te +PLDW 1111 0111 -001 ---- 1111 ----- -- 0 ---- # (register) 7mp +PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7 From patchwork Mon Aug 19 21:37:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171709 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3560900ily; Mon, 19 Aug 2019 15:16:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqyBUCYEGaRSe/ACHL4RVEM+N/lemQzC7VuN1IBBwmFxwGaGPKhheSPa+hZ9xrJWTO1kBnED X-Received: by 2002:a37:a14e:: with SMTP id k75mr23415886qke.65.1566253017921; Mon, 19 Aug 2019 15:16:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566253017; cv=none; d=google.com; s=arc-20160816; b=XdDabaKAlCvDcgfUDF94MuOv4z3knmXWKgaCGDwA1F/3Mm4MfSpgvgznpqSPFbFKAV FerS/3LvG0uQlv8eOk009Bme2BUHQkuR5vfMSc+2qlzhPecW8RN69+Gycw9QLON3w3mc /iAbBMvIgoijsdAUZmTrxFd4XcSlxzpDCN9hMxOiiDJBWSdlbPvTjZnxD3vW3Dasz/j6 lVUlf9REV3sVElAUIVsqOAOYb6v1/y1Xai82DY4Zpyju5lz+hgahf7vhcouhzkRgQItL ZFR1jmkcGcO6Zf5nwsyz9WW4P6EG4YiS3A+CGlelzXvSU4VznDq0L9asLgvhA7fqXTh6 q/aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=AfObyYVf+TtUvkYatWrX5oVYyhEhA7Z+ZbkDEmf7ZT8=; b=KqzxFgBx38SOj2aOU8x/LBChXyex5SJ0qjpjWaNfYRTt7gDzxmW2p5I8N4VSviNVs7 CdGGre1MFX3A0iXtExRcYayAGPOWY1xgSJrJCqqkCQjYBwnhZYnSqGRv3Rf8n7gop/8C 94omxkqi1Q7/NO4DYFgiGCo8FLOKM+7Voie/cUBWvJgpU2t+u/QV1ihim7M5oP6GkTlJ oeOYNBNl4M7w8mKYRut1X6+6pKThQL9nXyreOeg//0tbVcBElBrEDOKzl/gStFbiLuwT mUTJyKpJLBrXjbHJTzHl/oxARyGD4okcIzgP02qFiEIGfqAsEilRp+Q6bcg8R1k0UyXg qAUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RFuZtKWF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:25 -0700 Message-Id: <20190819213755.26175-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v2 38/68] target/arm: Convert Unallocated memory hint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 8 -------- target/arm/a32-uncond.decode | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/translate.c b/target/arm/translate.c index a30a9bb4e0..9ec6b25c03 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10216,14 +10216,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } return; } - if (((insn & 0x0f700000) == 0x04100000) || - ((insn & 0x0f700010) == 0x06100000)) { - if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { - goto illegal_op; - } - return; /* v7MP: Unallocated memory hint: must NOP */ - } - if ((insn & 0x0e000f00) == 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index aed381cb8e..afa95bf7aa 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -64,3 +64,11 @@ PLI 1111 0100 -101 ---- 1111 ---- ---- ---- # (imm, lit) 7 PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5te PLDW 1111 0111 -001 ---- 1111 ----- -- 0 ---- # (register) 7mp PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7 + +# Unallocated memory hints +# +# Since these are v7MP nops, and PLDW is v7MP and implemented as nop, +# (ab)use the PLDW helper. + +PLDW 1111 0100 -001 ---- ---- ---- ---- ---- +PLDW 1111 0110 -001 ---- ---- ---- ---0 ---- From patchwork Mon Aug 19 21:37:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171689 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3547722ily; Mon, 19 Aug 2019 15:02:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqxXPZN1yzEoDLh1BOBj+vK8xCLOzG/Bn2opMHgIaiRxY11Cm67PwaSWCCxusvg/Ms21kUk8 X-Received: by 2002:aa7:df03:: with SMTP id c3mr27543844edy.112.1566252176360; Mon, 19 Aug 2019 15:02:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566252176; cv=none; d=google.com; s=arc-20160816; b=Nnf1oa52N3Vncll9zoxZ4X2owrk7gyzNNxNw3J0QSk5lL+/1lCTQcjyd3IC5zPfkhh G4xaUBUXc1Ofv/lWuUsD6KTk7FrB+xSm1LclJCYJLd/kBPn+DcdTBF3SCIdUFZUNE1Rd OMKFM5Xc6jxSyB6WdDMu2WzW2I4GWkKZQXGttEHOm+sng8q0s2HC2tYnhbkzAGHHu7SQ nTxOWyeJ1ttjiscVaBLoELTTCLrZchLsGg95vboksZdTYi+YPjQ4CyA7rt9qRNZzagWD McsOEsT0sCzxFI9D4Y5Q/aP19QZ4RK0vedvceDhSn4J5jkQ1Q0qQsfEX5uZMtiI5e0vw 6Kew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=4oWyeRO7VGSUxbfq5SQ/Ttd5DuqgQfk+9PyV2J/44KI=; b=mo6RCAmodDNy04zD5dvL0tSo/+a6//oupeUcQQrh4AZi4aBxTiYNLExaS5zU9vftPJ dqs1yRfkXbI43T2mxitqTJoDlv762Bsx7/LHaNG+Xf5Gti3GdlTnGDpTzrwYnAVybBoz 90KlJki0qLxICpQ8BDO95fcJ3ddibAS2rtMba1pSrY7C3Un0d6IiySx/uUFu0WnsNYdI ZqsYHO0/h1KlSglIu90DyACKAzG1F/LcMrxYO6t4RRcT0c0Uti5LvgwR0V/dMj+3ROky oHv1K3H2+W4H/Qc/dWD52c1T/HdEsgp2Xe8EgJ+oIJw/pcwJL/5iRQO4LaKUpwD9Cnim yjDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Drn5lIP0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:26 -0700 Message-Id: <20190819213755.26175-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62c Subject: [Qemu-devel] [PATCH v2 39/68] target/arm: Convert Table Branch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 57 +++++++++++++++++++++++++----------------- target/arm/t32.decode | 8 +++++- 2 files changed, 41 insertions(+), 24 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 9ec6b25c03..7c05e7006e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9968,6 +9968,37 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) return true; } +static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) +{ + TCGv_i32 addr, tmp; + + tmp = load_reg(s, a->rm); + if (half) { + tcg_gen_add_i32(tmp, tmp, tmp); + } + addr = load_reg(s, a->rn); + tcg_gen_add_i32(addr, addr, tmp); + + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), + half ? MO_UW | s->be_data : MO_UB); + tcg_temp_free_i32(addr); + + tcg_gen_add_i32(tmp, tmp, tmp); + tcg_gen_addi_i32(tmp, tmp, read_pc(s)); + store_reg(s, 15, tmp); + return true; +} + +static bool trans_TBB(DisasContext *s, arg_tbranch *a) +{ + return op_tbranch(s, a, false); +} + +static bool trans_TBH(DisasContext *s, arg_tbranch *a) +{ + return op_tbranch(s, a, true); +} + /* * Supervisor call */ @@ -10350,9 +10381,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t rd, rn, rm, rs; - TCGv_i32 tmp; - TCGv_i32 addr; + uint32_t rd, rn, rs; int op; /* @@ -10398,7 +10427,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) rn = (insn >> 16) & 0xf; rs = (insn >> 12) & 0xf; rd = (insn >> 8) & 0xf; - rm = insn & 0xf; switch ((insn >> 25) & 0xf) { case 0: case 1: case 2: case 3: /* 16-bit instructions. Should never happen. */ @@ -10471,25 +10499,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) /* Load/store exclusive, in decodetree */ goto illegal_op; } else if ((insn & (7 << 5)) == 0) { - /* Table Branch. */ - addr = load_reg(s, rn); - tmp = load_reg(s, rm); - tcg_gen_add_i32(addr, addr, tmp); - if (insn & (1 << 4)) { - /* tbh */ - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - tmp = tcg_temp_new_i32(); - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); - } else { /* tbb */ - tcg_temp_free_i32(tmp); - tmp = tcg_temp_new_i32(); - gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); - } - tcg_temp_free_i32(addr); - tcg_gen_shli_i32(tmp, tmp, 1); - tcg_gen_addi_i32(tmp, tmp, read_pc(s)); - store_reg(s, 15, tmp); + /* Table Branch, in decodetree */ + goto illegal_op; } else { /* Load/store exclusive, load-acq/store-rel, in decodetree */ goto illegal_op; diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 354ad77fe6..0cc0808c05 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -487,7 +487,7 @@ LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1 LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1 -# Load/Store Exclusive and Load-Acquire/Store-Release +# Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch @strex_i .... .... .... rn:4 rt:4 rd:4 .... .... \ &strex rt2=15 imm=%imm8x4 @@ -531,6 +531,12 @@ LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0 LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0 LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0 +&tbranch rn rm +@tbranch .... .... .... rn:4 .... .... .... rm:4 &tbranch + +TBB 1110 1000 1101 .... 1111 0000 0000 .... @tbranch +TBH 1110 1000 1101 .... 1111 0000 0001 .... @tbranch + # Parallel addition and subtraction SADD8 1111 1010 1000 .... 1111 .... 0000 .... @rndm From patchwork Mon Aug 19 21:37:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171692 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3550303ily; Mon, 19 Aug 2019 15:05:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqyh6Ev3PHCa7ZBwNrDzrMTX1W4gNz9mMMivzr8gqjFWGZjHJln0bbWPA0eTofD1lWWR83N6 X-Received: by 2002:a17:906:9453:: with SMTP id z19mr23289643ejx.287.1566252325704; Mon, 19 Aug 2019 15:05:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566252325; cv=none; d=google.com; s=arc-20160816; b=l0rjQzeGCVqe/BlESOQo8dGLBL9nw78VENEVv4eGId/IuV2Ga3/Z+yn1vZlv5jJe91 hhAZtZiJcXX5kn2nub6PndhgEmYA3w4rY+m33JCjiC3RaFsXb6JzU3PNcMzcjXDb+mz6 E+umw/q6Dh0z51Y944F5uc7HkEy1S2pts39mfk+Hk3+eV94mP3o0nwnWqebCotTs11a5 +SuA/7q9MMC7TBya1di6lxQhqxBL2nc6nOyAsW59nqhs76Kv9cyHykbc7p1G4wTItMWX jkpSHTgFsOeijMKETcYw5ezTnXUeoxgQTi96SKZuskzr745yqSEOvdQKVm6+ifCHCvHJ vT9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=wLniY7IH5XOVstT1ZURU/Pqp4JvYW6tk9V3WWoNomaw=; b=z4YJh2bmYkcD7yZ8wxs9I32GjeHVUK8jy+IxA4KMf136J91zPkRgffpGiym9cROYud Ww5aJ/uPLjxDC3Q/Qp+kO3/fpZx9iE7C0wF7lU20pu7uk3oMMPlz2vpJOmJtv8wqZA1t dkAp0HcozlXE0+gUiSMW8Saxrm4sxFfHA+neMlBFY2bhSkKAKeD2x1cmZKFDqyl7S7AK ys09eBtWQyE9noYeeWEEyER4HjdiNX5hsmzG1yUq6uBw3OB6eX4BQho6WC+jP5b0FGfC 6GATxTYay2RdCLDnvigttHAE/XBa792Mmfoa6jYot/YteyXaN3ojhAoYVgm87ftypsyT WMbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="Fzr8/0vm"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:27 -0700 Message-Id: <20190819213755.26175-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v2 40/68] target/arm: Convert SG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 51 ++++++++++++++++++++++++------------------ target/arm/t32.decode | 5 ++++- 2 files changed, 33 insertions(+), 23 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 7c05e7006e..9a8864e8ff 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8426,6 +8426,34 @@ static bool trans_SMC(DisasContext *s, arg_SMC *a) return true; } +static bool trans_SG(DisasContext *s, arg_SG *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + /* + * SG (v8M only) + * The bulk of the behaviour for this instruction is implemented + * in v7m_handle_execute_nsc(), which deals with the insn when + * it is executed by a CPU in non-secure state from memory + * which is Secure & NonSecure-Callable. + * Here we only need to handle the remaining cases: + * * in NS memory (including the "security extension not + * implemented" case) : NOP + * * in S memory but CPU already secure (clear IT bits) + * We know that the attribute for the memory this insn is + * in must match the current CPU state, because otherwise + * get_phys_addr_pmsav8 would have generated an exception. + */ + if (s->v8m_secure) { + /* Like the IT insn, we don't need to generate any code */ + s->condexec_cond = 0; + s->condexec_mask = 0; + } + return true; +} + /* * Load/store register index */ @@ -10437,28 +10465,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) * - load/store doubleword, load/store exclusive, ldacq/strel, * table branch, TT. */ - if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_M) && - arm_dc_feature(s, ARM_FEATURE_V8)) { - /* 0b1110_1001_0111_1111_1110_1001_0111_111 - * - SG (v8M only) - * The bulk of the behaviour for this instruction is implemented - * in v7m_handle_execute_nsc(), which deals with the insn when - * it is executed by a CPU in non-secure state from memory - * which is Secure & NonSecure-Callable. - * Here we only need to handle the remaining cases: - * * in NS memory (including the "security extension not - * implemented" case) : NOP - * * in S memory but CPU already secure (clear IT bits) - * We know that the attribute for the memory this insn is - * in must match the current CPU state, because otherwise - * get_phys_addr_pmsav8 would have generated an exception. - */ - if (s->v8m_secure) { - /* Like the IT insn, we don't need to generate any code */ - s->condexec_cond = 0; - s->condexec_mask = 0; - } - } else if (insn & 0x01200000) { + if (insn & 0x01200000) { /* load/store dual, in decodetree */ goto illegal_op; } else if ((insn & (1 << 23)) == 0) { diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 0cc0808c05..ce46650446 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -485,7 +485,10 @@ STRD_ri_t32 1110 1001 .100 .... .... .... ........ @ldstd_ri8 w=0 p=1 LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1 -LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1 +{ + SG 1110 1001 0111 1111 1110 1001 01111111 + LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1 +} # Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch From patchwork Mon Aug 19 21:37:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171695 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3551902ily; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:28 -0700 Message-Id: <20190819213755.26175-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 41/68] target/arm: Convert TT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 87 +++++++++++++----------------------------- target/arm/t32.decode | 5 ++- 2 files changed, 31 insertions(+), 61 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 9a8864e8ff..d1078ca1ec 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8454,6 +8454,30 @@ static bool trans_SG(DisasContext *s, arg_SG *a) return true; } +static bool trans_TT(DisasContext *s, arg_TT *a) +{ + TCGv_i32 addr, tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + if (a->rd == 13 || a->rd == 15 || a->rn == 15) { + /* We UNDEF for these UNPREDICTABLE cases */ + return false; + } + if (a->A && !s->v8m_secure) { + return false; + } + + addr = load_reg(s, a->rn); + tmp = tcg_const_i32((a->A << 1) | a->T); + gen_helper_v7m_tt(tmp, cpu_env, addr, tmp); + tcg_temp_free_i32(addr); + store_reg(s, a->rd, tmp); + return true; +} + /* * Load/store register index */ @@ -10409,7 +10433,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t rd, rn, rs; + uint32_t rn; int op; /* @@ -10453,70 +10477,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) /* fall back to legacy decoder */ rn = (insn >> 16) & 0xf; - rs = (insn >> 12) & 0xf; - rd = (insn >> 8) & 0xf; switch ((insn >> 25) & 0xf) { case 0: case 1: case 2: case 3: /* 16-bit instructions. Should never happen. */ abort(); case 4: - if (insn & (1 << 22)) { - /* 0b1110_100x_x1xx_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store doubleword, load/store exclusive, ldacq/strel, - * table branch, TT. - */ - if (insn & 0x01200000) { - /* load/store dual, in decodetree */ - goto illegal_op; - } else if ((insn & (1 << 23)) == 0) { - /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store exclusive word - * - TT (v8M only) - */ - if (rs == 15) { - if (!(insn & (1 << 20)) && - arm_dc_feature(s, ARM_FEATURE_M) && - arm_dc_feature(s, ARM_FEATURE_V8)) { - /* 0b1110_1000_0100_xxxx_1111_xxxx_xxxx_xxxx - * - TT (v8M only) - */ - bool alt = insn & (1 << 7); - TCGv_i32 addr, op, ttresp; - - if ((insn & 0x3f) || rd == 13 || rd == 15 || rn == 15) { - /* we UNDEF for these UNPREDICTABLE cases */ - goto illegal_op; - } - - if (alt && !s->v8m_secure) { - goto illegal_op; - } - - addr = load_reg(s, rn); - op = tcg_const_i32(extract32(insn, 6, 2)); - ttresp = tcg_temp_new_i32(); - gen_helper_v7m_tt(ttresp, cpu_env, addr, op); - tcg_temp_free_i32(addr); - tcg_temp_free_i32(op); - store_reg(s, rd, ttresp); - break; - } - goto illegal_op; - } - /* Load/store exclusive, in decodetree */ - goto illegal_op; - } else if ((insn & (7 << 5)) == 0) { - /* Table Branch, in decodetree */ - goto illegal_op; - } else { - /* Load/store exclusive, load-acq/store-rel, in decodetree */ - goto illegal_op; - } - } else { - /* Load/store multiple, RFE, SRS, in decodetree */ - goto illegal_op; - } - break; + /* All in decodetree */ + goto illegal_op; case 5: /* All in decodetree */ goto illegal_op; diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ce46650446..bb875f77b0 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -506,7 +506,10 @@ STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1 @ldrex_d .... .... .... rn:4 rt:4 rt2:4 .... .... \ &ldrex imm=0 -STREX 1110 1000 0100 .... .... .... .... .... @strex_i +{ + TT 1110 1000 0100 rn:4 1111 rd:4 A:1 T:1 000000 + STREX 1110 1000 0100 .... .... .... .... .... @strex_i +} STREXB 1110 1000 1100 .... .... 1111 0100 .... @strex_0 STREXH 1110 1000 1100 .... .... 1111 0101 .... @strex_0 STREXD_t32 1110 1000 1100 .... .... .... 0111 .... @strex_d From patchwork Mon Aug 19 21:37:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171714 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3563932ily; Mon, 19 Aug 2019 15:20:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqyN+olYFLeuM1x4XK+Y808fXZwIxC6cExfIWzmem46CJMU8/LgY93RYjU8cqNBVgiVfK3jv X-Received: by 2002:ad4:514b:: with SMTP id g11mr12315403qvq.203.1566253246565; Mon, 19 Aug 2019 15:20:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566253246; cv=none; d=google.com; s=arc-20160816; b=UatxGJ9noSwyP8UHnuUpRURLO5o8FuI5s9eUxOhVz5YmTIxgWyTq6nX1DWsRayvqIt bygMXsmgPmnWRRV3r6gGAUoUXhk/WGBTqjXC8FxQAZwTDsN+b7mBXgdZ4REzF6Nb8hz8 qKiPAlmTW7EkjLAf0kLr5EN6Bo/8OW0bYU8cL9Q3m66kJEo9W1BTQRrAuXTNv5VHNTVV lD9unISIH28LqYGbvm+OmcF4bkBoMwqh8leQgL++AtfYrIv9cglhcA2r0UKoc+xMFtWl YiCkUnaC4bRCNhLLUnBGPDODqRZMUJ9DyVBfD7oI13Ylt5h28SjD+E1jUwfUqXg32E2q VPQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ya11/VX/aRn7vG6mAkOVxrie0vDf0+2x0xJimT8Kw/s=; b=xQmvIN0uVAD7OKl4VS00yDvPfBzMI94FQCtTh/dCYaFsdqsVh4AqGMgtgoBc1LsikI hUNP/VE2UQjvAbzaaIFOO3dSD/0Fvy43NKHBQZRZPHUbebSoagvW0xuZ+cNBvshq1t+G EYnslOzF4ivTFYeu+2I+E3OewQ2YfZhtukpCTGSpCjWmwasG0x/TH+5eM5IXFOEv7i4i h0zSb+HP6f7K7+B8YvaL9f/BJnsIofdVQhjZYBKdtE/IK3Sg7pZtnGotrevjsumtAjMZ +TRz4EKTwPaJNzgp8qa0Kn4RMNYZiN3VqzXaYpSRONVm11lmDp9ikWP+j2jBNGd3R9Qd GgcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=I3cLjXuS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:29 -0700 Message-Id: <20190819213755.26175-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 42/68] target/arm: Simplify disas_thumb2_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Fold away all of the cases that now just goto illegal_op, because all of their internal bits are now in decodetree. Signed-off-by: Richard Henderson --- target/arm/translate.c | 79 ++---------------------------------------- 1 file changed, 3 insertions(+), 76 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index d1078ca1ec..25c74206c2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10433,9 +10433,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t rn; - int op; - /* * ARMv6-M supports a limited subset of Thumb2 instructions. * Other Thumb1 architectures allow only 32-bit @@ -10476,34 +10473,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } /* fall back to legacy decoder */ - rn = (insn >> 16) & 0xf; switch ((insn >> 25) & 0xf) { case 0: case 1: case 2: case 3: /* 16-bit instructions. Should never happen. */ abort(); - case 4: - /* All in decodetree */ - goto illegal_op; - case 5: - /* All in decodetree */ - goto illegal_op; - case 13: /* Misc data processing. */ - op = ((insn >> 22) & 6) | ((insn >> 7) & 1); - if (op < 4 && (insn & 0xf000) != 0xf000) - goto illegal_op; - switch (op) { - case 0: /* Register controlled shift, in decodetree */ - case 1: /* Sign/zero extend, in decodetree */ - case 2: /* SIMD add/subtract, in decodetree */ - case 3: /* Other data processing, in decodetree */ - goto illegal_op; - case 4: case 5: - /* 32-bit multiply. Sum of absolute differences, in decodetree */ - goto illegal_op; - case 6: case 7: /* 64-bit multiply, Divide, in decodetree */ - goto illegal_op; - } - break; case 6: case 7: case 14: case 15: /* Coprocessor. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { @@ -10532,6 +10505,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } if (arm_dc_feature(s, ARM_FEATURE_VFP)) { + uint32_t rn = (insn >> 16) & 0xf; TCGv_i32 fptr = load_reg(s, rn); if (extract32(insn, 20, 1)) { @@ -10590,50 +10564,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } } break; - case 8: case 9: case 10: case 11: - if (insn & (1 << 15)) { - /* Branches, misc control. */ - if (insn & 0x5000) { - /* Unconditional branch, in decodetree */ - goto illegal_op; - } else if (((insn >> 23) & 7) == 7) { - /* Misc control */ - if (insn & (1 << 13)) - goto illegal_op; - - if (insn & (1 << 26)) { - /* hvc, smc, in decodetree */ - goto illegal_op; - } else { - op = (insn >> 20) & 7; - switch (op) { - case 0: /* msr cpsr, in decodetree */ - case 1: /* msr spsr, in decodetree */ - goto illegal_op; - case 2: /* cps, nop-hint, in decodetree */ - goto illegal_op; - case 3: /* Special control operations, in decodetree */ - case 4: /* bxj, in decodetree */ - goto illegal_op; - case 5: /* Exception return. */ - case 6: /* MRS, in decodetree */ - case 7: /* MSR, in decodetree */ - goto illegal_op; - } - } - } else { - /* Conditional branch, in decodetree */ - goto illegal_op; - } - } else { - /* - * 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx - * - Data-processing (modified immediate, plain binary immediate) - * All in decodetree. - */ - goto illegal_op; - } - break; case 12: if ((insn & 0x01100000) == 0x01000000) { if (disas_neon_ls_insn(s, insn)) { @@ -10641,14 +10571,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } break; } - /* Load/store single data item, in decodetree */ goto illegal_op; default: - goto illegal_op; + illegal_op: + unallocated_encoding(s); } - return; -illegal_op: - unallocated_encoding(s); } static void disas_thumb_insn(DisasContext *s, uint32_t insn) From patchwork Mon Aug 19 21:37:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171710 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3561781ily; Mon, 19 Aug 2019 15:18:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqwNRw/zyIWdhZawcRQlPFYy1NFIh9yg2N5ZxpOkiVj6+3Yu4eQw32wt3L8jaeQndNbxpdi9 X-Received: by 2002:ac8:1807:: with SMTP id q7mr23201363qtj.180.1566253083064; Mon, 19 Aug 2019 15:18:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566253083; cv=none; d=google.com; s=arc-20160816; b=T8qHGurUm/n9fB8APXIKH06OKbnyOyafVTahOujTBl8k7Nr05a/GKhP3N+ybpXu5Cc E521Lnd1h7MldQD4cPQfbTo/V7eKpWQ/3Tv1XOFX/V3GouffqXNLdksOWTuHAtPcanxc OmuQcZLKFXgOws16uFBDHd8aG9OEfIRKXX+d2DdXpSsG7nNM2JTrb2dFcp0LJubnQHbN JI0BRyKvfFpId55WNPMP3nO180s4s2h9NakZdpPjce/x6OEmouEwNPxWd85Z5zotMmZc wTChUTPXfm15GskKmfScZqpk5e9Ms6CR6mQ90BOyBJXZIHjI9KMVBle3hsEmZhHfAp7O RrXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=c57Ge3veQfkyW7vksKvqnmVUD20AJ8LyQ3MkWHHu68w=; b=PWmddN1kpox4XFm/8LKnTZ/i174C0XOopwURM6mXwzHcgOQCBzPIBeFERy8l+JYyp4 5OHpKG6LbZVWPT1D3Gu3u3gGyH9Tn1u3FG2/kZwCBfZ1OjwH02AHqEQ6bsUsCaAZ12dI X8R+c3WH4ZEIkxkxudBAQ74hguqGo0Itw4aAbGKajtv6sKYfO3CxG3zod/PTxmKSgEue CSIfl0ioht68yUbmXk5y/vKbx/jNxT9KAK4LlDA2Us6CgcS06XKGBFulybwtkrvGyO/v Zw970CL/jAuqBZ07ImzPg2LjvX4U3DpzzYGxhLQhgHzPAOrp9XAgEgWb13k8Mr8jfMg3 OFEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DCwIxhDj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:30 -0700 Message-Id: <20190819213755.26175-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v2 43/68] target/arm: Simplify disas_arm_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Fold away all of the cases that now just goto illegal_op, because all of their internal bits are now in decodetree. Signed-off-by: Richard Henderson --- target/arm/translate.c | 69 ++++++++++-------------------------------- 1 file changed, 16 insertions(+), 53 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 25c74206c2..49bab7d863 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10245,7 +10245,7 @@ static bool trans_PLI(DisasContext *s, arg_PLD *a) static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, op1; + unsigned int cond = insn >> 28; /* M variants do not implement ARM mode; this must raise the INVSTATE * UsageFault exception. @@ -10255,7 +10255,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) default_exception_el(s)); return; } - cond = insn >> 28; if (cond == 0xf) { /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we @@ -10320,11 +10319,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) goto illegal_op; } return; - } else if ((insn & 0x0fe00000) == 0x0c400000) { - /* Coprocessor double register transfer. */ - ARCH(5TE); - } else if ((insn & 0x0f000010) == 0x0e000010) { - /* Additional coprocessor register transfer. */ } goto illegal_op; } @@ -10339,55 +10333,24 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } /* fall back to legacy decoder */ - if ((insn & 0x0f900000) == 0x03000000) { - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - } else if ((insn & 0x0f900000) == 0x01000000 - && (insn & 0x00000090) != 0x00000090) { - /* miscellaneous instructions */ - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - } else if (((insn & 0x0e000000) == 0 && - (insn & 0x00000090) != 0x90) || - ((insn & 0x0e000000) == (1 << 25))) { - /* Data-processing (reg, reg-shift-reg, imm). */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } else { - /* other instructions */ - op1 = (insn >> 24) & 0xf; - switch(op1) { - case 0x0: - case 0x1: - case 0x4: - case 0x5: - case 0x6: - case 0x7: - case 0x08: - case 0x09: - case 0xa: - case 0xb: - case 0xf: - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - case 0xc: - case 0xd: - case 0xe: - if (((insn >> 8) & 0xe) == 10) { - /* VFP. */ - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } - } else if (disas_coproc_insn(s, insn)) { - /* Coprocessor. */ + switch ((insn >> 24) & 0xf) { + case 0xc: + case 0xd: + case 0xe: + if (((insn >> 8) & 0xe) == 10) { + /* VFP. */ + if (disas_vfp_insn(s, insn)) { goto illegal_op; } - break; - default: - illegal_op: - unallocated_encoding(s); - break; + } else if (disas_coproc_insn(s, insn)) { + /* Coprocessor. */ + goto illegal_op; } + break; + default: + illegal_op: + unallocated_encoding(s); + break; } } From patchwork Mon Aug 19 21:37:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171706 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3558916ily; Mon, 19 Aug 2019 15:14:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqyrekA1aqZE0z9H4yFjFfl6x3SKxv2EoWHZRP87+NEwa7FVAAUApORFb2EvAA5TyZ3+hlpO X-Received: by 2002:ac8:6146:: with SMTP id d6mr23657371qtm.36.1566252890779; Mon, 19 Aug 2019 15:14:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566252890; cv=none; d=google.com; s=arc-20160816; b=R0dkbk6gpP1xWf7TEK/BGKvDkZHVxnYDxWdn/p4Pfnm+GcnYi7LXeCmbLT2IPYIMri SFokjoV0lx/PXdhlI9MHZEqGI3SuFoAe6LUNUAZGcmhEMpNyMWAdAhvhbZFeLxGgQ3Ck LTFv+XLFTp8b1IvihYu56ZtEWwxWTcam8Wk3beGKSLjQ3IkStnJ4FMDl9yTIZYFAD25I EB1j1p8uyikvwYOpsk6guSADvJBLNQPaNasopySRFnphy5Th8LMW7rtCi+KUO7j9xSEK fCnMtUf7nN74EG9Nbu9h/omOdtwuuVtnz4ZIS3DsBj0bwP2bIbE+oNPr9+2aOyNeCzYZ +s/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=BfxhiN9KVAYzZaSCSHTjQwUy5qzA5PRPe+BsdkgEMbc=; b=jy76EUlmarx3KyG6/G72aYyI9SFteJ0mK+0d6eYXW4aEmpDZY0iRU7GiWkwSeExoQ5 x6m5qn0Ph9FNVqY4yoOMxGKDtiFPMgT1AUFUOBEHQhb73MJu+oA1p5T6nGzj5rieCGNn Y9gvWwHPUQHj+V/cRpFteyUSkH1040SpY2Z/rAe0PnI4y8lJUERz7T40XwD37DQ6LjKe K7dZtOW0/Q0HdGMlkSGYZFkjz+zPU2sqBL/kvQneHZ5D5uhk/Pxp5IVnXS3B2QjfEYU/ dx0yPYWV3iG85iLfu8nIk6CqVHPZ8t72KrTUmHPSdDCuMIGUUpkwtlOvjP28Zr2kTq1r +Bxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YbWqlQ1F; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:31 -0700 Message-Id: <20190819213755.26175-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 44/68] target/arm: Add skeleton for T16 decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 6 ++++++ target/arm/Makefile.objs | 6 ++++++ target/arm/t16.decode | 20 ++++++++++++++++++++ 3 files changed, 32 insertions(+) create mode 100644 target/arm/t16.decode -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/translate.c b/target/arm/translate.c index 49bab7d863..90d608a2d2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7538,6 +7538,7 @@ static int t32_branch24(DisasContext *s, int x) #include "decode-a32.inc.c" #include "decode-a32-uncond.inc.c" #include "decode-t32.inc.c" +#include "decode-t16.inc.c" /* Helpers to swap operands for reverse-subtract. */ static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) @@ -10550,6 +10551,11 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) TCGv_i32 tmp2; TCGv_i32 addr; + if (disas_t16(s, insn)) { + return; + } + /* fall back to legacy decoder */ + switch (insn >> 12) { case 0: case 1: diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 7806b4dac0..cf26c16f5f 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -43,12 +43,18 @@ target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE) $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\ "GEN", $(TARGET_DIR)$@) +target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) -w 16 --static-decode disas_t16 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + target/arm/translate-sve.o: target/arm/decode-sve.inc.c target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c target/arm/translate.o: target/arm/decode-a32.inc.c target/arm/translate.o: target/arm/decode-a32-uncond.inc.c target/arm/translate.o: target/arm/decode-t32.inc.c +target/arm/translate.o: target/arm/decode-t16.inc.c obj-y += tlb_helper.o debug_helper.o obj-y += translate.o op_helper.o diff --git a/target/arm/t16.decode b/target/arm/t16.decode new file mode 100644 index 0000000000..e954f61fe4 --- /dev/null +++ b/target/arm/t16.decode @@ -0,0 +1,20 @@ +# Thumb1 instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# From patchwork Mon Aug 19 21:37:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171694 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3551402ily; Mon, 19 Aug 2019 15:06:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqzz+JW6JhFE9CD56339hsBjLogplQL+EBzMgqSN63FbEOD5d2omIieAFvBI7TRUWwaA8kXd X-Received: by 2002:ad4:4391:: with SMTP id s17mr3069084qvr.64.1566252390000; Mon, 19 Aug 2019 15:06:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566252389; cv=none; d=google.com; s=arc-20160816; b=eh+3kr9jxT3oZdIoBzkdTsBFeZXqdoPiaA7ZFDsAg0Lpwulxtk7KlF1H6DwB0Lk4b8 Ifuh2nG07Yu4p75ah7on8vZMDnubpYngR8mxX7/+Qicq5Od4MVIrawEKSowpUGq/Anlu WBPPbP1aoKAakA8lLoiNiVneTKDqcktXuSfWXLuId8/8CAzFhRAy3hJ8Swj7T/xjd7lY NRZevDRyz3hUmdxkrcPMF5aa2W2SvmntmXhVrQRG1wVvrOHASIJKq7+G5foLdnHfsIM5 qRDRzTbSyDhyCNfJungXiP0mIsRAeTwkW/hiYHINpfj1w2dmT3jOtKLf8fKz/CCEWVH1 orRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=NNqewFxAhp3TmNZYeBy2lNscR/CrnSrYWBFvc4ZcTG4=; b=MSQ9vC/1hIkUE7B4SobPu2U3o9alXz/JygzBCuFlMSOLjj54YfaxWtirIc9Xwu14/Y HtyaqNyVRAkakyoVDzcViTRO/L8vt3OTbg3EcyP4o2dz04iRTIrNH1D6p/zRnaYERkO9 gUfJtAZ3OruPuummjuaW0IiSTQvBSqDFpYthHpt4iCqEZezqymc51loxAfTn7sillRla 7fIKIkomWHIEpI3XPKaU0YjJJSmaIfOBLntin4ikhMdK961N6iMrzhF29zKHBnZWFvL7 aikHX9UdnGGrAywphXw8XDXGWCzJS+nCv4Z2inD1D3ytJLMP4WNYUVseYoo+ng4ZRJLn 5IFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=r5EwM5I9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:32 -0700 Message-Id: <20190819213755.26175-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v2 45/68] target/arm: Convert T16 data-processing (two low regs) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 152 ++--------------------------------------- target/arm/t16.decode | 36 ++++++++++ 2 files changed, 43 insertions(+), 145 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 90d608a2d2..7c5769bd42 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -445,13 +445,6 @@ static inline void gen_logic_CC(TCGv_i32 var) tcg_gen_mov_i32(cpu_ZF, var); } -/* T0 += T1 + CF. */ -static void gen_adc(TCGv_i32 t0, TCGv_i32 t1) -{ - tcg_gen_add_i32(t0, t0, t1); - tcg_gen_add_i32(t0, t0, cpu_CF); -} - /* dest = T0 + T1 + CF. */ static void gen_add_carry(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) { @@ -7531,6 +7524,11 @@ static int t32_branch24(DisasContext *s, int x) return x << 1; } +static int t16_setflags(DisasContext *s) +{ + return s->condexec_mask == 0; +} + /* * Include the generated decoders. */ @@ -10742,145 +10740,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) /* * 0b0100_00xx_xxxx_xxxx - * - Data-processing (two low registers) + * - Data-processing (two low registers), in decodetree */ - rd = insn & 7; - rm = (insn >> 3) & 7; - op = (insn >> 6) & 0xf; - if (op == 2 || op == 3 || op == 4 || op == 7) { - /* the shift/rotate ops want the operands backwards */ - val = rm; - rm = rd; - rd = val; - val = 1; - } else { - val = 0; - } - - if (op == 9) { /* neg */ - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else if (op != 0xf) { /* mvn doesn't read its first operand */ - tmp = load_reg(s, rd); - } else { - tmp = NULL; - } - - tmp2 = load_reg(s, rm); - switch (op) { - case 0x0: /* and */ - tcg_gen_and_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0x1: /* eor */ - tcg_gen_xor_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0x2: /* lsl */ - if (s->condexec_mask) { - gen_shl(tmp2, tmp2, tmp); - } else { - gen_helper_shl_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x3: /* lsr */ - if (s->condexec_mask) { - gen_shr(tmp2, tmp2, tmp); - } else { - gen_helper_shr_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x4: /* asr */ - if (s->condexec_mask) { - gen_sar(tmp2, tmp2, tmp); - } else { - gen_helper_sar_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x5: /* adc */ - if (s->condexec_mask) { - gen_adc(tmp, tmp2); - } else { - gen_adc_CC(tmp, tmp, tmp2); - } - break; - case 0x6: /* sbc */ - if (s->condexec_mask) { - gen_sub_carry(tmp, tmp, tmp2); - } else { - gen_sbc_CC(tmp, tmp, tmp2); - } - break; - case 0x7: /* ror */ - if (s->condexec_mask) { - tcg_gen_andi_i32(tmp, tmp, 0x1f); - tcg_gen_rotr_i32(tmp2, tmp2, tmp); - } else { - gen_helper_ror_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x8: /* tst */ - tcg_gen_and_i32(tmp, tmp, tmp2); - gen_logic_CC(tmp); - rd = 16; - break; - case 0x9: /* neg */ - if (s->condexec_mask) - tcg_gen_neg_i32(tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - break; - case 0xa: /* cmp */ - gen_sub_CC(tmp, tmp, tmp2); - rd = 16; - break; - case 0xb: /* cmn */ - gen_add_CC(tmp, tmp, tmp2); - rd = 16; - break; - case 0xc: /* orr */ - tcg_gen_or_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0xd: /* mul */ - tcg_gen_mul_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0xe: /* bic */ - tcg_gen_andc_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0xf: /* mvn */ - tcg_gen_not_i32(tmp2, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp2); - val = 1; - rm = rd; - break; - } - if (rd != 16) { - if (val) { - store_reg(s, rm, tmp2); - if (op != 0xf) - tcg_temp_free_i32(tmp); - } else { - store_reg(s, rd, tmp); - tcg_temp_free_i32(tmp2); - } - } else { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - } - break; + goto illegal_op; case 5: /* load/store register offset. */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index e954f61fe4..44e7250c55 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -18,3 +18,39 @@ # # This file is processed by scripts/decodetree.py # + +&s_rrr_shi !extern s rd rn rm shim shty +&s_rrr_shr !extern s rn rd rm rs shty +&s_rri_rot !extern s rn rd imm rot +&s_rrrr !extern s rd rn rm ra + +# Set S if the instruction is outside of an IT block. +%s !function=t16_setflags + +# Data-processing (two low registers) + +%reg_0 0:3 + +@lll_noshr ...... .... rm:3 rd:3 \ + &s_rrr_shi %s rn=%reg_0 shim=0 shty=0 +@xll_noshr ...... .... rm:3 rn:3 \ + &s_rrr_shi s=1 rd=0 shim=0 shty=0 +@lxl_shr ...... .... rs:3 rd:3 \ + &s_rrr_shr %s rm=%reg_0 rn=0 + +AND_rrri 010000 0000 ... ... @lll_noshr +EOR_rrri 010000 0001 ... ... @lll_noshr +MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL +MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR +MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR +ADC_rrri 010000 0101 ... ... @lll_noshr +SBC_rrri 010000 0110 ... ... @lll_noshr +MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR +TST_xrri 010000 1000 ... ... @xll_noshr +RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=0 rot=0 +CMP_xrri 010000 1010 ... ... @xll_noshr +CMN_xrri 010000 1011 ... ... @xll_noshr +ORR_rrri 010000 1100 ... ... @lll_noshr +MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0 +BIC_rrri 010000 1110 ... ... @lll_noshr +MVN_rxri 010000 1111 ... ... @lll_noshr From patchwork Mon Aug 19 21:37:33 2019 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 46/68] target/arm: Convert T16 load/store (register offset) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 51 ++---------------------------------------- target/arm/t16.decode | 15 +++++++++++++ 2 files changed, 17 insertions(+), 49 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 7c5769bd42..e19961fb6c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10745,55 +10745,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) goto illegal_op; case 5: - /* load/store register offset. */ - rd = insn & 7; - rn = (insn >> 3) & 7; - rm = (insn >> 6) & 7; - op = (insn >> 9) & 7; - addr = load_reg(s, rn); - tmp = load_reg(s, rm); - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - - if (op < 3) { /* store */ - tmp = load_reg(s, rd); - } else { - tmp = tcg_temp_new_i32(); - } - - switch (op) { - case 0: /* str */ - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 1: /* strh */ - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 2: /* strb */ - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 3: /* ldrsb */ - gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 4: /* ldr */ - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 5: /* ldrh */ - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 6: /* ldrb */ - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 7: /* ldrsh */ - gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - } - if (op >= 3) { /* load */ - store_reg(s, rd, tmp); - } else { - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; + /* load/store register offset, in decodetree */ + goto illegal_op; case 6: /* load/store word immediate offset */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 44e7250c55..83fe4363c7 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&ldst_rr !extern p w u rn rt rm shimm shtype # Set S if the instruction is outside of an IT block. %s !function=t16_setflags @@ -54,3 +55,17 @@ ORR_rrri 010000 1100 ... ... @lll_noshr MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0 BIC_rrri 010000 1110 ... ... @lll_noshr MVN_rxri 010000 1111 ... ... @lll_noshr + +# Load/store (register offset) + +@ldst_rr ....... rm:3 rn:3 rt:3 \ + &ldst_rr p=1 w=0 u=1 shimm=0 shtype=0 + +STR_rr 0101 000 ... ... ... @ldst_rr +STRH_rr 0101 001 ... ... ... @ldst_rr +STRB_rr 0101 010 ... ... ... @ldst_rr +LDRSB_rr 0101 011 ... ... ... @ldst_rr +LDR_rr 0101 100 ... ... ... @ldst_rr +LDRH_rr 0101 101 ... ... ... @ldst_rr +LDRB_rr 0101 110 ... ... ... @ldst_rr +LDRSH_rr 0101 111 ... ... ... @ldst_rr From patchwork Mon Aug 19 21:37:34 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:34 -0700 Message-Id: <20190819213755.26175-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v2 47/68] target/arm: Convert T16 load/store (immediate offset) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 94 +++--------------------------------------- target/arm/t16.decode | 33 +++++++++++++++ 2 files changed, 38 insertions(+), 89 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index e19961fb6c..24537fc107 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10744,97 +10744,13 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) */ goto illegal_op; - case 5: - /* load/store register offset, in decodetree */ + case 5: /* load/store register offset, in decodetree */ + case 6: /* load/store word immediate offset, in decodetree */ + case 7: /* load/store byte immediate offset, in decodetree */ + case 8: /* load/store halfword immediate offset, in decodetree */ + case 9: /* load/store from stack, in decodetree */ goto illegal_op; - case 6: - /* load/store word immediate offset */ - rd = insn & 7; - rn = (insn >> 3) & 7; - addr = load_reg(s, rn); - val = (insn >> 4) & 0x7c; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 7: - /* load/store byte immediate offset */ - rd = insn & 7; - rn = (insn >> 3) & 7; - addr = load_reg(s, rn); - val = (insn >> 6) & 0x1f; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 8: - /* load/store halfword immediate offset */ - rd = insn & 7; - rn = (insn >> 3) & 7; - addr = load_reg(s, rn); - val = (insn >> 5) & 0x3e; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 9: - /* load/store from stack */ - rd = (insn >> 8) & 7; - addr = load_reg(s, 13); - val = (insn & 0xff) * 4; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - case 10: /* * 0b1010_xxxx_xxxx_xxxx diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 83fe4363c7..1cf79789ac 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &ldst_rr !extern p w u rn rt rm shimm shtype +&ldst_ri !extern p w u rn rt imm # Set S if the instruction is outside of an IT block. %s !function=t16_setflags @@ -69,3 +70,35 @@ LDR_rr 0101 100 ... ... ... @ldst_rr LDRH_rr 0101 101 ... ... ... @ldst_rr LDRB_rr 0101 110 ... ... ... @ldst_rr LDRSH_rr 0101 111 ... ... ... @ldst_rr + +# Load/store word/byte (immediate offset) + +%imm5_6x4 6:5 !function=times_4 + +@ldst_ri_1 ..... imm:5 rn:3 rt:3 \ + &ldst_ri p=1 w=0 u=1 +@ldst_ri_4 ..... ..... rn:3 rt:3 \ + &ldst_ri p=1 w=0 u=1 imm=%imm5_6x4 + +STR_ri 01100 ..... ... ... @ldst_ri_4 +LDR_ri 01101 ..... ... ... @ldst_ri_4 +STRB_ri 01110 ..... ... ... @ldst_ri_1 +LDRB_ri 01111 ..... ... ... @ldst_ri_1 + +# Load/store halfword (immediate offset) + +%imm5_6x2 6:5 !function=times_2 +@ldst_ri_2 ..... ..... rn:3 rt:3 \ + &ldst_ri p=1 w=0 u=1 imm=%imm5_6x2 + +STRH_ri 10000 ..... ... ... @ldst_ri_2 +LDRH_ri 10001 ..... ... ... @ldst_ri_2 + +# Load/store (SP-relative) + +%imm8_0x4 0:8 !function=times_4 +@ldst_spec_i ..... rt:3 ........ \ + &ldst_ri p=1 w=0 u=1 imm=%imm8_0x4 + +STR_ri 10010 ... ........ @ldst_spec_i rn=13 +LDR_ri 10011 ... ........ @ldst_spec_i rn=13 From patchwork Mon Aug 19 21:37:35 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:35 -0700 Message-Id: <20190819213755.26175-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42f Subject: [Qemu-devel] [PATCH v2 48/68] target/arm: Convert T16 add pc/sp (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 12 +----------- target/arm/t16.decode | 7 +++++++ 2 files changed, 8 insertions(+), 11 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 24537fc107..2640f50fcf 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10749,19 +10749,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) case 7: /* load/store byte immediate offset, in decodetree */ case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ + case 10: /* add PC/SP (immediate), in decodetree */ goto illegal_op; - case 10: - /* - * 0b1010_xxxx_xxxx_xxxx - * - Add PC/SP (immediate) - */ - rd = (insn >> 8) & 7; - val = (insn & 0xff) * 4; - tmp = add_reg_for_lit(s, insn & (1 << 11) ? 13 : 15, val); - store_reg(s, rd, tmp); - break; - case 11: /* misc */ op = (insn >> 8) & 0xf; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 1cf79789ac..71b3e8f02e 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&ri !extern rd imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm @@ -102,3 +103,9 @@ LDRH_ri 10001 ..... ... ... @ldst_ri_2 STR_ri 10010 ... ........ @ldst_spec_i rn=13 LDR_ri 10011 ... ........ @ldst_spec_i rn=13 + +# Add PC/SP (immediate) + +ADR 10100 rd:3 ........ imm=%imm8_0x4 +ADD_rri 10101 rd:3 ........ \ + &s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP From patchwork Mon Aug 19 21:37:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171699 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3553973ily; Mon, 19 Aug 2019 15:09:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqwbX7V9r/fm6DOPG8btO6+YFFrqs8P0she7t70oAOWgeBfDLm7QgPjU9fT2wjqN0VeWLvxk X-Received: by 2002:a50:b4b4:: with SMTP id w49mr27058869edd.269.1566252545318; Mon, 19 Aug 2019 15:09:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566252545; cv=none; d=google.com; s=arc-20160816; b=hUAxekwTE2TEqTIfMIlVTFBhkciwfvtOde8i92GEAXIJmVsTNj9qJ8WCNU9Q3WO+ip S378MHHgwmvQUPHudwqeRI+DV33McpUH5h3owZWLUCWRP0rTaPPmAwi0gn5SHbnPz6U4 2kHvXDhciBYWp9li3vovvnTOa/sI6qCcbqdmw3z+TdQl0PYqKs8u76dnt4naT/VFuuuX WCK8PCWJ43LnNYKddsZZunMRjQTQTCs+gt8XiDoeEU87J+QrxZ/1N8o6EEY87LXrqZD2 v2NfB4du2ngHsRbunQpFVYl9kTAyLSEi8ZirRDR0zVYrEnlMzTvW15kezgfB2BqOEVu3 rUQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ciKrEcP+T8tnigUgJH1zluGMRq2FWUolUVP3r6kA9kc=; b=chMgCBSu0pE8gch00RPcgpumOVNH6ipQRV+0pWzvVmBpdx+G7Hvkp+0X6LzPFlrUk0 j/E2SMf+yfpXnzvmBbx2q08MEzB6eOtdHHs3xuR7xtbBKLlRJjxRIq0GJlIxFcKh2UQS BuDFzSntiHevdTWrKvk+M1PNhi4EDPj2DcXrkS9uNLi8pYfsn/7ghzWYuhLY6mgXaUaE iRiUQ1bjol/XU1u5nUBGMp7z2lorql2frHxbZ5lzI3Zpah9AB9VNOzN5K+fboEJNroe2 HgVeBIHsEpJNJbGENIFL4EDzW0D2xL/xNpFBueFBseYpGfnw5BuyWlMAqUUUcU+jE/XH rFJg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fe3pQIVm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:36 -0700 Message-Id: <20190819213755.26175-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v2 49/68] target/arm: Convert T16 load/store multiple X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 48 ++++++++---------------------------------- target/arm/t16.decode | 8 +++++++ 2 files changed, 17 insertions(+), 39 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 2640f50fcf..d417958b23 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9976,6 +9976,14 @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) return do_ldm(s, a, 2); } +static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a) +{ + /* Writeback is conditional on the base register not being loaded. */ + a->w = !(a->list & (1 << a->rn)); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return do_ldm(s, a, 1); +} + /* * Branch, branch with link */ @@ -10750,6 +10758,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ case 10: /* add PC/SP (immediate), in decodetree */ + case 12: /* load/store multiple, in decodetree */ goto illegal_op; case 11: @@ -10973,45 +10982,6 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) } break; - case 12: - { - /* load/store multiple */ - TCGv_i32 loaded_var = NULL; - rn = (insn >> 8) & 0x7; - addr = load_reg(s, rn); - for (i = 0; i < 8; i++) { - if (insn & (1 << i)) { - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i == rn) { - loaded_var = tmp; - } else { - store_reg(s, i, tmp); - } - } else { - /* store */ - tmp = load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - /* advance to the next address */ - tcg_gen_addi_i32(addr, addr, 4); - } - } - if ((insn & (1 << rn)) == 0) { - /* base reg not in list: base register writeback */ - store_reg(s, rn, addr); - } else { - /* base reg in list: if load, complete it now */ - if (insn & (1 << 11)) { - store_reg(s, rn, loaded_var); - } - tcg_temp_free_i32(addr); - } - break; - } case 13: /* conditional branch or swi */ cond = (insn >> 8) & 0xf; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 71b3e8f02e..a7a437f930 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -26,6 +26,7 @@ &ri !extern rd imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm +&ldst_block !extern rn i b u w list # Set S if the instruction is outside of an IT block. %s !function=t16_setflags @@ -109,3 +110,10 @@ LDR_ri 10011 ... ........ @ldst_spec_i rn=13 ADR 10100 rd:3 ........ imm=%imm8_0x4 ADD_rri 10101 rd:3 ........ \ &s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP + +# Load/store multiple + +@ldstm ..... rn:3 list:8 &ldst_block i=1 b=0 u=0 w=1 + +STM 11000 ... ........ @ldstm +LDM_t16 11001 ... ........ @ldstm From patchwork Mon Aug 19 21:37:37 2019 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 50/68] target/arm: Convert T16 add/sub (3 low, 2 low and imm) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 ++------------------------ target/arm/t16.decode | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 24 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index d417958b23..6f30415371 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10572,31 +10572,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) * 0b0001_1xxx_xxxx_xxxx * - Add, subtract (three low registers) * - Add, subtract (two low registers and immediate) + * In decodetree. */ - rn = (insn >> 3) & 7; - tmp = load_reg(s, rn); - if (insn & (1 << 10)) { - /* immediate */ - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, (insn >> 6) & 7); - } else { - /* reg */ - rm = (insn >> 6) & 7; - tmp2 = load_reg(s, rm); - } - if (insn & (1 << 9)) { - if (s->condexec_mask) - tcg_gen_sub_i32(tmp, tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - } else { - if (s->condexec_mask) - tcg_gen_add_i32(tmp, tmp, tmp2); - else - gen_add_CC(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); + goto illegal_op; } else { /* shift immediate */ rm = (insn >> 3) & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index a7a437f930..2b5f368d31 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -117,3 +117,19 @@ ADD_rri 10101 rd:3 ........ \ STM 11000 ... ........ @ldstm LDM_t16 11001 ... ........ @ldstm + +# Add/subtract (three low registers) + +@addsub_3 ....... rm:3 rn:3 rd:3 \ + &s_rrr_shi %s shim=0 shty=0 + +ADD_rrri 0001100 ... ... ... @addsub_3 +SUB_rrri 0001101 ... ... ... @addsub_3 + +# Add/subtract (two low registers and immediate) + +@addsub_2i ....... imm:3 rn:3 rd:3 \ + &s_rri_rot %s rot=0 + +ADD_rri 0001 110 ... ... ... @addsub_2i +SUB_rri 0001 111 ... ... ... @addsub_2i From patchwork Mon Aug 19 21:37:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171718 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3566646ily; Mon, 19 Aug 2019 15:24:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqwLy409OGy6r8L06ggburUUuRNFG7ElL/J3D9t9dJfuVa9Yd7JtMbgYSyrx1a8VAcqSdR8d X-Received: by 2002:a37:9802:: with SMTP id a2mr23077814qke.346.1566253478263; Mon, 19 Aug 2019 15:24:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566253478; cv=none; d=google.com; s=arc-20160816; b=CWkrKne6CuyHJ/MF6Ely6BHwma/zJhqlnJO0ySL/Vxn65eaOdfZ3B7/F33I4d+IKFz YbTN1neyUvB4aeWin3DiHAaMbR+N2gWYyLOxYgPQ5obUeLsBLsgQLFf4zCCjvJl+7n8Z rdboZL92qcU9x/tImZCMPvEpO3hX9bTD2GEA40IWT/0/Yqc1ikNIbgNPUZkg+ZnkK+Fy SFqJrbjW0mHJpq4EvqoFtnwle8MK23oTjt/WK8ZIa3484ELkuZDjYcrF4lmk5KA4GoDZ DL+WlUlXHTI5MD8pwVGffvBFWgRkS+Bfyp4luVv95XBKKwqVa6o0UPjqO3bLC6poDX2U QZhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=t3Sk/E++ZxrnmWMmhTr25Xzz1GIdoAzJpID10oiImmY=; b=FlFCOJa5dwo2k4i0h6sJsONHDQvsQLhNW/4joIZdKAYr185qpqT0KcGWbb/3t8ylgZ H+PkOtoq9XouoSWRqH6QxaHL+za15QgRP7S3rzKMeTuwtCKpUa86sgYx+ihuEVeyLoay VWfY6HUgbE33QrUZxrmsv0LjgxSfPNP1TKyl1wrIvlZnhktwfT4s10xfV6JPabIa7kVf 34Ku++VJB3geklnme0v/kQUAOyjm9RCoDsuM5gmuztO4g4gYAmrN8mDGD74kMxinvAxf rlCPxQL34WOEj9m1K3FPvj4XIpv8Weg3thqoh244RaOjt0KyGEi45P7bYGZYLKodzliR 3OBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ok3UFEdR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:38 -0700 Message-Id: <20190819213755.26175-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v2 51/68] target/arm: Convert T16 one low register and immediate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 44 ++---------------------------------------- target/arm/t16.decode | 11 +++++++++++ 2 files changed, 13 insertions(+), 42 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 6f30415371..3a3b113822 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10586,48 +10586,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) store_reg(s, rd, tmp); } break; - case 2: case 3: - /* - * 0b001x_xxxx_xxxx_xxxx - * - Add, subtract, compare, move (one low register and immediate) - */ - op = (insn >> 11) & 3; - rd = (insn >> 8) & 0x7; - if (op == 0) { /* mov */ - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, insn & 0xff); - if (!s->condexec_mask) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - } else { - tmp = load_reg(s, rd); - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, insn & 0xff); - switch (op) { - case 1: /* cmp */ - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - break; - case 2: /* add */ - if (s->condexec_mask) - tcg_gen_add_i32(tmp, tmp, tmp2); - else - gen_add_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; - case 3: /* sub */ - if (s->condexec_mask) - tcg_gen_sub_i32(tmp, tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; - } - } - break; + case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ + goto illegal_op; case 4: if (insn & (1 << 11)) { rd = (insn >> 8) & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 2b5f368d31..0654275e68 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -133,3 +133,14 @@ SUB_rrri 0001101 ... ... ... @addsub_3 ADD_rri 0001 110 ... ... ... @addsub_2i SUB_rri 0001 111 ... ... ... @addsub_2i + +# Add, subtract, compare, move (one low register and immediate) + +%reg_8 8:3 +@arith_1i ..... rd:3 imm:8 \ + &s_rri_rot rot=0 rn=%reg_8 + +MOV_rxi 00100 ... ........ @arith_1i %s +CMP_xri 00101 ... ........ @arith_1i s=1 +ADD_rri 00110 ... ........ @arith_1i %s +SUB_rri 00111 ... ........ @arith_1i %s From patchwork Mon Aug 19 21:37:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171719 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3567545ily; Mon, 19 Aug 2019 15:25:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqzy8rh6GzMORTduMfzmRIGfbB1DqkqXexJNAuLwwSgMWaYbeDC+dOeXIbxL42aT/IoXFIjr X-Received: by 2002:ad4:5661:: with SMTP id bm1mr12487804qvb.119.1566253551214; Mon, 19 Aug 2019 15:25:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566253551; cv=none; d=google.com; s=arc-20160816; b=ZVVl4GhyBh9b6WMj2BUCBVMfdm+awex81gCc7sR0pTXZ4/1Y4BRybC18RTDD5glWzP Z12ZAyeTulGyWVHEZfyYeXm8/e38RgM6zHbmpDKbh2BQwJTzzD6xVAkwVipoeqfP4UWK UnLnZ2WsFyLIUBrpf0ybeGiA+LGFFqQmLQG4Ps0e2GUSLUHEi6vNWRiZY/g7iGgJaS0O 7xQPRAUL7bpDh5u58cxqOtW7mUXFQYkk5kmdFmD4RQT+QMmYbfncSatQCn65iXJuxWjY DGtwCMl3S99ieZjGiJ4guGa15YlDP266R2hIlsGJLcL/FRZT5ci9fl0OKnsaUvYm9HHC v7ZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=xWTPQIHYecFzB/xCsq79DFxtQ/kqN477ghAb6EWu45A=; b=rhh+cczPaZd9iLzI/MkjHZbrYRXCKnXeHf7C912OaRp0D7RSxSIQirOs2lDPASXwU5 SHgS/HbYsjFHST2eLhfSzzPgzevFR1N3hBt3CYTmayn5BY082e7XjP3lJTBjna1cilIb STQxOFKheQAwa4U1kQEu/+5jqGwsum9v/75nXVQ3cWISfF6Lg6Tg3PZBeJ2KFQWzZzBB yaepZUMW8XU9tel5kGQkPD2dhKjQJ6tBgowylKDcGj1bMtkmKhLcZyxJqI7IobQisO6l nogQ2qDJQDFDmkKf1DpRfj3sL/DUZR5p9kqS8JaAKHhi6FTEAZAilSFBfEdpbNA1m128 Hsaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=e8BwcgYX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:39:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:39 -0700 Message-Id: <20190819213755.26175-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v2 52/68] target/arm: Convert T16 branch and exchange X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 64 +++++++++++++++--------------------------- target/arm/t16.decode | 10 +++++++ 2 files changed, 33 insertions(+), 41 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 3a3b113822..60bfc943a3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8335,7 +8335,7 @@ static bool trans_BX(DisasContext *s, arg_BX *a) if (!ENABLE_ARCH_4T) { return false; } - gen_bx(s, load_reg(s, a->rm)); + gen_bx_excret(s, load_reg(s, a->rm)); return true; } @@ -8362,6 +8362,26 @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a) return true; } +static bool trans_BXNS(DisasContext *s, arg_BXNS *a) +{ + if (!s->v8m_secure || IS_USER_ONLY) { + unallocated_encoding(s); + } else { + gen_bxns(s, a->rm); + } + return true; +} + +static bool trans_BLXNS(DisasContext *s, arg_BLXNS *a) +{ + if (!s->v8m_secure || IS_USER_ONLY) { + unallocated_encoding(s); + } else { + gen_blxns(s, a->rm); + } + return true; +} + static bool trans_CLZ(DisasContext *s, arg_CLZ *a) { TCGv_i32 tmp; @@ -10637,49 +10657,11 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) } break; case 3: - { /* 0b0100_0111_xxxx_xxxx * - branch [and link] exchange thumb register + * In decodetree */ - bool link = insn & (1 << 7); - - if (insn & 3) { - goto undef; - } - if (link) { - ARCH(5); - } - if ((insn & 4)) { - /* BXNS/BLXNS: only exists for v8M with the - * security extensions, and always UNDEF if NonSecure. - * We don't implement these in the user-only mode - * either (in theory you can use them from Secure User - * mode but they are too tied in to system emulation.) - */ - if (!s->v8m_secure || IS_USER_ONLY) { - goto undef; - } - if (link) { - gen_blxns(s, rm); - } else { - gen_bxns(s, rm); - } - break; - } - /* BLX/BX */ - tmp = load_reg(s, rm); - if (link) { - val = (uint32_t)s->base.pc_next | 1; - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, val); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - } else { - /* Only BX works as exception-return, not BLX */ - gen_bx_excret(s, tmp); - } - break; - } + goto illegal_op; } break; } diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 0654275e68..edddbfb9b8 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &ri !extern rd imm +&r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list @@ -144,3 +145,12 @@ MOV_rxi 00100 ... ........ @arith_1i %s CMP_xri 00101 ... ........ @arith_1i s=1 ADD_rri 00110 ... ........ @arith_1i %s SUB_rri 00111 ... ........ @arith_1i %s + +# Branch and exchange + +@branchr .... .... . rm:4 ... &r + +BX 0100 0111 0 .... 000 @branchr +BLX_r 0100 0111 1 .... 000 @branchr +BXNS 0100 0111 0 .... 100 @branchr +BLXNS 0100 0111 1 .... 100 @branchr From patchwork Mon Aug 19 21:37:40 2019 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 53/68] target/arm: Convert T16 add, compare, move (two high registers) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 49 ++---------------------------------------- target/arm/t16.decode | 10 +++++++++ 2 files changed, 12 insertions(+), 47 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 60bfc943a3..e639059a5a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10620,55 +10620,10 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) store_reg(s, rd, tmp); break; } - if (insn & (1 << 10)) { - /* 0b0100_01xx_xxxx_xxxx - * - data processing extended, branch and exchange - */ - rd = (insn & 7) | ((insn >> 4) & 8); - rm = (insn >> 3) & 0xf; - op = (insn >> 8) & 3; - switch (op) { - case 0: /* add */ - tmp = load_reg(s, rd); - tmp2 = load_reg(s, rm); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rd == 13) { - /* ADD SP, SP, reg */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } - break; - case 1: /* cmp */ - tmp = load_reg(s, rd); - tmp2 = load_reg(s, rm); - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - break; - case 2: /* mov/cpy */ - tmp = load_reg(s, rm); - if (rd == 13) { - /* MOV SP, reg */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } - break; - case 3: - /* 0b0100_0111_xxxx_xxxx - * - branch [and link] exchange thumb register - * In decodetree - */ - goto illegal_op; - } - break; - } /* - * 0b0100_00xx_xxxx_xxxx - * - Data-processing (two low registers), in decodetree + * - Data-processing (two low registers), in decodetree + * - data processing extended, branch and exchange, in decodetree */ goto illegal_op; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index edddbfb9b8..5a570484e3 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -146,6 +146,16 @@ CMP_xri 00101 ... ........ @arith_1i s=1 ADD_rri 00110 ... ........ @arith_1i %s SUB_rri 00111 ... ........ @arith_1i %s +# Add, compare, move (two high registers) + +%reg_0_7 7:1 0:3 +@addsub_2h .... .... . rm:4 ... \ + &s_rrr_shi rd=%reg_0_7 rn=%reg_0_7 shim=0 shty=0 + +ADD_rrri 0100 0100 . .... ... @addsub_2h s=0 +CMP_xrri 0100 0101 . .... ... @addsub_2h s=1 +MOV_rxri 0100 0110 . .... ... @addsub_2h s=0 + # Branch and exchange @branchr .... .... . rm:4 ... &r From patchwork Mon Aug 19 21:37:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171703 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3557004ily; Mon, 19 Aug 2019 15:12:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqxDaSoJ14VlVuO0A6+xmUjGAQiHI4sRcltpyO6PY4QSmKnfIC1t37qVvCnKHvw8B3d8Kidv X-Received: by 2002:a17:907:39a:: with SMTP id ss26mr23507296ejb.278.1566252746169; Mon, 19 Aug 2019 15:12:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566252746; cv=none; d=google.com; s=arc-20160816; b=ndbjKrJ/AIQuF96gQO2TthE2S73ns2IUHL8B78lrFRjYGz1z1AvQe4Ek6O9CmLvbKl EOqaG8+FPEy0tC0w6KrovHIfKK/5PQNl0H3hp9r92al+rH+cIXVttFY7k1sJNmyxc5IE 6HNy1N1iHKaVrLI7EzS0IOrQluNgGkPGFkEGa2lQZSag/OxPCjNB0d47KOaOmAuC1BLa PUzrcrG1bZ57ehOGdfKcL1UdcQmzy0rx9gnnpK3jkh0Z6v4V5iK82H92nK3GUwNbKz3y GQd0tQD1Qtxbas99Ewe7EH60zXfhnYgqAIzBrHnWSxpZt9NP5TltY8yWiAOOJYiolxkN fFfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=QRvE4bPnAygv+cSuTTykDcVWK0tGfB+nP3/t4TESwEQ=; b=utFVHMl5w2AXq0J3X+WwAiPo5sHkX5C1/g1rxhAxbC3hxU2tQjOXpjN2iNFd1VmjBD pfoIfoFTQNYCqvZKdM+/kT8zCVOzaQXSiRH/QevoUbq3SeLCzCGObQ7skJEqDGI+yWYi JRHA1sWOwcQvZtTMBgX5c1VYbpmzp9O3+pHxgofpA6cwmTBf6WvlP5RMSJf2lOPvsWg3 U4FU3p7l91e8ZNOiMZgpXG4MBS513AtzMiRhQB/ty7aPZ3Af9Dbwangn/kRQsiQPIsoE qHO2fOkFD80hqHupLLr7QH6xotU1hjj1w2zg7TDFtzVb948Os+QMnrS38vqxNAosS918 gwCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aGlqZbDF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v2 54/68] target/arm: Convert T16 adjust sp (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 15 ++------------- target/arm/t16.decode | 9 +++++++++ 2 files changed, 11 insertions(+), 13 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index e639059a5a..cac3893386 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10640,19 +10640,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) /* misc */ op = (insn >> 8) & 0xf; switch (op) { - case 0: - /* - * 0b1011_0000_xxxx_xxxx - * - ADD (SP plus immediate) - * - SUB (SP minus immediate) - */ - tmp = load_reg(s, 13); - val = (insn & 0x7f) * 4; - if (insn & (1 << 7)) - val = -(int32_t)val; - tcg_gen_addi_i32(tmp, tmp, val); - store_sp_checked(s, tmp); - break; + case 0: /* add/sub (sp, immediate), in decodetree */ + goto illegal_op; case 2: /* sign/zero extend. */ ARCH(6); diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 5a570484e3..b425b86795 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -156,6 +156,15 @@ ADD_rrri 0100 0100 . .... ... @addsub_2h s=0 CMP_xrri 0100 0101 . .... ... @addsub_2h s=1 MOV_rxri 0100 0110 . .... ... @addsub_2h s=0 +# Adjust SP (immediate) + +%imm7_0x4 0:7 !function=times_4 +@addsub_sp_i .... .... . ....... \ + &s_rri_rot s=0 rd=13 rn=13 rot=0 imm=%imm7_0x4 + +ADD_rri 1011 0000 0 ....... @addsub_sp_i +SUB_rri 1011 0000 1 ....... @addsub_sp_i + # Branch and exchange @branchr .... .... . rm:4 ... &r From patchwork Mon Aug 19 21:37:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171704 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3557935ily; Mon, 19 Aug 2019 15:13:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqzFFi8Jy+dRF+jx7+n8SmhWaYe4+mP2uYMz9H+I6NOf7+Ig0Q9/Y+NWjoTq/fK2++PvbaqW X-Received: by 2002:a17:906:4f1a:: with SMTP id t26mr23120990eju.174.1566252812176; Mon, 19 Aug 2019 15:13:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566252812; cv=none; d=google.com; s=arc-20160816; b=kiSIKsSQXzqbL1ehi0SmVpNBQAc+FFVNP0dqpYyWQS+cVehg2Amxx5lp/Iba4ZT/5D KSw7WR0oR+3Gt77rW9yxufXM5IlTb2W5/hUNH8ZGciRGnL60nGhcfgZLEjx9V1kdjTda FPOpJQKSnuBMXb103onrA4FyCFoTUvD0a0FoR9eOdKcN3kpCiS7AeLMVJw+9HnIi9eF4 fk5EbBfNlhwznLnJU7Rpp6lJV5+VBu3EyOKzq8wMsJKtCYqJQGF8ba6dENa3cY7XKhZd Kh/L0ue/yEUsKoOrgecM05riEWnwKfSmlZmE2cpWJfUEwv44AuluJCCaUBbGizhswyUh J0Lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=IoEU+NRa2JWhajyfKqrmJYRYOBCu04dzJDGI4c2fGqA=; b=xXHkaqfRIOziGMZX2w8ZepfPhNTMkH7wvd3lIqESE3PeLVNjP5WzqkwD6RyT1Qhb9m 79yMXgQm8NjFnKMgV/TaxIOIlpsZ2EQPssVW1KDJ9VF6T3QiZ966Q7BAWtlV1ulaMg8h qwvOPtNaAsaoMQ4VZhI0slYjxX78nCtLPbm3YPSwnsgTOatCXaDp8RNvmGCRrM/IAJ+M +1co1MB1+xNGuv6mQBCTkvIVi5cRZ1ks/bNxVHj00S0Xowre+V9BIebfObhLFFQtrrgw h1I8aXNMqLakP8+KpwlwhadmuOKk8tD+IONEkfbUxTEdkDc2Ve74LlW+EojBaBxNrBuj lZBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fVWboJtD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.39.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:39:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:42 -0700 Message-Id: <20190819213755.26175-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 55/68] target/arm: Convert T16, extract X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 14 +------------- target/arm/t16.decode | 10 ++++++++++ 2 files changed, 11 insertions(+), 13 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index cac3893386..414c562fb3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10641,21 +10641,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) op = (insn >> 8) & 0xf; switch (op) { case 0: /* add/sub (sp, immediate), in decodetree */ + case 2: /* sign/zero extend, in decodetree */ goto illegal_op; - case 2: /* sign/zero extend. */ - ARCH(6); - rd = insn & 7; - rm = (insn >> 3) & 7; - tmp = load_reg(s, rm); - switch ((insn >> 6) & 3) { - case 0: gen_sxth(tmp); break; - case 1: gen_sxtb(tmp); break; - case 2: gen_uxth(tmp); break; - case 3: gen_uxtb(tmp); break; - } - store_reg(s, rd, tmp); - break; case 4: case 5: case 0xc: case 0xd: /* * 0b1011_x10x_xxxx_xxxx diff --git a/target/arm/t16.decode b/target/arm/t16.decode index b425b86795..b5b5086e8a 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&rrr_rot !extern rd rn rm rot &ri !extern rd imm &r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype @@ -173,3 +174,12 @@ BX 0100 0111 0 .... 000 @branchr BLX_r 0100 0111 1 .... 000 @branchr BXNS 0100 0111 0 .... 100 @branchr BLXNS 0100 0111 1 .... 100 @branchr + +# Extend + +@extend .... .... .. rm:3 rd:3 &rrr_rot rn=15 rot=0 + +SXTAH 1011 0010 00 ... ... @extend +SXTAB 1011 0010 01 ... ... @extend +UXTAH 1011 0010 10 ... ... @extend +UXTAB 1011 0010 11 ... ... @extend From patchwork Mon Aug 19 21:37:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171707 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3560584ily; Mon, 19 Aug 2019 15:16:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqwO1r1e6P8yMyUOf6nfbjDDMUN4i+uudwkMgR7UixmJnWcOE/YaExseQyzoZl4RxVEi1RSL X-Received: by 2002:a17:906:b35a:: with SMTP id cd26mr22572465ejb.243.1566252997935; Mon, 19 Aug 2019 15:16:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566252997; cv=none; d=google.com; s=arc-20160816; b=fcEEL3SL85pJFyAx7/i6DvckjUzTZ6l9ILh36Y9/mPsN8vpfTUpjbrCHpwCRMXWbWX 7VqDDjgGSzCXX+1BZX735uzo4GajCK7Tb4Qhu61FrCa/VLazcrQzoLTozrhzTL8m9/zG mpD/qkifAmV8BNv0QkIfzl6eewsgOerbJ49Yf8Ox39t9FSJJFQR3vJX2648TwUpTD9d9 E7doZP7JBMqNxW6ZWDc/DWpyuI0icC0xKNgyNuB5Zo3o5SoH+46m5BBmDBUBkvZs6I/G KW00/D00bOMxucy/5LXUuUYURDNa69WF+VOJKEXKEQencLb4Fa/iOVA9DTX/VwT0NTCy Nvug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=mDWM/Osv7r5Ybg7vyJ1eX9OFfB4jiv5oRDsEzB095y0=; b=IUSQFbUwlLJK3+O8FLueBI9KJwdlJcbBCA2mBYIdeUXuwj6/OphKZnRFIMWxAJihrz ezWE73TWm8UBscWeB8DpPyVhef1svEK1O0ehBvuNYx3Wknoz3Y8NMqhvJkjhWbwNdTK7 SdGAZ9LEJ8+t+CN9F4LVpFgG+RdPxMt9c9P4DQHby7WhVZaQxgfWVrsRE4dyhqoMSFMJ dJhzKW17QOlAvmGoPJAlPHL1Jt7t+/A4NyMyzAJ8c5m/nCJGTgSZCO4UYw1050kOgRS/ 1ggcQ0Km9vUk8LChkACclgSZ1zvt86uJYVEqhnYYUPXnv3emSonYBdbHihrtODMcR46K 4wlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rwPNNUYq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.39.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:39:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:43 -0700 Message-Id: <20190819213755.26175-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v2 56/68] target/arm: Convert T16, Change processor state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 85 ++++++++++++++++++++---------------------- target/arm/t16.decode | 12 ++++++ 2 files changed, 52 insertions(+), 45 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 414c562fb3..368f0ab147 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7474,6 +7474,11 @@ static int negate(DisasContext *s, int x) return -x; } +static int plus_2(DisasContext *s, int x) +{ + return x + 2; +} + static int times_2(DisasContext *s, int x) { return x * 2; @@ -10152,6 +10157,9 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a) { uint32_t mask, val; + if (ENABLE_ARCH_6 && arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } if (IS_USER(s)) { /* Implemented as NOP in user mode. */ return true; @@ -10182,6 +10190,36 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a) return true; } +static bool trans_CPS_v6m(DisasContext *s, arg_CPS_v6m *a) +{ + TCGv_i32 tmp, addr; + + if (!(ENABLE_ARCH_6 && arm_dc_feature(s, ARM_FEATURE_M))) { + return false; + } + if (IS_USER(s)) { + /* Implemented as NOP in user mode. */ + return true; + } + + tmp = tcg_const_i32(a->im); + /* FAULTMASK */ + if (a->F) { + addr = tcg_const_i32(19); + gen_helper_v7m_msr(cpu_env, addr, tmp); + tcg_temp_free_i32(addr); + } + /* PRIMASK */ + if (a->I) { + addr = tcg_const_i32(16); + gen_helper_v7m_msr(cpu_env, addr, tmp); + tcg_temp_free_i32(addr); + } + tcg_temp_free_i32(tmp); + gen_lookup_tb(s); + return true; +} + /* * Clear-Exclusive, Barriers */ @@ -10783,51 +10821,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) break; } - case 6: - switch ((insn >> 5) & 7) { - case 2: - /* setend */ - ARCH(6); - if (((insn >> 3) & 1) != !!(s->be_data == MO_BE)) { - gen_helper_setend(cpu_env); - s->base.is_jmp = DISAS_UPDATE; - } - break; - case 3: - /* cps */ - ARCH(6); - if (IS_USER(s)) { - break; - } - if (arm_dc_feature(s, ARM_FEATURE_M)) { - tmp = tcg_const_i32((insn & (1 << 4)) != 0); - /* FAULTMASK */ - if (insn & 1) { - addr = tcg_const_i32(19); - gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); - } - /* PRIMASK */ - if (insn & 2) { - addr = tcg_const_i32(16); - gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); - } - tcg_temp_free_i32(tmp); - gen_lookup_tb(s); - } else { - if (insn & (1 << 4)) { - shift = CPSR_A | CPSR_I | CPSR_F; - } else { - shift = 0; - } - gen_set_psr_im(s, ((insn & 7) << 6), 0, shift); - } - break; - default: - goto undef; - } - break; + case 6: /* setend, cps; in decodetree */ + goto illegal_op; default: goto undef; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index b5b5086e8a..3bf1a31731 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -29,6 +29,8 @@ &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list +&setend !extern E +&cps !extern mode imod M A I F # Set S if the instruction is outside of an IT block. %s !function=t16_setflags @@ -183,3 +185,13 @@ SXTAH 1011 0010 00 ... ... @extend SXTAB 1011 0010 01 ... ... @extend UXTAH 1011 0010 10 ... ... @extend UXTAB 1011 0010 11 ... ... @extend + +# Change processor state + +%imod 4:1 !function=plus_2 + +SETEND 1011 0110 010 1 E:1 000 &setend +{ + CPS_v6m 1011 0110 011 im:1 00 I:1 F:1 + CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=0 M=0 %imod +} From patchwork Mon Aug 19 21:37:44 2019 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::52f Subject: [Qemu-devel] [PATCH v2 57/68] target/arm: Convert T16, Reverse bytes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 18 +++--------------- target/arm/t16.decode | 9 +++++++++ 2 files changed, 12 insertions(+), 15 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 368f0ab147..176cba2992 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10608,7 +10608,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rn, rd, shift, cond; + uint32_t val, op, rm, rd, shift, cond; int32_t offset; int i; TCGv_i32 tmp; @@ -10805,20 +10805,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) break; } - /* Otherwise this is rev */ - ARCH(6); - rn = (insn >> 3) & 0x7; - rd = insn & 0x7; - tmp = load_reg(s, rn); - switch (op1) { - case 0: tcg_gen_bswap32_i32(tmp, tmp); break; - case 1: gen_rev16(tmp, tmp); break; - case 3: gen_revsh(tmp, tmp); break; - default: - g_assert_not_reached(); - } - store_reg(s, rd, tmp); - break; + /* Otherwise this is rev, in decodetree */ + goto illegal_op; } case 6: /* setend, cps; in decodetree */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 3bf1a31731..ec21be7ef0 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrr_rot !extern rd rn rm rot +&rr !extern rd rm &ri !extern rd imm &r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype @@ -195,3 +196,11 @@ SETEND 1011 0110 010 1 E:1 000 &setend CPS_v6m 1011 0110 011 im:1 00 I:1 F:1 CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=0 M=0 %imod } + +# Reverse bytes + +@rdm .... .... .. rm:3 rd:3 &rr + +REV 1011 1010 00 ... ... @rdm +REV16 1011 1010 01 ... ... @rdm +REVSH 1011 1010 11 ... ... @rdm From patchwork Mon Aug 19 21:37:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171724 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3569557ily; Mon, 19 Aug 2019 15:28:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqz/7NZy2oKffjS2hmRjfhnVTZqxxUHP9oTU5MqYmBuax60lw5kL6R/UPMDHos2WKJG+L2zc X-Received: by 2002:a37:b4c4:: with SMTP id d187mr21955234qkf.459.1566253713937; Mon, 19 Aug 2019 15:28:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566253713; cv=none; d=google.com; s=arc-20160816; b=kPncGnqM5GmmVjrCsuQEuP6rwuQvSfj5SvV0FmEB0ScDZYGkXntEu1sBBtM5Y+GbiG TIVw5mYcQRqguO4kk6vPfulVlMk1O9Z7F4A0Duk/e3An01ted2OIHnDCtL+q6NgtfJpQ bNZ6UJ6uLu2goxqDszU7gz4KrSWpmn93n1BTBE5Kg8C5QKlxaLil/qdCjSWofVAWyjxB OTgTq6FYRefBDUsdeX3ic7RdhTrRx2Zea36xNriO2XICYdB36ONhsOQ1jjGJ9qTdkzBb /GdXWHK67K1WEjxk0fevPOYLsKNmDbKOghRwzJtMBzIxlHtmDAJftWhSSloFQNs73Tdd nA9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=JUuR6qD1PO3BvQ9lvZTub8abynQZibA90MasCzAeg3k=; b=CV2MMIKhXG4CSJLwc6EJNDNuyxr2++YrWgSYQj34ahSL5H+A3p0D4biBVKt6p40RVA ZhqVK162yOrNK7f/YFAyqI5LzIRnVZ0ivb/zzkpMukKF6b4X2YZd+GkkQhnMNGKLiBmZ CHUYStLITucdKy0pGjgdiycxL9DtFEy/voLwDGvqepEydp1TJukEzMSd1BjEFAgOrbWa kcYBCtG9xCZqG0hjKDKav6Kxsv/x3j7R3bb9ynYNDg5kj5HXF8FiPavo0kNIJa5cGvSv MIDtpWHjfTWyWTC+rgtfylglFtQz7MnfyhsR2wA7STEyebuNhvI3XRUnLjhdDku9VAiB q7aA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kK8uVJsI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v2 58/68] target/arm: Convert T16, nop hints X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 3 +-- target/arm/t16.decode | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 176cba2992..67f0202d29 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10769,8 +10769,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) case 15: /* IT, nop-hint. */ if ((insn & 0xf) == 0) { - gen_nop_hint(s, (insn >> 4) & 0xf); - break; + goto illegal_op; /* nop hint, in decodetree */ } /* * IT (If-Then) diff --git a/target/arm/t16.decode b/target/arm/t16.decode index ec21be7ef0..d5b046d105 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -19,6 +19,7 @@ # This file is processed by scripts/decodetree.py # +&empty !extern &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot @@ -204,3 +205,19 @@ SETEND 1011 0110 010 1 E:1 000 &setend REV 1011 1010 00 ... ... @rdm REV16 1011 1010 01 ... ... @rdm REVSH 1011 1010 11 ... ... @rdm + +# Hints + +{ + YIELD 1011 1111 0001 0000 + WFE 1011 1111 0010 0000 + WFI 1011 1111 0011 0000 + + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1011 1111 0100 0000 + # SEVL 1011 1111 0101 0000 + + # The canonical nop has the second nibble as 0000, but the whole of the + # rest of the space is a reserved hint, behaves as nop. + NOP 1011 1111 ---- 0000 +} From patchwork Mon Aug 19 21:37:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171708 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3560702ily; Mon, 19 Aug 2019 15:16:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqwLmL1haIREgDA2GANYfaL8LM2BGjx+8BCcSJ7DVinOs8hlTUOO6ao0ouI9aiVz6KYyKZ6h X-Received: by 2002:a50:8981:: with SMTP id g1mr28275770edg.53.1566253006065; Mon, 19 Aug 2019 15:16:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566253006; cv=none; d=google.com; s=arc-20160816; b=hnInV8squUMw3qzDhZjM/MUzJOcTNHIF/bExttKa0Xt1ArQjTVUSNYuBR1OnJ6Boou iQSNbAUr+lW1l2TBBJvPH+k5PqJm+h9ptdUrIYOlcdHy9llqQyHTUYUEVctabuloTyf6 aM+vfUk+svuS/gW5xp0h8U3zm1L81dd3PGZG88sxxPGU0N9l8OMEJjdHd7+MM2thcx3c wxwqIW7i6ZkoY2iiwLr0OlR9E87rsbzj5vdUqM3Fws1l1OGHUAP+hPfi6v0ICG8OOlUA D+qvo/yNSC9hFfxuolpz4ioEDMGR++tUjmHlkOIQr3h2Pxa05YqjWUOa6v+MNbk37pgj rkXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=MSRdVhU7JG8W/BPDMD9yM4+AFvL57yq4+jCtr5it5qs=; b=Esq1121Q2pofHk8rHjEnOW4cqfJwWiYKsK4HASM5PmzHG3S3YLHONsyJ7Da4FFTqry jqRh6AfN70CFUPNgJtQRKfG6uhLBXnhhx7FYneMbkx8LOcBtx4LWbmjfRPm2B9V8bEVn Z/iEjiBp+AL0vx4GzQtRrssIk6Tl739w447UvEwb6OWk0otfw7OnM4PNL6nWqpuU98mN R90aaJ5DeZEurvWmkkemmO3T8ySN4ERt0ODgT8CnN2BAXPH5P3a2tZs+mY66mxKheFBs 1bY/IAxCRHyNOPbhdztrMuyPBb/mgX3J83PJt1X+scxv3P6palfFfMHdsHMjEjWU7IJA a0Ig== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MfNrJqun; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.39.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:39:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:46 -0700 Message-Id: <20190819213755.26175-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 59/68] target/arm: Split gen_nop_hint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that there all callers pass a constant value, split the switch statement into the individual trans_* functions. Signed-off-by: Richard Henderson --- target/arm/translate.c | 67 +++++++++++++++--------------------------- 1 file changed, 24 insertions(+), 43 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 67f0202d29..9e0345adf7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3045,46 +3045,6 @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc) gen_rfe(s, pc, load_cpu_field(spsr)); } -/* - * For WFI we will halt the vCPU until an IRQ. For WFE and YIELD we - * only call the helper when running single threaded TCG code to ensure - * the next round-robin scheduled vCPU gets a crack. In MTTCG mode we - * just skip this instruction. Currently the SEV/SEVL instructions - * which are *one* of many ways to wake the CPU from WFE are not - * implemented so we can't sleep like WFI does. - */ -static void gen_nop_hint(DisasContext *s, int val) -{ - switch (val) { - /* When running in MTTCG we don't generate jumps to the yield and - * WFE helpers as it won't affect the scheduling of other vCPUs. - * If we wanted to more completely model WFE/SEV so we don't busy - * spin unnecessarily we would need to do something more involved. - */ - case 1: /* yield */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_set_pc_im(s, s->base.pc_next); - s->base.is_jmp = DISAS_YIELD; - } - break; - case 3: /* wfi */ - gen_set_pc_im(s, s->base.pc_next); - s->base.is_jmp = DISAS_WFI; - break; - case 2: /* wfe */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_set_pc_im(s, s->base.pc_next); - s->base.is_jmp = DISAS_WFE; - } - break; - case 4: /* sev */ - case 5: /* sevl */ - /* TODO: Implement SEV, SEVL and WFE. May help SMP performance. */ - default: /* nop */ - break; - } -} - #define CPU_V001 cpu_V0, cpu_V0, cpu_V1 static inline void gen_neon_add(int size, TCGv_i32 t0, TCGv_i32 t1) @@ -8165,19 +8125,40 @@ DO_SMLAWX(SMLAWT, 1, 1) static bool trans_YIELD(DisasContext *s, arg_YIELD *a) { - gen_nop_hint(s, 1); + /* + * When running single-threaded TCG code, use the helper to ensure that + * the next round-robin scheduled vCPU gets a crack. When running in + * MTTCG we don't generate jumps to the helper as it won't affect the + * scheduling of other vCPUs. + */ + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_set_pc_im(s, s->base.pc_next); + s->base.is_jmp = DISAS_YIELD; + } return true; } static bool trans_WFE(DisasContext *s, arg_WFE *a) { - gen_nop_hint(s, 2); + /* + * When running single-threaded TCG code, use the helper to ensure that + * the next round-robin scheduled vCPU gets a crack. In MTTCG mode we + * just skip this instruction. Currently the SEV/SEVL instructions, + * which are *one* of many ways to wake the CPU from WFE, are not + * implemented so we can't sleep like WFI does. + */ + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_set_pc_im(s, s->base.pc_next); + s->base.is_jmp = DISAS_WFE; + } return true; } static bool trans_WFI(DisasContext *s, arg_WFI *a) { - gen_nop_hint(s, 3); + /* For WFI, halt the vCPU until an IRQ. */ + gen_set_pc_im(s, s->base.pc_next); + s->base.is_jmp = DISAS_WFI; return true; } From patchwork Mon Aug 19 21:37:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171711 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3562378ily; Mon, 19 Aug 2019 15:18:49 -0700 (PDT) X-Google-Smtp-Source: APXvYqx2FAvefdQNoTwD4gI8WcX7NlcH0rtB08Oe20VCng7OaUcs8aXALSIsTDAxoYpRcbbE3Zad X-Received: by 2002:a37:a388:: with SMTP id m130mr23871916qke.250.1566253129703; Mon, 19 Aug 2019 15:18:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566253129; cv=none; d=google.com; s=arc-20160816; b=cnlVvRwg8OHkb0oYs7z35t8goxQ6jh3u+iDsXvqst1/d9MIdL0sjImJkmQr6c8Ca82 fDR+Kqg8NlugBgxTB4TTp1Wk4y3/jJmcTlXClRbLKSLWCcr+2S+my0kfQYcBsC4hBJuZ 2/A0QG2tjnyS+kGpoczVqIGv4+8kHlhH/pcCdqTFdBC/w/2zucwhF48T7zd4L/5s66wV QW88BSiunNRkT4CHWrjzPVL6y6KIfrtvPVPkf0QRqG1TVAUsZ0I/KIW1XzcoRyqW/nAe IqyFTB34AC2CqagoEUDrTkFn09XnYqxMtVvD4sdNd/9/UbDpXK31rnFWGP4mXWxY7lS1 2yYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Ltc+Iekt5p0qb7H2sxDb1ZsirxTTtPcO/0Q5mx5ZDAc=; b=Q/ZtHIqC71m9O8XAA57fBPNrF5PWRbt/wqPouEsv3BzaTMz9q2Dh/2eOh/6KzZrdPk n4SURzYtba4BKKj37zO0OlmdysjFBuifPhy3PvsCFX3Wgfigr6wpj5SVD7oa96+9+DEb veKznNS5pZev05gcAaO51XXFTwsOeL0RNDCrqzdL94sXKchBCDZuOoEbsYfm32449QeX MMbhPZAGvXl1eNVcC2OnUjQp4DYR7mlPOJXxQnBCIsYM7mk9AQPZcg86CBtFyet3FR3Q 8g0a1eFDtZCRBAykFhgzJkqvAd+Fl+EE/bI5jVjJtmeQVHSZGvcYS9ljZ+pPD+HIgIWC U1gg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AOqI2pBL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::52a Subject: [Qemu-devel] [PATCH v2 60/68] target/arm: Convert T16, push and pop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 83 ++++++------------------------------------ target/arm/t16.decode | 10 +++++ 2 files changed, 22 insertions(+), 71 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 9e0345adf7..5f876290ba 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7494,6 +7494,16 @@ static int t16_setflags(DisasContext *s) return s->condexec_mask == 0; } +static int t16_push_list(DisasContext *s, int x) +{ + return (x & 0xff) | (x & 0x100) << (14 - 8); +} + +static int t16_pop_list(DisasContext *s, int x) +{ + return (x & 0xff) | (x & 0x100) << (15 - 8); +} + /* * Include the generated decoders. */ @@ -10591,7 +10601,6 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) { uint32_t val, op, rm, rd, shift, cond; int32_t offset; - int i; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -10664,76 +10673,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) goto illegal_op; case 4: case 5: case 0xc: case 0xd: - /* - * 0b1011_x10x_xxxx_xxxx - * - push/pop - */ - addr = load_reg(s, 13); - if (insn & (1 << 8)) - offset = 4; - else - offset = 0; - for (i = 0; i < 8; i++) { - if (insn & (1 << i)) - offset += 4; - } - if ((insn & (1 << 11)) == 0) { - tcg_gen_addi_i32(addr, addr, -offset); - } - - if (s->v8m_stackcheck) { - /* - * Here 'addr' is the lower of "old SP" and "new SP"; - * if this is a pop that starts below the limit and ends - * above it, it is UNKNOWN whether the limit check triggers; - * we choose to trigger. - */ - gen_helper_v8m_stackcheck(cpu_env, addr); - } - - for (i = 0; i < 8; i++) { - if (insn & (1 << i)) { - if (insn & (1 << 11)) { - /* pop */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, i, tmp); - } else { - /* push */ - tmp = load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - /* advance to the next address. */ - tcg_gen_addi_i32(addr, addr, 4); - } - } - tmp = NULL; - if (insn & (1 << 8)) { - if (insn & (1 << 11)) { - /* pop pc */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - /* don't set the pc until the rest of the instruction - has completed */ - } else { - /* push lr */ - tmp = load_reg(s, 14); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_gen_addi_i32(addr, addr, 4); - } - if ((insn & (1 << 11)) == 0) { - tcg_gen_addi_i32(addr, addr, -offset); - } - /* write back the new stack pointer */ - store_reg(s, 13, addr); - /* set the new PC value */ - if ((insn & 0x0900) == 0x0900) { - store_reg_from_load(s, 15, tmp); - } - break; + /* push/pop, in decodetree */ + goto illegal_op; case 1: case 3: case 9: case 11: /* czb */ rm = insn & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index d5b046d105..d731402036 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -221,3 +221,13 @@ REVSH 1011 1010 11 ... ... @rdm # rest of the space is a reserved hint, behaves as nop. NOP 1011 1111 ---- 0000 } + +# Push and Pop + +%push_list 0:9 !function=t16_push_list +%pop_list 0:9 !function=t16_pop_list + +STM 1011 010 ......... \ + &ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list +LDM_t16 1011 110 ......... \ + &ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list From patchwork Mon Aug 19 21:37:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171720 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3567672ily; Mon, 19 Aug 2019 15:26:01 -0700 (PDT) X-Google-Smtp-Source: APXvYqxfjXmpsGs2MSkUqp4aqNFLy67NMXW/soYoLVpjZRzpRNc047ma2iR8h2cpqdDBr7H7pRNu X-Received: by 2002:a0c:b281:: with SMTP id r1mr12478620qve.53.1566253561205; Mon, 19 Aug 2019 15:26:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566253561; cv=none; d=google.com; s=arc-20160816; b=dNBjNpOku+3/hSiXFLplyG9LvAcgZfoZr6hbmOebEG/Hju1g6zoOrR3/2vwmOUZzIl XvgF493gf+C5FXHl8vKBttw9S7Xi6+QjlrrIktU/Ag0RRVbjXkvGNOBsLnJ0+Ebq9oyG VnkvcbzzSYjwHxTODeScdxvcHLS+CWwhepYaIJic269R3bLk9A6/lARw63GSfFZPB0av LU+vmo6VTOwqF+VAszN8i1HODqNuyKWSyVd+N6z/1s8gbHlpxDJodeW6jKB10Mc+7IOu H260N8Q2rKH0DgoyXvoyhlZDefFVdk/jevw8d/1Vs6ZpJzYqPYvTLGP0cldXAOcLivoL 9g+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=M247+waxxQ2hFTPZWsca/mTPO3c20Nu5WDueYuMimjE=; b=D5JeZ+xrIftOhipqpSRtCfd2cCNvZa5H4iWSTAT/PW4QuGwwpah+FsWYoR6UOdq/K2 HSen5BauuPPxWiz4d2UxRuWTmOH5kckX3g1fhscDnbI+wr8h1ohUpTp+wzrAgYD8KI9u NmBUaT0yq4ht6VmuYYmnrpcwOtnL7tjIdeLQzB4pueqshkS89eGEHRtCXuJSRchpqXuQ kj2L/fXc3jxLIykYn1ifZ1lRW4rUp19Xo9t6ghMmnaYvZTRfFr4oGXGHISRl9bT9h7mM niYOgqfcH3I6pqGUG0Lj68UTGW35yA/pIjx/nvmpofeKxGnIsmBHB3Bcy6K1Chxz8Ui0 Z6IA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AandmyT7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.39.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:39:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:48 -0700 Message-Id: <20190819213755.26175-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 61/68] target/arm: Convert T16, Conditional branches, Supervisor call X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 +++----------------------- target/arm/t16.decode | 12 ++++++++++++ 2 files changed, 15 insertions(+), 23 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 5f876290ba..941266df14 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10599,7 +10599,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rd, shift, cond; + uint32_t val, op, rm, rd, shift; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10738,28 +10738,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) } break; - case 13: - /* conditional branch or swi */ - cond = (insn >> 8) & 0xf; - if (cond == 0xe) - goto undef; - - if (cond == 0xf) { - /* swi */ - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm = extract32(insn, 0, 8); - s->base.is_jmp = DISAS_SWI; - break; - } - /* generate a conditional jump to next instruction */ - arm_skip_unless(s, cond); - - /* jump to the offset */ - val = read_pc(s); - offset = ((int32_t)insn << 24) >> 24; - val += offset << 1; - gen_jmp(s, val); - break; + case 13: /* conditional branch or swi, in decodetree */ + goto illegal_op; case 14: if (insn & (1 << 11)) { diff --git a/target/arm/t16.decode b/target/arm/t16.decode index d731402036..98d60952a1 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -28,11 +28,13 @@ &rr !extern rd rm &ri !extern rd imm &r !extern rm +&i !extern imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list &setend !extern E &cps !extern mode imod M A I F +&ci !extern cond imm # Set S if the instruction is outside of an IT block. %s !function=t16_setflags @@ -231,3 +233,13 @@ STM 1011 010 ......... \ &ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list LDM_t16 1011 110 ......... \ &ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list + +# Conditional branches, Supervisor call + +%imm8_0x2 0:s8 !function=times_2 + +{ + UDF 1101 1110 ---- ---- + SVC 1101 1111 imm:8 &i + B_cond_thumb 1101 cond:4 ........ &ci imm=%imm8_0x2 +} From patchwork Mon Aug 19 21:37:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171722 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3568534ily; Mon, 19 Aug 2019 15:27:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqzvuwL+UxZYP1cWDaqNjPhndi4Lx5px+ayHf94KKnc8zyO9OlNyhwE6Sovj57JlxzCtpAUf X-Received: by 2002:a17:906:11da:: with SMTP id o26mr23496537eja.64.1566253633313; Mon, 19 Aug 2019 15:27:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566253633; cv=none; d=google.com; s=arc-20160816; b=ZTdEa++5seTIdcMz4p0iMAy2cjf8E2aOpF/kwhTttxIPz31oUwRXHq3yjnmHbBH1sk aWmUn1wk9XuAXziTQnU1SQx+Rd9e9QNBCAeB4toUJcFAkeOog8oMhJ5FWwmaL8HAj7HO Ph6DbjNbu66sJ5Fl564z7EF0qyX5POMiY2w71Z1+4WDnXiowlZd+wpFtGRO9BzOYxY27 5TayRFVfhSa/4Y22KWqu3YkvQpqE6n91nAINuq0k1lbJ+BO44FZFZpeWMyUkcaAeNDpZ 4r6mHjip6e/i0z3lK8waHVpyAuzYd3u4bSmZ9SCat/8ja7Crr1U1k2NvEjY0pFcxiB/A u08w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=EJyW8b8UYEXRGkuf/Ca0ZoUaQassWgEv4Qo6kd6MUJ0=; b=Xz/ihqm55H+burOVNmnC6wkW6WBwRoXPVeYdzYAsWFm94G+RALfTtVTeRcmXqu3Ono f/VG39BPNB6X7yYiyNNUo73Z+tz022Y0Jdzms1hOtNzoOx5Wy7Gb+MPk9bYk/NahRpmD xEZFIBTkZP/EmOKKFGCXwuKyg9YYtyWXigeeltfJy8zDSCLhHoKG8b3DCYye+kcY9CkA FKhJqk54nczzUInKBF3ujCdGNgywj4JDXZCuEEP/7XbY4WfWy2kG6KxW4vA0bPEf/V4n kFbqjD71peu4ZkXwwTZ4JA0mpxH4Ibkt3AfQQbEe+JwWY1E0tA24DBMYjavribKkfVHg zIyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IwEdf4oS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.39.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:39:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:49 -0700 Message-Id: <20190819213755.26175-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 62/68] target/arm: Convert T16, Miscellaneous 16-bit instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 109 ++++++++++++----------------------------- target/arm/t16.decode | 31 ++++++++---- 2 files changed, 54 insertions(+), 86 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 941266df14..dc670c9724 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10074,6 +10074,18 @@ static bool trans_TBH(DisasContext *s, arg_tbranch *a) return op_tbranch(s, a, true); } +static bool trans_CBZ(DisasContext *s, arg_CBZ *a) +{ + TCGv_i32 tmp = load_reg(s, a->rn); + + arm_gen_condlabel(s); + tcg_gen_brcondi_i32(a->nz ? TCG_COND_EQ : TCG_COND_NE, + tmp, 0, s->condlabel); + tcg_temp_free_i32(tmp); + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + /* * Supervisor call */ @@ -10295,6 +10307,25 @@ static bool trans_PLI(DisasContext *s, arg_PLD *a) return ENABLE_ARCH_7; } +/* + * If-then + */ + +static bool trans_IT(DisasContext *s, arg_IT *a) +{ + /* + * No actual code generated for this insn, just setup state. + * + * Combinations of firstcond and mask which set up an 0b1111 + * condition are UNPREDICTABLE; we take the CONSTRAINED + * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110, + * i.e. both meaning "execute always". + */ + s->condexec_cond = a->cond; + s->condexec_mask = a->imm; + return true; +} + /* * Legacy decoder. */ @@ -10661,83 +10692,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ case 10: /* add PC/SP (immediate), in decodetree */ + case 11: /* misc, in decodetree */ case 12: /* load/store multiple, in decodetree */ - goto illegal_op; - - case 11: - /* misc */ - op = (insn >> 8) & 0xf; - switch (op) { - case 0: /* add/sub (sp, immediate), in decodetree */ - case 2: /* sign/zero extend, in decodetree */ - goto illegal_op; - - case 4: case 5: case 0xc: case 0xd: - /* push/pop, in decodetree */ - goto illegal_op; - - case 1: case 3: case 9: case 11: /* czb */ - rm = insn & 7; - tmp = load_reg(s, rm); - arm_gen_condlabel(s); - if (insn & (1 << 11)) - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel); - else - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel); - tcg_temp_free_i32(tmp); - offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3; - gen_jmp(s, read_pc(s) + offset); - break; - - case 15: /* IT, nop-hint. */ - if ((insn & 0xf) == 0) { - goto illegal_op; /* nop hint, in decodetree */ - } - /* - * IT (If-Then) - * - * Combinations of firstcond and mask which set up an 0b1111 - * condition are UNPREDICTABLE; we take the CONSTRAINED - * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110, - * i.e. both meaning "execute always". - */ - s->condexec_cond = (insn >> 4) & 0xe; - s->condexec_mask = insn & 0x1f; - /* No actual code generated for this insn, just setup state. */ - break; - - case 0xe: /* bkpt */ - { - int imm8 = extract32(insn, 0, 8); - ARCH(5); - gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true)); - break; - } - - case 0xa: /* rev, and hlt */ - { - int op1 = extract32(insn, 6, 2); - - if (op1 == 2) { - /* HLT */ - int imm6 = extract32(insn, 0, 6); - - gen_hlt(s, imm6); - break; - } - - /* Otherwise this is rev, in decodetree */ - goto illegal_op; - } - - case 6: /* setend, cps; in decodetree */ - goto illegal_op; - - default: - goto undef; - } - break; - case 13: /* conditional branch or swi, in decodetree */ goto illegal_op; @@ -10793,7 +10749,6 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) } return; illegal_op: -undef: unallocated_encoding(s); } diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 98d60952a1..4ecbabd364 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -210,20 +210,33 @@ REVSH 1011 1010 11 ... ... @rdm # Hints +%it_cond 5:3 !function=times_2 + { - YIELD 1011 1111 0001 0000 - WFE 1011 1111 0010 0000 - WFI 1011 1111 0011 0000 + { + YIELD 1011 1111 0001 0000 + WFE 1011 1111 0010 0000 + WFI 1011 1111 0011 0000 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1011 1111 0100 0000 - # SEVL 1011 1111 0101 0000 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1011 1111 0100 0000 + # SEVL 1011 1111 0101 0000 - # The canonical nop has the second nibble as 0000, but the whole of the - # rest of the space is a reserved hint, behaves as nop. - NOP 1011 1111 ---- 0000 + # The canonical nop has the second nibble as 0000, but the whole of the + # rest of the space is a reserved hint, behaves as nop. + NOP 1011 1111 ---- 0000 + } + IT 1011 1111 ... imm:5 &ci cond=%it_cond } +# Miscellaneous 16-bit instructions + +%imm6_9_3 9:1 3:5 !function=times_2 + +HLT 1011 1010 10 imm:6 &i +BKPT 1011 1110 imm:8 &i +CBZ 1011 nz:1 0.1 ..... rn:3 imm=%imm6_9_3 + # Push and Pop %push_list 0:9 !function=t16_push_list From patchwork Mon Aug 19 21:37:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171723 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3569251ily; 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X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v2 63/68] target/arm: Convert T16, shift immediate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 ++------------------------ target/arm/t16.decode | 8 ++++++++ 2 files changed, 10 insertions(+), 24 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index dc670c9724..dc3c9049cd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10630,7 +10630,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rd, shift; + uint32_t val, rd; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10642,29 +10642,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) /* fall back to legacy decoder */ switch (insn >> 12) { - case 0: case 1: - - rd = insn & 7; - op = (insn >> 11) & 3; - if (op == 3) { - /* - * 0b0001_1xxx_xxxx_xxxx - * - Add, subtract (three low registers) - * - Add, subtract (two low registers and immediate) - * In decodetree. - */ - goto illegal_op; - } else { - /* shift immediate */ - rm = (insn >> 3) & 7; - shift = (insn >> 6) & 0x1f; - tmp = load_reg(s, rm); - gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0); - if (!s->condexec_mask) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - } - break; + case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */ case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ goto illegal_op; case 4: diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 4ecbabd364..1adad20804 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -126,6 +126,14 @@ ADD_rri 10101 rd:3 ........ \ STM 11000 ... ........ @ldstm LDM_t16 11001 ... ........ @ldstm +# Shift (immediate) + +@shift_i ..... shim:5 rm:3 rd:3 &s_rrr_shi %s rn=%reg_0 + +MOV_rxri 000 00 ..... ... ... @shift_i shty=0 # LSL +MOV_rxri 000 01 ..... ... ... @shift_i shty=1 # LSR +MOV_rxri 000 10 ..... ... ... @shift_i shty=2 # ASR + # Add/subtract (three low registers) @addsub_3 ....... rm:3 rn:3 rd:3 \ From patchwork Mon Aug 19 21:37:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171712 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3562924ily; Mon, 19 Aug 2019 15:19:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqyTAeMehF7b8Be8mJdEiYrxNQblwZcxBV1P+Z6tYtTnG/ShckJYVkNT1uSzFTNnxGn1oXW2 X-Received: by 2002:a37:a9d1:: with SMTP id s200mr22007730qke.301.1566253168869; Mon, 19 Aug 2019 15:19:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566253168; cv=none; d=google.com; s=arc-20160816; b=lZ67F9B46FHKdtvU000unDqsiKCbd6FVpBII6egSr8yT5Eb5ZL33zICxXY8TQYztrn IywpCb8l9UPJk+XIRfIBDknXnL9eAozZB/+cq7mzpGEWHkpw+R4JlNE3AOBZezOYs/h2 DXESQc1ucuVhyl8TfymIiXJXPVHct1rUE2k9R3Rdw6wRM9NygU90VyYBJj7G3ocBsfgu WIHmJhWOUI8xHLMAgjWCxaK4SE6dO8SLalWDzs412P/spWtDONFuwfeB3GIyS8244kyJ LEYFqkaSXRwQ0HE2ckd29XvVFvImav+j0JAfCFVJ24vyITBk7boS5wx4H1wQd9FWbiz7 eWlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=GQyk/IPAzG6M9shM4zauPndvY+PKuQRptTNum9FjIF4=; b=jZ7Z3mA3GAeJxsqLdq64eFqmqbeqTL4OVz+KzVihNSjISSWoMW4590osBHljcd5EAz huFWOBkuEXDHS1Vx++2rOZLPdb3il6vfiVftygEO9F2XQHwfvuyYH2qzMGeb/XGz/8T3 D8LGRdEcT5ZebPFpljE4ntqYAEMJVOAltN1NUcrtC3BApk9EcwcDQtTGB7xXRN5dy7tH L/iJtI8Fz0zWH2Q1pK9DEOmpPLBWwnM29F7syT83/8hQNnmN2IBv2ngY6EbgicqIY29j dm9S8k2A+zKsIoDuQ3Ad2mcBBCrGdGhW5Qi0DIWngfXQ8RqEJCwlKoRxajLPvb1A9ay5 t2Dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=U1Wa2Jjk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 64/68] target/arm: Convert T16, load (literal) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 42 ++---------------------------------------- target/arm/t16.decode | 4 ++++ 2 files changed, 6 insertions(+), 40 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index dc3c9049cd..1882057402 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -963,14 +963,6 @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ TCGv_i32 a32, int index) \ { \ gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \ -} \ -static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s, \ - TCGv_i32 val, \ - TCGv_i32 a32, int index, \ - ISSInfo issinfo) \ -{ \ - gen_aa32_ld##SUFF(s, val, a32, index); \ - disas_set_da_iss(s, OPC, issinfo); \ } #define DO_GEN_ST(SUFF, OPC) \ @@ -978,14 +970,6 @@ static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ TCGv_i32 a32, int index) \ { \ gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \ -} \ -static inline void gen_aa32_st##SUFF##_iss(DisasContext *s, \ - TCGv_i32 val, \ - TCGv_i32 a32, int index, \ - ISSInfo issinfo) \ -{ \ - gen_aa32_st##SUFF(s, val, a32, index); \ - disas_set_da_iss(s, OPC, issinfo | ISSIsWrite); \ } static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val) @@ -1034,9 +1018,7 @@ static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data); } -DO_GEN_LD(8s, MO_SB) DO_GEN_LD(8u, MO_UB) -DO_GEN_LD(16s, MO_SW) DO_GEN_LD(16u, MO_UW) DO_GEN_LD(32u, MO_UL) DO_GEN_ST(8, MO_UB) @@ -10630,11 +10612,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, rd; + uint32_t val; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; - TCGv_i32 addr; if (disas_t16(s, insn)) { return; @@ -10644,26 +10625,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) switch (insn >> 12) { case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */ case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ - goto illegal_op; - case 4: - if (insn & (1 << 11)) { - rd = (insn >> 8) & 7; - /* load pc-relative. Bit 1 of PC is ignored. */ - addr = add_reg_for_lit(s, 15, (insn & 0xff) * 4); - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), - rd | ISSIs16Bit); - tcg_temp_free_i32(addr); - store_reg(s, rd, tmp); - break; - } - - /* - * - Data-processing (two low registers), in decodetree - * - data processing extended, branch and exchange, in decodetree - */ - goto illegal_op; - + case 4: /* ldr lit, data proc (2reg), data proc ext, bx; in decodetree */ case 5: /* load/store register offset, in decodetree */ case 6: /* load/store word immediate offset, in decodetree */ case 7: /* load/store byte immediate offset, in decodetree */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 1adad20804..f87e6fde50 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -113,6 +113,10 @@ LDRH_ri 10001 ..... ... ... @ldst_ri_2 STR_ri 10010 ... ........ @ldst_spec_i rn=13 LDR_ri 10011 ... ........ @ldst_spec_i rn=13 +# Load (PC-relative) + +LDR_ri 01001 ... ........ @ldst_spec_i rn=15 + # Add PC/SP (immediate) ADR 10100 rd:3 ........ imm=%imm8_0x4 From patchwork Mon Aug 19 21:37:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171725 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3570648ily; Mon, 19 Aug 2019 15:30:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqzXnKSCEMwumI1Z2OLIHNzK7TYzJ9r4O5A/adzKv+p082TUAF75l5J7xlhS3IJSy98vZRAw X-Received: by 2002:ac8:4a0d:: with SMTP id x13mr22497698qtq.356.1566253805039; Mon, 19 Aug 2019 15:30:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566253805; cv=none; d=google.com; s=arc-20160816; b=1GXj4xXx5jCkNhD/exvx4F6J57xJrax1JpjzUJ6F4e71rT9WBv+K5/fvpJvBEeKr+0 uhUBFbEYpp+dENR4jn+8IRIBgBZzqsSz7gB+wTx5sIhKAPUx1SunUTxG5J87PnrMlJ0r hyNWRy0KV6ffkbitdnNDW4HbYNk323eIUOegr25DMZ1MXk6B54+PlSJ15ozd0G55Y2WI xsXjiby68nvdrjn8dzLCZvN/3mIxny2V+RTEQ3NonBuCjhCe6Sp7YYVcs8skbTLXYTw8 Isi48Pr4M+dxlG/bwoS1xIwipTHTNsM7pGH+kHdzCAHUdDMZdXqdNgsdVve2TYWL6SRZ UqBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=F8Uj+UTtvG6sIw1y6R0jwFOyJpam+CLYahliKmILVI4=; b=OvzV3Df9+jqQ8+lT5H4gy/DIJ2CMbqU4FzA4qzoe2KqYvgeA23JXDy0ewhPkH+A9/k FpvdV9U9T+ae4njDNMiYeeN2syy0l9RS7W1fE+8Oz139kjw+Xmhzsjox+spQqN5qGek7 TtHweOgFWPsjEUyOH0johDwKOjkSsVg19YjXl7/ZFvTAOfyZhGd3JsyoExJrYEdEgky7 NqqfAXLA9zl7p5rmt2EJd7P+DXBUMNNvOrcHLaWGbJEkpvw9WKRLCIclqA6UBy5XH0i3 AyuyA3EbYgNdOp26tl2cyZGUj4SbuO4IM3nzlhLbEc4iRdYdJud6flExI7RMd8DbnR29 /BQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=irfuP3oR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.39.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:39:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:52 -0700 Message-Id: <20190819213755.26175-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42e Subject: [Qemu-devel] [PATCH v2 65/68] target/arm: Convert T16, Unconditional branch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 9 ++------- target/arm/t16.decode | 6 ++++++ 2 files changed, 8 insertions(+), 7 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 1882057402..51b14d409f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10612,7 +10612,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10656,12 +10655,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) gen_bx(s, tmp); break; } - /* unconditional branch */ - val = read_pc(s); - offset = ((int32_t)insn << 21) >> 21; - val += offset << 1; - gen_jmp(s, val); - break; + /* unconditional branch, in decodetree */ + goto illegal_op; case 15: /* thumb_insn_is_16bit() ensures we can't get here for diff --git a/target/arm/t16.decode b/target/arm/t16.decode index f87e6fde50..35a5b03118 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -268,3 +268,9 @@ LDM_t16 1011 110 ......... \ SVC 1101 1111 imm:8 &i B_cond_thumb 1101 cond:4 ........ &ci imm=%imm8_0x2 } + +# Unconditional Branch + +%imm11_0x2 0:s11 !function=times_2 + +B 11100 ........... &i imm=%imm11_0x2 From patchwork Mon Aug 19 21:37:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171726 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3571656ily; Mon, 19 Aug 2019 15:31:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqxAZWKOqGYoK+VY5Dwcy47FD9pRFB0hR3igUpN4TN7cCZS2gs+bG3OqANvsnZFY8cuy7Ah9 X-Received: by 2002:a17:906:a89a:: with SMTP id ha26mr22557010ejb.110.1566253868697; Mon, 19 Aug 2019 15:31:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566253868; cv=none; d=google.com; s=arc-20160816; b=QlklJ0MtdbhD9riDCe7MPxrHw5eMjieU1Qg05Y5gA6N2nsZEykjYlYgZRXfrNrAAA/ RmrlVnT8cgGhQBHCwLUoW/1VyYrsCYhu79TNBb2bSVgJgHipCBOW59ow9yjrNy5Ubru+ op3299yINYllpzWOXZ7COLUgFLBqPrXRIQBBwar9jBrUCE5rzon1FHSQ1ipQj5SKVPZM uWIMP2ihfr37kJ3yfzeCpS6TPGquwTYztxexOUwBFoIMLmMKiR/+2D37Zb8RwlXNvsvD wZfMsch/S61gwiOILdgMvzCIZAT3IIINpmP2C5UG20xCVP6+qdDMKXjCNx3PKcWa/PDo Srpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=CE2MOpYeaURMh2McMQcADxkv9nuiol4iRofGvabxWa4=; b=SBX8YNuW3MN3k88pU1UBOA7Pgob55yw7NPduH5Pyuzha5HJ/7w8sggWpg+DK6fk4yO BdH34urmzJJqbknT2hrQ5FYsAiy/LbCzjY9od/YhrsGiNJ3AXKF12cDho5u1R37TvRhw y+6uMz9uzpwyoTeea5C+bfWsS67ZNCMgKo0cLbGqj3HvMJKoGjkRcZViMC1Tg+7f5WIc QjC/ClFraOkBxvSBqw9bFoG1C35FUTsw8LLj3DOwUznHa48LBHMDZSIeOLet0wxX5LXK G83LcEko30LSFWe2L/ILqaYwcVqvPfUCwhBgAZoaH1w0lpLK2qIVzVpAQAlXGJhliCeZ AgbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bHPuMY7A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.39.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:39:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:53 -0700 Message-Id: <20190819213755.26175-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52a Subject: [Qemu-devel] [PATCH v2 66/68] target/arm: Convert T16, long branches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 89 +++++++++++++++++++----------------------- target/arm/t16.decode | 3 ++ 2 files changed, 43 insertions(+), 49 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 51b14d409f..f8997a8424 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10025,6 +10025,44 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) return true; } +static bool trans_BL_BLX_prefix(DisasContext *s, arg_BL_BLX_prefix *a) +{ + /* + * thumb_insn_is_16bit() ensures we can't get here for + * a Thumb2 CPU, so this must be a thumb1 split BL/BLX. + */ + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); + tcg_gen_movi_i32(cpu_R[14], read_pc(s) + (a->imm << 12)); + return true; +} + +static bool trans_BL_suffix(DisasContext *s, arg_BL_suffix *a) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); + tcg_gen_addi_i32(tmp, cpu_R[14], (a->imm << 1) | 1); + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); + gen_bx(s, tmp); + return true; +} + +static bool trans_BLX_suffix(DisasContext *s, arg_BLX_suffix *a) +{ + TCGv_i32 tmp; + + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); + if (!ENABLE_ARCH_5) { + return false; + } + tmp = tcg_temp_new_i32(); + tcg_gen_addi_i32(tmp, cpu_R[14], a->imm << 1); + tcg_gen_andi_i32(tmp, tmp, -4); + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); + gen_bx(s, tmp); + return true; +} + static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) { TCGv_i32 addr, tmp; @@ -10612,10 +10650,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - int32_t offset; - TCGv_i32 tmp; - TCGv_i32 tmp2; - if (disas_t16(s, insn)) { return; } @@ -10634,53 +10668,10 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) case 11: /* misc, in decodetree */ case 12: /* load/store multiple, in decodetree */ case 13: /* conditional branch or swi, in decodetree */ - goto illegal_op; - case 14: - if (insn & (1 << 11)) { - /* thumb_insn_is_16bit() ensures we can't get here for - * a Thumb2 CPU, so this must be a thumb1 split BL/BLX: - * 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF) - */ - assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); - ARCH(5); - offset = ((insn & 0x7ff) << 1); - tmp = load_reg(s, 14); - tcg_gen_addi_i32(tmp, tmp, offset); - tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); - - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, s->base.pc_next | 1); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - break; - } - /* unconditional branch, in decodetree */ - goto illegal_op; - case 15: - /* thumb_insn_is_16bit() ensures we can't get here for - * a Thumb2 CPU, so this must be a thumb1 split BL/BLX. - */ - assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); - - if (insn & (1 << 11)) { - /* 0b1111_1xxx_xxxx_xxxx : BL suffix */ - offset = ((insn & 0x7ff) << 1) | 1; - tmp = load_reg(s, 14); - tcg_gen_addi_i32(tmp, tmp, offset); - - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, s->base.pc_next | 1); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - } else { - /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */ - uint32_t uoffset = ((int32_t)insn << 21) >> 9; - - tcg_gen_movi_i32(cpu_R[14], read_pc(s) + uoffset); - } - break; + /* branches, in decodetree */ + goto illegal_op; } return; illegal_op: diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 35a5b03118..5ee8457efb 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -274,3 +274,6 @@ LDM_t16 1011 110 ......... \ %imm11_0x2 0:s11 !function=times_2 B 11100 ........... &i imm=%imm11_0x2 +BLX_suffix 11101 imm:11 &i +BL_BLX_prefix 11110 imm:s11 &i +BL_suffix 11111 imm:11 &i From patchwork Mon Aug 19 21:37:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171727 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3572169ily; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.39.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:39:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:54 -0700 Message-Id: <20190819213755.26175-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 67/68] target/arm: Clean up disas_thumb_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that everything is converted, remove the rest of the legacy decode. Signed-off-by: Richard Henderson --- target/arm/translate.c | 27 ++------------------------- 1 file changed, 2 insertions(+), 25 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index f8997a8424..bac38e6261 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10650,32 +10650,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - if (disas_t16(s, insn)) { - return; + if (!disas_t16(s, insn)) { + unallocated_encoding(s); } - /* fall back to legacy decoder */ - - switch (insn >> 12) { - case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */ - case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ - case 4: /* ldr lit, data proc (2reg), data proc ext, bx; in decodetree */ - case 5: /* load/store register offset, in decodetree */ - case 6: /* load/store word immediate offset, in decodetree */ - case 7: /* load/store byte immediate offset, in decodetree */ - case 8: /* load/store halfword immediate offset, in decodetree */ - case 9: /* load/store from stack, in decodetree */ - case 10: /* add PC/SP (immediate), in decodetree */ - case 11: /* misc, in decodetree */ - case 12: /* load/store multiple, in decodetree */ - case 13: /* conditional branch or swi, in decodetree */ - case 14: - case 15: - /* branches, in decodetree */ - goto illegal_op; - } - return; -illegal_op: - unallocated_encoding(s); } static bool insn_crosses_page(CPUARMState *env, DisasContext *s) From patchwork Mon Aug 19 21:37:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171728 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3573119ily; Mon, 19 Aug 2019 15:32:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqzQm7Mz/aVPAfyCxEuhB0PgcVuwY4Ok9CBlWt3ia1MxsYVi8fx2Or1gJBlbpYCKrlzozOpD X-Received: by 2002:a17:906:841a:: with SMTP id n26mr23550640ejx.181.1566253967504; Mon, 19 Aug 2019 15:32:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566253967; cv=none; d=google.com; s=arc-20160816; b=cCfmF6j8l/vOV0b+SPencJ/UD+yVfGz1gV+793Ytufnvj14HQQQGoFMrOgqKxJyjmJ MZFt4ZTAZkw4RlYsRLP5HfuBU5q4mOhbdpQDOs26nXTnbHkLgTvvQZ+4OLMTV9M7TIze BqpjgcASjJf281E3YR1qwQnwEZJPJpFtb5mXpUd9dMw0zns1K7atO5meRWdh10JoMiXU ajyZHJt6xgT9v4flOAfvMPwEpn3jypuI1Z4ghGoBBNG7nDxa1bJcOWHSgIRoJW9obWW3 cEpV2alQZl11pVix1CZVU14YMsIFnPz2oVHvcRGbbL79GLlwwHSU5OOoKHEBJGu+9lyq /LyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=pOrmu4hSyVv/uT8dsNEbfV+BcoCBHIkgixiHAKgiaBE=; b=O1Eg5M1+Nl2p0ImnOLzDf7ALlqYOLozEW1StLpH5SAggMX/Qirgf7JLMM/aaRBL/tG Y1a9UxqVNYyfyHYgYnW9lEAoV21uht8enw3s+uQ6tozO3q74uCYSGHMZZqg598eJqHhH 6BMb8ssHDWeLoVVSFp7GaxgToU5wv6p01gjnb9asBhlQ5o9/buNiNQxo4k3jE4g3j048 f1j8BcT/UA7zfyct2c8JwF2CmMXMtAW+GTzaOfmr1tO0+uWO7TQWtZ5GXyPdf+bDtUKx Jaqh3xiNLy6pMJ5E7WFR9H0YTCkW12Kx50SWjmkJuILLlmdZjkMUN7xMhOeGkOhaBAcN 2zjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=szYWKgnb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.39.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:39:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:55 -0700 Message-Id: <20190819213755.26175-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 68/68] target/arm: Inline gen_bx_im into callers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There are only two remaining uses of gen_bx_im. In each case, we know the destination mode -- not changing in the case of gen_jmp or changing in the case of trans_BLX_i. Use this to simplify the surrounding code. For trans_BLX_i, use gen_jmp for the actual branch. For gen_jmp, use gen_set_pc_im to set up the single-step. Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 +++++++------------------- 1 file changed, 7 insertions(+), 19 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index bac38e6261..9162ad113a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -765,21 +765,6 @@ static inline void gen_set_pc_im(DisasContext *s, target_ulong val) tcg_gen_movi_i32(cpu_R[15], val); } -/* Set PC and Thumb state from an immediate address. */ -static inline void gen_bx_im(DisasContext *s, uint32_t addr) -{ - TCGv_i32 tmp; - - s->base.is_jmp = DISAS_JUMP; - if (s->thumb != (addr & 1)) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, addr & 1); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, thumb)); - tcg_temp_free_i32(tmp); - } - tcg_gen_movi_i32(cpu_R[15], addr & ~1); -} - /* Set PC and Thumb state from var. var is marked as dead. */ static inline void gen_bx(DisasContext *s, TCGv_i32 var) { @@ -2706,9 +2691,8 @@ static inline void gen_jmp (DisasContext *s, uint32_t dest) { if (unlikely(is_singlestepping(s))) { /* An indirect jump so that we still trigger the debug exception. */ - if (s->thumb) - dest |= 1; - gen_bx_im(s, dest); + gen_set_pc_im(s, dest); + s->base.is_jmp = DISAS_JUMP; } else { gen_goto_tb(s, 0, dest); } @@ -10016,12 +10000,16 @@ static bool trans_BL(DisasContext *s, arg_i *a) static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) { + TCGv_i32 tmp; + /* For A32, ARCH(5) is checked near the start of the uncond block. */ if (s->thumb && (a->imm & 2)) { return false; } tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); - gen_bx_im(s, (read_pc(s) & ~3) + a->imm + !s->thumb); + tmp = tcg_const_i32(!s->thumb); + store_cpu_field(tmp, thumb); + gen_jmp(s, (read_pc(s) & ~3) + a->imm); return true; }