From patchwork Thu Nov 23 11:38:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suraj Jaiswal X-Patchwork-Id: 746596 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="FTPmFASt" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35BFDD49; Thu, 23 Nov 2023 03:39:04 -0800 (PST) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AN7GGeb017205; Thu, 23 Nov 2023 11:38:52 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=/HMvisoKKdxErewtmk40Y03V2X0AbT3pYgpBbk9Rjm0=; b=FTPmFAStJQvWCXT2JqgjETF98n35+85+FhhC6cdOFjW7NJIPSQAjSW7Vk+3++cO5Jh5P WehfG11ilifcqIrbWByqi9seXkmlz8uIMhSZCoiF7Y/cwtbVG9sgJDK434fImaqFdq50 77nCb3ry0uxR4IIFMa/jzhJRtIfY9WMhjRLbsf5jF7mQwHmjOG3pcloVMTtxNT8JddJq Pv25Ax2zKCe9kl9HNe2XxEVfVldXecY+9n10n03ltcZ+y9Y0bhAvbTiRhvBxhgflbkwC 5rqq/RwPZ3L9Lsbf1ZZq8p0p+QYSz2KJJ7XRh76XGDGs/zseIrTRZOZ/L7eS76CXh7Ri fg== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uhf6ku4xj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Nov 2023 11:38:51 +0000 Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3ANBcoHw001075 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Nov 2023 11:38:50 GMT Received: from hu-jsuraj-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 23 Nov 2023 03:38:40 -0800 From: Suraj Jaiswal To: , Vinod Koul , Bhupesh Sharma , Andy Gross , Bjorn Andersson , Konrad Dybcio , "David S. Miller" , Eric Dumazet , "Jakub Kicinski" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Alexandre Torgue , "Jose Abreu" , Maxime Coquelin , , , , , , Prasad Sodagudi , Andrew Halaney CC: Subject: [PATCH net-next v3 1/3] dt-bindings: net: qcom,ethqos: add binding doc for fault IRQ for sa8775p Date: Thu, 23 Nov 2023 17:08:13 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: b_LEfvE0nJH2UYhSEG3J1ox4TGf0wXYC X-Proofpoint-ORIG-GUID: b_LEfvE0nJH2UYhSEG3J1ox4TGf0wXYC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-23_09,2023-11-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 priorityscore=1501 clxscore=1015 adultscore=0 mlxlogscore=904 spamscore=0 suspectscore=0 impostorscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311230083 Add binding doc for fault IRQ. The fault IRQ will be trigger for ECC,DPP,FSM error. Signed-off-by: Suraj Jaiswal --- Documentation/devicetree/bindings/net/qcom,ethqos.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/qcom,ethqos.yaml b/Documentation/devicetree/bindings/net/qcom,ethqos.yaml index 7bdb412a0185..e013cb51fb07 100644 --- a/Documentation/devicetree/bindings/net/qcom,ethqos.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ethqos.yaml @@ -37,12 +37,14 @@ properties: items: - description: Combined signal for various interrupt events - description: The interrupt that occurs when Rx exits the LPI state + - description: The interrupt that occurs when HW fault occurs interrupt-names: minItems: 1 items: - const: macirq - const: eth_lpi + - const: safety clocks: maxItems: 4 @@ -89,8 +91,9 @@ examples: <&gcc GCC_ETH_PTP_CLK>, <&gcc GCC_ETH_RGMII_CLK>; interrupts = , - ; - interrupt-names = "macirq", "eth_lpi"; + , + ; + interrupt-names = "macirq", "eth_lpi", "safety"; rx-fifo-depth = <4096>; tx-fifo-depth = <4096>; From patchwork Thu Nov 23 11:53:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suraj Jaiswal X-Patchwork-Id: 746593 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="RUYyE3Lf" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF7629A; Thu, 23 Nov 2023 03:54:16 -0800 (PST) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3ANB0RvQ029134; Thu, 23 Nov 2023 11:54:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=y/Nd+6w8S23TPbGZaLug3tvcWS5MO7EAocO+wJHDUn0=; b=RUYyE3LfAmDE7LpEcUaXhusXEYN+ceogeqoKEoahhg4Cgllt3PCFSHU5lJX7bQ5O8jgD bLmQwOVruh1jN2621pK5ExN5byZBCsp7eqR8rLVbq5SXyaojz4dwTS9bc1bCHlKBDhD9 c5LfjAjYaleIyrA8JBy45h+b8CT+eLNvAQCczMYugJSg0mYQvv4FcMWjvPy00IB/YGJK WcQKU5qdFo3qv9p3jvKeGX6zVo8chLOOLoA18mMtGnQmEI9a7bjIPJ5HGZuIKFuXqDDy SziAbLb1O0iZkmP7Az8FRof7anjTNf/Fdd9wcch06dphqoPsDXP/vFwY2UkTyKhz7npb bg== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uj4hwg6pu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Nov 2023 11:54:06 +0000 Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3ANBs5bi022181 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Nov 2023 11:54:05 GMT Received: from hu-jsuraj-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 23 Nov 2023 03:53:55 -0800 From: Suraj Jaiswal To: , Vinod Koul , Bhupesh Sharma , Andy Gross , Bjorn Andersson , Konrad Dybcio , "David S. Miller" , Eric Dumazet , "Jakub Kicinski" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Alexandre Torgue , "Jose Abreu" , Maxime Coquelin , , , , , , Prasad Sodagudi , Andrew Halaney CC: Subject: [PATCH net-next v3 2/3] arm64: dts: qcom: sa8775p: enable Fault IRQ Date: Thu, 23 Nov 2023 17:23:21 +0530 Message-ID: <66690488f08912698301a2c203d7c562798806a2.1700737841.git.quic_jsuraj@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: e21lWNffVAbzzo9pQTLuZthvJdmPTZAd X-Proofpoint-ORIG-GUID: e21lWNffVAbzzo9pQTLuZthvJdmPTZAd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-23_10,2023-11-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 mlxscore=0 mlxlogscore=662 suspectscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311230084 Message-ID: <20231123115321.UyLq6v6dxjMKUs5lEtNWVASqgsMa2mguMOrGEYXfswY@z> Add changes to support fault IRQ Handling Support for ethernet. Signed-off-by: Suraj Jaiswal --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 13dd44dd9ed1..15155adcd200 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2394,8 +2394,9 @@ ethernet1: ethernet@23000000 { <0x0 0x23016000 0x0 0x100>; reg-names = "stmmaceth", "rgmii"; - interrupts = ; - interrupt-names = "macirq"; + interrupts = + ; + interrupt-names = "macirq", "safety"; clocks = <&gcc GCC_EMAC1_AXI_CLK>, <&gcc GCC_EMAC1_SLV_AHB_CLK>, @@ -2427,8 +2428,9 @@ ethernet0: ethernet@23040000 { <0x0 0x23056000 0x0 0x100>; reg-names = "stmmaceth", "rgmii"; - interrupts = ; - interrupt-names = "macirq"; + interrupts = , + ; + interrupt-names = "macirq", "safety"; clocks = <&gcc GCC_EMAC0_AXI_CLK>, <&gcc GCC_EMAC0_SLV_AHB_CLK>, From patchwork Thu Nov 23 11:38:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suraj Jaiswal X-Patchwork-Id: 746595 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="S4oW4wKR" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 264DD10C0; Thu, 23 Nov 2023 03:39:18 -0800 (PST) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AN8fLHM007773; Thu, 23 Nov 2023 11:39:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=6juClkUBmcBTBsnEjdDc22tc/uO5kD0o1qqxtbwZTZM=; b=S4oW4wKRm2I3ppiPge+nPl+LYaNLjOrkEwx64EfTssDd5PypbUkDpZT1WtRhI1heA7zs NjXf+98H2zhe2q8yLI+f8BmhU29bOZTWppPXJy+85Ri/Tv/RbSdb9ex6EXq5CDI5lpAa qA8y3ZbngPWjhkD78+7ALREWCss0JZslNc0ciQP8xUygAGUhAKugZVDzzFfFgWMAf9uQ QZcJ2NYWNHI8L9AABa8YyzgqZ3NTS2A11BbNRk2F7nBYO3MZLUrNvvoAfRw4feP6ZXUm 6M0CcI+OTppAERi4g0OWl/zeHek+zCnYW1H4Ehg1qZN+lW6Cz6zJeGR9yHLZSZARGLkg vw== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uj3ec0b67-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Nov 2023 11:39:06 +0000 Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3ANBd59P005976 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Nov 2023 11:39:05 GMT Received: from hu-jsuraj-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 23 Nov 2023 03:38:55 -0800 From: Suraj Jaiswal To: , Vinod Koul , Bhupesh Sharma , Andy Gross , Bjorn Andersson , Konrad Dybcio , "David S. Miller" , Eric Dumazet , "Jakub Kicinski" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Alexandre Torgue , "Jose Abreu" , Maxime Coquelin , , , , , , Prasad Sodagudi , Andrew Halaney CC: Subject: [PATCH net-next v3 3/3] net: stmmac: Add driver support for DWMAC5 fault IRQ Support Date: Thu, 23 Nov 2023 17:08:15 +0530 Message-ID: <62eaaace3713751cb1ecac3163e857737107ca0e.1700737841.git.quic_jsuraj@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: inTtRkS7Bsh4eRNmB_EsvVggQ51OqJNb X-Proofpoint-GUID: inTtRkS7Bsh4eRNmB_EsvVggQ51OqJNb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-23_09,2023-11-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 clxscore=1015 mlxlogscore=999 phishscore=0 impostorscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311230083 Add IRQ support to listen HW fault like ECC,DPP,FSM fault and print the fault information in the kernel log. Signed-off-by: Suraj Jaiswal --- drivers/net/ethernet/stmicro/stmmac/common.h | 1 + drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 ++ .../net/ethernet/stmicro/stmmac/stmmac_main.c | 18 +++++++++++++++++ .../ethernet/stmicro/stmmac/stmmac_platform.c | 20 +++++++++++++++++++ 4 files changed, 41 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h index 6b935922054d..c4821c7ab674 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -347,6 +347,7 @@ enum request_irq_err { REQ_IRQ_ERR_SFTY_UE, REQ_IRQ_ERR_SFTY_CE, REQ_IRQ_ERR_LPI, + REQ_IRQ_ERR_SAFETY, REQ_IRQ_ERR_WOL, REQ_IRQ_ERR_MAC, REQ_IRQ_ERR_NO, diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h index cd7a9768de5f..8893d4b7fa38 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h @@ -33,6 +33,7 @@ struct stmmac_resources { int irq; int sfty_ce_irq; int sfty_ue_irq; + int safety_common_intr; int rx_irq[MTL_MAX_RX_QUEUES]; int tx_irq[MTL_MAX_TX_QUEUES]; }; @@ -331,6 +332,7 @@ struct stmmac_priv { /* XDP BPF Program */ unsigned long *af_xdp_zc_qps; struct bpf_prog *xdp_prog; + int safety_common_intr; }; enum stmmac_state { diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 8964fc8a955f..2ae4f34444de 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -3530,6 +3530,10 @@ static void stmmac_free_irq(struct net_device *dev, if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) free_irq(priv->wol_irq, dev); fallthrough; + case REQ_IRQ_ERR_SAFETY: + if (priv->safety_common_intr > 0 && priv->safety_common_intr != dev->irq) + free_irq(priv->safety_common_intr, dev); + fallthrough; case REQ_IRQ_ERR_WOL: free_irq(dev->irq, dev); fallthrough; @@ -3736,6 +3740,18 @@ static int stmmac_request_irq_single(struct net_device *dev) } } + if (priv->safety_common_intr > 0 && priv->safety_common_intr != dev->irq) { + ret = request_irq(priv->safety_common_intr, stmmac_safety_interrupt, + 0, "safety", dev); + if (unlikely(ret < 0)) { + netdev_err(priv->dev, + "%s: alloc safety failed %d (error: %d)\n", + __func__, priv->safety_common_intr, ret); + irq_err = REQ_IRQ_ERR_SAFETY; + goto irq_error; + } + } + return 0; irq_error: @@ -7398,6 +7414,8 @@ int stmmac_dvr_probe(struct device *device, priv->lpi_irq = res->lpi_irq; priv->sfty_ce_irq = res->sfty_ce_irq; priv->sfty_ue_irq = res->sfty_ue_irq; + priv->safety_common_intr = res->safety_common_intr; + for (i = 0; i < MTL_MAX_RX_QUEUES; i++) priv->rx_irq[i] = res->rx_irq[i]; for (i = 0; i < MTL_MAX_TX_QUEUES; i++) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index 1ffde555da47..bae1704d5f4b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -690,9 +690,25 @@ devm_stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac) #endif /* CONFIG_OF */ EXPORT_SYMBOL_GPL(devm_stmmac_probe_config_dt); +int stmmac_get_fault_intr_config(struct platform_device *pdev, struct stmmac_resources *res) +{ + int ret = 0; + + res->safety_common_intr = platform_get_irq_byname(pdev, "safety"); + + if (res->safety_common_intr < 0) { + if (res->safety_common_intr != -EPROBE_DEFER) + dev_err(&pdev->dev, "safety IRQ configuration information not found\n"); + ret = 1; + } + + return ret; +} + int stmmac_get_platform_resources(struct platform_device *pdev, struct stmmac_resources *stmmac_res) { + int ret = 0; memset(stmmac_res, 0, sizeof(*stmmac_res)); /* Get IRQ information early to have an ability to ask for deferred @@ -702,6 +718,10 @@ int stmmac_get_platform_resources(struct platform_device *pdev, if (stmmac_res->irq < 0) return stmmac_res->irq; + ret = stmmac_get_fault_intr_config(pdev, stmmac_res); + if (ret) + dev_err(&pdev->dev, "Fault interrupt not present\n"); + /* On some platforms e.g. SPEAr the wake up irq differs from the mac irq * The external wake up irq can be passed through the platform code * named as "eth_wake_irq"