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[178.235.187.180]) by smtp.gmail.com with ESMTPSA id 19-20020a170906319300b00992b8d56f3asm3500345ejy.105.2023.11.25.06.17.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 06:17:46 -0800 (PST) From: Konrad Dybcio Date: Sat, 25 Nov 2023 15:17:30 +0100 Subject: [PATCH 02/12] dt-bindings: display: msm: Add reg bus and rotator interconnects Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231125-topic-rb1_feat-v1-2-11d71b12b058@linaro.org> References: <20231125-topic-rb1_feat-v1-0-11d71b12b058@linaro.org> In-Reply-To: <20231125-topic-rb1_feat-v1-0-11d71b12b058@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Bryan O'Donoghue , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Will Deacon , Robin Murphy , Joerg Roedel , Krishna Manikandan , Robert Marko , Das Srinagesh Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700921858; l=1875; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=AFFsjfQ/BWb6zbEE2kIE5M6+YBHmlQ+rokF2C+2Kd04=; b=Ko21H+lWGGl59y8qJsZ+LTUw0AWkhTziUlqwg4+lQP0Zq18rNp2fD1omovB6ZeBmhVmjSNMTp wKdjaAGzz5nAy1P3zo5fSusiUSJLqx/3Pre4Gi7Q7gCCuziLVKdW0lH X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there are other connection paths: - a path that connects rotator block to the DDR. - a path that needs to be handled to ensure MDSS register access functions properly, namely the "reg bus", a.k.a the CPU-MDSS CFG interconnect. Describe these paths bindings to allow using them in device trees and in the driver Signed-off-by: Dmitry Baryshkov [Konrad: rework for one vs two MDP paths] Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/display/msm/mdss-common.yaml | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml index f69196e4cc76..c6305a6e0334 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml @@ -61,17 +61,27 @@ properties: ranges: true + # This is not a perfect description, but it's impossible to discern and match + # the entries like we do with interconnect-names interconnects: minItems: 1 items: - description: Interconnect path from mdp0 (or a single mdp) port to the data bus - description: Interconnect path from mdp1 port to the data bus + - description: Interconnect path from CPU to the reg bus interconnect-names: - minItems: 1 - items: - - const: mdp0-mem - - const: mdp1-mem + oneOf: + - minItems: 1 + items: + - const: mdp0-mem + - const: cpu-cfg + + - minItems: 2 + items: + - const: mdp0-mem + - const: mdp1-mem + - const: cpu-cfg resets: items: From patchwork Sat Nov 25 14:17:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 747264 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zlPiEMUt" Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50D2ED4E for ; Sat, 25 Nov 2023 06:17:55 -0800 (PST) Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-a0bdf4eeb46so47223966b.3 for ; Sat, 25 Nov 2023 06:17:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700921873; x=1701526673; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=oCxJjrmz0z+H04UIqC/ZDHtTQyFYGs6I+ck9k7G4Dco=; b=zlPiEMUtAIYRjaigsiS8XxggmWtq8FEo6GLn+Xyp+g5cIWyhsgte6AahCl2VqpsFAW aFZKav0Rd9rqJoWGnk0De5TlvJPwudRZaOcGvYsleEyvCMHeYjsZpk0cfkeITkwUrPEJ 5imii9zLTlcGQxJG89d2khBsSYQPWHQFQxDJkZDAmBjAZHT+CKxugxacZSRUbDIP3CQ9 +RFvrHDDvwBk9UxdyCvYPWyX8agG79dSHflIliL6nor9V00zMLAIQCniEHN9ZT817O04 RmFQZr6l68ebV28qbrCl4yMv9GrRqQIi83jQeWK/KYjP7e2b2jxXnUF0ATj4R16hXTSW ZjOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700921873; x=1701526673; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oCxJjrmz0z+H04UIqC/ZDHtTQyFYGs6I+ck9k7G4Dco=; b=RTWeJKj1frDLhct8C4AklxYQtJStzvywevNxlMvAx+B4jPMusguvSzP/dJUbqgWw4t we1OpG4b8vP5S2ue2RKuOVpYX5qOLbBbrVer1WYbhRtJsAma6Ym2riiQkN8IUlgBkQpS BfO+NW7BINJbfMXvub84e4XeH2q+mecWO6TtwVSsWdnrwMm1PeG2fVvgRe+FQFUBR9ZO Y4RZBtVJA2Z6EgDhMyG0PcHEwoOsOlrytHAbAM9U6yBpJDHZ7RDGP6LlO3Ha6qrBbVhe joJO/+VVPHCSivG0HWZisQtG1Lr2kf/7iM0IMT//P3u8dQ6t/6qKuK4CWNj/uw6UUiYr prxA== X-Gm-Message-State: AOJu0YzPczxqidLsEunA4K/R5Ngzb7pdwY3nQQFD6TiuRG9YSHxKZ66A KBpFlpNB3839Ki8h+O62cGe3PB9ORMkgUIh9uFY= X-Google-Smtp-Source: AGHT+IEbr7GDBeTPnW9gDDdo6VkIGH/WLIKWJrPZjcT5euLmhj3AB5FHgBzeyAAMU2jqxkCAgOefqA== X-Received: by 2002:a17:906:b796:b0:9fe:57b3:bc08 with SMTP id dt22-20020a170906b79600b009fe57b3bc08mr4394797ejb.41.1700921873218; Sat, 25 Nov 2023 06:17:53 -0800 (PST) Received: from [10.167.154.1] (178235187180.dynamic-4-waw-k-2-3-0.vectranet.pl. [178.235.187.180]) by smtp.gmail.com with ESMTPSA id 19-20020a170906319300b00992b8d56f3asm3500345ejy.105.2023.11.25.06.17.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 06:17:52 -0800 (PST) From: Konrad Dybcio Date: Sat, 25 Nov 2023 15:17:32 +0100 Subject: [PATCH 04/12] dt-bindings: display: msm: sm8450-mdss: Allow 3 interconnects Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231125-topic-rb1_feat-v1-4-11d71b12b058@linaro.org> References: <20231125-topic-rb1_feat-v1-0-11d71b12b058@linaro.org> In-Reply-To: <20231125-topic-rb1_feat-v1-0-11d71b12b058@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Bryan O'Donoghue , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Will Deacon , Robin Murphy , Joerg Roedel , Krishna Manikandan , Robert Marko , Das Srinagesh Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700921858; l=865; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=deb9D2Xe1g6rHblNJhukz7PgRHVCdj6e1NcVucThHsI=; b=04VTSyTWm5dlypXw+GdRqYQamBFxd0dqxWXQAZG+T+kAWcdfLMeRvfERanmuPSleYxvb1DvOc JNDbEQ+SZ00DtKtwDgvwPbS3PZP48Bpj+WwtQ3aYwSNN8E5K2QOT+y7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= In addition to MDP01, the cpu-cfg interconnect is also necessary. Allow it. Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml index 001b26e65301..e94e8630cc85 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml @@ -30,10 +30,10 @@ properties: maxItems: 1 interconnects: - maxItems: 2 + maxItems: 3 interconnect-names: - maxItems: 2 + maxItems: 3 patternProperties: "^display-controller@[0-9a-f]+$": From patchwork Sat Nov 25 14:17:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 747263 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="JVI45ek3" Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 064D81987 for ; Sat, 25 Nov 2023 06:18:02 -0800 (PST) Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2c8880fbb33so36399811fa.0 for ; Sat, 25 Nov 2023 06:18:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700921880; x=1701526680; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OMfZuIt+BqG7KJ9nvVW95qPOCXnGA5QHM/Q3t0t9+4M=; b=JVI45ek3nUjZLPzP4gXrVK6Ab8mYya+JK4b9mYzHFa9kiBUUgmVW6Ybu1S57XM133X sWPLVrKUB1M7pNEFCuz7eD4XAmzvC+6D3TR8kHQAgPPd38FkMkn17vsYbKb59i2meUfU SAWGZDfuF/G6CIujKfDfZtbA0Bemft9M9Cmo5bIwg33LZDJInr6K+D73xo6I50bQAUfZ z9cGALg2Ud+B2vcWHsrnWq4FX3j62ud1TC5RR+tsBGTZ27m7fEVeVX9eCCE784mz4DB/ aup5BIVu+Eln1mdCD3Bz44W4j/e+Za7ToZXE+PhXAaaOYF4wPXlUsOb7gnDnXe5kMDwd K1Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700921880; x=1701526680; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OMfZuIt+BqG7KJ9nvVW95qPOCXnGA5QHM/Q3t0t9+4M=; b=pNLY+GcEBWPzp12ujOfwDK95bF/vfaoB2rBWiUrpu1+FAlBkf3qrpTHuKg1SKj5XKu wtHUEdP1cuYcMqH6pMavAkZcSRQL7JmDgSjqCilh8czZkvv8rpUYs0y74XllWfuVWVbe 6Qghac2AQ+14oLdi3UhSx/C49YbtpNDnXHRwhiFVBeslvdz9L8Ct5kOuKOKri2uEArtV Tq5UteO3FG/RgXkVl5UqRMyAL05BndqtxVdMlS2kwEzXTrWAITGLbk+ttSDHledmgUIY 3Au7VpUhJB6Wz+JUwU2wExgTyK2PGcn9XVvZzJoCg5NXG8KdCjGUPDBE17wSYzR5gtM8 0WQg== X-Gm-Message-State: AOJu0YxDLtT7qlvjSTx6hUBo3riCllVrk+sHdV2nU2SmrgK7cTTdZcs6 ZE4dhDw0uRfGVL69QISN0jhWOmlvOfiakMTu+wM= X-Google-Smtp-Source: AGHT+IGY8/ylhRHLmys2VuwyghOEp5L7XnbE9NC1OHEjDt/EDFIyFNSFmFVQ5bIXBVUTdxQp2wEScQ== X-Received: by 2002:a2e:350d:0:b0:2c6:ed74:39bd with SMTP id z13-20020a2e350d000000b002c6ed7439bdmr4479087ljz.12.1700921879933; Sat, 25 Nov 2023 06:17:59 -0800 (PST) Received: from [10.167.154.1] (178235187180.dynamic-4-waw-k-2-3-0.vectranet.pl. [178.235.187.180]) by smtp.gmail.com with ESMTPSA id 19-20020a170906319300b00992b8d56f3asm3500345ejy.105.2023.11.25.06.17.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 06:17:59 -0800 (PST) From: Konrad Dybcio Date: Sat, 25 Nov 2023 15:17:34 +0100 Subject: [PATCH 06/12] dt-bindings: firmware: qcom,scm: Allow interconnect for everyone Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231125-topic-rb1_feat-v1-6-11d71b12b058@linaro.org> References: <20231125-topic-rb1_feat-v1-0-11d71b12b058@linaro.org> In-Reply-To: <20231125-topic-rb1_feat-v1-0-11d71b12b058@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Bryan O'Donoghue , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Will Deacon , Robin Murphy , Joerg Roedel , Krishna Manikandan , Robert Marko , Das Srinagesh Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700921858; l=1089; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=zKRggNekRjMo2HWiE/Zd6htFQdzWQ+j1rvOWJYZk1Dg=; b=J86IamNFPWjvFl8R15HeGrbbKv6nxOgsRyV2gcyGjGQvv0D4Sonw6dL4ASTha1oCz3/d/YNgs sy9rMHIgH7XD+CMd35v3AcW4emIGcmWa0HZbVIBI6fy/CV5AVKhIpjD X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Every Qualcomm SoC physically has a "CRYPTO0<->DDR" interconnect lane. Allow this property to be present, no matter the SoC. Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 0613a37a851a..f3a87a8426d0 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -178,21 +178,6 @@ allOf: minItems: 3 maxItems: 3 - # Interconnects - - if: - not: - properties: - compatible: - contains: - enum: - - qcom,scm-qdu1000 - - qcom,scm-sc8280xp - - qcom,scm-sm8450 - - qcom,scm-sm8550 - then: - properties: - interconnects: false - # Interrupts - if: not: From patchwork Sat Nov 25 14:17:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 747262 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ilXTmSy1" Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 259621BE5 for ; Sat, 25 Nov 2023 06:18:07 -0800 (PST) Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-a02d12a2444so408686466b.3 for ; Sat, 25 Nov 2023 06:18:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700921885; x=1701526685; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=8KqUGGYBrVzv5cHQpnzoWSbk/05sDmdEfZhra6WsNz8=; b=ilXTmSy1fKaWOkfyNsKSdyF2wRAkjqchhTWCQ2eYtvJ32W5mGG0tW6bztZ0CL76kEn vpwX0/EB9De53WEcXZ7e88slc5VKl6X0q6AbJ8YMSuyJY1eQ3N3fw06PmnXHDn42zVXh FwOUm6/QdObl8ZO+wIDe9Fq6Z6graV5Y8SNbU68qzaaDPAyhskGqQ1dtQ6Q5bC/M139q dkihHm89qNOSt1CyltyDPUCjeQpQxMS2jIauYnPckbOyRfWYD+eLmzl4unWRdMjsuHF3 Iw7Ox8qLCqIFsP+z2+Fv3YunO7oGip81BCnW32J+aQHNyuePg0V9ByCpFI6NnqmVeS/x z+eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700921885; x=1701526685; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8KqUGGYBrVzv5cHQpnzoWSbk/05sDmdEfZhra6WsNz8=; b=jEwYUDej5i9Ag5rPgjcmIv83X4PdIFV3ZHTYB1ahL9t9TCd11cv5Vamd6qw+CNXdkG hHaQELBH1MJAOD3JPsz0aPyXIrjsL0+f24h3nXah/95HmYwMoA3C18Ig+dsY5J2RtZU3 oLPrhvLFtBGWvaysgkPGli4KkMPHCkHCoDXybLXIr8b514gi34/arjA+EAoKRvmWmI+d 9o1WjVMMZQUUnh4FGd/ZW4BJ+6K9oOBfLDV5eU9wAx58EMBJyuti1yDa5wm4NlmSrbLg zUNbrV4xXBMrtDMMW8E908fmb870k3u5ISYibuqcGrz3zc6uAMfVN4ScaMnzKfz6clFy J95Q== X-Gm-Message-State: AOJu0YxGh2NndgukNdpIvAIkA0/zBVR7EzOSKZYVfRB+97Ih+eNfQJvP dANE+CFTqIEmKiVePbACAjiR4Y22J0s0JLq9wWg= X-Google-Smtp-Source: AGHT+IGHMYxRRfIqtxfNsI46ouXMj4qj601hEjLqK6qFENP4LosrLawLgnUb/fCSNeWBh+gO8y/pxg== X-Received: by 2002:a17:906:2c52:b0:a03:d6d0:a0c4 with SMTP id f18-20020a1709062c5200b00a03d6d0a0c4mr4414893ejh.44.1700921885071; Sat, 25 Nov 2023 06:18:05 -0800 (PST) Received: from [10.167.154.1] (178235187180.dynamic-4-waw-k-2-3-0.vectranet.pl. [178.235.187.180]) by smtp.gmail.com with ESMTPSA id 19-20020a170906319300b00992b8d56f3asm3500345ejy.105.2023.11.25.06.18.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 06:18:04 -0800 (PST) From: Konrad Dybcio Date: Sat, 25 Nov 2023 15:17:36 +0100 Subject: [PATCH 08/12] arm64: dts: qcom: qcm2290: Add display nodes Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231125-topic-rb1_feat-v1-8-11d71b12b058@linaro.org> References: <20231125-topic-rb1_feat-v1-0-11d71b12b058@linaro.org> In-Reply-To: <20231125-topic-rb1_feat-v1-0-11d71b12b058@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Bryan O'Donoghue , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Will Deacon , Robin Murphy , Joerg Roedel , Krishna Manikandan , Robert Marko , Das Srinagesh Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700921858; l=6335; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=BTvepHr7en8R5ipJOnsIKxJu6757PVnhk3uZkFoZtMc=; b=+sHcV3iZc4Z95WPgGaY1HBaB4k8THrzOvHBpzRWU/+lAQ0jqoCHVdvEx9wjXuViidmRa7vVYR AyKBHLRAZmwDpBehcWnsJy6p5lkSWlXqB1AOdhPeVA9AtJtJbLMIY/g X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Add the required nodes to support display on QCM2290. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 214 ++++++++++++++++++++++++++++++++++ 1 file changed, 214 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index d46e591e72b5..a3edc4667cc5 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -5,6 +5,7 @@ * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. */ +#include #include #include #include @@ -1105,6 +1106,219 @@ usb_dwc3: usb@4e00000 { }; }; + mdss: display-subsystem@5e00000 { + compatible = "qcom,qcm2290-mdss"; + reg = <0x0 0x05e00000 0x0 0x1000>; + reg-names = "mdss"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "core"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc MDSS_GDSC>; + + iommus = <&apps_smmu 0x420 0x2>, + <&apps_smmu 0x421 0x0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdp: display-controller@5e01000 { + compatible = "qcom,qcm2290-dpu"; + reg = <0x0 0x05e01000 0x0 0x8f000>, + <0x0 0x05eb0000 0x0 0x2008>; + reg-names = "mdp", + "vbif"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "iface", + "core", + "lut", + "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd QCM2290_VDDCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmpd_opp_min_svs>; + }; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-256000000 { + opp-hz = /bits/ 64 <256000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@5e94000 { + compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x05e94000 0x0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd QCM2290_VDDCX>; + phys = <&mdss_dsi0_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmpd_opp_min_svs>; + }; + + opp-164000000 { + opp-hz = /bits/ 64 <164000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmpd_opp_svs>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@5e94400 { + compatible = "qcom,dsi-phy-14nm-2290"; + reg = <0x0 0x05e94400 0x0 0x100>, + <0x0 0x05e94500 0x0 0x300>, + <0x0 0x05e94800 0x0 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "ref"; + + power-domains = <&rpmpd QCM2290_VDDMX>; + required-opps = <&rpmpd_opp_nom>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@5f00000 { + compatible = "qcom,qcm2290-dispcc"; + reg = <0x0 0x05f00000 0x0 0x20000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "gcc_disp_gpll0_clk_src", + "gcc_disp_gpll0_div_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk"; + #power-domain-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + remoteproc_mpss: remoteproc@6080000 { compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; reg = <0x0 0x06080000 0x0 0x100>; From patchwork Sat Nov 25 14:17:38 2023 Content-Type: text/plain; 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[178.235.187.180]) by smtp.gmail.com with ESMTPSA id 19-20020a170906319300b00992b8d56f3asm3500345ejy.105.2023.11.25.06.18.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 06:18:10 -0800 (PST) From: Konrad Dybcio Date: Sat, 25 Nov 2023 15:17:38 +0100 Subject: [PATCH 10/12] arm64: dts: qcom: qrb2210-rb1: Set up HDMI Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231125-topic-rb1_feat-v1-10-11d71b12b058@linaro.org> References: <20231125-topic-rb1_feat-v1-0-11d71b12b058@linaro.org> In-Reply-To: <20231125-topic-rb1_feat-v1-0-11d71b12b058@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Bryan O'Donoghue , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Will Deacon , Robin Murphy , Joerg Roedel , Krishna Manikandan , Robert Marko , Das Srinagesh Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700921858; l=2344; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=HG+qKKvGUGteXhS1Efd/CaFsVpJbWzVwdo27Zc2OxfM=; b=cgu/Ut7yxp3T/a5OVTyYp7MC9Q+0t412jE9OzRFi2ZwaFCoBnLSBn2ieUp1gG/Aiq6T8oDuP5 y+s5p0siYBhAps0OZzciqWKP9cotld3WnhaxXk7ub6dijzQ3T6jKxUX X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Add the required nodes to support display output via the HDMI port. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 86 ++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index 94885b9c21c8..ac6584164058 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -40,6 +40,17 @@ key-volume-up { }; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -158,6 +169,68 @@ vph_pwr: regulator-vph-pwr { }; }; +&gpi_dma0 { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + interrupts-extended = <&tlmm 46 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>; + + vdd-supply = <&vreg_hdmi_out_1p2>; + vcc-supply = <<9611_3v3>; + + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + pinctrl-names = "default"; + #sound-dai-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm2250_l5>; + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; +}; + &pm2250_resin { linux,code = ; status = "okay"; @@ -377,6 +450,19 @@ &sdhc_2 { }; &tlmm { + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio41"; + function = "gpio"; + input-disable; + output-high; + }; + + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio46"; + function = "gpio"; + bias-disable; + }; + sd_det_in_on: sd-det-in-on-state { pins = "gpio88"; function = "gpio"; From patchwork Sat Nov 25 14:17:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 747260 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="TPolLq+j" Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5E4610C3 for ; Sat, 25 Nov 2023 06:18:17 -0800 (PST) Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-a00191363c1so412541866b.0 for ; Sat, 25 Nov 2023 06:18:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700921896; x=1701526696; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=6AuHxZr8x/Uk1Y12/gMeKhnjQeN0t/qZ6GCe7PtBack=; b=TPolLq+j+yDKInvT7do8sCdsBjFU9otamHdDYzHOJwE3y0wk112L7RqJ1T0F+/4RPH VzQIyobkopEhMp234mv3UFituHVLRqgkDhEFyGPJisBOWyyE5Q4SPbULHREX/orgl9dZ Np7iRpfhmCr+i+FJ3RU1IHqixMER1byKcLKgBrnnCW21hOccRczr+jJCTolEqNPq6QU/ qCWe2FpjK8naEAUqW14355CBUWmdrWDDqmvA2Haugkt/aafeYSmoa2sJ2LIFRQN6C+nX ZPRl6CXyfvqoQge7ZRFm+vtGBebStczWgpCWSsdvLj/bxqAYXuDvVufYdkf1WuGTMEzi Lo0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700921896; x=1701526696; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6AuHxZr8x/Uk1Y12/gMeKhnjQeN0t/qZ6GCe7PtBack=; b=C28Fk8IVQc9WIHTGbWdRAwKqk8b9mYrWxltPghiCnuN73fSEDyYI6IRwY98PxLYj9p TRBjkn3hDRmc7G6PKD9Bqn0GaDcPxkyiTwuyW+US7Vp3jlFA61qUREN8cTsnUO8Cx8iL a2u0DqEM5FfS5PaXVIa3Vbi3IKDJ/QXJyRQTxLun6DO/DrV3rElfT18eXV5Rl/0+Yj1K 4c7Sw2A6/qq/+h/7eWBIEt8G2i5rv1NHhcMiYw/DKbzLBI8j5bd9nwtLMxJdA3VQ4FFn dU3Q7Iw8yg/7R7T+vsX2zPX516iaeVPD3DWYubr4xXegg3GI3R6tGQjRUv0+3UfCxIcS nPuQ== X-Gm-Message-State: AOJu0YyPwq58Am88fbard0/dLExFzV8ygqRiuDKZ5caTPTj76ghxn/S9 7luVAXD4aL67PlYoftP2dDpLG3NLigGAIbwhobY= X-Google-Smtp-Source: AGHT+IEWEyRd878coT3XTG8rCeCot3GJrL6vUjbz+4PBaJEmtJMsQ18SwIYunDl7AGB0ZPe2YkQmiQ== X-Received: by 2002:a17:906:eb0f:b0:a02:95ea:1289 with SMTP id mb15-20020a170906eb0f00b00a0295ea1289mr4986720ejb.20.1700921895817; Sat, 25 Nov 2023 06:18:15 -0800 (PST) Received: from [10.167.154.1] (178235187180.dynamic-4-waw-k-2-3-0.vectranet.pl. [178.235.187.180]) by smtp.gmail.com with ESMTPSA id 19-20020a170906319300b00992b8d56f3asm3500345ejy.105.2023.11.25.06.18.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 06:18:15 -0800 (PST) From: Konrad Dybcio Date: Sat, 25 Nov 2023 15:17:40 +0100 Subject: [PATCH 12/12] arm64: dts: qcom: qrb2210-rb1: add wifi variant property Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231125-topic-rb1_feat-v1-12-11d71b12b058@linaro.org> References: <20231125-topic-rb1_feat-v1-0-11d71b12b058@linaro.org> In-Reply-To: <20231125-topic-rb1_feat-v1-0-11d71b12b058@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Bryan O'Donoghue , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Will Deacon , Robin Murphy , Joerg Roedel , Krishna Manikandan , Robert Marko , Das Srinagesh Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700921858; l=1845; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=F+2+KPEjbmpD3TQ3tmcuJpeM3OLd440fgCNNO64cW48=; b=AHM7tx93ACOm+aMCiZmKs/B4UljcUXbt0A+dc2es12Xj+N/o+z8cKNsnWXmZtr0qEc8JRam6s DUqeIzB6YY9B3ImyhknQxgukJrl8Xik6yjChJIsSWnbLMjE49IYoq3C X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Dmitry Baryshkov The RB1 platform doesn't have board-specific board-id programmed, it uses generic 0xff. Thus add the property with the 'variant' of the calibration data. Note: the driver will check for the calibration data for the following IDs, so existing board-2.bin files will continue to work. - 'bus=snoc,qmi-board-id=ff,qmi-chip-id=120,variant=Thundercomm_RB1' - 'bus=snoc,qmi-board-id=ff,qmi-chip-id=120' - 'bus=snoc,qmi-board-id=ff' For the reference, the board is identified by the driver in the following way: ath10k_snoc c800000.wifi: qmi chip_id 0x120 chip_family 0x4007 board_id 0xff soc_id 0x40670000 ath10k_snoc c800000.wifi: qmi fw_version 0x337302d3 fw_build_timestamp 2023-01-06 01:50 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.3.3.7.c2-00723-QCAHLSWMTPLZ-1 ath10k_snoc c800000.wifi: wcn3990 hw1.0 target 0x00000008 chip_id 0x00000000 sub 0000:0000 ath10k_snoc c800000.wifi: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0 ath10k_snoc c800000.wifi: firmware ver api 5 features wowlan,mgmt-tx-by-reference,non-bmi crc32 b3d4b790 ath10k_snoc c800000.wifi: htt-ver 3.114 wmi-op 4 htt-op 3 cal file max-sta 32 raw 0 hwcrypto 1 Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index ac597eb3fe9d..bd7bcf803654 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -535,6 +535,7 @@ &wifi { vdd-1.8-xo-supply = <&pm2250_l13>; vdd-1.3-rfa-supply = <&pm2250_l10>; vdd-3.3-ch0-supply = <&pm2250_l22>; + qcom,ath10k-calibration-variant = "Thundercomm_RB1"; status = "okay"; };