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[93.34.89.13]) by smtp.googlemail.com with ESMTPSA id p34-20020a05600c1da200b00406408dc788sm9875344wms.44.2023.11.25.17.53.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 17:53:54 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next PATCH RFC v3 1/8] dt-bindings: net: document ethernet PHY package nodes Date: Sun, 26 Nov 2023 02:53:39 +0100 Message-Id: <20231126015346.25208-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231126015346.25208-1-ansuelsmth@gmail.com> References: <20231126015346.25208-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document ethernet PHY package nodes used to describe PHY shipped in bundle of 4-5 PHY. The special node describe a container of PHY that share common properties. This is a generic schema and PHY package should create specialized version with the required additional shared properties. Example are PHY package that have some regs only in one PHY of the package and will affect every other PHY in the package, for example related to PHY interface mode calibration or global PHY mode selection. The PHY package node MUST declare the base address used by the PHY driver for global configuration by calculating the offsets of the global PHY based on the base address of the PHY package and declare the "ethrnet-phy-package" compatible. Each reg of the PHY defined in the PHY package node is absolute and will reference the real address of the PHY on the bus. Signed-off-by: Christian Marangi --- .../bindings/net/ethernet-phy-package.yaml | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ethernet-phy-package.yaml diff --git a/Documentation/devicetree/bindings/net/ethernet-phy-package.yaml b/Documentation/devicetree/bindings/net/ethernet-phy-package.yaml new file mode 100644 index 000000000000..244d4bc29164 --- /dev/null +++ b/Documentation/devicetree/bindings/net/ethernet-phy-package.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ethernet-phy-package.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ethernet PHY Package Common Properties + +maintainers: + - Christian Marangi + +description: + This schema describe PHY package as simple container for + a bundle of PHYs that share the same properties and + contains the PHYs of the package themself. + + Each reg of the PHYs defined in the PHY package node is + absolute and describe the real address of the PHY on the bus. + +properties: + $nodename: + pattern: "^ethernet-phy-package(@[a-f0-9]+)?$" + + compatible: + const: ethernet-phy-package + + reg: + minimum: 0 + maximum: 31 + description: + The base ID number for the PHY package. + Commonly the ID of the first PHY in the PHY package. + + Some PHY in the PHY package might be not defined but + still exist on the device (just not attached to anything). + The reg defined in the PHY package node might differ and + the related PHY might be not defined. + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + ^ethernet-phy(@[a-f0-9]+)?$: + $ref: ethernet-phy.yaml# + +required: + - compatible + - reg + +additionalProperties: true + +examples: + - | + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy-package@16 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ethernet-phy-package"; + reg = <0x16>; + + ethernet-phy@16 { + reg = <0x16>; + }; + + phy4: ethernet-phy@1a { + reg = <0x1a>; + }; + }; + }; From patchwork Sun Nov 26 01:53:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 747431 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kx1nTZWx" Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67F81C6; Sat, 25 Nov 2023 17:53:58 -0800 (PST) Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-40838915cecso22031875e9.2; Sat, 25 Nov 2023 17:53:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700963637; x=1701568437; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=T6/qmHve1L25MiRLoatLwS+Zmpj0CqjsbvwNeXg845w=; b=kx1nTZWxMd/kGgWm8ONOiFZKEPxDg4SQGw1u1qnRzFPK1j4TfVc4W6DoErQXt+2ORX U3PsVqSkk9ULkI1nnXtEFyQ/w/lQMT441dhU93/yyFQRqEyUvDpjB5MhUpCt7iuoB/ev WEuvLw8aVuSUAE3blItgwLo6wO+KmvwogCgkQNuXLKjwmXG/4yT3E0Uvdwh30Vfv4DIP kpVxvDA0sS5QWok48t8ew4GUyeqTu8ppgjVaOL4bBo7K4qeDBji0cbRagpIKUZxeoxsU vLBbEY7uP0y0PbNDl6fKqTqXJ9HkQC5jMtdwKj8W677cAR/LQXIAtTmJOBgw3+f5Vk1e GVwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700963637; x=1701568437; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T6/qmHve1L25MiRLoatLwS+Zmpj0CqjsbvwNeXg845w=; b=PsV2Pz3oBL5oFenUaiCVTRs60FBe2dO4HQdtZSO0gkMdO5nVQCJxT5zIxw2ZeJGP0F pfYGzcXdKvTdX4lpRvBZPYE/q89O9ZDt4piEFbtVvQ1RBIdXdIscnUlAKpxkSd+PBd2j LCLpWHbLvpO1/tWjuiKhY2bH5s2RlxM4ZVdEKWhnAEolwas6GWdSihttt/8P7Pa3NfF2 cWL1gDVr9vix1rh+YZfy81BmrTIhiokGOeWTe561+lI9laIBmMHO3IAQvMko9r6g69V6 RxlQOb5A1LHPFoQpI2ztcUBNoCXyIiVOow1ru6DxVLELt0qHgZ9t2f+42nmRuTTUeiYN DNNQ== X-Gm-Message-State: AOJu0Yy9vvk46WwnbUfQHYFN0eEHq5j8eJhZH6KL3H2XlEQEUgMevKaT aY8W1lyAdqfDdPCz5Fxo4yo= X-Google-Smtp-Source: AGHT+IGFPIhYuPbdoh4RQpznTFaMlEGRX1LxY1xuT3XNZe5QH9o+8Q9NhKq9xrZp6+5zj8BaO1AVEA== X-Received: by 2002:a05:600c:3306:b0:40b:36d3:ce0a with SMTP id q6-20020a05600c330600b0040b36d3ce0amr1961117wmp.16.1700963636826; Sat, 25 Nov 2023 17:53:56 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id p34-20020a05600c1da200b00406408dc788sm9875344wms.44.2023.11.25.17.53.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 17:53:56 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next PATCH RFC v3 3/8] net: phy: add support for shared priv data size for PHY package in DT Date: Sun, 26 Nov 2023 02:53:41 +0100 Message-Id: <20231126015346.25208-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231126015346.25208-1-ansuelsmth@gmail.com> References: <20231126015346.25208-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for defining shared data size for PHY package defined in DT. A PHY driver has to define the value .phy_package_priv_data_size to make the generic OF PHY package function alloc priv data in the shared struct for the PHY package. Signed-off-by: Christian Marangi --- drivers/net/phy/phy_device.c | 7 ++++++- include/linux/phy.h | 3 +++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index f416f7434697..87f06b4ecbfe 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -3178,6 +3178,7 @@ static int of_phy_package(struct phy_device *phydev) { struct device_node *node = phydev->mdio.dev.of_node; struct device_node *package_node; + int shared_priv_data_size; u32 base_addr; int ret; @@ -3194,8 +3195,12 @@ static int of_phy_package(struct phy_device *phydev) if (of_property_read_u32(package_node, "reg", &base_addr)) return -EINVAL; + shared_priv_data_size = 0; + if (phydev->drv->phy_package_priv_data_size) + shared_priv_data_size = phydev->drv->phy_package_priv_data_size; + ret = devm_phy_package_join(&phydev->mdio.dev, phydev, - base_addr, 0); + base_addr, shared_priv_data_size); if (ret) return ret; diff --git a/include/linux/phy.h b/include/linux/phy.h index 80a4adaeb817..c4e6d0b3a86c 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -884,6 +884,8 @@ struct phy_led { * @flags: A bitfield defining certain other features this PHY * supports (like interrupts) * @driver_data: Static driver data + * @phy_package_priv_data_size: Size of the priv data to alloc + * for shared struct of PHY package. * * All functions are optional. If config_aneg or read_status * are not implemented, the phy core uses the genphy versions. @@ -901,6 +903,7 @@ struct phy_driver { const unsigned long * const features; u32 flags; const void *driver_data; + unsigned int phy_package_priv_data_size; /** * @soft_reset: Called to issue a PHY software reset From patchwork Sun Nov 26 01:53:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 747430 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PE/mzQvL" Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 221F2182; Sat, 25 Nov 2023 17:54:01 -0800 (PST) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-40b2ad4953cso22873245e9.0; Sat, 25 Nov 2023 17:54:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700963639; x=1701568439; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=qMmCWPX59UJtqG86RQS8Ot62rGrmo3eqFy3GB/yFnLs=; b=PE/mzQvLCET07AQLvRIG9wwbHZOjHS6eh4aC2K5pJOcd19QdkjmJ2Y86nkOS3FnjgZ QtXXu/gT6YFcLUJ3lGrWW+eFKbuKm2LkuNnA/JLOzNYb0c7FztjYhWFS/torW1D01GM6 wlGWChxdiV5KONbiPXrooyFB62orpH2ekheDpItAyxu/UcuVmv3o8Dc42jMzS2GmwZJJ 5YzlmJjlIWdxHGLgrDFUhs+GUKTRROaeqaBHfSQgx763qcp/noTKvFct6llRMjzA0u0T KO9fmaymAMniyY4lOAaszmykyta+uqW7x/cDBmsZ8eblz5J5BHXtMS/+xDZr/RjS1XCk V88g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700963639; x=1701568439; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qMmCWPX59UJtqG86RQS8Ot62rGrmo3eqFy3GB/yFnLs=; b=sV46AEbHUvH3sPMv9wC++vSdBjwFeeNGS21KsVp7+Njbu2TPCqNLhM3PVmIu4qH4Gc EbAaf4ui5gO2RUvY6tUXdiVCzNhCXwTiu7MxI087D8aNb9t0pT42MyeMYcOl6mGKdICA dOvTdqlNLa+sB71vso+TI2ckbCUOdwmYZQuobkNGpPW7w+8OcruXuQLmH/BV3IQ1pwdg Cv2VQvGa2Z9XKRXV9ffKNvr/ZsyRnlSFvmgGK+NV1NtqUD0+aXnkeSbNOXDi81IYbaBw JBE0P35M0aHaXyYqroWdEJtxjoGqWTC9+JjXbpemzYmoAhgOZXNPXW7Ic0a+cmKK4XvG pafw== X-Gm-Message-State: AOJu0YzELvAsksLiz/9b8I5A746tc3rLDEeycOet+xgoODSSYAQIQ+6l M0Inrad8ZKoWsB+l4tUWwHtI0QIWFZCo8g== X-Google-Smtp-Source: AGHT+IG1ceziC/+z97gXuY0UcTtf4RtdValQD8/J9dsJkOT+P4ZAnEAQamQO6FPuVGCiIDUiL9zX0A== X-Received: by 2002:a05:600c:1d03:b0:40b:3e26:8733 with SMTP id l3-20020a05600c1d0300b0040b3e268733mr3829685wms.0.1700963639298; Sat, 25 Nov 2023 17:53:59 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id p34-20020a05600c1da200b00406408dc788sm9875344wms.44.2023.11.25.17.53.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 17:53:59 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next PATCH RFC v3 5/8] dt-bindings: net: add QCA807x PHY defines Date: Sun, 26 Nov 2023 02:53:43 +0100 Message-Id: <20231126015346.25208-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231126015346.25208-1-ansuelsmth@gmail.com> References: <20231126015346.25208-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Robert Marko Add DT bindings defined for Qualcomm QCA807x PHY series related to calibration and DAC settings. Signed-off-by: Robert Marko Signed-off-by: Christian Marangi --- include/dt-bindings/net/qcom-qca807x.h | 30 ++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 include/dt-bindings/net/qcom-qca807x.h diff --git a/include/dt-bindings/net/qcom-qca807x.h b/include/dt-bindings/net/qcom-qca807x.h new file mode 100644 index 000000000000..e7d4d09b7dd4 --- /dev/null +++ b/include/dt-bindings/net/qcom-qca807x.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Device Tree constants for the Qualcomm QCA807X PHYs + */ + +#ifndef _DT_BINDINGS_QCOM_QCA807X_H +#define _DT_BINDINGS_QCOM_QCA807X_H + +/* Full amplitude, full bias current */ +#define QCA807X_CONTROL_DAC_FULL_VOLT_BIAS 0 +/* Amplitude follow DSP (amplitude is adjusted based on cable length), half bias current */ +#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS 1 +/* Full amplitude, bias current follow DSP (bias current is adjusted based on cable length) */ +#define QCA807X_CONTROL_DAC_FULL_VOLT_DSP_BIAS 2 +/* Both amplitude and bias current follow DSP */ +#define QCA807X_CONTROL_DAC_DSP_VOLT_BIAS 3 +/* Full amplitude, half bias current */ +#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS 4 +/* Amplitude follow DSP setting; 1/4 bias current when cable<10m, + * otherwise half bias current + */ +#define QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS 5 +/* Full amplitude; same bias current setting with “010” and “011”, + * but half more bias is reduced when cable <10m + */ +#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS_SHORT 6 +/* Amplitude follow DSP; same bias current setting with “110”, default value */ +#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS_SHORT 7 + +#endif From patchwork Sun Nov 26 01:53:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 747429 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dwDHoJ53" Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF94612D; Sat, 25 Nov 2023 17:54:04 -0800 (PST) Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4079ed65582so21063185e9.1; Sat, 25 Nov 2023 17:54:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700963643; x=1701568443; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Zx613whbRcvHwJRu+KDlj3qWu/B2xTU9Sffj+PGCEg4=; b=dwDHoJ53cNEtpFJnxmg8sZfq4Dy5JyMzr49Mu9iZKsT/Sz7nnrhQ9w2SJrt6Vy8su8 JoQaBWcjBHZ03OLrHXk5hI3ccibjp7zDqLzcDb5JRtozWH1zIv/X1tNIA1PFpPAttny+ zMj5dFMQ9B4h6ND04mvSU58IvScmrUanyZpP0pdX8+V9KzwmFVMZgnFzpnGcH1XbB2pL D/Ir9QK2EGWCzRqrkmbl5UcJOlRPa8VmLifU/U5qodpGqKP/iys34Wj3kPcaNxf78bXq TDKVH6R05sQUYvrE0aZcZIiX0yPsQgWD2fPELBtTfME1g7uUanb3PmCaEcTP7gJoT7XV FSbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700963643; x=1701568443; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zx613whbRcvHwJRu+KDlj3qWu/B2xTU9Sffj+PGCEg4=; b=WNeaLvetpeuirxYUnC3CSKaBsJlqhi92u/h8RJfduqUefPdXs8fgZ4fAzE3iRe+Vgu AMTIHL6odsfD7hBdiA+FSu2EKhv/H5JEBQLke+lgtP+WBzz0k7Wh78twQZo0MsCZCVzt LTKMsThtMF/F/Rh1UXuOkzVXV1E14wPLSi3knza+R7Y+evWaHXSBVT9DRQ8S19lBmiqS kjOr3K/P10ddC9O9qwWlWjUo9g1QVfknvnmUKJZS+PZhIh3NmahYxNXa/J+epRc07TmT 4ai9638AQfbjzThHAiUVkDcuJOId0PvXWrLtVKy94GwkZ5mcMxE4gBsrMFxn7Obdaj31 2/fQ== X-Gm-Message-State: AOJu0Yx9Ca+W/79E7FglfbA/vGkdzOcIkIyMjMMfoiIWdrvu9b5z17AI oRUC6l60lRk4gHqn0LqhkIs= X-Google-Smtp-Source: AGHT+IEppVdgFBdrmKPjDgzJlLd5FpI40ucsVwSm9OSTRl19LbUuF+6d7eHsWRDkMx/3j4fENS/p6A== X-Received: by 2002:a05:600c:1c12:b0:407:612b:91fb with SMTP id j18-20020a05600c1c1200b00407612b91fbmr2059247wms.30.1700963643104; Sat, 25 Nov 2023 17:54:03 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id p34-20020a05600c1da200b00406408dc788sm9875344wms.44.2023.11.25.17.54.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 17:54:02 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next PATCH RFC v3 8/8] net: phy: qca807x: Add support for configurable LED Date: Sun, 26 Nov 2023 02:53:46 +0100 Message-Id: <20231126015346.25208-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231126015346.25208-1-ansuelsmth@gmail.com> References: <20231126015346.25208-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 QCA8072/5 have up to 2 LEDs attached for PHY. LEDs can be configured to be ON/hw blink or be set to HW control. Hw blink mode is set to blink at 4Hz or 250ms. PHY can support both copper (TP) or fiber (FIBRE) kind and supports different HW control modes based on the port type. HW control modes supported for netdev trigger for copper ports are: - LINK_10 - LINK_100 - LINK_1000 - TX - RX - FULL_DUPLEX - HALF_DUPLEX HW control modes supported for netdev trigger for fiber ports are: - LINK_100 - LINK_1000 - TX - RX - FULL_DUPLEX - HALF_DUPLEX LED support conflicts with GPIO controller feature and must be disabled if gpio-controller is used for the PHY. Signed-off-by: Christian Marangi --- drivers/net/phy/qca807x.c | 382 +++++++++++++++++++++++++++++++++++++- 1 file changed, 375 insertions(+), 7 deletions(-) diff --git a/drivers/net/phy/qca807x.c b/drivers/net/phy/qca807x.c index be039d6de1fb..3c11b39ebe7e 100644 --- a/drivers/net/phy/qca807x.c +++ b/drivers/net/phy/qca807x.c @@ -79,17 +79,60 @@ #define QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH 0x801a #define QCA807X_CONTROL_DAC_MASK GENMASK(2, 0) +#define QCA807X_MMD7_LED_GLOBAL 0x8073 +#define QCA807X_LED_BLINK_1 GENMASK(11, 6) +#define QCA807X_LED_BLINK_2 GENMASK(5, 0) +/* Values are the same for both BLINK_1 and BLINK_2 */ +#define QCA807X_LED_BLINK_FREQ_MASK GENMASK(5, 3) +#define QCA807X_LED_BLINK_FREQ_2HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x0) +#define QCA807X_LED_BLINK_FREQ_4HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x1) +#define QCA807X_LED_BLINK_FREQ_8HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x2) +#define QCA807X_LED_BLINK_FREQ_16HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x3) +#define QCA807X_LED_BLINK_FREQ_32HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x4) +#define QCA807X_LED_BLINK_FREQ_64HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x5) +#define QCA807X_LED_BLINK_FREQ_128HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x6) +#define QCA807X_LED_BLINK_FREQ_256HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x7) +#define QCA807X_LED_BLINK_DUTY_MASK GENMASK(2, 0) +#define QCA807X_LED_BLINK_DUTY_50_50 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x0) +#define QCA807X_LED_BLINK_DUTY_75_25 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x1) +#define QCA807X_LED_BLINK_DUTY_25_75 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x2) +#define QCA807X_LED_BLINK_DUTY_33_67 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x3) +#define QCA807X_LED_BLINK_DUTY_67_33 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x4) +#define QCA807X_LED_BLINK_DUTY_17_83 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x5) +#define QCA807X_LED_BLINK_DUTY_83_17 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x6) +#define QCA807X_LED_BLINK_DUTY_8_92 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x7) #define QCA807X_MMD7_LED_100N_1 0x8074 #define QCA807X_MMD7_LED_100N_2 0x8075 #define QCA807X_MMD7_LED_1000N_1 0x8076 #define QCA807X_MMD7_LED_1000N_2 0x8077 -#define QCA807X_LED_TXACT_BLK_EN_2 BIT(10) -#define QCA807X_LED_RXACT_BLK_EN_2 BIT(9) -#define QCA807X_LED_GT_ON_EN_2 BIT(6) -#define QCA807X_LED_HT_ON_EN_2 BIT(5) -#define QCA807X_LED_BT_ON_EN_2 BIT(4) -#define QCA807X_GPIO_FORCE_EN BIT(15) -#define QCA807X_GPIO_FORCE_MODE_MASK GENMASK(14, 13) +/* Values are the same for LED1 and LED2 */ +/* Values for control 1 */ +#define QCA807X_LED_COPPER_ON_BLINK_MASK GENMASK(12, 0) +#define QCA807X_LED_FDX_ON_EN BIT(12) +#define QCA807X_LED_HDX_ON_EN BIT(11) +#define QCA807X_LED_TXACT_BLK_EN BIT(10) +#define QCA807X_LED_RXACT_BLK_EN BIT(9) +#define QCA807X_LED_GT_ON_EN BIT(6) +#define QCA807X_LED_HT_ON_EN BIT(5) +#define QCA807X_LED_BT_ON_EN BIT(4) +/* Values for control 2 */ +#define QCA807X_LED_FORCE_EN BIT(15) +#define QCA807X_LED_FORCE_MODE_MASK GENMASK(14, 13) +#define QCA807X_LED_FORCE_BLINK_1 FIELD_PREP(QCA807X_LED_FORCE_MODE_MASK, 0x3) +#define QCA807X_LED_FORCE_BLINK_2 FIELD_PREP(QCA807X_LED_FORCE_MODE_MASK, 0x2) +#define QCA807X_LED_FORCE_ON FIELD_PREP(QCA807X_LED_FORCE_MODE_MASK, 0x1) +#define QCA807X_LED_FORCE_OFF FIELD_PREP(QCA807X_LED_FORCE_MODE_MASK, 0x0) +#define QCA807X_LED_FIBER_ON_BLINK_MASK GENMASK(11, 1) +#define QCA807X_LED_FIBER_TXACT_BLK_EN BIT(10) +#define QCA807X_LED_FIBER_RXACT_BLK_EN BIT(9) +#define QCA807X_LED_FIBER_FDX_ON_EN BIT(6) +#define QCA807X_LED_FIBER_HDX_ON_EN BIT(5) +#define QCA807X_LED_FIBER_1000BX_ON_EN BIT(2) +#define QCA807X_LED_FIBER_100FX_ON_EN BIT(1) + +/* Some device repurpose the LED as GPIO out */ +#define QCA807X_GPIO_FORCE_EN QCA807X_LED_FORCE_EN +#define QCA807X_GPIO_FORCE_MODE_MASK QCA807X_LED_FORCE_MODE_MASK #define QCA807X_INTR_ENABLE 0x12 #define QCA807X_INTR_STATUS 0x13 @@ -350,6 +393,320 @@ static int qca807x_cable_test_start(struct phy_device *phydev) return ret; } +static int qca807x_led_parse_netdev(struct phy_device *phydev, unsigned long rules, + u16 *offload_trigger) +{ + /* Parsing specific to netdev trigger */ + switch (phydev->port) { + case PORT_TP: + if (test_bit(TRIGGER_NETDEV_TX, &rules)) + *offload_trigger |= QCA807X_LED_TXACT_BLK_EN; + if (test_bit(TRIGGER_NETDEV_RX, &rules)) + *offload_trigger |= QCA807X_LED_RXACT_BLK_EN; + if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) + *offload_trigger |= QCA807X_LED_BT_ON_EN; + if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) + *offload_trigger |= QCA807X_LED_HT_ON_EN; + if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) + *offload_trigger |= QCA807X_LED_GT_ON_EN; + if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) + *offload_trigger |= QCA807X_LED_HDX_ON_EN; + if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) + *offload_trigger |= QCA807X_LED_FDX_ON_EN; + break; + case PORT_FIBRE: + if (test_bit(TRIGGER_NETDEV_TX, &rules)) + *offload_trigger |= QCA807X_LED_FIBER_TXACT_BLK_EN; + if (test_bit(TRIGGER_NETDEV_RX, &rules)) + *offload_trigger |= QCA807X_LED_FIBER_RXACT_BLK_EN; + if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) + *offload_trigger |= QCA807X_LED_FIBER_100FX_ON_EN; + if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) + *offload_trigger |= QCA807X_LED_FIBER_1000BX_ON_EN; + if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) + *offload_trigger |= QCA807X_LED_FIBER_HDX_ON_EN; + if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) + *offload_trigger |= QCA807X_LED_FIBER_FDX_ON_EN; + break; + default: + return -EOPNOTSUPP; + } + + if (rules && !*offload_trigger) + return -EOPNOTSUPP; + + return 0; +} + +static int qca807x_led_hw_control_enable(struct phy_device *phydev, u8 index) +{ + int val, reg, ret; + + switch (index) { + case 0: + reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + reg = QCA807X_MMD7_LED_1000N_2; + break; + default: + return -EINVAL; + } + + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); + val &= ~QCA807X_LED_FORCE_EN; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, reg, val); + + return ret; +} + +static int qca807x_led_hw_is_supported(struct phy_device *phydev, u8 index, + unsigned long rules) +{ + u16 offload_trigger = 0; + + if (index > 1) + return -EINVAL; + + return qca807x_led_parse_netdev(phydev, rules, &offload_trigger); +} + +static int qca807x_led_hw_control_set(struct phy_device *phydev, u8 index, + unsigned long rules) +{ + int val, ret, copper_reg, fibre_reg; + u16 offload_trigger = 0; + + switch (index) { + case 0: + copper_reg = QCA807X_MMD7_LED_100N_1; + fibre_reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + copper_reg = QCA807X_MMD7_LED_1000N_1; + fibre_reg = QCA807X_MMD7_LED_1000N_2; + break; + default: + return -EINVAL; + } + + ret = qca807x_led_parse_netdev(phydev, rules, &offload_trigger); + if (ret) + return ret; + + ret = qca807x_led_hw_control_enable(phydev, index); + if (ret) + return ret; + + switch (phydev->port) { + case PORT_TP: + val = phy_read_mmd(phydev, MDIO_MMD_AN, copper_reg); + val &= ~QCA807X_LED_COPPER_ON_BLINK_MASK; + val |= offload_trigger; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, copper_reg, val); + break; + case PORT_FIBRE: + val = phy_read_mmd(phydev, MDIO_MMD_AN, fibre_reg); + val &= ~QCA807X_LED_FIBER_ON_BLINK_MASK; + val |= offload_trigger; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, fibre_reg, val); + break; + default: + return -EINVAL; + } + + return ret; +} + +static bool qca807x_led_hw_control_status(struct phy_device *phydev, u8 index) +{ + int val, reg; + + switch (index) { + case 0: + reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + reg = QCA807X_MMD7_LED_1000N_2; + break; + default: + return false; + } + + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); + + return !(val & QCA807X_LED_FORCE_EN); +} + +static int qca807x_led_hw_control_get(struct phy_device *phydev, u8 index, + unsigned long *rules) +{ + int val, copper_reg, fibre_reg; + + switch (index) { + case 0: + copper_reg = QCA807X_MMD7_LED_100N_1; + fibre_reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + copper_reg = QCA807X_MMD7_LED_1000N_1; + fibre_reg = QCA807X_MMD7_LED_100N_2; + break; + default: + return -EINVAL; + } + + /* Check if we have hw control enabled */ + if (qca807x_led_hw_control_status(phydev, index)) + return -EINVAL; + + /* Parsing specific to netdev trigger */ + switch (phydev->port) { + case PORT_TP: + val = phy_read_mmd(phydev, MDIO_MMD_AN, copper_reg); + if (val & QCA807X_LED_TXACT_BLK_EN) + set_bit(TRIGGER_NETDEV_TX, rules); + if (val & QCA807X_LED_RXACT_BLK_EN) + set_bit(TRIGGER_NETDEV_RX, rules); + if (val & QCA807X_LED_BT_ON_EN) + set_bit(TRIGGER_NETDEV_LINK_10, rules); + if (val & QCA807X_LED_HT_ON_EN) + set_bit(TRIGGER_NETDEV_LINK_100, rules); + if (val & QCA807X_LED_GT_ON_EN) + set_bit(TRIGGER_NETDEV_LINK_1000, rules); + if (val & QCA807X_LED_HDX_ON_EN) + set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules); + if (val & QCA807X_LED_FDX_ON_EN) + set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules); + break; + case PORT_FIBRE: + val = phy_read_mmd(phydev, MDIO_MMD_AN, fibre_reg); + if (val & QCA807X_LED_FIBER_TXACT_BLK_EN) + set_bit(TRIGGER_NETDEV_TX, rules); + if (val & QCA807X_LED_FIBER_RXACT_BLK_EN) + set_bit(TRIGGER_NETDEV_RX, rules); + if (val & QCA807X_LED_FIBER_100FX_ON_EN) + set_bit(TRIGGER_NETDEV_LINK_100, rules); + if (val & QCA807X_LED_FIBER_1000BX_ON_EN) + set_bit(TRIGGER_NETDEV_LINK_1000, rules); + if (val & QCA807X_LED_FIBER_HDX_ON_EN) + set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules); + if (val & QCA807X_LED_FIBER_FDX_ON_EN) + set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int qca807x_led_hw_control_reset(struct phy_device *phydev, u8 index) +{ + int val, copper_reg, fibre_reg, ret; + + switch (index) { + case 0: + copper_reg = QCA807X_MMD7_LED_100N_1; + fibre_reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + copper_reg = QCA807X_MMD7_LED_1000N_1; + fibre_reg = QCA807X_MMD7_LED_100N_2; + break; + default: + return -EINVAL; + } + + switch (phydev->port) { + case PORT_TP: + val = phy_read_mmd(phydev, MDIO_MMD_AN, copper_reg); + val &= ~QCA807X_LED_COPPER_ON_BLINK_MASK; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, copper_reg, val); + break; + case PORT_FIBRE: + val = phy_read_mmd(phydev, MDIO_MMD_AN, fibre_reg); + val &= ~QCA807X_LED_FIBER_ON_BLINK_MASK; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, fibre_reg, val); + break; + default: + return -EINVAL; + } + + return ret; +} + +static int qca807x_led_brightness_set(struct phy_device *phydev, + u8 index, enum led_brightness value) +{ + int val, ret; + u16 reg; + + switch (index) { + case 0: + reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + reg = QCA807X_MMD7_LED_1000N_2; + break; + default: + return -EINVAL; + } + + /* If we are setting off the LED reset any hw control rule */ + if (!value) { + ret = qca807x_led_hw_control_reset(phydev, index); + if (ret) + return ret; + } + + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); + val &= ~(QCA807X_LED_FORCE_EN | QCA807X_LED_FORCE_MODE_MASK); + val |= QCA807X_LED_FORCE_EN; + if (value) + val |= QCA807X_LED_FORCE_ON; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, reg, val); + + return ret; +} + +static int qca807x_led_blink_set(struct phy_device *phydev, u8 index, + unsigned long *delay_on, + unsigned long *delay_off) +{ + int val, ret; + u16 reg; + + switch (index) { + case 0: + reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + reg = QCA807X_MMD7_LED_1000N_2; + break; + default: + return -EINVAL; + } + + /* Set blink to 50% off, 50% on at 4Hz by default */ + val = phy_read_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_LED_GLOBAL); + val &= ~(QCA807X_LED_BLINK_FREQ_MASK | QCA807X_LED_BLINK_DUTY_MASK); + val |= QCA807X_LED_BLINK_FREQ_4HZ | QCA807X_LED_BLINK_DUTY_50_50; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_LED_GLOBAL, val); + + /* We use BLINK_1 for normal blinking */ + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); + val &= ~(QCA807X_LED_FORCE_EN | QCA807X_LED_FORCE_MODE_MASK); + val |= QCA807X_LED_FORCE_EN | QCA807X_LED_FORCE_BLINK_1; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, reg, val); + + /* We set blink to 4Hz, aka 250ms */ + *delay_on = 250 / 2; + *delay_off = 250 / 2; + + return ret; +} + #ifdef CONFIG_GPIOLIB static int qca807x_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) { @@ -739,6 +1096,12 @@ static int qca807x_probe(struct phy_device *phydev) ret = qca807x_gpio(phydev); if (ret) return ret; + + phydev->drv->led_brightness_set = NULL; + phydev->drv->led_blink_set = NULL; + phydev->drv->led_hw_is_supported = NULL; + phydev->drv->led_hw_control_set = NULL; + phydev->drv->led_hw_control_get = NULL; } } @@ -926,6 +1289,11 @@ static struct phy_driver qca807x_drivers[] = { .suspend = genphy_suspend, .cable_test_start = qca807x_cable_test_start, .cable_test_get_status = qca807x_cable_test_get_status, + .led_brightness_set = qca807x_led_brightness_set, + .led_blink_set = qca807x_led_blink_set, + .led_hw_is_supported = qca807x_led_hw_is_supported, + .led_hw_control_set = qca807x_led_hw_control_set, + .led_hw_control_get = qca807x_led_hw_control_get, /* PHY package define */ .phy_package_priv_data_size = sizeof(struct qca807x_shared_priv), .phy_package_probe_once = qca807x_phy_package_probe_once,