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Tue, 12 Dec 2023 04:34:11 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, Brian Cain , Thomas Huth , Paolo Bonzini , qemu-arm@nongnu.org, Manos Pitsidianakis , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson , Warner Losh , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 01/23] exec: Include 'cpu.h' before validating CPUArchState placement Date: Tue, 12 Dec 2023 13:33:37 +0100 Message-ID: <20231212123401.37493-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212123401.37493-1-philmd@linaro.org> References: <20231212123401.37493-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=philmd@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CPUArchState 'env' field is defined within the ArchCPU structure, so we need to include each target "cpu.h" header which defines it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh --- include/exec/cpu-all.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 5340907cfd..9a7b5737d3 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -411,10 +411,6 @@ static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) /* accel/tcg/cpu-exec.c */ int cpu_exec(CPUState *cpu); -/* Validate correct placement of CPUArchState. */ -QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0); -QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState)); - /** * env_archcpu(env) * @env: The architecture environment @@ -437,4 +433,9 @@ static inline CPUState *env_cpu(CPUArchState *env) return (void *)env - sizeof(CPUState); } +/* Validate correct placement of CPUArchState. */ +#include "cpu.h" +QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0); +QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState)); + #endif /* CPU_ALL_H */ From patchwork Tue Dec 12 12:33:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753060 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1875371wrs; Tue, 12 Dec 2023 04:35:48 -0800 (PST) X-Google-Smtp-Source: AGHT+IElYrYh/VZm4DuV9qqGTzoR1RQbrSCHSVK2Umw8nQUanlfiubmi/XNEIJyqZAyFBJNPQbhL X-Received: by 2002:a05:6870:5aaa:b0:1e9:f0fe:6ba4 with SMTP id dt42-20020a0568705aaa00b001e9f0fe6ba4mr5440325oab.11.1702384547679; Tue, 12 Dec 2023 04:35:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702384547; cv=none; d=google.com; s=arc-20160816; b=SBAhyTVPeOO+B5kYwIbM1mBlXNlJB7YqeiF4JzsW0OgLamgeDlLo0P/MvSzSPKCbPc Qw6UhAzi1PZibtIPZfKURLpdRIdKOUVhZkgtqkmtfKlJoL6I3PHRDV/4/KhGpLXqZYFi sQWeHJB2N6qVB1Jb06DBaU+1K/Xqsn1/P4nhJ+mf1P0RKaPDg0MFKIZ8RooqQZY1H/ZA vRm84VNEVnBAqtuX6tI9BIK7BgDsISUtdXnov/+voqV4ORRbFzRRnLeuetJgxy4UjMwS f/ubA3ASMlO9VOLcCp4QewHrdRCfmBn/0SkxdB2GMTXNEMWXJr70cTkhBcXgPFKU+cPr 2XHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=NDQDiSIXlkgjP0mASXiCW1Z5PDJEfauay7W7xh/vCZQ=; fh=L9+xlWXyKm6KsUaf8nJ3E7Oku33KOKYECsFhykRkiiE=; b=kNR5mppD2I26H7USfluIZZhOLgcutoH+n/VNZXIKyaJtG/FonHTffxVPfGKtFAdN2t 4AHydTzI1PFQOwMS274vo94DlpcFYj66vl3A9GDocB6viWKJXqrPOQg8pg1ifbB2tfh1 WmlCa6GRqvpkVmQp73m3FyXUOol+vpPfhavfi8gagVdjvNkUhz5TVOZHFInR7jM8LgiW M5gGbsckWrdmgL/c65JWTzgoQp6pk9n9r/5erOArNSvweGyfVAcfxf+cX7PJ5eF8JgS8 kN+DcdPvRZY3Q2tlj0bNfo4sATUJJCY07jKff0aoEL7FLA6S6XtJDWdD42Cgn4WfwhS9 PU4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TI3PkvJA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 12 Dec 2023 04:34:19 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, Brian Cain , Thomas Huth , Paolo Bonzini , qemu-arm@nongnu.org, Manos Pitsidianakis , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson , Warner Losh , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Marc-And?= =?utf-8?q?r=C3=A9_Lureau?= , =?utf-8?q?Daniel_?= =?utf-8?q?P=2E_Berrang=C3=A9?= , Peter Xu , David Hildenbrand Subject: [PATCH v2 02/23] exec: Expose 'target_page.h' API to user emulation Date: Tue, 12 Dec 2023 13:33:38 +0100 Message-ID: <20231212123401.37493-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212123401.37493-1-philmd@linaro.org> References: <20231212123401.37493-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=philmd@linaro.org; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org User-only objects might benefit from the "exec/target_page.h" API, which allows to build some objects once for all targets. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Reviewed-by: Richard Henderson --- meson.build | 2 +- page-target.c | 43 +++++++++++++++++++++++++++++++++++++++++++ system/physmem.c | 35 ----------------------------------- 3 files changed, 44 insertions(+), 36 deletions(-) create mode 100644 page-target.c diff --git a/meson.build b/meson.build index d2c4c2adb3..5fdc4ef8db 100644 --- a/meson.build +++ b/meson.build @@ -3488,7 +3488,7 @@ if get_option('b_lto') pagevary = declare_dependency(link_with: pagevary) endif common_ss.add(pagevary) -specific_ss.add(files('page-vary-target.c')) +specific_ss.add(files('page-target.c', 'page-vary-target.c')) subdir('backends') subdir('disas') diff --git a/page-target.c b/page-target.c new file mode 100644 index 0000000000..d286e2d58b --- /dev/null +++ b/page-target.c @@ -0,0 +1,43 @@ +/* + * QEMU page values getters (target independent) + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "exec/target_page.h" +#include "exec/cpu-defs.h" +#include "exec/cpu-all.h" + +size_t qemu_target_page_size(void) +{ + return TARGET_PAGE_SIZE; +} + +int qemu_target_page_mask(void) +{ + return TARGET_PAGE_MASK; +} + +int qemu_target_page_bits(void) +{ + return TARGET_PAGE_BITS; +} + +int qemu_target_page_bits_min(void) +{ + return TARGET_PAGE_BITS_MIN; +} + +/* Convert target pages to MiB (2**20). */ +size_t qemu_target_pages_to_MiB(size_t pages) +{ + int page_bits = TARGET_PAGE_BITS; + + /* So far, the largest (non-huge) page size is 64k, i.e. 16 bits. */ + g_assert(page_bits < 20); + + return pages >> (20 - page_bits); +} diff --git a/system/physmem.c b/system/physmem.c index a63853a7bc..4bdb3d0592 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -3422,41 +3422,6 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, return 0; } -/* - * Allows code that needs to deal with migration bitmaps etc to still be built - * target independent. - */ -size_t qemu_target_page_size(void) -{ - return TARGET_PAGE_SIZE; -} - -int qemu_target_page_mask(void) -{ - return TARGET_PAGE_MASK; -} - -int qemu_target_page_bits(void) -{ - return TARGET_PAGE_BITS; -} - -int qemu_target_page_bits_min(void) -{ - return TARGET_PAGE_BITS_MIN; -} - -/* Convert target pages to MiB (2**20). */ -size_t qemu_target_pages_to_MiB(size_t pages) -{ - int page_bits = TARGET_PAGE_BITS; - - /* So far, the largest (non-huge) page size is 64k, i.e. 16 bits. */ - g_assert(page_bits < 20); - - return pages >> (20 - page_bits); -} - bool cpu_physical_memory_is_io(hwaddr phys_addr) { MemoryRegion*mr; From patchwork Tue Dec 12 12:33:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753065 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1875842wrs; Tue, 12 Dec 2023 04:36:49 -0800 (PST) X-Google-Smtp-Source: AGHT+IH9I8+m3VvzEZz3u8aEuqMjHWBMXI4WY2GHevAODpGlTAzcXpgw0WZhrGkt3tIEBp09k1Xv X-Received: by 2002:ac8:5984:0:b0:425:9a27:89a9 with SMTP id e4-20020ac85984000000b004259a2789a9mr8369618qte.60.1702384609366; Tue, 12 Dec 2023 04:36:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702384609; cv=none; d=google.com; s=arc-20160816; b=Ji8lspg5Qa1kM5qEzwF9Ctg3TkQpNgh1DbruvwH2/Rx6xp3YExdz9MkxEnVrrNGSHF IagyIxvFG7pQJYt6i2+4P0x34CJq4SGvzw4GqVOfiRJOMatzQ3QlHV0X6p39Qr2Wy9VQ 1h8zRQlXkxEBtuszyuaq8p0mjItxYlg14xSRB7Nx9Y+n1DUp+RFr6QOHILS+f97XDe6w Qp7C/J3FAU9J5WqgcNRhBYNNLKseYnNYAHHV4mptuMuu3+QgfvYMir1+aPBWshCK3eGM V2D2vXc2q3zcpzObxHoNqZsc+OuDgK6L/TTJtJdhQE7QPoI0UbLB9TZzw1JnMsGUTHqt fZhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gzbhv68ZzKweBnjWkRTwSmm/SDs4f1x+mdWf7p/OxfQ=; fh=lPxnjIzG9iRtjJWVU3RHKsNr723ZMNcTu34iECj9Lx8=; b=0H+NSnQGmPVlIRiiocixqjvHClsSLnaH2iMAhoMdjXSSjwSGkDSn9vJAmdoOgBmVnO h4HVFNLyCXjz/2kVfPf43qg7YmCS5+uCuLuk6/4GjvpzEB3stOQS0YN2T7yW0uRq7g+W vq6FPFimsQerGkDe3SzThFkaLhMkc5/NFnwI4AwP6sLmyArOTZK1BiBNzbdr3j55QaZk k9sE9X7u3hu0dmmE2uG+B0gKWbSjlF2a71mFHg5x9by/wq6mFX2PRcqSCzHdN9ZdOyX4 YMweYIkwfLJo/IwFZRik8wSywPZmsgb/LpW/XLQm03KTZeg9flkNHgAqniSob+hq4Dpe /hfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=do5N7ygw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , David Hildenbrand , Ilya Leoshkevich , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 03/23] target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h' Date: Tue, 12 Dec 2023 13:33:39 +0100 Message-ID: <20231212123401.37493-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212123401.37493-1-philmd@linaro.org> References: <20231212123401.37493-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12b; envelope-from=philmd@linaro.org; helo=mail-lf1-x12b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org accel/tcg/ files requires the following definitions: - TARGET_LONG_BITS - TARGET_PAGE_BITS - TARGET_PHYS_ADDR_SPACE_BITS - TCG_GUEST_DEFAULT_MO The first 3 are defined in "cpu-param.h". The last one in "cpu.h", with a bunch of definitions irrelevant for TCG. By moving the TCG_GUEST_DEFAULT_MO definition to "cpu-param.h", we can simplify various accel/tcg includes. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/alpha/cpu-param.h | 3 +++ target/alpha/cpu.h | 3 --- target/arm/cpu-param.h | 8 +++++--- target/arm/cpu.h | 3 --- target/avr/cpu-param.h | 2 ++ target/avr/cpu.h | 2 -- target/hppa/cpu-param.h | 8 ++++++++ target/hppa/cpu.h | 6 ------ target/i386/cpu-param.h | 3 +++ target/i386/cpu.h | 3 --- target/loongarch/cpu-param.h | 2 ++ target/loongarch/cpu.h | 2 -- target/microblaze/cpu-param.h | 3 +++ target/microblaze/cpu.h | 3 --- target/mips/cpu-param.h | 2 ++ target/mips/cpu.h | 2 -- target/openrisc/cpu-param.h | 2 ++ target/openrisc/cpu.h | 2 -- target/ppc/cpu-param.h | 2 ++ target/ppc/cpu.h | 2 -- target/riscv/cpu-param.h | 2 ++ target/riscv/cpu.h | 2 -- target/s390x/cpu-param.h | 6 ++++++ target/s390x/cpu.h | 3 --- target/sparc/cpu-param.h | 23 +++++++++++++++++++++++ target/sparc/cpu.h | 23 ----------------------- target/xtensa/cpu-param.h | 3 +++ target/xtensa/cpu.h | 3 --- 28 files changed, 66 insertions(+), 62 deletions(-) diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index 68c46f7998..419e454702 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -15,4 +15,7 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 44 #define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) +/* Alpha processors have a weak memory model */ +#define TCG_GUEST_DEFAULT_MO (0) + #endif diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index d672e911dd..5d9aa09ed9 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -24,9 +24,6 @@ #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" -/* Alpha processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #define ICACHE_LINE_SIZE 32 #define DCACHE_LINE_SIZE 32 diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index f9b462a98f..59a5f9e480 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -23,14 +23,16 @@ # ifdef TARGET_AARCH64 # define TARGET_TAGGED_ADDRESSES # endif -#else +#else /* !CONFIG_USER_ONLY */ /* * ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 * have to support 1K tiny pages. */ # define TARGET_PAGE_BITS_VARY # define TARGET_PAGE_BITS_MIN 10 - -#endif +#endif /* !CONFIG_USER_ONLY */ + +/* ARM processors have a weak memory model */ +#define TCG_GUEST_DEFAULT_MO (0) #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a0282e0d28..ea5c8660dc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -27,9 +27,6 @@ #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" -/* ARM processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #ifdef TARGET_AARCH64 #define KVM_HAVE_MCE_INJECTION 1 #endif diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 9a92bc74fc..93c2f470d0 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -32,4 +32,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24 +#define TCG_GUEST_DEFAULT_MO 0 + #endif diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 7960c5c57a..02a787b4f3 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -30,8 +30,6 @@ #define CPU_RESOLVING_TYPE TYPE_AVR_CPU -#define TCG_GUEST_DEFAULT_MO 0 - /* * AVR has two memory spaces, data & code. * e.g. both have 0 address diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index bb3d7ef6f7..473d489f01 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -21,4 +21,12 @@ #define TARGET_PAGE_BITS 12 +/* PA-RISC 1.x processors have a strong memory model. */ +/* + * ??? While we do not yet implement PA-RISC 2.0, those processors have + * a weak memory model, but with TLB bits that force ordering on a per-page + * basis. It's probably easier to fall back to a strong memory model. + */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 8be45c69c9..6b10ab20ba 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -25,12 +25,6 @@ #include "qemu/cpu-float.h" #include "qemu/interval-tree.h" -/* PA-RISC 1.x processors have a strong memory model. */ -/* ??? While we do not yet implement PA-RISC 2.0, those processors have - a weak memory model, but with TLB bits that force ordering on a per-page - basis. It's probably easier to fall back to a strong memory model. */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #define MMU_ABS_W_IDX 6 #define MMU_ABS_IDX 7 #define MMU_KERNEL_IDX 8 diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index 911b4cd51b..5e15335203 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -24,4 +24,7 @@ #endif #define TARGET_PAGE_BITS 12 +/* The x86 has a strong memory model with some store-after-load re-ordering */ +#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) + #endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index cd2e295bd6..852adf35db 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -30,9 +30,6 @@ #define XEN_NR_VIRQS 24 -/* The x86 has a strong memory model with some store-after-load re-ordering */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) - #define KVM_HAVE_MCE_INJECTION 1 /* support for self modifying code even if the modified instruction is diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index cfe195db4e..db5ad1c69f 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -14,4 +14,6 @@ #define TARGET_PAGE_BITS 12 +#define TCG_GUEST_DEFAULT_MO (0) + #endif diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 00d1fba597..dd1ab75ce9 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -39,8 +39,6 @@ #define IOCSR_MEM_SIZE 0x428 -#define TCG_GUEST_DEFAULT_MO (0) - #define FCSR0_M1 0x1f /* FCSR1 mask, Enables */ #define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */ #define FCSR0_M3 0x300 /* FCSR3 mask, Round Mode */ diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index 9770b0eb52..e530fead1c 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -29,4 +29,7 @@ /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ #define TARGET_PAGE_BITS 12 +/* MicroBlaze is always in-order. */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b5374365f5..943bae67d1 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -24,9 +24,6 @@ #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" -/* MicroBlaze is always in-order. */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - typedef struct CPUArchState CPUMBState; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 594c91a156..6f6ac1688f 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -30,4 +30,6 @@ #define TARGET_PAGE_BITS_MIN 12 #endif +#define TCG_GUEST_DEFAULT_MO (0) + #endif diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 52f13f0363..620db820f8 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -10,8 +10,6 @@ #include "hw/clock.h" #include "mips-defs.h" -#define TCG_GUEST_DEFAULT_MO (0) - typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; /* MSA Context */ diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h index 3f08207485..fbfc0f568b 100644 --- a/target/openrisc/cpu-param.h +++ b/target/openrisc/cpu-param.h @@ -13,4 +13,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define TCG_GUEST_DEFAULT_MO (0) + #endif diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index dedeb89f8e..e757e84caf 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -24,8 +24,6 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" -#define TCG_GUEST_DEFAULT_MO (0) - /** * OpenRISCCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index 0a0416e0a8..c5565beae2 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -33,4 +33,6 @@ #endif #define TARGET_PAGE_BITS 12 +#define TCG_GUEST_DEFAULT_MO 0 + #endif diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f8101ffa29..f21d8de6ff 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -29,8 +29,6 @@ #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU -#define TCG_GUEST_DEFAULT_MO 0 - #define TARGET_PAGE_BITS_64K 16 #define TARGET_PAGE_BITS_16M 24 diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index b2a9396dec..1fbd64939d 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -28,4 +28,6 @@ * - M mode HLV/HLVX/HSV 0b111 */ +#define TCG_GUEST_DEFAULT_MO 0 + #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d74b361be6..01cddf5180 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -42,8 +42,6 @@ typedef struct CPUArchState CPURISCVState; # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 #endif -#define TCG_GUEST_DEFAULT_MO 0 - /* * RISC-V-specific extra insn start words: * 1: Original instruction opcode diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index 84ca08626b..11d23b600d 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -13,4 +13,10 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 +/* + * The z/Architecture has a strong memory model with some + * store-after-load re-ordering. + */ +#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) + #endif diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index fa3aac4f97..10a63821b5 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -33,9 +33,6 @@ #define ELF_MACHINE_UNAME "S390X" -/* The z/Architecture has a strong memory model with some store-after-load re-ordering */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) - #define TARGET_HAS_PRECISE_SMC #define TARGET_INSN_START_EXTRA_WORDS 2 diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index cb11980404..82293fb844 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -23,4 +23,27 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif +/* + * From Oracle SPARC Architecture 2015: + * + * Compatibility notes: The PSO memory model described in SPARC V8 and + * SPARC V9 compatibility architecture specifications was never implemented + * in a SPARC V9 implementation and is not included in the Oracle SPARC + * Architecture specification. + * + * The RMO memory model described in the SPARC V9 specification was + * implemented in some non-Sun SPARC V9 implementations, but is not + * directly supported in Oracle SPARC Architecture 2015 implementations. + * + * Therefore always use TSO in QEMU. + * + * D.5 Specification of Partial Store Order (PSO) + * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. + * + * D.6 Specification of Total Store Order (TSO) + * ... PSO with the additional requirement that all [stores] are followed + * by an implied MEMBAR #StoreStore. + */ +#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) + #endif diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 6999a10a40..10b04d37c6 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -6,29 +6,6 @@ #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" -/* - * From Oracle SPARC Architecture 2015: - * - * Compatibility notes: The PSO memory model described in SPARC V8 and - * SPARC V9 compatibility architecture specifications was never implemented - * in a SPARC V9 implementation and is not included in the Oracle SPARC - * Architecture specification. - * - * The RMO memory model described in the SPARC V9 specification was - * implemented in some non-Sun SPARC V9 implementations, but is not - * directly supported in Oracle SPARC Architecture 2015 implementations. - * - * Therefore always use TSO in QEMU. - * - * D.5 Specification of Partial Store Order (PSO) - * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. - * - * D.6 Specification of Total Store Order (TSO) - * ... PSO with the additional requirement that all [stores] are followed - * by an implied MEMBAR #StoreStore. - */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) - #if !defined(TARGET_SPARC64) #define TARGET_DPREGS 16 #else diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index b1da0555de..0000725f2f 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -17,4 +17,7 @@ #define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif +/* Xtensa processors have a weak memory model */ +#define TCG_GUEST_DEFAULT_MO (0) + #endif diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 8a423706d8..ca32657041 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -34,9 +34,6 @@ #include "hw/clock.h" #include "xtensa-isa.h" -/* Xtensa processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - enum { /* Additional instructions */ XTENSA_OPTION_CODE_DENSITY, From patchwork Tue Dec 12 12:33:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753057 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1875114wrs; Tue, 12 Dec 2023 04:35:17 -0800 (PST) X-Google-Smtp-Source: AGHT+IHiKn2WpQGDN2kaom4r9q1gTgEHXS7BAGDT2CZBoCN3YbzVFqbVskaJHOM92zbGbR8CfJIj X-Received: by 2002:ae9:c003:0:b0:77e:fe58:5b58 with SMTP id u3-20020ae9c003000000b0077efe585b58mr7358514qkk.95.1702384517443; Tue, 12 Dec 2023 04:35:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702384517; cv=none; d=google.com; s=arc-20160816; b=yFzeoVfyxAc1T40zdENkEZGdqDsZ9HJv/fo9GbIAcpzH7mhukTP/2ieTu895UC2I// b+RjcnccNECXmMYh13yIr9yw9Rlg3y1tgfXjb0hnuxEXdYCwDOqWUmYEjohBy76lXE97 Tl+0pRp+HHuTUIQb/GvuOozJj77LsHDwngYHDWxDFXQxpeKbYRo0cj+h00zH1q4GKEii 0jstGMnS8CRq/XbUuBgMOkaTQq/uwhoEaSALopEsUvC07boLzY81mbRQrQkgLpHtfL5t RlO/NGT1UybFVgGSjNX0PvanEboqzggm4JzlM9lkV+STxdoKJ5kxNIRqk+69ohoQuJQu gmMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MXgjVQ2n+XwsEUqQbXGRL1Mo/9FL6x1+dKtNElcWrbs=; fh=gLv/fLsneP+NoZglr2Fx6cBcBP2mPFyvD4cPt6IOrfo=; b=mOqGyVNxGGLYReZcUjQWFcVHAeFvnQSy7dOO57/M8pgAhCpNuChPYBsiL/eABfKq7z 3V+Ya4haCjAgyYhtqnoPz86aeKRmW9kl/SvprwFMq+iRu7k7oDA0w6UCmBzMe/oTKrok Ox4uOD3Ty2lolYKqDvEgzkcAPwI0+04LVkznHt/LNCB7IWbGte4rvBntPqHLR1JPmqkB MXt7/jFg7+4CAuTenvLLba21YeyC0y+//YCNorh9VYDzYG36MX1kRyqgn5sRY/4lFkcg o71/HBrN5KTPUJXC0YnGLPh+rNr3kS87Tj9fGIo9kVWKC5rI2iapddFuM2ZmuznuhN5l 1TZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sq8oLII3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Chris Wulff , Marek Vasut Subject: [PATCH v2 04/23] accel: Include missing 'exec/cpu_ldst.h' header Date: Tue, 12 Dec 2023 13:33:40 +0100 Message-ID: <20231212123401.37493-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212123401.37493-1-philmd@linaro.org> References: <20231212123401.37493-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=philmd@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Theses files call cpu_ldl_code() which is declared in "exec/cpu_ldst.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/translator.c | 1 + target/hexagon/translate.c | 1 + target/microblaze/cpu.c | 1 + target/microblaze/translate.c | 1 + target/nios2/translate.c | 1 + 5 files changed, 5 insertions(+) diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 38c34009a5..5b019a0852 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -12,6 +12,7 @@ #include "qemu/error-report.h" #include "exec/exec-all.h" #include "exec/translator.h" +#include "exec/cpu_ldst.h" #include "exec/plugin-gen.h" #include "tcg/tcg-op-common.h" #include "internal-target.h" diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 666c061180..744dc4fc3f 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -23,6 +23,7 @@ #include "exec/helper-gen.h" #include "exec/helper-proto.h" #include "exec/translation-block.h" +#include "exec/cpu_ldst.h" #include "exec/log.h" #include "internal.h" #include "attribs.h" diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bbb3335cad..91d7cd9061 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -28,6 +28,7 @@ #include "qemu/module.h" #include "hw/qdev-properties.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "exec/gdbstub.h" #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 49bfb4a0ea..1c9a364c2b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "disas/disas.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "tcg/tcg-op.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" diff --git a/target/nios2/translate.c b/target/nios2/translate.c index e806623594..a74eb6909f 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -25,6 +25,7 @@ #include "cpu.h" #include "tcg/tcg-op.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "disas/disas.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" From patchwork Tue Dec 12 12:33:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753069 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1876370wrs; Tue, 12 Dec 2023 04:37:52 -0800 (PST) X-Google-Smtp-Source: AGHT+IHeH9mgCXJswv7v5hMnFI/F50zfOYANKbXLw+iShK5M0VWHWQYXAaAskpM4enQOz/9lPnnq X-Received: by 2002:ac8:7c46:0:b0:425:8f81:6c8b with SMTP id o6-20020ac87c46000000b004258f816c8bmr10399848qtv.53.1702384671970; Tue, 12 Dec 2023 04:37:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702384671; cv=none; d=google.com; s=arc-20160816; b=JuTz8ooCZzikz2FIz5iTuDA7+784HsQcNUrLI7miCUoMngHolBUHkX9v0oLHef/tIA KVzowEVFLePUgs+Zqj5EM3luSP8nZV7gOTRhG8QhHc30X1iTL1tkaNV095/BReDVSpAK eStr81Gaq5rYHHQp06Oi9K0RRN+d/y9s8cn4huJmRH02YaRfCClS//fhW9s3LORTEFVu zxN8yZ2+99Pv7/2WldGkRPKCwCJnyY526+5l3Sy2wd9bcGLwNc4eW1d5kaWwVhg2nWoM 8DQGiXzz+K47tlhBl+8r9WbxHC8UJnxiMbpXx3ihSDl+vWquZruq2ZwjislanPdTxUJ+ F8lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hNDHIJ1gpHeb2DpFjhHXsFTasuOwWoH4S7CHuQ8aaek=; fh=vlFEGdij83GYetLrOUaCnR04sbYRvtckD5L7fw5192c=; b=F+Xk1oIKL1I2VFcAdWDIZXgwgqywOdpZOjrtpYtw31ZI+cWtWHKK6pyuScfzJHkcq2 gH0CZfy1Wzb+wWZN+2nTAIgKZZx3MAVfY8/G/og05Rg/2CWAglnh1wHSwXwEahJpLWF0 B11u2kz7o0R6meqks3f07TaTEdZ+jgtWg4IbjHq1AvClKwr9uuMfF8+FY9r5FfAUbVGw p/h57qNuNg4NtpezGQ46gDKFHjk5yS9/EI0XI7tDsLqGmq3Nd8wNANbpmYE7hfBpv2Ab /BL3iO4H/cOoUjTrvWaIVye2N5Tt/sAhTkTWnU7n2vxMwHyIeqrZ7ghuQGRPyKJ1mFjf yt5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ojx0WGqE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 12 Dec 2023 04:34:41 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, Brian Cain , Thomas Huth , Paolo Bonzini , qemu-arm@nongnu.org, Manos Pitsidianakis , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson , Warner Losh , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 05/23] gdbstub: Include missing 'hw/core/cpu.h' header Date: Tue, 12 Dec 2023 13:33:41 +0100 Message-ID: <20231212123401.37493-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212123401.37493-1-philmd@linaro.org> References: <20231212123401.37493-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=philmd@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Functions such gdb_get_cpu_pid() dereference CPUState so require the structure declaration from "hw/core/cpu.h": static uint32_t gdb_get_cpu_pid(CPUState *cpu) { ... return cpu->cluster_index + 1; } Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh --- gdbstub/gdbstub.c | 1 + 1 file changed, 1 insertion(+) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 46d752bbc2..034a4ac211 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -37,6 +37,7 @@ #include "hw/cpu/cluster.h" #include "hw/boards.h" #endif +#include "hw/core/cpu.h" #include "sysemu/hw_accel.h" #include "sysemu/runstate.h" From patchwork Tue Dec 12 12:33:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753066 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1876151wrs; Tue, 12 Dec 2023 04:37:22 -0800 (PST) X-Google-Smtp-Source: AGHT+IF4BDwBbzv/Eu8p5WYFNmdgQMC9DlqXIb0e04W135ggAqR7V4Pz9lnu7fk27kZ85OEtTsN+ X-Received: by 2002:a05:622a:4ce:b0:425:953d:1831 with SMTP id q14-20020a05622a04ce00b00425953d1831mr7769235qtx.46.1702384642144; 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Avoid including the huge "cpu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/semihosting/uaccess.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/semihosting/uaccess.h b/include/semihosting/uaccess.h index 3963eafc3e..6c8835fbcb 100644 --- a/include/semihosting/uaccess.h +++ b/include/semihosting/uaccess.h @@ -14,7 +14,7 @@ #error Cannot include semihosting/uaccess.h from user emulation #endif -#include "cpu.h" +#include "exec/cpu-defs.h" #define get_user_u64(val, addr) \ ({ uint64_t val_ = 0; \ From patchwork Tue Dec 12 12:33:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753062 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1875657wrs; Tue, 12 Dec 2023 04:36:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IG+0kMX6sgvoHMUEm8DOlXGe7H7DkaE6yyx8/4Qfai95yOb9CJ4TGA8lxeEeGL7mHxHW1n8 X-Received: by 2002:a05:620a:2a10:b0:77e:fdc2:90a7 with SMTP id o16-20020a05620a2a1000b0077efdc290a7mr7049933qkp.91.1702384583410; Tue, 12 Dec 2023 04:36:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702384583; cv=none; d=google.com; s=arc-20160816; b=CsSVkhw2fRDUyBVdETityqOgjagbPyZYr76i8iDsXzbZQQxZpYzI2Fma5fHqvhruBy hCFqXADiHmisSHKgHW8icy3xRnzSyfNFRxGg5kb5fsVcf/JkRR7klqFxoK5r5yVAolmJ 7xVNAMJFykUZTaB/zJmnznR7ibX0pTe3rOq8DOi5DhrY+qlFs3ZslqbOnZ0jl8h5u859 8K58Y7r5dNzd6nqu6/MkbVmYWkUdRRUfp8acbriaSClNryKn16cam+gaig46jAy7YKAR 3PhWma1mM/QV3mVqM9Vje8IvAxXyQEUtpE5SyaWw1QpiqqC3dCW4/rKikXWEGFd0jjol 3wLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/FjRv+vnD4PJf/d4rT729kMYrO2SSxTsxM5m/jedirA=; fh=vlFEGdij83GYetLrOUaCnR04sbYRvtckD5L7fw5192c=; b=DO2ucmOm413fXIcfR2SbziRH1moPKdM78avTt7jHcp67Zi5FnhZv7nIRQSiUNgn7MN BV+Nu3WF97yw+LnztYKuF9JMvtuw335PO998jmIWvZyGMn6GW6mH3xSVc/uWjayf3v8J o4FiWL6IRXmjWivZknCsQCJhIBebUUR65YabTPgqDpxCczS/FJK2ZCxN7OaTQQCf81La IDwM+apanpfSihLEZ5obpJiaq5T6ufrP3oZMG4Kl6hV5IaLWR/t072NOz8yZ0TIY17qr /dnKb1wgqBXvZ90bHId/r1fVgqoMu5L9d882O3NEKku/+UMj3RAqIqa1mmGxY+Wpro0v +ifg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="onBrAB/Z"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q26-20020a05620a039a00b0077437335298si9869768qkm.765.2023.12.12.04.36.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Dec 2023 04:36:23 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="onBrAB/Z"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rD1yb-000871-33; Tue, 12 Dec 2023 07:35:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rD1yV-00082t-J8 for qemu-devel@nongnu.org; Tue, 12 Dec 2023 07:35:01 -0500 Received: from mail-lj1-x229.google.com ([2a00:1450:4864:20::229]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rD1yT-0006mY-BI for qemu-devel@nongnu.org; Tue, 12 Dec 2023 07:34:58 -0500 Received: by mail-lj1-x229.google.com with SMTP id 38308e7fff4ca-2ca09601127so75167691fa.1 for ; Tue, 12 Dec 2023 04:34:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702384495; x=1702989295; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/FjRv+vnD4PJf/d4rT729kMYrO2SSxTsxM5m/jedirA=; b=onBrAB/ZaIb3ARiQhlOWwn2lH3QcQ8yMBCnmlSn0eUoxt6naqapSRhl4FqxMFuVY9P ZiAbVKlUX8xPa8AIFB7WWTAggHWG/lRXA8iZaPqicxNG+g7FH0kV+FEwSs0mKz2xzGRC UhRrdf2e0azr94sHFNyiBMZVnyEMT1sicrxaRDETNSikdBOq9UVf4jI4WYM6+f7r4e3w sDZKxuLCueUI48kbBk5zWFakTzE+gE/3khADzJPbi3hTltJnWAWA6ilxyZRo99hveCfW anc002/M2bCqDY28gj2s2qIHTVOGEK6AET02ppoOrCp/3/YTox9XKHAgdHgL5jRHNPl7 GXVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702384495; x=1702989295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/FjRv+vnD4PJf/d4rT729kMYrO2SSxTsxM5m/jedirA=; b=GTariVnGsF55tR76Inwix9IX1/Y0VrocGKJsZv+CaeeEckEjHcE3C9AabbQSKxEeik 47KUy8FaGOfCraEB7N21B6/KTLYLCszXXNuwI5EiOl7beKJSkWxAkhr6FxustwlGKhLl pk2kni8EJ7NETdSyNkwjs7JrwlEgg/wNmZ2iAw090gOIRRQn/uUaZeDfDS3dcushgaiU 4yD4AZw2ufplrAkN2TE8NST6+M2XrMDg6R9JowXLiPMMIeruqTwD5cilNujo2zaNBrSc cqvpQyX2rv9nI0mYUaNTELJOOx83ULHXWkIAjNxIAQ7SLRiOdLIfQCZ2YJYY1Nfd2BAT t35g== X-Gm-Message-State: AOJu0Yy7qKjJ3bGbDG1P/WANJtS/I8BvOV1wBk4eGqp4FXQWVwqLsFMA qE7E4+NcKERk/D1Zi6gJHnR2C0Vr9XObcPTDj4YESA== X-Received: by 2002:a2e:870e:0:b0:2ca:23e6:7373 with SMTP id m14-20020a2e870e000000b002ca23e67373mr2252314lji.90.1702384495204; Tue, 12 Dec 2023 04:34:55 -0800 (PST) Received: from m1x-phil.lan ([176.176.175.193]) by smtp.gmail.com with ESMTPSA id bt13-20020a0564020a4d00b00551d6d51401sm42198edb.53.2023.12.12.04.34.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 12 Dec 2023 04:34:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, Brian Cain , Thomas Huth , Paolo Bonzini , qemu-arm@nongnu.org, Manos Pitsidianakis , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson , Warner Losh , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 07/23] semihosting/guestfd: Remove unused 'semihosting/uaccess.h' header Date: Tue, 12 Dec 2023 13:33:43 +0100 Message-ID: <20231212123401.37493-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212123401.37493-1-philmd@linaro.org> References: <20231212123401.37493-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=philmd@linaro.org; helo=mail-lj1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Nothing in guestfd.c requires "semihosting/uaccess.h" nor "qemu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson --- semihosting/guestfd.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/semihosting/guestfd.c b/semihosting/guestfd.c index 955c2efbd0..d3241434c5 100644 --- a/semihosting/guestfd.c +++ b/semihosting/guestfd.c @@ -12,10 +12,7 @@ #include "gdbstub/syscalls.h" #include "semihosting/semihost.h" #include "semihosting/guestfd.h" -#ifdef CONFIG_USER_ONLY -#include "qemu.h" -#else -#include "semihosting/uaccess.h" +#ifndef CONFIG_USER_ONLY #include CONFIG_DEVICES #endif From patchwork Tue Dec 12 12:33:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753067 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1876312wrs; Tue, 12 Dec 2023 04:37:43 -0800 (PST) X-Google-Smtp-Source: AGHT+IH8HoLmaKCXDY0THVGNd2reh2jgd+rqmv+T9cg4se6y5UzhytuNhsS7oP7/tgJAKkJEumTB X-Received: by 2002:ac8:5dca:0:b0:425:a834:d073 with SMTP id e10-20020ac85dca000000b00425a834d073mr8372907qtx.102.1702384662830; Tue, 12 Dec 2023 04:37:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702384662; cv=none; d=google.com; s=arc-20160816; b=QhnoGEAlYmify1r7WNovnFkU6SkHl8WtuXLIVoHWfqb/ZvUBLbV+F2y5+3x9mc1ng/ 4imf7eqKeLGo7sYmOYZBWgkXekbexIrv8q8BQAOtbEDbRCVi8d7lV0k/H9nesgQjxGgv 4itC9zyfEXhBxxWZZGfKhcdA7xt6ZictA/q0Vax9JWwTzFJpzrG0kJum0nFEEvhu4Xy0 fU9hk8RHa4ZDcCUbcfe5V8Tn+4pYtadDN8cIrZOzXp+ivsjn2RdjT+fAwO3SDTXcvt0a dPLnEHHjjbDstEWNvtfPVmsXOcnEy9t4CE438hVRqJBGom47a1atqCMfbXVVfyuRvDod Y4RQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WbDQbeYc3MqbJhEQi67twemcgBt5US82mKEOXjqMt3c=; fh=vlFEGdij83GYetLrOUaCnR04sbYRvtckD5L7fw5192c=; b=i8asHjGzTfr/xQgPTRbA3ww0LuukG0fsRzFMf7EovQ8NNwosAYelcWw1S8jQzuzt5J P05WsHmfda3RDlfS/NAa4ZmcZDQOPFONbUP1L6kC8jvCtL0N/R2LIY3zmKrouPNMIVES Efj3EzBMGAqh60R/7ctRWOCsE1yZcldcorlublLPsqQhnxRr9L6knaq7D6UTTNZkGUE3 uaTsaC2Y4gVsg6ajBJm8n+N9aflPgzumcUJtDt2macYwGfjOIAUxgqtwm9L+L4wtMvrl C0+kz2P660DJKsIykCIuOuIcO9c7HOJgKFg0LSinaZDC+cjeOgO0nMVnIrdx30Ik1tmg 0z7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LCWjlppo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 12 Dec 2023 04:35:01 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, Brian Cain , Thomas Huth , Paolo Bonzini , qemu-arm@nongnu.org, Manos Pitsidianakis , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson , Warner Losh , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 08/23] host/load-extract: Include missing 'qemu/atomic.h' and 'qemu/int128.h' Date: Tue, 12 Dec 2023 13:33:44 +0100 Message-ID: <20231212123401.37493-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212123401.37493-1-philmd@linaro.org> References: <20231212123401.37493-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org int128_make128(), int128_getlo() and int128_urshift() are declared in "qemu/int128.h". qatomic_read__nocheck() is declared in "qemu/atomic.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson --- host/include/generic/host/load-extract-al16-al8.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/host/include/generic/host/load-extract-al16-al8.h b/host/include/generic/host/load-extract-al16-al8.h index d95556130f..6b47339b57 100644 --- a/host/include/generic/host/load-extract-al16-al8.h +++ b/host/include/generic/host/load-extract-al16-al8.h @@ -8,6 +8,9 @@ #ifndef HOST_LOAD_EXTRACT_AL16_AL8_H #define HOST_LOAD_EXTRACT_AL16_AL8_H +#include "qemu/atomic.h" +#include "qemu/int128.h" + /** * load_atom_extract_al16_or_al8: * @pv: host address From patchwork Tue Dec 12 12:33:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753061 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1875574wrs; Tue, 12 Dec 2023 04:36:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IEwZij7LJtARBYsCI0GQ8XKg1+hWoETwa3Jj0zmhLjs3moizIyixf7zM06dS88AVu5bIh+K X-Received: by 2002:a0c:d60a:0:b0:67a:9b28:118e with SMTP id c10-20020a0cd60a000000b0067a9b28118emr5330734qvj.55.1702384572155; Tue, 12 Dec 2023 04:36:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702384572; cv=none; d=google.com; s=arc-20160816; b=U4aEMq8r8CCXwNHheEb5Xy54PeB5zDmW1M7JyoM8NaAWQzuAleNRbtYy9f6+t73G5J NF6LFmo/gwWDAidFNctiforxnLDG5L1jp/qdcJ8WEx0OwVjUyzDEijzs0HZjvtnBP6CZ LcnM9yLlJ4ku/yqS8yc+yZJkTIzoZCor8rxppacqsSszGzTi30kANNBphGPSJyTfXVNK ocDuq6vOoiAtFZ3wb0ymMRa9MV/0Q3AeHkDjNRXiT4cz/gPL6V0cVS9nNQvqbizTLSfZ NBSQYDcoq+Y8xtwi9L8mJvgyElRCZpXNlFGGJvQWk+/lL7viFJWk8Bl2K8XmbM1/WV5E YMug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bTgCkgY7q586A21zu0JSDs5UTTpVyxNoAlIlHHAmSdk=; fh=vlFEGdij83GYetLrOUaCnR04sbYRvtckD5L7fw5192c=; b=psU9uyk7PG9n3Nwx/vjQre+v8ALTQvp2Y43coXNSQ9a6h3t1HO9HgmUNLtDx2yaAvu xqpDWrN1grI7weimRRmR+oMFuCrDch8d83+cxM5Co1xyCUDuVtZ7qk05tZlCEPCFu2oj 81gE1UqNtySCPilZoOYrDO/dIys8dkWwdPVn5EVz6H0JfTXM2fipF0r+bpYsdvo0P6Zl T61Nf2rjre7p4fYWCIMvqIrE/q79kiyQO+tjs1h+4y1Aw+mp9HenKScPxuc3y+pP0Kel w6j41umhVAebJXkoYEXA1VCnb/RPjNmrO2RElx+XJHS18EcQbZDcwapZHbG7o7rNYL58 Tqzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zwHbRq2a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id pe19-20020a056214495300b0067a1d0732b5si8876900qvb.190.2023.12.12.04.36.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Dec 2023 04:36:12 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zwHbRq2a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rD1yp-0008J9-1o; Tue, 12 Dec 2023 07:35:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rD1yk-0008GI-2k for qemu-devel@nongnu.org; Tue, 12 Dec 2023 07:35:15 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rD1yh-0006q7-3A for qemu-devel@nongnu.org; Tue, 12 Dec 2023 07:35:13 -0500 Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-a22eba5a290so61159566b.3 for ; Tue, 12 Dec 2023 04:35:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702384508; x=1702989308; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bTgCkgY7q586A21zu0JSDs5UTTpVyxNoAlIlHHAmSdk=; b=zwHbRq2awpGt5JlyY4dKfQyVMATxJjwGo5yHedO62OqPLt1NnnPFBpuY3utoy8ts7m FoL1xP+8BS2vEd2RxtLiGLaYbfK0I4meFcOY7wy8L5CTyxXEa54wnn62SujcXNthYIz7 XYaaq9GLC//gVVzAA9SCfdXfUACS/vOiFXjdOLW3qzMzJM7hQr673DP1dgsB2jevmsl1 Qb0sYw11KV8XVOwMuQ/5mEaxtProPlnZEMC50+GwfpYJV+b84UMqQ/yzEbEgQ0mxWlOe iMyLiz9t9MjiwRmIf+FjsOSm3W+qbpmuqKnXFLzYrAW88t2S/mKN7eSc3Rh7qZavKk6u mARQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702384508; x=1702989308; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bTgCkgY7q586A21zu0JSDs5UTTpVyxNoAlIlHHAmSdk=; b=Bw3hXN5lgHBrhXW3PCBq48CQZOApZ1+59F7Y0+UFvIbrQCBQy5vJzNUk2QJqEGNYVN vhpXd7eM3dkoPmYDzmy1zDDqkLpbnxadQTl8t1Iv8CCGnWyohZceAiRlN9D6sVuwW0u/ viX8kNrsR99Aa6hhf/nkoimoS6yDzypQv0x3NN6p+xf+iK5zCJE9K5z+TJ2iX7MwXUQQ nOTAf4p8O1AevXhiyac4oXU0OTGvewxfhEX+8/8B+WmCwKnfI/0Iev8ks3lGvJPIV6Bi ucylhOm+ma+O/SkLQRQPobbRz2+AU6kWy0MbPUzcsw9W9MwDzUENDFvLekwparhyiUm9 Z5aQ== X-Gm-Message-State: AOJu0Yw15ucyIvNz6fYwqakQlA6x27Qm9Y09+x6q2O/6ciYOCl9kvhTn 3lnr22cDXzgyV5LrbydK1kgIFHXfmyMQBr2+MKmUog== X-Received: by 2002:a17:906:51ca:b0:a19:a19b:55db with SMTP id v10-20020a17090651ca00b00a19a19b55dbmr2697065ejk.107.1702384508710; Tue, 12 Dec 2023 04:35:08 -0800 (PST) Received: from m1x-phil.lan ([176.176.175.193]) by smtp.gmail.com with ESMTPSA id wb8-20020a170907d50800b00a1cb351dd4fsm6233385ejc.9.2023.12.12.04.35.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 12 Dec 2023 04:35:08 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, Brian Cain , Thomas Huth , Paolo Bonzini , qemu-arm@nongnu.org, Manos Pitsidianakis , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson , Warner Losh , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 09/23] host/atomic128: Include missing 'qemu/atomic.h' header Date: Tue, 12 Dec 2023 13:33:45 +0100 Message-ID: <20231212123401.37493-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212123401.37493-1-philmd@linaro.org> References: <20231212123401.37493-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org qatomic_cmpxchg__nocheck(), qatomic_read__nocheck(), qatomic_set__nocheck() are defined in "qemu/atomic.h". Include it in order to avoid: In file included from include/exec/helper-proto.h:10: In file included from include/exec/helper-proto-common.h:10: In file included from include/qemu/atomic128.h:61: In file included from host/include/aarch64/host/atomic128-cas.h:16: host/include/generic/host/atomic128-cas.h:23:11: error: call to undeclared function 'qatomic_cmpxchg__nocheck'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] r.i = qatomic_cmpxchg__nocheck(ptr_align, c.i, n.i); ^ Signed-off-by: Philippe Mathieu-Daudé --- host/include/generic/host/atomic128-cas.h | 2 ++ host/include/generic/host/atomic128-ldst.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/host/include/generic/host/atomic128-cas.h b/host/include/generic/host/atomic128-cas.h index 6b40cc2271..4824f14659 100644 --- a/host/include/generic/host/atomic128-cas.h +++ b/host/include/generic/host/atomic128-cas.h @@ -11,6 +11,8 @@ #ifndef HOST_ATOMIC128_CAS_H #define HOST_ATOMIC128_CAS_H +#include "qemu/atomic.h" + #if defined(CONFIG_ATOMIC128) static inline Int128 ATTRIBUTE_ATOMIC128_OPT atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) diff --git a/host/include/generic/host/atomic128-ldst.h b/host/include/generic/host/atomic128-ldst.h index 691e6a8531..12e4aca2da 100644 --- a/host/include/generic/host/atomic128-ldst.h +++ b/host/include/generic/host/atomic128-ldst.h @@ -11,6 +11,8 @@ #ifndef HOST_ATOMIC128_LDST_H #define HOST_ATOMIC128_LDST_H +#include "qemu/atomic.h" + #if defined(CONFIG_ATOMIC128) # define HAVE_ATOMIC128_RO 1 # define HAVE_ATOMIC128_RW 1 From patchwork Tue Dec 12 12:33:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753073 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1876677wrs; Tue, 12 Dec 2023 04:38:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IHkKy+fwvmymczt7LKYsVEKGEYjGoVq/rjPz2JRa1GD/poIxxSsc/Asvp6ccV4hb7Yy75tV X-Received: by 2002:ac8:5790:0:b0:425:4042:f447 with SMTP id v16-20020ac85790000000b004254042f447mr8614390qta.43.1702384705099; Tue, 12 Dec 2023 04:38:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702384705; cv=none; d=google.com; s=arc-20160816; b=EWcbNwwqsX/NpWjcGzma8fu4UhepjunbVTqyREb615BCcDXBn298yY0iIMdQ18eMxs TCHIlJUA4dg3FQqnpVBKrjCIM6WY6B/k0RePaNf1EKzOn7m1WDCdqve2VhFap2DhzKjl PFpht5IfZEJ4FdT7mSmK/gMfzadEM9UpxgJnYeJvNDavp+UFIFI+1/VhEEQvOEP+SqdF 6wploI0kk9SHlBMN/GQ69S/NWpmzYFtGCQqHaO3nFg7XOd1tmL9tvpZj7uBJV1EBy/Vp NjB37iQxjxfNuMHEPYwk2/wdR9ptY2MPO9EWqNJ54QmNpg/wMVfSkTYyrcu+O+4wAGiD w6Gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=my60g7IAHtC+Xh4NyAr8rtLaKcoTnKLvvJwkWl2gbFo=; fh=uaeyFMM36sIsZb6AkIqDR1BECOcykgmj+fGmoTV95c4=; b=saO78NUV/+pOwqYIAUDmYBnke54MQDybvI2cUhljFPbPx6plUDcW4JGnjwJ5B854gr DZD0JpQVUdmpFiwcA4ccHQaib0Vs4f/Umu2hIFk+GnqWFRYXoz3vP1XzGA5LB5F6AycO GVHiakP3p1hQw2PFOPxIXrX+OiuzSz3aAm3XKJvk/edg/jKnKHp/+xayVjJ5F5wMNR1n tIJNiZRmW8KNjMPKUEPVk/pJXhrL7KwaoNbJlv0bY9E5yFFH3WmJKGC9lHv9qgmd3ZXf 6/Ip4216/IyVnoQbbDw5Nb6OYtOpJ4eJAJKgtDykifGEgKqJMWHUh5W14FSns+rJJijU iFRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="V5UI/R/l"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/i386/tcg/fpu_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 4430d3d380..3bb018fbae 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -21,6 +21,7 @@ #include #include "cpu.h" #include "tcg-cpu.h" +#include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" From patchwork Tue Dec 12 12:33:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753075 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1876763wrs; Tue, 12 Dec 2023 04:38:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IFzYD194JeATVX9nqMCt+tYnGfiYf2MqfWJRpk77jMLwfmgDxw/p4ghfIr6uPW9AzHYfmnS X-Received: by 2002:a05:622a:1708:b0:41e:1d15:69a6 with SMTP id h8-20020a05622a170800b0041e1d1569a6mr10255672qtk.31.1702384715140; Tue, 12 Dec 2023 04:38:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702384715; cv=none; d=google.com; s=arc-20160816; b=KxXSs7O9wte8RaAS7rFywy9ruS1jhUWgkKH57/RHS50aV8Ajf2jOFPiMHKJvZ8erwv bSF31B9/KeOI5q/lbudH+gAJmtyCEcpv6KDYiqgGuPkNpUkXyZbEVsmiNQ7LHnf6UCYQ uZEtdpIur3BAr26y8WMYin+hBLwVt/TCX8/426cIQx0XTMD3Ub4lUMCh5cZG6pipi6B7 ZKgRGwxO+FxW3i6ta9AIHLBd3jTJcsSXufLaty61sJO6pm1Rp2QJzElia9z2FkEYa+Ow z3jJA9oCSvgGStPkJOjt/XIHwARKGubw4l4jsMOqPqbR7SRJPuNCtlv8C7PI0f31K7kt p8SA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Sxk2B1Wo2pXRo42/SYBVVIycoetyzxarj96J9gTlCqc=; fh=vlFEGdij83GYetLrOUaCnR04sbYRvtckD5L7fw5192c=; b=gCYSli660DIx1V5jnHtWKstCkLfLjn/Ay24MirkiOPGNbpMOHlvTI7gjQ72W8QzFS/ n1XkIud3f37XRGJ9vc7XVXUO6WIacIhxPjjiQzBEEj/MT46oES7Jviy2QlgL/lnjpj+5 UNc1djaSRErQaGd9QIMejNXopTkQJndZeJx46tLp+J+wz8XamqxCqOn9bXy8TeBktV8D OFWUQh3hI4rvV+6nQx8j82w/TenfEN5CU77d6BMZRNm0GdZXuRCFjee5LBsr0tzpX7lH 1XNo9+7xLtRzkNDWRSNiluxAGmrEJy2FnKXbFQol6HANBo4ZOSK8Aq616sRnvN4AuaQg 3Smw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=V2bpmBkd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson --- accel/tcg/tcg-accel-ops.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 1b57290682..58806e2d7f 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -37,6 +37,8 @@ #include "exec/tb-flush.h" #include "exec/gdbstub.h" +#include "hw/core/cpu.h" + #include "tcg-accel-ops.h" #include "tcg-accel-ops-mttcg.h" #include "tcg-accel-ops-rr.h" From patchwork Tue Dec 12 12:33:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753063 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1875734wrs; Tue, 12 Dec 2023 04:36:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IHJ4o1Q/uP9B3fhpu2sOVIuOnHP/Ketdpg3byG3RPh3GTvX6AoPewjLbniA0ak5dyT+xMxt X-Received: by 2002:a05:6808:38c3:b0:3ba:5dd:9457 with SMTP id el3-20020a05680838c300b003ba05dd9457mr6253549oib.38.1702384593949; Tue, 12 Dec 2023 04:36:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702384593; cv=none; d=google.com; s=arc-20160816; b=h2s2yxL5VTyO/eEMER7q6vJUMfNgPByZnWR54ZzYGDRD+h+lerpzMREnXlLS0XSazk tEBAxrXN42h0vwQbQ8LCqf4gt+bJ6Ubpx7S6j4HivjVYoWKRiJTUoLGkx5v92lYnWgEX 5vXIB74d++cijEmvcwC7YZsFcN3prJKrPnJI+yrJv+U5RIVwl1BcvS7cM12AfvC3Y9HG dIAJKH8mSddw02kZWjZ24jzA/6OObieSFkWSzDuwqud1gRu76wB4SlnGNZGZWM1xGraX S81cypQOrfnxXB0VeCzW1/+5m+o66LJx0TIvGvXovyFjKz4H8d+djKqWBJfQigSq6C2d tasg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PWTWSX0YuZXSOblIfpck8oXRK7z4+HrveIQtpqWVbLc=; fh=vlFEGdij83GYetLrOUaCnR04sbYRvtckD5L7fw5192c=; b=Lcbb7dlK3revwhjxSPMq17EG0b9RDtqEN4wlxb6oTZYlzZ3gshhJXdTZC8XlhKyZ6Y hwZbd2eKMxLE+JFH9bdDR5wdtQdYLuyFi60A7YlhKVsKVkY3l1WU6miMEBX8IzCCDSRW JqjjVE8PG2ONEB9lGpQpcvt9H2zqbvfSWAFx7evlcINAOBWDuWB2ELC6cvFhOKI2fJw4 hwOu4Fnehf6xJT7z4+kmtsiz3nNQ2xmIPi8IAE0V6R2F+f9oWq0jTomuBfP1k0Q6D4U+ PTiSY2CoWl/jb1OOsngDjnory54Z/bPfWGvIcDOHZ+wNSMPAw5xHbp12Zbwot2f4Cpz8 76YQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R4mMcVNa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson --- include/exec/cpu-all.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 9a7b5737d3..26b44ca125 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -22,7 +22,6 @@ #include "exec/cpu-common.h" #include "exec/memory.h" #include "exec/tswap.h" -#include "qemu/thread.h" #include "hw/core/cpu.h" #include "qemu/rcu.h" From patchwork Tue Dec 12 12:33:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753077 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1877047wrs; Tue, 12 Dec 2023 04:39:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IHVqlW0OMXg5heL88SrPPym49UFPbjQya9zcuHwmgFQcLI1awg+4ZPnM6oybKhu+lEh+mHS X-Received: by 2002:a05:620a:a45:b0:77d:cb4b:bda with SMTP id j5-20020a05620a0a4500b0077dcb4b0bdamr7551442qka.9.1702384746792; Tue, 12 Dec 2023 04:39:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702384746; cv=none; d=google.com; s=arc-20160816; b=XW+l5BF8yZfvRZuR6HaOcf1nR4qHkIRmxIDMLTPbXNpG8nM9oBb5Haht7LPjrcoyUx i67nuE58rLozCoTPuh/oA5fS1Nlz6VhJIhGjJtiNZ6TU/IxoBoAKNPTw5IE391h5m8MW N+AzJifDN2lvNbEW9G4AhV5dRg5YZurWgPXZEkJXl9NdWKsU3mbkTsiLOJdcDaJS2LUX ZE662lWGl/R1d97kFCRjhpEVaSwkkLhcueGiHsvyrsHW6MtYm+7E5RHYMvlXuzGHLssG jgaptNWCDMYPeHim7gdccKfaeAbN52XpdiM/UK8x80suI91X2ethCaFK+Z6pdMrVMwuW TK1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/12RdsXJD+64tXWZALzavaBTbOyfNyTOEXXMF3szcR4=; fh=LO/BsHhviOYxE+eStnDDVVmSnBBAHvhaoSI4fAkKvrk=; b=n7e8UwOy0b9QsB9+/MePpMVaeSr+nUaidWHXtJYV4s1RgO3dfklKcJ1pfbAS+8SuHG mHSnLRWaMrgp5jKEE3FolmHG+OQj+s67IijI7/p2GooQFeUlEjRZsmlxxYKnGOLFNzKd neBvj3m5kt72QnQJ7cfw7FeK5MVO9nhR/TJJhjOsuNlChA3Rnxov1oyG6IFcRAYJObW9 0DpeqbAr7JXgA/iXT2sw8hdRGADXg3EWbwhXNL8ac2ehV+Nzlx9R1h7yQTaZzHCX4F72 oTFg+rhGd5QAhqeURqgYn/F9c1mrr0lRo1qu30wprH8BdULL6eXO6v6GTTsznf2fB+Xo adsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XXO2y1Q1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t21-20020a05620a451500b0077573396927si11408970qkp.260.2023.12.12.04.39.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Dec 2023 04:39:06 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XXO2y1Q1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rD1zj-0001mx-89; Tue, 12 Dec 2023 07:36:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rD1zQ-0001a4-Gu for qemu-devel@nongnu.org; Tue, 12 Dec 2023 07:36:00 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rD1z9-0007b8-My for qemu-devel@nongnu.org; Tue, 12 Dec 2023 07:35:56 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-40c3ceded81so31018875e9.1 for ; Tue, 12 Dec 2023 04:35:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702384537; x=1702989337; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/12RdsXJD+64tXWZALzavaBTbOyfNyTOEXXMF3szcR4=; b=XXO2y1Q1sTv5RhnlMJ1ucgtmOio7rX34/sMkUnpiYJHKDfPIddWW2t8nmAlY8WfLIg /aK8Jkv0VnGBGOxel+m9x6wP/21sDli7p5NOEQBArDK32Hd6VE1TcmTDMC5QuDWRH5Ha 9nPUteGz6OpDcnhm2oI3/ySQALgKYX9OQBoKePf8653KJEjr6lL4ApqRFlhaueIenkh2 7dZzMkBpQlr272OzEfYIHAGNV/nz729fAJXMIou7U0+KDbpCWjCP+hOVRnHX4ZNj5v5m OADuUkS1SVy34w5hTtAAedhpeNSdyIP+bx6R5gnJMl5PgxUMLHykyWPS25I0OB2fS4Xq qz3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702384537; x=1702989337; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/12RdsXJD+64tXWZALzavaBTbOyfNyTOEXXMF3szcR4=; b=J5jeNqNcifRr3CkFh4OIO+qxGIbp8rS66xdz3FxdaJ6bYKbHydcvpHCs0vVmyj5qBV yjGU2vTdHalLi6jOxzMZCAmnVcxJKl+Oii3Ny+y+Ttv1Khab8sVEhrtsvm2L2R5/X09R FcqkjBa1542Yqpox6tw+ijJXSKGQhrLHMj378ZrvG1bj6V6WsY05A4fUHWjm2qTNaQH+ 84hHaI4ZpsMx+GEwzN/3QTqy+luwopNBg6OV81Y2PLhTEVH+Jfon8JuUgb1JOo6SrVwi bRmCSQcrNhZn448A92Wkh8pX/E0vVT4dQuP85M64v9mIn7ZrwqXHddI8ii0cbFUQK6Gc 1utg== X-Gm-Message-State: AOJu0YzQrCJhSbyIs/ncmfTxHD6bCV7JLRdsrHafpuAVKTJqTMyWWxi5 E6WASSG0lk4t/CB3PiJ9B9FwFh/FMOOxqZzrqVzRpA== X-Received: by 2002:a05:600c:1d12:b0:40c:32fe:e123 with SMTP id l18-20020a05600c1d1200b0040c32fee123mr3266787wms.167.1702384537429; Tue, 12 Dec 2023 04:35:37 -0800 (PST) Received: from m1x-phil.lan ([176.176.175.193]) by smtp.gmail.com with ESMTPSA id tb19-20020a1709078b9300b00a1cd30d06d1sm6338905ejc.14.2023.12.12.04.35.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 12 Dec 2023 04:35:36 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, Brian Cain , Thomas Huth , Paolo Bonzini , qemu-arm@nongnu.org, Manos Pitsidianakis , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson , Warner Losh , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= , Peter Xu , David Hildenbrand Subject: [PATCH v2 13/23] exec/cpu-all: Reduce 'qemu/rcu.h' header inclusion Date: Tue, 12 Dec 2023 13:33:49 +0100 Message-ID: <20231212123401.37493-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212123401.37493-1-philmd@linaro.org> References: <20231212123401.37493-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "exec/cpu-all.h" doesn't need definitions from "qemu/rcu.h", however "exec/ram_addr.h" does. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/exec/cpu-all.h | 1 - include/exec/ram_addr.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 26b44ca125..5b5379b94c 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -23,7 +23,6 @@ #include "exec/memory.h" #include "exec/tswap.h" #include "hw/core/cpu.h" -#include "qemu/rcu.h" /* some important defines: * diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index 90676093f5..aab7d6c57c 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -25,6 +25,7 @@ #include "sysemu/tcg.h" #include "exec/ramlist.h" #include "exec/ramblock.h" +#include "qemu/rcu.h" extern uint64_t total_dirty_pages; From patchwork Tue Dec 12 12:33:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753064 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1875818wrs; Tue, 12 Dec 2023 04:36:45 -0800 (PST) X-Google-Smtp-Source: AGHT+IEOto/vEULalAw5iLS8eGdfp863OwdIpYs9aNwT57k/CTZlBGEFw2h5WX90fJmqDA8Ok8cR X-Received: by 2002:a05:6214:48:b0:67a:96c7:4c90 with SMTP id c8-20020a056214004800b0067a96c74c90mr5747460qvr.38.1702384604837; Tue, 12 Dec 2023 04:36:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702384604; cv=none; d=google.com; s=arc-20160816; b=vDIASwKRyaAWU8VwKCkIfBbw/fggbQ/k/ohRv9ER4J9dFivcEwETebiHimgo/QYRjX kekwo99iNgEFMtDVv4kwFbl1O+O9fdMKBEZ9rGEqBr0ZLoWjZ798u0W4zVQSgNGcdrbz 2B8KNl2Qy2cNt4SgHTLqAk8H/OqukWvIpZT+vF0sHsC+OEo7UWkEWAhec4bBOJlWcxNk nfZ8xssD1ZnCoxq1XBw1kIAupyhjo0EBdXRYiGcLIbH7RFQ2uLUcOh565FFCjArJu8BE BgOVSXGcpjtrj848LZCvZjD2Un+gup37Pdr4W9WaQ9BpQRSh05t6S+Fg1ovnXfF+Fy+c T3MA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OWfYjgvijR4Yk7OOcPMVJ3eTtKOWWmhjXW8fnIT+sQQ=; fh=vlFEGdij83GYetLrOUaCnR04sbYRvtckD5L7fw5192c=; b=OEI18YYjnJ5M9C0jswgh6juQS6whe4ei0VfC2v/9M6G5Nvsoh78U60Uq6aOL0PycXX yaSCwvZuQbarVNjH+DB2j1ozVU7xbxWDNlYWcSrEMyXY56gKupA1uTNmykfzaesXXj8K uhgU8QMtChIOz7bzq6rPzL2IgEC+mu2ReaLn/fjVSRARqDw/YniDrnWPSsDA9ZaKQZpg QQaH9ZOnFtmny6Wfrh7DAoWYkIs0a5KfuLfEBtePsOr5ZVZD2Qa3QJOXnTZjH93rMcZK uJ/bWfK5mU6PBcsVx3Tcdyroq+z4Y/wEzx5Kg1jvyvA4d5vIrNUuXw+jXOm1wWXKUpGW dSZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NVzlCuX9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson --- include/exec/cpu-all.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 5b5379b94c..b042d94892 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -38,11 +38,9 @@ #if TARGET_LONG_SIZE == 4 #define tswapl(s) tswap32(s) -#define tswapls(s) tswap32s((uint32_t *)(s)) #define bswaptls(s) bswap32s(s) #else #define tswapl(s) tswap64(s) -#define tswapls(s) tswap64s((uint64_t *)(s)) #define bswaptls(s) bswap64s(s) #endif From patchwork Tue Dec 12 12:33:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753076 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1876992wrs; Tue, 12 Dec 2023 04:39:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IHHHdKZEpi1tOFoeh0wdDY6lm7Qivba56Wpi8hb5zn1HmY4YLO2sQb7ct57jCB7uRAmgmL1 X-Received: by 2002:a05:6808:229f:b0:3ba:57:1a0b with SMTP id bo31-20020a056808229f00b003ba00571a0bmr5307564oib.7.1702384740084; Tue, 12 Dec 2023 04:39:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702384740; cv=none; d=google.com; s=arc-20160816; b=bdrT5i04zuynzgECJX+SET5xpSRyISJ0UXG9obrM2pRPsjfjDet6BZIYcj/i1T/eWM bsd8bR3fGx+7eYyYJm+TBtIVF/7eYIP+D3/yG86CEEmZp1zjBNr3mNGAea64VeOC789K hQNIsZU1XBXxWodh/ucUp43uD8T/PGGCX9ONxkFpeXZ+VSe+BJHwe5jmgT9uf2inU3Da jaK4YaXv2ABrPgpjDBg2O5JyHoDpczltblG+VJD8Zm8oiHX0QmcumV6trxDXRVNvQDre 0+q+sJSu1mGtJHZK2hwyIKjRvPU7488LY3SvtK/Bemm7vSpHbRNqNTVUaoGnPSymW7zw YUKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LKqz8+rrRr+9OnCGqaF5kY8vCRVBvOcgtedefIMaXhg=; fh=zFh10cOfJXxh05dYupUjqn/R0oZQPEp3aMoWWRcpFb0=; b=p8VJ0OrT11OpeBUOU43U/rYVlKoor/pPUPiwvT9L8wki5vsh3MeO1l9iR9XqtxAis9 DPBTfEEjpB78PpULa3rpiBVVtwelRIpLUA44ZGYfaY6G68Xnt9m3PBMaugGTKx/qJHIs 3WydC30Abf5tvXcu/S7GS7bNsqEJ7efJ2e1x5foVTsr7GubRGackakxS2aXuW2NnR50M jMnwu5meaWaI9x2Ym3GULkqV9kDjy6iOQVHqEFYGsH39WEertK3/XGIdzaFD5HKsh+y4 Cf7Wg2LpynU9r41EmBoJOq8CEc7I+STm8WYVdmUmtJ/d6Bnly05HZqygiAAxu8B2tPBe LSYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IonMcDD8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tsirkin" , Alistair Francis , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang Subject: [PATCH v2 15/23] exec: Declare target_words_bigendian() in 'exec/tswap.h' Date: Tue, 12 Dec 2023 13:33:51 +0100 Message-ID: <20231212123401.37493-16-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212123401.37493-1-philmd@linaro.org> References: <20231212123401.37493-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=philmd@linaro.org; helo=mail-ed1-x536.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We usually check target endianess before swapping values, so target_words_bigendian() declaration makes sense in "exec/tswap.h" with the target swapping helpers. Remove "hw/core/cpu.h" when it was only included to get the target_words_bigendian() declaration. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson --- include/exec/tswap.h | 12 +++++++++++- include/hw/core/cpu.h | 11 ----------- cpu-target.c | 1 + disas/disas.c | 1 + hw/audio/virtio-snd.c | 2 +- hw/core/cpu-sysemu.c | 2 +- hw/core/generic-loader.c | 2 +- hw/display/vga.c | 2 +- hw/virtio/virtio.c | 1 + 9 files changed, 18 insertions(+), 16 deletions(-) diff --git a/include/exec/tswap.h b/include/exec/tswap.h index 68944a880b..77954bbc2b 100644 --- a/include/exec/tswap.h +++ b/include/exec/tswap.h @@ -8,9 +8,19 @@ #ifndef TSWAP_H #define TSWAP_H -#include "hw/core/cpu.h" #include "qemu/bswap.h" +/** + * target_words_bigendian: + * Returns true if the (default) endianness of the target is big endian, + * false otherwise. Note that in target-specific code, you can use + * TARGET_BIG_ENDIAN directly instead. On the other hand, common + * code should normally never need to know about the endianness of the + * target, so please do *not* use this function unless you know very well + * what you are doing! + */ +bool target_words_bigendian(void); + /* * If we're in target-specific code, we can hard-code the swapping * condition, otherwise we have to do (slower) run-time checks. diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 3208b938f7..d6b077da71 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1153,17 +1153,6 @@ bool cpu_exec_realizefn(CPUState *cpu, Error **errp); void cpu_exec_unrealizefn(CPUState *cpu); void cpu_exec_reset_hold(CPUState *cpu); -/** - * target_words_bigendian: - * Returns true if the (default) endianness of the target is big endian, - * false otherwise. Note that in target-specific code, you can use - * TARGET_BIG_ENDIAN directly instead. On the other hand, common - * code should normally never need to know about the endianness of the - * target, so please do *not* use this function unless you know very well - * what you are doing! - */ -bool target_words_bigendian(void); - const char *target_name(void); void page_size_init(void); diff --git a/cpu-target.c b/cpu-target.c index 997ca2e846..4c1e19ca81 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -33,6 +33,7 @@ #endif #include "sysemu/cpus.h" #include "sysemu/tcg.h" +#include "exec/tswap.h" #include "exec/replay-core.h" #include "exec/cpu-common.h" #include "exec/exec-all.h" diff --git a/disas/disas.c b/disas/disas.c index 0d2d06c2ec..89a1e7d767 100644 --- a/disas/disas.c +++ b/disas/disas.c @@ -6,6 +6,7 @@ #include "disas/disas.h" #include "disas/capstone.h" #include "hw/core/cpu.h" +#include "exec/tswap.h" #include "exec/memory.h" /* Filled in by elfload.c. Simplistic, but will do for now. */ diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c index 137fa77a01..a80f23aa71 100644 --- a/hw/audio/virtio-snd.c +++ b/hw/audio/virtio-snd.c @@ -20,11 +20,11 @@ #include "qemu/log.h" #include "qemu/error-report.h" #include "include/qemu/lockable.h" +#include "exec/tswap.h" #include "sysemu/runstate.h" #include "trace.h" #include "qapi/error.h" #include "hw/audio/virtio-snd.h" -#include "hw/core/cpu.h" #define VIRTIO_SOUND_VM_VERSION 1 #define VIRTIO_SOUND_JACK_DEFAULT 0 diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index d0d6a910f9..2a9a2a4eb5 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "hw/core/cpu.h" +#include "exec/tswap.h" #include "hw/core/sysemu-cpu-ops.h" bool cpu_paging_enabled(const CPUState *cpu) diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c index d4b5c501d8..ea8628b892 100644 --- a/hw/core/generic-loader.c +++ b/hw/core/generic-loader.c @@ -31,7 +31,7 @@ */ #include "qemu/osdep.h" -#include "hw/core/cpu.h" +#include "exec/tswap.h" #include "sysemu/dma.h" #include "sysemu/reset.h" #include "hw/boards.h" diff --git a/hw/display/vga.c b/hw/display/vga.c index 37557c3442..d11a30a785 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -26,7 +26,7 @@ #include "qemu/units.h" #include "sysemu/reset.h" #include "qapi/error.h" -#include "hw/core/cpu.h" +#include "exec/tswap.h" #include "hw/display/vga.h" #include "hw/i386/x86.h" #include "hw/pci/pci.h" diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index 3a160f86ed..28dc1f4c15 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -20,6 +20,7 @@ #include "qemu/log.h" #include "qemu/main-loop.h" #include "qemu/module.h" +#include "exec/tswap.h" #include "qom/object_interfaces.h" #include "hw/core/cpu.h" #include "hw/virtio/virtio.h" From patchwork Tue Dec 12 12:33:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753074 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1876685wrs; Tue, 12 Dec 2023 04:38:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IE8a5jTH/9Zm3kEVJUDAtM6u9LAAvIhWA+5WtgtHDdu/LB+W7L8Yj2jJw+NDbQNNIJXOZsx X-Received: by 2002:a05:622a:40f:b0:425:4043:50e8 with SMTP id n15-20020a05622a040f00b00425404350e8mr8390735qtx.119.1702384705685; Tue, 12 Dec 2023 04:38:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702384705; cv=none; d=google.com; s=arc-20160816; b=BfzWLnuiH3HK4uu9WeVkH/hqqkz1KuaQzehtm5h9ADTr0mV9tEz0wh3RHxLVGxSi56 0BHodYLlnR0azQGWfJEjCQIzVPeblCTYYJCiHj6FMZKacEhfZOhwj8VrEHk+xZqUA7Hy pCwdPVLUZe8hNn/ojJ5RwMK6qoAaomtpBgbF2IF0wDW+0zcAQzm4YTGPbeGy1x9mhcuj pcaR0ZnUCAIv4NcaTyTMKE3kvMyiSpYwdhG38soZbq7ns5sO8H3tsjdUpG/GrkrAp1qo D4+s0mUG/5nUeW6yYDW+4OaJGlIzKSp5xONGwL02JqXzYzHyCqb7iV1gC7iEVffOUVcZ Bhag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xslJUC3cunhRFccFUTnzrLeqNr8O79apnk92wLCDXQw=; fh=jUXvrctdLNvPTPf8EqilWtRTPbB+utYg2FT0iF33S44=; b=RY3j095HzF+xxbBHNV1acNseyiMWyFGnEP/s6FJ3Mj7piLUB6TMMjrUYZXdlsktBP/ Rjad+5Q1xAjnJfNpx2pBKFAviUmzv6FiWj0pnEIN1tiujj1wP+7isedSWnwq9j0OwMXR 67NsTTSzfePy2VX8jFMgFVttw0LlmdEGCHnVZc2Kul5kcwLCpd0dnDbb7aqo21OgN/eT /3EGvDm1Dz/SZyHC3eYcM0FFKQLQdNo1snM/RJwdhwl0nHBeWvmpaWpWyegfn6r77YcQ BL5HYT7QyqxjGPB0kpfyGei3g54Kzad2kkHH21Oi7pfC8FWfGO/FmeU9UOm5695DrvGj NgkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EN3Ao34P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id bb21-20020a05622a1b1500b004239b93e4f0si10050227qtb.784.2023.12.12.04.38.25 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Dec 2023 04:38:25 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EN3Ao34P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rD1zn-0002TU-2U; Tue, 12 Dec 2023 07:36:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rD1zg-0001w1-Mf for qemu-devel@nongnu.org; Tue, 12 Dec 2023 07:36:14 -0500 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rD1zW-0008JK-8j for qemu-devel@nongnu.org; Tue, 12 Dec 2023 07:36:07 -0500 Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-a1d2f89ddabso683060566b.1 for ; Tue, 12 Dec 2023 04:36:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702384559; x=1702989359; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xslJUC3cunhRFccFUTnzrLeqNr8O79apnk92wLCDXQw=; b=EN3Ao34P4ki+7vLzwl7xvjTvlEVfVG/ByVbjMnT71aaENKSciRJr5lgUlrVS21BbQg puQOsuOrnXig12ZwH7Ph8VJtFKzi1avHlEemsbxskngSTkbK+Bq1mq+1eCAgKnsQ6xXk 4sqPKQ2ZhHV/bjIfurE3dB8WCJEJ2roUv8MDcuR0C13HoB8R9l3oO2MDh2whofzp8J35 tQxsqEZ7kotVUFghx5VsMPFkpY0n9GPdrENnKIzWMEPD1lHq16H7wAUTV9MvqkhtzYk0 K/3iMvm0ymqxoB+bHZ+YBU9jNazTyfbx8P87od2YRFXpxW/RXiD7DbAujku8NBzoBTvu kRMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702384559; x=1702989359; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xslJUC3cunhRFccFUTnzrLeqNr8O79apnk92wLCDXQw=; b=qh1GgSKbk0F17IxMAeU0bZttHscOobfHsrwFQnmr/3J5rLleSqBhvFui4B7BC+GvBv jf3hGSTeDlQAEPWNmLgmRSWR7LquDE7BfHVI0fZxKjdjyLgKqRQBlPaYskmyArxOtchK KsATJNYYtVvqQ05xg+q6jWAurlNAR7SGGJRa4PLrgOVED3B2zv34ch6XqHkHhp9M72Xb mxlIXVpwMOqPUoDpMmyqE2ZPVsZgJiMUH3HqoPisRKcAQcU+DTbLZ1Rq37AgJDjbE/F+ f2AlTt0ghbVGwXEzV1H8WVlqxoD38pDqGrd0WrL+spV/FLXfnJnU0ykXGMJaOw21DXlI SS9g== X-Gm-Message-State: AOJu0YxsL5poWJ6seeParPy0r8DMcsaYoNyPlIeI8nVH8GietlD0LSIN Zc6UEeti2hBRClvsIOl3OUVBtvTbtKJsO17MXhv+qg== X-Received: by 2002:a17:906:35cb:b0:a1d:c75c:3d3a with SMTP id p11-20020a17090635cb00b00a1dc75c3d3amr3374408ejb.29.1702384559159; Tue, 12 Dec 2023 04:35:59 -0800 (PST) Received: from m1x-phil.lan ([176.176.175.193]) by smtp.gmail.com with ESMTPSA id ts4-20020a170907c5c400b00a1cc1be1158sm6202405ejc.165.2023.12.12.04.35.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 12 Dec 2023 04:35:58 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, Brian Cain , Thomas Huth , Paolo Bonzini , qemu-arm@nongnu.org, Manos Pitsidianakis , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson , Warner Losh , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= , Kyle Evans , Laurent Vivier Subject: [PATCH v2 16/23] exec: Move [b]tswapl() declarations to 'exec/user/tswap-target.h' Date: Tue, 12 Dec 2023 13:33:52 +0100 Message-ID: <20231212123401.37493-17-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212123401.37493-1-philmd@linaro.org> References: <20231212123401.37493-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=philmd@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org tswapl() and bswaptls() are target-dependent and only used by user emulation. Move their definitions to a new header: "exec/user/tswap-target.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson --- bsd-user/freebsd/target_os_elf.h | 1 + bsd-user/freebsd/target_os_stack.h | 1 + bsd-user/netbsd/target_os_elf.h | 1 + bsd-user/openbsd/target_os_elf.h | 1 + include/exec/cpu-all.h | 8 -------- include/exec/user/abitypes.h | 1 + include/exec/user/tswap-target.h | 22 ++++++++++++++++++++++ bsd-user/signal.c | 1 + bsd-user/strace.c | 1 + linux-user/elfload.c | 1 + linux-user/i386/signal.c | 1 + linux-user/ppc/signal.c | 1 + 12 files changed, 32 insertions(+), 8 deletions(-) create mode 100644 include/exec/user/tswap-target.h diff --git a/bsd-user/freebsd/target_os_elf.h b/bsd-user/freebsd/target_os_elf.h index 9df17d56d8..27d8ce036c 100644 --- a/bsd-user/freebsd/target_os_elf.h +++ b/bsd-user/freebsd/target_os_elf.h @@ -22,6 +22,7 @@ #include "target_arch_elf.h" #include "elf.h" +#include "exec/user/tswap-target.h" #define bsd_get_ncpu() 1 /* until we pull in bsd-proc.[hc] */ diff --git a/bsd-user/freebsd/target_os_stack.h b/bsd-user/freebsd/target_os_stack.h index d15fc3263f..6125208182 100644 --- a/bsd-user/freebsd/target_os_stack.h +++ b/bsd-user/freebsd/target_os_stack.h @@ -23,6 +23,7 @@ #include #include "target_arch_sigtramp.h" #include "qemu/guest-random.h" +#include "exec/user/tswap-target.h" /* * The initial FreeBSD stack is as follows: diff --git a/bsd-user/netbsd/target_os_elf.h b/bsd-user/netbsd/target_os_elf.h index 2f3cb20871..23b422bfce 100644 --- a/bsd-user/netbsd/target_os_elf.h +++ b/bsd-user/netbsd/target_os_elf.h @@ -22,6 +22,7 @@ #include "target_arch_elf.h" #include "elf.h" +#include "exec/user/tswap-target.h" /* this flag is uneffective under linux too, should be deleted */ #ifndef MAP_DENYWRITE diff --git a/bsd-user/openbsd/target_os_elf.h b/bsd-user/openbsd/target_os_elf.h index 6dca9c5a85..fc1dfa2e49 100644 --- a/bsd-user/openbsd/target_os_elf.h +++ b/bsd-user/openbsd/target_os_elf.h @@ -22,6 +22,7 @@ #include "target_arch_elf.h" #include "elf.h" +#include "exec/user/tswap-target.h" /* this flag is uneffective under linux too, should be deleted */ #ifndef MAP_DENYWRITE diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index b042d94892..95af418920 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -36,14 +36,6 @@ #define BSWAP_NEEDED #endif -#if TARGET_LONG_SIZE == 4 -#define tswapl(s) tswap32(s) -#define bswaptls(s) bswap32s(s) -#else -#define tswapl(s) tswap64(s) -#define bswaptls(s) bswap64s(s) -#endif - /* Target-endianness CPU memory access functions. These fit into the * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h. */ diff --git a/include/exec/user/abitypes.h b/include/exec/user/abitypes.h index 6178453d94..ed10d5fe7e 100644 --- a/include/exec/user/abitypes.h +++ b/include/exec/user/abitypes.h @@ -2,6 +2,7 @@ #define EXEC_USER_ABITYPES_H #include "cpu.h" +#include "exec/user/tswap-target.h" #ifdef TARGET_ABI32 #define TARGET_ABI_BITS 32 diff --git a/include/exec/user/tswap-target.h b/include/exec/user/tswap-target.h new file mode 100644 index 0000000000..ff302436fe --- /dev/null +++ b/include/exec/user/tswap-target.h @@ -0,0 +1,22 @@ +/* + * target-specific swap() definitions + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#ifndef EXEC_USER_TSWAP_H +#define EXEC_USER_TSWAP_H + +#include "exec/cpu-defs.h" +#include "exec/tswap.h" + +#if TARGET_LONG_SIZE == 4 +#define tswapl(s) tswap32(s) +#define bswaptls(s) bswap32s(s) +#else +#define tswapl(s) tswap64(s) +#define bswaptls(s) bswap64s(s) +#endif + +#endif diff --git a/bsd-user/signal.c b/bsd-user/signal.c index ca31470772..7b2d25230a 100644 --- a/bsd-user/signal.c +++ b/bsd-user/signal.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu.h" +#include "exec/user/tswap-target.h" #include "gdbstub/user.h" #include "signal-common.h" #include "trace.h" diff --git a/bsd-user/strace.c b/bsd-user/strace.c index 96499751eb..a1b738e63c 100644 --- a/bsd-user/strace.c +++ b/bsd-user/strace.c @@ -22,6 +22,7 @@ #include #include "qemu.h" +#include "exec/user/tswap-target.h" #include "os-strace.h" /* OS dependent strace print functions */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index cf9e74468b..debea5c355 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -6,6 +6,7 @@ #include #include "qemu.h" +#include "exec/user/tswap-target.h" #include "user-internals.h" #include "signal-common.h" #include "loader.h" diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c index bc5d45302e..eea1fa68c9 100644 --- a/linux-user/i386/signal.c +++ b/linux-user/i386/signal.c @@ -21,6 +21,7 @@ #include "user-internals.h" #include "signal-common.h" #include "linux-user/trace.h" +#include "exec/user/tswap-target.h" /* from the Linux kernel - /arch/x86/include/uapi/asm/sigcontext.h */ diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c index 7e7302823b..988b59a916 100644 --- a/linux-user/ppc/signal.c +++ b/linux-user/ppc/signal.c @@ -21,6 +21,7 @@ #include "user-internals.h" #include "signal-common.h" #include "linux-user/trace.h" +#include "exec/user/tswap-target.h" #include "vdso-asmoffset.h" /* See arch/powerpc/include/asm/ucontext.h. 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Tue, 12 Dec 2023 04:36:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, Brian Cain , Thomas Huth , Paolo Bonzini , qemu-arm@nongnu.org, Manos Pitsidianakis , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson , Warner Losh , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= , Nicholas Piggin , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= Subject: [PATCH v2 17/23] target/ppc/excp_helper: Avoid 'abi_ptr' in system emulation Date: Tue, 12 Dec 2023 13:33:53 +0100 Message-ID: <20231212123401.37493-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212123401.37493-1-philmd@linaro.org> References: <20231212123401.37493-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=philmd@linaro.org; helo=mail-lj1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org 'abi_ptr' is a user specific type. The system emulation equivalent is 'target_ulong'. Use it in ppc_ldl_code() to emphasis this is not an user emulation function. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- target/ppc/excp_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index a42743a3e0..3d7c9bbf1a 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -142,7 +142,7 @@ static inline bool insn_need_byteswap(CPUArchState *env) return !!(env->msr & ((target_ulong)1 << MSR_LE)); } -static uint32_t ppc_ldl_code(CPUArchState *env, abi_ptr addr) +static uint32_t ppc_ldl_code(CPUArchState *env, target_ulong addr) { uint32_t insn = cpu_ldl_code(env, addr); From patchwork Tue Dec 12 12:33:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753068 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1876325wrs; Tue, 12 Dec 2023 04:37:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IETBoTxSYQDI63Pq/cktTSiD1+tvXJNHu+7AqVU9DX0CRsGEgV2XpAi4rY+ZUbktevgThvW X-Received: by 2002:a05:620a:1258:b0:77f:5e41:d17d with SMTP id a24-20020a05620a125800b0077f5e41d17dmr6122720qkl.123.1702384664413; Tue, 12 Dec 2023 04:37:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702384664; cv=none; d=google.com; s=arc-20160816; b=NCxNmBom0IsOJoMfAjSBN0O4pFXJa0ucY8+GuO1RRljBgPZ5217tPpq7557De4fkCL KrF5QPBGxl0uNLJwnQqr0VZSQXwqCCrXU4Hk/Heusy6+pFRcl1EaBuOaYj6/qTxBTcO7 znlwqWdZzIPugW/pO6/8uEPZFk45Wyoho163NrM4OgXQKu3WC5HwWBUoKAPNQeXMDp5Z 0otxwcnBWPHLBFy8XUOqFxretTPLj2u+b0DWwy+4IJAI8QA+AFTTpJAWeyvs64qTfEKQ +C9eOpyBLrQ967Sk2JS65b1a0WvMXAq/ZSJx5LtSfnSswWAIeOUY05S4OluHlJXYp3WQ I5rA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=tD7bO+DUD+k+B6E3Kx/bmS2SAE12lsrmdjyahyo0DL0=; fh=uKLhH5BJN6BNufdvAUi0ctLuhmiSUl4+/kXiuO2m6Fg=; b=SHEEYxlcSAiQvnZMjS1jElkl4gaVgkPYrnBNB738cmUdVBENjHcEmZ/4GjJBI0oijr onMjKpwRrST+l0eT5mgtHKncgVhb3BfIp3NXNk1RKDXGM9kND0Vagfa2oTgWGn3UuN9o UfTpxXCpeAU1CkZlkOY8p5yIlLAwOQ2uscpIu+Qrdo1uR5qgYBEYqo01I4zMVn3uFyc+ IWhgz3KXD7a4F6QAp71DIz5bNBQdUYmM/J64rBO3gNiIiZ3yJTkRCx5vZZTMqlDNGMcG qQIDBR/rrUP0ZgcdQc5vnuicC6WZx2tKVYUUsdw96ACTnD2SC62Auyfk43qhKq64v165 8GwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IwboWPP1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 12 Dec 2023 04:36:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, Brian Cain , Thomas Huth , Paolo Bonzini , qemu-arm@nongnu.org, Manos Pitsidianakis , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson , Warner Losh , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= , Riku Voipio Subject: [PATCH v2 18/23] accel/tcg: Un-inline retaddr helpers to 'user-retaddr.h' Date: Tue, 12 Dec 2023 13:33:54 +0100 Message-ID: <20231212123401.37493-19-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212123401.37493-1-philmd@linaro.org> References: <20231212123401.37493-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=philmd@linaro.org; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org set_helper_retaddr() is only used in accel/tcg/user-exec.c. clear_helper_retaddr() is only used in accel/tcg/user-exec.c and accel/tcg/user-exec.c. No need to expose their definitions to all user-emulation files including "exec/cpu_ldst.h", move them to a new "user-retaddr.h" header (restricted to accel/tcg/). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/user-retaddr.h | 28 ++++++++++++++++++++++++++++ include/exec/cpu_ldst.h | 28 ++-------------------------- accel/tcg/cpu-exec.c | 3 +++ accel/tcg/user-exec.c | 1 + 4 files changed, 34 insertions(+), 26 deletions(-) create mode 100644 accel/tcg/user-retaddr.h diff --git a/accel/tcg/user-retaddr.h b/accel/tcg/user-retaddr.h new file mode 100644 index 0000000000..e0f57e1994 --- /dev/null +++ b/accel/tcg/user-retaddr.h @@ -0,0 +1,28 @@ +#ifndef ACCEL_TCG_USER_RETADDR_H +#define ACCEL_TCG_USER_RETADDR_H + +#include "qemu/atomic.h" + +extern __thread uintptr_t helper_retaddr; + +static inline void set_helper_retaddr(uintptr_t ra) +{ + helper_retaddr = ra; + /* + * Ensure that this write is visible to the SIGSEGV handler that + * may be invoked due to a subsequent invalid memory operation. + */ + signal_barrier(); +} + +static inline void clear_helper_retaddr(void) +{ + /* + * Ensure that previous memory operations have succeeded before + * removing the data visible to the signal handler. + */ + signal_barrier(); + helper_retaddr = 0; +} + +#endif diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 6061e33ac9..25e7239cc5 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -300,31 +300,7 @@ Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, abi_ptr addr, Int128 cmpv, Int128 newv, MemOpIdx oi, uintptr_t retaddr); -#if defined(CONFIG_USER_ONLY) - -extern __thread uintptr_t helper_retaddr; - -static inline void set_helper_retaddr(uintptr_t ra) -{ - helper_retaddr = ra; - /* - * Ensure that this write is visible to the SIGSEGV handler that - * may be invoked due to a subsequent invalid memory operation. - */ - signal_barrier(); -} - -static inline void clear_helper_retaddr(void) -{ - /* - * Ensure that previous memory operations have succeeded before - * removing the data visible to the signal handler. - */ - signal_barrier(); - helper_retaddr = 0; -} - -#else +#if !defined(CONFIG_USER_ONLY) #include "tcg/oversized-guest.h" @@ -376,7 +352,7 @@ static inline CPUTLBEntry *tlb_entry(CPUState *cpu, uintptr_t mmu_idx, return &cpu->neg.tlb.f[mmu_idx].table[tlb_index(cpu, mmu_idx, addr)]; } -#endif /* defined(CONFIG_USER_ONLY) */ +#endif /* !defined(CONFIG_USER_ONLY) */ #if TARGET_BIG_ENDIAN # define cpu_lduw_data cpu_lduw_be_data diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index c938eb96f8..e591992d0c 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -44,6 +44,9 @@ #include "tb-context.h" #include "internal-common.h" #include "internal-target.h" +#if defined(CONFIG_USER_ONLY) +#include "user-retaddr.h" +#endif /* -icount align implementation. */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 68b252cb8e..2575f0842f 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -31,6 +31,7 @@ #include "tcg/tcg-ldst.h" #include "internal-common.h" #include "internal-target.h" +#include "user-retaddr.h" __thread uintptr_t helper_retaddr; From patchwork Tue Dec 12 12:33:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753079 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1877157wrs; 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Tue, 12 Dec 2023 04:36:19 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, Brian Cain , Thomas Huth , Paolo Bonzini , qemu-arm@nongnu.org, Manos Pitsidianakis , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson , Warner Losh , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 19/23] exec/user: Do not include 'cpu.h' in 'abitypes.h' Date: Tue, 12 Dec 2023 13:33:55 +0100 Message-ID: <20231212123401.37493-20-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212123401.37493-1-philmd@linaro.org> References: <20231212123401.37493-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=philmd@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "exec/user/abitypes.h" requires: - "exec/cpu-defs.h" (TARGET_LONG_BITS) - "exec/tswap.h" (tswap32) In order to avoid "cpu.h", pick the minimum required headers. Assert this user-specific header is only included from user emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- include/exec/user/abitypes.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/exec/user/abitypes.h b/include/exec/user/abitypes.h index ed10d5fe7e..fbb55684d3 100644 --- a/include/exec/user/abitypes.h +++ b/include/exec/user/abitypes.h @@ -1,7 +1,12 @@ #ifndef EXEC_USER_ABITYPES_H #define EXEC_USER_ABITYPES_H -#include "cpu.h" +#ifndef CONFIG_USER_ONLY +#error Cannot include this header from system emulation +#endif + +#include "exec/cpu-defs.h" +#include "exec/tswap.h" #include "exec/user/tswap-target.h" #ifdef TARGET_ABI32 From patchwork Tue Dec 12 12:33:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753071 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1876611wrs; Tue, 12 Dec 2023 04:38:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IGVH1CxJteQn9V9GKr9aVK/iDEYO/g+sGvKEdYcXiYHHYIXphfxmOMh/FLXRsB40dZXyxsu X-Received: by 2002:ad4:5744:0:b0:67a:a72d:fbae with SMTP id q4-20020ad45744000000b0067aa72dfbaemr12248730qvx.44.1702384696390; Tue, 12 Dec 2023 04:38:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702384696; cv=none; d=google.com; s=arc-20160816; b=Vpg684vGEJSrX6c3UhXldD7U0DAQxSSOS4diKLAV1xRTOW9+1kgJHHZ275L7mUZ4CE xis2iYeYxijSZ3nXb1o4MWJj3igR8dP6ywHMEDL5GT5PKleDPZvphb0e2HQfAaqpUjfX enJnE5HMjEyB9mAQ1FXTGEuyMuza0j2wF+8w+K3K20kfVwyFb0Q6M0FHgwd4L6ayxT5n A6feJC+6aQptM9cCqkpuGhgONX4Tg1lZSXy28/vV7elQpm7Ynz0R7j1SeoMPCZlGgiRB ZQMF2dWL+ge5RtzJH+/oZv0gN3nP25nfWmGyl+gDoay/dPuSTtGAQzLrZVJ8irzqGVmQ WZ4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XcUJPYPixvkbPwyuTaViLgu23Dq6vUSgutR3BpOkySY=; fh=vlFEGdij83GYetLrOUaCnR04sbYRvtckD5L7fw5192c=; b=X6M0gqAzGRWhKVgfa8dLoRylCYH4vcwuNhNJWUVCtrGnP0yBMX3FVc//XeEohCQxPr LiPoYVsagTSSlewFvvjff8Op5otIvr75RAQ4jHFvoypKQWILbQOTXVHrbpI72VdiM6Fq QEav2f8Re6OJLB7PNtVdY6Z692e60yqPoF2GmdnL7PhDJ1hKf+hpsHEl7FzZPl/Z0KsJ TEt0rlGQrwKUSvSYgcL68DbJ+nWlbwU+f9qeaKen7B260LLq17khXZaog8ddjhg2JJ5k 20S+9vIUbsJgcHz9xII6oKTcCZ2iourPy2YmPixTyXA7zSirklKTi4qIm+BMjbxCAPKs evzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M6xa4qnd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Some source files requiring abi_ptr type don't need the load/store helpers. In order to simplify, create a new "exec/abi_ptr.h" header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/exec/abi_ptr.h | 33 +++++++++++++++++++++++++++++++++ include/exec/cpu_ldst.h | 17 +++-------------- include/exec/exec-all.h | 1 + include/exec/translator.h | 5 ++++- accel/tcg/cputlb.c | 1 + 5 files changed, 42 insertions(+), 15 deletions(-) create mode 100644 include/exec/abi_ptr.h diff --git a/include/exec/abi_ptr.h b/include/exec/abi_ptr.h new file mode 100644 index 0000000000..2b6ae470c4 --- /dev/null +++ b/include/exec/abi_ptr.h @@ -0,0 +1,33 @@ +/* + * QEMU abi_ptr type + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#ifndef EXEC_ABI_PTR_H +#define EXEC_ABI_PTR_H + +#include "cpu-param.h" + +#if defined(CONFIG_USER_ONLY) +/* + * sparc32plus has 64bit long but 32bit space address + * this can make bad result with g2h() and h2g() + */ +#if TARGET_VIRT_ADDR_SPACE_BITS <= 32 +typedef uint32_t abi_ptr; +#define TARGET_ABI_FMT_ptr "%x" +#else +typedef uint64_t abi_ptr; +#define TARGET_ABI_FMT_ptr "%"PRIx64 +#endif + +#else /* !CONFIG_USER_ONLY */ + +#include "exec/target_long.h" + +typedef target_ulong abi_ptr; +#define TARGET_ABI_FMT_ptr TARGET_FMT_lx + +#endif /* !CONFIG_USER_ONLY */ + +#endif diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 25e7239cc5..64e0319996 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -63,20 +63,11 @@ #define CPU_LDST_H #include "exec/memopidx.h" +#include "exec/abi_ptr.h" #include "qemu/int128.h" #include "cpu.h" #if defined(CONFIG_USER_ONLY) -/* sparc32plus has 64bit long but 32bit space address - * this can make bad result with g2h() and h2g() - */ -#if TARGET_VIRT_ADDR_SPACE_BITS <= 32 -typedef uint32_t abi_ptr; -#define TARGET_ABI_FMT_ptr "%x" -#else -typedef uint64_t abi_ptr; -#define TARGET_ABI_FMT_ptr "%"PRIx64 -#endif #ifndef TARGET_TAGGED_ADDRESSES static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x) @@ -120,10 +111,8 @@ static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong len) assert(h2g_valid(x)); \ h2g_nocheck(x); \ }) -#else -typedef target_ulong abi_ptr; -#define TARGET_ABI_FMT_ptr TARGET_FMT_lx -#endif + +#endif /* CONFIG_USER_ONLY */ uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr); int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr); diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index df3d93a2e2..5b6be2de6c 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -22,6 +22,7 @@ #include "cpu.h" #if defined(CONFIG_USER_ONLY) +#include "exec/abi_ptr.h" #include "exec/cpu_ldst.h" #endif #include "exec/translation-block.h" diff --git a/include/exec/translator.h b/include/exec/translator.h index 6d3f59d095..574058b900 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -19,7 +19,10 @@ */ #include "qemu/bswap.h" -#include "exec/cpu_ldst.h" /* for abi_ptr */ +#include "exec/cpu-common.h" +#include "exec/cpu-defs.h" +#include "exec/abi_ptr.h" +#include "cpu.h" /** * gen_intermediate_code diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index db3f93fda9..852a55fbb6 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -34,6 +34,7 @@ #include "qemu/atomic.h" #include "qemu/atomic128.h" #include "exec/translate-all.h" +#include "exec/abi_ptr.h" #include "trace.h" #include "tb-hash.h" #include "internal-common.h" From patchwork Tue Dec 12 12:33:57 2023 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id q11-20020ac8450b000000b00423ebc64ab5si9528767qtn.247.2023.12.12.04.42.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Dec 2023 04:42:19 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ThPacPTp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rD20m-0004dG-1g; Tue, 12 Dec 2023 07:37:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rD20B-0003f3-1F for qemu-devel@nongnu.org; Tue, 12 Dec 2023 07:36:45 -0500 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rD206-0000qB-FX for qemu-devel@nongnu.org; Tue, 12 Dec 2023 07:36:42 -0500 Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-a1915034144so742353966b.0 for ; Tue, 12 Dec 2023 04:36:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702384594; x=1702989394; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UFHPuaJlGIZrE/w+wBk6CARRnPU80SYEtnM2ju+CrtY=; b=ThPacPTpcNdd5Qb/M3Onu6B3EWSayIYppvhq421UAml+0njkTiCuas2ahYCFA437vO n3UuEAX6oeclRmhiAyxpCVSGgEXTmZaPuAF0wN841n6KQXEkd0wPzP0d0T7S7eDWACrc rUyUQLciXYzpeJ2zPh0Er3VwUluhZuvChyo2icGHIdVmvLNLNeX4hvbBZ7co1s1JNS65 H7umbEySev1OgxEjrrAvAPri6uS9f1RVdE0albT4CDNgCpTraJ0eLAZ/saSXbrHq6JTz fIMm39ZjIeClKz/MuO0W730eYgXXVCz5tBT397UCRwSaolyfnOqkhHQhb5M4LEwipAHx Wy4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702384594; x=1702989394; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UFHPuaJlGIZrE/w+wBk6CARRnPU80SYEtnM2ju+CrtY=; b=O22/keaD6pXtyOSFL0ELaqUMKYryWQ8QSYrVjD1jjFzZmcGW73zfT/cIHte4BJC3i+ BU7rvmKYiH8hzLYXEZk89k/VX8a44GZhJzc/7FDsh8pIVyNEzC/bE0HRodmRx6NX/rNy 2liedAEa8jgoZ8XUhRcppm7jbaHAxEGz5dkdmWIb74MK+EIZkTzlqOBizAyJq50lhgXe MGfHyirCfuY8ygYhu5Za5FU0npMR5QNloSUxuq8B6IxnUz+NnYLoj/r6H+Y68506CjMI 9f+mCxbmwtuBMYIEHSBYqnfteNh1uKHoZeA2FL2yPzu0I0QOZFWg8VQrR5PDTPC9TjXk U8cg== X-Gm-Message-State: AOJu0YxaIRhY9c/Xcy22tPH79PqPexEj7rvy+TXuduK0iVAbNdfNPGra huF8OjrgUYma3V6NgPen7oLsh+kzU7sNSE4+ccYSLw== X-Received: by 2002:a17:906:44a:b0:a1b:86e5:4e1 with SMTP id e10-20020a170906044a00b00a1b86e504e1mr3066964eja.108.1702384594559; Tue, 12 Dec 2023 04:36:34 -0800 (PST) Received: from m1x-phil.lan ([176.176.175.193]) by smtp.gmail.com with ESMTPSA id ll9-20020a170907190900b00a1cbb289a7csm6155242ejc.183.2023.12.12.04.36.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 12 Dec 2023 04:36:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, Brian Cain , Thomas Huth , Paolo Bonzini , qemu-arm@nongnu.org, Manos Pitsidianakis , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson , Warner Losh , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= , Kyle Evans , Laurent Vivier Subject: [PATCH v2 21/23] exec/cpu-all: Restrict inclusion of 'exec/user/guest-base.h' Date: Tue, 12 Dec 2023 13:33:57 +0100 Message-ID: <20231212123401.37493-22-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212123401.37493-1-philmd@linaro.org> References: <20231212123401.37493-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=philmd@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Declare 'have_guest_base' in "exec/user/guest-base.h". Very few files require this header, so explicitly include it there instead of "exec/cpu-all.h" which is used in many source files. Assert this user-specific header is only included from user emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/exec/cpu-all.h | 3 --- include/exec/cpu_ldst.h | 2 ++ include/exec/user/guest-base.h | 6 ++++++ bsd-user/main.c | 1 + linux-user/elfload.c | 1 + linux-user/main.c | 1 + 6 files changed, 11 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 95af418920..d2ddfae286 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -65,9 +65,6 @@ #if defined(CONFIG_USER_ONLY) #include "exec/user/abitypes.h" -#include "exec/user/guest-base.h" - -extern bool have_guest_base; /* * If non-zero, the guest virtual address space is a contiguous subset diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 64e0319996..e039cc7f80 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -69,6 +69,8 @@ #if defined(CONFIG_USER_ONLY) +#include "exec/user/guest-base.h" + #ifndef TARGET_TAGGED_ADDRESSES static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x) { diff --git a/include/exec/user/guest-base.h b/include/exec/user/guest-base.h index afe2ab7fbb..cf40151360 100644 --- a/include/exec/user/guest-base.h +++ b/include/exec/user/guest-base.h @@ -7,6 +7,12 @@ #ifndef EXEC_USER_GUEST_BASE_H #define EXEC_USER_GUEST_BASE_H +#ifndef CONFIG_USER_ONLY +#error Cannot include this header from system emulation +#endif + extern uintptr_t guest_base; +extern bool have_guest_base; + #endif diff --git a/bsd-user/main.c b/bsd-user/main.c index e6014f517e..c331d727e1 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -36,6 +36,7 @@ #include "qemu/help_option.h" #include "qemu/module.h" #include "exec/exec-all.h" +#include "exec/user/guest-base.h" #include "tcg/startup.h" #include "qemu/timer.h" #include "qemu/envlist.h" diff --git a/linux-user/elfload.c b/linux-user/elfload.c index debea5c355..a8c106ec0c 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -7,6 +7,7 @@ #include "qemu.h" #include "exec/user/tswap-target.h" +#include "exec/user/guest-base.h" #include "user-internals.h" #include "signal-common.h" #include "loader.h" diff --git a/linux-user/main.c b/linux-user/main.c index 0cdaf30d34..84691d707b 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -38,6 +38,7 @@ #include "qemu/help_option.h" #include "qemu/module.h" #include "qemu/plugin.h" +#include "exec/user/guest-base.h" #include "exec/exec-all.h" #include "exec/gdbstub.h" #include "gdbstub/user.h" From patchwork Tue Dec 12 12:33:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753070 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1876377wrs; Tue, 12 Dec 2023 04:37:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IHXZcMQFAeXHQUN8Ywz/cvSLtcw4YotGAm41ZKiqxDXlADaZOczQV+RlQ8hXf8L5mvXdfED X-Received: by 2002:a05:6870:a551:b0:1ff:7d4:99c9 with SMTP id p17-20020a056870a55100b001ff07d499c9mr7750266oal.91.1702384672936; Tue, 12 Dec 2023 04:37:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702384672; cv=none; d=google.com; s=arc-20160816; b=rXhGcFFqpj5Im6PAOjyjtkoNmlZXymjXtLm3manpolaT/7aksQ9zlqLwa8x6HjPi0H PRGRcQHRbgnViJvn6LrvVCX7BjDTl3e+D5REaPxkROlObJvRA5zt93DNfLVEgEGgML74 HifU1Bvdj3SGV5WoIooSNG23EtEGz3hL59RpKk8VLMX+cWAgNL2ueIPhl3D8IgQk2OUT cU+mG/Ht3aGSW1XC4SWvjp1r745HCjK3lBu82RXyLj/6phrHx/jMCe3Osmm0k3XC2Opk uGXqgMdo4MrG/aYwpc+66XTb5MiJ88ELQhR8XvmixTYlDCrfJBeyi4EZ1BV/YiOd55Tq LJUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Nc4ub95FjFsArc8viE3w6mQWwtTvnR5ELbrL08LD5PU=; fh=Fb2gqGWOlEnL5yka190kk1/GUgMfWkqQrrdfov5OnEE=; b=R2qngiJj3aOFWoBwPwxQqnpwym/gQitTE0uo5E4aipE8sOnJpx57kGElIlFxUXtNr/ BGjCmJ5arH3l/pI/FTkJTi1D+PpkN7XW9IJCP3Mel6cRoaPW3coPs6diAt3iPq/t7CcG mw1Dec8i8kSmSZmrlBLiJ8azV1sQ2v3Fee75bWCdin3P3dFExfeykgIGnW0zvznqla/e fviPXozjcCx0xrnGLd8uipIhIrAg+s5WCi4xST1Dn3diIGpzHS5EhVPsLMzJaGt0kOma KMT607fPb6tEJsex0+uODbnCgAgnLvZ5zY+uiCblvDalpBgkD34yOMNih51tcUEdDJU5 YONA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cHbEOVu+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Laurent Vivier , Peter Xu , David Hildenbrand , Peter Maydell , Michael Rolnik , Eduardo Habkost , Song Gao , Huacai Chen , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Yoshinori Sato , Ilya Leoshkevich , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov Subject: [PATCH v2 22/23] exec/cpu-all: Extract page-protection definitions to page-prot-common.h Date: Tue, 12 Dec 2023 13:33:58 +0100 Message-ID: <20231212123401.37493-23-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212123401.37493-1-philmd@linaro.org> References: <20231212123401.37493-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Extract page-protection definitions from "exec/cpu-all.h" to "exec/page-prot-common.h". The list of files requiring the new header was generated using: $ git grep -wE \ 'PAGE_(READ|WRITE|EXEC|BITS|VALID|ANON|RESERVED|TARGET_.|PASSTHROUGH)' Signed-off-by: Philippe Mathieu-Daudé --- bsd-user/bsd-mem.h | 1 + bsd-user/qemu.h | 1 + include/exec/cpu-all.h | 35 +------------------------ include/exec/page-prot-common.h | 38 ++++++++++++++++++++++++++++ include/semihosting/uaccess.h | 1 + target/arm/cpu.h | 1 + target/ppc/internal.h | 1 + target/ppc/mmu-radix64.h | 2 ++ accel/tcg/cputlb.c | 1 + accel/tcg/tb-maint.c | 1 + accel/tcg/user-exec.c | 1 + bsd-user/mmap.c | 1 + bsd-user/signal.c | 1 + cpu-target.c | 1 + hw/ppc/ppc440_bamboo.c | 1 + hw/ppc/sam460ex.c | 1 + hw/ppc/virtex_ml507.c | 1 + linux-user/arm/cpu_loop.c | 1 + linux-user/elfload.c | 1 + linux-user/mmap.c | 1 + linux-user/nios2/cpu_loop.c | 1 + linux-user/signal.c | 1 + linux-user/syscall.c | 1 + system/physmem.c | 1 + target/alpha/helper.c | 1 + target/arm/ptw.c | 1 + target/arm/tcg/m_helper.c | 1 + target/arm/tcg/mte_helper.c | 1 + target/arm/tcg/sve_helper.c | 1 + target/avr/helper.c | 1 + target/cris/mmu.c | 1 + target/hppa/mem_helper.c | 1 + target/hppa/translate.c | 1 + target/i386/tcg/sysemu/excp_helper.c | 1 + target/loongarch/tlb_helper.c | 1 + target/m68k/helper.c | 1 + target/microblaze/helper.c | 1 + target/microblaze/mmu.c | 1 + target/mips/sysemu/physaddr.c | 1 + target/mips/tcg/sysemu/tlb_helper.c | 1 + target/nios2/helper.c | 1 + target/nios2/mmu.c | 1 + target/openrisc/mmu.c | 1 + target/ppc/mmu-hash32.c | 1 + target/ppc/mmu-hash64.c | 1 + target/ppc/mmu-radix64.c | 1 + target/ppc/mmu_common.c | 1 + target/ppc/mmu_helper.c | 1 + target/riscv/cpu_helper.c | 1 + target/riscv/pmp.c | 1 + target/riscv/vector_helper.c | 1 + target/rx/cpu.c | 1 + target/s390x/mmu_helper.c | 1 + target/s390x/tcg/mem_helper.c | 1 + target/sh4/helper.c | 1 + target/sparc/ldst_helper.c | 1 + target/sparc/mmu_helper.c | 1 + target/tricore/helper.c | 1 + target/xtensa/mmu_helper.c | 1 + target/xtensa/op_helper.c | 1 + 60 files changed, 98 insertions(+), 34 deletions(-) create mode 100644 include/exec/page-prot-common.h diff --git a/bsd-user/bsd-mem.h b/bsd-user/bsd-mem.h index 21d9bab889..f95472bcab 100644 --- a/bsd-user/bsd-mem.h +++ b/bsd-user/bsd-mem.h @@ -56,6 +56,7 @@ #include #include "qemu-bsd.h" +#include "exec/page-prot-common.h" extern struct bsd_shm_regions bsd_shm_regions[]; extern abi_ulong target_brk; diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index dc842fffa7..1e38d2cb66 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -36,6 +36,7 @@ extern char **environ; #include "target_os_signal.h" #include "target.h" #include "exec/gdbstub.h" +#include "exec/page-prot-common.h" #include "qemu/clang-tsa.h" #include "qemu-os.h" diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index d2ddfae286..1e67085d47 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -19,6 +19,7 @@ #ifndef CPU_ALL_H #define CPU_ALL_H +#include "exec/page-prot-common.h" #include "exec/cpu-common.h" #include "exec/memory.h" #include "exec/tswap.h" @@ -156,40 +157,6 @@ extern const TargetPageBits target_page; #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) -/* same as PROT_xxx */ -#define PAGE_READ 0x0001 -#define PAGE_WRITE 0x0002 -#define PAGE_EXEC 0x0004 -#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) -#define PAGE_VALID 0x0008 -/* - * Original state of the write flag (used when tracking self-modifying code) - */ -#define PAGE_WRITE_ORG 0x0010 -/* - * Invalidate the TLB entry immediately, helpful for s390x - * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() - */ -#define PAGE_WRITE_INV 0x0020 -/* For use with page_set_flags: page is being replaced; target_data cleared. */ -#define PAGE_RESET 0x0040 -/* For linux-user, indicates that the page is MAP_ANON. */ -#define PAGE_ANON 0x0080 - -#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) -/* FIXME: Code that sets/uses this is broken and needs to go away. */ -#define PAGE_RESERVED 0x0100 -#endif -/* Target-specific bits that will be used via page_get_flags(). */ -#define PAGE_TARGET_1 0x0200 -#define PAGE_TARGET_2 0x0400 - -/* - * For linux-user, indicates that the page is mapped with the same semantics - * in both guest and host. - */ -#define PAGE_PASSTHROUGH 0x0800 - #if defined(CONFIG_USER_ONLY) void page_dump(FILE *f); diff --git a/include/exec/page-prot-common.h b/include/exec/page-prot-common.h new file mode 100644 index 0000000000..a38157e8b9 --- /dev/null +++ b/include/exec/page-prot-common.h @@ -0,0 +1,38 @@ +#ifndef EXEC_PAGE_PROT_COMMON_H +#define EXEC_PAGE_PROT_COMMON_H + +/* same as PROT_xxx */ +#define PAGE_READ 0x0001 +#define PAGE_WRITE 0x0002 +#define PAGE_EXEC 0x0004 +#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) +#define PAGE_VALID 0x0008 +/* + * Original state of the write flag (used when tracking self-modifying code) + */ +#define PAGE_WRITE_ORG 0x0010 +/* + * Invalidate the TLB entry immediately, helpful for s390x + * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() + */ +#define PAGE_WRITE_INV 0x0020 +/* For use with page_set_flags: page is being replaced; target_data cleared. */ +#define PAGE_RESET 0x0040 +/* For linux-user, indicates that the page is MAP_ANON. */ +#define PAGE_ANON 0x0080 + +#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) +/* FIXME: Code that sets/uses this is broken and needs to go away. */ +#define PAGE_RESERVED 0x0100 +#endif +/* Target-specific bits that will be used via page_get_flags(). */ +#define PAGE_TARGET_1 0x0200 +#define PAGE_TARGET_2 0x0400 + +/* + * For linux-user, indicates that the page is mapped with the same semantics + * in both guest and host. + */ +#define PAGE_PASSTHROUGH 0x0800 + +#endif diff --git a/include/semihosting/uaccess.h b/include/semihosting/uaccess.h index 6c8835fbcb..02783cca33 100644 --- a/include/semihosting/uaccess.h +++ b/include/semihosting/uaccess.h @@ -15,6 +15,7 @@ #endif #include "exec/cpu-defs.h" +#include "exec/page-prot-common.h" #define get_user_u64(val, addr) \ ({ uint64_t val_ = 0; \ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ea5c8660dc..c14012e07d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -25,6 +25,7 @@ #include "hw/registerfields.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/page-prot-common.h" #include "qapi/qapi-types-common.h" #ifdef TARGET_AARCH64 diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 5b20ecbd33..6bcfbcbed8 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -19,6 +19,7 @@ #define PPC_INTERNAL_H #include "hw/registerfields.h" +#include "exec/page-prot-common.h" /* PM instructions */ typedef enum { diff --git a/target/ppc/mmu-radix64.h b/target/ppc/mmu-radix64.h index 4c768aa5cc..1a3fd8f65b 100644 --- a/target/ppc/mmu-radix64.h +++ b/target/ppc/mmu-radix64.h @@ -3,6 +3,8 @@ #ifndef CONFIG_USER_ONLY +#include "exec/page-prot-common.h" + /* Radix Quadrants */ #define R_EADDR_MASK 0x3FFFFFFFFFFFFFFF #define R_EADDR_VALID_MASK 0xC00FFFFFFFFFFFFF diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 852a55fbb6..4e9d6fdb19 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -21,6 +21,7 @@ #include "qemu/main-loop.h" #include "hw/core/tcg-cpu-ops.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/memory.h" #include "exec/cpu_ldst.h" #include "exec/cputlb.h" diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index da39a43bd8..717e31e602 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -23,6 +23,7 @@ #include "exec/cputlb.h" #include "exec/log.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/tb-flush.h" #include "exec/translate-all.h" #include "sysemu/tcg.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 2575f0842f..5ce602b8d6 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -25,6 +25,7 @@ #include "qemu/rcu.h" #include "exec/cpu_ldst.h" #include "exec/translate-all.h" +#include "exec/page-prot-common.h" #include "exec/helper-proto.h" #include "qemu/atomic128.h" #include "trace/trace-root.h" diff --git a/bsd-user/mmap.c b/bsd-user/mmap.c index 3ef11b2807..deb384605e 100644 --- a/bsd-user/mmap.c +++ b/bsd-user/mmap.c @@ -17,6 +17,7 @@ * along with this program; if not, see . */ #include "qemu/osdep.h" +#include "exec/page-prot-common.h" #include "qemu.h" diff --git a/bsd-user/signal.c b/bsd-user/signal.c index 7b2d25230a..699ac60837 100644 --- a/bsd-user/signal.c +++ b/bsd-user/signal.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu.h" +#include "exec/page-prot-common.h" #include "exec/user/tswap-target.h" #include "gdbstub/user.h" #include "signal-common.h" diff --git a/cpu-target.c b/cpu-target.c index 4c1e19ca81..a7209e8de9 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -21,6 +21,7 @@ #include "qapi/error.h" #include "exec/target_page.h" +#include "exec/page-prot-common.h" #include "hw/qdev-core.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index a189942de4..45a215be6d 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -15,6 +15,7 @@ #include "qemu/units.h" #include "qemu/datadir.h" #include "qemu/error-report.h" +#include "exec/page-prot-common.h" #include "net/net.h" #include "hw/pci/pci.h" #include "hw/boards.h" diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 1e615b8d35..ffe467fb16 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -21,6 +21,7 @@ #include "kvm_ppc.h" #include "sysemu/device_tree.h" #include "sysemu/block-backend.h" +#include "exec/page-prot-common.h" #include "hw/loader.h" #include "elf.h" #include "exec/memory.h" diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index d02f330650..e2da13c064 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "qemu/datadir.h" #include "qemu/units.h" +#include "exec/page-prot-common.h" #include "cpu.h" #include "hw/sysbus.h" #include "hw/char/serial.h" diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index b404117ff3..0d05daea91 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -24,6 +24,7 @@ #include "cpu_loop-common.h" #include "signal-common.h" #include "semihosting/common-semi.h" +#include "exec/page-prot-common.h" #include "target/arm/syndrome.h" #define get_user_code_u32(x, gaddr, env) \ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index a8c106ec0c..84484fee97 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -8,6 +8,7 @@ #include "qemu.h" #include "exec/user/tswap-target.h" #include "exec/user/guest-base.h" +#include "exec/page-prot-common.h" #include "user-internals.h" #include "signal-common.h" #include "loader.h" diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 96c9433e27..d37803fc8c 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -20,6 +20,7 @@ #include #include "trace.h" #include "exec/log.h" +#include "exec/page-prot-common.h" #include "qemu.h" #include "user-internals.h" #include "user-mmap.h" diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index da77ede76b..03434abe3b 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -22,6 +22,7 @@ #include "user-internals.h" #include "cpu_loop-common.h" #include "signal-common.h" +#include "exec/page-prot-common.h" void cpu_loop(CPUNios2State *env) { diff --git a/linux-user/signal.c b/linux-user/signal.c index b35d1e512f..50cba136db 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/bitops.h" #include "gdbstub/user.h" +#include "exec/page-prot-common.h" #include "hw/core/tcg-cpu-ops.h" #include diff --git a/linux-user/syscall.c b/linux-user/syscall.c index e384e14248..3d2467d7c8 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -25,6 +25,7 @@ #include "qemu/plugin.h" #include "tcg/startup.h" #include "target_mman.h" +#include "exec/page-prot-common.h" #include #include #include diff --git a/system/physmem.c b/system/physmem.c index 4bdb3d0592..0bea47b5d2 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -31,6 +31,7 @@ #endif /* CONFIG_TCG */ #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/target_page.h" #include "hw/qdev-core.h" #include "hw/qdev-properties.h" diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 970c869771..ea7a769644 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "fpu/softfloat-types.h" #include "exec/helper-proto.h" #include "qemu/qemu-print.h" diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 1762b058ae..5eca492db4 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -11,6 +11,7 @@ #include "qemu/range.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "cpu.h" #include "internals.h" #include "cpu-features.h" diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index a26adb75aa..1198b32929 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -16,6 +16,7 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #ifdef CONFIG_TCG #include "exec/cpu_ldst.h" #include "semihosting/common-semi.h" diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index ffb8ea1c34..47f512e6c6 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/ram_addr.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index f006d152cc..7713b7a4d4 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" diff --git a/target/avr/helper.c b/target/avr/helper.c index fdc9884ea0..62758b00ed 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -24,6 +24,7 @@ #include "cpu.h" #include "hw/core/tcg-cpu-ops.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" #include "exec/helper-proto.h" diff --git a/target/cris/mmu.c b/target/cris/mmu.c index b574ec6e5b..dee485419d 100644 --- a/target/cris/mmu.c +++ b/target/cris/mmu.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "mmu.h" #ifdef DEBUG diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 08abd1a9f9..0d78e273f6 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/helper-proto.h" #include "hw/core/cpu.h" #include "trace.h" diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3ef39b1bd7..7e3867e4aa 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -22,6 +22,7 @@ #include "disas/disas.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "exec/helper-proto.h" diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c index 5b86f439ad..a3bf3b7292 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "tcg/helper-tcg.h" typedef struct TranslateParams { diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c index 449043c68b..7f0e413e1e 100644 --- a/target/loongarch/tlb_helper.c +++ b/target/loongarch/tlb_helper.c @@ -13,6 +13,7 @@ #include "internals.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "cpu-csr.h" diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 0a1544cd68..7a69c4a28d 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/gdbstub.h" #include "exec/helper-proto.h" #include "gdbstub/helpers.h" diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 98bdb82de8..e4ce57560d 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "qemu/host-utils.h" #include "exec/log.h" diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 75651979a9..c0b0844f71 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -22,6 +22,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" static unsigned int tlb_decode_size(unsigned int f) { diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c index 05990aa5bb..7ac51c6019 100644 --- a/target/mips/sysemu/physaddr.c +++ b/target/mips/sysemu/physaddr.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "../internal.h" static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index 4ede904800..d0cb46bd1b 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "internal.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "exec/helper-proto.h" diff --git a/target/nios2/helper.c b/target/nios2/helper.c index bb3b09e5a7..b64caa11f6 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "exec/helper-proto.h" diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index d9b690b78e..da7f20cc07 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -22,6 +22,7 @@ #include "qemu/qemu-print.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "mmu.h" #include "exec/helper-proto.h" #include "trace/trace-target_nios2.h" diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 603c26715e..6ca7cc023e 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -22,6 +22,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "hw/loader.h" diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 3976416840..da446632c9 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "sysemu/kvm.h" #include "kvm_ppc.h" #include "internal.h" diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index d645c0bb94..1633a0e5d0 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -21,6 +21,7 @@ #include "qemu/units.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" #include "sysemu/hw_accel.h" diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 5823e039e6..13f5ed7fb7 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "qemu/error-report.h" #include "sysemu/kvm.h" #include "kvm_ppc.h" diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 6ca5d12207..83a91a92ea 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -25,6 +25,7 @@ #include "mmu-hash64.h" #include "mmu-hash32.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/log.h" #include "helper_regs.h" #include "qemu/error-report.h" diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index f87d35379a..6368dceb16 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -25,6 +25,7 @@ #include "mmu-hash64.h" #include "mmu-hash32.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/log.h" #include "helper_regs.h" #include "qemu/error-report.h" diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e7e23b34f4..565e6614d9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -24,6 +24,7 @@ #include "internals.h" #include "pmu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "instmap.h" #include "tcg/tcg-op.h" #include "trace.h" diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 162e88a90a..59f4c3d481 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -25,6 +25,7 @@ #include "cpu.h" #include "trace.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, uint8_t val); diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index c1c3a4d1ea..968bff34f2 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/memop.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 9cc9d9d15e..6cc3173a1e 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "migration/vmstate.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "hw/loader.h" #include "fpu/softfloat.h" #include "tcg/debug-assert.h" diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index fbb2f1b4d4..0b2240e39a 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -24,6 +24,7 @@ #include "sysemu/kvm.h" #include "sysemu/tcg.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "trace.h" #include "hw/hw.h" #include "hw/s390x/storage-keys.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 84103251b9..2a8ee4df6b 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -25,6 +25,7 @@ #include "tcg_s390x.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/cpu_ldst.h" #include "hw/core/tcg-cpu-ops.h" #include "qemu/int128.h" diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 5a6f653c12..c9f41d1e2e 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/log.h" #if !defined(CONFIG_USER_ONLY) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 09066d5487..078e25e363 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -23,6 +23,7 @@ #include "tcg/tcg.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "exec/cpu_ldst.h" #include "asi.h" diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 453498c670..e723868148 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "qemu/qemu-print.h" #include "trace.h" diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 7e5da3cb23..e736630a79 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -20,6 +20,7 @@ #include "hw/registerfields.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #include "fpu/softfloat-helpers.h" #include "qemu/qemu-print.h" diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 12552a3347..d7611f1168 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -33,6 +33,7 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" +#include "exec/page-prot-common.h" #define XTENSA_MPU_SEGMENT_MASK 0x0000001f #define XTENSA_MPU_ACC_RIGHTS_MASK 0x00000f00 diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 496754ba57..a9048ad6ac 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -28,6 +28,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" +#include "exec/page-prot-common.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" #include "qemu/atomic.h" From patchwork Tue Dec 12 12:33:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 753078 Delivered-To: patch@linaro.org Received: by 2002:a5d:4c83:0:b0:333:3a04:f257 with SMTP id z3csp1877109wrs; Tue, 12 Dec 2023 04:39:14 -0800 (PST) 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Tue, 12 Dec 2023 04:36:51 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, Brian Cain , Thomas Huth , Paolo Bonzini , qemu-arm@nongnu.org, Manos Pitsidianakis , =?utf-8?q?Alex_Benn=C3=A9e?= , Anton Johansson , Warner Losh , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 23/23] exec/cpu_ldst: Avoid including 'cpu.h' Date: Tue, 12 Dec 2023 13:33:59 +0100 Message-ID: <20231212123401.37493-24-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212123401.37493-1-philmd@linaro.org> References: <20231212123401.37493-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=philmd@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "exec/cpu_ldst.h" doesn't need to huge "cpu.h" header, but simply: - exec/cpu-defs.h (TARGET_LONG_BITS) - exec/tlb-common.h (CPUTLBEntry) - exec/user/abitypes.h (abi_ulong) - exec/user/guest-base.h (guest_base) - exec/cpu-all.h (GUEST_ADDR_MAX and env_cpu) Signed-off-by: Philippe Mathieu-Daudé --- env_cpu() will soon be removed from "exec/cpu-all.h". Do we want to move GUEST_ADDR_MAX declaration to "user/guest-base.h", eventually renaming it as "user/guest-addr.h"? --- include/exec/cpu_ldst.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index e039cc7f80..ec0784bf15 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -65,11 +65,14 @@ #include "exec/memopidx.h" #include "exec/abi_ptr.h" #include "qemu/int128.h" -#include "cpu.h" +#include "exec/cpu-defs.h" +#include "exec/tlb-common.h" #if defined(CONFIG_USER_ONLY) +#include "exec/user/abitypes.h" #include "exec/user/guest-base.h" +#include "exec/cpu-all.h" #ifndef TARGET_TAGGED_ADDRESSES static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x)