From patchwork Thu Aug 29 11:33:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172578 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2090882ily; Thu, 29 Aug 2019 04:34:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqwCwyC3RrE5zl/GkfNbMfkqx+sxaR0lIy0Z9MgULK32kZ8BJdtR9T18LpbgoFRZhvT8wpx2 X-Received: by 2002:aa7:8602:: with SMTP id p2mr10720854pfn.138.1567078496790; Thu, 29 Aug 2019 04:34:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078496; cv=none; d=google.com; s=arc-20160816; b=OpgUdP25BxKW7wHDb60xEyNWmTxOaYanDQ274X0V9B5HmsXKjmWQ0oi7869h/PPdpp pmwlZfhNlIeWzhwpJ0TeY18LzBAmy8TfOdT/FeN//8AzkR7LbnXYm1C7bCclME7JFmuo V+VzK1rsBYHE0v9aOQEb9DbVQVKHoueYsFa26tLyotbVKTYni6Je9cisFUDirLfN8g5v PYgaUSE0l2rHtrk+kPRQDs4ybaJw1SB0cwtjK/9eJbD+qPCNuKUbgNNsiGvRiezJOgBC bKICBCrxB1ZbcyTk0bhOwV6aulnmwSficRCsud9iBhP+PJe7MUCzS+RU+tRYlmNAaaK8 gV4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=t+8ZINgorfc9/vHqnYTLmiCH63MmZJ4ah1lcUclNBnY=; b=ns/lAW/hNsiuRxNktuo1mqoPydwA5sMsWeiultFFfw42ubziLBeF8r5nZIKcQZSsRg znBpKdZiFW/+WRvE12VUygua+b0j0iOdsMaMOhG9o7E8KjZt8ZZ/TZ3M26VngWBG9k1H 8J80W3IEH2Njv3YZtIBAWILYlbrPz+rFbtxovRWGKmdcT+mMrNavLBhkJEwODxPxtqxh QNJphs8leq5bsZQ1alhtgm+NGyoP3SHfxm6vmbMLTsfE64ZTz2TmUBihsxVekOFb7JLY P7sLhwmFFqkPF9/u7ZM6cUbmQCUIFn9Cu+mpVko4486OM9nPrjCPmK67FZu1JizBhEXF ipzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nCZcANTj; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i2si1752366pgk.534.2019.08.29.04.34.56; Thu, 29 Aug 2019 04:34:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nCZcANTj; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726379AbfH2Le4 (ORCPT + 14 others); Thu, 29 Aug 2019 07:34:56 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:43182 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725990AbfH2Le4 (ORCPT ); Thu, 29 Aug 2019 07:34:56 -0400 Received: by mail-pg1-f194.google.com with SMTP id k3so1435351pgb.10 for ; Thu, 29 Aug 2019 04:34:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t+8ZINgorfc9/vHqnYTLmiCH63MmZJ4ah1lcUclNBnY=; b=nCZcANTj/VNAghMCqmhGdelYjpzJSNUODI1MeolRwGX3zV0RZ6cTZyhBDhxf30vbvg IkLKsTO09Sw7p8F+QQZ/dyIU6LDSLt14M+i7RWDo+xmqe+7UZrE1gpasqOae5bUnmtnY bZYtRNqdELatX3EBN5JSjhvVUEazVL+8ZG4DKfRLhmxrbw+IKn6J/1c6V2cMMkThVNvr +HjrmOBBAziBdsZj2nUzXPwD5hES6Ujave3wFaUXCN3sqQeC9opJK2OXRegCxJPNivSv CBPquIEQBdQjpnSgkAFjNOyT8/fSEdG1h4P3pvDHVQvjfjJjVzJZVORmthdGiEFBUzA1 zKgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t+8ZINgorfc9/vHqnYTLmiCH63MmZJ4ah1lcUclNBnY=; b=jb9ZtKbjWVancD5tkfl9SHeWJd7mS4hX5DUoyOio0ulDEbJXSPD8foTCGT3hMbEFSz 5AwX7vQuE5Q2jl+doWwHpcEFSh0zyhKG4VcBXO8ESUcaunGih0xGIPt2sJVM6vCiS2xw WAIGLYMqkHj+Kr5M2fHW1XlvmGyJdfOjgAd1PLZ2wZNALJqXmQfzBl4DD7bLTI0O51LO cGfQRpXqFr6n0HbsEqcW0ZlV+S+cA+Zv2cKl4CbS5OpHF90hB2YRiSJ53BL/dJrbJ8GL C5nGGkSJl2zEEAYKya4i6D/RB4b1gIjnL3yb6nV7eB82M8/XCCrBR+aeR73oT6yonHGX l4qA== X-Gm-Message-State: APjAAAXbdS4wapjurPOTIcTl1m9rddiOqfVP+OGxPTKEMsfmAdCwif7o qyU9icvZztuEA9Bc3YRF9XbprsB93OU= X-Received: by 2002:a62:53c3:: with SMTP id h186mr10792040pfb.178.1567078495033; Thu, 29 Aug 2019 04:34:55 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id a13sm2564706pfn.104.2019.08.29.04.34.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:34:54 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 01/44] arm64: barrier: Add CSDB macros to control data-value prediction Date: Thu, 29 Aug 2019 17:03:46 +0530 Message-Id: <4ba4e0d015f2e044e3eaf57e1239ae3e12d5a80e.1567077734.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit 669474e772b952b14f4de4845a1558fd4c0414a4 upstream. For CPUs capable of data value prediction, CSDB waits for any outstanding predictions to architecturally resolve before allowing speculative execution to continue. Provide macros to expose it to the arch code. Reviewed-by: Mark Rutland Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/assembler.h | 7 +++++++ arch/arm64/include/asm/barrier.h | 2 ++ 2 files changed, 9 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b Reviewed-by: Mark Rutland [v4.4 backport] diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index f68abb17aa4b..683c2875278f 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -95,6 +95,13 @@ dmb \opt .endm +/* + * Value prediction barrier + */ + .macro csdb + hint #20 + .endm + #define USER(l, x...) \ 9999: x; \ .section __ex_table,"a"; \ diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index f2d2c0bbe21b..574486634c62 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -28,6 +28,8 @@ #define dmb(opt) asm volatile("dmb " #opt : : : "memory") #define dsb(opt) asm volatile("dsb " #opt : : : "memory") +#define csdb() asm volatile("hint #20" : : : "memory") + #define mb() dsb(sy) #define rmb() dsb(ld) #define wmb() dsb(st) From patchwork Thu Aug 29 11:33:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172579 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2090931ily; Thu, 29 Aug 2019 04:34:59 -0700 (PDT) X-Google-Smtp-Source: APXvYqz5DfsollYCqw8qx7cydlSvUFsm7FgJJ8U+6u0UV9adwXCHALlyOmxmTISDU4v36hwwIh4H X-Received: by 2002:a63:31cc:: with SMTP id x195mr7788448pgx.147.1567078499585; Thu, 29 Aug 2019 04:34:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078499; cv=none; d=google.com; s=arc-20160816; b=kHTKz9ttmvyeXgbIFaNlYtdTQtblWeWrCODn1VbYWnqkhOrFDboR2ur0PurzqfitKw c1HerFT0Wn/Pb+dO3BFdaikqbHgtE6GtKG9QGeYVue9VM95jPTwbNytWs7ffyoYyda2x BQMGCpHhqBkjPZs1TOdxt2w+0FGpDCr2VFNZECarnbviV8+E7eDml2Nn6VoFJrtRIsVO +BZGoV9/dtq266bPa245XhPEDxgxvqQDEMFvCBDBFlyyazBj5n7cUbEd6Of21rOu7Zd7 mTP5+02ZJ88l70Z7xirHpYLwEtuaYNNAUa0aD9bTvmb3SAYvVGg7yDMuQ8Q2oPyTo4gR F7QA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QZmd1kVLh8a0enxFfoIC/p5hW82ft4CjkM7ASI4iKD4=; b=Vc2bXD6q0jpaZ811IAwAXjlUen51knepcB0llqk2bVeVcgB0gZ4LUElIJo62mTnvdL ytA6tWs44kcmFoVYjvQAAPr40hqtbXzJn4iC3q+O/rBJE6F1EQf8zPeLGocb92wonfpG EwGOUgo5EQy6PkGJ5EbEyLdMMVBFF1kOQ1KpmOLUC6fp+aAJZF6NeP7AKch/+koF6Aj6 i5CBS3p5yJ4bHmBm0QRwb3ybal4L/ntKpf0H7j6ykUa3H9hxhSR51PLmLP9c78DuWb72 0BrvzZl2FfeQO6YEx84WXY1sIvjpy2GtogRC46o0/KTsA85uuub80tMVxR/ehNN4UP70 IrvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gtKVgQDc; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i2si1752366pgk.534.2019.08.29.04.34.59; Thu, 29 Aug 2019 04:34:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gtKVgQDc; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727026AbfH2Le7 (ORCPT + 14 others); Thu, 29 Aug 2019 07:34:59 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:42387 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726983AbfH2Le6 (ORCPT ); Thu, 29 Aug 2019 07:34:58 -0400 Received: by mail-pg1-f196.google.com with SMTP id p3so1434875pgb.9 for ; Thu, 29 Aug 2019 04:34:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QZmd1kVLh8a0enxFfoIC/p5hW82ft4CjkM7ASI4iKD4=; b=gtKVgQDc9GJLsqxkdO8KHXtp476POxHclR4w6cx/eJloeqLLtmxIGGY7ToOzR9UfpY mtkJxWZmFxaWeQhYjV62uXXInNjF5dDf3djI1IZn1tEjn3YELqzx15He1/yBUkAa2J/g yVMauTVFsu9mNLCSBCkJ6jcqVA0VN6/sqzVXuvS61g0flUiw+pRqovwedo858JXI0stW K2gPSOtM1b4XhMfLMPiqGfe7kKMa2XLwpUKvz+ZtOKHEsTXbxzuhOcxMppZiT8t0HgNa JGxLu/qgJJgU0RhLcEK1vrGGYXoKvf5QIWb0p2jOHiYT8LLyW1KJdljpq4hkNtbUc5Xm BZ4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QZmd1kVLh8a0enxFfoIC/p5hW82ft4CjkM7ASI4iKD4=; b=HHJs0hCxghGPLwOLArn7hABzPu5uqtICREBYNo5okjWvkaOyBWUYlG4LfdJZPbwq97 b4Z/5yFizdGqQUww35Z65pswOlr5RoKIH5biCdgwRuwirwLxIv8baXQY3XgVR9Ql8nIZ HqHJpeYaibnXllZdOOdhlqkeXUhaHyd3VZtsItjbx9AqRURwoFjfcj0y9Jon6rGS0cVM oXCpCNCMZv3H1f+XRKvZp18WrFFcCV94S7e2VpsGd0SlRG6BvgCpyI+tBjrFGnUZFfIA 9NqxSNoFTRNEmMsPi+5kNIPdmzTzKbU35h3PU7jcXG6+OiXJ4H1Cl0iqxT+nPnISHkpw X91A== X-Gm-Message-State: APjAAAWxgp7hyeWnIjXxLt5uL5dTssZEYCiFB+IJMc5cTgDhcUk0yxZa rI7IdrMOi19YeAfiw5o6IOns2LvYFPY= X-Received: by 2002:a62:1444:: with SMTP id 65mr10603079pfu.145.1567078497711; Thu, 29 Aug 2019 04:34:57 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id d20sm2784549pfo.90.2019.08.29.04.34.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:34:57 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 02/44] arm64: Implement array_index_mask_nospec() Date: Thu, 29 Aug 2019 17:03:47 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Robin Murphy commit 022620eed3d0bc4bf2027326f599f5ad71c2ea3f upstream. Provide an optimised, assembly implementation of array_index_mask_nospec() for arm64 so that the compiler is not in a position to transform the code in ways which affect its ability to inhibit speculation (e.g. by introducing conditional branches). This is similar to the sequence used by x86, modulo architectural differences in the carry/borrow flags. Reviewed-by: Mark Rutland Signed-off-by: Robin Murphy Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/barrier.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b Reviewed-by: Mark Rutland [v4.4 backport] diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index 574486634c62..7c25e3e11b6d 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -37,6 +37,27 @@ #define dma_rmb() dmb(oshld) #define dma_wmb() dmb(oshst) +/* + * Generate a mask for array_index__nospec() that is ~0UL when 0 <= idx < sz + * and 0 otherwise. + */ +#define array_index_mask_nospec array_index_mask_nospec +static inline unsigned long array_index_mask_nospec(unsigned long idx, + unsigned long sz) +{ + unsigned long mask; + + asm volatile( + " cmp %1, %2\n" + " sbc %0, xzr, xzr\n" + : "=r" (mask) + : "r" (idx), "Ir" (sz) + : "cc"); + + csdb(); + return mask; +} + #define smp_mb() dmb(ish) #define smp_rmb() dmb(ishld) #define smp_wmb() dmb(ishst) From patchwork Thu Aug 29 11:33:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172580 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2090969ily; Thu, 29 Aug 2019 04:35:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqyciQgNNQLt2sobRgFeLGWkzxVRpqORTh5o3CWHmsCf/QXlsu3sQsRpFHoUiATDb+lxeq79 X-Received: by 2002:a62:1858:: with SMTP id 85mr11007263pfy.120.1567078502258; Thu, 29 Aug 2019 04:35:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078502; cv=none; d=google.com; s=arc-20160816; b=gd+fIpFoGIrJK1wgrOQC3k3NyXPtVMyubPRbnngkkGvN5EifCM0cR4z14LE/cjmmRO pkAdG01ffvlXyGOJwbuFum06c3SEirj6/ZnK+0UXFTxPj43XcbEGQODhdREp/rHrZhCT Cn4B7WPw1FBFn7G+ssTvkNu2k0hnSZ9cPkdi8jG9eXIv54R0Cx4AsQXDs4dnGBdyfu+w 5pgIx6+YrIy7+vGUvCj9wgphyktnplUB/6CnbV9pUPr3wli2N3HjDgG/7BXnRKaDhFLL P3QPYzxUdlABMlLafXmtwCHyc1ELsXPslwi4LD4hNd6hyq+vdpn3tWadVjfeBIb/v8PD kpFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ES6KJwQvdOYp/ZF0zdgUUsDi+h2pkDI/v1RQA0OQPVY=; b=xi64judaOcDaTY6IsK5tvK+XOZaaiWROunnquYUjS0BNxXRrLwMMuWUeQc1Oog0q9/ EuhkVXZZlrZyKyaOGOJrvV6bOWuveOpGG71UYMyI+6eVsAmTNIahWkODoazV85i+/CYj 1tfI2a9ziQzTmvtVteRC3SjIXu+zc524Ov1ckWM41sy7xcHhCtkEyujvHKmWyKNOlCTS o3QsolNdH79MjuRokFYHpM7uvuqQYUMtP7fFWpHjcPHZjdl87nAELiQ3XVevuTfyFa3n MiiR1eT6ylarIgGqWw1QLQZz3jycEaDY+48N/YCDH1J3LP2ln4zDi+5w1sTELFA6HvuG 8VTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N8ypWh9b; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i2si1752366pgk.534.2019.08.29.04.35.02; Thu, 29 Aug 2019 04:35:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N8ypWh9b; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727051AbfH2LfB (ORCPT + 14 others); Thu, 29 Aug 2019 07:35:01 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:41700 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726983AbfH2LfB (ORCPT ); Thu, 29 Aug 2019 07:35:01 -0400 Received: by mail-pf1-f195.google.com with SMTP id 196so1855157pfz.8 for ; Thu, 29 Aug 2019 04:35:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ES6KJwQvdOYp/ZF0zdgUUsDi+h2pkDI/v1RQA0OQPVY=; b=N8ypWh9bUBCQg5Qrp3UqxAwWng+Qg3fzHmDGkcGYs3MmNmm2g40ZfbG6LcePKVNtcN 2SqhleEP3CF+UMjT+Q8lIsUUb04onlh1FnqC+rOlnICQ5SY72w9ZTRSz+Ssvc6ocLrB2 t7UZ9Ici3AH5doJc+q+SWI6Mpno9SBbcmKo/oYyy9Dub9FpEdk6mbwwKHfmKfAC8GCOR P/hlqL30UkbzV3NZhDtedPQ8hNugxum8f6BjdZDwMHsIboa30nvtGlJICaeHXjA1rqLp E6UpmqFPrUEn3Muc2TJPfcw7aGy3xgrPS0UMR6jaUZNekPVxRXqeM1jxxTZMs/IAvZ9O +g5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ES6KJwQvdOYp/ZF0zdgUUsDi+h2pkDI/v1RQA0OQPVY=; b=c4htNs0lT/jwzjnbqoXGSoTsjpeIRv/u4FuAQk/bfbTWj+i3n1EmXaC/+23AKFp4e2 /iz+JpLZqLfnoS8GeoHLlvNCY5cvy34MscAXv+Xwt4ILfp2ndyxDnw1s2w+wsC2Rw8GC 1GudU+BcrZdzPuBU9Q70pQJ6e/HM0YiClcZioQ3y7ou7DrM5Y7Z/3TJD029VNyQp/WDe D5lN3kH2RMEsx/figpZXtjcJsZpxnO8v+PuKvzbduj7YJiaV3LIt+Th+IV2qxzwR69Xq CjqRK7jACdnUhr7gVqya0UxFvKFSp8dCwNcVzypIB2yaDPI6f55B2EBCPHRUA6/LN8rI m5NA== X-Gm-Message-State: APjAAAUmn7byfQhkh7pSHT/vl2SJYv4FXj/JzxEWWlUoWLYcCKb7Z+E2 M0NaA9SFAss+17b3eQ6hXob+8h/mh1E= X-Received: by 2002:a63:9e56:: with SMTP id r22mr7890169pgo.221.1567078500171; Thu, 29 Aug 2019 04:35:00 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id p2sm5205020pfb.122.2019.08.29.04.34.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:34:59 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 03/44] arm64: move TASK_* definitions to Date: Thu, 29 Aug 2019 17:03:48 +0530 Message-Id: <687d13717c9736bc33b9128bd09371fc0453fbdd.1567077734.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Yury Norov commit eef94a3d09aab437c8c254de942d8b1aa76455e2 upstream. ILP32 series [1] introduces the dependency on for TASK_SIZE macro. Which in turn requires , and include , giving a circular dependency, because TASK_SIZE is currently located in . In other architectures, TASK_SIZE is defined in , and moving TASK_SIZE there fixes the problem. Discussion: https://patchwork.kernel.org/patch/9929107/ [1] https://github.com/norov/linux/tree/ilp32-next CC: Will Deacon CC: Laura Abbott Cc: Ard Biesheuvel Cc: Catalin Marinas Cc: James Morse Suggested-by: Mark Rutland Signed-off-by: Yury Norov Signed-off-by: Will Deacon Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/memory.h | 15 --------------- arch/arm64/include/asm/processor.h | 21 +++++++++++++++++++++ arch/arm64/kernel/entry.S | 2 +- 3 files changed, 22 insertions(+), 16 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b Reviewed-by: Mark Rutland [v4.4 backport] diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h index b42b930cc19a..959a1e9188fe 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -43,8 +43,6 @@ * (VA_BITS - 1)) * VA_BITS - the maximum number of bits for virtual addresses. * VA_START - the first kernel virtual address. - * TASK_SIZE - the maximum size of a user space task. - * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area. * The module space lives between the addresses given by TASK_SIZE * and PAGE_OFFSET - it must be within 128MB of the kernel text. */ @@ -58,19 +56,6 @@ #define PCI_IO_END (MODULES_VADDR - SZ_2M) #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) #define FIXADDR_TOP (PCI_IO_START - SZ_2M) -#define TASK_SIZE_64 (UL(1) << VA_BITS) - -#ifdef CONFIG_COMPAT -#define TASK_SIZE_32 UL(0x100000000) -#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ - TASK_SIZE_32 : TASK_SIZE_64) -#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \ - TASK_SIZE_32 : TASK_SIZE_64) -#else -#define TASK_SIZE TASK_SIZE_64 -#endif /* CONFIG_COMPAT */ - -#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4)) /* * Physical vs virtual RAM address space conversion. These are diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index d08559528927..75d9ef6c457c 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -19,6 +19,10 @@ #ifndef __ASM_PROCESSOR_H #define __ASM_PROCESSOR_H +#define TASK_SIZE_64 (UL(1) << VA_BITS) + +#ifndef __ASSEMBLY__ + /* * Default implementation of macro that returns current * instruction pointer ("program counter"). @@ -36,6 +40,22 @@ #include #ifdef __KERNEL__ +/* + * TASK_SIZE - the maximum size of a user space task. + * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area. + */ +#ifdef CONFIG_COMPAT +#define TASK_SIZE_32 UL(0x100000000) +#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ + TASK_SIZE_32 : TASK_SIZE_64) +#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \ + TASK_SIZE_32 : TASK_SIZE_64) +#else +#define TASK_SIZE TASK_SIZE_64 +#endif /* CONFIG_COMPAT */ + +#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4)) + #define STACK_TOP_MAX TASK_SIZE_64 #ifdef CONFIG_COMPAT #define AARCH32_VECTORS_BASE 0xffff0000 @@ -188,4 +208,5 @@ static inline void spin_lock_prefetch(const void *x) int cpu_enable_pan(void *__unused); +#endif /* __ASSEMBLY__ */ #endif /* __ASM_PROCESSOR_H */ diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 586326981769..c849be9231bb 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include #include From patchwork Thu Aug 29 11:33:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172581 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2091003ily; Thu, 29 Aug 2019 04:35:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqxlWSXoK14633G76Kxinke6J/g6VbwL2s3klVcn9breAdVd03izoDhCoCahAB6bjUgqoSmm X-Received: by 2002:a05:6a00:46:: with SMTP id i6mr10993357pfk.196.1567078504927; Thu, 29 Aug 2019 04:35:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078504; cv=none; d=google.com; s=arc-20160816; b=W5kr/fahMKgTaP5Qa+98ZhjnNlCogIV8xg0W6CuRK3X0iN9GADVZ49GQyLsYq42xuG nI8wjKKpmJ2/nVUbFvI3qsb8c8TPAn4e7bQkRlJ6gDbx2IyYlLwtaqHOA1hjtf6XiTIq VCsC4dImHP/Us6eBOweyt/tnVmSpMz1l6J2A2j5nLxDEPWNLrOSsa+h/WTz84TgvvNd9 KNwqnG7A8qonDwghJK5StmHCv3ZuVSnc/GKiZiDAdXg5eD5pg4Eoyotl2fK+UPavs6Rn XK4fWi7UsrReW/k1f18IB93igsxC+XIgvTN+iholDKaOJP8Ua/tQPUhMO6KbCJ+elBHL rUBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kHvdeN9oObJ1DWOknB6wJwOgumkOXHrRy2jfFMpABJ8=; b=BndY7t/FIGOI2tI2jWNkzl1TbE5ucp7Wvqis+z7MMEkhIoxQa8OH0SPrt2KCEiaw/K T0ER4838ecbZerVVnq1Zo3mIG2d8KnHu7xYG7iW4OzHKoS9JjzxoKFOzaiX5vak4zjt8 kyy+2n4VbxqGtD07hay7LMzfwHwC1q64SqCn+z34zW2IRCNUGRJySNC+OgnWj8FAnWvO 7f8Jh0cIKJqBb4uLmq3NjnXTtxRkWoKMHBWTFzm3haOzfKuwC+LeJj2GRCr8iuqdnRLV eJBOcVGjBjCVUsRwFhNTD4DMGtUEsaiAJRBTe2pewkTuKa1nahvOM8ODArAXpCRBXaJW Yh+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E0eqydah; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i2si1752366pgk.534.2019.08.29.04.35.04; Thu, 29 Aug 2019 04:35:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E0eqydah; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727025AbfH2LfE (ORCPT + 14 others); Thu, 29 Aug 2019 07:35:04 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:37455 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725990AbfH2LfE (ORCPT ); Thu, 29 Aug 2019 07:35:04 -0400 Received: by mail-pf1-f193.google.com with SMTP id y9so1869135pfl.4 for ; Thu, 29 Aug 2019 04:35:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kHvdeN9oObJ1DWOknB6wJwOgumkOXHrRy2jfFMpABJ8=; b=E0eqydahPr0xeqAZBqi7e7Ni2Cc7nIKSMFIuNCPVKFztaIU87as0wu7lDsChydOqGE NbY+aHH+m1XpuQBiGurAvDyfVB0nHBqDRtTAGQ1awghUZNaq2B48O0LmzC8wpRaq66tY szMNV1zVUisdCHI08NTOlzn4PakgRnebE/apB/GcumiTa4iqV0HWl7ZTIlHBxpNRwhe3 Nv7IOKHIXLlb5fIi32MTa9SZgj5k5ZmrS34KaFtZznALoqeZC7U9wV8aordLxF5kwnnV E0x0OmA/bhCg4SA9x9i6QWFR0otYSFu8tjYUiZp1qjp6JqY4hwfhC3lDHeLTzIVXLlqS TIkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kHvdeN9oObJ1DWOknB6wJwOgumkOXHrRy2jfFMpABJ8=; b=Pw260uzY8pintlyUnXsL8+xp27a+34/gpYV/ykdXeQ+2ldlPflUQVyYytDv5btSn/C qhi9T9n805ik7v9ZsHP2QJq9d3r4ecZoQiwJ8HpESov0XZB60hWCZw8wyA9orxp0SJ3O QSlLZPi01TYV5+TTJBcWhdpp++RSd/T0Do0fnYG25mHE20o0tOxpi6aBDTUViuP0xrXE wS0K/ldeKKV5+AURwce8khedHGQTM0Dh6B+phN+H+NIT8SjfzijcLcK6zVkAwEmnEvTk wiJrXo+HPTb3AtGgxleCL382bEYtmKGaM0kpCDz9fNxefAAPnMlDbtdQFRGT4ZHJY6Y/ PwFg== X-Gm-Message-State: APjAAAX5toISo6/rxy7SuW5yF5ew2K98A1O9ObxAZfa030tJisXW13Fa aAcaIO/zW2F68/8Y3l8kXAp/KjsjXkY= X-Received: by 2002:a63:1020:: with SMTP id f32mr8172264pgl.203.1567078502823; Thu, 29 Aug 2019 04:35:02 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id e66sm6387216pfe.142.2019.08.29.04.35.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:35:02 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 04/44] arm64: Make USER_DS an inclusive limit Date: Thu, 29 Aug 2019 17:03:49 +0530 Message-Id: <55f8561f1ee207237fdcfbc8c5dc043be06d3de6.1567077734.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Robin Murphy commit 51369e398d0d33e8f524314e672b07e8cf870e79 upstream. Currently, USER_DS represents an exclusive limit while KERNEL_DS is inclusive. In order to do some clever trickery for speculation-safe masking, we need them both to behave equivalently - there aren't enough bits to make KERNEL_DS exclusive, so we have precisely one option. This also happens to correct a longstanding false negative for a range ending on the very top byte of kernel memory. Mark Rutland points out that we've actually got the semantics of addresses vs. segments muddled up in most of the places we need to amend, so shuffle the {USER,KERNEL}_DS definitions around such that we can correct those properly instead of just pasting "-1"s everywhere. Signed-off-by: Robin Murphy Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ 4.4: Dropped changes from fault.c and fixed minor rebase conflict ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/processor.h | 3 ++ arch/arm64/include/asm/uaccess.h | 45 +++++++++++++++++------------- arch/arm64/kernel/entry.S | 4 +-- 3 files changed, 31 insertions(+), 21 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b Reviewed-by: Mark Rutland [v4.4 backport] diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index 75d9ef6c457c..ff1449c25bf4 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -21,6 +21,9 @@ #define TASK_SIZE_64 (UL(1) << VA_BITS) +#define KERNEL_DS UL(-1) +#define USER_DS (TASK_SIZE_64 - 1) + #ifndef __ASSEMBLY__ /* diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 829fa6d3e561..c625cc5531fc 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -56,10 +56,7 @@ struct exception_table_entry extern int fixup_exception(struct pt_regs *regs); -#define KERNEL_DS (-1UL) #define get_ds() (KERNEL_DS) - -#define USER_DS TASK_SIZE_64 #define get_fs() (current_thread_info()->addr_limit) static inline void set_fs(mm_segment_t fs) @@ -87,22 +84,32 @@ static inline void set_fs(mm_segment_t fs) * Returns 1 if the range is valid, 0 otherwise. * * This is equivalent to the following test: - * (u65)addr + (u65)size <= current->addr_limit - * - * This needs 65-bit arithmetic. + * (u65)addr + (u65)size <= (u65)current->addr_limit + 1 */ -#define __range_ok(addr, size) \ -({ \ - unsigned long __addr = (unsigned long __force)(addr); \ - unsigned long flag, roksum; \ - __chk_user_ptr(addr); \ - asm("adds %1, %1, %3; ccmp %1, %4, #2, cc; cset %0, ls" \ - : "=&r" (flag), "=&r" (roksum) \ - : "1" (__addr), "Ir" (size), \ - "r" (current_thread_info()->addr_limit) \ - : "cc"); \ - flag; \ -}) +static inline unsigned long __range_ok(unsigned long addr, unsigned long size) +{ + unsigned long limit = current_thread_info()->addr_limit; + + __chk_user_ptr(addr); + asm volatile( + // A + B <= C + 1 for all A,B,C, in four easy steps: + // 1: X = A + B; X' = X % 2^64 + " adds %0, %0, %2\n" + // 2: Set C = 0 if X > 2^64, to guarantee X' > C in step 4 + " csel %1, xzr, %1, hi\n" + // 3: Set X' = ~0 if X >= 2^64. For X == 2^64, this decrements X' + // to compensate for the carry flag being set in step 4. For + // X > 2^64, X' merely has to remain nonzero, which it does. + " csinv %0, %0, xzr, cc\n" + // 4: For X < 2^64, this gives us X' - C - 1 <= 0, where the -1 + // comes from the carry in being clear. Otherwise, we are + // testing X' - C == 0, subject to the previous adjustments. + " sbcs xzr, %0, %1\n" + " cset %0, ls\n" + : "+r" (addr), "+r" (limit) : "Ir" (size) : "cc"); + + return addr; +} /* * When dealing with data aborts, watchpoints, or instruction traps we may end @@ -111,7 +118,7 @@ static inline void set_fs(mm_segment_t fs) */ #define untagged_addr(addr) sign_extend64(addr, 55) -#define access_ok(type, addr, size) __range_ok(addr, size) +#define access_ok(type, addr, size) __range_ok((unsigned long)(addr), size) #define user_addr_max get_fs /* diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index c849be9231bb..4c5013b09dcb 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -96,10 +96,10 @@ .else add x21, sp, #S_FRAME_SIZE get_thread_info tsk - /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */ + /* Save the task's original addr_limit and set USER_DS */ ldr x20, [tsk, #TI_ADDR_LIMIT] str x20, [sp, #S_ORIG_ADDR_LIMIT] - mov x20, #TASK_SIZE_64 + mov x20, #USER_DS str x20, [tsk, #TI_ADDR_LIMIT] .endif /* \el == 0 */ mrs x22, elr_el1 From patchwork Thu Aug 29 11:33:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172582 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2091078ily; Thu, 29 Aug 2019 04:35:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqw1buBKi03HIROL9pP7nCeIKTUPl42CjyU3zrSyxEpvRBwMOV0KFNkptzlFzuu1/oWBHY2e X-Received: by 2002:a62:1515:: with SMTP id 21mr10615378pfv.81.1567078507546; Thu, 29 Aug 2019 04:35:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078507; cv=none; d=google.com; s=arc-20160816; b=v5Y35F92ja5doNCaOOGJ22bYK0DsvMjlgbGUkmRzZLJtTuq8Au/quM6gQM+/F70tZs HdcrQg2XzwDKM1ipz9QOSvabj92UI3WLcXAyZbed+y9GC1pb9Cnqph93VmaWsC/wBEhQ qC+W/vmJNrOiIJhEL5d0QpNTQSpVr7gK4GnMCJA38DVdEmakLA1V0Y4BaPS/KAWjwuhB 54v05fKgZo00ptccnyq+r8i1DlNJShtaq/FDUt/27W8lz9KteEBPiqLhmzFmOLxs+TXY nqxTd/QtX5mbVsQxltNIAxLjbztKspxO7tFQdACDVQ37o8yAz4jUXIS8LqXQjX1rNrhN cZbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=oplH30x1zLW/kw5XTQuFI7s72sVvdi1RahKBb4zAIVI=; b=Vb/rY8XgdwPPWi2JsEoO7XSk65jUEj8FDoWbK1eUEDPOR5rvNLQ1ABvyZ7cWA+1o4g hKtqOPHF2aPHOApljaQbAmcaFrELXJJHxfX1/6PlrqwoRP9wRrf4gcA6+9zRoZfISwPv hTIpQuXcOQxI0BCXly3F/cyOMQmpLFKaU0r7Ry4f4++Vle95cHroJQC6JEnoYPZXfuTP 5Zkbq0+iDSGU82Ej/MOhymnvoD21PvHV8pWFQxA2cb+p/c/PisPnLACTsyA05N5iDTey jVXl2zBvc2d+egrRhxla0I9j46EvhNN9KyfU+wkGgnJIAh7XLdMRSU4BR+x0rZyIpEe7 4oww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Xf1eInn9; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Similarly to x86, mitigate speculation past an access_ok() check by masking the pointer against the address limit before use. Even if we don't expect speculative writes per se, it is plausible that a CPU may still speculate at least as far as fetching a cache line for writing, hence we also harden put_user() and clear_user() for peace of mind. Signed-off-by: Robin Murphy Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/uaccess.h | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b Reviewed-by: Mark Rutland [v4.4 backport] diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index c625cc5531fc..75363d723262 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -121,6 +121,26 @@ static inline unsigned long __range_ok(unsigned long addr, unsigned long size) #define access_ok(type, addr, size) __range_ok((unsigned long)(addr), size) #define user_addr_max get_fs +/* + * Sanitise a uaccess pointer such that it becomes NULL if above the + * current addr_limit. + */ +#define uaccess_mask_ptr(ptr) (__typeof__(ptr))__uaccess_mask_ptr(ptr) +static inline void __user *__uaccess_mask_ptr(const void __user *ptr) +{ + void __user *safe_ptr; + + asm volatile( + " bics xzr, %1, %2\n" + " csel %0, %1, xzr, eq\n" + : "=&r" (safe_ptr) + : "r" (ptr), "r" (current_thread_info()->addr_limit) + : "cc"); + + csdb(); + return safe_ptr; +} + /* * The "__xxx" versions of the user access functions do not verify the address * space - it must have been done previously with a separate "access_ok()" @@ -193,7 +213,7 @@ do { \ __typeof__(*(ptr)) __user *__p = (ptr); \ might_fault(); \ access_ok(VERIFY_READ, __p, sizeof(*__p)) ? \ - __get_user((x), __p) : \ + __p = uaccess_mask_ptr(__p), __get_user((x), __p) : \ ((x) = 0, -EFAULT); \ }) @@ -259,7 +279,7 @@ do { \ __typeof__(*(ptr)) __user *__p = (ptr); \ might_fault(); \ access_ok(VERIFY_WRITE, __p, sizeof(*__p)) ? \ - __put_user((x), __p) : \ + __p = uaccess_mask_ptr(__p), __put_user((x), __p) : \ -EFAULT; \ }) @@ -297,7 +317,7 @@ static inline unsigned long __must_check copy_in_user(void __user *to, const voi static inline unsigned long __must_check clear_user(void __user *to, unsigned long n) { if (access_ok(VERIFY_WRITE, to, n)) - n = __clear_user(to, n); + n = __clear_user(__uaccess_mask_ptr(to), n); return n; } From patchwork Thu Aug 29 11:33:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172583 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2091116ily; Thu, 29 Aug 2019 04:35:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqz1wUo+SHTJx0qjyAd3dj1kQQJI4sNhCz4ZGRnUuiESTa1JcSbD0RZ1khdSDhchNe+hNgt+ X-Received: by 2002:a63:c006:: with SMTP id h6mr7843442pgg.290.1567078509784; Thu, 29 Aug 2019 04:35:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078509; cv=none; d=google.com; s=arc-20160816; b=p5GHjEzAP49d72jDdhZCsg0vbRqfniOvLHHjcc22h0mTMFIKZnkxG8Qkm9b9i2XcQI t2ZpfAAXNPeqA+/9J1QgLxJupASglwSknPQ0RWoga6zVFvzk6eBdAaXKj1DQfdnOJlnj wyi+o3ci6ojD4QfQ0+OIOXZdrmPxWt/v+lIDnDFDp831KKN8/nHecRzO2immHoHe4HWb FjZV/HFmP7dAwVbb0aKJhl3v3ePuMaOx9X+ByRXwm3JOwiGnsxXRpJbou130eCYf5rZ9 C/DIDVS/cQPyPdamlJLl2t7F92HAEzNVyN9Xr2OG7WxjSpX8nlmKt6Q3o916FG/cT9HH HrsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=1IdhsUs/fdllTh2EJ+ScRqWrO1uX9GsPUvP6PugnTR0=; b=oHRd3/EfCeviYLB6brxBSfvySFx8aiDPnX3xs/19AH+CHIrsS0nTvP9FHIp5cC6suw LZ+GMiVRK8beh792jHlGoqiJEPDCcs8wOb1LlTO7FsrkcPpDxz98K/k1G7klMswDE5/p KJcfllavOuRCfCNP581l8CeQutId0+kwej3X+h3uBwJvEAzYngvb1z3GU8Mfj5zlHRfY kQ+1kiam0zpfWUyhGiARVlJ2b6+AzHba4MQDY0CmJ7ufXKkUq+/TTrLKyyCVonAitfRs 2Q2kq2UDoE+8IzPmZlhPTjATskJXSVjv7isibO0lvcO8/HBntv0WMrQk2prNFW02Exqd JS+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nxI85Uwx; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i2si1752366pgk.534.2019.08.29.04.35.09; Thu, 29 Aug 2019 04:35:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nxI85Uwx; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727040AbfH2LfJ (ORCPT + 14 others); Thu, 29 Aug 2019 07:35:09 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:37503 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725990AbfH2LfJ (ORCPT ); Thu, 29 Aug 2019 07:35:09 -0400 Received: by mail-pl1-f195.google.com with SMTP id bj8so1451884plb.4 for ; Thu, 29 Aug 2019 04:35:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1IdhsUs/fdllTh2EJ+ScRqWrO1uX9GsPUvP6PugnTR0=; b=nxI85UwxnbVBJqSbq8Ywtoc623bVciPB583W6cIvsNcR9oBenNkMhgmn56N8dl7tHE HCJXonvD30tGaKZHMMV+hUfBy0X963d3yoXUwEU4wjSg1Z72lbwKhxPibPpL4vvKT/sr d9eU0YSkgUUaRy9GZaJXXWZccVQd7hOExhRb4tLvsZBKRmh5CCx4FM+iAh/eQCsKLWWp FIY3VPxy1ObVuPcERjVujhSRX3z9hbu98dIF01oxC51utQfIXqj2ZtYwJ+WWA85tkvl2 4cF/61lyqS+8CzAr/GFd2AGhz0eitx64Llmj8Bs0pXoci4lMlRg6vnKzxGxcF7afafI0 OAOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1IdhsUs/fdllTh2EJ+ScRqWrO1uX9GsPUvP6PugnTR0=; b=nzc+bMDn9x0oy0k79dQnB2e+7k5RYgRK/wkhTjppKc/UwU/lqgkcb+SRezfJ22x7vr uw1hJjJncdBxOoj97r4to4wGntlFZZ6CilKoUQCMCDjJHhPAL3wII4JB3TRXeIeL8Ql+ mZjObrwi0jFJOdco2X2mJsMOfFHZeEq1QLomf/g4rRl4D/dYkrVe5uYkHJ5bYTTocLqC +mfq1xn2RLkmZtnp1JtsVNA9O4pZ8/jS5Q4CLH8uwKq1S/FgrsAOO9zRP/GJEEUlwSa7 8DYGqdO+WQwyNmDVO4RUkXQDXp91Ck5cnuAD9sip8pBiu3MUJ8E4d6BMx4bLPglR1lMT JyEg== X-Gm-Message-State: APjAAAUrP6HevA4j9SCavWoHoL8tND4J0OG5XzBPjCqwoLORfRiVoFpj P62KphGSA6/8ExGs8Rlub1NsT8bx+es= X-Received: by 2002:a17:902:f217:: with SMTP id gn23mr9333792plb.21.1567078508102; Thu, 29 Aug 2019 04:35:08 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id u18sm2794235pfl.29.2019.08.29.04.35.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:35:07 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 06/44] arm64: entry: Ensure branch through syscall table is bounded under speculation Date: Thu, 29 Aug 2019 17:03:51 +0530 Message-Id: <093a9777605bdd2ab2c33948a4e7a3fbb275de4d.1567077734.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit 6314d90e64936c584f300a52ef173603fb2461b5 upstream. In a similar manner to array_index_mask_nospec, this patch introduces an assembly macro (mask_nospec64) which can be used to bound a value under speculation. This macro is then used to ensure that the indirect branch through the syscall table is bounded under speculation, with out-of-range addresses speculating as calls to sys_io_setup (0). Reviewed-by: Mark Rutland Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: use existing scno & sc_nr definitions ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/assembler.h | 11 +++++++++++ arch/arm64/kernel/entry.S | 1 + 2 files changed, 12 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b Reviewed-by: Mark Rutland [v4.4 backport] diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 683c2875278f..2b30363a3a89 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -102,6 +102,17 @@ hint #20 .endm +/* + * Sanitise a 64-bit bounded index wrt speculation, returning zero if out + * of bounds. + */ + .macro mask_nospec64, idx, limit, tmp + sub \tmp, \idx, \limit + bic \tmp, \tmp, \idx + and \idx, \idx, \tmp, asr #63 + csdb + .endm + #define USER(l, x...) \ 9999: x; \ .section __ex_table,"a"; \ diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 4c5013b09dcb..e6aec982dea9 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -697,6 +697,7 @@ el0_svc_naked: // compat entry point b.ne __sys_trace cmp scno, sc_nr // check upper syscall limit b.hs ni_sys + mask_nospec64 scno, sc_nr, x19 // enforce bounds for syscall number ldr x16, [stbl, scno, lsl #3] // address in the syscall table blr x16 // call sys_* routine b ret_fast_syscall From patchwork Thu Aug 29 11:33:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172584 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2091176ily; Thu, 29 Aug 2019 04:35:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqy023f9upk3wNxpC0qwqBEDeDNRcqAIrjbUwvm1XzUiwOjbqM+c1kXxz7BJrCX6lUnTvRLI X-Received: by 2002:aa7:93cc:: with SMTP id y12mr10814534pff.246.1567078512837; Thu, 29 Aug 2019 04:35:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078512; cv=none; d=google.com; s=arc-20160816; b=qz/ZT4ziqqoNTH44IrvLzMiYXS2ytLSAzkBFcZscgV5ohFMG+J3VENaohH3I+02fV4 P4BcrHUEgNrZvk0z2FFWVuuiWJ6lY+coGVc46LMl2hLOmRUu8ttWfrQu+Xe3Aqf3haxv JfB/ltJNzyaDRF597xXmMucLJeN+1OUuxbtKJdK3Cr5d5PrsXbTTmTmQ9tbhxb0YLTa0 acW+JSYcUL7Vlxvln4mYP2hLCy9cqGyYmbC6MO0XMgEtLcmceTSUL5jficWnPIPxktor kSsnEtPYDU+XeFpOPaBdDkC/ZFTTThtDLU5lDNy9ztBU4oJjHgZ6CBk6AcoBCxKg9nG5 I8Ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gNlfncScxDREAT7VjTEXAFzdaeKYbTqQ4JYCBMZ7gaA=; b=MtBwLWI/DafV5Hz5JONLOiaaUXyxJ6Sj2kaEfPBjmrmUJmQHfmXv0381l9hnwLRSDg z4vsdZN2J4VMWVOb2gzn+hSFvTjLPo5qiPb3KwTdhFefHqo2RNU0Dft77htW2QgXnUa9 fTyIsABM8KL8wrCadts14G3a1cpuAIWlL9Eme4IwabEeyq8YopV43P0Dg2kZfW2aJO2x /6AlePFJ+Wkw16191bZ6xW7bg1y7J42Ku5Io1EUUUYC6WDsMepEAtEmP87PwcreSOhMd GPP04FrDSuQomfUiA8i4xyMRriVqGmuvdxVkgeEAMTNP02xbLl0NHxnoxwJ/QcPRzY7G /maw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nr9Gk8pF; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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A mispredicted conditional call to set_fs could result in the wrong addr_limit being forwarded under speculation to a subsequent access_ok check, potentially forming part of a spectre-v1 attack using uaccess routines. This patch prevents this forwarding from taking place, but putting heavy barriers in set_fs after writing the addr_limit. Reviewed-by: Mark Rutland Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/uaccess.h | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b Reviewed-by: Mark Rutland [v4.4 backport] diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 75363d723262..fc11c50af558 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -62,6 +62,13 @@ extern int fixup_exception(struct pt_regs *regs); static inline void set_fs(mm_segment_t fs) { current_thread_info()->addr_limit = fs; + + /* + * Prevent a mispredicted conditional call to set_fs from forwarding + * the wrong address limit to access_ok under speculation. + */ + dsb(nsh); + isb(); } #define segment_eq(a, b) ((a) == (b)) From patchwork Thu Aug 29 11:33:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172585 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2091249ily; Thu, 29 Aug 2019 04:35:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqyeUknwIRrWCFI0S7IEQ6OT2BMA4AP3DTG2VMKySSUL5+RemFA7evGDxedyJ+fugHpgrav4 X-Received: by 2002:a17:902:e686:: with SMTP id cn6mr9528487plb.12.1567078515583; Thu, 29 Aug 2019 04:35:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078515; cv=none; d=google.com; s=arc-20160816; b=B+n05wpgYpu5/COEqJ6VcQmV3ASLxIN0QldD5QH0ZgHqPsbHCNXgShgXBPirWMX1p+ oiy6enQcWBkKQlOdWbUKTPcmLpcqZxA0/WlDf0xPOYXrS6mylhLH6cY+MQPDlh82OxL5 FvTKDdTSjjv9p2G/oQO5k8oQwnpBWUr8cVy2vJJMSg9rTqKHjUpXJTIGp4T0XxUnsKfM FlnIa/NH9ElInfsn3R6svqAQ/VTa7BcvOjNFVpuOZPZTt7Ev6AFTGnKjGs/ZhHQEOgjj wmRu0sM9yGsOLySnKIYVDwZT2HE96x46Z7D7cM0u7JdV81+BNLRLrGJQCHTHhC5UlBr8 OEzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Lt3w372XAiP2T5A3AE8p2nBAFVuCKsgxbI6J0UJSdP8=; b=NVTs1r6WppNFUKg8/4jmIT1rRMWgdVIyrw4k9axcaXEdeyk6iLtXU4YRmqGVPEzMHG UyeA3kerToL1wI4/PZfPxKAiWOQQdD8XQxan1yAzhUUe8Z8h6rBT2l7WDCGDZYsOC2Tw gSjWSFXlt70pl+sbfs+7OjSmRXl+eDwscBp8jQm63Mcg5FOFN6sgeuGsIJq4KAUGOE0S CWIskpCzh2dagogHrBeQ/vmosdYK+815u3rUf/FnT3bjG1V9PDjr6S+EUKjzhG/OLZZn MUSgv2Y5br0Y0a0/VHYrTKaz6qecCYwtxO9lmAdeBTKcdJpJdV8uKWJIRf5XPG45hC2r zyNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=w34Lfs1Q; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h13si1698624plr.12.2019.08.29.04.35.15; Thu, 29 Aug 2019 04:35:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=w34Lfs1Q; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727142AbfH2LfO (ORCPT + 14 others); Thu, 29 Aug 2019 07:35:14 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:35774 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727073AbfH2LfO (ORCPT ); Thu, 29 Aug 2019 07:35:14 -0400 Received: by mail-pg1-f196.google.com with SMTP id n4so1457053pgv.2 for ; Thu, 29 Aug 2019 04:35:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Lt3w372XAiP2T5A3AE8p2nBAFVuCKsgxbI6J0UJSdP8=; b=w34Lfs1Qqs58LGmtolXD4m8NuERCbaTGl+FkcIHv817QZ4KWsO2vTcuI6Mx2gTcM4Q 3bKnw0mvesmQ+NPRMoZNsIDSREQdQV7hdSNJo0lpexFV/SG7ii/cwDMH7lxzQyN6Q2lK RBJ5fBWK47IUN/p/NIwZqvWAKE/F4fxxRF3JK4AfHAz71RLUaM4IH20p5z0mB1g9sPAc YD76t/u7pLj1CF3JvTIl2F3NKZ5zIqzHM8aCE8cT1lgp1x5n0RxvGLtBOJYnw3dS/V2D 6YNsG3i/dJHFutF8HbVNmcfKrNF1iEOMIpW0UeuPYopUkDjxPDLmzAokpEDXFxNkimum HBpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Lt3w372XAiP2T5A3AE8p2nBAFVuCKsgxbI6J0UJSdP8=; b=DxjuxZyFH9NcmCbfcN3eBXmuNJLrJGUqlaFhUKJSiYF3YNjoKUZ4vaAI0eTmh8xNa9 Clh8PRE123oHPZk0GH3K5WG4EN289P8droEdVeYfe6Kv2quXCKIIjiGbcyXD0fFgp8Qd PPRwZWsqrKCvhPmfkX0aIJNK4s82ZbblGUaqaGlmAR4uGriQi2Lh7M0nTGNW8tTPo8yv IQK1mZyukXWlSIorjW3KY0DBnMCMRneAejvLu7Gs3Y5LGwtelaV0MM/uevHVZW3K4ImN eKS+JTFKwtTaf2vVNJJqREHopJ2Py7yidugxW1EwU6XRIVlnZiSyqsDL5+fo2ZQwwZsF 0slQ== X-Gm-Message-State: APjAAAVxD5WTMlZAeYA2KsKrUjMXKZYM5JyHhj6mgdgsEN0DpBekL4ym RR7qkQw1xZeE7D1n2dR77oUKhW9Ph10= X-Received: by 2002:a62:db43:: with SMTP id f64mr11200661pfg.38.1567078513287; Thu, 29 Aug 2019 04:35:13 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id u69sm1878521pgu.77.2019.08.29.04.35.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:35:12 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 08/44] arm64: uaccess: Don't bother eliding access_ok checks in __{get, put}_user Date: Thu, 29 Aug 2019 17:03:53 +0530 Message-Id: <40fe1d91c9cd8d78ae952b821185681621f92b10.1567077734.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit 84624087dd7e3b482b7b11c170ebc1f329b3a218 upstream. access_ok isn't an expensive operation once the addr_limit for the current thread has been loaded into the cache. Given that the initial access_ok check preceding a sequence of __{get,put}_user operations will take the brunt of the miss, we can make the __* variants identical to the full-fat versions, which brings with it the benefits of address masking. The likely cost in these sequences will be from toggling PAN/UAO, which we can address later by implementing the *_unsafe versions. Reviewed-by: Robin Murphy Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: Fixed conflicts around {__get_user|__put_user}_unaligned macros ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/uaccess.h | 62 ++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 26 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b Reviewed-by: Mark Rutland [v4.4 backport] diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index fc11c50af558..a34324436ce1 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -200,30 +200,35 @@ do { \ CONFIG_ARM64_PAN)); \ } while (0) -#define __get_user(x, ptr) \ +#define __get_user_check(x, ptr, err) \ ({ \ - int __gu_err = 0; \ - __get_user_err((x), (ptr), __gu_err); \ - __gu_err; \ + __typeof__(*(ptr)) __user *__p = (ptr); \ + might_fault(); \ + if (access_ok(VERIFY_READ, __p, sizeof(*__p))) { \ + __p = uaccess_mask_ptr(__p); \ + __get_user_err((x), __p, (err)); \ + } else { \ + (x) = 0; (err) = -EFAULT; \ + } \ }) #define __get_user_error(x, ptr, err) \ ({ \ - __get_user_err((x), (ptr), (err)); \ + __get_user_check((x), (ptr), (err)); \ (void)0; \ }) -#define __get_user_unaligned __get_user - -#define get_user(x, ptr) \ +#define __get_user(x, ptr) \ ({ \ - __typeof__(*(ptr)) __user *__p = (ptr); \ - might_fault(); \ - access_ok(VERIFY_READ, __p, sizeof(*__p)) ? \ - __p = uaccess_mask_ptr(__p), __get_user((x), __p) : \ - ((x) = 0, -EFAULT); \ + int __gu_err = 0; \ + __get_user_check((x), (ptr), __gu_err); \ + __gu_err; \ }) +#define __get_user_unaligned __get_user + +#define get_user __get_user + #define __put_user_asm(instr, reg, x, addr, err) \ asm volatile( \ "1: " instr " " reg "1, [%2]\n" \ @@ -266,30 +271,35 @@ do { \ CONFIG_ARM64_PAN)); \ } while (0) -#define __put_user(x, ptr) \ +#define __put_user_check(x, ptr, err) \ ({ \ - int __pu_err = 0; \ - __put_user_err((x), (ptr), __pu_err); \ - __pu_err; \ + __typeof__(*(ptr)) __user *__p = (ptr); \ + might_fault(); \ + if (access_ok(VERIFY_WRITE, __p, sizeof(*__p))) { \ + __p = uaccess_mask_ptr(__p); \ + __put_user_err((x), __p, (err)); \ + } else { \ + (err) = -EFAULT; \ + } \ }) #define __put_user_error(x, ptr, err) \ ({ \ - __put_user_err((x), (ptr), (err)); \ + __put_user_check((x), (ptr), (err)); \ (void)0; \ }) -#define __put_user_unaligned __put_user - -#define put_user(x, ptr) \ +#define __put_user(x, ptr) \ ({ \ - __typeof__(*(ptr)) __user *__p = (ptr); \ - might_fault(); \ - access_ok(VERIFY_WRITE, __p, sizeof(*__p)) ? \ - __p = uaccess_mask_ptr(__p), __put_user((x), __p) : \ - -EFAULT; \ + int __pu_err = 0; \ + __put_user_check((x), (ptr), __pu_err); \ + __pu_err; \ }) +#define __put_user_unaligned __put_user + +#define put_user __put_user + extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n); extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n); extern unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n); From patchwork Thu Aug 29 11:33:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172586 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2091285ily; Thu, 29 Aug 2019 04:35:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqzh+aIrWBEnzkD8uUuQ+eooMZ/+w7HzqCFyFvqxJsbbsj2CHh9E3yc6RofyRpxzN1eshYmG X-Received: by 2002:a63:e213:: with SMTP id q19mr7820654pgh.180.1567078517898; Thu, 29 Aug 2019 04:35:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078517; cv=none; d=google.com; s=arc-20160816; b=WScoDR7WFpv6x3YTH7BS310TRSSMw1x1rvHuecLAJbS5N4TM+lr+NolLiixsrm3/1/ VP9vLWQMqYsjL892W49WbF04r6zgRL14i+bxEIuP7tRncYWFu42utRM0HLOsKQzFjsO4 w3RVAPPVdHTtNioC5oW3lhnALEE4IMzaOrxIDTuPlRo8RQZC5YQh2niZ2bWQkUFghbJf xBlmnqILMh7CU65q5nd2osewKKa03dPnWgiBQTIoSf/BRdbfKKSdWe+wZKOInY2q9PWI AdX1/hdUSXmAIzd4KO7isyhP7ALeTxw1OOI6KR4FptYMGyxXWhtzY2jHOzbX9vBxeJR9 f0QQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+i1PP70VM4gp+yGXoK79tVzWNeTCN5YHgyu+1fomQgA=; b=d3JU21bxexJsCzYBfiAR+rx+GXHalNUBHwuSh0M9YIOEXDOTH79a2MpN2IW84HWUIk SM5ealrzXw2Ak2Z9AIV781eRP8lSx9ZuBBNAjJ7v4+rjZU5Bc0Wh3LFI4cxEfZUIp4Rg MOve/WTpUulIR7H49yc4wSLBHCQPkKnNcA+ir+XTwenTT10nLLa66Q+0kbbq99086qH1 +zKYbAMNm4pJz0B4O3DiG426e8JSZ8TmTKWzeFzOtCTx4t5AMgOD99oLRMrImY11H7c8 9y5ZoyGnpivjr0HGon4wyik9W/iR9Nw4JcLGy6EMUQMmZWPradAZbpOlGlHv4S97mrpk od5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VUGv1GtX; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Memory access coded in an assembly won't be seen by KASAN as a compiler can instrument only C code. Add kasan_check_[read,write]() API which is going to be used to check a certain memory range. Link: http://lkml.kernel.org/r/1462538722-1574-3-git-send-email-aryabinin@virtuozzo.com Signed-off-by: Andrey Ryabinin Acked-by: Alexander Potapenko Cc: Dmitry Vyukov Cc: Ingo Molnar Cc: "H. Peter Anvin" Cc: Thomas Gleixner Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds [ v4.4: Fixed MAINTAINERS conflict and added whole kasan entry. Drop 4th argument to check_memory_region(). ] Signed-off-by: Viresh Kumar --- MAINTAINERS | 14 ++++++++++++++ include/linux/kasan-checks.h | 12 ++++++++++++ mm/kasan/kasan.c | 12 ++++++++++++ 3 files changed, 38 insertions(+) create mode 100644 include/linux/kasan-checks.h -- 2.21.0.rc0.269.g1a574e7a288b Reviewed-by: Mark Rutland [v4.4 backport] diff --git a/MAINTAINERS b/MAINTAINERS index f4d4a5544dc1..2a8826732967 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5982,6 +5982,20 @@ S: Maintained F: Documentation/hwmon/k8temp F: drivers/hwmon/k8temp.c +KASAN +M: Andrey Ryabinin +R: Alexander Potapenko +R: Dmitry Vyukov +L: kasan-dev@googlegroups.com +S: Maintained +F: arch/*/include/asm/kasan.h +F: arch/*/mm/kasan_init* +F: Documentation/kasan.txt +F: include/linux/kasan*.h +F: lib/test_kasan.c +F: mm/kasan/ +F: scripts/Makefile.kasan + KCONFIG M: "Yann E. MORIN" L: linux-kbuild@vger.kernel.org diff --git a/include/linux/kasan-checks.h b/include/linux/kasan-checks.h new file mode 100644 index 000000000000..b7f8aced7870 --- /dev/null +++ b/include/linux/kasan-checks.h @@ -0,0 +1,12 @@ +#ifndef _LINUX_KASAN_CHECKS_H +#define _LINUX_KASAN_CHECKS_H + +#ifdef CONFIG_KASAN +void kasan_check_read(const void *p, unsigned int size); +void kasan_check_write(const void *p, unsigned int size); +#else +static inline void kasan_check_read(const void *p, unsigned int size) { } +static inline void kasan_check_write(const void *p, unsigned int size) { } +#endif + +#endif diff --git a/mm/kasan/kasan.c b/mm/kasan/kasan.c index b7397b459960..1cdcab0c976a 100644 --- a/mm/kasan/kasan.c +++ b/mm/kasan/kasan.c @@ -274,6 +274,18 @@ static __always_inline void check_memory_region(unsigned long addr, void __asan_loadN(unsigned long addr, size_t size); void __asan_storeN(unsigned long addr, size_t size); +void kasan_check_read(const void *p, unsigned int size) +{ + check_memory_region((unsigned long)p, size, false); +} +EXPORT_SYMBOL(kasan_check_read); + +void kasan_check_write(const void *p, unsigned int size) +{ + check_memory_region((unsigned long)p, size, true); +} +EXPORT_SYMBOL(kasan_check_write); + #undef memset void *memset(void *addr, int c, size_t len) { From patchwork Thu Aug 29 11:33:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172587 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2091342ily; Thu, 29 Aug 2019 04:35:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqxl/GyQFlJprudK8WNWoZkW7y+6gBa7m1fq+GC9Px7MGSBYvipzHODVMbM7JMWYTe1G0vHi X-Received: by 2002:a63:1:: with SMTP id 1mr7789045pga.162.1567078520450; Thu, 29 Aug 2019 04:35:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078520; cv=none; d=google.com; s=arc-20160816; b=oaRucWAgCz+mcyn5P6IY7E2dQCwjhvtwbRTusIbTb8cCX9KA3g583tpofWAz8c+LHf RwidADM+YXQaYYYLUOos8kEuw8bGHnnXdOHYMa6EnXJLGnvloy2kYW4S66hGE5ZumfWX txGJAy3dWLithtaMQkUXjJSUxXrUbHo4XH8UlwAJfpR+l9dn8UqwTTHsl/XzrjSteTfj 8M5xU8xFlYLzuZeAvsBxX8NRqGHp/fml7Y9TcH2kvM6TIDHUtg20pz3BtmHJqvrfxsdj dqXkmkYrqB7tqTKsH5IiAKjiBqVwfTOj/qjq9e5hGPENjPuRnOLnvt/RX1i5dSBPUAWR 07Hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=t0RCljGeD4tzeQJetzsGgy9r5JSUQjn098IzF6ZdUW0=; b=rM4OBaXY9e1IVYkQEahBSMid/RNrxidLqVzpwx/tcQHG1/JBlk1MiL4J5XDvJhHJI5 FFiFI72j8js4A/swnFQ+0fXugZhSU5rZdZ8F3mr5+TAiBDeMO/OCoKl5T1txYOMyQk32 PaAp+c8sV+QGPqGgBkV79IwfUPk6TTHoIfFIBpj5PG9SXR2ltSAiKWhdrmYDjs1v8lcM FwB7hcRE/JVF4KS8p5yNgS754jGit32ojd7iU0zV/ImC0bOOxl7DlketrCeuxr/oO670 z+7Ha0dBG6vLi7eCHBpDmgWoC42Asebemx9VPPzEqzGYjF0f9yN3lJD/w5c7bD5Usvo7 I7Ag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YQZAocWE; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The upstream commit 1771c6e1a567ea0ba2cccc0a4ffe68a1419fd8ef ("x86/kasan: instrument user memory access API") added KASAN instrument to x86 user memory access API, so added such instrument to ARM64 too. Define __copy_to/from_user in C in order to add kasan_check_read/write call, rename assembly implementation to __arch_copy_to/from_user. Tested by test_kasan module. Acked-by: Andrey Ryabinin Reviewed-by: Mark Rutland Tested-by: Mark Rutland Signed-off-by: Yang Shi Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/uaccess.h | 25 +++++++++++++++++++++---- arch/arm64/kernel/arm64ksyms.c | 4 ++-- arch/arm64/lib/copy_from_user.S | 4 ++-- arch/arm64/lib/copy_to_user.S | 4 ++-- 4 files changed, 27 insertions(+), 10 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b Reviewed-by: Mark Rutland [v4.4 backport] diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index a34324436ce1..693a0d784534 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -22,6 +22,7 @@ * User space memory access functions */ #include +#include #include #include @@ -300,15 +301,29 @@ do { \ #define put_user __put_user -extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n); -extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n); +extern unsigned long __must_check __arch_copy_from_user(void *to, const void __user *from, unsigned long n); +extern unsigned long __must_check __arch_copy_to_user(void __user *to, const void *from, unsigned long n); extern unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n); extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n); +static inline unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n) +{ + kasan_check_write(to, n); + return __arch_copy_from_user(to, from, n); +} + +static inline unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n) +{ + kasan_check_read(from, n); + return __arch_copy_to_user(to, from, n); +} + static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n) { + kasan_check_write(to, n); + if (access_ok(VERIFY_READ, from, n)) - n = __copy_from_user(to, from, n); + n = __arch_copy_from_user(to, from, n); else /* security hole - plug it */ memset(to, 0, n); return n; @@ -316,8 +331,10 @@ static inline unsigned long __must_check copy_from_user(void *to, const void __u static inline unsigned long __must_check copy_to_user(void __user *to, const void *from, unsigned long n) { + kasan_check_read(from, n); + if (access_ok(VERIFY_WRITE, to, n)) - n = __copy_to_user(to, from, n); + n = __arch_copy_to_user(to, from, n); return n; } diff --git a/arch/arm64/kernel/arm64ksyms.c b/arch/arm64/kernel/arm64ksyms.c index 3b6d8cc9dfe0..c654df05b7d7 100644 --- a/arch/arm64/kernel/arm64ksyms.c +++ b/arch/arm64/kernel/arm64ksyms.c @@ -33,8 +33,8 @@ EXPORT_SYMBOL(copy_page); EXPORT_SYMBOL(clear_page); /* user mem (segment) */ -EXPORT_SYMBOL(__copy_from_user); -EXPORT_SYMBOL(__copy_to_user); +EXPORT_SYMBOL(__arch_copy_from_user); +EXPORT_SYMBOL(__arch_copy_to_user); EXPORT_SYMBOL(__clear_user); EXPORT_SYMBOL(__copy_in_user); diff --git a/arch/arm64/lib/copy_from_user.S b/arch/arm64/lib/copy_from_user.S index 4699cd74f87e..281e75db899a 100644 --- a/arch/arm64/lib/copy_from_user.S +++ b/arch/arm64/lib/copy_from_user.S @@ -66,7 +66,7 @@ .endm end .req x5 -ENTRY(__copy_from_user) +ENTRY(__arch_copy_from_user) ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(0)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) add end, x0, x2 @@ -75,7 +75,7 @@ ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(1)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) mov x0, #0 // Nothing to copy ret -ENDPROC(__copy_from_user) +ENDPROC(__arch_copy_from_user) .section .fixup,"ax" .align 2 diff --git a/arch/arm64/lib/copy_to_user.S b/arch/arm64/lib/copy_to_user.S index 7512bbbc07ac..db4d187de61f 100644 --- a/arch/arm64/lib/copy_to_user.S +++ b/arch/arm64/lib/copy_to_user.S @@ -65,7 +65,7 @@ .endm end .req x5 -ENTRY(__copy_to_user) +ENTRY(__arch_copy_to_user) ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(0)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) add end, x0, x2 @@ -74,7 +74,7 @@ ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(1)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) mov x0, #0 ret -ENDPROC(__copy_to_user) +ENDPROC(__arch_copy_to_user) .section .fixup,"ax" .align 2 From patchwork Thu Aug 29 11:33:56 2019 Content-Type: text/plain; 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Like we've done for get_user and put_user, ensure that user pointers are masked before invoking the underlying __arch_{clear,copy_*}_user operations. Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: fixup for v4.4 style uaccess primitives ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/uaccess.h | 18 ++++++++++-------- arch/arm64/kernel/arm64ksyms.c | 4 ++-- arch/arm64/lib/clear_user.S | 6 +++--- arch/arm64/lib/copy_in_user.S | 4 ++-- 4 files changed, 17 insertions(+), 15 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b Reviewed-by: Mark Rutland [v4.4 backport] diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 693a0d784534..f2f5a152f372 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -303,19 +303,18 @@ do { \ extern unsigned long __must_check __arch_copy_from_user(void *to, const void __user *from, unsigned long n); extern unsigned long __must_check __arch_copy_to_user(void __user *to, const void *from, unsigned long n); -extern unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n); -extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n); +extern unsigned long __must_check __arch_copy_in_user(void __user *to, const void __user *from, unsigned long n); static inline unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n) { kasan_check_write(to, n); - return __arch_copy_from_user(to, from, n); + return __arch_copy_from_user(to, __uaccess_mask_ptr(from), n); } static inline unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n) { kasan_check_read(from, n); - return __arch_copy_to_user(to, from, n); + return __arch_copy_to_user(__uaccess_mask_ptr(to), from, n); } static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n) @@ -338,22 +337,25 @@ static inline unsigned long __must_check copy_to_user(void __user *to, const voi return n; } -static inline unsigned long __must_check copy_in_user(void __user *to, const void __user *from, unsigned long n) +static inline unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n) { if (access_ok(VERIFY_READ, from, n) && access_ok(VERIFY_WRITE, to, n)) - n = __copy_in_user(to, from, n); + n = __arch_copy_in_user(__uaccess_mask_ptr(to), __uaccess_mask_ptr(from), n); return n; } +#define copy_in_user __copy_in_user #define __copy_to_user_inatomic __copy_to_user #define __copy_from_user_inatomic __copy_from_user -static inline unsigned long __must_check clear_user(void __user *to, unsigned long n) +extern unsigned long __must_check __arch_clear_user(void __user *to, unsigned long n); +static inline unsigned long __must_check __clear_user(void __user *to, unsigned long n) { if (access_ok(VERIFY_WRITE, to, n)) - n = __clear_user(__uaccess_mask_ptr(to), n); + n = __arch_clear_user(__uaccess_mask_ptr(to), n); return n; } +#define clear_user __clear_user extern long strncpy_from_user(char *dest, const char __user *src, long count); diff --git a/arch/arm64/kernel/arm64ksyms.c b/arch/arm64/kernel/arm64ksyms.c index c654df05b7d7..abe4e0984dbb 100644 --- a/arch/arm64/kernel/arm64ksyms.c +++ b/arch/arm64/kernel/arm64ksyms.c @@ -35,8 +35,8 @@ EXPORT_SYMBOL(clear_page); /* user mem (segment) */ EXPORT_SYMBOL(__arch_copy_from_user); EXPORT_SYMBOL(__arch_copy_to_user); -EXPORT_SYMBOL(__clear_user); -EXPORT_SYMBOL(__copy_in_user); +EXPORT_SYMBOL(__arch_clear_user); +EXPORT_SYMBOL(__arch_copy_in_user); /* physical memory */ EXPORT_SYMBOL(memstart_addr); diff --git a/arch/arm64/lib/clear_user.S b/arch/arm64/lib/clear_user.S index a9723c71c52b..fc6bb0f83511 100644 --- a/arch/arm64/lib/clear_user.S +++ b/arch/arm64/lib/clear_user.S @@ -24,7 +24,7 @@ .text -/* Prototype: int __clear_user(void *addr, size_t sz) +/* Prototype: int __arch_clear_user(void *addr, size_t sz) * Purpose : clear some user memory * Params : addr - user memory address to clear * : sz - number of bytes to clear @@ -32,7 +32,7 @@ * * Alignment fixed up by hardware. */ -ENTRY(__clear_user) +ENTRY(__arch_clear_user) ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(0)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) mov x2, x1 // save the size for fixup return @@ -57,7 +57,7 @@ USER(9f, strb wzr, [x0] ) ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(1)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) ret -ENDPROC(__clear_user) +ENDPROC(__arch_clear_user) .section .fixup,"ax" .align 2 diff --git a/arch/arm64/lib/copy_in_user.S b/arch/arm64/lib/copy_in_user.S index 81c8fc93c100..0219aa85b3cc 100644 --- a/arch/arm64/lib/copy_in_user.S +++ b/arch/arm64/lib/copy_in_user.S @@ -67,7 +67,7 @@ .endm end .req x5 -ENTRY(__copy_in_user) +ENTRY(__arch_copy_in_user) ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(0)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) add end, x0, x2 @@ -76,7 +76,7 @@ ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(1)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) mov x0, #0 ret -ENDPROC(__copy_in_user) +ENDPROC(__arch_copy_in_user) .section .fixup,"ax" .align 2 From patchwork Thu Aug 29 11:33:57 2019 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id b30si1720301pla.299.2019.08.29.04.35.26; Thu, 29 Aug 2019 04:35:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Gta/BjHJ"; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727503AbfH2LfZ (ORCPT + 14 others); Thu, 29 Aug 2019 07:35:25 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:45718 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727474AbfH2LfZ (ORCPT ); Thu, 29 Aug 2019 07:35:25 -0400 Received: by mail-pl1-f194.google.com with SMTP id y8so1436315plr.12 for ; Thu, 29 Aug 2019 04:35:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/kfHaZYBMHfOrWZM24aWUbS5m2tlkmGASsL26R9/1y0=; b=Gta/BjHJoeHx/0jnh1mD82z3khHO6OWus+AnqVK3jTMQburxYF8f+9Z5B3h2u7q1bT 84dbThD5qRne9UCWmSA+BYv0pk23FljWmIz76uW6/Ow8fWPVKhgag2RjQ6C4kBvCWQo9 +4QnJy6S6Fy5mLK5goPYNl7hYK4g/iMvBFs5tQeZTDY7DzYSBAIBNbPY3jKdVZb0GX1H +cMY5BX/5+4HCogaMqFgyON4hoe5hlRVX4WX/ekBlqCc9oWfPxiXwJI87eJ5Nd7Kz2Nn VkDV29OAc3yUJ8RMRXiQii5iSlSIIW1kucniCtdKxTkhYG+t2ECVSJf8APZjLZZk1x6V 4kaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/kfHaZYBMHfOrWZM24aWUbS5m2tlkmGASsL26R9/1y0=; b=C94XcVjB5aC91LVgcwCufOKSxcEBiArBexUZUv6xChoQ6YsaRie+I4oD1rHTnogujE x3a0BsTwGmJ7KRwGggzD3Vw6r/jwVEFcdV6z4LCdxXLvrIBSCn2XVAPJ8iNSkQHMl7Hn lFvHLJrFJAsUbIbE7PvOGXHevDOtvEuXMTjUG2x5iJOyQ+h11pmY+VrhGbRL6SyFJnEh Ez6IB9Ut+Pob+GXKOu0DDL7et6Hd35amI54l/sOXTexq938b88MK4bkhGzqP0QmFwpM1 IIHGFhLF2mcuTL/Qp9EOmbykF03kZ08J34NbSHNpB/RnoG7FKqfVufDMp1ZOK0k8muM/ SiwQ== X-Gm-Message-State: APjAAAWGUPXbrVHVymmbvwMG3ZSFtfQDnsb8f81NQOCzMIOokYYEOpKB K6wlzUDqcNpmRdhYDPtGK2ay0XQp0Zk= X-Received: by 2002:a17:902:7c16:: with SMTP id x22mr6330064pll.234.1567078523996; Thu, 29 Aug 2019 04:35:23 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id y194sm2790098pfg.116.2019.08.29.04.35.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:35:23 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 12/44] arm64: cpufeature: Test 'matches' pointer to find the end of the list Date: Thu, 29 Aug 2019 17:03:57 +0530 Message-Id: <617ad445043f040c5ab986b9620b2ba7847b561e.1567077734.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: James Morse commit 644c2ae198412c956700e55a2acf80b2541f6aa5 upstream. CPU feature code uses the desc field as a test to find the end of the list, this means every entry must have a description. This generates noise for entries in the list that aren't really features, but combinations of them. e.g. > CPU features: detected feature: Privileged Access Never > CPU features: detected feature: PAN and not UAO These combination features are needed for corner cases with alternatives, where cpu features interact. Change all walkers of the arm64_features[] and arm64_hwcaps[] lists to test 'matches' not 'desc', and only print 'desc' if it is non-NULL. Signed-off-by: James Morse Reviewed-by : Suzuki K Poulose Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/cpufeature.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c1eddc07d996..bdb4cd9ffccf 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -744,7 +744,7 @@ static void setup_cpu_hwcaps(void) int i; const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps; - for (i = 0; hwcaps[i].desc; i++) + for (i = 0; hwcaps[i].matches; i++) if (hwcaps[i].matches(&hwcaps[i])) cap_set_hwcap(&hwcaps[i]); } @@ -754,11 +754,11 @@ void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, { int i; - for (i = 0; caps[i].desc; i++) { + for (i = 0; caps[i].matches; i++) { if (!caps[i].matches(&caps[i])) continue; - if (!cpus_have_cap(caps[i].capability)) + if (!cpus_have_cap(caps[i].capability) && caps[i].desc) pr_info("%s %s\n", info, caps[i].desc); cpus_set_cap(caps[i].capability); } @@ -772,7 +772,7 @@ static void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) { int i; - for (i = 0; caps[i].desc; i++) + for (i = 0; caps[i].matches; i++) if (caps[i].enable && cpus_have_cap(caps[i].capability)) /* * Use stop_machine() as it schedules the work allowing @@ -884,7 +884,7 @@ void verify_local_cpu_capabilities(void) return; caps = arm64_features; - for (i = 0; caps[i].desc; i++) { + for (i = 0; caps[i].matches; i++) { if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg) continue; /* @@ -897,7 +897,7 @@ void verify_local_cpu_capabilities(void) caps[i].enable(NULL); } - for (i = 0, caps = arm64_hwcaps; caps[i].desc; i++) { + for (i = 0, caps = arm64_hwcaps; caps[i].matches; i++) { if (!cpus_have_hwcap(&caps[i])) continue; if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) From patchwork Thu Aug 29 11:33:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172590 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2091518ily; Thu, 29 Aug 2019 04:35:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqyFlCjC5pf8I2HdH8hXWpMnuDSI1k5Hmh8FsYW1kXjnwY3zQL7PQaSbcG8YnKqUS4lCbd1W X-Received: by 2002:a65:44cb:: with SMTP id g11mr5490228pgs.265.1567078529386; Thu, 29 Aug 2019 04:35:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078529; cv=none; d=google.com; s=arc-20160816; b=gv5jAGag+YCyisP3T7PR9GI1yRxZGADHwtH8myUe3N0H5WU/kJfm7N/UfzyY8DpcdY GGTsSErDacPiiZpM1Dl9CDGiNcqxl8MQO3mg1WFdTaargyqv6yXe7GB0+2CcJyJu6d7Z I3RxwrSGZZCvFTwqgpbEPZiVy0PTUY7RlR1cg1l8yiG9U02qpF0Eww24BlzAjPynvrRn Clo9ueRujuVkCKxWoIXq9Jan6nCS3dYTYSxF9VZCbsXXEdJxhXtWR0oi/FlW8Va9Nl9B 6MPoQB2ydTg2WeToqDcsaSsWgTrsuPsNphD1VA8YnQ2LmbcoUbvu+3CBfdpcLYeUmR3v 613A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+8jS5wU9g41nb7lUYf6O/ux0jWphtxOIXXxsA7/oFkw=; b=XMRyQG8flGSX83vIIN1g4AsAOr5+1mJbejwx8QhvT+67fXudMTachSQx2fVmSnIbv7 kjLsAxymDqZViMaDM/imjQYHLtJo0VYgUUhFpWhEk2N5QxgeGLvmQKfIxYrSHZ+Xvl6H o6qH6BzecijHCyCCwJnwfZlaI2zpKFoeVJzPmCo8TVr34kh6nYkIYHOS6vl9+TLjfgj0 qnrez8jIJJsh+MF7oWxP3CUk26iigY8nCrl8m3m8Tb4z1X8Wz0JYlqAGvq2rktg9LMdz ofIWRYTUPsRxgb4+DAWfUtwt/YOmpDPElIF9cFDmo+eUK7/GRtuE52+a4WLEm8LSbY6A 04lA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SlQ7dAyL; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Add scope parameter to the arm64_cpu_capabilities::matches(), so that this can be reused for checking the capability on a given CPU vs the system wide. The system uses the default scope associated with the capability for initialising the CPU_HWCAPs and ELF_HWCAPs. Cc: James Morse Cc: Marc Zyngier Cc: Andre Przywara Cc: Will Deacon Reviewed-by: Catalin Marinas Signed-off-by: Suzuki K Poulose Signed-off-by: Will Deacon [ v4.4: Changes made according to 4.4 codebase ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/cpufeature.h | 9 ++- arch/arm64/kernel/cpu_errata.c | 5 +- arch/arm64/kernel/cpufeature.c | 105 +++++++++++++++------------- 3 files changed, 70 insertions(+), 49 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index ad83c245781c..4c31e14c0f0e 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -74,10 +74,17 @@ struct arm64_ftr_reg { struct arm64_ftr_bits *ftr_bits; }; +/* scope of capability check */ +enum { + SCOPE_SYSTEM, + SCOPE_LOCAL_CPU, +}; + struct arm64_cpu_capabilities { const char *desc; u16 capability; - bool (*matches)(const struct arm64_cpu_capabilities *); + int def_scope; /* default scope */ + bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope); int (*enable)(void *); /* Called on all active CPUs */ union { struct { /* To be used for erratum handling only */ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index a3e846a28b05..0971d80d3623 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -29,10 +29,12 @@ MIDR_ARCHITECTURE_MASK) static bool __maybe_unused -is_affected_midr_range(const struct arm64_cpu_capabilities *entry) +is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) { u32 midr = read_cpuid_id(); + WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); + if ((midr & CPU_MODEL_MASK) != entry->midr_model) return false; @@ -42,6 +44,7 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry) } #define MIDR_RANGE(model, min, max) \ + .def_scope = SCOPE_LOCAL_CPU, \ .matches = is_affected_midr_range, \ .midr_model = model, \ .midr_range_min = min, \ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index bdb4cd9ffccf..d0c82bc02de4 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -589,6 +589,48 @@ u64 read_system_reg(u32 id) return regp->sys_val; } +/* + * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated. + * Read the system register on the current CPU + */ +static u64 __raw_read_system_reg(u32 sys_id) +{ + switch (sys_id) { + case SYS_ID_PFR0_EL1: return (u64)read_cpuid(ID_PFR0_EL1); + case SYS_ID_PFR1_EL1: return (u64)read_cpuid(ID_PFR1_EL1); + case SYS_ID_DFR0_EL1: return (u64)read_cpuid(ID_DFR0_EL1); + case SYS_ID_MMFR0_EL1: return (u64)read_cpuid(ID_MMFR0_EL1); + case SYS_ID_MMFR1_EL1: return (u64)read_cpuid(ID_MMFR1_EL1); + case SYS_ID_MMFR2_EL1: return (u64)read_cpuid(ID_MMFR2_EL1); + case SYS_ID_MMFR3_EL1: return (u64)read_cpuid(ID_MMFR3_EL1); + case SYS_ID_ISAR0_EL1: return (u64)read_cpuid(ID_ISAR0_EL1); + case SYS_ID_ISAR1_EL1: return (u64)read_cpuid(ID_ISAR1_EL1); + case SYS_ID_ISAR2_EL1: return (u64)read_cpuid(ID_ISAR2_EL1); + case SYS_ID_ISAR3_EL1: return (u64)read_cpuid(ID_ISAR3_EL1); + case SYS_ID_ISAR4_EL1: return (u64)read_cpuid(ID_ISAR4_EL1); + case SYS_ID_ISAR5_EL1: return (u64)read_cpuid(ID_ISAR4_EL1); + case SYS_MVFR0_EL1: return (u64)read_cpuid(MVFR0_EL1); + case SYS_MVFR1_EL1: return (u64)read_cpuid(MVFR1_EL1); + case SYS_MVFR2_EL1: return (u64)read_cpuid(MVFR2_EL1); + + case SYS_ID_AA64PFR0_EL1: return (u64)read_cpuid(ID_AA64PFR0_EL1); + case SYS_ID_AA64PFR1_EL1: return (u64)read_cpuid(ID_AA64PFR0_EL1); + case SYS_ID_AA64DFR0_EL1: return (u64)read_cpuid(ID_AA64DFR0_EL1); + case SYS_ID_AA64DFR1_EL1: return (u64)read_cpuid(ID_AA64DFR0_EL1); + case SYS_ID_AA64MMFR0_EL1: return (u64)read_cpuid(ID_AA64MMFR0_EL1); + case SYS_ID_AA64MMFR1_EL1: return (u64)read_cpuid(ID_AA64MMFR1_EL1); + case SYS_ID_AA64ISAR0_EL1: return (u64)read_cpuid(ID_AA64ISAR0_EL1); + case SYS_ID_AA64ISAR1_EL1: return (u64)read_cpuid(ID_AA64ISAR1_EL1); + + case SYS_CNTFRQ_EL0: return (u64)read_cpuid(CNTFRQ_EL0); + case SYS_CTR_EL0: return (u64)read_cpuid(CTR_EL0); + case SYS_DCZID_EL0: return (u64)read_cpuid(DCZID_EL0); + default: + BUG(); + return 0; + } +} + #include static bool @@ -600,19 +642,24 @@ feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) } static bool -has_cpuid_feature(const struct arm64_cpu_capabilities *entry) +has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) { u64 val; - val = read_system_reg(entry->sys_reg); + WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); + if (scope == SCOPE_SYSTEM) + val = read_system_reg(entry->sys_reg); + else + val = __raw_read_system_reg(entry->sys_reg); + return feature_matches(val, entry); } -static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry) +static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) { bool has_sre; - if (!has_cpuid_feature(entry)) + if (!has_cpuid_feature(entry, scope)) return false; has_sre = gic_enable_sre(); @@ -627,6 +674,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "GIC system register CPU interface", .capability = ARM64_HAS_SYSREG_GIC_CPUIF, + .def_scope = SCOPE_SYSTEM, .matches = has_useable_gicv3_cpuif, .sys_reg = SYS_ID_AA64PFR0_EL1, .field_pos = ID_AA64PFR0_GIC_SHIFT, @@ -636,6 +684,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "Privileged Access Never", .capability = ARM64_HAS_PAN, + .def_scope = SCOPE_SYSTEM, .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64MMFR1_EL1, .field_pos = ID_AA64MMFR1_PAN_SHIFT, @@ -647,6 +696,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "LSE atomic instructions", .capability = ARM64_HAS_LSE_ATOMICS, + .def_scope = SCOPE_SYSTEM, .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64ISAR0_EL1, .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, @@ -656,6 +706,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "32-bit EL0 Support", .capability = ARM64_HAS_32BIT_EL0, + .def_scope = SCOPE_SYSTEM, .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64PFR0_EL1, .field_pos = ID_AA64PFR0_EL0_SHIFT, @@ -667,6 +718,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { #define HWCAP_CAP(reg, field, min_value, type, cap) \ { \ .desc = #cap, \ + .def_scope = SCOPE_SYSTEM, \ .matches = has_cpuid_feature, \ .sys_reg = reg, \ .field_pos = field, \ @@ -745,7 +797,7 @@ static void setup_cpu_hwcaps(void) const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps; for (i = 0; hwcaps[i].matches; i++) - if (hwcaps[i].matches(&hwcaps[i])) + if (hwcaps[i].matches(&hwcaps[i], hwcaps[i].def_scope)) cap_set_hwcap(&hwcaps[i]); } @@ -755,7 +807,7 @@ void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, int i; for (i = 0; caps[i].matches; i++) { - if (!caps[i].matches(&caps[i])) + if (!caps[i].matches(&caps[i], caps[i].def_scope)) continue; if (!cpus_have_cap(caps[i].capability) && caps[i].desc) @@ -800,47 +852,6 @@ static inline void set_sys_caps_initialised(void) sys_caps_initialised = true; } -/* - * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated. - */ -static u64 __raw_read_system_reg(u32 sys_id) -{ - switch (sys_id) { - case SYS_ID_PFR0_EL1: return (u64)read_cpuid(ID_PFR0_EL1); - case SYS_ID_PFR1_EL1: return (u64)read_cpuid(ID_PFR1_EL1); - case SYS_ID_DFR0_EL1: return (u64)read_cpuid(ID_DFR0_EL1); - case SYS_ID_MMFR0_EL1: return (u64)read_cpuid(ID_MMFR0_EL1); - case SYS_ID_MMFR1_EL1: return (u64)read_cpuid(ID_MMFR1_EL1); - case SYS_ID_MMFR2_EL1: return (u64)read_cpuid(ID_MMFR2_EL1); - case SYS_ID_MMFR3_EL1: return (u64)read_cpuid(ID_MMFR3_EL1); - case SYS_ID_ISAR0_EL1: return (u64)read_cpuid(ID_ISAR0_EL1); - case SYS_ID_ISAR1_EL1: return (u64)read_cpuid(ID_ISAR1_EL1); - case SYS_ID_ISAR2_EL1: return (u64)read_cpuid(ID_ISAR2_EL1); - case SYS_ID_ISAR3_EL1: return (u64)read_cpuid(ID_ISAR3_EL1); - case SYS_ID_ISAR4_EL1: return (u64)read_cpuid(ID_ISAR4_EL1); - case SYS_ID_ISAR5_EL1: return (u64)read_cpuid(ID_ISAR4_EL1); - case SYS_MVFR0_EL1: return (u64)read_cpuid(MVFR0_EL1); - case SYS_MVFR1_EL1: return (u64)read_cpuid(MVFR1_EL1); - case SYS_MVFR2_EL1: return (u64)read_cpuid(MVFR2_EL1); - - case SYS_ID_AA64PFR0_EL1: return (u64)read_cpuid(ID_AA64PFR0_EL1); - case SYS_ID_AA64PFR1_EL1: return (u64)read_cpuid(ID_AA64PFR0_EL1); - case SYS_ID_AA64DFR0_EL1: return (u64)read_cpuid(ID_AA64DFR0_EL1); - case SYS_ID_AA64DFR1_EL1: return (u64)read_cpuid(ID_AA64DFR0_EL1); - case SYS_ID_AA64MMFR0_EL1: return (u64)read_cpuid(ID_AA64MMFR0_EL1); - case SYS_ID_AA64MMFR1_EL1: return (u64)read_cpuid(ID_AA64MMFR1_EL1); - case SYS_ID_AA64ISAR0_EL1: return (u64)read_cpuid(ID_AA64ISAR0_EL1); - case SYS_ID_AA64ISAR1_EL1: return (u64)read_cpuid(ID_AA64ISAR1_EL1); - - case SYS_CNTFRQ_EL0: return (u64)read_cpuid(CNTFRQ_EL0); - case SYS_CTR_EL0: return (u64)read_cpuid(CTR_EL0); - case SYS_DCZID_EL0: return (u64)read_cpuid(DCZID_EL0); - default: - BUG(); - return 0; - } -} - /* * Park the CPU which doesn't have the capability as advertised * by the system. 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[209.132.180.67]) by mx.google.com with ESMTP id b30si1720301pla.299.2019.08.29.04.35.30; Thu, 29 Aug 2019 04:35:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IKKCbODs; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727161AbfH2Lfa (ORCPT + 14 others); Thu, 29 Aug 2019 07:35:30 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:33201 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727320AbfH2Lfa (ORCPT ); Thu, 29 Aug 2019 07:35:30 -0400 Received: by mail-pl1-f193.google.com with SMTP id go14so1457264plb.0 for ; Thu, 29 Aug 2019 04:35:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZERHer/S6V7v3IyXGHBRQXsjn5NA4nSXv7B2aoThKNw=; b=IKKCbODsWP1UqJxIEV6Bfp2AqAC3Q/r0uWJ2QI9EEp/nBCW8Djdn6c7BX718jtGwOK t2V3BjtDhWGc0pHePPoA+TpkuzPHNqqWDJkDTWfCI5+csokkit/xYobK/zw+XyD5u+Jm u9DxwOHZgmfQHbVa/myrVi16KRIUDEalhL7WqcS8a3ss3gKo4NC04T6Q5l5lSOH6TD5B PnbN78U/TyeB30y0zFag0X5UjTq6lH1/l2CJe3dUqicd3gyn+LohzNokaCtUQLoWNCTO ICeige/+bZxebev7udCVlGwl634g0ngiT8vQvelsTWSEn7l14fz1FRG60iF20bFpxFOh 9/NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZERHer/S6V7v3IyXGHBRQXsjn5NA4nSXv7B2aoThKNw=; b=fF4R6va7RoSYCy5zixpM+0tsVoN4Sp2WJuBN3bfP+eOncmBokmoJwcTPjmkhHh6NbN UpsvFzfrSWfSyGt49rbrlnxD/ywTtQhaGGa/aazLXLKYgmXCoRpu2bI00taJwcAdqnif EDCrXYeIbwsHYBAtWKUDOui1HPR+4GPnAiNDr9uIeg8pVDoh5ir/EMqf2wSydJODh982 bwMkuTy/yuZy5ICsGcXYbAI/E7G0b4CNDRFdkTS43g4Qeoqt4gd9k5X2MznkaA2v5IUt VweT5cGco5IwOp5ICExWh/gbakhdosHcx91CkqD2mtz3GR0k7rYvgYEZp4U0u9alB3TO 3Otg== X-Gm-Message-State: APjAAAX4Al195z6+ijpyKLbZoy04V+Mf1jM4ojVcRZGDqlqd6QGsnMM/ fq9dqYG4KlbKdBdTZxUGQ8CFXNwIqtM= X-Received: by 2002:a17:902:d907:: with SMTP id c7mr306952plz.126.1567078529021; Thu, 29 Aug 2019 04:35:29 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id a18sm1855103pgl.44.2019.08.29.04.35.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:35:28 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 14/44] arm64: Introduce cpu_die_early Date: Thu, 29 Aug 2019 17:03:59 +0530 Message-Id: <9f45e596fc1718310503f80b04d91eeb138d2ef5.1567077734.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Suzuki K Poulose commit ee02a15919cf86c004142edaa05b43f7ff10edf0 upstream. Or in other words, make fail_incapable_cpu() reusable. We use fail_incapable_cpu() to kill a secondary CPU early during the bringup, which doesn't have the system advertised capabilities. This patch makes the routine more generic, to kill a secondary booting CPU, getting rid of the dependency on capability struct. This can be used by checks which are not necessarily attached to a capability struct (e.g, cpu ASIDBits). In that process, renames the function to cpu_die_early() to better match its functionality. This will be moved to arch/arm64/kernel/smp.c later. Cc: Mark Rutland Acked-by: Will Deacon Signed-off-by: Suzuki K Poulose Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/cpufeature.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index d0c82bc02de4..b7f01bf47988 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -853,15 +853,15 @@ static inline void set_sys_caps_initialised(void) } /* - * Park the CPU which doesn't have the capability as advertised - * by the system. + * Kill the calling secondary CPU, early in bringup before it is turned + * online. */ -static void fail_incapable_cpu(char *cap_type, - const struct arm64_cpu_capabilities *cap) +void cpu_die_early(void) { int cpu = smp_processor_id(); - pr_crit("CPU%d: missing %s : %s\n", cpu, cap_type, cap->desc); + pr_crit("CPU%d: will not boot\n", cpu); + /* Mark this CPU absent */ set_cpu_present(cpu, 0); @@ -902,8 +902,11 @@ void verify_local_cpu_capabilities(void) * If the new CPU misses an advertised feature, we cannot proceed * further, park the cpu. */ - if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) - fail_incapable_cpu("arm64_features", &caps[i]); + if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) { + pr_crit("CPU%d: missing feature: %s\n", + smp_processor_id(), caps[i].desc); + cpu_die_early(); + } if (caps[i].enable) caps[i].enable(NULL); } @@ -911,8 +914,11 @@ void verify_local_cpu_capabilities(void) for (i = 0, caps = arm64_hwcaps; caps[i].matches; i++) { if (!cpus_have_hwcap(&caps[i])) continue; - if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) - fail_incapable_cpu("arm64_hwcaps", &caps[i]); + if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) { + pr_crit("CPU%d: missing HWCAP: %s\n", + smp_processor_id(), caps[i].desc); + cpu_die_early(); + } } } From patchwork Thu Aug 29 11:34:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172591 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2091589ily; Thu, 29 Aug 2019 04:35:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqwKK2A7Oa/bdaZxlUQ8MVH/hmP4rQeNEUGsHu42Sem7Yiee0w51VRBIllYk2Hf1acc/1paE X-Received: by 2002:a63:db45:: with SMTP id x5mr7810984pgi.293.1567078533594; Thu, 29 Aug 2019 04:35:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078533; cv=none; d=google.com; s=arc-20160816; b=l1QvujvUJs8EnfEPNUtPYi+JfoM+b4YWcySOAGVLe2BovJoPBVlTQ+HHDwbtLgQ5BQ IZmgGzaMtk/z/GpdlUSBg+bOPOqJFd70h10Ey6EPPJ86KIM6qcxDZgByCiavThX3Y1n4 wSt3AD+gw70Uy9GH0DqbzPMpMrE61jNYw5XnjwAjErCyGFj6Sa8a9Y7RW3JHv7c0+nAf 2b7IF75GUOMt6ovCxaCfH8gEh2Nk4HFmrnFJkCcQf7n8OgtLlQNtsWNJblP1VCHR3uch GES3LxPBb9lIkX6YKzr8FuJhTixftJXWc4EiLZxAJ6ywf+feoaREYuMXLg1aQmI1vTnn CO8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=O+J5pz+r7c0NpS1D8X6SYhx9QHuTsDp1UjRErYyLM4s=; b=MU9BjL/JPyodB6U+mOCXdwTzflni26rshOI3FaVHd2kiv15Lz1CHhGgzzHDw21oFWp l23iA4hsahbI4+RSuoxNKK/QW+1awmMPUaKApDqhH0i4H/vzwQLcjo0IS9q+5BLSD7N8 whc8i7bjuwD2P/FcAfuH3+xz4BljRPVF8PLKI6GQWeQhwJiv/VursxczgplFVbfz/wmF pjXpvv/mr/a0QkNYFV5fmmEk3Ma1PZi796ZFOqtzszlVB0NODE5w+BnmLvlml+zsK/uw bdKcg9shDmDdNYw2E/PHpdofWUnoqje6dseLGM+SPUk7THvNijljr2AioD/e0tjbBhGC LeJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oZTPTec0; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b30si1720301pla.299.2019.08.29.04.35.33; Thu, 29 Aug 2019 04:35:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oZTPTec0; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727362AbfH2Lfd (ORCPT + 14 others); Thu, 29 Aug 2019 07:35:33 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:42079 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727320AbfH2Lfc (ORCPT ); Thu, 29 Aug 2019 07:35:32 -0400 Received: by mail-pf1-f194.google.com with SMTP id i30so1854585pfk.9 for ; Thu, 29 Aug 2019 04:35:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O+J5pz+r7c0NpS1D8X6SYhx9QHuTsDp1UjRErYyLM4s=; b=oZTPTec0QCZyIdYWeoFDwwmLFP9g4lc0dbPQ/YV/Da2dsknHe6hU0UrVQ4lKyjcwHL ythaQ75viCx336XmpgjZGoZvhFyjdwlsqgHBHvQk9PBGbD8d4drBBMLFsOTWEUWhVV1T ad5FhTlYfhoP8xBkXaztzU1nDsDlDYbVbZ0uSEPlqF63pwu15tJl3IxJbzE6xsrg07M2 mAqCLPLR5a5s5AxsLhfs2ki+B/4gTV8AqSfT1mlyNowc+oBuTifKnCT1XSZAaIFJeGAi oPFzIhprwBPwaEt8QRs226mpGYFBXaFhdXyv+O2ggl7op8bq3FLoQ5KncK3dPUrJgaP2 IIHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O+J5pz+r7c0NpS1D8X6SYhx9QHuTsDp1UjRErYyLM4s=; b=MRgjcP3XVSkd0kQ6q32witFCAvzOjzeuM0UVhrlLW+VMrQHntgfE+EVJnyfJgniWBx 74GVnBq7FJkH2s0ZKCQ0n3w9RYKl/oOcRVNh7BLH5eEp1J87CucU4jZ8yGkL5O6tddxZ gkEFUwedeiz2aB5NJ6TYRQjc0FYUFMgXmJ/TH3ckOltjmiyxuZ1HW2J1WxSNpGdE80AZ fnCQc5crzib8rL8gEBOKYLwDkhchru7yS6GnA1ChbvBBqEMOEDaUdRt3z5aMTDRLLZQK vYDoUn4/Sf0axQMIs2088CC27yn+66/KeXc2FdQyd4MQeh1kOLmGtrgoEBSAMjpbAg6E YK/g== X-Gm-Message-State: APjAAAU+rFm/70TEXRoSz9/djGh3UyCi8Mgh6FiDS/GtMppU6rwEI2DM NCGVkY2MBDuHer4qG/T2zmmXfTByHcw= X-Received: by 2002:a17:90a:77c9:: with SMTP id e9mr8828325pjs.141.1567078531812; Thu, 29 Aug 2019 04:35:31 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id z16sm6800192pfr.136.2019.08.29.04.35.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:35:31 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 15/44] arm64: Add a helper for parking CPUs in a loop Date: Thu, 29 Aug 2019 17:04:00 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Suzuki K Poulose Commit c4bc34d20273db698c51951a1951dba0a722e162 upstream. Adds a routine which can be used to park CPUs (spinning in kernel) when they can't be killed. Cc: Mark Rutland Acked-by: Will Deacon Signed-off-by: Suzuki K Poulose Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/smp.h | 8 ++++++++ arch/arm64/kernel/cpufeature.c | 5 +---- 2 files changed, 9 insertions(+), 4 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index d9c3d6a6100a..53b53a9b3e5a 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -69,4 +69,12 @@ extern int __cpu_disable(void); extern void __cpu_die(unsigned int cpu); extern void cpu_die(void); +static inline void cpu_park_loop(void) +{ + for (;;) { + wfe(); + wfi(); + } +} + #endif /* ifndef __ASM_SMP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b7f01bf47988..4adf18307568 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -868,10 +868,7 @@ void cpu_die_early(void) /* Check if we can park ourselves */ if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die) cpu_ops[cpu]->cpu_die(cpu); - asm( - "1: wfe\n" - " wfi\n" - " b 1b"); + cpu_park_loop(); } /* From patchwork Thu Aug 29 11:34:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172593 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2091653ily; Thu, 29 Aug 2019 04:35:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqxUsSGf/AMEqpZ8+4vWDvKzMKbmTjjhtZW+VOaju4gKktdQi/3RAQBN3KSEKxArbMkjKbPu X-Received: by 2002:a17:90a:bf01:: with SMTP id c1mr9426067pjs.30.1567078536431; Thu, 29 Aug 2019 04:35:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078536; cv=none; d=google.com; s=arc-20160816; b=lW9UCKbsS9koNt+XjxqnjMemxBvIGsQX1BPIJwIFue4mZA++OgtI05AJQjmbWQOobq wYO8Q0OxnYw+FXXFFLVY1MkF6/oGfUHo+QDqTSqiJFuI9hWnUlJUXEWTCFbgQKXw6YBY b1sOSg0H7dJyiKkZQHWNU5z4kyJ76/ncIIl1T9sTEZRM9GVBBKyUsIdtk8aDGryEBKaQ F4Nt51LGzhozGg/fPJbKVwvMQDQ4cECkwNMYxC9TwWJt6QMYOSQdzkmI0ZHrMvbRXPe1 SRRatTxm+S+2IO0q0oNg3ZRpR3PSBM7QspkLWfBCPuiXucezeIBOxQLfcS19F7DcmZsF 7QHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=S7tWZ4SSsguq1kKDGe+eHq1QEkjWGUVJOVs6gRGydRo=; b=zBLnZ8fX9ZTIqXs9ZXX4wm5RJtRzvaCMrphAQ8uyRrJV8JlHqkJxRbjmSeOzFko1Ku SvXLADgvzdMh0CH6xIuBIK8O7TFw9EuEz7Cx0LeF2uJ78RaexUbqp3riqDcJCmIUzn8t 3iPN5sYueSlm0rf9meScKJyMls6ZHZYvmG9oXhHae0+5NcDfRO8VTJv/qavA87+RE+SK eJ3Up4CqLmcMbT79+vraGIrQqjr1PBYyZ8JaJHGmEXcHkXegOCWyNzXQ5nJlRSeXkwYz 9joTjGg+4yxgsr00KxlNgR51BWhWK/a+aXpScXCnVgcD/gRZYwI1FHCpiCOfeUqiAT52 ldsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pYRYAxtK; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b30si1720301pla.299.2019.08.29.04.35.36; Thu, 29 Aug 2019 04:35:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pYRYAxtK; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727285AbfH2Lff (ORCPT + 14 others); Thu, 29 Aug 2019 07:35:35 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:41767 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727578AbfH2Lff (ORCPT ); Thu, 29 Aug 2019 07:35:35 -0400 Received: by mail-pf1-f195.google.com with SMTP id 196so1856031pfz.8 for ; Thu, 29 Aug 2019 04:35:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S7tWZ4SSsguq1kKDGe+eHq1QEkjWGUVJOVs6gRGydRo=; b=pYRYAxtKgJJnWHVpW0dvFREmu6GDQq9DGA2/QUcdzPieHaQAPryaUQrqmtGboo0fNX ucmEoXA9ZB46cMtJGX78GnCicYNC++GJQJkMXz/tGcvUr4BEnOpiN6Vz2J5L77r9x9MM 4mQWEHQHXhkTW+0xxyaKY8SSwx9IvM6cDDeWRkWv27lPUSj5O/lsYAKmoOvb0p24mbkb uWzPPL7Hdcn3bGGsED/RiRw/xRXzqUsF/ikKm4O7mO+iTHJpwDJeEsZ6cq+WYt08USGP xjz3Y/E/j9b+UxSntJWH+OukE40S8fXyZaHE7v1zcKaa7ATOWu4OkAXUOH78FOqmgnvz qUQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S7tWZ4SSsguq1kKDGe+eHq1QEkjWGUVJOVs6gRGydRo=; b=MXWyFY5+Jbo72cGs4oR/2GW4ve2Q87gZG57K7VDINgUzqrNzqU/0xKduXaDVZ25SMk erVz728HV43wdajfJEmAyDXvwzVGrfPSUbRT5nOc006mP+iQtSlzya3KwxGcxi8bN7RI lEXSOdf8M2pniT97tWRGglm6zeHBK4CWRNtNQg1Gx84X5xpsMabt+KWBuDxiovG3/8V0 ffenjzCVRPFyCM71WmitNFs+rs8rcZHMtm3y4UvlHQ0ZpxvFfSDxC5UxWeJUUoba7dIQ eechgmLfvsRdxeSeM9Jxm5Hpa9pXNaQvu6+BJtiSUGq1lPn4ZjXlP2hd31kc9IGyN4gf 0FpA== X-Gm-Message-State: APjAAAWRjyWgIVQpD5IM9U+H7U39ej5mY245P4NbSVbdhtkPqvxakk5c fx16QprbytpvhX0+oVP96C0QJCDTAQA= X-Received: by 2002:a17:90a:f485:: with SMTP id bx5mr9464169pjb.113.1567078534588; Thu, 29 Aug 2019 04:35:34 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id e13sm6729834pfl.130.2019.08.29.04.35.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:35:33 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 16/44] arm64: Move cpu_die_early to smp.c Date: Thu, 29 Aug 2019 17:04:01 +0530 Message-Id: <59d2f5d6f0d1e777646712b74e542fdf160c953f.1567077734.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Suzuki K Poulose Commit fce6361fe9b0caeba0c05b7d72ceda406f8780df upstream. This patch moves cpu_die_early to smp.c, where it fits better. No functional changes, except for adding the necessary checks for CONFIG_HOTPLUG_CPU. Cc: Mark Rutland Acked-by: Will Deacon Signed-off-by: Suzuki K Poulose Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/smp.h | 1 + arch/arm64/kernel/cpufeature.c | 19 ------------------- arch/arm64/kernel/smp.c | 22 ++++++++++++++++++++++ 3 files changed, 23 insertions(+), 19 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index 53b53a9b3e5a..32e75ee21d5e 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -68,6 +68,7 @@ extern int __cpu_disable(void); extern void __cpu_die(unsigned int cpu); extern void cpu_die(void); +extern void cpu_die_early(void); static inline void cpu_park_loop(void) { diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 4adf18307568..a0273cd8be51 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -852,25 +852,6 @@ static inline void set_sys_caps_initialised(void) sys_caps_initialised = true; } -/* - * Kill the calling secondary CPU, early in bringup before it is turned - * online. - */ -void cpu_die_early(void) -{ - int cpu = smp_processor_id(); - - pr_crit("CPU%d: will not boot\n", cpu); - - /* Mark this CPU absent */ - set_cpu_present(cpu, 0); - - /* Check if we can park ourselves */ - if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die) - cpu_ops[cpu]->cpu_die(cpu); - cpu_park_loop(); -} - /* * Run through the enabled system capabilities and enable() it on this CPU. * The capabilities were decided based on the available CPUs at the boot time. diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 03c0946b79d2..23e8ae0c6305 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -312,6 +312,28 @@ void cpu_die(void) } #endif +/* + * Kill the calling secondary CPU, early in bringup before it is turned + * online. + */ +void cpu_die_early(void) +{ + int cpu = smp_processor_id(); + + pr_crit("CPU%d: will not boot\n", cpu); + + /* Mark this CPU absent */ + set_cpu_present(cpu, 0); + +#ifdef CONFIG_HOTPLUG_CPU + /* Check if we can park ourselves */ + if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die) + cpu_ops[cpu]->cpu_die(cpu); +#endif + + cpu_park_loop(); +} + static void __init hyp_mode_check(void) { if (is_hyp_mode_available()) From patchwork Thu Aug 29 11:34:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172594 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2091728ily; Thu, 29 Aug 2019 04:35:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqyL0z/9vOm2MLP5c1Up1qn9QpZJaEmOkpGduCq4tgBqSCDhmUP9jyqxtv/ODK4ax3GOIqJI X-Received: by 2002:a17:90a:bc06:: with SMTP id w6mr9687761pjr.130.1567078540828; Thu, 29 Aug 2019 04:35:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078540; cv=none; d=google.com; s=arc-20160816; b=q0XLitLSChzfSA9SGL21GlDiNbdib17yIicRvEZBkaF5z+i3gl/PrcY20fU2rFHi6X Obx/DDqR1761pg/fTeWoBXoXgSDDEkJIfUSkKy8NXphhTn7/XsApRovJiaatAGG6xv7+ cK86NzoDNHYK7ajiOuDmSysaK+4xotn5QYDqn1HI2j1SUP4EGMmTdHE79G+lM1QEwAaW 5Mvdk5mGww9NC/6mMVrixrfKvYMwCTUyqsXlpCZAF88D7Hj/PmTcHjtYMiW6n+UDuRA3 Q0RxYiQTE1+PqMja9BHZVZh51G+cFmmxupHKIRDtOeQkxHDxqBsE+pSYoKrzDcEQZhr9 0IQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NiMpS2GtyMwnZTpxG4MhAWhnIU6AXgssIk4MKZtthvc=; b=xnQqkufnIlvRMHZwrB8CxuHPqfawJX9Czd2/93BfXBRLJHzgbUhKEjJPCDezt8TIO2 UDjBljxqa7rawzXnqoj4Gvk9nYfi9Fg3h71ch0Ity82XzpjK2rhlRTm2iKJYBnOu+GEE mXEDZ+8IFMtIqiFsL7qYpMT01epKHSbT5RA90bi6HNX2Rall1CfSloQJfiLTmZSBqctl nA3OTPKeM2h7VI5QfFkqus2FGonL7Iim0U9Biyhp32S0uGhyfussjyHYgFUQdREGBEMh Yf3vWboi33Er5r7VeUJVB0W9FZYJHEIW58QxyjqkW/zObqMi8Vk6ucNtRwpj2mHCR5VC 3lAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DkQ5KEtw; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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CPU Errata work arounds are detected and applied to the kernel code at boot time and the data is then freed up. If a new hotplugged CPU requires a work around which was not applied at boot time, there is nothing we can do but simply fail the booting. Cc: Will Deacon Cc: Mark Rutland Cc: Andre Przywara Reviewed-by: Catalin Marinas Signed-off-by: Suzuki K Poulose Signed-off-by: Will Deacon [ Viresh: Resolved rebase conflict ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/cpufeature.h | 2 ++ arch/arm64/kernel/cpu_errata.c | 20 ++++++++++++++++++++ arch/arm64/kernel/cpufeature.c | 2 ++ 3 files changed, 24 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 4c31e14c0f0e..dd1aab8e52aa 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -173,6 +173,8 @@ void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, const char *info); void check_local_cpu_errata(void); +void verify_local_cpu_errata(void); + #ifdef CONFIG_HOTPLUG_CPU void verify_local_cpu_capabilities(void); #else diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 0971d80d3623..a3567881c01b 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -116,6 +116,26 @@ const struct arm64_cpu_capabilities arm64_errata[] = { } }; +/* + * The CPU Errata work arounds are detected and applied at boot time + * and the related information is freed soon after. If the new CPU requires + * an errata not detected at boot, fail this CPU. + */ +void verify_local_cpu_errata(void) +{ + const struct arm64_cpu_capabilities *caps = arm64_errata; + + for (; caps->matches; caps++) + if (!cpus_have_cap(caps->capability) && + caps->matches(caps, SCOPE_LOCAL_CPU)) { + pr_crit("CPU%d: Requires work around for %s, not detected" + " at boot time\n", + smp_processor_id(), + caps->desc ? : "an erratum"); + cpu_die_early(); + } +} + void check_local_cpu_errata(void) { update_cpu_capabilities(arm64_errata, "enabling workaround for"); diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index a0273cd8be51..9a4b638b1c18 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -872,6 +872,8 @@ void verify_local_cpu_capabilities(void) if (!sys_caps_initialised) return; + verify_local_cpu_errata(); + caps = arm64_features; for (i = 0; caps[i].matches; i++) { if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg) From patchwork Thu Aug 29 11:34:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172595 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2091769ily; Thu, 29 Aug 2019 04:35:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqySCiOaGbjirZNgKPVYaVCQSg9s5jFetsfetZANTxqhcbNEe6//Hpy+TijGY0C2VRF3uSt8 X-Received: by 2002:a17:90a:b30f:: with SMTP id d15mr9231061pjr.19.1567078542602; Thu, 29 Aug 2019 04:35:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078542; cv=none; d=google.com; s=arc-20160816; b=GvmTCblBHrBlieVWpvmTXTsb0MrRgXirrouAWOCnoocC0GYtCeO6RHXCUe55zHQ6YG 4RsAdXDappyQg1Wpqxqs4fbUE6Fj5KTPIKUOct5NKeiDARzS8J3U4YI2yIGTKxJ5D0S5 miwCqrFXH0SJscQTNAbtBCT3k3/jTueGnufHXOz3j/JSUBqN9XS0ARHLxzE5BbIoAfSb 748nS41BU+J+mP/odnM+MVDm4NmLFvQR8hHkJAOevVPjiHkvGu3a2HevpgWEnBDQS4/u JWhJKAmvKqgXTLPGt/Q3fsr52A+Z0UmD7ZTzSmRlAtqD+dZHrwecXjQ/Uasil40QtlzX nO7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dewjZZw0HbdCyicLrnA8hjXb53SKvhtBESHu+qhlc+Y=; b=Aq7Gs7kPMvs2jGSmL0IrMTEQiQ/cUJisf/dHRExcgFPV6mc2eSC8/anOPGduk3PWbv 81nFiE6QRBQ34lLbRtO6KyHgLIPJpyCXWGTtdtLlI8K5Dw87MGlNrXhVXUsM2+lmG9dA oNkrXQUlTdO8hOXBYE11G/MkaoxdN08RMf1Xg0HiMjPf97dNPvhv1kqQhIqppl0XsWg/ 4JTpEV5gmbuFfYWAuWvJE0SWiwrtWA5QKUKL72uGxwi8GuSpyIFzmiXjjAiN87SKapKZ to4nWfEmuciL/qr5RVJ9wmZyPIFAc6YP6qysSiKog+JBeorjKvJATC2RVfnpg5W3hGWP 9o3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lIExeLrh; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Currently we call the (optional) enable function for CPU _features_ only. As CPU _errata_ descriptions share the same data structure and having an enable function is useful for errata as well (for instance to set bits in SCTLR), lets call it when enumerating erratas too. Signed-off-by: Andre Przywara Reviewed-by: Suzuki K Poulose Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/cpufeature.h | 2 ++ arch/arm64/kernel/cpu_errata.c | 5 +++++ arch/arm64/kernel/cpufeature.c | 3 ++- 3 files changed, 9 insertions(+), 1 deletion(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index dd1aab8e52aa..0267bab6ac18 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -171,7 +171,9 @@ void __init setup_cpu_features(void); void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, const char *info); +void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps); void check_local_cpu_errata(void); +void __init enable_errata_workarounds(void); void verify_local_cpu_errata(void); diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index a3567881c01b..d9f095439011 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -140,3 +140,8 @@ void check_local_cpu_errata(void) { update_cpu_capabilities(arm64_errata, "enabling workaround for"); } + +void __init enable_errata_workarounds(void) +{ + enable_cpu_capabilities(arm64_errata); +} diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 9a4b638b1c18..7773bea6927e 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -820,7 +820,7 @@ void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, * Run through the enabled capabilities and enable() it on all active * CPUs */ -static void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) +void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) { int i; @@ -923,6 +923,7 @@ void __init setup_cpu_features(void) /* Set the CPU feature capabilies */ setup_feature_capabilities(); + enable_errata_workarounds(); setup_cpu_hwcaps(); /* Advertise that we have computed the system capabilities */ From patchwork Thu Aug 29 11:34:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172596 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2091825ily; Thu, 29 Aug 2019 04:35:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqz2igISXEEnxqQyPbjcnE58Hj7TFjK/LZO1sL0NNyGUnSmGyFDNwbBSbc1SoIGVS2hjd2cE X-Received: by 2002:a62:ee0e:: with SMTP id e14mr11032913pfi.31.1567078545233; Thu, 29 Aug 2019 04:35:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078545; cv=none; d=google.com; s=arc-20160816; b=i112xmGCU7ZsQtv2mi7cBlqHxaOtQxy83FtzACnjrhgLoNF4OB/2vKZ5pwRuYVOCvv nqNSPQbIkAQWgKaSvZOJNx5nixzYJZZ9l6RxDh/iC7YSWv/h4oqIF/0zlTafUKaDc6oJ bq3dfV8RzbNvMFYcQ9PkLyzbJLqSS3pYnl423JyLD51qmXqmZqnEokVVa8g2x3Wa/zCt KIeHRDcXKriMBmdSdWHNTJnW3QweITY5KJY5QOQiHNB4vMzVfVp2OQYVJmj1el3EQQ1K 3Sw4vuEYLRFqCz7UHDZoa4rnO0gnBx6H6iSliNkDxQ+CSMnrNZaYvj+0zRcbDaLOdWzu 9IKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fkxeJKseCGMXAXIlAcnMLE13XsHo9zOa4aO4yBF3DzQ=; b=l37PdFTczjUl0qZLVKwYaSlvbSHjcKuwuNJD9CwYVTnLgBqi4iaRGb0cpTQJzPYSAT VMPTiSlsS5XKkHAhCrbWq0VXH7NiiSeZsB5Brc+1LmLx2oIEmcoxgL+yIDl6Yp6HqEPn iIvRgvtVfq8BkQ7uIbhbssexZKg5yJKqvJMAz/v2gHb24PI3TXU2JQDKWCvg/JFqw0yC mjGjLYLVIwXspdRMbTjIJ+89AmeRMjyB/qN7lI5pAC4m9JejZu/W+xvYPMaZmUrqurNc Jpdo09A2fkXAKF/zfQFBsFpSnkhzgreRvDdrHP4WiR0/12js+g2qUi9DZHTtMK+iJWdN aUDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zujYWfHM; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Right now we run through the work around checks on a CPU from __cpuinfo_store_cpu. There are some problems with that: 1) We initialise the system wide CPU feature registers only after the Boot CPU updates its cpuinfo. Now, if a work around depends on the variance of a CPU ID feature (e.g, check for Cache Line size mismatch), we have no way of performing it cleanly for the boot CPU. 2) It is out of place, invoked from __cpuinfo_store_cpu() in cpuinfo.c. It is not an obvious place for that. This patch rearranges the CPU specific capability(aka work around) checks. 1) At the moment we use verify_local_cpu_capabilities() to check if a new CPU has all the system advertised features. Use this for the secondary CPUs to perform the work around check. For that we rename verify_local_cpu_capabilities() => check_local_cpu_capabilities() which: If the system wide capabilities haven't been initialised (i.e, the CPU is activated at the boot), update the system wide detected work arounds. Otherwise (i.e a CPU hotplugged in later) verify that this CPU conforms to the system wide capabilities. 2) Boot CPU updates the work arounds from smp_prepare_boot_cpu() after we have initialised the system wide CPU feature values. Cc: Mark Rutland Cc: Andre Przywara Cc: Will Deacon Cc: Catalin Marinas Signed-off-by: Suzuki K Poulose Signed-off-by: Will Deacon Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/cpufeature.h | 8 +------- arch/arm64/kernel/cpufeature.c | 23 +++++++++++++++-------- arch/arm64/kernel/cpuinfo.c | 2 -- arch/arm64/kernel/smp.c | 8 +++++++- 4 files changed, 23 insertions(+), 18 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 0267bab6ac18..1bc51f8835e5 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -177,13 +177,7 @@ void __init enable_errata_workarounds(void); void verify_local_cpu_errata(void); -#ifdef CONFIG_HOTPLUG_CPU -void verify_local_cpu_capabilities(void); -#else -static inline void verify_local_cpu_capabilities(void) -{ -} -#endif +void check_local_cpu_capabilities(void); u64 read_system_reg(u32 id); diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 7773bea6927e..c74df3ca000e 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -860,18 +860,11 @@ static inline void set_sys_caps_initialised(void) * cannot do anything to fix it up and could cause unexpected failures. So * we park the CPU. */ -void verify_local_cpu_capabilities(void) +static void verify_local_cpu_capabilities(void) { int i; const struct arm64_cpu_capabilities *caps; - /* - * If we haven't computed the system capabilities, there is nothing - * to verify. - */ - if (!sys_caps_initialised) - return; - verify_local_cpu_errata(); caps = arm64_features; @@ -902,6 +895,20 @@ void verify_local_cpu_capabilities(void) } } +void check_local_cpu_capabilities(void) +{ + /* + * If we haven't finalised the system capabilities, this CPU gets + * a chance to update the errata work arounds. + * Otherwise, this CPU should verify that it has all the system + * advertised capabilities. + */ + if (!sys_caps_initialised) + check_local_cpu_errata(); + else + verify_local_cpu_capabilities(); +} + #else /* !CONFIG_HOTPLUG_CPU */ static inline void set_sys_caps_initialised(void) diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 0166cfbc866c..13e659fda04a 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -239,8 +239,6 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) info->reg_mvfr2 = read_cpuid(MVFR2_EL1); cpuinfo_detect_icache_policy(info); - - check_local_cpu_errata(); } void cpuinfo_store_cpu(void) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 23e8ae0c6305..02b76bb78d59 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -161,7 +161,7 @@ asmlinkage notrace void secondary_start_kernel(void) * this CPU ticks all of those. If it doesn't, the CPU will * fail to come online. */ - verify_local_cpu_capabilities(); + check_local_cpu_capabilities(); if (cpu_ops[cpu]->cpu_postboot) cpu_ops[cpu]->cpu_postboot(); @@ -357,6 +357,12 @@ void __init smp_prepare_boot_cpu(void) { set_my_cpu_offset(per_cpu_offset(smp_processor_id())); cpuinfo_store_boot_cpu(); + /* + * Run the errata work around checks on the boot CPU, once we have + * initialised the cpu feature infrastructure from + * cpuinfo_store_boot_cpu() above. + */ + check_local_cpu_errata(); } static u64 __init of_get_cpu_mpidr(struct device_node *dn) From patchwork Thu Aug 29 11:34:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172597 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2091893ily; Thu, 29 Aug 2019 04:35:48 -0700 (PDT) X-Google-Smtp-Source: APXvYqwwdwOy6XHYGORq/POOlZ1jsQS3palpp1W7AOC+BVcY/G0+NFhXSHDiPrWSHOgj/NSkKo+w X-Received: by 2002:a63:e213:: with SMTP id q19mr7822510pgh.180.1567078548174; Thu, 29 Aug 2019 04:35:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078548; cv=none; d=google.com; s=arc-20160816; b=x2UtGhh+bFb6QPaAqsFw3HCSEMBT7VhjgB/lH6VwrL5jNutE+I7oHmYXxG808reJNt buAbCatR9MHTPIbimWExgqH9Kdlc416qSseRfVA8rSvZzgPtsEkVk6G7CwGwLYzzmrUN Pk9JUT/raOgCdq8g4HiqPIj1lVOkqgXMt85Btz7AXnCO1lsztl7CDfCq/lH87Htv+2Bq BtSOaf8Dm1DFSJUESjRVLMjHKnjH8uv+jfKAKX27tnYufbjgN4ViWDwGwdlpNSg93WRQ FSWjxuvY4WSAlSYjFpUCq52stktpYCN1/5vGIjxQOFVluw1it613Ap99i13ZNYoKfju8 YkXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=j1PYP8TRl6+XUUI1RLnfOfH8okdoaEeO+GZk5UMu4vo=; b=ieGs7tBwWz/lHUWRGeRNXX3Hejn/VtiNI8ogAv24dkm5si1JSOUlOEhSce0/GS7mll EFZPR9eS75aZKWRYOSbLXMVDsqoWBsz4fHSOD0EusNZaOifGVBEUsJJ2xEHuKSGi2wQX 6HvzsnqBr1eEu4mBi2USY9+xlR7W3l7CG5Tv/GBqW2Nbe1a8onhK+1o11fvOWvIoKfpt JhO3j+xRUwJ7ob2v1gSCg4iuh0C4v9c1hlVs4uDlWpuMEPU2aJmtVTNjf847/XZ94Tk9 hooE4y4LcMruOxqJn+Wg+EcKZE9L/Q57siA766CtsyyYh4tscP6BIO2jnGxNUpjLqF6N T4Lg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ip6B9wM3; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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When a CPU is brought up after we have finalised the system wide capabilities (i.e, features and errata), we make sure the new CPU doesn't need a new errata work around which has not been detected already. However we don't run enable() method on the new CPU for the errata work arounds already detected. This could cause the new CPU running without potential work arounds. It is upto the "enable()" method to decide if this CPU should do something about the errata. Fixes: commit 6a6efbb45b7d95c84 ("arm64: Verify CPU errata work arounds on hotplugged CPU") Cc: Will Deacon Cc: Mark Rutland Cc: Andre Przywara Cc: Dave Martin Signed-off-by: Suzuki K Poulose Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/cpu_errata.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index d9f095439011..047f1da59cb1 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -125,15 +125,18 @@ void verify_local_cpu_errata(void) { const struct arm64_cpu_capabilities *caps = arm64_errata; - for (; caps->matches; caps++) - if (!cpus_have_cap(caps->capability) && - caps->matches(caps, SCOPE_LOCAL_CPU)) { + for (; caps->matches; caps++) { + if (cpus_have_cap(caps->capability)) { + if (caps->enable) + caps->enable((void *)caps); + } else if (caps->matches(caps, SCOPE_LOCAL_CPU)) { pr_crit("CPU%d: Requires work around for %s, not detected" " at boot time\n", smp_processor_id(), caps->desc ? : "an erratum"); cpu_die_early(); } + } } void check_local_cpu_errata(void) From patchwork Thu Aug 29 11:34:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172598 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2091928ily; Thu, 29 Aug 2019 04:35:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqyRb2Hqt26GJsO+tDdHY+pwr7nm/09ZJgqSaUeksOuNRAD2RUhSddA2oNwLOfzW+bpY4U+Y X-Received: by 2002:a62:383:: with SMTP id 125mr10730644pfd.248.1567078550880; Thu, 29 Aug 2019 04:35:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078550; cv=none; d=google.com; s=arc-20160816; b=t048bah/PTaFubS+giVlcev3tPDmIqGt8p7DASQsY7zYa+7uTBcYgtR5d9PRX7whf2 MpDGp2uYtTpJLc69n3eLy+gMxi4vlVrUQeZR5J4Q1jDhvsG7IhX6N7DfZPrIXJC2R4dB xQM+jueVA1O9zwTxp5z0I9E2QSHi5I2jQ+Yam1zDvtlgvfMHhZx8obBmw0d/ggO4ciF2 7QwGUCXa4JmQUgbF5ogctiUvms98ag/tHYpJUazfjvqfx2q3dKzkXzjfyVIy+yAZT+Ek VPrmyNE5AoCw9mZyyqjhBGK2BE+6AQFFI5MqALMrmXT42suebiW7r47EKo2h1KmxFdHF 3A/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=L+Gdnz2jFF65J3PIUhAk0AHlnEqUM/+ROCtumKJNSeI=; b=wFL/z+vrBfuFDwBHYMR9ZCfHpQ5vr98jYYlPMA22G7IlAx+l6n99lM3rk45DRWZoKK 9uBxy3M4UwBTPjzFo8ZLBNGh8FZ/H9tiyQNlP6LqIDzILX/glnGis0DLEguIvmCfrFgG 4J9RrLvh+ogzO7GjwmCrx6zuoGFFq4QwLVFXIMt9A3t6SmsjlelUcW/SLpB2ZdSgoN6k R0PQRNf67xnu8UHzAewM09GLYOONLx4aF+JsCWvkrSXyt5M2i+QNPnEev859P7SMpB5G qAqp7DDr8Slxhtksk4E7IgJ8vlw5ux+v5P+MfhKUtGET0k9KgT5SmZNgR/FJ19IIyzJR HMeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Oe6Dz415; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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In order to invoke the CPU capability ->matches callback from the ->enable callback for applying local-CPU workarounds, we need a handle on the capability structure. This patch passes a pointer to the capability structure to the ->enable callback. Reviewed-by: Suzuki K Poulose Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: Use &caps[i] instead as caps isn't incremented ] Signed-off-by: Viresh Kumar --- arch/arm64/kernel/cpufeature.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c74df3ca000e..474b34243521 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -832,7 +832,7 @@ void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) * uses an IPI, giving us a PSTATE that disappears when * we return. */ - stop_machine(caps[i].enable, NULL, cpu_online_mask); + stop_machine(caps[i].enable, (void *)&caps[i], cpu_online_mask); } #ifdef CONFIG_HOTPLUG_CPU @@ -881,7 +881,7 @@ static void verify_local_cpu_capabilities(void) cpu_die_early(); } if (caps[i].enable) - caps[i].enable(NULL); + caps[i].enable((void *)&caps[i]); } for (i = 0, caps = arm64_hwcaps; caps[i].matches; i++) { From patchwork Thu Aug 29 11:34:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172599 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2091974ily; Thu, 29 Aug 2019 04:35:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqz/xQKamzBKviiQqxbcypaK8+XYfFZMLh7TZ4UegRpe3yc29HDj1kX0JFsR5irZVBUvNoB6 X-Received: by 2002:a62:ee0e:: with SMTP id e14mr11033611pfi.31.1567078553383; Thu, 29 Aug 2019 04:35:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078553; cv=none; d=google.com; s=arc-20160816; b=rnm5GtQAx2vcXim6mIU1DYLs0Zd497156R5+UPeaYsmoOzz1jU4JzylNOYRmjYxaef L8Tk7u/Vx7Qy8WdbIENKZuJbnNRyuObsJEEuoOzEJf8sdf5aO9rwOQqJpoQ/+0UIYk/B zoFAL4vGn1wlR1DubvYxAN+2U5K3b2wnS6/90cnE3+o0RAzBLTG6WdJ4JetZwQWtxg/d Jtjl61L/QC/XDOX+ZrOTukOK0CqsJOtldDSjL+JM44vb737MSdYgUSpUFyLT24kvA4Td ymCHF10b3ELFxDYIpgPKC6+4P3X6OTM+YZ3/CObSi4FeBZQ8GWak32yqKKgEeEDjZYg/ UvXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tUK8ETga6k61l9Q+/z8rY6SIV6XG+DcjRuCd/1NWAIQ=; b=N4Xrlao0PpAODSXLMhfgLtibsLRC0P07ncS2rhpyzqZdlYPrEp9Lj/j4gUxfrP1453 tOtqfKHCcOZ1wgsJsYa91WrNFtN3B7tVlva3Gy0jUG2kDe1ImtgCy376XHNm19iXmVOi rzWvU//qeM6ZUaC2YK0HZz1Si4K5yXUlIFx/fnuKXjZqscZorYiID6B7yavv06NxuZTC tinOxjakYw/bcm/Cqeh7hMgKKCYERlY8CKU9oJ1qIlj24ibYjz4UOEXGCQsnnOuOayUC rUZwK02bTHXDPkx6xHleW3psbbo6ARTUt+VSz2OI/raoD7rSAgMaDdBXG5SCA86//LWi XNxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EKkXXo+2; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b30si1720301pla.299.2019.08.29.04.35.53; Thu, 29 Aug 2019 04:35:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EKkXXo+2; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727213AbfH2Lfw (ORCPT + 14 others); Thu, 29 Aug 2019 07:35:52 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:42469 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727118AbfH2Lfw (ORCPT ); Thu, 29 Aug 2019 07:35:52 -0400 Received: by mail-pg1-f194.google.com with SMTP id p3so1436028pgb.9 for ; Thu, 29 Aug 2019 04:35:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tUK8ETga6k61l9Q+/z8rY6SIV6XG+DcjRuCd/1NWAIQ=; b=EKkXXo+25/F2wHAvxwC+L41EuvRc64ZuVgzd/LPBxjuYWjUOugeBxX/JmSX8/pPuWi tcTrkn9aLyId59ixMbK5XFkaU3wK0vKNY3VK/rHHrRBg/dPSckEW+9rmjlNWuQM9Tisx 0KJ3e7msSb2P0/kZmniWPexAfGtt/YjGycG7slVs+YzEMUXsFeD2Aewrk9WB7F+DPfeI TTd0iWFy2hXN8TbqyaK53fAVy0kmnGxF83t3lGsQU142ZiTORguncJKiCnZh3bb1pSpG YnyCr7j6D258ztcvLdFikS1wRddMjD+luCPjxUZUU/kiSvqvN5wsIEBuOgsJZ320VmEd wT8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tUK8ETga6k61l9Q+/z8rY6SIV6XG+DcjRuCd/1NWAIQ=; b=n7wkJoQuCXaZ0LBu0eBMmXr2XSp1wGIQHsj77xjw4Wx4PoJg2UFAfmIbA0Xrr2K+8J si6KyxSPYMs3CkdDINrI4L0Fh6FTmV8BycXf/WekQ7kJqtRoq258iLVM5nWYRK4IIhHN //zhXsAoPVHQjF/I0a+7WjPsRS794u2Z6ebEMV5yfqey8fC/MXVW4+yOpMCraiYl/Yss d4jdZzyNVnHiK+YG3lKLVCkM4kT9r+Nq5ZXt7qnVqvuCWF9Q6UHUFmY9Wnf87KsnQl2b 0uubg9m8/qe5eQXjphekx2dGO7IoCkecR/cCLrqncMgb58B3ZtzD1rWXz+izMxCsaoBK iohg== X-Gm-Message-State: APjAAAVlZEjOt+gGiGUG2loQBJIfayBaabeNns86XhKfAVqHgnbP5wy2 PVLr3h+VwT4h9j5ST2CdGFnMBeMFUaI= X-Received: by 2002:a17:90b:8c1:: with SMTP id ds1mr9513477pjb.114.1567078551685; Thu, 29 Aug 2019 04:35:51 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id c199sm3767496pfb.28.2019.08.29.04.35.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:35:50 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 22/44] drivers/firmware: Expose psci_get_version through psci_ops structure Date: Thu, 29 Aug 2019 17:04:07 +0530 Message-Id: <116c1fadc5685b62ab36b1a368eede3f9b1bb9da.1567077734.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit d68e3ba5303f7e1099f51fdcd155f5263da8569b upstream. Entry into recent versions of ARM Trusted Firmware will invalidate the CPU branch predictor state in order to protect against aliasing attacks. This patch exposes the PSCI "VERSION" function via psci_ops, so that it can be invoked outside of the PSCI driver where necessary. Acked-by: Lorenzo Pieralisi Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- drivers/firmware/psci.c | 2 ++ include/linux/psci.h | 1 + 2 files changed, 3 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index ae70d2485ca1..290f8982e7b3 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -305,6 +305,8 @@ static void __init psci_init_migrate(void) static void __init psci_0_2_set_functions(void) { pr_info("Using standard PSCI v0.2 function IDs\n"); + psci_ops.get_version = psci_get_version; + psci_function_id[PSCI_FN_CPU_SUSPEND] = PSCI_FN_NATIVE(0_2, CPU_SUSPEND); psci_ops.cpu_suspend = psci_cpu_suspend; diff --git a/include/linux/psci.h b/include/linux/psci.h index 12c4865457ad..04b4d92c7791 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -25,6 +25,7 @@ bool psci_power_state_loses_context(u32 state); bool psci_power_state_is_valid(u32 state); struct psci_operations { + u32 (*get_version)(void); int (*cpu_suspend)(u32 state, unsigned long entry_point); int (*cpu_off)(u32 state); int (*cpu_on)(unsigned long cpuid, unsigned long entry_point); From patchwork Thu Aug 29 11:34:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172600 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092039ily; Thu, 29 Aug 2019 04:35:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqzZQenQjhE4BPkZzHAWYPtWu3ufNkbgjHI87OkZE+ndmNy6l9Z+/iQ4SRSkpM98z7DV0Kah X-Received: by 2002:a17:90a:326e:: with SMTP id k101mr9771717pjb.15.1567078556002; Thu, 29 Aug 2019 04:35:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078555; cv=none; d=google.com; s=arc-20160816; b=jRm4fdZeSRVKSxzdAq6sF8ZFbeBm0mQPziVcc3beQ4cfq9N6qnvDDUTYHhlS8uQwef 8fyUdtLYROH1kWu6ZQpgZa4fk527qKT6F+A2Pcqi3+04ZeRaByS6gLM6cQs6AFybFtvS vuFs57Et7byZyy9jMOOQ+eZJCwucAnUgfI/B5LdTOyUNWxsezoKLXGH6NBldvyjBv9x0 A1Dl9Ed3P5fczHeWDbZf42Aa6100g8UNeMeqQzrnUBGPPXreHU6YT5Ou1BAbvb6YVfVq I3aypCKVn4Bz8uONW+iEfgo4fOiMXNfgKIzJw8rq0ByIEB/DUdwfx/srrVhjknU4lIAS 4ntA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Cnuqc1YlBQBZ4RWPKzaqy9DfMXgSoNZrvvTdeydR7XY=; b=IgeNucHPtXBABq5hlHa2w+LQHvBZLfs9AYWIl7OKBsnszdPdvl8dSLhANbTDrEuuzM xh+Bzlqt2qFZwgEBca1hyfIatwusRcvC26UXz97/r39lesy/bLeuzbdn6FjhksuCECYj 5VeVrUjnPQJnKc0BXQNMf5vI+Bfg4Bhq8kllePUZgq829onBtawin+fnVHqieEhnCfde pG8Y6xB8rrCNAwcSZDHt9IxOz/xb/o1403tkAHr+FZH2Kv7JJahRytSW5Bl5DvdUw3dc TCYzSLFyena0rUgjGcTL8IN5os6sAz5YXxWWlgxOc5yAeEP1VAKVtVP8WQPia4J9Kx2d cTnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UW0U9Y3O; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This patch takes the errata workaround code out of cpu_do_switch_mm into a dedicated post_ttbr0_update_workaround macro which will be reused in a subsequent patch. Cc: Will Deacon Cc: James Morse Cc: Kees Cook Reviewed-by: Mark Rutland Signed-off-by: Catalin Marinas [ v4.4: Included cpufeature.h and adapted to use alternative_if_not ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/assembler.h | 18 ++++++++++++++++++ arch/arm64/mm/proc.S | 11 +---------- 2 files changed, 19 insertions(+), 10 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 2b30363a3a89..8ab46508e836 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -23,6 +23,7 @@ #ifndef __ASM_ASSEMBLER_H #define __ASM_ASSEMBLER_H +#include #include #include #include @@ -282,4 +283,21 @@ lr .req x30 // link register .Ldone\@: .endm +/* + * Errata workaround post TTBR0_EL1 update. + */ + .macro post_ttbr0_update_workaround +#ifdef CONFIG_CAVIUM_ERRATUM_27456 +alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 + ret + nop + nop + nop +alternative_else + ic iallu + dsb nsh + isb +#endif + .endm + #endif /* __ASM_ASSEMBLER_H */ diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index f09636738007..4eb1084e203a 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -139,17 +139,8 @@ ENTRY(cpu_do_switch_mm) bfi x0, x1, #48, #16 // set the ASID msr ttbr0_el1, x0 // set TTBR0 isb -alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 + post_ttbr0_update_workaround ret - nop - nop - nop -alternative_else - ic iallu - dsb nsh - isb - ret -alternative_endif ENDPROC(cpu_do_switch_mm) .section ".text.init", #alloc, #execinstr From patchwork Thu Aug 29 11:34:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172601 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092101ily; Thu, 29 Aug 2019 04:35:58 -0700 (PDT) X-Google-Smtp-Source: APXvYqyPEaCHwHy0edsy+ck8edDTbx48E6y/e9Lf0PE7k8RrnAqaWlTbamugAufb0iWp5yskja0o X-Received: by 2002:aa7:8808:: with SMTP id c8mr10409161pfo.67.1567078558509; Thu, 29 Aug 2019 04:35:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078558; cv=none; d=google.com; s=arc-20160816; b=mNGIGYRUbBvEYtEULhQYTaPV0002ycWywBUAoUNINU6V9Jr0H7hadbK4MWigDyWHpc Pn+8TUJOP4t2YOPGekTG7lIgT7wnEJdbHPTHuRv7uMCZhMsQsnL2ygMRXmQm7JS8Tt8V nNRRYJUwAuXCQqEWwDKV72P+SiFWZ1Iac8vfbIU2Mz9T774LuVEZCdboxsLJzkUx4xTj 1LWToqs0aNhJYsOzVlSz+ipEcFLB5yhfX+JDFiSJYIi+0L7Rsw+PJw0saXkZMagieebx xzYQvcPzb3IrFQCq3o0CWeMpZtG0si/p26SyhaNYXYzATDBTzWgjewo636+MRrUGOrTA Fg4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FJU6AKZYmaWbov8SdJbQnRPRbYy33d5KJviuZzujVLk=; b=skLgKetrzCY/er/ts6NZ8dSxx3py6+CWug/MGUDd7+t8SqU0/DhTZFB8+GfZINseKb RdW1aifazeIJ1YS+ElZo5a4GYaU1VO0Y/knwdSiLfNCmtlu4japM0eQqvR2T5TkWa9ud 6qrh4P4qIWRBYxjnRdNIaDpo9uUkOjK2TKJcjq9er0srUTMRzJFJ7l+uavaNjylaOOCq QMqVTNdENRBFEwKbrwntQ+zHdU1MAgL99LO21Xf3XfwpVtX4VDfTXyKg9XHlfEvhhqMd VkVQc3L67CNxmY8WjQrZdz+JZDqRhZ3QfGpJzfSbvCf0SqJvjP3YoB7QJRFG1qZwNiMZ wMPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dqcvWNww; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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We will soon need to invoke a CPU-specific function pointer after changing page tables, so move post_ttbr_update_workaround out into C code to make this possible. Signed-off-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: Removed cpufeature.h, included alternative.h, dropped entry.S changes and adapted to drop alternative_if_not ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/assembler.h | 18 ------------------ arch/arm64/mm/context.c | 10 ++++++++++ arch/arm64/mm/proc.S | 3 +-- 3 files changed, 11 insertions(+), 20 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 8ab46508e836..2b30363a3a89 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -23,7 +23,6 @@ #ifndef __ASM_ASSEMBLER_H #define __ASM_ASSEMBLER_H -#include #include #include #include @@ -283,21 +282,4 @@ lr .req x30 // link register .Ldone\@: .endm -/* - * Errata workaround post TTBR0_EL1 update. - */ - .macro post_ttbr0_update_workaround -#ifdef CONFIG_CAVIUM_ERRATUM_27456 -alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 - ret - nop - nop - nop -alternative_else - ic iallu - dsb nsh - isb -#endif - .endm - #endif /* __ASM_ASSEMBLER_H */ diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index e87f53ff5f58..492d2968fa8f 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -185,6 +186,15 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) cpu_switch_mm(mm->pgd, mm); } +/* Errata workaround post TTBRx_EL1 update. */ +asmlinkage void post_ttbr_update_workaround(void) +{ + asm(ALTERNATIVE("nop; nop; nop", + "ic iallu; dsb nsh; isb", + ARM64_WORKAROUND_CAVIUM_27456, + CONFIG_CAVIUM_ERRATUM_27456)); +} + static int asids_init(void) { int fld = cpuid_feature_extract_field(read_cpuid(ID_AA64MMFR0_EL1), 4); diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 4eb1084e203a..a70b712ca94a 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -139,8 +139,7 @@ ENTRY(cpu_do_switch_mm) bfi x0, x1, #48, #16 // set the ASID msr ttbr0_el1, x0 // set TTBR0 isb - post_ttbr0_update_workaround - ret + b post_ttbr_update_workaround // Back to C code... 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Aliasing attacks against CPU branch predictors can allow an attacker to redirect speculative control flow on some CPUs and potentially divulge information from one context to another. This patch adds initial skeleton code behind a new Kconfig option to enable implementation-specific mitigations against these attacks for CPUs that are affected. Co-developed-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: Changes made according to 4.4 codebase ] Signed-off-by: Viresh Kumar --- arch/arm64/Kconfig | 17 +++++++ arch/arm64/include/asm/cpufeature.h | 3 +- arch/arm64/include/asm/mmu.h | 39 +++++++++++++++ arch/arm64/include/asm/sysreg.h | 2 + arch/arm64/kernel/Makefile | 5 ++ arch/arm64/kernel/bpi.S | 55 +++++++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 74 +++++++++++++++++++++++++++++ arch/arm64/kernel/cpufeature.c | 3 +- arch/arm64/kernel/entry.S | 8 ++-- arch/arm64/mm/context.c | 2 + arch/arm64/mm/fault.c | 16 +++++++ 11 files changed, 219 insertions(+), 5 deletions(-) create mode 100644 arch/arm64/kernel/bpi.S -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index f18b8c26a959..5fa01073566b 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -624,6 +624,23 @@ config FORCE_MAX_ZONEORDER However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 4M allocations matching the default size used by generic code. +config HARDEN_BRANCH_PREDICTOR + bool "Harden the branch predictor against aliasing attacks" if EXPERT + default y + help + Speculation attacks against some high-performance processors rely on + being able to manipulate the branch predictor for a victim context by + executing aliasing branches in the attacker context. Such attacks + can be partially mitigated against by clearing internal branch + predictor state and limiting the prediction logic in some situations. + + This config option will take CPU-specific actions to harden the + branch predictor against aliasing attacks and may rely on specific + instruction sequences or control bits being set by the system + firmware. + + If unsure, say Y. + menuconfig ARMV8_DEPRECATED bool "Emulate deprecated/obsolete ARMv8 instructions" depends on COMPAT diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 1bc51f8835e5..93fb24d14d95 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -32,8 +32,9 @@ #define ARM64_WORKAROUND_834220 7 #define ARM64_WORKAROUND_CAVIUM_27456 8 #define ARM64_HAS_32BIT_EL0 9 +#define ARM64_HARDEN_BRANCH_PREDICTOR 10 -#define ARM64_NCAPS 10 +#define ARM64_NCAPS 11 #ifndef __ASSEMBLY__ diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h index 990124a67eeb..8d0129210416 100644 --- a/arch/arm64/include/asm/mmu.h +++ b/arch/arm64/include/asm/mmu.h @@ -16,6 +16,8 @@ #ifndef __ASM_MMU_H #define __ASM_MMU_H +#include + typedef struct { atomic64_t id; void *vdso; @@ -28,6 +30,43 @@ typedef struct { */ #define ASID(mm) ((mm)->context.id.counter & 0xffff) +typedef void (*bp_hardening_cb_t)(void); + +struct bp_hardening_data { + int hyp_vectors_slot; + bp_hardening_cb_t fn; +}; + +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR +extern char __bp_harden_hyp_vecs_start[], __bp_harden_hyp_vecs_end[]; + +DECLARE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); + +static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void) +{ + return this_cpu_ptr(&bp_hardening_data); +} + +static inline void arm64_apply_bp_hardening(void) +{ + struct bp_hardening_data *d; + + if (!cpus_have_cap(ARM64_HARDEN_BRANCH_PREDICTOR)) + return; + + d = arm64_get_bp_hardening_data(); + if (d->fn) + d->fn(); +} +#else +static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void) +{ + return NULL; +} + +static inline void arm64_apply_bp_hardening(void) { } +#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ + extern void paging_init(void); extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt); extern void init_mem_pgprot(void); diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 50150320f80d..523b089fb408 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -95,6 +95,8 @@ #define ID_AA64ISAR0_AES_SHIFT 4 /* id_aa64pfr0 */ +#define ID_AA64PFR0_CSV2_SHIFT 56 +#define ID_AA64PFR0_SVE_SHIFT 32 #define ID_AA64PFR0_GIC_SHIFT 24 #define ID_AA64PFR0_ASIMD_SHIFT 20 #define ID_AA64PFR0_FP_SHIFT 16 diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 474691f8b13a..aa8f28210219 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -42,7 +42,12 @@ arm64-obj-$(CONFIG_PCI) += pci.o arm64-obj-$(CONFIG_ARMV8_DEPRECATED) += armv8_deprecated.o arm64-obj-$(CONFIG_ACPI) += acpi.o +ifeq ($(CONFIG_KVM),y) +arm64-obj-$(CONFIG_HARDEN_BRANCH_PREDICTOR) += bpi.o +endif + obj-y += $(arm64-obj-y) vdso/ + obj-m += $(arm64-obj-m) head-y := head.o extra-y += $(head-y) vmlinux.lds diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S new file mode 100644 index 000000000000..06a931eb2673 --- /dev/null +++ b/arch/arm64/kernel/bpi.S @@ -0,0 +1,55 @@ +/* + * Contains CPU specific branch predictor invalidation sequences + * + * Copyright (C) 2018 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +.macro ventry target + .rept 31 + nop + .endr + b \target +.endm + +.macro vectors target + ventry \target + 0x000 + ventry \target + 0x080 + ventry \target + 0x100 + ventry \target + 0x180 + + ventry \target + 0x200 + ventry \target + 0x280 + ventry \target + 0x300 + ventry \target + 0x380 + + ventry \target + 0x400 + ventry \target + 0x480 + ventry \target + 0x500 + ventry \target + 0x580 + + ventry \target + 0x600 + ventry \target + 0x680 + ventry \target + 0x700 + ventry \target + 0x780 +.endm + + .align 11 +ENTRY(__bp_harden_hyp_vecs_start) + .rept 4 + vectors __kvm_hyp_vector + .endr +ENTRY(__bp_harden_hyp_vecs_end) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 047f1da59cb1..19c51d1cd302 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -43,6 +43,80 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) return (midr >= entry->midr_range_min && midr <= entry->midr_range_max); } +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR +#include +#include + +DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); + +#ifdef CONFIG_KVM +static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, + const char *hyp_vecs_end) +{ + void *dst = __bp_harden_hyp_vecs_start + slot * SZ_2K; + int i; + + for (i = 0; i < SZ_2K; i += 0x80) + memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start); + + flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K); +} + +static void __install_bp_hardening_cb(bp_hardening_cb_t fn, + const char *hyp_vecs_start, + const char *hyp_vecs_end) +{ + static int last_slot = -1; + static DEFINE_SPINLOCK(bp_lock); + int cpu, slot = -1; + + spin_lock(&bp_lock); + for_each_possible_cpu(cpu) { + if (per_cpu(bp_hardening_data.fn, cpu) == fn) { + slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu); + break; + } + } + + if (slot == -1) { + last_slot++; + BUG_ON(((__bp_harden_hyp_vecs_end - __bp_harden_hyp_vecs_start) + / SZ_2K) <= last_slot); + slot = last_slot; + __copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end); + } + + __this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot); + __this_cpu_write(bp_hardening_data.fn, fn); + spin_unlock(&bp_lock); +} +#else +static void __install_bp_hardening_cb(bp_hardening_cb_t fn, + const char *hyp_vecs_start, + const char *hyp_vecs_end) +{ + __this_cpu_write(bp_hardening_data.fn, fn); +} +#endif /* CONFIG_KVM */ + +static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, + bp_hardening_cb_t fn, + const char *hyp_vecs_start, + const char *hyp_vecs_end) +{ + u64 pfr0; + + if (!entry->matches(entry, SCOPE_LOCAL_CPU)) + return; + + pfr0 = read_cpuid(ID_AA64PFR0_EL1); + if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT)) + return; + + __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end); +} +#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ + #define MIDR_RANGE(model, min, max) \ .def_scope = SCOPE_LOCAL_CPU, \ .matches = is_affected_midr_range, \ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 474b34243521..07c39d1f4479 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -83,7 +83,8 @@ static struct arm64_ftr_bits ftr_id_aa64isar0[] = { }; static struct arm64_ftr_bits ftr_id_aa64pfr0[] = { - ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0), + ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 24, 0), ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0), ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index e6aec982dea9..05bfc71639fc 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -495,13 +495,15 @@ ENDPROC(el1_irq) * Instruction abort handling */ mrs x26, far_el1 - // enable interrupts before calling the main handler - enable_dbg_and_irq + msr daifclr, #(8 | 4 | 1) +#ifdef CONFIG_TRACE_IRQFLAGS + bl trace_hardirqs_off +#endif ct_user_exit mov x0, x26 orr x1, x25, #1 << 24 // use reserved ISS bit for instruction aborts mov x2, sp - bl do_mem_abort + bl do_el0_ia_bp_hardening b ret_to_user el0_fpsimd_acc: /* diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 492d2968fa8f..be42bd3dca5c 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -193,6 +193,8 @@ asmlinkage void post_ttbr_update_workaround(void) "ic iallu; dsb nsh; isb", ARM64_WORKAROUND_CAVIUM_27456, CONFIG_CAVIUM_ERRATUM_27456)); + + arm64_apply_bp_hardening(); } static int asids_init(void) diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 89abdf9af4e6..1878c881a247 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -535,6 +535,22 @@ asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr, arm64_notify_die("", regs, &info, esr); } +asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr, + unsigned int esr, + struct pt_regs *regs) +{ + /* + * We've taken an instruction abort from userspace and not yet + * re-enabled IRQs. If the address is a kernel address, apply + * BP hardening prior to enabling IRQs and pre-emption. + */ + if (addr > TASK_SIZE) + arm64_apply_bp_hardening(); + + local_irq_enable(); + do_mem_abort(addr, esr, regs); +} + /* * Handle stack alignment exceptions. */ From patchwork Thu Aug 29 11:34:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172603 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092206ily; Thu, 29 Aug 2019 04:36:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqwmW5Vn76OZ+SMfyKE11odXi81fysLyVGSBG9dTqPKNGA2ufAh38LRmfH9w/qKzVdGxpBMk X-Received: by 2002:aa7:984a:: with SMTP id n10mr10918849pfq.3.1567078564396; Thu, 29 Aug 2019 04:36:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078564; cv=none; d=google.com; s=arc-20160816; b=MrHRhjq0qvFaxO6Ks3hobYDiUO74ZJv9PZyq7g9QBvxyNQJBuyXHT/b7Hxuc+Je9Wd eL2OEHNsmCeAtDFy02WW27hMcwsmc2ug/dM8AF7QfYfJsgu/w2njdOMqdmw7ibiisOZy SnotobYLSveXISY6RxNkv9Q+zSIclvQSw3M2fhq07hR05Br4ztZZtrpUPV6+HnC9blEU HXLVz5GR0QK4HvvkM34moIEun+Lwy0GND/s/ICKa3NZQRwvsXDbYAlCZIww8e+K1siv8 ipiztd0hHmRL2LrIKd8VYEneWvG58UQb6YxLsF+1Q+uS0RICn8WgRHORwukJcLMhAPV1 x5+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7MRMdAKqkkU6zuM8WMZXIs4D8fug3sxafZUJy2Rr9SE=; b=bsXJefSUWijVLgHyRA4d3HyRCT6YC8noDw+C+9KctdwgJ489T/tfsZ/UP2tCiPTQc8 YTLEeVs3zCqBT9sznm6FeATV8o3OspEjg7la+u0voZSoUz9zte9SEC6eedNQLoeg5+Wh GVN9sZZqg0WR3NNPhnwwBlh1w67wS5DN+Qd/FktT3G0bHd5VwNheJczOwNgYJz9PEKu3 jrPRqigxU6+JOBja7+PeN2Bla6j91OshDKGrd3EBMm5p+sXKWjac1V2gfMeoGif+9sMN 6nPsZd8NR9xH/usRo3iv2UeUYWSiLbxVjhC548wBCkyfIMiki9eOFxBgUwlIn3W5W4ql G3PA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vVyItguL; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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We call arm64_apply_bp_hardening() from post_ttbr_update_workaround, which has the unexpected consequence of being triggered on every exception return to userspace when ARM64_SW_TTBR0_PAN is selected, even if no context switch actually occured. This is a bit suboptimal, and it would be more logical to only invalidate the branch predictor when we actually switch to a different mm. In order to solve this, move the call to arm64_apply_bp_hardening() into check_and_switch_context(), where we're guaranteed to pick a different mm context. Acked-by: Will Deacon Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/mm/context.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index be42bd3dca5c..de5afc27b4e6 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -183,6 +183,8 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) raw_spin_unlock_irqrestore(&cpu_asid_lock, flags); switch_mm_fastpath: + arm64_apply_bp_hardening(); + cpu_switch_mm(mm->pgd, mm); } @@ -193,8 +195,6 @@ asmlinkage void post_ttbr_update_workaround(void) "ic iallu; dsb nsh; isb", ARM64_WORKAROUND_CAVIUM_27456, CONFIG_CAVIUM_ERRATUM_27456)); - - arm64_apply_bp_hardening(); } static int asids_init(void) From patchwork Thu Aug 29 11:34:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172604 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092239ily; Thu, 29 Aug 2019 04:36:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqyrKvAmPw85zpz89ReIjEGw2QzgGSGWruwGY3OqDEpklF/gTwNxOF8ARCgCxMbAzpGktLHb X-Received: by 2002:a17:902:ac86:: with SMTP id h6mr9493460plr.79.1567078566546; Thu, 29 Aug 2019 04:36:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078566; cv=none; d=google.com; s=arc-20160816; b=ol9nJ8MGB4gvUJ/hY/7D3UTOy7YdkYrf7hzTZweR3TtJgtKGg1gCITE+SPMHN/LNjm xPdaW/YIrf0KB6gWq9/s45cNd95kzA6RaFxbYfynYEbBk3myUNET9E23Nmn7qndaBTuS DUhPtxapAwgpN/UFb6529dudeAzOIqSSLiiEFtrpGVxPpfmba9BAjyYGXpdt2P/jlDAZ g+NNLUDDmIw69/ZLZvQ/0IST1/qE5/yVbGnAxhFrUarfrmmBpAqJJmZpvYnawndRc0N/ 5n7D+4YHCQ4s/jSU/ZVIRCuTO4Vg9Dndiv1Rfm7dIkacBDnWVKl7BxbbrjD5QbpjQCcj aIWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=y6GazOWQm4IOOc6xrMbLHqM6mIdOvxmzg2BIOtMFGqg=; b=KOkxFyp74dMxTgyU7wpI+i5Q7KCYFpTHwF6pO3hpCsp597+C2ihpPts3zOaKdBrtsE /u8LTkbxHWs6MWV//YLxgY6SXgecLoBpnP6w5sMTg6Y9XgJkDw7P10hXr6AOCTp31cHf uXUa6q7ME27PqjWMoNhtGCfYqeqACRKuEeJNZVnqhcLIRdaKXHJB4ZiCtkY8uadAA89/ mQ0VBlGWYOGdfgrRQf9RnNkFIcHs9/HDv2edTK9CAVrOKLyS79SN44Qn9BCZqJca/beM lnr1apwpKDzeLbIzfHEB2S6N6kZT0lCFi1X3sRgAsvwGPRqFqdBgUuOszosNP0kWgMaP QIXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LyNvyEL5; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c67si2276378pfb.211.2019.08.29.04.36.06; Thu, 29 Aug 2019 04:36:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LyNvyEL5; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727500AbfH2LgG (ORCPT + 14 others); Thu, 29 Aug 2019 07:36:06 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:34935 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727421AbfH2LgF (ORCPT ); Thu, 29 Aug 2019 07:36:05 -0400 Received: by mail-pl1-f194.google.com with SMTP id gn20so1458748plb.2 for ; Thu, 29 Aug 2019 04:36:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y6GazOWQm4IOOc6xrMbLHqM6mIdOvxmzg2BIOtMFGqg=; b=LyNvyEL50rTrdkIjipcrLCUtIh4hp0sPiDDZNm2ss9LdOgbQO2Z5KQJOoEpkvAXgJp 2QpodfuPyGGaNRQadqdv3j4PfCLK26hknY1obYrHuUurdxwNueTidXsjcit+3hLKtwUU YJlmFFKYU1L5PDFxZLaGsjkMsWjdNOHI9EBneFPah8x5LtE4AejBca8qWlYGVNSlThKx ni6xB0phzYbDpMgrCZkMABWszq7FpzhMhJTOv8FHHzGtpsLIE82jHJ+YifCYESWcpIRk l6ayd71M7UMDayZrv68qBPQeQtbsYENCskRHqqVefLjRudwLeNUS4vpNxFHaYW0av0Wo zolQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y6GazOWQm4IOOc6xrMbLHqM6mIdOvxmzg2BIOtMFGqg=; b=kRtPlZ2Aa6PfAr8CU4Z1D9/+yIvA6XecVDp4iPP5pl6QAy0ZoA6ZomIvh1e0ypLXjC ScDRH0zMesd4UacAQGf9Y6EeGpyoTsF2wRJGjMb0Gl2TYVb6Sbpuv4GBPXx69guaXGZQ ZDbermqOGww+x9CHPJjkg2yF1xwY+0UViVJ/TXgrm2GoAwtkSuxolq7K0AZT+A3HAjwF 9yypXFyb95MqPSMxmFguCZMjCJVBl/5HY4faRythqYUOzT7ruOsh1gSdQhWryBFGnTw6 w+uPiLFhm/Tzjbv3L1ShnDZlEzLhhXspicW5zzj9xx+gvJjLfFmx6EE0VyP5lpwSJvU7 hniw== X-Gm-Message-State: APjAAAVbAPEYTxAjtzXc50yXn7Mqw+MPXBJCDQQl2mxgu8DiVdc/n5YC /bX+ycrduNDJYshnYGQdVrq10oOPnDo= X-Received: by 2002:a17:902:fa5:: with SMTP id 34mr9509568plz.285.1567078564877; Thu, 29 Aug 2019 04:36:04 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id 4sm3138639pfe.76.2019.08.29.04.36.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:36:04 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 27/44] arm64: entry: Apply BP hardening for high-priority synchronous exceptions Date: Thu, 29 Aug 2019 17:04:12 +0530 Message-Id: <711165f3d8dce609dfb777b3705fe1b58ca237cf.1567077734.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit 5dfc6ed27710c42cbc15db5c0d4475699991da0a upstream. Software-step and PC alignment fault exceptions have higher priority than instruction abort exceptions, so apply the BP hardening hooks there too if the user PC appears to reside in kernel space. Reported-by: Dan Hettena Reviewed-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: Resolved rebase conflicts ] Signed-off-by: Viresh Kumar --- arch/arm64/kernel/entry.S | 6 ++++-- arch/arm64/mm/fault.c | 9 +++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 05bfc71639fc..42a141f01f3b 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -530,8 +530,10 @@ ENDPROC(el1_irq) * Stack or PC alignment exception handling */ mrs x26, far_el1 - // enable interrupts before calling the main handler - enable_dbg_and_irq + enable_dbg +#ifdef CONFIG_TRACE_IRQFLAGS + bl trace_hardirqs_off +#endif ct_user_exit mov x0, x26 mov x1, x25 diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 1878c881a247..082f385b6592 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -561,6 +561,12 @@ asmlinkage void __exception do_sp_pc_abort(unsigned long addr, struct siginfo info; struct task_struct *tsk = current; + if (user_mode(regs)) { + if (instruction_pointer(regs) > TASK_SIZE) + arm64_apply_bp_hardening(); + local_irq_enable(); + } + if (show_unhandled_signals && unhandled_signal(tsk, SIGBUS)) pr_info_ratelimited("%s[%d]: %s exception: pc=%p sp=%p\n", tsk->comm, task_pid_nr(tsk), @@ -621,6 +627,9 @@ asmlinkage int __exception do_debug_exception(unsigned long addr_if_watchpoint, if (interrupts_enabled(regs)) trace_hardirqs_off(); + if (user_mode(regs) && instruction_pointer(regs) > TASK_SIZE) + arm64_apply_bp_hardening(); + if (!inf->fn(addr_if_watchpoint, esr, regs)) { rv = 1; } else { From patchwork Thu Aug 29 11:34:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172605 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092288ily; Thu, 29 Aug 2019 04:36:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqws0ReeJ+UwxatzdXj6dEtJKch7ILvnGtIYJu8wf8hczSqIhkSVF8rDoYgqJADrWe9sBu66 X-Received: by 2002:a62:ee0e:: with SMTP id e14mr11035031pfi.31.1567078569110; Thu, 29 Aug 2019 04:36:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078569; cv=none; d=google.com; s=arc-20160816; b=Ue6t7C+IBQOcr6W9fWwi90kYWEUkftSlhUfUUVFCdIeYA8AlWUIENuJS6GqF87zZLM AUISutUwLjnuxkNnyKzVcDTKe6Ifxse0vpnwjQ7OK8kpUZt31smD+kFrav5H3XCgZoY5 PiiWIDLyoN/CDDw/lDv93T0dw1qeP7+pxP9DuPQK1UPvgPaIlU+LeJQtzXnjYuDTLRnA FJw3kXtO8z3Ob8q5CFdIpAd8Y0T0DrzdaZ94GA6wQRf1DiZhBkofN1yfgflHO7naYDFI 8SO15uTzyOuXKnmKYXV49qWNh+YbX9cU9q65CAmXe0Dqhukm0k7misXA3Lvm0OktUyoZ 6kcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kL4bvpTkIxzXH8Y5LirqPgKQFts/fgCJz2Uk/H1BBsA=; b=C4FodW4EFQ3CAlem56IRDl27AA6ofxj89LlBBBotK/IYMgc3M/81nNp6lgjdQkrgUr n9pi5yjeALjOtB1oqwPzCymkoIRVXcDNYILwRq12cH27ppc2zmbAy2uX73/9cFG1TrlN HaNZR0yWTvrU0NkTukRwFn1y67oJ9Sqb7gkhlQuuEd5Nt4xE7xT7vG3J5grBvrJGysFF /N9G4dO3IOHyVmhozOrG9KMd1S2UfsQpdhGM+OWkOQtn2h8+POFZjvrpbGiJE0vV5cVr 22oertH7uGR9mpm3VbCc81T24PSnbPMKHEIYoh9v6X++dUmi7xqvbmfPaoGs6EdL96v2 ndRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uQR2nK9A; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c67si2276378pfb.211.2019.08.29.04.36.08; Thu, 29 Aug 2019 04:36:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uQR2nK9A; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727087AbfH2LgI (ORCPT + 14 others); Thu, 29 Aug 2019 07:36:08 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:46132 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727072AbfH2LgI (ORCPT ); Thu, 29 Aug 2019 07:36:08 -0400 Received: by mail-pl1-f195.google.com with SMTP id o3so1429115plb.13 for ; Thu, 29 Aug 2019 04:36:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kL4bvpTkIxzXH8Y5LirqPgKQFts/fgCJz2Uk/H1BBsA=; b=uQR2nK9Abh6tvSTERRD5xBq9uwIxsZobXq4VEfEob3EK6BxdIufTOc5Wx3Y/FVU4uc JWR1NrqBH7lUEVzldljV3kwsB+S09nQFWAzzaR3VX9uxPnRn8IXDKjrv2CwTLnMaYHYb /Oz0Ek425YEemXc/7qOYG6eSOdf2MaBTXINhNAnGlqFpjO/CPx6xeW4x0phOm4w4AAnU MhjlHro4CJmTRlEKwdlqXVEI9OZZvBTPuJbLamLy9gPjCo8VToC1yGgADlXvtZjfOZ+b io0G7yJ1Xb4O27IQJpP/v2qJpHKzTFev0xrvzTrIGNbhswhr+mNOJcu8WS95sQRWCZb8 blkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kL4bvpTkIxzXH8Y5LirqPgKQFts/fgCJz2Uk/H1BBsA=; b=ejLIbnrZ3SpNp5XEkKPad4u/MsSfEfDsBflVpKhDH1jX+jg3/edNIkR0ljz1I46WoM NsVKsBBmVX8L8NIJiaSQudyvisHMcdL2xXE6mJhaDD3s2pW3D4CGqqEUnz7BCuUvFVqQ MSKzPerptVcksG4ll2UTxQpTIVU4P/q8ORmltrC+T2h7xRxxlTKXmDAt8n0gaWhq7NdL pTlzeO3iViXw/sjYpUGQK3KEAWFIBzJSm9RdD1Mjdp8D4qav/Aqc7BppEbY78HOacVxO ouuDmvF1X9Kvu69w9Rd0Tzt0RSlE2ZjA7JMHHcMj6Wnzbfd5vZ1e08If01iglrm+2wsg LHuQ== X-Gm-Message-State: APjAAAWJRkpMTysuVz7W2CyjMhU6SIWSk48HdmIbVANQ7W4zvGgWbTex qeW9es8aDK9lhGgzCSwypd2EA3d04Gs= X-Received: by 2002:a17:902:7c8b:: with SMTP id y11mr9687584pll.259.1567078567353; Thu, 29 Aug 2019 04:36:07 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id g14sm2587953pfo.41.2019.08.29.04.36.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:36:06 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 28/44] arm64: entry: Apply BP hardening for suspicious interrupts from EL0 Date: Thu, 29 Aug 2019 17:04:13 +0530 Message-Id: <16be0cb9c5bbcff5cfe74cf8d47c5a4084e45b5e.1567077734.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit 30d88c0e3ace625a92eead9ca0ad94093a8f59fe upstream. It is possible to take an IRQ from EL0 following a branch to a kernel address in such a way that the IRQ is prioritised over the instruction abort. Whilst an attacker would need to get the stars to align here, it might be sufficient with enough calibration so perform BP hardening in the rare case that we see a kernel address in the ELR when handling an IRQ from EL0. Reported-by: Dan Hettena Reviewed-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/entry.S | 5 +++++ arch/arm64/mm/fault.c | 6 ++++++ 2 files changed, 11 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 42a141f01f3b..1548be9732ce 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -582,6 +582,11 @@ ENDPROC(el0_sync) #endif ct_user_exit +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + tbz x22, #55, 1f + bl do_el0_irq_bp_hardening +1: +#endif irq_handler #ifdef CONFIG_TRACE_IRQFLAGS diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 082f385b6592..9ff48d083c4c 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -535,6 +535,12 @@ asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr, arm64_notify_die("", regs, &info, esr); } +asmlinkage void __exception do_el0_irq_bp_hardening(void) +{ + /* PC has already been checked in entry.S */ + arm64_apply_bp_hardening(); +} + asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr, unsigned int esr, struct pt_regs *regs) From patchwork Thu Aug 29 11:34:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172606 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092342ily; Thu, 29 Aug 2019 04:36:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqxHop7yk1ntQvSGJsz1sLJeeevglTVR3vDX83ZQH3G5hRYfZ8H1Bka1uxFGxvWc5WR4nqxg X-Received: by 2002:a17:902:7d98:: with SMTP id a24mr9101196plm.139.1567078571902; Thu, 29 Aug 2019 04:36:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078571; cv=none; d=google.com; s=arc-20160816; b=f8EF5HipHNCMP/AS4aZIvSV6pM11p+uGbjcfZbbz6RjbMZQlYS763XLSpA7ioN3KMQ 6Conw+KEn/5T7qM/Ekuel3fdTQGTn3NIaqK+fc2E5EEL3HReGnQ+pdlXDfMtjMqFzyow i9TatEmkCE4wWl4uezjftHORZfBCAaSunSFhLzzJ4F2J2aoD5dEVJZQvvAZJv9QQfgZE AN2O3334VUbfxdkw483ft26Ix+msJ6tri0wzbj8El74Ixh+WDHj3dWAUQA25y2nms4Nh 1qTvslWMc3G9f1lOMrZM+6uGy0yocao/+tCVxbobM/3hUEZ5mlIuX5gjaBPc5wfXjauH bkTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=D7dDso9mEizkFlSNIpcQXEVsYMAg+0dXCi9osCif4dQ=; b=SuKjHeFhcA3oAXsJC2q67lZkS6SF6PrKeKL8TIRgGUn3t8FflTEObVf3dXsslFs1dC TLU4Yo6moAl9fhvWoJtiGR61ms0iBL/p0UCmtmCFJYu7BTXUAhCaHpohXNJD6DuNbb75 3Wm89ueBrE0wG6ntjcGmggMknnh/4U83QjkD9fNpVlwLbIGdlkj0eKmFP9YUtq/qqkfv coifI0+2PZZQgxJPXnGu4SPK4wt8LvusV0X7KkLzc1UvwNxVngrWDNv2uW0g5kv/caBZ 8gc5PBvtj+zeEzFAE032QEyP/99PhehJi2Bct6HZxLb1S8WPxm07n9zVixe8+c8c6MnK Pz9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ARrmgjAQ; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c67si2276378pfb.211.2019.08.29.04.36.11; Thu, 29 Aug 2019 04:36:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ARrmgjAQ; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727072AbfH2LgL (ORCPT + 14 others); Thu, 29 Aug 2019 07:36:11 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:41830 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727065AbfH2LgL (ORCPT ); Thu, 29 Aug 2019 07:36:11 -0400 Received: by mail-pf1-f196.google.com with SMTP id 196so1857010pfz.8 for ; Thu, 29 Aug 2019 04:36:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D7dDso9mEizkFlSNIpcQXEVsYMAg+0dXCi9osCif4dQ=; b=ARrmgjAQyWJ3A4H4QgsubRRxM85gcS37EsYBleh0p2pXl6UY9hbPYZcOyuJR3mVRa9 +QWoqI+LoqVQna7nhm7rI1cOu0XOtVBblELb8gpt7GtH7GBQ0foQJEzZIzr88uCClaBz qqFVG+I6NBY9BKoxQvSXqR735A5i1oKRwChtj3giEyO112Yb7ZenwG7LdlyGoK36dazL i3RsOyEsdSdbIKPtB6BV3CiElXyPRHj2rPUdopOYNYkggTMGIbFMNZn4/cQOvl5+Lalf aTpS/LgRJqgkQBfqjcrbCbJO0To4tgT8DZMiY8o1G3IakSjVFzJigRQkKNepKEymVTz/ shNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D7dDso9mEizkFlSNIpcQXEVsYMAg+0dXCi9osCif4dQ=; b=RFvaObLP3q/IlrFwwDVp9S12u9m7bUHYd3j12s4+3kTrslh199h1lQFSVzlsMW9OJV c836eWsV7T2az5A/Zytf+KeBBRPjAPVAWz7va7/gK7OaCm9feVDFg9V6XiE1DhYCh0W3 PYnqqQfQe8HG6gVU1FoCKN6Rd8hmQo1q4X+8R3QJgzddm7rMYpMNgBAsN4Q4lYqosbzg AQbOvUgyLHGL8VNGDKHgd7QyDwFcGAOlX2i+9frJya5etR5aQYW2efQxgw/tX7S+qJ3b n6QNyNxo+7xh2jKZk6pZzPhj4/STXLqpc/fWxB/yNadH3QUxKAxwh8IrRgYg0p1U2+4W /30A== X-Gm-Message-State: APjAAAXZ6Hk85P+XQwS2sKOys38x0p0KfBCekV7KE3nS507COwZCV1FR IKNxZ5y4mN6XICuj0WvpI0GNS5psOSU= X-Received: by 2002:a63:20a:: with SMTP id 10mr7790456pgc.226.1567078570025; Thu, 29 Aug 2019 04:36:10 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id y14sm1899716pge.7.2019.08.29.04.36.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:36:09 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 29/44] arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75 Date: Thu, 29 Aug 2019 17:04:14 +0530 Message-Id: <6b46a425ec244a76a7cebf5e1cdfa6e1d0a6c7a8.1567077734.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit a65d219fe5dc7887fd5ca04c2ac3e9a34feb8dfc upstream. Hook up MIDR values for the Cortex-A72 and Cortex-A75 CPUs, since they will soon need MIDR matches for hardening the branch predictor. Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: Add A73 values as well ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/cputype.h | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index f43e10cfeda2..2a1f44646048 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -77,14 +77,20 @@ #define ARM_CPU_PART_AEM_V8 0xD0F #define ARM_CPU_PART_FOUNDATION 0xD00 #define ARM_CPU_PART_CORTEX_A57 0xD07 +#define ARM_CPU_PART_CORTEX_A72 0xD08 #define ARM_CPU_PART_CORTEX_A53 0xD03 #define ARM_CPU_PART_CORTEX_A55 0xD05 +#define ARM_CPU_PART_CORTEX_A73 0xD09 +#define ARM_CPU_PART_CORTEX_A75 0xD0A #define APM_CPU_PART_POTENZA 0x000 #define CAVIUM_CPU_PART_THUNDERX 0x0A1 #define MIDR_CORTEX_A55 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) +#define MIDR_CORTEX_A72 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) +#define MIDR_CORTEX_A73 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) +#define MIDR_CORTEX_A75 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) #ifndef __ASSEMBLY__ From patchwork Thu Aug 29 11:34:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172607 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092392ily; Thu, 29 Aug 2019 04:36:14 -0700 (PDT) X-Google-Smtp-Source: APXvYqyhVp+rmi3MzlLoEFSQBhnNHPpM82VsufBc5/Z0iNrev5ZOipfLI+mc9jzKEMICqAaV1gXo X-Received: by 2002:aa7:90c1:: with SMTP id k1mr10542578pfk.46.1567078574517; Thu, 29 Aug 2019 04:36:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078574; cv=none; d=google.com; s=arc-20160816; b=bt4edFYnMlxohe/02nSaT8rt69eIB9XwtBA7G0/zc6QP/Joq/YD5Isy1STXadY/Mbp P1Iiywqa+0Q3b89LrFDefSyusOqVuUBj3YuJ6/lN18ww9ewwx3GNyaNR8sx17ahhAQId gCbkgO5auv/kkOGHSzHmUhGboufofL2IUN4sCE9/IHtTdLl5dIZs8UGsE6qW9JRkKUUJ KN2O/fXuvcKXZkrzw8Y3lrQT/yjLdJ5+vG+dUeJHkaWVXKKLZ5uqBNW7oIRBI9CQuV+t Acc0nhQ9PwFY44FMhdZKsVCW19kZ5dhauLF8L0WtsqhluMHVWW+CS2HwFtsiuwUIt4Xv kOew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=sqSfnQDS8sjUZN/3AxA8S/yruKf46+OQJxAy5E4hEak=; b=MRAvgmfxzpMRwFk3Jd8vORc6aPcR/Uu+8OCi9oZXIuUMSY7qMSHW/g0zd69gaFM1ZU FRC8WSKqA9Q0vnhpciKxhsGcUk+O2ZofNbd0KRnMthbuBOOwhP9dxNQMgtGvBbFfbQo+ t/xvF7KBHi/RbYh/qHT6Ksrix7a6nPiAXuxLKsfMdd13+bq76majuVChLz6abcFzbBMj icPGSfVsyVMu5l0E8xIcY6OFOx3tRo4abpWW8P3znkDoY/g1PLxImVgy2P++2lH4F2Zx GXbshKz4BrawOgxce3vyEwsZN8HmQry2sjx7nESHIA7g4IXQq4dwdlSu2FYMn0rs3rCo okbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mcZvlnlT; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c67si2276378pfb.211.2019.08.29.04.36.14; Thu, 29 Aug 2019 04:36:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mcZvlnlT; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727122AbfH2LgN (ORCPT + 14 others); Thu, 29 Aug 2019 07:36:13 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:34944 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727066AbfH2LgN (ORCPT ); Thu, 29 Aug 2019 07:36:13 -0400 Received: by mail-pl1-f194.google.com with SMTP id gn20so1458889plb.2 for ; Thu, 29 Aug 2019 04:36:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sqSfnQDS8sjUZN/3AxA8S/yruKf46+OQJxAy5E4hEak=; b=mcZvlnlTjxDEMpsXVxgZHCis3EpF9YKEnl0Ae7vuyVNS2u5DsBmOpKu/RfyQY4zst4 WJ6II+4t9IB2/P5txc1C3I3Np7nADPSzcXWHbYbRQ5mjaMV/Q70uDa1eXdwLx4L/H1LE h2/Z87csKjZVXK2Jk3u43fy7aoYHA+l58kS+mcD5zTVL2tNNGwHuC6GbGWrQVIQ90jvt aa+QaAM01GJcJeenk3D8K0YFFYwl1QQfsaBPmiHcBmnF9TfXbkRBjff1fVlefRtMNNhn YS1V3p06jYuC6sbH3f2RCtKxaMrWYTkXD2GmUCqwfUvFV0t0KJruEDE5MJpqDswVGQ9H m6Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sqSfnQDS8sjUZN/3AxA8S/yruKf46+OQJxAy5E4hEak=; b=iWxF2D4NyzIAZ2rmflDNYmZ2uXwhkcsTj9CtrYy6x8hWMtG+C/KgynsN1hTtEb+Lui G3Uct2QbwPD4+brWaD7rTgxX9lB/DSzP6aCEO9BHV1J54eYu8LJTjPTJefi+EcswctkB o64uBhCHWzg/JrgpTg81vxKrY2Sll+CTLM7UVpKWAHIbaEH5wsaI/kw9JZC+2kFkK9pG CjWxtUBDbrwoE8pan83Cy9Q0Y0ZOTkWORHtE3IQcAAxkN9JB2mhMfqcCT4lNuIiHFflH FoeR6M+lUzq2FuXSo1Is1gTjg1LaajrNtl3TlYQZx77nsMOVA+TiDJMZwePw3fAvOIFH 4vYw== X-Gm-Message-State: APjAAAUUoxUN3AX4tVFD8qmKhB3JNEenBUwJX/j4qsZzoc96UbFhW3C5 otroOn5uQJMOnL5Rtq5iQEMbvHJZO4Y= X-Received: by 2002:a17:902:74c7:: with SMTP id f7mr5308584plt.263.1567078572662; Thu, 29 Aug 2019 04:36:12 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id e66sm6401987pfe.142.2019.08.29.04.36.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:36:12 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 30/44] arm64: cpu_errata: Allow an erratum to be match for all revisions of a core Date: Thu, 29 Aug 2019 17:04:15 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit 06f1494f837da8997d670a1ba87add7963b08922 upstream. Some minor erratum may not be fixed in further revisions of a core, leading to a situation where the workaround needs to be updated each time an updated core is released. Introduce a MIDR_ALL_VERSIONS match helper that will work for all versions of that MIDR, once and for all. Acked-by: Thomas Gleixner Acked-by: Mark Rutland Acked-by: Daniel Lezcano Reviewed-by: Suzuki K Poulose Signed-off-by: Marc Zyngier Signed-off-by: Viresh Kumar --- arch/arm64/kernel/cpu_errata.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 19c51d1cd302..80765feae955 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -124,6 +124,13 @@ static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, .midr_range_min = min, \ .midr_range_max = max +#define MIDR_ALL_VERSIONS(model) \ + .def_scope = SCOPE_LOCAL_CPU, \ + .matches = is_affected_midr_range, \ + .midr_model = model, \ + .midr_range_min = 0, \ + .midr_range_max = (MIDR_VARIANT_MASK | MIDR_REVISION_MASK) + const struct arm64_cpu_capabilities arm64_errata[] = { #if defined(CONFIG_ARM64_ERRATUM_826319) || \ defined(CONFIG_ARM64_ERRATUM_827319) || \ From patchwork Thu Aug 29 11:34:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172608 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092430ily; Thu, 29 Aug 2019 04:36:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqwsGlAA9Iv2Lb2H1UOMoJo9oY7tuU3MOhYq+ODsZ+hG9B2jwebaZlpQ7k7kHOhvOzZB4MH8 X-Received: by 2002:aa7:8a83:: with SMTP id a3mr10736247pfc.115.1567078576930; Thu, 29 Aug 2019 04:36:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078576; cv=none; d=google.com; s=arc-20160816; b=DRWmlkzo3DITfC0GRY0xtGrFuJDRRq6zwM/YHxaBGGdFvgfTyOqho6xf0wLCSQDENo cRXy0VpsnBbIeRKf2RcsuGcGAsn7t5kvRXJdot/ojYIXBWl1TmcgKiFnw8E3aIcBRArc d+KgRmuprszOQiWsZ6iUdFMK3BW4HoEO2CWCrru2Ze9QoavlernLNtKYAzVrEXR1zMw4 DbrGn8n6ArF5E3+nfbJ11+kPFftmyCemTFBQsgvT0mNHfRy6Hzgb84wkE9uFUBwyvl3s SvusbtU+zDZrFpq9TIcyxQHwOtxgR7ovRElIKtnALIDzLNmQT+0eaQp2mbz2qy6PmAlY xt0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mSGnDnoJppey6/ef3bclxREaifXq44bcCaQXzmdFJKI=; b=PoXGDTTqKaRPCuEFLnDTd+RPZE0DH4w98D0ak/rJMUoTU+CDL8IBZvJdoB1VRycHAy IMMuPT5bjujavKV/mrpV/iItwpw9SMPMaY9pAm+69rklisp+ohGFdYFD04mh5sUphn07 pXa1wglCzsjm471SOcV5Be7znjk9DscqCJXKh2xJ4rPm6pWBn629N+lGQeRcQU0qReNk /Zu8aFHeaYpKA6U/lbOQ8XCYlSauLozAtlYB8q7BDwk3iblwLDr8TDmZaX7CcbkvfNSf MJabXMYhk4E/vWhogpexFsHqXdCQLIVZ+35lqo5laSgwZUluP6BEgllPyAdrP3G7hm0K TYEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nXcOnYdY; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c67si2276378pfb.211.2019.08.29.04.36.16; Thu, 29 Aug 2019 04:36:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nXcOnYdY; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727308AbfH2LgQ (ORCPT + 14 others); Thu, 29 Aug 2019 07:36:16 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:45937 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727233AbfH2LgQ (ORCPT ); Thu, 29 Aug 2019 07:36:16 -0400 Received: by mail-pf1-f195.google.com with SMTP id w26so1847126pfq.12 for ; Thu, 29 Aug 2019 04:36:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mSGnDnoJppey6/ef3bclxREaifXq44bcCaQXzmdFJKI=; b=nXcOnYdYMdRjWarWiT6SdA55JtdySdi8Xl5GquX5MxjKkQzJ9KFmEQOzRPFYPJRpSr wcuvNVoh2ZQkX3w9Jqr+g20rf272MKrogLKH2Wrfiys31R+f+e0s7EyJHAR4Kso0QYIS D62puFY/Dy7VzsKWWPCHiYGubvMeKmzHHbTV2hy0Q1t2neSTTqrNWBUjJ7J2NFNyojm3 fAeRLY7nruyHOH+YaJ6yqANeyXlx7xxx7AkgtM4lgAPhxc4CdzNBWyE094lmFoa2YSnv J1AOKcOp+FBmNBohefYmwPPT8iW56v6bLb33jf1J+pliVneLKuX3WU7741dOLqkstbL6 KWeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mSGnDnoJppey6/ef3bclxREaifXq44bcCaQXzmdFJKI=; b=pV4Nu0ggnSlCaykQ/7zJ/FkqWyn1TF7ZYnAYRQMkEuZ1VAZpqL/YdM+6fTCi52Geut KqJ/CtD0tY7kLMHfjgy7qNY7FRhp/MnZ0Cwh8JiK25vUMeHMWJj+/R1Zdr/7Hkk5CJ2n ppiJM32WRZWBm8fbrNOse16OQ36Ga8ueSGGVi8aCjg/OgHJ1mBWtzhkh0N4jK3YOnFA8 nHC5LdF2DlhU+uKCSMdpD+IKvPUfaFBLD3SA8yCWrzohH05jiT2hexV9ETRqrBNRYvgC tL6MeoU6oGu40qMIIc0euRs0reDsxpzExuI9CKgqEyF1OYLA2EgF6q0IQH9dZ9NX90jh G4GQ== X-Gm-Message-State: APjAAAWBcrN5DfaUFe8zgl85u4r/uvyFz1mFUpYqsJzl7+ky3CmJ/bm3 mHziXkPPAKoBDlw+7kgL8PGvYt+QzNw= X-Received: by 2002:a17:90a:8c94:: with SMTP id b20mr7222310pjo.127.1567078575132; Thu, 29 Aug 2019 04:36:15 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id u4sm2734902pfh.186.2019.08.29.04.36.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:36:14 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 31/44] arm64: Implement branch predictor hardening for affected Cortex-A CPUs Date: Thu, 29 Aug 2019 17:04:16 +0530 Message-Id: <13a05e3ef8a5b63df9eae88bc995f81c925e81fc.1567077734.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit aa6acde65e03186b5add8151e1ffe36c3c62639b upstream. Cortex-A57, A72, A73 and A75 are susceptible to branch predictor aliasing and can theoretically be attacked by malicious code. This patch implements a PSCI-based mitigation for these CPUs when available. The call into firmware will invalidate the branch predictor state, preventing any malicious entries from affecting other victim contexts. Co-developed-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/bpi.S | 24 +++++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 42 ++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S index 06a931eb2673..dec95bd82e31 100644 --- a/arch/arm64/kernel/bpi.S +++ b/arch/arm64/kernel/bpi.S @@ -53,3 +53,27 @@ ENTRY(__bp_harden_hyp_vecs_start) vectors __kvm_hyp_vector .endr ENTRY(__bp_harden_hyp_vecs_end) +ENTRY(__psci_hyp_bp_inval_start) + sub sp, sp, #(8 * 18) + stp x16, x17, [sp, #(16 * 0)] + stp x14, x15, [sp, #(16 * 1)] + stp x12, x13, [sp, #(16 * 2)] + stp x10, x11, [sp, #(16 * 3)] + stp x8, x9, [sp, #(16 * 4)] + stp x6, x7, [sp, #(16 * 5)] + stp x4, x5, [sp, #(16 * 6)] + stp x2, x3, [sp, #(16 * 7)] + stp x0, x1, [sp, #(16 * 8)] + mov x0, #0x84000000 + smc #0 + ldp x16, x17, [sp, #(16 * 0)] + ldp x14, x15, [sp, #(16 * 1)] + ldp x12, x13, [sp, #(16 * 2)] + ldp x10, x11, [sp, #(16 * 3)] + ldp x8, x9, [sp, #(16 * 4)] + ldp x6, x7, [sp, #(16 * 5)] + ldp x4, x5, [sp, #(16 * 6)] + ldp x2, x3, [sp, #(16 * 7)] + ldp x0, x1, [sp, #(16 * 8)] + add sp, sp, #(8 * 18) +ENTRY(__psci_hyp_bp_inval_end) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 80765feae955..dbd7b944a37e 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -50,6 +50,8 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); #ifdef CONFIG_KVM +extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; + static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, const char *hyp_vecs_end) { @@ -91,6 +93,9 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn, spin_unlock(&bp_lock); } #else +#define __psci_hyp_bp_inval_start NULL +#define __psci_hyp_bp_inval_end NULL + static void __install_bp_hardening_cb(bp_hardening_cb_t fn, const char *hyp_vecs_start, const char *hyp_vecs_end) @@ -115,6 +120,21 @@ static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end); } + +#include + +static int enable_psci_bp_hardening(void *data) +{ + const struct arm64_cpu_capabilities *entry = data; + + if (psci_ops.get_version) + install_bp_hardening_cb(entry, + (bp_hardening_cb_t)psci_ops.get_version, + __psci_hyp_bp_inval_start, + __psci_hyp_bp_inval_end); + + return 0; +} #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ #define MIDR_RANGE(model, min, max) \ @@ -192,6 +212,28 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_RANGE(MIDR_THUNDERX, 0x00, (1 << MIDR_VARIANT_SHIFT) | 1), }, +#endif +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), + .enable = enable_psci_bp_hardening, + }, #endif { } From patchwork Thu Aug 29 11:34:17 2019 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id c67si2276378pfb.211.2019.08.29.04.36.19; Thu, 29 Aug 2019 04:36:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xvti4GEQ; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727421AbfH2LgT (ORCPT + 14 others); Thu, 29 Aug 2019 07:36:19 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:41761 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727233AbfH2LgT (ORCPT ); Thu, 29 Aug 2019 07:36:19 -0400 Received: by mail-pg1-f195.google.com with SMTP id x15so1439707pgg.8 for ; Thu, 29 Aug 2019 04:36:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=s6UKYk23he3dGgebGJrG3RauZikPx4goXsUxb0kpSkg=; b=xvti4GEQ0/UPk2nKKLyO2tTOZPg7+31lw96qhbCVrk3QdQo4q4HNqbarF3AYx73djD V5arFRASUiOZIduD8dflJdHV2Nd9NMdb/daV+e+zGAsfXaOgWF/DLP7TzshTPE7EtJ+I sbhroYXEYVv+nS26O7sc8qM7ZOEMZT/V5bMtiDWFA2lsa8bZ8xDLtcnM9lzolhWMuBNJ Ao7Fne0gvklPDie5i5YFRhMjZzETIoVSv8Ve4igx3A5V5Hn7zrjFHu6RIFY9BfGl7R+C 8qFaRLGk6xC4U0Evaqi1ejKpFDEcSjJ47F1a6IKa6MT+fLoe9IbnBBbQgwgNMQkktr46 sHqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=s6UKYk23he3dGgebGJrG3RauZikPx4goXsUxb0kpSkg=; b=S79OcZ1xTx8cbhJ8sBtjiowvs7bXAbhNsGhxqKoaFG+wRi4GnKWXeIr8ia1Lkr+n8U vUSgzTtw2C9vKrTlInZebdLPEjOw/nSEeWDQmlQ39/pAMYR4IeKvm4d98Wmo9O7I/kEm 6vRIfA998UCe/QVgjyZfjwvApC+pPhP/uVgescpUEEHqWYnbMHISbHJGifACzV2COaz9 vxJVrR0l44oFrkQ4N9BY8t8MRyCncPqSBRiTNHa3YEaXxNIaHL3GPPr9lxt2zwr1bIAZ hxxG68IMKwvjB9bx7TnihIp0MDkAMoGpMnqP6Je2ph0qCztvzLZ29Xb3tjxDQWHEI4Si TN5A== X-Gm-Message-State: APjAAAWSPhpCF3Q/rf2sTLgNNcSai9nahgQNpikiA98lUVuHWcVLK/gR aZxPiKhjM/fzbH8bHixMi9wDtpJiQ5M= X-Received: by 2002:aa7:91d3:: with SMTP id z19mr10725682pfa.135.1567078578038; Thu, 29 Aug 2019 04:36:18 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id u7sm2042123pgr.94.2019.08.29.04.36.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:36:17 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 32/44] arm64: cputype info for Broadcom Vulcan Date: Thu, 29 Aug 2019 17:04:17 +0530 Message-Id: <245df11a4507b678b87e3dea9116afd23f7b0041.1567077734.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Jayachandran C commit 9eb8a2cdf65ce47c3aa68f1297c84d8bcf5a7b3a upstream. Add Broadcom Vulcan implementor ID and part ID in cputype.h. This is to document the values. Signed-off-by: Jayachandran C Acked-by: Will Deacon Acked-by: Catalin Marinas Signed-off-by: Florian Fainelli Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/cputype.h | 3 +++ 1 file changed, 3 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 2a1f44646048..c6976dd6c32a 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -73,6 +73,7 @@ #define ARM_CPU_IMP_ARM 0x41 #define ARM_CPU_IMP_APM 0x50 #define ARM_CPU_IMP_CAVIUM 0x43 +#define ARM_CPU_IMP_BRCM 0x42 #define ARM_CPU_PART_AEM_V8 0xD0F #define ARM_CPU_PART_FOUNDATION 0xD00 @@ -87,6 +88,8 @@ #define CAVIUM_CPU_PART_THUNDERX 0x0A1 +#define BRCM_CPU_PART_VULCAN 0x516 + #define MIDR_CORTEX_A55 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) #define MIDR_CORTEX_A72 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) #define MIDR_CORTEX_A73 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) From patchwork Thu Aug 29 11:34:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172610 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092495ily; Thu, 29 Aug 2019 04:36:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqwPi2pSdniTIWjZ8JWJTX0lKxyxggdDjhmconK1vQkxc2FU/DVNiW8/bYXw69LrFhTilqYn X-Received: by 2002:a17:902:302:: with SMTP id 2mr9374629pld.149.1567078582233; Thu, 29 Aug 2019 04:36:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078582; cv=none; d=google.com; s=arc-20160816; b=mhBRQ8KGBhn+XAnR4ymiwSYsM/PKCyC1b3a0hVtTtcax+3Rl2LQuW2NPnxrki59MAO DIaDQChBNhRubd610FkMfKO5JMUluvL1/hB+6aOY77wG0zWlt8p485KRQnc2FfJet2L1 +STHcJ0JUNRxmGLMdmncITmbY6+bKTncMZYGD9OpLdA7oxgKAmQRHGIQLHc/WDt1ufv6 S+xMSWo4kKy+dePDVr0rBAHjCNWWRtvg0cBMxsEzOozCvyfcL7Abr4/AWIXpyPlW7WZB ZpbR09HdO5rsFG8CDQrW6A4TPo8CpNhDa5cHeDXo2GtprHKePpwjQjxkvFowuM6EHPE2 lIgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=sBbWRB3LgLlv2c3U4FxHDhn97v+yXFInuDLMYZ1aFeE=; b=RJHI33U98K1jjXsq8HIqZB2XHBrHFGlfjnlU1ugQGAFMkVDQyWTZgfzDv0dN/noTuq Hhjwxlq5a7NbW0h0mOgkShy/N46455dSuNbmnzdYsQSBrvHw+qVPRded8ZNBFYhrXoyG TBYaVZ3VJJqv5ABnR7twFNfxDIVrt/9PQ8UnRs1rsI505YfNPNA+jma+U7Yhl+bKUiFG ukHmKC+UulomFd4oSnE8GcW41vjmuDPOyjdKzFHFnUkyim6RgxYkVaoZsZkSC1pWpIX0 9Nats4Bbc5hhLjR1tHC1sGzhih8I94HgtwSbH4r0zrmEvS2KbRatWQO5f7iQE3+3yOgb WvRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Xmq4KtCB; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Add the older Broadcom ID as well as the new Cavium ID for ThunderX2 CPUs. Signed-off-by: Jayachandran C Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/cputype.h | 3 +++ 1 file changed, 3 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index c6976dd6c32a..9cc7d485c812 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -87,6 +87,7 @@ #define APM_CPU_PART_POTENZA 0x000 #define CAVIUM_CPU_PART_THUNDERX 0x0A1 +#define CAVIUM_CPU_PART_THUNDERX2 0x0AF #define BRCM_CPU_PART_VULCAN 0x516 @@ -94,6 +95,8 @@ #define MIDR_CORTEX_A72 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) #define MIDR_CORTEX_A73 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) #define MIDR_CORTEX_A75 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) +#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_PART(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2) +#define MIDR_BRCM_VULCAN MIDR_CPU_PART(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN) #ifndef __ASSEMBLY__ From patchwork Thu Aug 29 11:34:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172611 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092541ily; Thu, 29 Aug 2019 04:36:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqyvPN/HoOkkuGSRrvPQICtGkgrlTap3EUi39ugaK5ejJAtMgDce7L3nq6BCe8QrIEDA13vD X-Received: by 2002:a63:1:: with SMTP id 1mr7792996pga.162.1567078584769; Thu, 29 Aug 2019 04:36:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078584; cv=none; d=google.com; s=arc-20160816; b=iYQSXbUEJRQ9NFoARls6C+JkP2Q9Ht7STQJ6iVfIqmjMBSBPg9X0zW965tgxEHZjIx jyzQax4702MPEI7r/+xaKf3ALDw/1z9Rg6BULY5Wzrgtm5kEa2bae4gW3g7SsSmnohNS k87FQclXuMhciyWNkG30/1Bn6QR3Q4hiHTxXAx/uwG5/R9JlitoSzyhfBel2p9UI98fN XA2Q/y2sRi+YFk91fpeVGTIg56WUF7BLob/wI7yHQSSu47H5Wie4V1yCC0dWgZT//4Sr x86vlCTKQm8fOx1lar1XNuQzrjBWEfOZ5tXJBz2jLk3kM7XPM+thZ/APm36SFqoYupSH aPfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dkWh8S1DsW6tSZCYoLWe69ClR5UVvKugQ1/Th9fCzhU=; b=sSdmY+t4aKt3t31k3Eblh/QukpqWbvcJbtSVB81qxOWtBGrkS3vbkGuAchfVjn1zaU P8QBQEo8g0FIbNpJ1mj76TQ8NK5H80aHwU3gPH3C+caf8tNsplNYpFuB7Xb+Kcq6WA01 JoeN0ea6CazSwsUpnZVreLiFs8zB7+dzVXDRF3E+/bAG/BKHX6Q6OXHRfo+AjKpYBCCO TXrh5wzrxECiI21SZYC0+guGI1xTxP9kDpjcNX5SeRD7oZDoObY8DCBLxYhFsjzbYhPz cmsBIo59vGOK2ONs8WziuTACCAU07RfzxTo8hGksZnLq3u0glTX/aTWarjSMbPYwsHB9 +gLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gwTGiqyd; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c67si2276378pfb.211.2019.08.29.04.36.24; Thu, 29 Aug 2019 04:36:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gwTGiqyd; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727189AbfH2LgY (ORCPT + 14 others); Thu, 29 Aug 2019 07:36:24 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:42513 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725990AbfH2LgY (ORCPT ); Thu, 29 Aug 2019 07:36:24 -0400 Received: by mail-pg1-f194.google.com with SMTP id p3so1436683pgb.9 for ; Thu, 29 Aug 2019 04:36:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dkWh8S1DsW6tSZCYoLWe69ClR5UVvKugQ1/Th9fCzhU=; b=gwTGiqyd1i0ey/EjaZDRrHjSr8gfQOYUawu8ybrHlGoJXfZFdHdv76ymB94bXuy5C7 OA8AjmChqVIkkYPWK6ygHXDBNYOYGkoAhRrShHbZeaRHGG53Y1D/k+gLdO/GKe5Q5xfE fL+Tsj+BL7rll0SI0ZZBa1dm7YrfAjXR5n4N0rRmfms8qWKXuJ4l+GDnDgwzMOkGo21/ y+PSskm+p0nA+iofaGta5EIfhGWlzRFkkJkGjknmZA97KV2JxrIxV3u+p2+9xBCbOxn5 XrrjPAED5EXO56K+jXLwqfrgwwt1csJ5/dIOzzOK3kwWQj9/g9Yg6pmR1pnkdhGs1lSG In5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dkWh8S1DsW6tSZCYoLWe69ClR5UVvKugQ1/Th9fCzhU=; b=IMTYmkLaOaiun3a1MaXfZtAB/Q5aRBVPC+MduXgPVEjdnWWBse8imYx1NLvaD+mslV I4iFc1xFsVKU5DLPtABgtsRXgkafBzowPVxinsQ+ug8rffTNI/KuHwNTPpSVsknEY2Ny s+PEuSFFTLCWouj6PCGxKqjGbtB80Z5HGRtk/MjQEQux55zYATex9tdPw9ml0rritUUo wzmJSZcIVQHTA9GK0PvF4W+mqzXSlyehZ+IyYYmnrFXFxE9nfbhBA0lSNrGfIoW4SIEU JM0VH82nGBAMsq2lwzo0ZYag0m3mXPAngKH/cPdVjPsY276QRGuqqmgMYIO9g6kKYuPS RFbA== X-Gm-Message-State: APjAAAXv7kj+7K9dnIstBJhMNFjdzW/ujGnbpooyS7u1TUqpVt0D2rKR VsOLPC8L0Iu+di7eyOFPAiQ6BRv1ec4= X-Received: by 2002:a17:90a:b303:: with SMTP id d3mr9677868pjr.28.1567078583076; Thu, 29 Aug 2019 04:36:23 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id y8sm3422359pfe.146.2019.08.29.04.36.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:36:22 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 34/44] arm64: Branch predictor hardening for Cavium ThunderX2 Date: Thu, 29 Aug 2019 17:04:19 +0530 Message-Id: <428a36a4c7d91a280917ec2a65b16ab0cb11bb6b.1567077734.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Jayachandran C commit f3d795d9b360523beca6d13ba64c2c532f601149 upstream. Use PSCI based mitigation for speculative execution attacks targeting the branch predictor. We use the same mechanism as the one used for Cortex-A CPUs, we expect the PSCI version call to have a side effect of clearing the BTBs. Acked-by: Will Deacon Signed-off-by: Jayachandran C Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/cpu_errata.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index dbd7b944a37e..ff22915a2865 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -234,6 +234,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), .enable = enable_psci_bp_hardening, }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), + .enable = enable_psci_bp_hardening, + }, #endif { } From patchwork Thu Aug 29 11:34:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172612 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092594ily; Thu, 29 Aug 2019 04:36:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqxDuBNdMYR/v3y7XMwXwO5CGVUoCP/hHnVZXWppGoB0t9uWuhAYwoQCWaC/evRkmfGKJ606 X-Received: by 2002:a63:593:: with SMTP id 141mr7776826pgf.78.1567078587413; Thu, 29 Aug 2019 04:36:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078587; cv=none; d=google.com; s=arc-20160816; b=f37OK0BK1Sb1lMsUAHn5woJXAOMn2vaTHLue6TsqxEEC+0lxLTAAr8YD0OBxcQ2n89 MWODfoLZE46iJaR2DB7z1Vgl0ixQJCbIXYCgKqxYdze2s+D8umo8nkk0E109dwD1Lm9D tE5EuwF0d+dDjaqeS1jaJrlnDdT/dkr4AUJFKBX1TmsUYRS4AR+G7Y3RVBzH6PqxlyBW XU4WyeFpWERb96tRqL2t1UfxyqqDDmgyhZR90rO+gmkZUf1X0uKGvptfrtyP8oCBRnBF +7WDSjlX4FflFf1om+o1KXMwx0y4N5ghf+b4zPwXkLUFWgYCzq3ZY0agpmw1gWdY9+Gr 7GoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yC2M+WqtpDn8WEqkn0+0Dw3Z53HTrfg3c6ZZe0WXdnU=; b=NPXfGXen8NpkiKy7REx7/RGvPWldg22Yym9grPUHe/5RI4d+Fu43ZFiqaOgdTeH5Uj 7yycPHD0mHGV+xpbCRnMCBe5nS5n93Nv3zCpOORlBwdB4m0DyMHH5WVMxkedAtSoxnji 6pMjwm/FAOM3F+ZE0r97boB3y3tvfsEDOW6KxrapfNH2IAZjd9NPI+vbIz97jS4BWLRq vva12pFwmJQn3nQHtm4wIS4tJiNwmHe7OPLxgm/ncjpegTPMqfIqXS9XemkkS50HGW/7 DbSAyaxrk0IJisxc9eTKDhlPIRhu/m/0WBpNp6S5zLmW+SZ0nqJW142sAQCeHMC1eTJF DqEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="GxHvDA/6"; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c67si2276378pfb.211.2019.08.29.04.36.27; Thu, 29 Aug 2019 04:36:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="GxHvDA/6"; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727578AbfH2Lg0 (ORCPT + 14 others); Thu, 29 Aug 2019 07:36:26 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:37625 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727559AbfH2Lg0 (ORCPT ); Thu, 29 Aug 2019 07:36:26 -0400 Received: by mail-pl1-f193.google.com with SMTP id bj8so1453326plb.4 for ; Thu, 29 Aug 2019 04:36:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yC2M+WqtpDn8WEqkn0+0Dw3Z53HTrfg3c6ZZe0WXdnU=; b=GxHvDA/6fmrmac7D30qhXaKJnx1ZeBV+vKF0Tl5JzbIvDOFX05R94gDcyfHQmLOLs1 plEfoetXfkZlVD6jwNSSr7oRBDMLpXF1WXjHaM6r3KZ6yR/NLXnK/9xdwHwCJR6SrOI9 Uh9KgJGdolnR8ogY8td4UHSXUXFbzv1+d2SksDGk/S1Uor4QDfVW4f15kIW/7Wnk90pV uLJVdO2pxy5/65zcH+bHojgJlKtkGrGb5anNzESVrsYjfXpk2M2brqhZOJXeGljU7Asi QiAmassVz/TKw/MKJQpLE7lUihCvmP7XSrpvpfsVaJlL1bQ+U+GUOVqgJ1LhBGmXRvvq Nh5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yC2M+WqtpDn8WEqkn0+0Dw3Z53HTrfg3c6ZZe0WXdnU=; b=WO57AleN+qfWAXSXf9uQVh22JTwr0IdaQ+c3vydK/KMmxL4lfGrYL7C2NbvXwdUaTx T9YsEMYM1RIn17k8BI+bcDv6vuqX3FO99wU9bXl9uExi4oN90feOgt05oJqmU7VQCQGk F3peUqu4bO9XDxUlERl7cyH8P0P8BWOd7YqsTOqL8g1lFFYdnuDoLsQ4uTo3GlhLgvr+ rexdvE9RuzpXuFfTwkV1D6Nt8CcFAdwTKG4MAFoUszbe1NCEKvBeDwMJfjWBx0TAu+fi kWio+9CKm360m2omFrs1qdMHdbWVWsw+p1IqkpKdKI9kMEchapRwbqFieI9Jot4gMdJC sYbg== X-Gm-Message-State: APjAAAXZv1KiHVnv84pOKFFNfODWBklc9C9YaH7p6nndIJDtKxmkfeTD UUL6DiAcrwM0sGnGjfOstjkkemhhmOY= X-Received: by 2002:a17:902:f30e:: with SMTP id gb14mr9461817plb.32.1567078585655; Thu, 29 Aug 2019 04:36:25 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id w2sm2198815pjr.27.2019.08.29.04.36.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:36:25 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 35/44] ARM: 8478/2: arm/arm64: add arm-smccc Date: Thu, 29 Aug 2019 17:04:20 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Jens Wiklander commit 98dd64f34f47ce19b388d9015f767f48393a81eb upstream. Adds helpers to do SMC and HVC based on ARM SMC Calling Convention. CONFIG_HAVE_ARM_SMCCC is enabled for architectures that may support the SMC or HVC instruction. It's the responsibility of the caller to know if the SMC instruction is supported by the platform. This patch doesn't provide an implementation of the declared functions. Later patches will bring in implementations and set CONFIG_HAVE_ARM_SMCCC for ARM and ARM64 respectively. Reviewed-by: Lorenzo Pieralisi Signed-off-by: Jens Wiklander Signed-off-by: Russell King [ v4.4: Added #ifndef __ASSEMBLY__ section to fix compilation issues ] Signed-off-by: Viresh Kumar --- drivers/firmware/Kconfig | 3 ++ include/linux/arm-smccc.h | 107 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+) create mode 100644 include/linux/arm-smccc.h -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index cf478fe6b335..49a3a1185bb6 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -173,6 +173,9 @@ config QCOM_SCM_64 def_bool y depends on QCOM_SCM && ARM64 +config HAVE_ARM_SMCCC + bool + source "drivers/firmware/broadcom/Kconfig" source "drivers/firmware/google/Kconfig" source "drivers/firmware/efi/Kconfig" diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h new file mode 100644 index 000000000000..611d10580340 --- /dev/null +++ b/include/linux/arm-smccc.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2015, Linaro Limited + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef __LINUX_ARM_SMCCC_H +#define __LINUX_ARM_SMCCC_H + +#include +#include + +/* + * This file provides common defines for ARM SMC Calling Convention as + * specified in + * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html + */ + +#define ARM_SMCCC_STD_CALL 0 +#define ARM_SMCCC_FAST_CALL 1 +#define ARM_SMCCC_TYPE_SHIFT 31 + +#define ARM_SMCCC_SMC_32 0 +#define ARM_SMCCC_SMC_64 1 +#define ARM_SMCCC_CALL_CONV_SHIFT 30 + +#define ARM_SMCCC_OWNER_MASK 0x3F +#define ARM_SMCCC_OWNER_SHIFT 24 + +#define ARM_SMCCC_FUNC_MASK 0xFFFF + +#define ARM_SMCCC_IS_FAST_CALL(smc_val) \ + ((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT)) +#define ARM_SMCCC_IS_64(smc_val) \ + ((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT)) +#define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val) & ARM_SMCCC_FUNC_MASK) +#define ARM_SMCCC_OWNER_NUM(smc_val) \ + (((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK) + +#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \ + (((type) << ARM_SMCCC_TYPE_SHIFT) | \ + ((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \ + (((owner) & ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \ + ((func_num) & ARM_SMCCC_FUNC_MASK)) + +#define ARM_SMCCC_OWNER_ARCH 0 +#define ARM_SMCCC_OWNER_CPU 1 +#define ARM_SMCCC_OWNER_SIP 2 +#define ARM_SMCCC_OWNER_OEM 3 +#define ARM_SMCCC_OWNER_STANDARD 4 +#define ARM_SMCCC_OWNER_TRUSTED_APP 48 +#define ARM_SMCCC_OWNER_TRUSTED_APP_END 49 +#define ARM_SMCCC_OWNER_TRUSTED_OS 50 +#define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 + +#ifndef __ASSEMBLY__ + +/** + * struct arm_smccc_res - Result from SMC/HVC call + * @a0-a3 result values from registers 0 to 3 + */ +struct arm_smccc_res { + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; +}; + +/** + * arm_smccc_smc() - make SMC calls + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This function is used to make SMC calls following SMC Calling Convention. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the SMC instruction. The return values are updated with the content + * from register 0 to 3 on return from the SMC instruction. + */ +asmlinkage void arm_smccc_smc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, unsigned long a4, + unsigned long a5, unsigned long a6, unsigned long a7, + struct arm_smccc_res *res); + +/** + * arm_smccc_hvc() - make HVC calls + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This function is used to make HVC calls following SMC Calling + * Convention. The content of the supplied param are copied to registers 0 + * to 7 prior to the HVC instruction. The return values are updated with + * the content from register 0 to 3 on return from the HVC instruction. + */ +asmlinkage void arm_smccc_hvc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, unsigned long a4, + unsigned long a5, unsigned long a6, unsigned long a7, + struct arm_smccc_res *res); + +#endif /*__ASSEMBLY__*/ +#endif /*__LINUX_ARM_SMCCC_H*/ From patchwork Thu Aug 29 11:34:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172613 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092637ily; Thu, 29 Aug 2019 04:36:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqxM7eq4oPfje4QUQIaPInmtSNENznOfQOC9wUNSGkwcGUX6dFP96HifrSgYLXvlDKcfYr/Y X-Received: by 2002:a63:d741:: with SMTP id w1mr7679784pgi.155.1567078590276; Thu, 29 Aug 2019 04:36:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078590; cv=none; d=google.com; s=arc-20160816; b=XoYX5lTnrUd1mfG4srPCnZE6pYZkHOw8dvIVvCH74FOmi2HRDShZd9/kKPwG8b+g/s NYfIFtgT067XRgu+iJLVhZKP/BCT72edCGm5G4YQGduA089rIKY+ywOF8KqhCadE2z5z tqISTW42ctzLc5kHbB9BOZE+kMVSEK9ptfFEXvC3k8xDi8Hyo+rgXQ3ZLFs8iv82lyHe m3OkzvttWcEH3qB3Wu78AWRMRoxtdLzWlG0Mj0w+6Mv3885zsav3/zhLJouJLEO/R07r ch59CC+0LpesBmLOpFjG6BImR7fGcu78d+sEXxd6I91q+5uS4ua65rxvWFOTiR/NtIcj G/Qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FDb8snX7fHtHRXPBtLwcic7/q7BlhqslXapsBvvT9m4=; b=N4Pg+XP7+p+o3PIN6zm83hnNZ8M/tn8SbnyMM+rvA6dEP8QmcZgLUOfD+I5pEMsyJI Dyd8HkYJo9kSmhf70mwaOOWiccNRep7Rd1tn4BufEUpd1SBRNDeZDUWM4c4XJC4klrB7 QkkScgOMWNzmYgCoWF9kq8IKhwdX6eFQBqJBnd/UhLX9uyGrR0oOs+fnORKlh7L9nunw EwnjaakaZBvxzPCNcdHjqW7BmN3jh+p5FB6JkhIfjywPh9NuKpmWGZanaiFxEbe3XxkL 5WwjU1sjfbG9QknuBpc9IKEg4FJf90hgBgaiGPG3M3JI8UrsoPjwbpw3oIpS/1YsCs1I MTDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MxVDtRC9; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c67si2276378pfb.211.2019.08.29.04.36.30; Thu, 29 Aug 2019 04:36:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MxVDtRC9; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727602AbfH2Lg3 (ORCPT + 14 others); Thu, 29 Aug 2019 07:36:29 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:46876 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727600AbfH2Lg3 (ORCPT ); Thu, 29 Aug 2019 07:36:29 -0400 Received: by mail-pg1-f195.google.com with SMTP id m3so1427671pgv.13 for ; Thu, 29 Aug 2019 04:36:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FDb8snX7fHtHRXPBtLwcic7/q7BlhqslXapsBvvT9m4=; b=MxVDtRC9Y4lv4jG9hpAos0s+xIe/ARHMDGnoPf/99+Afqj27WqVXGxDp3whA9QF9rj zy6wvMMqo4wV7qE94YEu6uNAYmR1PdZl7H1LI3+jvKB3HAGDQVz2VXLAu5QxQQce/tBe tijrc9X0p0SFXFGpn7D1/0Vt2zlF/lfu/jfnPZBOego/s4nfxvYu+221uEN/M+F0kZIQ i62nKBUOyZX4z8HEn4x2m79tYCUbVRXtoorbzSgzRr+smMy30rrjJW+3cMfV3nV4jg9R RxjZkvAcYmnbOSd/PLmZv80PXkXR0tDFpIGhFn5lfhXWdkjuEyokQp/zUJDuKEjCWkcj mPwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FDb8snX7fHtHRXPBtLwcic7/q7BlhqslXapsBvvT9m4=; b=AyVyJHjRgD/VujCzuvgbtOjyeaumZrnhb5kd2LCZlmSqOKjKu1gDJtpfXQ/8x2iZfG zjx4hRX+WRMbBd8Cot4ztgYFAu6LDUCMjN3rHst920gVuy12ClpAQS7PLxCqApehCSqg SbQJn0GHlRyoX9XW7anusCxkUpczeMHSTpcTNzcU2g5McKejaEdnz4SalFkw2yGJFYlY D+FxL/Xsuq+SmHSbHEvz5W2yDfP221YHwXMoRsVrEzveDba6FLtdXqZW1hwv2M/WmM4x /M1AUbdkJU6vT/GYCgPOufFJK1r2PgOHLZnidXEsiLbYgkUOvLHEWkoHSCmHzNFa6XVN /XiQ== X-Gm-Message-State: APjAAAVdoO+pqQtl0FFxWsDaDl2BejCt/74p5Lr9fEHyevWWvKhMgokl hI+78eU0lkpgxbnasXfo+Xny+oECfo4= X-Received: by 2002:a65:6850:: with SMTP id q16mr6555728pgt.423.1567078588390; Thu, 29 Aug 2019 04:36:28 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id e9sm3945514pfh.155.2019.08.29.04.36.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:36:27 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 36/44] arm/arm64: KVM: Advertise SMCCC v1.1 Date: Thu, 29 Aug 2019 17:04:21 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit 09e6be12effdb33bf7210c8867bbd213b66a499e upstream. The new SMC Calling Convention (v1.1) allows for a reduced overhead when calling into the firmware, and provides a new feature discovery mechanism. Make it visible to KVM guests. Tested-by: Ard Biesheuvel Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ Viresh: Picked only arm-smccc.h changes ] Signed-off-by: Viresh Kumar --- include/linux/arm-smccc.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 611d10580340..da9f3916f9a9 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -60,6 +60,19 @@ #define ARM_SMCCC_OWNER_TRUSTED_OS 50 #define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 +#define ARM_SMCCC_VERSION_1_0 0x10000 +#define ARM_SMCCC_VERSION_1_1 0x10001 + +#define ARM_SMCCC_VERSION_FUNC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 0) + +#define ARM_SMCCC_ARCH_FEATURES_FUNC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 1) + #ifndef __ASSEMBLY__ /** From patchwork Thu Aug 29 11:34:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172614 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092680ily; Thu, 29 Aug 2019 04:36:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqyMXid8iyjYamTgyvZ8I0eglJCpVzZU6DOmglkiKPKT764aBE1s7CzKvWQnf2jGUq8x7CVC X-Received: by 2002:a17:90a:e2c5:: with SMTP id fr5mr9354701pjb.122.1567078592863; Thu, 29 Aug 2019 04:36:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078592; cv=none; d=google.com; s=arc-20160816; b=n0wEAlML58y1fYuQn/7b1xDWcTnpR0KDl82UsqnVedv0bzWzOnpwhAgbMDMCX4sGEQ JuDIeKwGs0NBBxV4/CSZesCpxkViTMTX5sFCWSEr3cwwTucDbYS3EzZ0daYz+jMfO94J AzlaPfY78vnY1VTL6IZTeM8UNiLw6SlTM8eMXCdyXccvIqqt8dB7l5BOg18R3kMjh7kO enLY4k0mt2pvNl+r3JL99OtQJqazpgkLjlykHn2B98U8OgwpsM1tFaaegvtz9bMs/WN3 pw6DNGXcp0HthWxMkka1156t5lkNIo/zlst8Zw1YyhfJ0h2YYWmpKf8S6+AkE/tBcxWd VdIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=z7GSqiJ6aBNFVvBBcZiH2v3S1Pbs9vo106t8SFNGIe4=; b=wKdtzk1WSziT3mCTnTcKShyXG8VjuZeW1FS7uXDGr2GN0ZiHy33MppVUJNd/qTtXiW BDECCAiV2tycsd182iKUHIFoW2vXeM55FA384T2KuQbk6KqpETfktSj2Ed82EaiuSfPd y/2Vxzcdn8fPTJVAmyGjUSCJmzPZpqZHFUU6XksEOuYOv+wDwBhQ9OfjZ0vJCAI9znSM wn9EmnCOzuJM7sxa+00P+LNFeoBXmyKG8WcuvZYJNIDtesF3ispECRwS8RDDNiKCF5YJ 3NTJtKXfSS2p0aZytItThKJBoYYbXqIQotbjwCw9tGLIw4V80eQWlcxOS+h43UzKXnEW PGEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HgYnyGY4; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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A new feature of SMCCC 1.1 is that it offers firmware-based CPU workarounds. In particular, SMCCC_ARCH_WORKAROUND_1 provides BP hardening for CVE-2017-5715. If the host has some mitigation for this issue, report that we deal with it using SMCCC_ARCH_WORKAROUND_1, as we apply the host workaround on every guest exit. Tested-by: Ard Biesheuvel Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ Viresh: Picked on only arm-smccc.h changes ] Signed-off-by: Viresh Kumar --- include/linux/arm-smccc.h | 5 +++++ 1 file changed, 5 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index da9f3916f9a9..1f02e4045a9e 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -73,6 +73,11 @@ ARM_SMCCC_SMC_32, \ 0, 1) +#define ARM_SMCCC_ARCH_WORKAROUND_1 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 0x8000) + #ifndef __ASSEMBLY__ /** From patchwork Thu Aug 29 11:34:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172615 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092726ily; Thu, 29 Aug 2019 04:36:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqwRtWF63KWfEv0nOQSH14jEzCef6oJVMG2Te6SGiOxGNKVs1yrZAj6/3opwZ9ql7MqsLpGi X-Received: by 2002:a65:68d9:: with SMTP id k25mr7928353pgt.337.1567078595297; Thu, 29 Aug 2019 04:36:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078595; cv=none; d=google.com; s=arc-20160816; b=B/C5OsS29kpuq2sU7zpwcC5WLkW66KBAYX7Pwm2elDklNpPnKmIqKL6I44vATPYT/S NVslChT2sdnZJcoIVMu22MBays3/fQRBD4cnkUAkkhyWC5n3XZwBI/HgVVG3NFwob35L YlvXpPYdcx6SnExuo5TaUOiQxuKR5btrXmD33pxymUvB7sMEUgy1f16uq4i2h27Dp8Ed q7dUTx0oHrJCWTSiaepZs6VKws4n/7dc58bxtpca6lPA/SA7U/JL0/u8I2Xk0JZH6cuC ZYOyiX7ulOucoLK5XMeTyMKLInVDJY88EzW13bJ26sinpuRxrKzts/3HtHrFKYd40SZF l8Jw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=lhetsf/v1WHqsODDPiuS8lCaAlBwJqZTnWnIuf4OhuE=; b=xXGW9N56xSnSSIQfvtpOufI1GF07ML5YpigJA5oEcVAmAQW7luk4IXqW57SpWjWj1i +63SPbAKe31XyTMxU2zWqz4WV/mSmkF3jr71xtkOlLhtrnf8ZqbJOuDZ8pgrEcSp996T Rc3nrIInx4fb7uz4WWLLm3NbjxA5Y65EkmTWUNKK+sb0iz5N774jJZrxnwzMZnzpEt0U XYi9frlk7cO57eovr5FHwTmQuE9eZ0zk1M7B5epXfMXl7qvNZmoEAdVNsHOnuVZoPq82 repE0BUWLfWIVN9GC33h3vJsaBUG2ETEXkrA2LgNsWxcouV4R3y9gZ/bpYbHZQkbFPq4 86KQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cNwMOzQn; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c67si2276378pfb.211.2019.08.29.04.36.35; Thu, 29 Aug 2019 04:36:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cNwMOzQn; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727559AbfH2Lge (ORCPT + 14 others); Thu, 29 Aug 2019 07:36:34 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:33299 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727066AbfH2Lge (ORCPT ); Thu, 29 Aug 2019 07:36:34 -0400 Received: by mail-pl1-f196.google.com with SMTP id go14so1458414plb.0 for ; Thu, 29 Aug 2019 04:36:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lhetsf/v1WHqsODDPiuS8lCaAlBwJqZTnWnIuf4OhuE=; b=cNwMOzQnTLEHODvHIhQEnk+Or/WiI+H6A+OFIgCMQxmFa7qTizeB59vjBlk2ZlWxoS yoNczpSvCyLVXQRZy+fLaAbQw0CFyX3aIxQekDbCNGzplBly07uvwFrMXE3dfv1V49xv 6Mde+wGHyN2HFXTsAEoYaP0yJ/eU+95AGWAt54rttyYtEzIrQM4L5QPY0jiyU9mdvzZf hy/YSEaACuc2AYos9Pj/veNFe69xiuRljYhJcpic/XY8UF/2hu0p1OPAKvDByDJWfMho c8EzaXuTX+F9YQ7MZhYOJNt5DRR1TDqjDdCp4Qm3EicA5Ck/031pqGP4/+DUCBChh9B6 yCyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lhetsf/v1WHqsODDPiuS8lCaAlBwJqZTnWnIuf4OhuE=; b=rQ6LeaQ1lB7gCfZGFpJRxcxaMoqoydLTz/r5vc1VxWUTv+jh4Ww3LcKtWECBiyewd0 qCqERE0gcmercUtkpMusVBd1EjSyWU8EaSlnKJ78MAjC/nNdvDl/jEXaJzSwaO3Tju/O K8m4y5zDxkplZuPivyB1QCiTXvOUemSoaUXUAe4uk+Co284FkY6f0iEr79NbiiI1n92S keInXH9zeW6ihbD1QKmPaXBu+wOP/2eME18dKuuH8Q7/oSH86soq3/fpBqirSugIMsn/ i+5N1tRfVqIybrYBdQ2YKqd9pwDP8jHxyDiMXOQCNwM7xiT/DHfMkOIFB7pIkCn4Ri7t jfWw== X-Gm-Message-State: APjAAAU9ohGV+FidNiN0wGGTdZtSUW76L4mPUxG/zFECrSBk409MrMZC TuEWOMmL4V5/CKtMVibJ3tWhmsoIikY= X-Received: by 2002:a17:902:bd4a:: with SMTP id b10mr9277181plx.219.1567078593597; Thu, 29 Aug 2019 04:36:33 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id b6sm2266314pgq.26.2019.08.29.04.36.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:36:33 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 38/44] firmware/psci: Expose PSCI conduit Date: Thu, 29 Aug 2019 17:04:23 +0530 Message-Id: <9325adff57fcdbf3524e2dbb35d8616a0343051e.1567077734.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit 09a8d6d48499f93e2abde691f5800081cd858726 upstream. In order to call into the firmware to apply workarounds, it is useful to find out whether we're using HVC or SMC. Let's expose this through the psci_ops. Acked-by: Lorenzo Pieralisi Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- drivers/firmware/psci.c | 28 +++++++++++++++++++++++----- include/linux/psci.h | 7 +++++++ 2 files changed, 30 insertions(+), 5 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index 290f8982e7b3..7b2665f6b38d 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -54,7 +54,9 @@ bool psci_tos_resident_on(int cpu) return cpu == resident_cpu; } -struct psci_operations psci_ops; +struct psci_operations psci_ops = { + .conduit = PSCI_CONDUIT_NONE, +}; typedef unsigned long (psci_fn)(unsigned long, unsigned long, unsigned long, unsigned long); @@ -187,6 +189,22 @@ static unsigned long psci_migrate_info_up_cpu(void) 0, 0, 0); } +static void set_conduit(enum psci_conduit conduit) +{ + switch (conduit) { + case PSCI_CONDUIT_HVC: + invoke_psci_fn = __invoke_psci_fn_hvc; + break; + case PSCI_CONDUIT_SMC: + invoke_psci_fn = __invoke_psci_fn_smc; + break; + default: + WARN(1, "Unexpected PSCI conduit %d\n", conduit); + } + + psci_ops.conduit = conduit; +} + static int get_set_conduit_method(struct device_node *np) { const char *method; @@ -199,9 +217,9 @@ static int get_set_conduit_method(struct device_node *np) } if (!strcmp("hvc", method)) { - invoke_psci_fn = __invoke_psci_fn_hvc; + set_conduit(PSCI_CONDUIT_HVC); } else if (!strcmp("smc", method)) { - invoke_psci_fn = __invoke_psci_fn_smc; + set_conduit(PSCI_CONDUIT_SMC); } else { pr_warn("invalid \"method\" property: %s\n", method); return -EINVAL; @@ -463,9 +481,9 @@ int __init psci_acpi_init(void) pr_info("probing for conduit method from ACPI.\n"); if (acpi_psci_use_hvc()) - invoke_psci_fn = __invoke_psci_fn_hvc; + set_conduit(PSCI_CONDUIT_HVC); else - invoke_psci_fn = __invoke_psci_fn_smc; + set_conduit(PSCI_CONDUIT_SMC); return psci_probe(); } diff --git a/include/linux/psci.h b/include/linux/psci.h index 04b4d92c7791..e071a1b8ddb5 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -24,6 +24,12 @@ bool psci_tos_resident_on(int cpu); bool psci_power_state_loses_context(u32 state); bool psci_power_state_is_valid(u32 state); +enum psci_conduit { + PSCI_CONDUIT_NONE, + PSCI_CONDUIT_SMC, + PSCI_CONDUIT_HVC, +}; + struct psci_operations { u32 (*get_version)(void); int (*cpu_suspend)(u32 state, unsigned long entry_point); @@ -33,6 +39,7 @@ struct psci_operations { int (*affinity_info)(unsigned long target_affinity, unsigned long lowest_affinity_level); int (*migrate_info_type)(void); + enum psci_conduit conduit; }; extern struct psci_operations psci_ops; From patchwork Thu Aug 29 11:34:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172616 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092769ily; Thu, 29 Aug 2019 04:36:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqyInW+JpQL9JF7H6SnnaeT9usjp+z3N5+Kb/UZUJ9jFhNV/22UNiXb1ai4AUIMie2SdxPf7 X-Received: by 2002:a17:902:1a4:: with SMTP id b33mr9187303plb.141.1567078597968; Thu, 29 Aug 2019 04:36:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078597; cv=none; d=google.com; s=arc-20160816; b=sGFpOtIkLDhBVnvQM+hmevUCjpB5JYjRd0GwTUpUvda7o+iMrAgP90ONVoEyLrmQre QZQkKuqSbeGAJn/71APWtqTAZ7cyD0R9WKj9DXWOEP6Wy35ggnUMuzskkNSE292R4B4E TVee4GDjV/WWFR6nk/tGsNVE2n5OK2cuwVh89Ub4EK4KCFweB32Lk2uB42W857V0B4uH quPdR/EdIybUvyPD0WWhAeoE9E2t6jaofN3jArFxTADkBOdpo+8TZCAFY2X4j124VYgO KvCLMJAlLHreLr8QM3v8d9t5ZCBSr4/qtJ0ek8Eofsdcrtiyq+5dckquRdUBORwqJnqJ WJDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8FgYZ0lVoh76yEFRGdkiTuXxRHgDjc15a9Db0UAG0RM=; b=Z8T6x2mXZyDmUMaa4M+cJeLJfv0HuVEKS37c9NIJsLEZhO47FwvO4bX+pHuXDsrOSD MkdK7JecATISgiS0Bmv5Hs5KFG67xUBb09Dg/jF1QLwovpZ5zTRT+hyN6h1C22J7Ug1z 5Sesffbu9G0nraejvi2MIs2vmCuKEBAQukSa5OebSuCR8WvF4Gnx9aZDCoaTIUNur7/P iHcABdv6533DQm+zL9g1a7njeuUn4hOw00wD2zIZVwMY97l77+Wv6xS6xZ4je/F+mjHX SZ+f3H+QzurgKvuc6s2zLc2SSp1aOoefBLBzBPFe6MZWuC4FD62vZ3U2IR4ZphmQk+wY uo1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UeOn1W6g; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c67si2276378pfb.211.2019.08.29.04.36.37; Thu, 29 Aug 2019 04:36:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UeOn1W6g; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727600AbfH2Lgh (ORCPT + 14 others); Thu, 29 Aug 2019 07:36:37 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:36392 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727066AbfH2Lgh (ORCPT ); Thu, 29 Aug 2019 07:36:37 -0400 Received: by mail-pf1-f193.google.com with SMTP id w2so1874231pfi.3 for ; Thu, 29 Aug 2019 04:36:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8FgYZ0lVoh76yEFRGdkiTuXxRHgDjc15a9Db0UAG0RM=; b=UeOn1W6gwCyzjiugPXX9SymT/iYCvcguyV59792moJTQ0odoPIXAPUDBRV5S7/ZGnz 5LmJ2aoVZ/BH5zX3UM7Ot5Lvj1GLHlfSQJ6y85yEiGvj8gY4+jMYcqFv3DdEcGOHmy14 XlJiiVT+m8VhZHrXTyIxObNjygZVYGrCro+uaz9h1Nw4FZwmGpU8iQO2yRB4vS67itrA odn9Yw5LwC5AG45CtUY5g1U0UpM09fMOAWj5qZnweKbY1hvLI/B9FIRY/TO4GRichLyn ttyQVfv0rgHThUXWTw2ZKzW4Eesi+LQpVES7ypKaKBsu99fp3xAjjtmXwy27fSV2A7co wkVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8FgYZ0lVoh76yEFRGdkiTuXxRHgDjc15a9Db0UAG0RM=; b=sZpowqV5ZT9aiPkt96GZyzqSBtry2e1SLSpZ2R7dgAsqsZ6JFAsJotax6NzLy3E5FO 9tkZfHuaonwNsS0EeC+yiEbdxXmG3hUkZl+6CFa8I86sPC7bQ2tBNNtQGh0jNRl/gXBv xabU6RBua+uFdaB1Ln3Om2NIgnKACpXefRpKYrJELs3jaj60lIyE/1IJP9mFePx34ig3 nXBb7xAU0+HunrF0CbMIyC4uNsu4UncWx708kxndmz+/ndt4EfTYoAi/JmVpY8/IYuNP raD8QzH+YuBwCZ1ffnRVX0uoa4VGbZZAxyD9KLkUGxfZ5E2PQL5avzebwa26J3VL9Pnk sufA== X-Gm-Message-State: APjAAAV6H6QOJ9V8uy34Ex5WCJTT8WaD8/4kloQDFeGjYyYWifkaTFAv JA2Qc0PjDpgX6qboToPj91rzjE/6pxk= X-Received: by 2002:a65:5144:: with SMTP id g4mr7940524pgq.202.1567078596132; Thu, 29 Aug 2019 04:36:36 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id m145sm2667406pfd.68.2019.08.29.04.36.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:36:35 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 39/44] firmware/psci: Expose SMCCC version through psci_ops Date: Thu, 29 Aug 2019 17:04:24 +0530 Message-Id: <0e4f990741cd3607fbdf1fc46dc7f47c598b199a.1567077734.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit e78eef554a912ef6c1e0bbf97619dafbeae3339f upstream. Since PSCI 1.0 allows the SMCCC version to be (indirectly) probed, let's do that at boot time, and expose the version of the calling convention as part of the psci_ops structure. Acked-by: Lorenzo Pieralisi Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ v4.4: Included arm-smccc.h ] Signed-off-by: Viresh Kumar --- drivers/firmware/psci.c | 28 ++++++++++++++++++++++++++++ include/linux/psci.h | 6 ++++++ 2 files changed, 34 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index 7b2665f6b38d..0809a48e8089 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -13,6 +13,7 @@ #define pr_fmt(fmt) "psci: " fmt +#include #include #include #include @@ -56,6 +57,7 @@ bool psci_tos_resident_on(int cpu) struct psci_operations psci_ops = { .conduit = PSCI_CONDUIT_NONE, + .smccc_version = SMCCC_VERSION_1_0, }; typedef unsigned long (psci_fn)(unsigned long, unsigned long, @@ -320,6 +322,31 @@ static void __init psci_init_migrate(void) pr_info("Trusted OS resident on physical CPU 0x%lx\n", cpuid); } +static void __init psci_init_smccc(void) +{ + u32 ver = ARM_SMCCC_VERSION_1_0; + int feature; + + feature = psci_features(ARM_SMCCC_VERSION_FUNC_ID); + + if (feature != PSCI_RET_NOT_SUPPORTED) { + u32 ret; + ret = invoke_psci_fn(ARM_SMCCC_VERSION_FUNC_ID, 0, 0, 0); + if (ret == ARM_SMCCC_VERSION_1_1) { + psci_ops.smccc_version = SMCCC_VERSION_1_1; + ver = ret; + } + } + + /* + * Conveniently, the SMCCC and PSCI versions are encoded the + * same way. No, this isn't accidental. + */ + pr_info("SMC Calling Convention v%d.%d\n", + PSCI_VERSION_MAJOR(ver), PSCI_VERSION_MINOR(ver)); + +} + static void __init psci_0_2_set_functions(void) { pr_info("Using standard PSCI v0.2 function IDs\n"); @@ -368,6 +395,7 @@ static int __init psci_probe(void) psci_init_migrate(); if (PSCI_VERSION_MAJOR(ver) >= 1) { + psci_init_smccc(); psci_init_cpu_suspend(); psci_init_system_suspend(); } diff --git a/include/linux/psci.h b/include/linux/psci.h index e071a1b8ddb5..e5c3277bfd78 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -30,6 +30,11 @@ enum psci_conduit { PSCI_CONDUIT_HVC, }; +enum smccc_version { + SMCCC_VERSION_1_0, + SMCCC_VERSION_1_1, +}; + struct psci_operations { u32 (*get_version)(void); int (*cpu_suspend)(u32 state, unsigned long entry_point); @@ -40,6 +45,7 @@ struct psci_operations { unsigned long lowest_affinity_level); int (*migrate_info_type)(void); enum psci_conduit conduit; + enum smccc_version smccc_version; }; extern struct psci_operations psci_ops; From patchwork Thu Aug 29 11:34:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172617 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092813ily; Thu, 29 Aug 2019 04:36:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqxIORWU85jJ1PCIhfRqQFfGymlFz6driXJTYl80NboXTHtGBezMvssDnnkwna7PMXEBw3Qz X-Received: by 2002:aa7:8a83:: with SMTP id a3mr10738295pfc.115.1567078600466; Thu, 29 Aug 2019 04:36:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078600; cv=none; d=google.com; s=arc-20160816; b=DYiQ2OEnDW3Zsd6QjddISTKP2z9wYb5TyXZSudxhHRlkKxyqLtjEM/w4QHk1szJpbu dAEzhUyd2YlWuob10QVplWMYZ9R2sosYbQCj3+DK1EWjEkCI+viH53RevC8LelPDiTEV 9V2Mhm7K7SqToM4JvyR4o+hNZ0HR5PyEyuAmIWuLqQdJSCe+hjNFAo5KmO2Pbcewor6E K0YBs9Sc23rA1jyz+ozUZPOVKgSJprIY4SmQY6eZs5dDRCoD/WZzQeMXl+p8L/7ZGEuD ibRwo/fNqV6tHyyMllynJvhMnO8ZPX4fBdhj0f7oEUGaI+VZ4SZ9wUVx8G/kxFIbXa8Z 8x8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QAkAWOSid7lK0+CYFipQ6VxUVVXehQyD0WFI7UyGT+o=; b=L2JJydadTpq308QGQ4x+IMn82L6K+HG1MugJ6YyiuWAlqQww96YDXeYWL3FAKTbviQ 9IdOoKlaNsfNNjUPQZ4tDcEL7pTke21AJ3nZ+AL3+Xn5Y+nlLy0ka+ZX2KDO48vufsjh RGxNiWZHOuJUcekA0Yk3tGg18aAhhBKvOiOkK14TC3ZjfRt/5q8GAFVQUOu0c4EHFJWu jNXLjg6WR+yhXd4lLwQu6pZvVxPAm7oLLmj3Q5bd6ml1HwX83BSDyV74YmD7DFUk3QI7 WmtslYhfVos2upu9Xka+qaNo97KuTdG5BiLAqkBEUJlwe/CFtTx0AASvbmHcy1cKZ4YS HG8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CWNDmywD; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c67si2276378pfb.211.2019.08.29.04.36.40; Thu, 29 Aug 2019 04:36:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CWNDmywD; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727620AbfH2Lgj (ORCPT + 14 others); Thu, 29 Aug 2019 07:36:39 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:43340 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727066AbfH2Lgj (ORCPT ); Thu, 29 Aug 2019 07:36:39 -0400 Received: by mail-pg1-f194.google.com with SMTP id k3so1437518pgb.10 for ; Thu, 29 Aug 2019 04:36:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QAkAWOSid7lK0+CYFipQ6VxUVVXehQyD0WFI7UyGT+o=; b=CWNDmywD9pwBoSyGrr+As4k3fmuk2k2e1Cj+YhyHwoayQ98EB8aWbyk0qtrgFFX8ab aVj+ZGKObm0d/C5Z/A/Nz6OT7wBkXe6cOp05PWhqrZRKRBN5Ow4TuLZwJFmEgbTUdKkw yrGwA36TGEbFabFc0dbcBZFc47loi7MIMCQuX0/g4yx5KBjLkkRImE7PriTYyeHftjxH pIApOewCjuzGA3UkACN5KdDuwCYA23Me5BXxuQajWqAcsrrh7Jt3xFu3gdl8A8T+9p+u iA2pL7GWbXmPwfouuSEsj9u73oy0HpXWKLf6BdUCwdTvUKpZVS5mWn8s8ANB8N6HuJGt 6WHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QAkAWOSid7lK0+CYFipQ6VxUVVXehQyD0WFI7UyGT+o=; b=ctfimmplnp4EF2ZpopLKw+0hMDEZnQorJOm3QU0q+jgn5BzeXowE+ly7Ol/LbzQzK4 3hQHwUON0hRJb2dVRsptVCNVETp1KiPhVV1uBu25XbYYT20XFDO4Iz/ATbHxGQuMWd6g 7cS3MwDRgev/TtDQ3nEA/Km3/GhZbVp6EAXoixjoD2ULwuUSzroXV84DHQ7Zfuq7Q3wV 0M2MvwY+Xjq8tjhsgIX1CWEpYwmiGyG4wpfpu14bwAM42mjHCpUUbdmLp5JKyZJ2cJQa hxvYGgN2DS0lIMWcz5Sb3rM4Qr0ANWuUflM35PZEogxDweB2quaPFFnG6d9bPul+48G8 ZQkQ== X-Gm-Message-State: APjAAAUIlsqBV8TILHV10fiU7D9PSBcptuK2o0gRyTKC8YRK5xbVL2P7 Fh+AVi4SVneu65QDEZZOmjNssjdV4iY= X-Received: by 2002:a65:4509:: with SMTP id n9mr7834393pgq.133.1567078598673; Thu, 29 Aug 2019 04:36:38 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id p90sm6514025pjp.7.2019.08.29.04.36.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:36:38 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 40/44] arm/arm64: smccc: Make function identifiers an unsigned quantity Date: Thu, 29 Aug 2019 17:04:25 +0530 Message-Id: <9bafd5233bd85eb31c7780a5d1149943da897e23.1567077734.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit ded4c39e93f3b72968fdb79baba27f3b83dad34c upstream. Function identifiers are a 32bit, unsigned quantity. But we never tell so to the compiler, resulting in the following: 4ac: b26187e0 mov x0, #0xffffffff80000001 We thus rely on the firmware narrowing it for us, which is not always a reasonable expectation. Cc: stable@vger.kernel.org Reported-by: Ard Biesheuvel Acked-by: Ard Biesheuvel Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- include/linux/arm-smccc.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 1f02e4045a9e..4c45fd75db5d 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -16,6 +16,7 @@ #include #include +#include /* * This file provides common defines for ARM SMC Calling Convention as @@ -23,8 +24,8 @@ * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html */ -#define ARM_SMCCC_STD_CALL 0 -#define ARM_SMCCC_FAST_CALL 1 +#define ARM_SMCCC_STD_CALL _AC(0,U) +#define ARM_SMCCC_FAST_CALL _AC(1,U) #define ARM_SMCCC_TYPE_SHIFT 31 #define ARM_SMCCC_SMC_32 0 From patchwork Thu Aug 29 11:34:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172618 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092868ily; Thu, 29 Aug 2019 04:36:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqy/rXIyBiBzTpBiYCgwivjaD4Vl+Tp6irZ4pCCuQMbKPurV08uBRv7v3XwHHCxJSVxTE14W X-Received: by 2002:a62:4ed1:: with SMTP id c200mr10714297pfb.218.1567078603837; Thu, 29 Aug 2019 04:36:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078603; cv=none; d=google.com; s=arc-20160816; b=mf+LxzUFq3GcFNorLxhsK+HWtvc/8BOVTo1Mh870kYmBUwivICMWzpcuFsg9CFGp3E 1TN0Pnv0T/VijKRVM96qtDxNylychB/a0pn6RBPN89apBXAQ4BSPV/scGWPv0b6cCTNz psLB/slXbfA8ebkwfwBqr3zHew50xe84RheltYFMTULetSO4AskIqz1MbkKzZn3u7HkQ X78f37FXlQkIgrL47egMphlMiCU+sABHfJWNVpnKlCUcIc5BWmXSkYNuYTh96854fTsv sQ7iZ0quznfpFN1XB430THLAErZojYjnHPZRgpDoFUf+3aCci+1MUVee17LK7I5dWBCu pxXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kulBovnYLz4YjgSJ0sOniJhX8Qcc8ljUXoag6+mJQMI=; b=UzGGjNR/o1Ly+XF0L5UAYnCE+LtzeZKeqln2tYU97GhyCgxngKINmAd/lQW3fQdhdK j16A0kzTdfS24AHBk5fb3hfMH0N3cmxomVq2AvBfgBfh4Q1ICitXrqmp06uj7kU4gzxK 3LJ11AgufEVNYsZMJhGwr4UdMCJIXbia70evZqsCkEQxowpLq21NZIx99AjVq6Z/Nbf3 fQacEKpyMwnVXWKeU0pJ1HaD1i65lcAsTvshS3XDvOFE6H3GIDwSS36Xbhsgyc3MqwXj xWWrywwNSxMCERYHZ77e1JT06U9S/O+k+E84rwl7dFPqbdHs1sb0/4sTT3hWtiuarJ3P F+Zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BlhYBuuy; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c67si2276378pfb.211.2019.08.29.04.36.43; Thu, 29 Aug 2019 04:36:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BlhYBuuy; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727650AbfH2Lgn (ORCPT + 14 others); Thu, 29 Aug 2019 07:36:43 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:37907 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727626AbfH2Lgn (ORCPT ); Thu, 29 Aug 2019 07:36:43 -0400 Received: by mail-pg1-f194.google.com with SMTP id e11so1449733pga.5 for ; Thu, 29 Aug 2019 04:36:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kulBovnYLz4YjgSJ0sOniJhX8Qcc8ljUXoag6+mJQMI=; b=BlhYBuuycLpnnh0E3Sf36GnCkmkx4gtPm9w77t2/ACX/DCMb0B9TS0q8JasqzxSuBI mbtY2tX0Omo6CY3nY3oPixI59WZku5dIoLg3A7TFRtkffdnhoPmwDQU/Fq3EJY9DQmun rz6FHo6+grLkICimR0JxlbMbdxjGLuyY0p4nPpQI/0HxdNYPv0wAVvZuovA3FydibnCE BXQYf+yho4Ho5VWqLH9sSZk4/0k0R0a4eRbffIZEm9PdC9k5NcAOO7y4uudjkYFmHl/n Nmsl5Ms3NEIKdEiOgs8Gpgb+gezvfuam8aO48NsDcc//WD9vEDJP57I3mPvQO5LGMOzO e4yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kulBovnYLz4YjgSJ0sOniJhX8Qcc8ljUXoag6+mJQMI=; b=mWo8P1OzDutbpb/lf+Wo6PYzpP2RSIwkEyArstRRNBkpjKaJNIFmT8hYSd2RC2pZsm fBHygznuzsjG1dfnMqAD9FyVRz2fjI2veZzW8lDG7Ep1TqWneezxm6Wd3ZO9rgK8WOhd YHlFjWt6++ToJzFZgp70mzFEyaHnTrJsK0I0LEAHMs7LThddxMVJWHYyvnPAqw3Z8wom aAdIvzgsGVHFnWTxu8T/NsmD4c3oWZyAolm+bHFtflHI4uFjhOkWNTbd4360K2sWUqQJ fS47PDne65xdP6ZdIEFSNN+bGjUhCBx9mYVqGf8cyd37JXQYfbvvwnmFwIAPe3l0I7i5 i2Dg== X-Gm-Message-State: APjAAAU/2SIZcdJFRwL8sv14OowcAlDsst7OAkBaYdGb/4XAU2bPxbkt kG8+Fwnu8bgDnBUVCR220CvmuyZiSwY= X-Received: by 2002:a63:6eca:: with SMTP id j193mr7748646pgc.74.1567078601318; Thu, 29 Aug 2019 04:36:41 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id p2sm5226679pfb.122.2019.08.29.04.36.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:36:40 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 41/44] arm/arm64: smccc: Implement SMCCC v1.1 inline primitive Date: Thu, 29 Aug 2019 17:04:26 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit f2d3b2e8759a5833df6f022e42df2d581e6d843c upstream. One of the major improvement of SMCCC v1.1 is that it only clobbers the first 4 registers, both on 32 and 64bit. This means that it becomes very easy to provide an inline version of the SMC call primitive, and avoid performing a function call to stash the registers that would otherwise be clobbered by SMCCC v1.0. Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- include/linux/arm-smccc.h | 141 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 4c45fd75db5d..60c2ad6316d8 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -122,5 +122,146 @@ asmlinkage void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a5, unsigned long a6, unsigned long a7, struct arm_smccc_res *res); +/* SMCCC v1.1 implementation madness follows */ +#ifdef CONFIG_ARM64 + +#define SMCCC_SMC_INST "smc #0" +#define SMCCC_HVC_INST "hvc #0" + +#elif defined(CONFIG_ARM) +#include +#include + +#define SMCCC_SMC_INST __SMC(0) +#define SMCCC_HVC_INST __HVC(0) + +#endif + +#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x + +#define __count_args(...) \ + ___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0) + +#define __constraint_write_0 \ + "+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_1 \ + "+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_2 \ + "+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3) +#define __constraint_write_3 \ + "+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3) +#define __constraint_write_4 __constraint_write_3 +#define __constraint_write_5 __constraint_write_4 +#define __constraint_write_6 __constraint_write_5 +#define __constraint_write_7 __constraint_write_6 + +#define __constraint_read_0 +#define __constraint_read_1 +#define __constraint_read_2 +#define __constraint_read_3 +#define __constraint_read_4 "r" (r4) +#define __constraint_read_5 __constraint_read_4, "r" (r5) +#define __constraint_read_6 __constraint_read_5, "r" (r6) +#define __constraint_read_7 __constraint_read_6, "r" (r7) + +#define __declare_arg_0(a0, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register unsigned long r1 asm("r1"); \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_1(a0, a1, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_2(a0, a1, a2, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register unsigned long r3 asm("r3") + +#define __declare_arg_3(a0, a1, a2, a3, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register typeof(a3) r3 asm("r3") = a3 + +#define __declare_arg_4(a0, a1, a2, a3, a4, res) \ + __declare_arg_3(a0, a1, a2, a3, res); \ + register typeof(a4) r4 asm("r4") = a4 + +#define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ + __declare_arg_4(a0, a1, a2, a3, a4, res); \ + register typeof(a5) r5 asm("r5") = a5 + +#define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ + __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ + register typeof(a6) r6 asm("r6") = a6 + +#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ + __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ + register typeof(a7) r7 asm("r7") = a7 + +#define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) +#define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) + +#define ___constraints(count) \ + : __constraint_write_ ## count \ + : __constraint_read_ ## count \ + : "memory" +#define __constraints(count) ___constraints(count) + +/* + * We have an output list that is not necessarily used, and GCC feels + * entitled to optimise the whole sequence away. "volatile" is what + * makes it stick. + */ +#define __arm_smccc_1_1(inst, ...) \ + do { \ + __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ + asm volatile(inst "\n" \ + __constraints(__count_args(__VA_ARGS__))); \ + if (___res) \ + *___res = (typeof(*___res)){r0, r1, r2, r3}; \ + } while (0) + +/* + * arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call + * + * This is a variadic macro taking one to eight source arguments, and + * an optional return structure. + * + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This macro is used to make SMC calls following SMC Calling Convention v1.1. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the SMC instruction. The return values are updated with the content + * from register 0 to 3 on return from the SMC instruction if not NULL. + */ +#define arm_smccc_1_1_smc(...) __arm_smccc_1_1(SMCCC_SMC_INST, __VA_ARGS__) + +/* + * arm_smccc_1_1_hvc() - make an SMCCC v1.1 compliant HVC call + * + * This is a variadic macro taking one to eight source arguments, and + * an optional return structure. + * + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This macro is used to make HVC calls following SMC Calling Convention v1.1. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the HVC instruction. The return values are updated with the content + * from register 0 to 3 on return from the HVC instruction if not NULL. + */ +#define arm_smccc_1_1_hvc(...) __arm_smccc_1_1(SMCCC_HVC_INST, __VA_ARGS__) + #endif /*__ASSEMBLY__*/ #endif /*__LINUX_ARM_SMCCC_H*/ From patchwork Thu Aug 29 11:34:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172619 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092896ily; Thu, 29 Aug 2019 04:36:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqz28obxp8GYzmHdFdk5vwHttUlohogLelRKdjBuyfMIrCWhxgzhhRlZnSyEX8MBKZugN7rf X-Received: by 2002:a63:f04:: with SMTP id e4mr7666342pgl.38.1567078605854; Thu, 29 Aug 2019 04:36:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567078605; cv=none; d=google.com; s=arc-20160816; b=E1AfmdXMXklF/Pz1W+Dk/8sm5AcsUfDdEhKqN0CPAKlPawKIkTvh5jQc6G/7YmvXCc 00mpE7w/W1RoVpH6ds7/bgS1KNmnynhpuTIS9mqGwhwlkw0gsFIKHZ+8E8zNNXZaUy8P MZ4TJYVjVA3GM+z496qdg6i+XbfJj10grSs+m0OkG2Ce82PWEOnev2cgcrf185lgBbla zUiC3+i0HrnLXTMNq9+VnjDeXAVgcg+XE506zhIgSs51hJOHlcElwSQkReN+nEv1TRfA ZKs0gAwMmXUQUMW1bMe0jrv9Ph22Jyrj9s0jwqsEXQQqw+5mfuMADgv/W8E8vb+KSt5q Zp/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TheFOcfsNrP/iCpBXsyGMi/69Bi3Htfiid5k4ekGSX4=; b=kFKbxZe6mu/YDKQ4JCN5/3y/JitdflVjt+41FHybz8pBwJrCxqM6XiVCPX6rvCv4g1 WWal4YvFUmspH3axY0bD6xhW3XUsUR8j2ksoiUX9+rHpbbs1Q758b80Rj1TxWhhT5Ziz iACjJy8FSkpKk4Lxc6P1q0IZw7voXOt8V2ZKAL1uVQX+5fvtZmjE4SnN7FG1PcVRkskG i10RnUN0Mjp7rl6X5U6x7rG2VMCDgQut9U4eXbSVuE31hgAkZmB8Y8BB1NSYogLJi5qU AMr+AuKr/VIp8CC/beZXdHSQ+ZQqkfneaqHJkRJRvWaGKTUlUIL6NDPsqD5JM28yhUbX gSJg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=n38s+xFr; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c67si2276378pfb.211.2019.08.29.04.36.45; Thu, 29 Aug 2019 04:36:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=n38s+xFr; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727653AbfH2Lgp (ORCPT + 14 others); Thu, 29 Aug 2019 07:36:45 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:40420 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727626AbfH2Lgp (ORCPT ); Thu, 29 Aug 2019 07:36:45 -0400 Received: by mail-pf1-f193.google.com with SMTP id w16so1862429pfn.7 for ; Thu, 29 Aug 2019 04:36:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TheFOcfsNrP/iCpBXsyGMi/69Bi3Htfiid5k4ekGSX4=; b=n38s+xFrZoG7NCVO7TAqYKmXPHP2CGuOyeOVNTxy6K9X+QStTrvlEfgSpScbAJXMmq 4NlMZQQvRkmnvgElpw/I0VQQIG8M/alDFia4vW3NEacYu7vgk4VTZIVA3QbP9V7x161R CHIbIvsFIGPH2h7zN+rtDDFxIdD7BkwvvFYl+54KAd8JPt3yIInUNH/D8xtBI0VbhhBu WlPxKGKKJC2NJZmPbJDVVD4W33xE3WaC9luHR/neOStBBQDhwn3X/URdBZObdV6oq1yV OMgJjBhWf57W6iPRWjubtQab+f9ydB36RGZkVxeTAq9jlBmIxbQRE+mu81HjGwdR5Q6b M1gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TheFOcfsNrP/iCpBXsyGMi/69Bi3Htfiid5k4ekGSX4=; b=Y1TN2vNVXAD/+LXaLwlxySeplcPvTuMFnEBuW761HpWKokj9gRgVxHh77Cnk4f9jvW y+wzs2xijIc4dJm9P5/FBmkXmW7+ouaf3RyVvlqPsE0IFmVUFDKWJqU4Bia29gAwWBnE tJrg4jKB8qEjKav9MIsB2McdT9NXysDz2Ayh8tQo4xlMUmkJ/WQEL03BVGK+b8LPeOQv D17FKBG6OJdystCeDW0ScHFEUDjhwYNN+q+CcXu/rM5uV70keAvr9Y4w5mG9AZckpRr4 I4GWvTBlbkxEGT4vUrqHhO4ocFFQ20ZxhmHawnMbz5ucbhWsNWZoyHRiNMsc19H15xgY fROg== X-Gm-Message-State: APjAAAWEJzaN7tkOa4PmDFORK0NLQEp4AftzQkbRL4EtOhEE8Mhyx0NM m/W+Q6kkSKBWorKCU5JUYxJeE2Y9aVc= X-Received: by 2002:aa7:9a12:: with SMTP id w18mr11220897pfj.110.1567078603896; Thu, 29 Aug 2019 04:36:43 -0700 (PDT) Received: from localhost ([122.167.132.221]) by smtp.gmail.com with ESMTPSA id c22sm2767174pfi.82.2019.08.29.04.36.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Aug 2019 04:36:43 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry , Mark Rutland Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH ARM64 v4.4 V3 42/44] arm64: Add ARM_SMCCC_ARCH_WORKAROUND_1 BP hardening support Date: Thu, 29 Aug 2019 17:04:27 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit b092201e0020614127f495c092e0a12d26a2116e upstream. Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1. It is lovely. Really. Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/bpi.S | 20 ++++++++++ arch/arm64/kernel/cpu_errata.c | 68 +++++++++++++++++++++++++++++++++- 2 files changed, 87 insertions(+), 1 deletion(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S index dec95bd82e31..c72f261f4b64 100644 --- a/arch/arm64/kernel/bpi.S +++ b/arch/arm64/kernel/bpi.S @@ -17,6 +17,7 @@ */ #include +#include .macro ventry target .rept 31 @@ -77,3 +78,22 @@ ENTRY(__psci_hyp_bp_inval_start) ldp x0, x1, [sp, #(16 * 8)] add sp, sp, #(8 * 18) ENTRY(__psci_hyp_bp_inval_end) + +.macro smccc_workaround_1 inst + sub sp, sp, #(8 * 4) + stp x2, x3, [sp, #(8 * 0)] + stp x0, x1, [sp, #(8 * 2)] + mov w0, #ARM_SMCCC_ARCH_WORKAROUND_1 + \inst #0 + ldp x2, x3, [sp, #(8 * 0)] + ldp x0, x1, [sp, #(8 * 2)] + add sp, sp, #(8 * 4) +.endm + +ENTRY(__smccc_workaround_1_smc_start) + smccc_workaround_1 smc +ENTRY(__smccc_workaround_1_smc_end) + +ENTRY(__smccc_workaround_1_hvc_start) + smccc_workaround_1 hvc +ENTRY(__smccc_workaround_1_hvc_end) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index ff22915a2865..d5fd7be563bc 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -51,6 +51,10 @@ DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); #ifdef CONFIG_KVM extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; +extern char __smccc_workaround_1_smc_start[]; +extern char __smccc_workaround_1_smc_end[]; +extern char __smccc_workaround_1_hvc_start[]; +extern char __smccc_workaround_1_hvc_end[]; static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, const char *hyp_vecs_end) @@ -95,6 +99,10 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn, #else #define __psci_hyp_bp_inval_start NULL #define __psci_hyp_bp_inval_end NULL +#define __smccc_workaround_1_smc_start NULL +#define __smccc_workaround_1_smc_end NULL +#define __smccc_workaround_1_hvc_start NULL +#define __smccc_workaround_1_hvc_end NULL static void __install_bp_hardening_cb(bp_hardening_cb_t fn, const char *hyp_vecs_start, @@ -121,17 +129,75 @@ static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end); } +#include +#include #include +static void call_smc_arch_workaround_1(void) +{ + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); +} + +static void call_hvc_arch_workaround_1(void) +{ + arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); +} + +static bool check_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry) +{ + bp_hardening_cb_t cb; + void *smccc_start, *smccc_end; + struct arm_smccc_res res; + + if (!entry->matches(entry, SCOPE_LOCAL_CPU)) + return false; + + if (psci_ops.smccc_version == SMCCC_VERSION_1_0) + return false; + + switch (psci_ops.conduit) { + case PSCI_CONDUIT_HVC: + arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, + ARM_SMCCC_ARCH_WORKAROUND_1, &res); + if (res.a0) + return false; + cb = call_hvc_arch_workaround_1; + smccc_start = __smccc_workaround_1_hvc_start; + smccc_end = __smccc_workaround_1_hvc_end; + break; + + case PSCI_CONDUIT_SMC: + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, + ARM_SMCCC_ARCH_WORKAROUND_1, &res); + if (res.a0) + return false; + cb = call_smc_arch_workaround_1; + smccc_start = __smccc_workaround_1_smc_start; + smccc_end = __smccc_workaround_1_smc_end; + break; + + default: + return false; + } + + install_bp_hardening_cb(entry, cb, smccc_start, smccc_end); + + return true; +} + static int enable_psci_bp_hardening(void *data) { const struct arm64_cpu_capabilities *entry = data; - if (psci_ops.get_version) + if (psci_ops.get_version) { + if (check_smccc_arch_workaround_1(entry)) + return 0; + install_bp_hardening_cb(entry, (bp_hardening_cb_t)psci_ops.get_version, __psci_hyp_bp_inval_start, __psci_hyp_bp_inval_end); + } return 0; } From patchwork Thu Aug 29 11:34:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 172620 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2092936ily; Thu, 29 Aug 2019 04:36:48 -0700 (PDT) X-Google-Smtp-Source: APXvYqx2OTfZNKyCYzMzSg/1Ia89k2PKUJvqpAIOkeIhoKteM3lddMS23DIRYGjavjjf57A/giUt X-Received: by 2002:a62:1a45:: with SMTP id a66mr11111892pfa.142.1567078608370; Thu, 29 Aug 2019 04:36:48 -0700 (PDT) ARC-Seal: i=1; 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Now that we've standardised on SMCCC v1.1 to perform the branch prediction invalidation, let's drop the previous band-aid. If vendors haven't updated their firmware to do SMCCC 1.1, they haven't updated PSCI either, so we don't loose anything. Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ v4.4: Dropped switch.c changes ] Signed-off-by: Viresh Kumar --- arch/arm64/kernel/bpi.S | 24 ------------------ arch/arm64/kernel/cpu_errata.c | 45 ++++++++++------------------------ 2 files changed, 13 insertions(+), 56 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S index c72f261f4b64..dc4eb154e33b 100644 --- a/arch/arm64/kernel/bpi.S +++ b/arch/arm64/kernel/bpi.S @@ -54,30 +54,6 @@ ENTRY(__bp_harden_hyp_vecs_start) vectors __kvm_hyp_vector .endr ENTRY(__bp_harden_hyp_vecs_end) -ENTRY(__psci_hyp_bp_inval_start) - sub sp, sp, #(8 * 18) - stp x16, x17, [sp, #(16 * 0)] - stp x14, x15, [sp, #(16 * 1)] - stp x12, x13, [sp, #(16 * 2)] - stp x10, x11, [sp, #(16 * 3)] - stp x8, x9, [sp, #(16 * 4)] - stp x6, x7, [sp, #(16 * 5)] - stp x4, x5, [sp, #(16 * 6)] - stp x2, x3, [sp, #(16 * 7)] - stp x0, x1, [sp, #(16 * 8)] - mov x0, #0x84000000 - smc #0 - ldp x16, x17, [sp, #(16 * 0)] - ldp x14, x15, [sp, #(16 * 1)] - ldp x12, x13, [sp, #(16 * 2)] - ldp x10, x11, [sp, #(16 * 3)] - ldp x8, x9, [sp, #(16 * 4)] - ldp x6, x7, [sp, #(16 * 5)] - ldp x4, x5, [sp, #(16 * 6)] - ldp x2, x3, [sp, #(16 * 7)] - ldp x0, x1, [sp, #(16 * 8)] - add sp, sp, #(8 * 18) -ENTRY(__psci_hyp_bp_inval_end) .macro smccc_workaround_1 inst sub sp, sp, #(8 * 4) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index d5fd7be563bc..2a17789bb963 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -50,7 +50,6 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); #ifdef CONFIG_KVM -extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; extern char __smccc_workaround_1_smc_start[]; extern char __smccc_workaround_1_smc_end[]; extern char __smccc_workaround_1_hvc_start[]; @@ -97,8 +96,6 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn, spin_unlock(&bp_lock); } #else -#define __psci_hyp_bp_inval_start NULL -#define __psci_hyp_bp_inval_end NULL #define __smccc_workaround_1_smc_start NULL #define __smccc_workaround_1_smc_end NULL #define __smccc_workaround_1_hvc_start NULL @@ -143,24 +140,25 @@ static void call_hvc_arch_workaround_1(void) arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); } -static bool check_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry) +static int enable_smccc_arch_workaround_1(void *data) { + const struct arm64_cpu_capabilities *entry = data; bp_hardening_cb_t cb; void *smccc_start, *smccc_end; struct arm_smccc_res res; if (!entry->matches(entry, SCOPE_LOCAL_CPU)) - return false; + return 0; if (psci_ops.smccc_version == SMCCC_VERSION_1_0) - return false; + return 0; switch (psci_ops.conduit) { case PSCI_CONDUIT_HVC: arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, ARM_SMCCC_ARCH_WORKAROUND_1, &res); if (res.a0) - return false; + return 0; cb = call_hvc_arch_workaround_1; smccc_start = __smccc_workaround_1_hvc_start; smccc_end = __smccc_workaround_1_hvc_end; @@ -170,35 +168,18 @@ static bool check_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *e arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, ARM_SMCCC_ARCH_WORKAROUND_1, &res); if (res.a0) - return false; + return 0; cb = call_smc_arch_workaround_1; smccc_start = __smccc_workaround_1_smc_start; smccc_end = __smccc_workaround_1_smc_end; break; default: - return false; + return 0; } install_bp_hardening_cb(entry, cb, smccc_start, smccc_end); - return true; -} - -static int enable_psci_bp_hardening(void *data) -{ - const struct arm64_cpu_capabilities *entry = data; - - if (psci_ops.get_version) { - if (check_smccc_arch_workaround_1(entry)) - return 0; - - install_bp_hardening_cb(entry, - (bp_hardening_cb_t)psci_ops.get_version, - __psci_hyp_bp_inval_start, - __psci_hyp_bp_inval_end); - } - return 0; } #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ @@ -283,32 +264,32 @@ const struct arm64_cpu_capabilities arm64_errata[] = { { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, #endif { From patchwork Thu Aug 29 11:34:29 2019 Content-Type: text/plain; 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The arm64 futex code has some explicit dereferencing of user pointers where performing atomic operations in response to a futex command. This patch uses masking to limit any speculative futex operations to within the user address space. Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/futex.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b Reviewed-by: Mark Rutland [v4.4 backport] diff --git a/arch/arm64/include/asm/futex.h b/arch/arm64/include/asm/futex.h index 34d4d2e2f561..8ab6e83cb629 100644 --- a/arch/arm64/include/asm/futex.h +++ b/arch/arm64/include/asm/futex.h @@ -53,9 +53,10 @@ : "memory") static inline int -arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr) +arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *_uaddr) { int oldval = 0, ret, tmp; + u32 __user *uaddr = __uaccess_mask_ptr(_uaddr); pagefault_disable(); @@ -93,15 +94,17 @@ arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr) } static inline int -futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *_uaddr, u32 oldval, u32 newval) { int ret = 0; u32 val, tmp; + u32 __user *uaddr; - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) + if (!access_ok(VERIFY_WRITE, _uaddr, sizeof(u32))) return -EFAULT; + uaddr = __uaccess_mask_ptr(_uaddr); asm volatile("// futex_atomic_cmpxchg_inatomic\n" ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, CONFIG_ARM64_PAN) " prfm pstl1strm, %2\n"