From patchwork Fri Dec 15 07:39:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 754525 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A600D107B4; Fri, 15 Dec 2023 07:40:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="BM+dOhc9" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BF3orro031304; Fri, 15 Dec 2023 07:40:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=yrH4I9MLB1rBoTIeqw2Ara0pvTd3qHEwJTMWIE48IO0=; b=BM +dOhc9y/FU4QTkNzcJjmXG5RsYmPubZvunktO1r6l43xgYZH6fNPW1Ch35HNZcRb wHbqEiEllCpRb0100ogqv6AhoOLfluHI358A9exuOQzLHtG9Rk0P1Zg8TCexf5+N L+35o548qws67/2j/v/Jt2zIKavxOfri/xlrSy0+GPLaXJFtd9mJIErya4RcThcO EBsOvKEXiKHQ3fKOxSul1swjGgHvEwFoxBv61v6s276AGELgTZ7yThJC9k4dV2rm ZdEye+yn1OtpOlswhhdyIT6qQV3JE9Xg7mqPJPqkxYOYppcyZ7ZhxtIlqhcz4WS2 5BjckeGAQSQdktPLgJZw== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uysrpu5u7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:40:31 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BF7eVC7022277 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:40:31 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:40:26 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , , Russell King Subject: [PATCH v8 01/14] net: phy: introduce core support for phy-mode = "10g-qxgmii" Date: Fri, 15 Dec 2023 15:39:51 +0800 Message-ID: <20231215074005.26976-2-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: eC44DPYKKp4gnutReU_KR3V7XSv0_AGw X-Proofpoint-GUID: eC44DPYKKp4gnutReU_KR3V7XSv0_AGw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 lowpriorityscore=0 clxscore=1011 malwarescore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 From: Vladimir Oltean 10G-QXGMII is a MAC-to-PHY interface defined by the USXGMII multiport specification. It uses the same signaling as USXGMII, but it multiplexes 4 ports over the link, resulting in a maximum speed of 2.5G per port. Some in-tree SoCs like the NXP LS1028A use "usxgmii" when they mean either the single-port USXGMII or the quad-port 10G-QXGMII variant, and they could get away just fine with that thus far. But there is a need to distinguish between the 2 as far as SerDes drivers are concerned. Signed-off-by: Vladimir Oltean Signed-off-by: Luo Jie Reviewed-by: Andrew Lunn Reviewed-by: Russell King (Oracle) --- Documentation/networking/phy.rst | 6 ++++++ drivers/net/phy/phy-core.c | 1 + drivers/net/phy/phylink.c | 11 +++++++++-- include/linux/phy.h | 4 ++++ include/linux/phylink.h | 2 ++ 5 files changed, 22 insertions(+), 2 deletions(-) diff --git a/Documentation/networking/phy.rst b/Documentation/networking/phy.rst index 1283240d7620..f64641417c54 100644 --- a/Documentation/networking/phy.rst +++ b/Documentation/networking/phy.rst @@ -327,6 +327,12 @@ Some of the interface modes are described below: This is the Penta SGMII mode, it is similar to QSGMII but it combines 5 SGMII lines into a single link compared to 4 on QSGMII. +``PHY_INTERFACE_MODE_10G_QXGMII`` + Represents the 10G-QXGMII PHY-MAC interface as defined by the Cisco USXGMII + Multiport Copper Interface document. It supports 4 ports over a 10.3125 GHz + SerDes lane, each port having speeds of 2.5G / 1G / 100M / 10M achieved + through symbol replication. The PCS expects the standard USXGMII code word. + Pause frames / flow control =========================== diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c index 966c93cbe616..1cd58723d6d0 100644 --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c @@ -141,6 +141,7 @@ int phy_interface_num_ports(phy_interface_t interface) return 1; case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_QUSGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: return 4; case PHY_INTERFACE_MODE_PSGMII: return 5; diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 48d3bd3e9fc7..938faac14930 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -231,6 +231,7 @@ static int phylink_interface_max_speed(phy_interface_t interface) return SPEED_1000; case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_10G_QXGMII: return SPEED_2500; case PHY_INTERFACE_MODE_5GBASER: @@ -500,7 +501,11 @@ static unsigned long phylink_get_capabilities(phy_interface_t interface, switch (interface) { case PHY_INTERFACE_MODE_USXGMII: - caps |= MAC_10000FD | MAC_5000FD | MAC_2500FD; + caps |= MAC_10000FD | MAC_5000FD; + fallthrough; + + case PHY_INTERFACE_MODE_10G_QXGMII: + caps |= MAC_2500FD; fallthrough; case PHY_INTERFACE_MODE_RGMII_TXID: @@ -941,6 +946,7 @@ static int phylink_parse_mode(struct phylink *pl, phylink_set(pl->supported, 25000baseSR_Full); fallthrough; case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: case PHY_INTERFACE_MODE_10GKR: case PHY_INTERFACE_MODE_10GBASER: phylink_set(pl->supported, 10baseT_Half); @@ -1837,7 +1843,8 @@ static int phylink_validate_phy(struct phylink *pl, struct phy_device *phy, if (phy->is_c45 && state->rate_matching == RATE_MATCH_NONE && state->interface != PHY_INTERFACE_MODE_RXAUI && state->interface != PHY_INTERFACE_MODE_XAUI && - state->interface != PHY_INTERFACE_MODE_USXGMII) + state->interface != PHY_INTERFACE_MODE_USXGMII && + state->interface != PHY_INTERFACE_MODE_10G_QXGMII) state->interface = PHY_INTERFACE_MODE_NA; return phylink_validate(pl, supported, state); diff --git a/include/linux/phy.h b/include/linux/phy.h index dbb5e13e3e1b..87859a32f6ef 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -125,6 +125,7 @@ extern const int phy_10gbit_features_array[1]; * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN + * @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII * @PHY_INTERFACE_MODE_MAX: Book keeping * * Describes the interface between the MAC and PHY. @@ -165,6 +166,7 @@ typedef enum { PHY_INTERFACE_MODE_10GKR, PHY_INTERFACE_MODE_QUSGMII, PHY_INTERFACE_MODE_1000BASEKX, + PHY_INTERFACE_MODE_10G_QXGMII, PHY_INTERFACE_MODE_MAX, } phy_interface_t; @@ -286,6 +288,8 @@ static inline const char *phy_modes(phy_interface_t interface) return "100base-x"; case PHY_INTERFACE_MODE_QUSGMII: return "qusgmii"; + case PHY_INTERFACE_MODE_10G_QXGMII: + return "10g-qxgmii"; default: return "unknown"; } diff --git a/include/linux/phylink.h b/include/linux/phylink.h index 875439ab45de..92bd2726cc8a 100644 --- a/include/linux/phylink.h +++ b/include/linux/phylink.h @@ -128,6 +128,7 @@ static inline unsigned int phylink_pcs_neg_mode(unsigned int mode, case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_QUSGMII: case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: /* These protocols are designed for use with a PHY which * communicates its negotiation result back to the MAC via * inband communication. Note: there exist PHYs that run @@ -680,6 +681,7 @@ static inline int phylink_get_link_timer_ns(phy_interface_t interface) case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: return 1600000; case PHY_INTERFACE_MODE_1000BASEX: From patchwork Fri Dec 15 07:39:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 755330 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2330515AD1; Fri, 15 Dec 2023 07:41:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="UDXA9K0/" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BF6HeXC015948; Fri, 15 Dec 2023 07:40:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=8TbqspJYbdL/IuX/TEac0i9VshMmSvoHEJ8s53kuZdY=; b=UD XA9K0/QAKbvqKIC3BKdheXuQhAKt/DRNLaRF95wBWBx4bAizGdq/f7ESEknc9hb3 DfOvI8mgZQKLspXyexc/J/W2Fr6Sz4jkgKYPhzg1fisJhG6RH9jv2yj+KrUPAuTz CX/DVGTzijBeeP6yIzLkTsBVtB5LQs2UfVeDB2RbBLVhHH+i/PNpLPLSTgL0tOz+ EYgjuQUWi8/lTHOcNgWPnUx+HxwaDFgSIBFfNmRM2fdb56cpKjaJ9L1sDyDAO4zd 66KPls0mBQ0ecyKSEhuU9M8jW7ZTHr7NL6uvBtGlHJRjHG+3GhmwpNz5jbR53M9K kAbw6EAXalWK0+Nd0pog== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3v0hdf86xj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:40:36 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BF7eZbu021320 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:40:35 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:40:31 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , , Conor Dooley Subject: [PATCH v8 02/14] dt-bindings: net: ethernet-controller: add 10g-qxgmii mode Date: Fri, 15 Dec 2023 15:39:52 +0800 Message-ID: <20231215074005.26976-3-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: R1Ht2yVbj2hPwiEkHlZPJ_baP76zoO6l X-Proofpoint-GUID: R1Ht2yVbj2hPwiEkHlZPJ_baP76zoO6l X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=966 impostorscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 priorityscore=1501 mlxscore=0 phishscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 From: Vladimir Oltean Add the new interface mode 10g-qxgmii, which is similar to usxgmii but extend to 4 channels to support maximum of 4 ports with the link speed 10M/100M/1G/2.5G. Signed-off-by: Vladimir Oltean Signed-off-by: Luo Jie Acked-by: Conor Dooley Reviewed-by: Andrew Lunn --- Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index d14d123ad7a0..0ef6103c5fd8 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -104,6 +104,7 @@ properties: - usxgmii - 10gbase-r - 25gbase-r + - 10g-qxgmii phy-mode: $ref: "#/properties/phy-connection-type" From patchwork Fri Dec 15 07:39:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 754524 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73A6B171A6; Fri, 15 Dec 2023 07:41:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="WjChY9h4" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BF1lDQ6016090; Fri, 15 Dec 2023 07:40:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=7EcrWuVPNPlFIOb9ibXQQvSvBKt1s8SH1X++e787ah0=; b=Wj ChY9h4UxkTtrvJxKXo+M7c8MbE5NOTHfpV+Ky1SOyG12qUhTGdQWOxEaE5FRAp54 woD5awvU90C3ubDlaRzyC32g7ooz6My+Q/3A9H257nYHJb+yUrKpJOdNy4SjFf96 IDMCquSbicriLmFIj8svUdtJy7fxByKsYjftFHVfWwflOajuwrB1Ahvbm8rURPFz OaKHbubN7d0sm92AuBX917PDtP0TZ2STC/CnP3zTpnkMt6L3dsm3sqDQHrZJiTUC fQS02qYslf5IF+F3lmA9tJ1oMFO9lK4R2vbn1BY6AY9+01b3EgVxa2jSHBJx0S/O I/Tbro+tttdnhCPY0xdA== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uysrpu5ug-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:40:40 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BF7eeWw022305 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:40:40 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:40:35 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 03/14] net: phy: at803x: add QCA8084 ethernet phy support Date: Fri, 15 Dec 2023 15:39:53 +0800 Message-ID: <20231215074005.26976-4-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Ocxn7EI-dBn93S0TsSc28NXxt-HcBvy_ X-Proofpoint-GUID: Ocxn7EI-dBn93S0TsSc28NXxt-HcBvy_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 mlxscore=0 bulkscore=0 mlxlogscore=965 priorityscore=1501 impostorscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 Add qca8084 PHY support, which is four-port PHY with maximum link capability 2.5G, the features of each port is almost same as QCA8081 and slave seed config is not needed. Three kind of interface modes supported by qca8084. PHY_INTERFACE_MODE_10G_QXGMII, PHY_INTERFACE_MODE_2500BASEX and PHY_INTERFACE_MODE_SGMII. The PCS(serdes) and clock are also needed to be configured to bringup qca8084 PHY, which will be added in the pcs driver. The additional CDT configurations used for qca8084. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 49 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index b9d3a26cf6dc..eacde4fa5d6c 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -176,6 +176,7 @@ #define AT8030_PHY_ID_MASK 0xffffffef #define QCA8081_PHY_ID 0x004dd101 +#define QCA8084_PHY_ID 0x004dd180 #define QCA8327_A_PHY_ID 0x004dd033 #define QCA8327_B_PHY_ID 0x004dd034 @@ -1835,6 +1836,9 @@ static bool qca808x_is_prefer_master(struct phy_device *phydev) static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev) { + if (phydev_id_compare(phydev, QCA8084_PHY_ID)) + return false; + return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); } @@ -1899,6 +1903,23 @@ static int qca808x_read_status(struct phy_device *phydev) return ret; if (phydev->link) { + /* There are two PCSs available for QCA8084, which support the + * following interface modes. + * + * 1. PHY_INTERFACE_MODE_10G_QXGMII utilizes PCS1 for all + * available 4 ports, which is for all link speeds. + * + * 2. PHY_INTERFACE_MODE_2500BASEX utilizes PCS0 for the + * fourth port, which is only for the link speed 2500M same + * as QCA8081. + * + * 3. PHY_INTERFACE_MODE_SGMII utilizes PCS0 for the fourth + * port, which is for the link speed 10M, 100M and 1000M same + * as QCA8081. + */ + if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII) + return 0; + if (phydev->speed == SPEED_2500) phydev->interface = PHY_INTERFACE_MODE_2500BASEX; else @@ -2033,6 +2054,14 @@ static int qca808x_cable_test_start(struct phy_device *phydev) phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); + if (phydev_id_compare(phydev, QCA8084_PHY_ID)) { + /* Adjust the positive and negative pulse thereshold of CDT */ + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8075, 0xa060); + + /* Disable the near echo bypass */ + phy_modify_mmd(phydev, MDIO_MMD_PCS, 0x807f, BIT(15), 0); + } + return 0; } @@ -2304,6 +2333,25 @@ static struct phy_driver at803x_driver[] = { .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, .link_change_notify = qca808x_link_change_notify, +}, { + /* Qualcomm QCA8084 */ + PHY_ID_MATCH_MODEL(QCA8084_PHY_ID), + .name = "Qualcomm QCA8084", + .flags = PHY_POLL_CABLE_TEST, + .config_intr = at803x_config_intr, + .handle_interrupt = at803x_handle_interrupt, + .get_tunable = at803x_get_tunable, + .set_tunable = at803x_set_tunable, + .set_wol = at803x_set_wol, + .get_wol = at803x_get_wol, + .get_features = qca808x_get_features, + .config_aneg = at803x_config_aneg, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_status = qca808x_read_status, + .soft_reset = qca808x_soft_reset, + .cable_test_start = qca808x_cable_test_start, + .cable_test_get_status = qca808x_cable_test_get_status, }, }; module_phy_driver(at803x_driver); @@ -2319,6 +2367,7 @@ static struct mdio_device_id __maybe_unused atheros_tbl[] = { { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, + { PHY_ID_MATCH_MODEL(QCA8084_PHY_ID) }, { } }; From patchwork Fri Dec 15 07:39:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 755329 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 582D6199A9; Fri, 15 Dec 2023 07:41:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index eacde4fa5d6c..1030896dd546 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -922,6 +922,12 @@ static void at803x_link_change_notify(struct phy_device *phydev) } } +static bool phydev_id_is_qca808x(struct phy_device *phydev) +{ + return phydev_id_compare(phydev, QCA8081_PHY_ID) || + phydev_id_compare(phydev, QCA8084_PHY_ID); +} + static int at803x_read_specific_status(struct phy_device *phydev) { int ss; @@ -941,8 +947,8 @@ static int at803x_read_specific_status(struct phy_device *phydev) if (sfc < 0) return sfc; - /* qca8081 takes the different bits for speed value from at803x */ - if (phydev->drv->phy_id == QCA8081_PHY_ID) + /* qca808x takes the different bits for speed value from at803x */ + if (phydev_id_is_qca808x(phydev)) speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss); else speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss); @@ -1073,7 +1079,7 @@ static int at803x_config_aneg(struct phy_device *phydev) */ ret = 0; - if (phydev->drv->phy_id == QCA8081_PHY_ID) { + if (phydev_id_is_qca808x(phydev)) { int phy_ctrl = 0; /* The reg MII_BMCR also needs to be configured for force mode, the From patchwork Fri Dec 15 07:39:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 754523 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 511341798E; Fri, 15 Dec 2023 07:41:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ooL6fgF0" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BF6eU7G031895; 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Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 1030896dd546..252fae4329cc 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -280,6 +280,15 @@ #define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072 #define QCA8081_PHY_FIFO_RSTN BIT(11) +/* QCA8084 ADC clock edge */ +#define QCA8084_ADC_CLK_SEL 0x8b80 +#define QCA8084_ADC_CLK_SEL_ACLK GENMASK(7, 4) +#define QCA8084_ADC_CLK_SEL_ACLK_FALL 0xf +#define QCA8084_ADC_CLK_SEL_ACLK_RISE 0x0 + +#define QCA8084_MSE_THRESHOLD 0x800a +#define QCA8084_MSE_THRESHOLD_2P5G_VAL 0x51c6 + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -2163,6 +2172,26 @@ static void qca808x_link_change_notify(struct phy_device *phydev) QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); } +static int qca8084_config_init(struct phy_device *phydev) +{ + int ret; + + /* Invert ADC clock edge */ + ret = at803x_debug_reg_mask(phydev, QCA8084_ADC_CLK_SEL, + QCA8084_ADC_CLK_SEL_ACLK, + FIELD_PREP(QCA8084_ADC_CLK_SEL_ACLK, + QCA8084_ADC_CLK_SEL_ACLK_FALL)); + if (ret < 0) + return ret; + + /* Adjust MSE threshold value to avoid link issue with + * some link partner. + */ + return phy_write_mmd(phydev, MDIO_MMD_PMAPMD, + QCA8084_MSE_THRESHOLD, + QCA8084_MSE_THRESHOLD_2P5G_VAL); +} + static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ @@ -2358,6 +2387,7 @@ static struct phy_driver at803x_driver[] = { .soft_reset = qca808x_soft_reset, .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, + .config_init = qca8084_config_init, }, }; module_phy_driver(at803x_driver); From patchwork Fri Dec 15 07:39:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 754522 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 848831BDDC; Fri, 15 Dec 2023 07:41:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="kOfX8EMg" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BF4FYsi012570; Fri, 15 Dec 2023 07:40:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=7+uJJsu7r1bUFsYmXKjWyci5NkWtJ9QfDE/bEKYNGi4=; b=kO fX8EMggrnJZSdnX85aXLbmklAI1Ab2vT1OF1TKG4EkJN6/COQm9dIVUBFyACQNFt 0gelLMstqeggovyxJ0ThQPZP3JnNGUijBlObgumGMJIa9yJMYczZhhdyOwJeMeZJ WwDiopGtjzl3sR3dVUC+FGVQqyJ7cSe7WtOBCL2N4F8+XDGDKcLfV50MyucqSp13 fSRmeNt493ZUCEOi9aYeiF9cLRP2Z2qANo9yicLCZNnd+uvXsLvc/aTI8l5vrUmS bzRXYcrVLdS2k5sJ1hroFr91cnkLElqWfFRHKgnjG9Nx7bmi5HRBN8GroSwSCocW KqC1m/MZFo1AUaWH+69g== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3v05jqhhcm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:40:53 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BF7erYh002820 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:40:53 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:40:48 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 06/14] net: phy: at803x: add qca8084_link_change_notify Date: Fri, 15 Dec 2023 15:39:56 +0800 Message-ID: <20231215074005.26976-7-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: gqoNSi-LJIoA_ez-vGOEIq0HPfvfEzZ9 X-Proofpoint-GUID: gqoNSi-LJIoA_ez-vGOEIq0HPfvfEzZ9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 adultscore=0 suspectscore=0 spamscore=0 mlxscore=0 clxscore=1015 impostorscore=0 phishscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 When the link is changed, qca8084 needs to do the fifo reset and adjust the IPG level for the qusgmii link speed 1000M. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 41 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 252fae4329cc..bb382089ab77 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -289,6 +289,13 @@ #define QCA8084_MSE_THRESHOLD 0x800a #define QCA8084_MSE_THRESHOLD_2P5G_VAL 0x51c6 +#define QCA8084_FIFO_CONTROL 0x19 +#define QCA8084_FIFO_MAC_2_PHY BIT(1) +#define QCA8084_FIFO_PHY_2_MAC BIT(0) + +#define QCA8084_MMD7_IPG_OP 0x901d +#define QCA8084_IPG_10_TO_11_EN BIT(0) + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -2192,6 +2199,39 @@ static int qca8084_config_init(struct phy_device *phydev) QCA8084_MSE_THRESHOLD_2P5G_VAL); } +static void qca8084_link_change_notify(struct phy_device *phydev) +{ + int ret; + + ret = phy_modify(phydev, QCA8084_FIFO_CONTROL, + QCA8084_FIFO_MAC_2_PHY | QCA8084_FIFO_PHY_2_MAC, + 0); + if (ret) + return; + + /* If the PHY works on PHY_INTERFACE_MODE_10G_QXGMII mode, the fifo + * needs to be kept as reset state in link down status. + */ + if (phydev->interface != PHY_INTERFACE_MODE_10G_QXGMII || + phydev->link) { + msleep(50); + ret = phy_modify(phydev, QCA8084_FIFO_CONTROL, + QCA8084_FIFO_MAC_2_PHY | + QCA8084_FIFO_PHY_2_MAC, + QCA8084_FIFO_MAC_2_PHY | + QCA8084_FIFO_PHY_2_MAC); + if (ret) + return; + } + + /* Enable IPG 10 to 11 tuning on link speed 1000M of QUSGMII mode. */ + if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII) + phy_modify_mmd(phydev, MDIO_MMD_AN, QCA8084_MMD7_IPG_OP, + QCA8084_IPG_10_TO_11_EN, + phydev->speed == SPEED_1000 ? + QCA8084_IPG_10_TO_11_EN : 0); +} + static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ @@ -2388,6 +2428,7 @@ static struct phy_driver at803x_driver[] = { .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, .config_init = qca8084_config_init, + .link_change_notify = qca8084_link_change_notify, }, }; module_phy_driver(at803x_driver); From patchwork Fri Dec 15 07:39:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 755328 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 714681947C; Fri, 15 Dec 2023 07:41:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="HlI6XGqb" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BF4o2O0022299; Fri, 15 Dec 2023 07:40:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=dJ5kQvuoEbVrG4WmjFAM8eSccltqgqQY4QEeEFSI+gk=; b=Hl I6XGqb3okTHmJAtVktLZ/3egBSh309JPdCBGLNWklZlBe6SvWdoX32SpYE3Ulnq5 QBXoDTKOdPc6o4SiOyxl4WxPE4pWMaZb5qPzjq3wHAYnj0HgPt7g2ksmfVQjDvfj 1106D0VZINS4K8f5IlttrXqeXD1adMr1qJAE2XYAUI7OCL1F/JPX/BWT159rDxU8 yTR7owizsmZqDbxiVvJ54slzsLpSRXqbakmejYc5W663wVfl/UzifM4RFaeLW2Ra aQkLYj2qZQW8+ySVAmlsPZqIp5McAmmDqHcMm1nG6koR/FnkRZ8yIxRyYuJ7EBj4 fkT/udd3GkHlc9zUJ73g== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3v07c6286b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:40:58 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BF7ev71021940 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:40:57 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:40:53 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 07/14] net: phy: at803x: add the possible_interfaces Date: Fri, 15 Dec 2023 15:39:57 +0800 Message-ID: <20231215074005.26976-8-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 9Z0uW0s37wvLdjGJ4fJsZZfAowzMiEOz X-Proofpoint-ORIG-GUID: 9Z0uW0s37wvLdjGJ4fJsZZfAowzMiEOz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=954 mlxscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 spamscore=0 phishscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 When qca808x works on the interface mode sgmii or 2500base-x, the interface mode can be switched according to the PHY link speed. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index bb382089ab77..cd1bdb61d122 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -2179,10 +2179,22 @@ static void qca808x_link_change_notify(struct phy_device *phydev) QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); } +static void qca808x_fill_possible_interfaces(struct phy_device *phydev) +{ + unsigned long *possible = phydev->possible_interfaces; + + if (phydev->interface != PHY_INTERFACE_MODE_10G_QXGMII) { + __set_bit(PHY_INTERFACE_MODE_2500BASEX, possible); + __set_bit(PHY_INTERFACE_MODE_SGMII, possible); + } +} + static int qca8084_config_init(struct phy_device *phydev) { int ret; + qca808x_fill_possible_interfaces(phydev); + /* Invert ADC clock edge */ ret = at803x_debug_reg_mask(phydev, QCA8084_ADC_CLK_SEL, QCA8084_ADC_CLK_SEL_ACLK, From patchwork Fri Dec 15 07:39:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 754521 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CB6C2556D; Fri, 15 Dec 2023 07:41:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="QxRuoIVz" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BF6MrIJ017495; Fri, 15 Dec 2023 07:41:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=aIflHOg5j1TD5f9dlGljKMBH2UICanRLywB993J/YwY=; b=Qx RuoIVzx+EE96WpuEhrLghz7q8FuNuq0tfdy94WNXCT8oPqNgYypHhj4zIsPU+xvR 4rJWSDLaMpORIpQPr6gLkQh6XKIMs114ho64rmK539kozAvQVK/5xpAC1wcoaj8/ I9+bxyoQFpz6zFtgJiU8QCbZrcXCt3q0TCZEmUe0eFWHj8SJ/f6eXme/c/AjqCZ6 GkREBxH8mCQ6hI+azqkmcbHs+UXA6fnHdwD/GZYftQ51JBe61lQtjbsWa7ieLCsN hVgNlspWrI7Z/tljI4cbrvCaF/oEEbl4wXkA922fmTHzA9qW6XmYHKcHDLrZuAtH cYvj+DpmQoPVQoZPiA0Q== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3v090u1pav-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:41:03 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BF7f2ZX002948 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:41:02 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:40:57 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 08/14] net: phy: at803x: add qca8084 switch registe access Date: Fri, 15 Dec 2023 15:39:58 +0800 Message-ID: <20231215074005.26976-9-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: VS13WMsugyyZgO5FD35iY-Z8g9HFBcn9 X-Proofpoint-ORIG-GUID: VS13WMsugyyZgO5FD35iY-Z8g9HFBcn9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 For qca8084 chip, there are GCC, TLMM and security control modules besides the PHY, these moudles are accessed with 32 bits value, which has the special MDIO sequences to read or write this 32bit register. There are initial configurations configured to make qca8084 PHY probeable, and the MDIO address of qca8084 can be programmed for the PHY device and PCS device. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 85 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index cd1bdb61d122..4982bde5a8a5 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -296,6 +296,13 @@ #define QCA8084_MMD7_IPG_OP 0x901d #define QCA8084_IPG_10_TO_11_EN BIT(0) +/* QCA8084 includes secure control module, which supports customizing the + * MDIO address of PHY device and PCS device, the register of secure control + * is accessed by MDIO bus with the special MDIO sequences. + */ +#define QCA8084_HIGH_ADDR_PREFIX 0x18 +#define QCA8084_LOW_ADDR_PREFIX 0x10 + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -408,6 +415,84 @@ static int at803x_read_page(struct phy_device *phydev) return AT803X_PAGE_FIBER; } +static void qca8084_split_addr(u32 regaddr, u16 *r1, u16 *r2, + u16 *page, u16 *sw_addr) +{ + *r1 = regaddr & 0x1c; + + regaddr >>= 5; + *r2 = regaddr & 0x7; + + regaddr >>= 3; + *page = regaddr & 0xffff; + + regaddr >>= 16; + *sw_addr = regaddr & 0xff; +} + +static int __qca8084_set_page(struct mii_bus *bus, u16 sw_addr, u16 page) +{ + return __mdiobus_write(bus, QCA8084_HIGH_ADDR_PREFIX | (sw_addr >> 5), + sw_addr & 0x1f, page); +} + +static int __qca8084_mii_read(struct mii_bus *bus, u16 addr, u16 reg, u32 *val) +{ + int ret, data; + + ret = __mdiobus_read(bus, addr, reg); + if (ret >= 0) { + data = ret; + + ret = __mdiobus_read(bus, addr, reg | BIT(1)); + if (ret >= 0) + *val = data | ret << 16; + } + + return ret < 0 ? ret : 0; +} + +static int __qca8084_mii_write(struct mii_bus *bus, u16 addr, u16 reg, u32 val) +{ + int ret; + + ret = __mdiobus_write(bus, addr, reg, lower_16_bits(val)); + if (!ret) + ret = __mdiobus_write(bus, addr, reg | BIT(1), upper_16_bits(val)); + + return ret; +} + +static int qca8084_mii_modify(struct phy_device *phydev, u32 regaddr, + u32 clear, u32 set) +{ + struct mii_bus *bus; + u16 reg, addr, page, sw_addr; + u32 val; + int ret; + + bus = phydev->mdio.bus; + mutex_lock(&bus->mdio_lock); + + qca8084_split_addr(regaddr, ®, &addr, &page, &sw_addr); + ret = __qca8084_set_page(bus, sw_addr, page); + if (ret < 0) + goto qca8084_mii_modify_exit; + + ret = __qca8084_mii_read(bus, QCA8084_LOW_ADDR_PREFIX | addr, + reg, &val); + if (ret < 0) + goto qca8084_mii_modify_exit; + + val &= ~clear; + val |= set; + ret = __qca8084_mii_write(bus, QCA8084_LOW_ADDR_PREFIX | addr, + reg, val); +qca8084_mii_modify_exit: + mutex_unlock(&bus->mdio_lock); + return ret; +}; + static int at803x_enable_rx_delay(struct phy_device *phydev) { return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, From patchwork Fri Dec 15 07:39:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 755327 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 809DF15AD2; Fri, 15 Dec 2023 07:41:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="LGYpKm3L" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BF6CUGu014168; Fri, 15 Dec 2023 07:41:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=RdEmD3F3bi1zawZ4fZPZaXG3kduxBS2lem2ZYGbtznE=; b=LG YpKm3LUCpHylDySCpBGuqqGGxA1B/9TO89APpKGqJykpZq17bxxY0eaYr31KgHMi kaPM0JP+Z4Gl3XGEuvQdsS4nVQ648yLL8Rzv5nB+pGSd/BMX2eoR7frHrnRS6BjR qs4MKb/GCMActx4kj7IsHz0nE/UbNEeL12iddzkhEglT8y2/M0P5hYuCbQvQx9/g VnimaVI2ekLTLG/3fQLPCeaRGqlZHMNDoQeX4GVgwW353urXx2hlPPXml2lhiQUN 0rkzOAyXMIVhDS6OHHCrkf4dHxgqi8m9Mm/uThMNbNKHrsxhpdQCY0eN2kfhYXa4 6DIv9+jlZvqUy6hCaRqA== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3v0hb0073r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:41:07 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BF7f6I1017425 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:41:06 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:41:02 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 09/14] net: phy: at803x: set MDIO address of qca8084 PHY Date: Fri, 15 Dec 2023 15:39:59 +0800 Message-ID: <20231215074005.26976-10-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: sr5AobqIUzm8XPFAzPsebmS0KoR_PxX4 X-Proofpoint-GUID: sr5AobqIUzm8XPFAzPsebmS0KoR_PxX4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 spamscore=0 mlxlogscore=999 clxscore=1015 lowpriorityscore=0 bulkscore=0 suspectscore=0 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 Program the MDIO address of qca8084 PHY and PCS device in the PHY probe function. The MDIO address of qca8084 device is configured according to the property "qcom,phy-addr-fixup" of phy node, which defines the MDIO address for 4 PHYs and 3 PCSes, each MDIO address occupies 5 bits in the config register. The MDIO address of qca8084 should be configured correctly before doing the clock initialization in the PHY probe function, so the property "reg" can't be used to configure the MDIO address of phy device one by one, the clock initialization will be configured with all 4 PHY devices in one PHY probe function. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 61 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 4982bde5a8a5..c8830898ce2e 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -303,6 +303,18 @@ #define QCA8084_HIGH_ADDR_PREFIX 0x18 #define QCA8084_LOW_ADDR_PREFIX 0x10 +#define QCA8084_PCS_CFG 0xc90f014 +#define QCA8084_PCS_ADDR0_MASK GENMASK(4, 0) +#define QCA8084_PCS_ADDR1_MASK GENMASK(9, 5) +#define QCA8084_PCS_ADDR2_MASK GENMASK(14, 10) + +#define QCA8084_EPHY_CFG 0xc90f018 +#define QCA8084_EPHY_ADDR0_MASK GENMASK(4, 0) +#define QCA8084_EPHY_ADDR1_MASK GENMASK(9, 5) +#define QCA8084_EPHY_ADDR2_MASK GENMASK(14, 10) +#define QCA8084_EPHY_ADDR3_MASK GENMASK(19, 15) +#define QCA8084_EPHY_LDO_EN GENMASK(21, 20) + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -764,6 +776,51 @@ static int at803x_parse_dt(struct phy_device *phydev) return 0; } +static int qca8084_parse_and_set_phyaddr(struct phy_device *phydev) +{ + struct device_node *node; + u32 addr[7]; + int ret; + + node = phydev->mdio.dev.of_node; + + /* The property "qcom,phy-addr-fixup" is only defined in one + * PHY device tree node. + */ + ret = of_property_read_u32_array(node, "qcom,phy-addr-fixup", + addr, ARRAY_SIZE(addr)); + if (ret) + return ret == -EINVAL ? 0 : ret; + + /* There are 4 PHYs and 3 PCSes on qca8084 chip, each device address + * occupies 5 bits of the config register to customize the MDIO address. + */ + ret = qca8084_mii_modify(phydev, QCA8084_EPHY_CFG, + QCA8084_EPHY_ADDR0_MASK | + QCA8084_EPHY_ADDR1_MASK | + QCA8084_EPHY_ADDR2_MASK | + QCA8084_EPHY_ADDR3_MASK, + FIELD_PREP(QCA8084_EPHY_ADDR0_MASK, addr[0]) | + FIELD_PREP(QCA8084_EPHY_ADDR1_MASK, addr[1]) | + FIELD_PREP(QCA8084_EPHY_ADDR2_MASK, addr[2]) | + FIELD_PREP(QCA8084_EPHY_ADDR3_MASK, addr[3])); + if (ret) + return ret; + + return qca8084_mii_modify(phydev, QCA8084_PCS_CFG, + QCA8084_PCS_ADDR0_MASK | + QCA8084_PCS_ADDR1_MASK | + QCA8084_PCS_ADDR2_MASK, + FIELD_PREP(QCA8084_PCS_ADDR0_MASK, addr[4]) | + FIELD_PREP(QCA8084_PCS_ADDR1_MASK, addr[5]) | + FIELD_PREP(QCA8084_PCS_ADDR2_MASK, addr[6])); +} + +static int qca8084_probe(struct phy_device *phydev) +{ + return qca8084_parse_and_set_phyaddr(phydev); +} + static int at803x_probe(struct phy_device *phydev) { struct device *dev = &phydev->mdio.dev; @@ -776,6 +833,9 @@ static int at803x_probe(struct phy_device *phydev) phydev->priv = priv; + if (phydev_id_compare(phydev, QCA8084_PHY_ID)) + return qca8084_probe(phydev); + ret = at803x_parse_dt(phydev); if (ret) return ret; @@ -2510,6 +2570,7 @@ static struct phy_driver at803x_driver[] = { PHY_ID_MATCH_MODEL(QCA8084_PHY_ID), .name = "Qualcomm QCA8084", .flags = PHY_POLL_CABLE_TEST, + .probe = at803x_probe, .config_intr = at803x_config_intr, .handle_interrupt = at803x_handle_interrupt, .get_tunable = at803x_get_tunable, From patchwork Fri Dec 15 07:40:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 755325 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34E7C2DB6A; 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Fri, 15 Dec 2023 07:41:11 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BF7fA7T023137 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:41:10 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:41:06 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 10/14] net: phy: at803x: parse qca8084 clocks and resets Date: Fri, 15 Dec 2023 15:40:00 +0800 Message-ID: <20231215074005.26976-11-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: OLesixKOsNH-XVeCyfJ7bjwkc9o125RD X-Proofpoint-GUID: OLesixKOsNH-XVeCyfJ7bjwkc9o125RD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 adultscore=0 suspectscore=0 spamscore=0 mlxscore=0 clxscore=1015 impostorscore=0 phishscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 These clock and reset IDs are needed to bring up qca8084, after the initializations with these clocks and resets, the PHY function can be accessed correctly such as reading the capabilities of PHY. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 87 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index c8830898ce2e..4c884d6b60bc 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -21,6 +21,8 @@ #include #include #include +#include +#include #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 #define AT803X_SFC_ASSERT_CRS BIT(11) @@ -337,6 +339,52 @@ static struct at803x_hw_stat qca83xx_hw_stats[] = { { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, }; +enum { + SRDS0_SYS_CLK, + SRDS1_SYS_CLK, + GEPHY0_SYS_CLK, + GEPHY1_SYS_CLK, + GEPHY2_SYS_CLK, + GEPHY3_SYS_CLK, +}; + +enum { + SRDS0_SYS_RESET, + SRDS1_SYS_RESET, + GEPHY0_SYS_RESET, + GEPHY1_SYS_RESET, + GEPHY2_SYS_RESET, + GEPHY3_SYS_RESET, + GEPHY0_RESET, + GEPHY1_RESET, + GEPHY2_RESET, + GEPHY3_RESET, + GEPHY_DSP_RESET, +}; + +static const char *const qca8084_clock_name[] = { + "srds0_sys", + "srds1_sys", + "gephy0_sys", + "gephy1_sys", + "gephy2_sys", + "gephy3_sys", +}; + +static const char *const qca8084_reset_name[] = { + "srds0_sys", + "srds1_sys", + "gephy0_sys", + "gephy1_sys", + "gephy2_sys", + "gephy3_sys", + "gephy0_soft", + "gephy1_soft", + "gephy2_soft", + "gephy3_soft", + "gephy_dsp", +}; + struct at803x_priv { int flags; u16 clk_25m_reg; @@ -348,6 +396,8 @@ struct at803x_priv { struct regulator_dev *vddio_rdev; struct regulator_dev *vddh_rdev; u64 stats[ARRAY_SIZE(qca83xx_hw_stats)]; + struct clk *clk[ARRAY_SIZE(qca8084_clock_name)]; + struct reset_control *reset[ARRAY_SIZE(qca8084_reset_name)]; }; struct at803x_context { @@ -816,8 +866,45 @@ static int qca8084_parse_and_set_phyaddr(struct phy_device *phydev) FIELD_PREP(QCA8084_PCS_ADDR2_MASK, addr[6])); } +static int qca8084_parse_dt(struct phy_device *phydev) +{ + struct at803x_priv *priv; + int i; + + priv = phydev->priv; + for (i = 0; i < ARRAY_SIZE(qca8084_clock_name); i++) { + priv->clk[i] = devm_clk_get_optional(&phydev->mdio.dev, + qca8084_clock_name[i]); + if (IS_ERR(priv->clk[i])) { + phydev_err(phydev, "failed to get the clock ID %s!\n", + qca8084_clock_name[i]); + + return PTR_ERR(priv->clk[i]); + } + } + + for (i = 0; i < ARRAY_SIZE(qca8084_reset_name); i++) { + priv->reset[i] = devm_reset_control_get_optional_exclusive(&phydev->mdio.dev, + qca8084_reset_name[i]); + if (IS_ERR(priv->reset[i])) { + phydev_err(phydev, "failed to get the reset ID %s!\n", + qca8084_reset_name[i]); + + return PTR_ERR(priv->reset[i]); + } + } + + return 0; +} + static int qca8084_probe(struct phy_device *phydev) { + int ret; + + ret = qca8084_parse_dt(phydev); + if (ret) + return ret; + return qca8084_parse_and_set_phyaddr(phydev); } From patchwork Fri Dec 15 07:40:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 755326 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3A502D029; 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Fri, 15 Dec 2023 07:41:16 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BF7fF2e022290 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:41:15 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:41:10 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 11/14] net: phy: at803x: add qca808x initial config sequence Date: Fri, 15 Dec 2023 15:40:01 +0800 Message-ID: <20231215074005.26976-12-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: js2mG3IoUt3K-BjxiWZi_PVM-QOzSeY_ X-Proofpoint-ORIG-GUID: js2mG3IoUt3K-BjxiWZi_PVM-QOzSeY_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 adultscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 After GPIO reset, these Ethernet clock sequence needs to be configured before reading the features of PHY, the Ethernet system clock works on 25MHZ. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 84 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 83 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 4c884d6b60bc..9885a728c72a 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -897,6 +897,84 @@ static int qca8084_parse_dt(struct phy_device *phydev) return 0; } +static int qca8084_clock_config(struct phy_device *phydev) +{ + struct at803x_priv *priv; + int ret = 0; + + /* The ethernet clock IDs are only defined in one PHY device + * tree node, and these ethernet clocks only needs to be configured + * one time, which work on the clock rate 25MHZ. + */ + priv = phydev->priv; + if (!priv->clk[SRDS0_SYS_CLK]) + return 0; + + ret = clk_set_rate(priv->clk[SRDS0_SYS_CLK], 25000000); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[SRDS0_SYS_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[SRDS1_SYS_CLK]); + if (ret) + return ret; + + /* Reset PCS system clocks */ + reset_control_assert(priv->reset[SRDS0_SYS_RESET]); + reset_control_assert(priv->reset[SRDS1_SYS_RESET]); + fsleep(20000); + + reset_control_deassert(priv->reset[SRDS0_SYS_RESET]); + reset_control_deassert(priv->reset[SRDS1_SYS_RESET]); + + ret = clk_prepare_enable(priv->clk[GEPHY0_SYS_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[GEPHY1_SYS_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[GEPHY2_SYS_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[GEPHY3_SYS_CLK]); + if (ret) + return ret; + + /* Reset ethernet system clocks */ + reset_control_assert(priv->reset[GEPHY0_SYS_RESET]); + reset_control_assert(priv->reset[GEPHY1_SYS_RESET]); + reset_control_assert(priv->reset[GEPHY2_SYS_RESET]); + reset_control_assert(priv->reset[GEPHY3_SYS_RESET]); + fsleep(20000); + + reset_control_deassert(priv->reset[GEPHY0_SYS_RESET]); + reset_control_deassert(priv->reset[GEPHY1_SYS_RESET]); + reset_control_deassert(priv->reset[GEPHY2_SYS_RESET]); + reset_control_deassert(priv->reset[GEPHY3_SYS_RESET]); + + /* Release ethernet DSP reset */ + reset_control_deassert(priv->reset[GEPHY0_RESET]); + reset_control_deassert(priv->reset[GEPHY1_RESET]); + reset_control_deassert(priv->reset[GEPHY2_RESET]); + reset_control_deassert(priv->reset[GEPHY3_RESET]); + reset_control_deassert(priv->reset[GEPHY_DSP_RESET]); + + /* Enable efuse loading into analog circuit */ + ret = qca8084_mii_modify(phydev, QCA8084_EPHY_CFG, + QCA8084_EPHY_LDO_EN, 0); + if (ret) + return ret; + + fsleep(10000); + return 0; +} + static int qca8084_probe(struct phy_device *phydev) { int ret; @@ -905,7 +983,11 @@ static int qca8084_probe(struct phy_device *phydev) if (ret) return ret; - return qca8084_parse_and_set_phyaddr(phydev); + ret = qca8084_parse_and_set_phyaddr(phydev); + if (ret) + return ret; + + return qca8084_clock_config(phydev); } static int at803x_probe(struct phy_device *phydev) From patchwork Fri Dec 15 07:40:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 754520 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E609B2D7AA; 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Fri, 15 Dec 2023 07:41:20 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BF7fJZ5022331 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:41:19 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:41:15 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 12/14] net: phy: at803x: configure qca8084 common clocks Date: Fri, 15 Dec 2023 15:40:02 +0800 Message-ID: <20231215074005.26976-13-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ydnC9ijGTP51n5Tjq2aUS8FJyQTbYZ78 X-Proofpoint-GUID: ydnC9ijGTP51n5Tjq2aUS8FJyQTbYZ78 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 spamscore=0 mlxlogscore=999 clxscore=1015 lowpriorityscore=0 bulkscore=0 suspectscore=0 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 After initial clock sequence, the clock source 312.5MHZ is available, the common clocks based on clock source 312.5MHZ needs to be configured, which includes APB bridge clock tree with rate 312.5MHZ, AHB clock tree with 104.17MHZ. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 69 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 9885a728c72a..3ef4eacf40c7 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -340,6 +340,14 @@ static struct at803x_hw_stat qca83xx_hw_stats[] = { }; enum { + APB_BRIDGE_CLK, + AHB_CLK, + SEC_CTRL_AHB_CLK, + TLMM_CLK, + TLMM_AHB_CLK, + CNOC_AHB_CLK, + MDIO_AHB_CLK, + MDIO_MASTER_AHB_CLK, SRDS0_SYS_CLK, SRDS1_SYS_CLK, GEPHY0_SYS_CLK, @@ -363,6 +371,14 @@ enum { }; static const char *const qca8084_clock_name[] = { + "apb_bridge", + "ahb", + "sec_ctrl_ahb", + "tlmm", + "tlmm_ahb", + "cnoc_ahb", + "mdio_ahb", + "mdio_master_ahb", "srds0_sys", "srds1_sys", "gephy0_sys", @@ -975,6 +991,53 @@ static int qca8084_clock_config(struct phy_device *phydev) return 0; } +static int qca8084_common_clock_init(struct phy_device *phydev) +{ + struct at803x_priv *priv; + int ret = 0; + + priv = phydev->priv; + /* Enable APB bridge tree clock */ + ret = clk_set_rate(priv->clk[APB_BRIDGE_CLK], 312500000); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[APB_BRIDGE_CLK]); + if (ret) + return ret; + + /* Enable AHB tree clocks */ + ret = clk_set_rate(priv->clk[AHB_CLK], 104170000); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[AHB_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[SEC_CTRL_AHB_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[TLMM_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[TLMM_AHB_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[CNOC_AHB_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[MDIO_AHB_CLK]); + if (ret) + return ret; + + return clk_prepare_enable(priv->clk[MDIO_MASTER_AHB_CLK]); +} + static int qca8084_probe(struct phy_device *phydev) { int ret; @@ -987,7 +1050,11 @@ static int qca8084_probe(struct phy_device *phydev) if (ret) return ret; - return qca8084_clock_config(phydev); + ret = qca8084_clock_config(phydev); + if (ret) + return ret; + + return qca8084_common_clock_init(phydev); } static int at803x_probe(struct phy_device *phydev) From patchwork Fri Dec 15 07:40:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 754519 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5752B2DF97; Fri, 15 Dec 2023 07:41:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="KHUNE3HD" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BF4LTQM022214; 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Fri, 15 Dec 2023 07:41:23 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:41:19 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 13/14] net: phy: at803x: configure qca8084 work mode Date: Fri, 15 Dec 2023 15:40:03 +0800 Message-ID: <20231215074005.26976-14-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: m2vpYiDdnsP8sPIVRPedSndbDS1d-WoS X-Proofpoint-ORIG-GUID: m2vpYiDdnsP8sPIVRPedSndbDS1d-WoS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 There are four kind of work modes supported by qca8084. 1. Quad PHYs work on 10g-qxgmii. 2. PHY1, PHY2, PHY3 wors on 10g-qxgmii, PHY4 works on sgmii. 3. Quad PHYs connected with internal MACs by GMII, which works on switch mode. 4. PHY1, PHY2, PHY3 connected with internal MACs by GMII, PHY4 works on sgmii. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 53 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 3ef4eacf40c7..ac72b0551ed8 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -317,6 +317,13 @@ #define QCA8084_EPHY_ADDR3_MASK GENMASK(19, 15) #define QCA8084_EPHY_LDO_EN GENMASK(21, 20) +#define QCA8084_WORK_MODE_CFG 0xc90f030 +#define QCA8084_WORK_MODE_MASK GENMASK(5, 0) +#define QCA8084_WORK_MODE_QXGMII (BIT(5) | GENMASK(3, 0)) +#define QCA8084_WORK_MODE_QXGMII_PORT4_SGMII (BIT(5) | GENMASK(2, 0)) +#define QCA8084_WORK_MODE_SWITCH BIT(4) +#define QCA8084_WORK_MODE_SWITCH_PORT4_SGMII BIT(5) + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -1038,6 +1045,46 @@ static int qca8084_common_clock_init(struct phy_device *phydev) return clk_prepare_enable(priv->clk[MDIO_MASTER_AHB_CLK]); } +static int qca8084_parse_and_set_work_mode(struct phy_device *phydev) +{ + struct device_node *node; + struct at803x_priv *priv; + u32 value, work_mode; + int ret; + + node = phydev->mdio.dev.of_node; + priv = phydev->priv; + + /* The property "qcom,phy-work-mode" is only defined in one + * PHY device tree node. + */ + ret = of_property_read_u32(node, "qcom,phy-work-mode", &value); + if (ret) + return ret == -EINVAL ? 0 : ret; + + switch (value) { + case 0: + work_mode = QCA8084_WORK_MODE_QXGMII; + break; + case 1: + work_mode = QCA8084_WORK_MODE_QXGMII_PORT4_SGMII; + break; + case 2: + work_mode = QCA8084_WORK_MODE_SWITCH; + break; + case 3: + work_mode = QCA8084_WORK_MODE_SWITCH_PORT4_SGMII; + break; + default: + phydev_err(phydev, "invalid qcom,phy-work-mode %d\n", value); + return -EINVAL; + } + + return qca8084_mii_modify(phydev, QCA8084_WORK_MODE_CFG, + QCA8084_WORK_MODE_MASK, + FIELD_PREP(QCA8084_WORK_MODE_MASK, work_mode)); +} + static int qca8084_probe(struct phy_device *phydev) { int ret; @@ -1054,7 +1101,11 @@ static int qca8084_probe(struct phy_device *phydev) if (ret) return ret; - return qca8084_common_clock_init(phydev); + ret = qca8084_common_clock_init(phydev); + if (ret) + return ret; + + return qca8084_parse_and_set_work_mode(phydev); } static int at803x_probe(struct phy_device *phydev) From patchwork Fri Dec 15 07:40:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 755324 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CC1430331; Fri, 15 Dec 2023 07:41:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="htNYVwBU" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BF6HWWf022899; Fri, 15 Dec 2023 07:41:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=AhES8Y7x+ZpiqbfFpeHU+5rxqGlvKWJu/Mp3zVbaca0=; b=ht NYVwBUG0MhcA8iKOg1xpcqrFYN6/1YfR1xwe8qABPDcfFb4yXmPn+ysVsWwwrnR0 nuKeW0cM6q4GQuGy7ATn1uyOgNvGeDUZHvw9cIdsviuSNBEfJgvsH/254mKykPvD JXG/tOAvrY6HUaOf03lUQ7oB3dYsZr3k3AD2qDcOlYGCQYwd/qiavUlSRV4Gcfp4 jjR9kgtZCgSDEUXJ7Njro+gaVHS5ktzpCGsvp8bubUT0rP4WD3ugBzR3J9sXv9p6 MSwn/MpBo/HRq/SNNW+ed/pa91lbsmJ39xTa7BqpqNDkMQzVDapGkl7UCZrjFP1B jB6R2gS6XC+Z6MV6kJmg== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3v0741jcym-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:41:28 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BF7fRMf022408 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Dec 2023 07:41:27 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 23:41:23 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v8 14/14] dt-bindings: net: ar803x: add qca8084 PHY properties Date: Fri, 15 Dec 2023 15:40:04 +0800 Message-ID: <20231215074005.26976-15-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231215074005.26976-1-quic_luoj@quicinc.com> References: <20231215074005.26976-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: yx8mAsx_35qSXdlQGbbb70N0gxc5x5Qj X-Proofpoint-GUID: yx8mAsx_35qSXdlQGbbb70N0gxc5x5Qj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 clxscore=1015 suspectscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 spamscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 mlxlogscore=728 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312150047 The following properties are added for qca8084 PHY. 1. add the compatible string "ethernet-phy-id004d.d180" since the PHY device is not accessible during MDIO bus register. 2. add property "qcom,phy-addr-fixup" for customizing MDIO address. 3. add property "qcom,phy-work-mode" for specifying qca8084 PHY work mode. 4. add the initial clocks and resets. Signed-off-by: Luo Jie --- .../devicetree/bindings/net/qca,ar803x.yaml | 158 +++++++++++++++++- 1 file changed, 155 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/qca,ar803x.yaml b/Documentation/devicetree/bindings/net/qca,ar803x.yaml index 3acd09f0da86..febff039a44f 100644 --- a/Documentation/devicetree/bindings/net/qca,ar803x.yaml +++ b/Documentation/devicetree/bindings/net/qca,ar803x.yaml @@ -14,9 +14,6 @@ maintainers: description: | Bindings for Qualcomm Atheros AR803x PHYs -allOf: - - $ref: ethernet-phy.yaml# - properties: qca,clk-out-frequency: description: Clock output frequency in Hertz. @@ -85,6 +82,161 @@ properties: $ref: /schemas/regulator/regulator.yaml unevaluatedProperties: false + qcom,phy-addr-fixup: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + MDIO address for 4 PHY devices and 3 PCS devices + + qcom,phy-work-mode: + description: PHY device work mode. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + clocks: + items: + - description: APB bridge clock + - description: AHB clock + - description: Security control clock + - description: TLMM clock + - description: TLMM AHB clock + - description: CNOC AHB clock + - description: MDIO AHB clock + - description: MDIO master AHB clock + - description: PCS0 system clock + - description: PCS1 system clock + - description: EPHY0 system clock + - description: EPHY1 system clock + - description: EPHY2 system clock + - description: EPHY3 system clock + description: PHY initial common clock configs + + clock-names: + items: + - const: apb_bridge + - const: ahb + - const: sec_ctrl_ahb + - const: tlmm + - const: tlmm_ahb + - const: cnoc_ahb + - const: mdio_ahb + - const: mdio_master_ahb + - const: srds0_sys + - const: srds1_sys + - const: gephy0_sys + - const: gephy1_sys + - const: gephy2_sys + - const: gephy3_sys + + resets: + items: + - description: PCS0 system reset + - description: PCS1 system reset + - description: EPHY0 system reset + - description: EPHY1 system reset + - description: EPHY2 system reset + - description: EPHY3 system reset + - description: EPHY0 software reset + - description: EPHY1 software reset + - description: EPHY2 software reset + - description: EPHY3 software reset + - description: Ethernet DSP reset + description: PHY initial common reset configs + + reset-names: + items: + - const: srds0_sys + - const: srds1_sys + - const: gephy0_sys + - const: gephy1_sys + - const: gephy2_sys + - const: gephy3_sys + - const: gephy0_soft + - const: gephy1_soft + - const: gephy2_soft + - const: gephy3_soft + - const: gephy_dsp + +allOf: + - $ref: ethernet-phy.yaml# + + - if: + properties: + compatible: + contains: + enum: + - ethernet-phy-id004d.d180 + then: + properties: + clocks: + items: + - description: APB bridge clock + - description: AHB clock + - description: Security control clock + - description: TLMM clock + - description: TLMM AHB clock + - description: CNOC AHB clock + - description: MDIO AHB clock + - description: MDIO master AHB clock + - description: PCS0 system clock + - description: PCS1 system clock + - description: EPHY0 system clock + - description: EPHY1 system clock + - description: EPHY2 system clock + - description: EPHY3 system clock + clock-names: + items: + - const: apb_bridge + - const: ahb + - const: sec_ctrl_ahb + - const: tlmm + - const: tlmm_ahb + - const: cnoc_ahb + - const: mdio_ahb + - const: mdio_master_ahb + - const: srds0_sys + - const: srds1_sys + - const: gephy0_sys + - const: gephy1_sys + - const: gephy2_sys + - const: gephy3_sys + resets: + items: + - description: PCS0 system reset + - description: PCS1 system reset + - description: EPHY0 system reset + - description: EPHY1 system reset + - description: EPHY2 system reset + - description: EPHY3 system reset + - description: EPHY0 software reset + - description: EPHY1 software reset + - description: EPHY2 software reset + - description: EPHY3 software reset + - description: Ethernet DSP reset + reset-names: + items: + - const: srds0_sys + - const: srds1_sys + - const: gephy0_sys + - const: gephy1_sys + - const: gephy2_sys + - const: gephy3_sys + - const: gephy0_soft + - const: gephy1_soft + - const: gephy2_soft + - const: gephy3_soft + - const: gephy_dsp + required: + - qcom,phy-addr-fixup + - qcom,phy-work-mode + - clocks + - clock-names + - resets + - reset-names + else: + properties: + qcom,phy-addr-fixup: false + qcom,phy-work-mode: false + unevaluatedProperties: false examples: