From patchwork Thu Dec 14 05:58:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Sung X-Patchwork-Id: 754640 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="igKCzf4H" Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92691116; Wed, 13 Dec 2023 21:58:56 -0800 (PST) X-UUID: da6e7f589a4511eea5db2bebc7c28f94-20231214 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=3bwWmp38+I/LoyedglLaGgKkEJRhkTImvrhTZ0gSEPs=; b=igKCzf4HofhXL0ogKOVijumawkX37VyIXmmya0y+Fu/vbrGE0Wd/5kGg+fDCrhX+O0HCAqrTsaha4BL4iG7gJrVJUs9xQa9LV5qG/SyJQLkgXjwa2cj7hCnStOHBlK6EEecNE07nG2bsissQ9qyAvs7n4jWHe9z/7lXNWN3oyaY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35, REQID:d89b6128-f6b5-4ca9-9a74-2fbb10a39f39, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7, CLOUDID:b7fc2e61-c89d-4129-91cb-8ebfae4653fc, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: da6e7f589a4511eea5db2bebc7c28f94-20231214 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1991151540; Thu, 14 Dec 2023 13:58:50 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 14 Dec 2023 13:58:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 14 Dec 2023 13:58:48 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , "CK Hu" CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Moudy Ho , Hsiao Chien Sung , Nathan Lu , "Nancy . Lin" , "Roy-CW . Yeh" , "Jason-JH . Lin" , xinlei lee , , , , , Subject: [PATCH v12 01/23] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188 Date: Thu, 14 Dec 2023 13:58:25 +0800 Message-ID: <20231214055847.4936-2-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231214055847.4936-1-shawn.sung@mediatek.com> References: <20231214055847.4936-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--0.514200-8.000000 X-TMASE-MatchedRID: tiRXYRqWr+sDh1tb/sWFHED6z8N1m1ALqm/9CTn1HV3fUZT83lbkED1/ uZDvFhzjSBg3ErWyNT+HEeMTfR0Cex8TzIzimOwPC24oEZ6SpSmb4wHqRpnaDhUxVZ+Rusinlhs Lt/52TF0AWrHvp7qOwsHzTd24q1uoA2TD8tY3kE5k1ZaUl3aMTw3PBm/Zic8sCGQAUePfIpy/dt 4cTkSYy0ma3zYT97IFAYfQIAUhBayZvmCbKVb49sZL6x5U/HridGByp+zdaDg= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--0.514200-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 8F101DB31689358404B0806D8F8142DCAD30F4E8E6952F3CF12E90321A86CBEA2000:8 X-MTK: N Add compatible name for MediaTek MT8188 ETHDR. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Reviewed-by: CK Hu Signed-off-by: Hsiao Chien Sung --- .../bindings/display/mediatek/mediatek,ethdr.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml index 801fa66ae615..677882348ede 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml @@ -23,7 +23,11 @@ description: properties: compatible: - const: mediatek,mt8195-disp-ethdr + oneOf: + - const: mediatek,mt8195-disp-ethdr + - items: + - const: mediatek,mt8188-disp-ethdr + - const: mediatek,mt8195-disp-ethdr reg: maxItems: 7 From patchwork Thu Dec 14 05:58:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Sung X-Patchwork-Id: 754641 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="hQAtEnLN" Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB5CB1BC1; Wed, 13 Dec 2023 21:58:58 -0800 (PST) X-UUID: da65302e9a4511eeba30773df0976c77-20231214 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=zT0/dVzTq/5/KwjP2Gaq1AJNyFqB1WS0NxFr2ZWObRU=; b=hQAtEnLNbhunP6KjD4NVxO192cCE16uHqSw5LM9vQUlSIFNHQeK2Grf5l0freSiGQd+h7RTfynhhFrnH553IE1Flbai3V/nYs5/46Mo17gnJHi25ccLPSlkodAKNQ8n5VuBGEOLbhkeAHDB2i4YX9y1Vle9IvXuu33eay/npvyc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35, REQID:7374aded-f82d-441c-859a-ed1b2de473d5, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7, CLOUDID:3bbfa7fd-4a48-46e2-b946-12f04f20af8c, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: da65302e9a4511eeba30773df0976c77-20231214 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1061979112; Thu, 14 Dec 2023 13:58:50 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 14 Dec 2023 13:58:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 14 Dec 2023 13:58:48 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , "CK Hu" CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Moudy Ho , Hsiao Chien Sung , Nathan Lu , "Nancy . Lin" , "Roy-CW . Yeh" , "Jason-JH . Lin" , xinlei lee , , , , , Subject: [PATCH v12 02/23] dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188 Date: Thu, 14 Dec 2023 13:58:26 +0800 Message-ID: <20231214055847.4936-3-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231214055847.4936-1-shawn.sung@mediatek.com> References: <20231214055847.4936-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--0.514200-8.000000 X-TMASE-MatchedRID: tiRXYRqWr+sDh1tb/sWFHED6z8N1m1ALqm/9CTn1HV3fUZT83lbkED1/ uZDvFhzjSBg3ErWyNT+HEeMTfR0Cex8TzIzimOwPC24oEZ6SpSmb4wHqRpnaDnM7QywOsMaA7nm J4V/Qs0LD2w3h4bqG8G78Q8SFinQH1YTFGXn+YVpCGhrVBcn9nye2Q1OA/Wt49hViwM+K6rnffS 22Lf8M9Ema3zYT97IFAYfQIAUhBayZvmCbKVb49sZL6x5U/HridGByp+zdaDg= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--0.514200-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 7BF01D8E9422302803E2809614DBAD15FC07834700D366739298BB634293B2822000:8 X-MTK: N Add compatible name for MediaTek MT8188 MDP-RDMA. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Reviewed-by: CK Hu Signed-off-by: Hsiao Chien Sung --- .../bindings/display/mediatek/mediatek,mdp-rdma.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml index dd12e2ff685c..7570a0684967 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml @@ -21,7 +21,11 @@ description: properties: compatible: - const: mediatek,mt8195-vdo1-rdma + oneOf: + - const: mediatek,mt8195-vdo1-rdma + - items: + - const: mediatek,mt8188-vdo1-rdma + - const: mediatek,mt8195-vdo1-rdma reg: maxItems: 1 From patchwork Thu Dec 14 05:58:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Sung X-Patchwork-Id: 754637 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="asFqUIDb" Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC1E91BCC; Wed, 13 Dec 2023 21:58:58 -0800 (PST) X-UUID: da4d658e9a4511eeba30773df0976c77-20231214 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Dum0ZzdIzX75g8CGTmR32v++7pJ8YrqnJQNjcoVOBkE=; b=asFqUIDbBr1nGLGTN+ifhP8m5IbbNwS17EuO5bG34V0cohwA48X2KbjfGgRklVeeZK+Jmw7a2iE7DB3uOXm3yjN/b55V4fGQb9oypcyKrkF+ctmCHZFvGwvrCFFFDNQFPRSYylCUOPIrPJTZ1/cUStthNW+r1pB6fETwEraBaWA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35, REQID:55a9bd80-a996-4130-95ea-25ff62557ae8, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7, CLOUDID:a1fc2e61-c89d-4129-91cb-8ebfae4653fc, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: da4d658e9a4511eeba30773df0976c77-20231214 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1483390256; Thu, 14 Dec 2023 13:58:50 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 14 Dec 2023 13:58:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 14 Dec 2023 13:58:48 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Moudy Ho , Hsiao Chien Sung , Nathan Lu , "Nancy . Lin" , "Roy-CW . Yeh" , "Jason-JH . Lin" , xinlei lee , , , , , Subject: [PATCH v12 05/23] dt-bindings: arm: mediatek: Add compatible for MT8188 Date: Thu, 14 Dec 2023 13:58:29 +0800 Message-ID: <20231214055847.4936-6-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231214055847.4936-1-shawn.sung@mediatek.com> References: <20231214055847.4936-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Add compatible name for MediaTek MT8188 VDOSYS1. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Signed-off-by: Hsiao Chien Sung --- .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 536f5a5ebd24..642fa2e4736e 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -32,6 +32,7 @@ properties: - mediatek,mt8183-mmsys - mediatek,mt8186-mmsys - mediatek,mt8188-vdosys0 + - mediatek,mt8188-vdosys1 - mediatek,mt8192-mmsys - mediatek,mt8195-vdosys1 - mediatek,mt8195-vppsys0 From patchwork Thu Dec 14 05:58:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Sung X-Patchwork-Id: 754632 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="RVj61kku" Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99E581FCA; Wed, 13 Dec 2023 21:59:00 -0800 (PST) X-UUID: da7257e09a4511eea5db2bebc7c28f94-20231214 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=UR/S1UxCer2k4dFXkRhizCzcUnDc13Stjl4b3+4bCQw=; b=RVj61kkuG6UUT+lbFVGvSdioSgL5t82umnekhWszZwbKmEVSefaroiv3RACe+DGWYReK40sz3iDmPrXQV9W5TWkMLC+RwfB802Z9M25bDyMyfK52ZziEtpDHqOvnjLhKnaPNRO3R2bmHUQlYvo8E8vGHyyBVicfDGsS9R6gRSdo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35, REQID:c9ad17ed-a138-49d3-8915-9a9db768a626, IP:0, U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:5d391d7, CLOUDID:853c29bd-2ac7-4da2-9f94-677a477649d9, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: da7257e09a4511eea5db2bebc7c28f94-20231214 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 960041727; Thu, 14 Dec 2023 13:58:50 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 14 Dec 2023 13:58:49 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 14 Dec 2023 13:58:49 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , "CK Hu" CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Moudy Ho , Hsiao Chien Sung , Nathan Lu , "Nancy . Lin" , "Roy-CW . Yeh" , "Jason-JH . Lin" , xinlei lee , , , , , Subject: [PATCH v12 07/23] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys Date: Thu, 14 Dec 2023 13:58:31 +0800 Message-ID: <20231214055847.4936-8-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231214055847.4936-1-shawn.sung@mediatek.com> References: <20231214055847.4936-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--12.092300-8.000000 X-TMASE-MatchedRID: fy8eojAHNBhu7xCoxCPC8uG5dRZCgxC3U+A7YkpDJ1j/evmlVf9xZkN+ V6ZFLcNdtJpHKHYUE3Lijpjet3oGSJENJ9hsU5Jwe5NWR5iixe0xmlBLt0TR1qlOTQPV+ZnxfVC vDJTS5GQ0ULOv9iNOM0q+cX2jmfqvmxh0gY/o+VkVglQa/gMvfOzKzoL8f1RMol3uZzZ1GLejCh ZWWXQ3gZMWaqBLFuhwzQoDEar/LDjbyQLwqvsCyZRrnSy7UTtbaN2KuTwsCwL511+bLp7hQB9jn kReMwaFal7mjjOU741jT78HlvEsMrkX/peFUgpWQpxiLlDD9FUn8jQhMLowhQ5SzgJNSArLxQEW kQw644LKSwUInkCO+uXoW8d/wZybh7GScaYGFCD8gEfQ4Av4R+G/rsUP6wPWkR+/pTNS9t33vb5 M20LflOfgapjv6qPbFE5r8gFFSOl3fQM/OfraXNRZ1mKTfKthamKrgqy61cKbKItl61J/yZ+inT K0bC9eKrauXd3MZDXwkc8gQobdR8OTabmISqL1W20auwPpV8FHWVcCRb9mSA3F9QGXn4lU X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--12.092300-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 2084B0D3F3E26B5CCD31E9259596AA531B745E5F4DDB192C8D2E4046CF98A5DC2000:8 X-MTK: N - Add register definitions for MT8188 - Add VDOSYS1 routing table - Update MUTEX definitions accordingly - Set VSYNC length from 0x40 (default) to 1 since ETHDR is bypassed Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mt8188-mmsys.h | 126 ++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 13 +++ drivers/soc/mediatek/mtk-mmsys.h | 29 +++++++ drivers/soc/mediatek/mtk-mutex.c | 35 ++++++++ 4 files changed, 203 insertions(+) diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h index 448cc3761b43..a9490c3c4256 100644 --- a/drivers/soc/mediatek/mt8188-mmsys.h +++ b/drivers/soc/mediatek/mt8188-mmsys.h @@ -67,6 +67,56 @@ #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18) #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19) +#define MT8188_VDO1_HDR_TOP_CFG 0xd00 +#define MT8188_VDO1_MIXER_IN1_ALPHA 0xd30 +#define MT8188_VDO1_MIXER_IN1_PAD 0xd40 +#define MT8188_VDO1_MIXER_VSYNC_LEN 0xd5c +#define MT8188_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 +#define MT8188_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 +#define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04 +#define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1 +#define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08 +#define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1 +#define MT8188_VDO1_DISP_DPI1_SEL_IN 0xf10 +#define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0 +#define MT8188_VDO1_DISP_DP_INTF0_SEL_IN 0xf14 +#define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0 +#define MT8188_VDO1_MERGE4_SOUT_SEL 0xf18 +#define MT8188_MERGE4_SOUT_TO_DPI1_SEL BIT(2) +#define MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL BIT(3) +#define MT8188_VDO1_MIXER_IN1_SEL_IN 0xf24 +#define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_IN2_SEL_IN 0xf28 +#define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_IN3_SEL_IN 0xf2c +#define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_IN4_SEL_IN 0xf30 +#define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_OUT_SOUT_SEL 0xf34 +#define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1 +#define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c +#define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1 +#define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40 +#define MT8188_SOUT_TO_MIXER_IN1_SEL 1 +#define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44 +#define MT8188_SOUT_TO_MIXER_IN2_SEL 1 +#define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48 +#define MT8188_SOUT_TO_MIXER_IN3_SEL 1 +#define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c +#define MT8188_SOUT_TO_MIXER_IN4_SEL 1 +#define MT8188_VDO1_MERGE4_ASYNC_SEL_IN 0xf50 +#define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1 +#define MT8188_VDO1_MIXER_IN1_SOUT_SEL 0xf58 +#define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_IN2_SOUT_SEL 0xf5c +#define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_IN3_SOUT_SEL 0xf60 +#define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_IN4_SOUT_SEL 0xf64 +#define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_SOUT_SEL_IN 0xf68 +#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 + static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = { { DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, @@ -146,4 +196,80 @@ static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = { }, }; +static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = { + { + DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1, + MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 + }, { + DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1, + MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 + }, { + DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2, + MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 + }, { + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN1_SEL + }, { + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN2_SEL + }, { + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN3_SEL + }, { + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN4_SEL + }, { + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, + MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), + MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL + }, { + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT + }, { + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT + }, { + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT + }, { + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT + }, { + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, + MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), + MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER + }, { + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, + MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), + MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, + MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), + MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, + MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), + MT8188_MERGE4_SOUT_TO_DPI1_SEL + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, + MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), + MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, + MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0), + MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL + } +}; + #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 88209102ff3b..1b160fcc1d27 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -89,6 +89,14 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table), }; +static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = { + .clk_driver = "clk-mt8188-vdo1", + .routes = mmsys_mt8188_vdo1_routing_table, + .num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table), + .num_resets = 96, + .vsync_len = 1, +}; + static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .clk_driver = "clk-mt8192-mm", .routes = mmsys_mt8192_routing_table, @@ -169,6 +177,10 @@ void mtk_mmsys_ddp_connect(struct device *dev, if (cur == routes[i].from_comp && next == routes[i].to_comp) mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, routes[i].val, NULL); + + if (mmsys->data->vsync_len) + mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, GENMASK(31, 0), + mmsys->data->vsync_len, NULL); } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); @@ -429,6 +441,7 @@ static const struct of_device_id of_match_mtk_mmsys[] = { { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data }, { .compatible = "mediatek,mt8186-mmsys", .data = &mt8186_mmsys_driver_data }, { .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data }, + { .compatible = "mediatek,mt8188-vdosys1", .data = &mt8188_vdosys1_driver_data }, { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data }, /* "mediatek,mt8195-mmsys" compatible is deprecated */ { .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data }, diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 6725403d2e3a..9d8507f98b7a 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -86,6 +86,34 @@ struct mtk_mmsys_routes { u32 val; }; +/** + * struct mtk_mmsys_driver_data - Settings of the mmsys + * @clk_driver: Clock driver name that the mmsys is using + * (defined in drivers/clk/mediatek/clk-*.c). + * @routes: Routing table of the mmsys. + * It provides mux settings from one module to another. + * @num_routes: Array size of the routes. + * @sw0_rst_offset: Register offset for the reset control. + * @num_resets: Number of reset bits that are defined + * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe) + * or VDOSYS (Video). Only VDOSYS needs to be added to drm driver. + * @vsync_len: VSYNC length of the MIXER. + * VSYNC is usually triggered by the connector, so its length is a + * fixed value when the frame rate is decided, but ETHDR and + * MIXER generate their own VSYNC due to hardware design, therefore + * MIXER has to sync with ETHDR by adjusting VSYNC length. + * On MT8195, there is no such setting so we use the gap between + * falling edge and rising edge of SOF (Start of Frame) signal to + * do the job, but since MT8188, VSYNC_LEN setting is introduced to + * solve the problem and is given 0x40 (ticks) as the default value. + * Please notice that this value has to be set to 1 (minimum) if + * ETHDR is bypassed, otherwise MIXER could wait too long and causing + * underflow. + * + * Each MMSYS (multi-media system) may have different settings, they may use + * different clock sources, mux settings, reset control ...etc., and these + * differences are all stored here. + */ struct mtk_mmsys_driver_data { const char *clk_driver; const struct mtk_mmsys_routes *routes; @@ -93,6 +121,7 @@ struct mtk_mmsys_driver_data { const u16 sw0_rst_offset; const u32 num_resets; const bool is_vppsys; + const u8 vsync_len; }; /* diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 9d9f5ae578ac..e76722289175 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -133,6 +133,22 @@ #define MT8188_MUTEX_MOD_DISP_POSTMASK0 24 #define MT8188_MUTEX_MOD2_DISP_PWM0 33 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 0 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 1 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 2 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 3 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 4 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 23 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 24 +#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER 30 +#define MT8188_MUTEX_MOD_DISP1_DP_INTF1 39 + #define MT8195_MUTEX_MOD_DISP_OVL0 0 #define MT8195_MUTEX_MOD_DISP_WDMA0 1 #define MT8195_MUTEX_MOD_DISP_RDMA0 2 @@ -264,6 +280,7 @@ #define MT8183_MUTEX_SOF_DPI0 2 #define MT8188_MUTEX_SOF_DSI0 1 #define MT8188_MUTEX_SOF_DP_INTF0 3 +#define MT8188_MUTEX_SOF_DP_INTF1 4 #define MT8195_MUTEX_SOF_DSI0 1 #define MT8195_MUTEX_SOF_DSI1 2 #define MT8195_MUTEX_SOF_DP_INTF0 3 @@ -275,6 +292,7 @@ #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) #define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7) #define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7) +#define MT8188_MUTEX_EOF_DP_INTF1 (MT8188_MUTEX_SOF_DP_INTF1 << 7) #define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7) #define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7) #define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7) @@ -445,6 +463,21 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DSI0] = MT8188_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_PWM0] = MT8188_MUTEX_MOD2_DISP_PWM0, [DDP_COMPONENT_DP_INTF0] = MT8188_MUTEX_MOD_DISP_DP_INTF0, + [DDP_COMPONENT_DP_INTF1] = MT8188_MUTEX_MOD_DISP1_DP_INTF1, + [DDP_COMPONENT_ETHDR_MIXER] = MT8188_MUTEX_MOD_DISP1_DISP_MIXER, + [DDP_COMPONENT_MDP_RDMA0] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA0, + [DDP_COMPONENT_MDP_RDMA1] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA1, + [DDP_COMPONENT_MDP_RDMA2] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA2, + [DDP_COMPONENT_MDP_RDMA3] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA3, + [DDP_COMPONENT_MDP_RDMA4] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA4, + [DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5, + [DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6, + [DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7, + [DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0, + [DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1, + [DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2, + [DDP_COMPONENT_MERGE4] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE3, + [DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4, }; static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { @@ -605,6 +638,8 @@ static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SOF_MAX] = { MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0, [MUTEX_SOF_DP_INTF0] = MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0, + [MUTEX_SOF_DP_INTF1] = + MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1, }; static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = { From patchwork Thu Dec 14 05:58:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Sung X-Patchwork-Id: 754643 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="RWJ3rF9p" Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2EE01BEF; Wed, 13 Dec 2023 21:58:58 -0800 (PST) X-UUID: da6aa2f29a4511eeba30773df0976c77-20231214 DKIM-Signature: v=1; a=rsa-sha256; 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Thu, 14 Dec 2023 13:58:50 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 14 Dec 2023 13:58:49 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 14 Dec 2023 13:58:49 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , "CK Hu" CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Moudy Ho , Hsiao Chien Sung , Nathan Lu , "Nancy . Lin" , "Roy-CW . Yeh" , "Jason-JH . Lin" , xinlei lee , , , , , Subject: [PATCH v12 08/23] soc: mediatek: Support MT8188 VDOSYS1 Padding in mtk-mmsys Date: Thu, 14 Dec 2023 13:58:32 +0800 Message-ID: <20231214055847.4936-9-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231214055847.4936-1-shawn.sung@mediatek.com> References: <20231214055847.4936-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--2.314700-8.000000 X-TMASE-MatchedRID: GIpmbigRs3Zys0UAwvp+/GNW0DAjL5p+Wot5Z16+u76SO6So6QGgyhFx R5JQAS6O09NQNrxIpFYBtjkcfRMmqZH0YXYnbGozFEUknJ/kEl7dB/CxWTRRu+rAZ8KTspSz4pO wtvaNyGU21IzBwIEUQNBciwMhYJ9AFXiaNYdPFkDhRl/VmKpeVFSGqGyCth7tWKn7RAyIwlr1gk Y4kFyM/aNKra/RjMJFF0aD5ljt43pMcHZD6gqu7wxMjfifIXfowkvVoA11Twp+3BndfXUhXQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--2.314700-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 2BCD55A10750F069E6634C8F23433FA4C81A3D9A8E23E4FEA2E5324D568DF8B22000:8 X-MTK: N - Add Padding components - Add Mutex module definitions for Padding Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mtk-mutex.c | 16 ++++++++++++++++ include/linux/soc/mediatek/mtk-mmsys.h | 8 ++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index e76722289175..73c256d3950b 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -141,6 +141,14 @@ #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7 +#define MT8188_MUTEX_MOD_DISP1_PADDING0 8 +#define MT8188_MUTEX_MOD_DISP1_PADDING1 9 +#define MT8188_MUTEX_MOD_DISP1_PADDING2 10 +#define MT8188_MUTEX_MOD_DISP1_PADDING3 11 +#define MT8188_MUTEX_MOD_DISP1_PADDING4 12 +#define MT8188_MUTEX_MOD_DISP1_PADDING5 13 +#define MT8188_MUTEX_MOD_DISP1_PADDING6 14 +#define MT8188_MUTEX_MOD_DISP1_PADDING7 15 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22 @@ -473,6 +481,14 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_MDP_RDMA5] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA5, [DDP_COMPONENT_MDP_RDMA6] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA6, [DDP_COMPONENT_MDP_RDMA7] = MT8188_MUTEX_MOD_DISP1_MDP_RDMA7, + [DDP_COMPONENT_PADDING0] = MT8188_MUTEX_MOD_DISP1_PADDING0, + [DDP_COMPONENT_PADDING1] = MT8188_MUTEX_MOD_DISP1_PADDING1, + [DDP_COMPONENT_PADDING2] = MT8188_MUTEX_MOD_DISP1_PADDING2, + [DDP_COMPONENT_PADDING3] = MT8188_MUTEX_MOD_DISP1_PADDING3, + [DDP_COMPONENT_PADDING4] = MT8188_MUTEX_MOD_DISP1_PADDING4, + [DDP_COMPONENT_PADDING5] = MT8188_MUTEX_MOD_DISP1_PADDING5, + [DDP_COMPONENT_PADDING6] = MT8188_MUTEX_MOD_DISP1_PADDING6, + [DDP_COMPONENT_PADDING7] = MT8188_MUTEX_MOD_DISP1_PADDING7, [DDP_COMPONENT_MERGE1] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE0, [DDP_COMPONENT_MERGE2] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE1, [DDP_COMPONENT_MERGE3] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE2, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 2475ef914746..4885b065b849 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -62,6 +62,14 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_OVL1, + DDP_COMPONENT_PADDING0, + DDP_COMPONENT_PADDING1, + DDP_COMPONENT_PADDING2, + DDP_COMPONENT_PADDING3, + DDP_COMPONENT_PADDING4, + DDP_COMPONENT_PADDING5, + DDP_COMPONENT_PADDING6, + DDP_COMPONENT_PADDING7, DDP_COMPONENT_POSTMASK0, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, From patchwork Thu Dec 14 05:58:34 2023 Content-Type: text/plain; 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Lin" , "Roy-CW . Yeh" , "Jason-JH . Lin" , xinlei lee , , , , , Subject: [PATCH v12 10/23] soc: mediatek: Add MT8188 VDOSYS reset bit map Date: Thu, 14 Dec 2023 13:58:34 +0800 Message-ID: <20231214055847.4936-11-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231214055847.4936-1-shawn.sung@mediatek.com> References: <20231214055847.4936-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Add MT8188 reset bit map for VDOSYS0 and VDOSYS1. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mt8188-mmsys.h | 84 +++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 7 ++- 2 files changed, 90 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8188-mmsys.h index a9490c3c4256..6bebf1a69fc0 100644 --- a/drivers/soc/mediatek/mt8188-mmsys.h +++ b/drivers/soc/mediatek/mt8188-mmsys.h @@ -3,6 +3,10 @@ #ifndef __SOC_MEDIATEK_MT8188_MMSYS_H #define __SOC_MEDIATEK_MT8188_MMSYS_H +#include +#include + +#define MT8188_VDO0_SW0_RST_B 0x190 #define MT8188_VDO0_OVL_MOUT_EN 0xf14 #define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) #define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) @@ -67,6 +71,7 @@ #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18) #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19) +#define MT8188_VDO1_SW0_RST_B 0x1d0 #define MT8188_VDO1_HDR_TOP_CFG 0xd00 #define MT8188_VDO1_MIXER_IN1_ALPHA 0xd30 #define MT8188_VDO1_MIXER_IN1_PAD 0xd40 @@ -117,6 +122,85 @@ #define MT8188_VDO1_MIXER_SOUT_SEL_IN 0xf68 #define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 +static const u8 mmsys_mt8188_vdo0_rst_tb[] = { + [MT8188_VDO0_RST_DISP_OVL0] = MMSYS_RST_NR(0, 0), + [MT8188_VDO0_RST_FAKE_ENG0] = MMSYS_RST_NR(0, 2), + [MT8188_VDO0_RST_DISP_CCORR0] = MMSYS_RST_NR(0, 4), + [MT8188_VDO0_RST_DISP_MUTEX0] = MMSYS_RST_NR(0, 6), + [MT8188_VDO0_RST_DISP_GAMMA0] = MMSYS_RST_NR(0, 8), + [MT8188_VDO0_RST_DISP_DITHER0] = MMSYS_RST_NR(0, 10), + [MT8188_VDO0_RST_DISP_WDMA0] = MMSYS_RST_NR(0, 17), + [MT8188_VDO0_RST_DISP_RDMA0] = MMSYS_RST_NR(0, 19), + [MT8188_VDO0_RST_DSI0] = MMSYS_RST_NR(0, 21), + [MT8188_VDO0_RST_DSI1] = MMSYS_RST_NR(0, 22), + [MT8188_VDO0_RST_DSC_WRAP0] = MMSYS_RST_NR(0, 23), + [MT8188_VDO0_RST_VPP_MERGE0] = MMSYS_RST_NR(0, 24), + [MT8188_VDO0_RST_DP_INTF0] = MMSYS_RST_NR(0, 25), + [MT8188_VDO0_RST_DISP_AAL0] = MMSYS_RST_NR(0, 26), + [MT8188_VDO0_RST_INLINEROT0] = MMSYS_RST_NR(0, 27), + [MT8188_VDO0_RST_APB_BUS] = MMSYS_RST_NR(0, 28), + [MT8188_VDO0_RST_DISP_COLOR0] = MMSYS_RST_NR(0, 29), + [MT8188_VDO0_RST_MDP_WROT0] = MMSYS_RST_NR(0, 30), + [MT8188_VDO0_RST_DISP_RSZ0] = MMSYS_RST_NR(0, 31), +}; + +static const u8 mmsys_mt8188_vdo1_rst_tb[] = { + [MT8188_VDO1_RST_SMI_LARB2] = MMSYS_RST_NR(0, 0), + [MT8188_VDO1_RST_SMI_LARB3] = MMSYS_RST_NR(0, 1), + [MT8188_VDO1_RST_GALS] = MMSYS_RST_NR(0, 2), + [MT8188_VDO1_RST_FAKE_ENG0] = MMSYS_RST_NR(0, 3), + [MT8188_VDO1_RST_FAKE_ENG1] = MMSYS_RST_NR(0, 4), + [MT8188_VDO1_RST_MDP_RDMA0] = MMSYS_RST_NR(0, 5), + [MT8188_VDO1_RST_MDP_RDMA1] = MMSYS_RST_NR(0, 6), + [MT8188_VDO1_RST_MDP_RDMA2] = MMSYS_RST_NR(0, 7), + [MT8188_VDO1_RST_MDP_RDMA3] = MMSYS_RST_NR(0, 8), + [MT8188_VDO1_RST_VPP_MERGE0] = MMSYS_RST_NR(0, 9), + [MT8188_VDO1_RST_VPP_MERGE1] = MMSYS_RST_NR(0, 10), + [MT8188_VDO1_RST_VPP_MERGE2] = MMSYS_RST_NR(0, 11), + [MT8188_VDO1_RST_VPP_MERGE3] = MMSYS_RST_NR(1, 0), + [MT8188_VDO1_RST_VPP_MERGE4] = MMSYS_RST_NR(1, 1), + [MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 2), + [MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 3), + [MT8188_VDO1_RST_DISP_MUTEX] = MMSYS_RST_NR(1, 4), + [MT8188_VDO1_RST_MDP_RDMA4] = MMSYS_RST_NR(1, 5), + [MT8188_VDO1_RST_MDP_RDMA5] = MMSYS_RST_NR(1, 6), + [MT8188_VDO1_RST_MDP_RDMA6] = MMSYS_RST_NR(1, 7), + [MT8188_VDO1_RST_MDP_RDMA7] = MMSYS_RST_NR(1, 8), + [MT8188_VDO1_RST_DP_INTF1_MMCK] = MMSYS_RST_NR(1, 9), + [MT8188_VDO1_RST_DPI0_MM_CK] = MMSYS_RST_NR(1, 10), + [MT8188_VDO1_RST_DPI1_MM_CK] = MMSYS_RST_NR(1, 11), + [MT8188_VDO1_RST_MERGE0_DL_ASYNC] = MMSYS_RST_NR(1, 13), + [MT8188_VDO1_RST_MERGE1_DL_ASYNC] = MMSYS_RST_NR(1, 14), + [MT8188_VDO1_RST_MERGE2_DL_ASYNC] = MMSYS_RST_NR(1, 15), + [MT8188_VDO1_RST_MERGE3_DL_ASYNC] = MMSYS_RST_NR(1, 16), + [MT8188_VDO1_RST_MERGE4_DL_ASYNC] = MMSYS_RST_NR(1, 17), + [MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 18), + [MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 19), + [MT8188_VDO1_RST_PADDING0] = MMSYS_RST_NR(1, 20), + [MT8188_VDO1_RST_PADDING1] = MMSYS_RST_NR(1, 21), + [MT8188_VDO1_RST_PADDING2] = MMSYS_RST_NR(1, 22), + [MT8188_VDO1_RST_PADDING3] = MMSYS_RST_NR(1, 23), + [MT8188_VDO1_RST_PADDING4] = MMSYS_RST_NR(1, 24), + [MT8188_VDO1_RST_PADDING5] = MMSYS_RST_NR(1, 25), + [MT8188_VDO1_RST_PADDING6] = MMSYS_RST_NR(1, 26), + [MT8188_VDO1_RST_PADDING7] = MMSYS_RST_NR(1, 27), + [MT8188_VDO1_RST_DISP_RSZ0] = MMSYS_RST_NR(1, 28), + [MT8188_VDO1_RST_DISP_RSZ1] = MMSYS_RST_NR(1, 29), + [MT8188_VDO1_RST_DISP_RSZ2] = MMSYS_RST_NR(1, 30), + [MT8188_VDO1_RST_DISP_RSZ3] = MMSYS_RST_NR(1, 31), + [MT8188_VDO1_RST_HDR_VDO_FE0] = MMSYS_RST_NR(2, 0), + [MT8188_VDO1_RST_HDR_GFX_FE0] = MMSYS_RST_NR(2, 1), + [MT8188_VDO1_RST_HDR_VDO_BE] = MMSYS_RST_NR(2, 2), + [MT8188_VDO1_RST_HDR_VDO_FE1] = MMSYS_RST_NR(2, 16), + [MT8188_VDO1_RST_HDR_GFX_FE1] = MMSYS_RST_NR(2, 17), + [MT8188_VDO1_RST_DISP_MIXER] = MMSYS_RST_NR(2, 18), + [MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC] = MMSYS_RST_NR(2, 19), + [MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC] = MMSYS_RST_NR(2, 20), + [MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC] = MMSYS_RST_NR(2, 21), + [MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC] = MMSYS_RST_NR(2, 22), + [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] = MMSYS_RST_NR(2, 23), +}; + static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = { { DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index fee958d0b8a6..08a1c22de00b 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -87,13 +87,18 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { .clk_driver = "clk-mt8188-vdo0", .routes = mmsys_mt8188_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table), + .sw0_rst_offset = MT8188_VDO0_SW0_RST_B, + .rst_tb = mmsys_mt8188_vdo0_rst_tb, + .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo0_rst_tb), }; static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data = { .clk_driver = "clk-mt8188-vdo1", .routes = mmsys_mt8188_vdo1_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table), - .num_resets = 96, + .sw0_rst_offset = MT8188_VDO1_SW0_RST_B, + .rst_tb = mmsys_mt8188_vdo1_rst_tb, + .num_resets = ARRAY_SIZE(mmsys_mt8188_vdo1_rst_tb), .vsync_len = 1, }; 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Thu, 14 Dec 2023 13:58:51 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 14 Dec 2023 13:58:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 14 Dec 2023 13:58:50 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , "CK Hu" CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Moudy Ho , Hsiao Chien Sung , Nathan Lu , "Nancy . Lin" , "Roy-CW . Yeh" , "Jason-JH . Lin" , xinlei lee , , , , , Subject: [PATCH v12 12/23] drm/mediatek: Add component ID to component match structure Date: Thu, 14 Dec 2023 13:58:36 +0800 Message-ID: <20231214055847.4936-13-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231214055847.4936-1-shawn.sung@mediatek.com> References: <20231214055847.4936-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--12.137500-8.000000 X-TMASE-MatchedRID: +0gY6okUAw/wi+JtrEQDF72xWbKjBfWPT5++FIORChDJYIv7y0tu9rsI asnPqvyQZClGcL9tHydiFleaZxjZFswdQieqpnTaFYJUGv4DL3zljSRvSGpq3PYST2HmKKfiiDY Xi2hIM/kth7GMj8XazrtoEorx7rLzYlldA0POS1JDiyuN5FvFNqp2m4S4J4ZoCqIJhrrDy29DJi enRpkiMjalcgn9jL/LojCvEB8eY1zD6egsHKBhOBIRh9wkXSlFfS0Ip2eEHnz3IzXlXlpamPoLR 4+zsDTtw1tMVU7ONTz62tQ01i0/pTZ3KK++KXBqCB5aR9420KRyT8YBnoJBig== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--12.137500-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: F055E5BE60AA0F6960934B5382F2E91C52CD838192822F0C0934863AC85AE68B2000:8 X-MTK: N Add component ID to component match structure so we can configure them with a for-loop. The main reason we do such code refactoring is that there is a new hardware component called "Padding" since MT8188, while MT8195 doesn't have this module, we can't use the original logic to manage the components. While MT8195 does not define Padding in the device tree, the corresponding components will be NULL and being skipped by the functions. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 69 ++++++++----------- 1 file changed, 30 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c index 114eded8177e..9f569d0f52b3 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -52,6 +52,7 @@ enum mtk_ovl_adaptor_comp_id { struct ovl_adaptor_comp_match { enum mtk_ovl_adaptor_comp_type type; + enum mtk_ddp_comp_id comp_id; int alias_id; }; @@ -68,19 +69,19 @@ static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = { }; static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = { - [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 }, - [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 }, - [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 }, - [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 3 }, - [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 4 }, - [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 5 }, - [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 6 }, - [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, 7 }, - [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 }, - [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 }, - [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 }, - [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 }, - [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 }, + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA0, 0 }, + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA1, 1 }, + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA2, 2 }, + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA3, 3 }, + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA4, 4 }, + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA5, 5 }, + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA6, 6 }, + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA7, 7 }, + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1 }, + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2 }, + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3 }, + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4 }, + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0 }, }; void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, @@ -314,36 +315,26 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device *dev) void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex) { - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA3); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA4); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA5); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA6); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA7); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE1); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); + int i; + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev); + + for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) { + if (!ovl_adaptor->ovl_adaptor_comp[i]) + continue; + mtk_mutex_add_comp(mutex, comp_matches[i].comp_id); + } } void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex) { - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA3); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA4); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA5); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA6); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA7); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE1); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); + int i; + struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev); + + for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) { + if (!ovl_adaptor->ovl_adaptor_comp[i]) + continue; + mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id); + } } void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsigned int next) From patchwork Thu Dec 14 05:58:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Sung X-Patchwork-Id: 754636 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="af1/zlIL" Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9261418B; Wed, 13 Dec 2023 21:59:01 -0800 (PST) X-UUID: db22954c9a4511eea5db2bebc7c28f94-20231214 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Twmmag5MwvkgiILdQ8ML6Ne9q0reVvpGkR+7v4r1CTw=; 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Thu, 14 Dec 2023 13:58:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 14 Dec 2023 13:58:50 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Moudy Ho , Hsiao Chien Sung , Nathan Lu , "Nancy . Lin" , "Roy-CW . Yeh" , "Jason-JH . Lin" , xinlei lee , , , , , Subject: [PATCH v12 13/23] drm/mediatek: Manage component's clock with function pointers Date: Thu, 14 Dec 2023 13:58:37 +0800 Message-ID: <20231214055847.4936-14-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231214055847.4936-1-shawn.sung@mediatek.com> References: <20231214055847.4936-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N By registering component related functions to the pointers, we can easily manage them within a for-loop and simplify the logic of clock control significantly. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 89 +++++++++---------- 1 file changed, 43 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c index 9f569d0f52b3..a815dc8e2110 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -54,6 +54,7 @@ struct ovl_adaptor_comp_match { enum mtk_ovl_adaptor_comp_type type; enum mtk_ddp_comp_id comp_id; int alias_id; + const struct mtk_ddp_comp_funcs *funcs; }; struct mtk_disp_ovl_adaptor { @@ -68,20 +69,35 @@ static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = { [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr", }; +static const struct mtk_ddp_comp_funcs ethdr = { + .clk_enable = mtk_ethdr_clk_enable, + .clk_disable = mtk_ethdr_clk_disable, +}; + +static const struct mtk_ddp_comp_funcs merge = { + .clk_enable = mtk_merge_clk_enable, + .clk_disable = mtk_merge_clk_disable, +}; + +static const struct mtk_ddp_comp_funcs rdma = { + .clk_enable = mtk_mdp_rdma_clk_enable, + .clk_disable = mtk_mdp_rdma_clk_disable, +}; + static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = { - [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA0, 0 }, - [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA1, 1 }, - [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA2, 2 }, - [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA3, 3 }, - [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA4, 4 }, - [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA5, 5 }, - [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA6, 6 }, - [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA7, 7 }, - [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1 }, - [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2 }, - [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3 }, - [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4 }, - [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0 }, + [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA0, 0, &rdma }, + [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA1, 1, &rdma }, + [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA2, 2, &rdma }, + [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA3, 3, &rdma }, + [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA4, 4, &rdma }, + [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA5, 5, &rdma }, + [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA6, 6, &rdma }, + [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA7, 7, &rdma }, + [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1, &merge }, + [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2, &merge }, + [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3, &merge }, + [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4, &merge }, + [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0, ðdr }, }; void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, @@ -197,40 +213,25 @@ int mtk_ovl_adaptor_clk_enable(struct device *dev) ret = pm_runtime_get_sync(comp); if (ret < 0) { dev_err(dev, "Failed to enable power domain %d, err %d\n", i, ret); - goto pwr_err; + goto error; } } for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) { comp = ovl_adaptor->ovl_adaptor_comp[i]; - - if (i < OVL_ADAPTOR_MERGE0) - ret = mtk_mdp_rdma_clk_enable(comp); - else if (i < OVL_ADAPTOR_ETHDR0) - ret = mtk_merge_clk_enable(comp); - else - ret = mtk_ethdr_clk_enable(comp); + if (!comp || !comp_matches[i].funcs->clk_enable) + continue; + ret = comp_matches[i].funcs->clk_enable(comp); if (ret) { dev_err(dev, "Failed to enable clock %d, err %d\n", i, ret); - goto clk_err; + while (--i >= 0) + comp_matches[i].funcs->clk_disable(comp); + i = OVL_ADAPTOR_MERGE0; + goto error; } } - - return ret; - -clk_err: - while (--i >= 0) { - comp = ovl_adaptor->ovl_adaptor_comp[i]; - if (i < OVL_ADAPTOR_MERGE0) - mtk_mdp_rdma_clk_disable(comp); - else if (i < OVL_ADAPTOR_ETHDR0) - mtk_merge_clk_disable(comp); - else - mtk_ethdr_clk_disable(comp); - } - i = OVL_ADAPTOR_MERGE0; - -pwr_err: + return 0; +error: while (--i >= 0) pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]); @@ -245,15 +246,11 @@ void mtk_ovl_adaptor_clk_disable(struct device *dev) for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) { comp = ovl_adaptor->ovl_adaptor_comp[i]; - - if (i < OVL_ADAPTOR_MERGE0) { - mtk_mdp_rdma_clk_disable(comp); + if (!comp || !comp_matches[i].funcs->clk_disable) + continue; + comp_matches[i].funcs->clk_disable(comp); + if (i < OVL_ADAPTOR_MERGE0) pm_runtime_put(comp); - } else if (i < OVL_ADAPTOR_ETHDR0) { - mtk_merge_clk_disable(comp); - } else { - mtk_ethdr_clk_disable(comp); - } } } From patchwork Thu Dec 14 05:58:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Sung X-Patchwork-Id: 754639 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Qo8AmcdT" Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36D6218C; 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Thu, 14 Dec 2023 13:58:53 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 14 Dec 2023 13:58:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 14 Dec 2023 13:58:51 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Moudy Ho , Hsiao Chien Sung , Nathan Lu , "Nancy . Lin" , "Roy-CW . Yeh" , "Jason-JH . Lin" , xinlei lee , , , , , Subject: [PATCH v12 20/23] drm/mediatek: Return error if MDP RDMA failed to enable the clock Date: Thu, 14 Dec 2023 13:58:44 +0800 Message-ID: <20231214055847.4936-21-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231214055847.4936-1-shawn.sung@mediatek.com> References: <20231214055847.4936-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Return the result of clk_prepare_enable() instead of always returns 0. Fixes: f8946e2b6bb2 ("drm/mediatek: Add display MDP RDMA support for MT8195") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c index dc7c9e991990..ee9ce9b6d078 100644 --- a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c @@ -262,8 +262,7 @@ int mtk_mdp_rdma_clk_enable(struct device *dev) { struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev); - clk_prepare_enable(rdma->clk); - return 0; + return clk_prepare_enable(rdma->clk); } void mtk_mdp_rdma_clk_disable(struct device *dev) From patchwork Thu Dec 14 05:58:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Sung X-Patchwork-Id: 754633 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="KKzr740H" Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14B7410A; Wed, 13 Dec 2023 21:59:06 -0800 (PST) X-UUID: dc2ffbdc9a4511eeba30773df0976c77-20231214 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=51HJOr0dS/v7F5/qreWZJjS+j7SqqpS9LnYC/XsgvTU=; b=KKzr740HrfaIZXy2KJYb4YNfw07Yx6fM9H5mRg2R4mz5r2hUY+lSd16DplOzvtcsVkSqj7J/hzSP1fAf4wJoGXcYq6AJovEu0pUb3BivMD0GKnhiSvnnaku3IYjOWXHYQfsU7qxQvP7mn7u7cJStSflr/hHaTLbM2pCNcf88fb4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35, REQID:c0145a90-8267-451c-b6cf-9f10bc5f4bad, IP:0, U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:5d391d7, CLOUDID:a55fc673-1bd3-4f48-b671-ada88705968c, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: dc2ffbdc9a4511eeba30773df0976c77-20231214 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1261397788; Thu, 14 Dec 2023 13:58:53 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 14 Dec 2023 13:58:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 14 Dec 2023 13:58:51 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , CK Hu CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Moudy Ho , Hsiao Chien Sung , Nathan Lu , "Nancy . Lin" , "Roy-CW . Yeh" , "Jason-JH . Lin" , xinlei lee , , , , , Subject: [PATCH v12 21/23] drm/mediatek: Remove the redundant driver data for DPI Date: Thu, 14 Dec 2023 13:58:45 +0800 Message-ID: <20231214055847.4936-22-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231214055847.4936-1-shawn.sung@mediatek.com> References: <20231214055847.4936-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N DPI input is in 1T2P mode on both MT8195 and MT8188. Remove the redundant driver data to align the settings, or the screen will glitch. Fixes: 2847cd7e6403 ("drm/mediatek: Add mt8188 dpi compatibles and platform data") Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_dpi.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 4e3d9f7b4d8c..beb7d9d08e97 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -966,20 +966,6 @@ static const struct mtk_dpi_conf mt8186_conf = { .csc_enable_bit = CSC_ENABLE, }; -static const struct mtk_dpi_conf mt8188_dpintf_conf = { - .cal_factor = mt8195_dpintf_calculate_factor, - .max_clock_khz = 600000, - .output_fmts = mt8195_output_fmts, - .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts), - .pixels_per_iter = 4, - .input_2pixel = false, - .dimension_mask = DPINTF_HPW_MASK, - .hvsize_mask = DPINTF_HSIZE_MASK, - .channel_swap_shift = DPINTF_CH_SWAP, - .yuv422_en_bit = DPINTF_YUV422_EN, - .csc_enable_bit = DPINTF_CSC_ENABLE, -}; - static const struct mtk_dpi_conf mt8192_conf = { .cal_factor = mt8183_calculate_factor, .reg_h_fre_con = 0xe0, @@ -1103,7 +1089,7 @@ static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt8173-dpi", .data = &mt8173_conf }, { .compatible = "mediatek,mt8183-dpi", .data = &mt8183_conf }, { .compatible = "mediatek,mt8186-dpi", .data = &mt8186_conf }, - { .compatible = "mediatek,mt8188-dp-intf", .data = &mt8188_dpintf_conf }, + { .compatible = "mediatek,mt8188-dp-intf", .data = &mt8195_dpintf_conf }, { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf }, { .compatible = "mediatek,mt8195-dp-intf", .data = &mt8195_dpintf_conf }, { /* sentinel */ }, From patchwork Thu Dec 14 05:58:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Sung X-Patchwork-Id: 754638 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="tXIMVimV" Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 980CB197; Wed, 13 Dec 2023 21:59:03 -0800 (PST) X-UUID: dc6ab9ac9a4511eea5db2bebc7c28f94-20231214 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=HHX1jEUoL6Mf8DrcHwvOl88aw89wvX7S7JVecHhId2M=; b=tXIMVimVzERdSn6TyF+pyo8kLz14HGDcqILW/DFJteUYpM6c/dAkFX/cfzuwp7YCA0Y8isbSM/OY5dFSv/RP+h9JQN1DxwWpnLq2m6GYpwxjyyvxZ7O8d+OkQyLfqUsns35OFtiHlxweFIL5wEXxs5+RqrXihQOz80n6DgdOey8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35, REQID:d76e4737-2114-43da-839a-3c60d8a0b3c3, IP:0, U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:5d391d7, CLOUDID:a23c29bd-2ac7-4da2-9f94-677a477649d9, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: dc6ab9ac9a4511eea5db2bebc7c28f94-20231214 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 593049922; Thu, 14 Dec 2023 13:58:53 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 14 Dec 2023 13:58:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 14 Dec 2023 13:58:52 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , "CK Hu" CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Moudy Ho , Hsiao Chien Sung , Nathan Lu , "Nancy . Lin" , "Roy-CW . Yeh" , "Jason-JH . Lin" , xinlei lee , , , , , Subject: [PATCH v12 23/23] drm/mediatek: Support MT8188 VDOSYS1 in display driver Date: Thu, 14 Dec 2023 13:58:47 +0800 Message-ID: <20231214055847.4936-24-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231214055847.4936-1-shawn.sung@mediatek.com> References: <20231214055847.4936-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--6.544100-8.000000 X-TMASE-MatchedRID: k6EjByr1NNCA1UdczcLx7jvfsoCuAcP+uLwbhNl9B5VcKZwALwMGs43y qnCHUnfZLYexjI/F2s67aBKK8e6y8yUtdpGicV4RKaMQ6tw7oDJMkOX0UoduuQqiCYa6w8tv5pf 3ZiBJgsHc0NDBaoYShZjXlVZ6P0cvj2hRzH1UwuAURSScn+QSXt0H8LFZNFG7bkV4e2xSge4sw3 GEmIriBSUhMPBH5sX4M517nGGNRDAnSTeZe+bs5kuFvzEYSdV+ X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--6.544100-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 9CD57752886B2D27EDB266D57A02EC8B0E9144DB819A1D626578D8FF6ECF02B42000:8 X-MTK: N - The mmsys_dev_num in MT8188 VDOSYS0 was set to 1 since VDOSYS1 was not available before. Increase it to support VDOSYS1 in display driver. - Add compatible name for MT8188 VDOSYS1 (shares the same driver data with MT8195 VDOSYS1) Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index f7504d1edc62..8cbbf55a6454 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -293,7 +293,7 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main), .conn_routes = mt8188_mtk_ddp_main_routes, .num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes), - .mmsys_dev_num = 1, + .mmsys_dev_num = 2, }; static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { @@ -334,6 +334,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt8186_mmsys_driver_data}, { .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data}, + { .compatible = "mediatek,mt8188-vdosys1", + .data = &mt8195_vdosys1_driver_data}, { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data}, { .compatible = "mediatek,mt8195-mmsys",