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[178.235.179.137]) by smtp.gmail.com with ESMTPSA id ts7-20020a170907c5c700b00a1dd58874b8sm14260693ejc.119.2023.12.18.08.02.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 08:02:17 -0800 (PST) From: Konrad Dybcio Date: Mon, 18 Dec 2023 17:02:02 +0100 Subject: [PATCH 01/12] interconnect: qcom: sm8550: Remove bogus per-RSC BCMs and nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231218-topic-8550_fixes-v1-1-ce1272d77540@linaro.org> References: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> In-Reply-To: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> To: Bjorn Andersson , Georgi Djakov , Abel Vesa , Michael Turquette , Stephen Boyd , Taniya Das , Jagadeesh Kona , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sai Prakash Ranjan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1702915332; l=31363; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=oof9143qzZLAgiksoPESQ2uwG+Rp/r2cv+dzhypmSIo=; b=UXrhyJZfhlrZYbJqjztI/iSm67qEyz0rqXbNkzvsdFs7SAJY0Z8eDU4iZTtVPby7d532Yu60f qvYRV2kKZ9TCkRQ2trHgINrMsIPWpgPrq2jETSjqoHvXMRY6u2DFBJE X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The downstream kernel has infrastructure for passing votes from different interconnect nodes onto different RPMh RSCs. This neither implemented, not is going to be implemented upstream (in favor of a different solution using ICC tags through the same node). Unfortunately, as it happens, meaningless (in the upstream context) parts of the vendor driver were copied, ending up causing havoc - since all "per-RSC" (in quotes because they all point to the main APPS one) BCMs defined within the driver overwrite the value in RPMh on every aggregation. To both avoid keeping bogus code around and possibly introducing impossible-to-track-down bugs (busses shutting down for no reason), get rid of the duplicated BCMs and their associated ICC nodes. Fixes: e6f0d6a30f73 ("interconnect: qcom: Add SM8550 interconnect provider driver") Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8550.c | 574 ------------------------------------- drivers/interconnect/qcom/sm8550.h | 284 ++++++++---------- 2 files changed, 122 insertions(+), 736 deletions(-) diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c index 629faa4c9aae..abc52ad3d1f2 100644 --- a/drivers/interconnect/qcom/sm8550.c +++ b/drivers/interconnect/qcom/sm8550.c @@ -524,231 +524,6 @@ static struct qcom_icc_node xm_gic = { .links = { SM8550_SLAVE_SNOC_GEM_NOC_GC }, }; -static struct qcom_icc_node qnm_mnoc_hf_disp = { - .name = "qnm_mnoc_hf_disp", - .id = SM8550_MASTER_MNOC_HF_MEM_NOC_DISP, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_SLAVE_LLCC_DISP }, -}; - -static struct qcom_icc_node qnm_pcie_disp = { - .name = "qnm_pcie_disp", - .id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_DISP, - .channels = 1, - .buswidth = 16, - .num_links = 1, - .links = { SM8550_SLAVE_LLCC_DISP }, -}; - -static struct qcom_icc_node llcc_mc_disp = { - .name = "llcc_mc_disp", - .id = SM8550_MASTER_LLCC_DISP, - .channels = 4, - .buswidth = 4, - .num_links = 1, - .links = { SM8550_SLAVE_EBI1_DISP }, -}; - -static struct qcom_icc_node qnm_mdp_disp = { - .name = "qnm_mdp_disp", - .id = SM8550_MASTER_MDP_DISP, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP }, -}; - -static struct qcom_icc_node qnm_mnoc_hf_cam_ife_0 = { - .name = "qnm_mnoc_hf_cam_ife_0", - .id = SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_SLAVE_LLCC_CAM_IFE_0 }, -}; - -static struct qcom_icc_node qnm_mnoc_sf_cam_ife_0 = { - .name = "qnm_mnoc_sf_cam_ife_0", - .id = SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_SLAVE_LLCC_CAM_IFE_0 }, -}; - -static struct qcom_icc_node qnm_pcie_cam_ife_0 = { - .name = "qnm_pcie_cam_ife_0", - .id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0, - .channels = 1, - .buswidth = 16, - .num_links = 1, - .links = { SM8550_SLAVE_LLCC_CAM_IFE_0 }, -}; - -static struct qcom_icc_node llcc_mc_cam_ife_0 = { - .name = "llcc_mc_cam_ife_0", - .id = SM8550_MASTER_LLCC_CAM_IFE_0, - .channels = 4, - .buswidth = 4, - .num_links = 1, - .links = { SM8550_SLAVE_EBI1_CAM_IFE_0 }, -}; - -static struct qcom_icc_node qnm_camnoc_hf_cam_ife_0 = { - .name = "qnm_camnoc_hf_cam_ife_0", - .id = SM8550_MASTER_CAMNOC_HF_CAM_IFE_0, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 }, -}; - -static struct qcom_icc_node qnm_camnoc_icp_cam_ife_0 = { - .name = "qnm_camnoc_icp_cam_ife_0", - .id = SM8550_MASTER_CAMNOC_ICP_CAM_IFE_0, - .channels = 1, - .buswidth = 8, - .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 }, -}; - -static struct qcom_icc_node qnm_camnoc_sf_cam_ife_0 = { - .name = "qnm_camnoc_sf_cam_ife_0", - .id = SM8550_MASTER_CAMNOC_SF_CAM_IFE_0, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 }, -}; - -static struct qcom_icc_node qnm_mnoc_hf_cam_ife_1 = { - .name = "qnm_mnoc_hf_cam_ife_1", - .id = SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_SLAVE_LLCC_CAM_IFE_1 }, -}; - -static struct qcom_icc_node qnm_mnoc_sf_cam_ife_1 = { - .name = "qnm_mnoc_sf_cam_ife_1", - .id = SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_SLAVE_LLCC_CAM_IFE_1 }, -}; - -static struct qcom_icc_node qnm_pcie_cam_ife_1 = { - .name = "qnm_pcie_cam_ife_1", - .id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1, - .channels = 1, - .buswidth = 16, - .num_links = 1, - .links = { SM8550_SLAVE_LLCC_CAM_IFE_1 }, -}; - -static struct qcom_icc_node llcc_mc_cam_ife_1 = { - .name = "llcc_mc_cam_ife_1", - .id = SM8550_MASTER_LLCC_CAM_IFE_1, - .channels = 4, - .buswidth = 4, - .num_links = 1, - .links = { SM8550_SLAVE_EBI1_CAM_IFE_1 }, -}; - -static struct qcom_icc_node qnm_camnoc_hf_cam_ife_1 = { - .name = "qnm_camnoc_hf_cam_ife_1", - .id = SM8550_MASTER_CAMNOC_HF_CAM_IFE_1, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 }, -}; - -static struct qcom_icc_node qnm_camnoc_icp_cam_ife_1 = { - .name = "qnm_camnoc_icp_cam_ife_1", - .id = SM8550_MASTER_CAMNOC_ICP_CAM_IFE_1, - .channels = 1, - .buswidth = 8, - .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 }, -}; - -static struct qcom_icc_node qnm_camnoc_sf_cam_ife_1 = { - .name = "qnm_camnoc_sf_cam_ife_1", - .id = SM8550_MASTER_CAMNOC_SF_CAM_IFE_1, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 }, -}; - -static struct qcom_icc_node qnm_mnoc_hf_cam_ife_2 = { - .name = "qnm_mnoc_hf_cam_ife_2", - .id = SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_SLAVE_LLCC_CAM_IFE_2 }, -}; - -static struct qcom_icc_node qnm_mnoc_sf_cam_ife_2 = { - .name = "qnm_mnoc_sf_cam_ife_2", - .id = SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_SLAVE_LLCC_CAM_IFE_2 }, -}; - -static struct qcom_icc_node qnm_pcie_cam_ife_2 = { - .name = "qnm_pcie_cam_ife_2", - .id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2, - .channels = 1, - .buswidth = 16, - .num_links = 1, - .links = { SM8550_SLAVE_LLCC_CAM_IFE_2 }, -}; - -static struct qcom_icc_node llcc_mc_cam_ife_2 = { - .name = "llcc_mc_cam_ife_2", - .id = SM8550_MASTER_LLCC_CAM_IFE_2, - .channels = 4, - .buswidth = 4, - .num_links = 1, - .links = { SM8550_SLAVE_EBI1_CAM_IFE_2 }, -}; - -static struct qcom_icc_node qnm_camnoc_hf_cam_ife_2 = { - .name = "qnm_camnoc_hf_cam_ife_2", - .id = SM8550_MASTER_CAMNOC_HF_CAM_IFE_2, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 }, -}; - -static struct qcom_icc_node qnm_camnoc_icp_cam_ife_2 = { - .name = "qnm_camnoc_icp_cam_ife_2", - .id = SM8550_MASTER_CAMNOC_ICP_CAM_IFE_2, - .channels = 1, - .buswidth = 8, - .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 }, -}; - -static struct qcom_icc_node qnm_camnoc_sf_cam_ife_2 = { - .name = "qnm_camnoc_sf_cam_ife_2", - .id = SM8550_MASTER_CAMNOC_SF_CAM_IFE_2, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 }, -}; - static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", .id = SM8550_SLAVE_A1NOC_SNOC, @@ -1342,137 +1117,6 @@ static struct qcom_icc_node qns_gemnoc_sf = { .links = { SM8550_MASTER_SNOC_SF_MEM_NOC }, }; -static struct qcom_icc_node qns_llcc_disp = { - .name = "qns_llcc_disp", - .id = SM8550_SLAVE_LLCC_DISP, - .channels = 4, - .buswidth = 16, - .num_links = 1, - .links = { SM8550_MASTER_LLCC_DISP }, -}; - -static struct qcom_icc_node ebi_disp = { - .name = "ebi_disp", - .id = SM8550_SLAVE_EBI1_DISP, - .channels = 4, - .buswidth = 4, - .num_links = 0, -}; - -static struct qcom_icc_node qns_mem_noc_hf_disp = { - .name = "qns_mem_noc_hf_disp", - .id = SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_MASTER_MNOC_HF_MEM_NOC_DISP }, -}; - -static struct qcom_icc_node qns_llcc_cam_ife_0 = { - .name = "qns_llcc_cam_ife_0", - .id = SM8550_SLAVE_LLCC_CAM_IFE_0, - .channels = 4, - .buswidth = 16, - .num_links = 1, - .links = { SM8550_MASTER_LLCC_CAM_IFE_0 }, -}; - -static struct qcom_icc_node ebi_cam_ife_0 = { - .name = "ebi_cam_ife_0", - .id = SM8550_SLAVE_EBI1_CAM_IFE_0, - .channels = 4, - .buswidth = 4, - .num_links = 0, -}; - -static struct qcom_icc_node qns_mem_noc_hf_cam_ife_0 = { - .name = "qns_mem_noc_hf_cam_ife_0", - .id = SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 }, -}; - -static struct qcom_icc_node qns_mem_noc_sf_cam_ife_0 = { - .name = "qns_mem_noc_sf_cam_ife_0", - .id = SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 }, -}; - -static struct qcom_icc_node qns_llcc_cam_ife_1 = { - .name = "qns_llcc_cam_ife_1", - .id = SM8550_SLAVE_LLCC_CAM_IFE_1, - .channels = 4, - .buswidth = 16, - .num_links = 1, - .links = { SM8550_MASTER_LLCC_CAM_IFE_1 }, -}; - -static struct qcom_icc_node ebi_cam_ife_1 = { - .name = "ebi_cam_ife_1", - .id = SM8550_SLAVE_EBI1_CAM_IFE_1, - .channels = 4, - .buswidth = 4, - .num_links = 0, -}; - -static struct qcom_icc_node qns_mem_noc_hf_cam_ife_1 = { - .name = "qns_mem_noc_hf_cam_ife_1", - .id = SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 }, -}; - -static struct qcom_icc_node qns_mem_noc_sf_cam_ife_1 = { - .name = "qns_mem_noc_sf_cam_ife_1", - .id = SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 }, -}; - -static struct qcom_icc_node qns_llcc_cam_ife_2 = { - .name = "qns_llcc_cam_ife_2", - .id = SM8550_SLAVE_LLCC_CAM_IFE_2, - .channels = 4, - .buswidth = 16, - .num_links = 1, - .links = { SM8550_MASTER_LLCC_CAM_IFE_2 }, -}; - -static struct qcom_icc_node ebi_cam_ife_2 = { - .name = "ebi_cam_ife_2", - .id = SM8550_SLAVE_EBI1_CAM_IFE_2, - .channels = 4, - .buswidth = 4, - .num_links = 0, -}; - -static struct qcom_icc_node qns_mem_noc_hf_cam_ife_2 = { - .name = "qns_mem_noc_hf_cam_ife_2", - .id = SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 }, -}; - -static struct qcom_icc_node qns_mem_noc_sf_cam_ife_2 = { - .name = "qns_mem_noc_sf_cam_ife_2", - .id = SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 }, -}; - static struct qcom_icc_bcm bcm_acv = { .name = "ACV", .enable_mask = 0x8, @@ -1639,161 +1283,6 @@ static struct qcom_icc_bcm bcm_sn7 = { .nodes = { &qns_pcie_mem_noc }, }; -static struct qcom_icc_bcm bcm_acv_disp = { - .name = "ACV", - .enable_mask = 0x1, - .num_nodes = 1, - .nodes = { &ebi_disp }, -}; - -static struct qcom_icc_bcm bcm_mc0_disp = { - .name = "MC0", - .num_nodes = 1, - .nodes = { &ebi_disp }, -}; - -static struct qcom_icc_bcm bcm_mm0_disp = { - .name = "MM0", - .num_nodes = 1, - .nodes = { &qns_mem_noc_hf_disp }, -}; - -static struct qcom_icc_bcm bcm_sh0_disp = { - .name = "SH0", - .num_nodes = 1, - .nodes = { &qns_llcc_disp }, -}; - -static struct qcom_icc_bcm bcm_sh1_disp = { - .name = "SH1", - .enable_mask = 0x1, - .num_nodes = 2, - .nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp }, -}; - -static struct qcom_icc_bcm bcm_acv_cam_ife_0 = { - .name = "ACV", - .enable_mask = 0x0, - .num_nodes = 1, - .nodes = { &ebi_cam_ife_0 }, -}; - -static struct qcom_icc_bcm bcm_mc0_cam_ife_0 = { - .name = "MC0", - .num_nodes = 1, - .nodes = { &ebi_cam_ife_0 }, -}; - -static struct qcom_icc_bcm bcm_mm0_cam_ife_0 = { - .name = "MM0", - .num_nodes = 1, - .nodes = { &qns_mem_noc_hf_cam_ife_0 }, -}; - -static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = { - .name = "MM1", - .enable_mask = 0x1, - .num_nodes = 4, - .nodes = { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0, - &qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 }, -}; - -static struct qcom_icc_bcm bcm_sh0_cam_ife_0 = { - .name = "SH0", - .num_nodes = 1, - .nodes = { &qns_llcc_cam_ife_0 }, -}; - -static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = { - .name = "SH1", - .enable_mask = 0x1, - .num_nodes = 3, - .nodes = { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0, - &qnm_pcie_cam_ife_0 }, -}; - -static struct qcom_icc_bcm bcm_acv_cam_ife_1 = { - .name = "ACV", - .enable_mask = 0x0, - .num_nodes = 1, - .nodes = { &ebi_cam_ife_1 }, -}; - -static struct qcom_icc_bcm bcm_mc0_cam_ife_1 = { - .name = "MC0", - .num_nodes = 1, - .nodes = { &ebi_cam_ife_1 }, -}; - -static struct qcom_icc_bcm bcm_mm0_cam_ife_1 = { - .name = "MM0", - .num_nodes = 1, - .nodes = { &qns_mem_noc_hf_cam_ife_1 }, -}; - -static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = { - .name = "MM1", - .enable_mask = 0x1, - .num_nodes = 4, - .nodes = { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1, - &qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 }, -}; - -static struct qcom_icc_bcm bcm_sh0_cam_ife_1 = { - .name = "SH0", - .num_nodes = 1, - .nodes = { &qns_llcc_cam_ife_1 }, -}; - -static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = { - .name = "SH1", - .enable_mask = 0x1, - .num_nodes = 3, - .nodes = { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1, - &qnm_pcie_cam_ife_1 }, -}; - -static struct qcom_icc_bcm bcm_acv_cam_ife_2 = { - .name = "ACV", - .enable_mask = 0x0, - .num_nodes = 1, - .nodes = { &ebi_cam_ife_2 }, -}; - -static struct qcom_icc_bcm bcm_mc0_cam_ife_2 = { - .name = "MC0", - .num_nodes = 1, - .nodes = { &ebi_cam_ife_2 }, -}; - -static struct qcom_icc_bcm bcm_mm0_cam_ife_2 = { - .name = "MM0", - .num_nodes = 1, - .nodes = { &qns_mem_noc_hf_cam_ife_2 }, -}; - -static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = { - .name = "MM1", - .enable_mask = 0x1, - .num_nodes = 4, - .nodes = { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2, - &qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 }, -}; - -static struct qcom_icc_bcm bcm_sh0_cam_ife_2 = { - .name = "SH0", - .num_nodes = 1, - .nodes = { &qns_llcc_cam_ife_2 }, -}; - -static struct qcom_icc_bcm bcm_sh1_cam_ife_2 = { - .name = "SH1", - .enable_mask = 0x1, - .num_nodes = 3, - .nodes = { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2, - &qnm_pcie_cam_ife_2 }, -}; - static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { }; @@ -1945,14 +1434,6 @@ static const struct qcom_icc_desc sm8550_cnoc_main = { static struct qcom_icc_bcm * const gem_noc_bcms[] = { &bcm_sh0, &bcm_sh1, - &bcm_sh0_disp, - &bcm_sh1_disp, - &bcm_sh0_cam_ife_0, - &bcm_sh1_cam_ife_0, - &bcm_sh0_cam_ife_1, - &bcm_sh1_cam_ife_1, - &bcm_sh0_cam_ife_2, - &bcm_sh1_cam_ife_2, }; static struct qcom_icc_node * const gem_noc_nodes[] = { @@ -1971,21 +1452,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, [SLAVE_LLCC] = &qns_llcc, [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, - [MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp, - [MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp, - [SLAVE_LLCC_DISP] = &qns_llcc_disp, - [MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0] = &qnm_mnoc_hf_cam_ife_0, - [MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0] = &qnm_mnoc_sf_cam_ife_0, - [MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0] = &qnm_pcie_cam_ife_0, - [SLAVE_LLCC_CAM_IFE_0] = &qns_llcc_cam_ife_0, - [MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1] = &qnm_mnoc_hf_cam_ife_1, - [MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1] = &qnm_mnoc_sf_cam_ife_1, - [MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1] = &qnm_pcie_cam_ife_1, - [SLAVE_LLCC_CAM_IFE_1] = &qns_llcc_cam_ife_1, - [MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2] = &qnm_mnoc_hf_cam_ife_2, - [MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2] = &qnm_mnoc_sf_cam_ife_2, - [MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2] = &qnm_pcie_cam_ife_2, - [SLAVE_LLCC_CAM_IFE_2] = &qns_llcc_cam_ife_2, }; static const struct qcom_icc_desc sm8550_gem_noc = { @@ -2044,27 +1510,11 @@ static const struct qcom_icc_desc sm8550_lpass_lpicx_noc = { static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_acv, &bcm_mc0, - &bcm_acv_disp, - &bcm_mc0_disp, - &bcm_acv_cam_ife_0, - &bcm_mc0_cam_ife_0, - &bcm_acv_cam_ife_1, - &bcm_mc0_cam_ife_1, - &bcm_acv_cam_ife_2, - &bcm_mc0_cam_ife_2, }; static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [SLAVE_EBI1] = &ebi, - [MASTER_LLCC_DISP] = &llcc_mc_disp, - [SLAVE_EBI1_DISP] = &ebi_disp, - [MASTER_LLCC_CAM_IFE_0] = &llcc_mc_cam_ife_0, - [SLAVE_EBI1_CAM_IFE_0] = &ebi_cam_ife_0, - [MASTER_LLCC_CAM_IFE_1] = &llcc_mc_cam_ife_1, - [SLAVE_EBI1_CAM_IFE_1] = &ebi_cam_ife_1, - [MASTER_LLCC_CAM_IFE_2] = &llcc_mc_cam_ife_2, - [SLAVE_EBI1_CAM_IFE_2] = &ebi_cam_ife_2, }; static const struct qcom_icc_desc sm8550_mc_virt = { @@ -2077,13 +1527,6 @@ static const struct qcom_icc_desc sm8550_mc_virt = { static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, - &bcm_mm0_disp, - &bcm_mm0_cam_ife_0, - &bcm_mm1_cam_ife_0, - &bcm_mm0_cam_ife_1, - &bcm_mm1_cam_ife_1, - &bcm_mm0_cam_ife_2, - &bcm_mm1_cam_ife_2, }; static struct qcom_icc_node * const mmss_noc_nodes[] = { @@ -2100,23 +1543,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, [SLAVE_SERVICE_MNOC] = &srvc_mnoc, - [MASTER_MDP_DISP] = &qnm_mdp_disp, - [SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp, - [MASTER_CAMNOC_HF_CAM_IFE_0] = &qnm_camnoc_hf_cam_ife_0, - [MASTER_CAMNOC_ICP_CAM_IFE_0] = &qnm_camnoc_icp_cam_ife_0, - [MASTER_CAMNOC_SF_CAM_IFE_0] = &qnm_camnoc_sf_cam_ife_0, - [SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0] = &qns_mem_noc_hf_cam_ife_0, - [SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0] = &qns_mem_noc_sf_cam_ife_0, - [MASTER_CAMNOC_HF_CAM_IFE_1] = &qnm_camnoc_hf_cam_ife_1, - [MASTER_CAMNOC_ICP_CAM_IFE_1] = &qnm_camnoc_icp_cam_ife_1, - [MASTER_CAMNOC_SF_CAM_IFE_1] = &qnm_camnoc_sf_cam_ife_1, - [SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1] = &qns_mem_noc_hf_cam_ife_1, - [SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1] = &qns_mem_noc_sf_cam_ife_1, - [MASTER_CAMNOC_HF_CAM_IFE_2] = &qnm_camnoc_hf_cam_ife_2, - [MASTER_CAMNOC_ICP_CAM_IFE_2] = &qnm_camnoc_icp_cam_ife_2, - [MASTER_CAMNOC_SF_CAM_IFE_2] = &qnm_camnoc_sf_cam_ife_2, - [SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2] = &qns_mem_noc_hf_cam_ife_2, - [SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2] = &qns_mem_noc_sf_cam_ife_2, }; static const struct qcom_icc_desc sm8550_mmss_noc = { diff --git a/drivers/interconnect/qcom/sm8550.h b/drivers/interconnect/qcom/sm8550.h index 8d5862c04bca..c9b2986e1293 100644 --- a/drivers/interconnect/qcom/sm8550.h +++ b/drivers/interconnect/qcom/sm8550.h @@ -12,167 +12,127 @@ #define SM8550_MASTER_A1NOC_SNOC 0 #define SM8550_MASTER_A2NOC_SNOC 1 #define SM8550_MASTER_ANOC_PCIE_GEM_NOC 2 -#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0 3 -#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1 4 -#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2 5 -#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_DISP 6 -#define SM8550_MASTER_APPSS_PROC 7 -#define SM8550_MASTER_CAMNOC_HF 8 -#define SM8550_MASTER_CAMNOC_HF_CAM_IFE_0 9 -#define SM8550_MASTER_CAMNOC_HF_CAM_IFE_1 10 -#define SM8550_MASTER_CAMNOC_HF_CAM_IFE_2 11 -#define SM8550_MASTER_CAMNOC_ICP 12 -#define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_0 13 -#define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_1 14 -#define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_2 15 -#define SM8550_MASTER_CAMNOC_SF 16 -#define SM8550_MASTER_CAMNOC_SF_CAM_IFE_0 17 -#define SM8550_MASTER_CAMNOC_SF_CAM_IFE_1 18 -#define SM8550_MASTER_CAMNOC_SF_CAM_IFE_2 19 -#define SM8550_MASTER_CDSP_HCP 20 -#define SM8550_MASTER_CDSP_PROC 21 -#define SM8550_MASTER_CNOC_CFG 22 -#define SM8550_MASTER_CNOC_MNOC_CFG 23 -#define SM8550_MASTER_COMPUTE_NOC 24 -#define SM8550_MASTER_CRYPTO 25 -#define SM8550_MASTER_GEM_NOC_CNOC 26 -#define SM8550_MASTER_GEM_NOC_PCIE_SNOC 27 -#define SM8550_MASTER_GFX3D 28 -#define SM8550_MASTER_GIC 29 -#define SM8550_MASTER_GIC_AHB 30 -#define SM8550_MASTER_GPU_TCU 31 -#define SM8550_MASTER_IPA 32 -#define SM8550_MASTER_LLCC 33 -#define SM8550_MASTER_LLCC_CAM_IFE_0 34 -#define SM8550_MASTER_LLCC_CAM_IFE_1 35 -#define SM8550_MASTER_LLCC_CAM_IFE_2 36 -#define SM8550_MASTER_LLCC_DISP 37 -#define SM8550_MASTER_LPASS_GEM_NOC 38 -#define SM8550_MASTER_LPASS_LPINOC 39 -#define SM8550_MASTER_LPASS_PROC 40 -#define SM8550_MASTER_LPIAON_NOC 41 -#define SM8550_MASTER_MDP 42 -#define SM8550_MASTER_MDP_DISP 43 -#define SM8550_MASTER_MNOC_HF_MEM_NOC 44 -#define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 45 -#define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 46 -#define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 47 -#define SM8550_MASTER_MNOC_HF_MEM_NOC_DISP 48 -#define SM8550_MASTER_MNOC_SF_MEM_NOC 49 -#define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 50 -#define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 51 -#define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 52 -#define SM8550_MASTER_MSS_PROC 53 -#define SM8550_MASTER_PCIE_0 54 -#define SM8550_MASTER_PCIE_1 55 -#define SM8550_MASTER_PCIE_ANOC_CFG 56 -#define SM8550_MASTER_QDSS_BAM 57 -#define SM8550_MASTER_QDSS_ETR 58 -#define SM8550_MASTER_QDSS_ETR_1 59 -#define SM8550_MASTER_QSPI_0 60 -#define SM8550_MASTER_QUP_1 61 -#define SM8550_MASTER_QUP_2 62 -#define SM8550_MASTER_QUP_CORE_0 63 -#define SM8550_MASTER_QUP_CORE_1 64 -#define SM8550_MASTER_QUP_CORE_2 65 -#define SM8550_MASTER_SDCC_2 66 -#define SM8550_MASTER_SDCC_4 67 -#define SM8550_MASTER_SNOC_GC_MEM_NOC 68 -#define SM8550_MASTER_SNOC_SF_MEM_NOC 69 -#define SM8550_MASTER_SP 70 -#define SM8550_MASTER_SYS_TCU 71 -#define SM8550_MASTER_UFS_MEM 72 -#define SM8550_MASTER_USB3_0 73 -#define SM8550_MASTER_VIDEO 74 -#define SM8550_MASTER_VIDEO_CV_PROC 75 -#define SM8550_MASTER_VIDEO_PROC 76 -#define SM8550_MASTER_VIDEO_V_PROC 77 -#define SM8550_SLAVE_A1NOC_SNOC 78 -#define SM8550_SLAVE_A2NOC_SNOC 79 -#define SM8550_SLAVE_AHB2PHY_NORTH 80 -#define SM8550_SLAVE_AHB2PHY_SOUTH 81 -#define SM8550_SLAVE_ANOC_PCIE_GEM_NOC 82 -#define SM8550_SLAVE_AOSS 83 -#define SM8550_SLAVE_APPSS 84 -#define SM8550_SLAVE_BOOT_IMEM 85 -#define SM8550_SLAVE_CAMERA_CFG 86 -#define SM8550_SLAVE_CDSP_MEM_NOC 87 -#define SM8550_SLAVE_CLK_CTL 88 -#define SM8550_SLAVE_CNOC_CFG 89 -#define SM8550_SLAVE_CNOC_MNOC_CFG 90 -#define SM8550_SLAVE_CNOC_MSS 91 -#define SM8550_SLAVE_CPR_NSPCX 92 -#define SM8550_SLAVE_CRYPTO_0_CFG 93 -#define SM8550_SLAVE_CX_RDPM 94 -#define SM8550_SLAVE_DDRSS_CFG 95 -#define SM8550_SLAVE_DISPLAY_CFG 96 -#define SM8550_SLAVE_EBI1 97 -#define SM8550_SLAVE_EBI1_CAM_IFE_0 98 -#define SM8550_SLAVE_EBI1_CAM_IFE_1 99 -#define SM8550_SLAVE_EBI1_CAM_IFE_2 100 -#define SM8550_SLAVE_EBI1_DISP 101 -#define SM8550_SLAVE_GEM_NOC_CNOC 102 -#define SM8550_SLAVE_GFX3D_CFG 103 -#define SM8550_SLAVE_I2C 104 -#define SM8550_SLAVE_IMEM 105 -#define SM8550_SLAVE_IMEM_CFG 106 -#define SM8550_SLAVE_IPA_CFG 107 -#define SM8550_SLAVE_IPC_ROUTER_CFG 108 -#define SM8550_SLAVE_LLCC 109 -#define SM8550_SLAVE_LLCC_CAM_IFE_0 110 -#define SM8550_SLAVE_LLCC_CAM_IFE_1 111 -#define SM8550_SLAVE_LLCC_CAM_IFE_2 112 -#define SM8550_SLAVE_LLCC_DISP 113 -#define SM8550_SLAVE_LPASS_GEM_NOC 114 -#define SM8550_SLAVE_LPASS_QTB_CFG 115 -#define SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC 116 -#define SM8550_SLAVE_LPICX_NOC_LPIAON_NOC 117 -#define SM8550_SLAVE_MEM_NOC_PCIE_SNOC 118 -#define SM8550_SLAVE_MNOC_HF_MEM_NOC 119 -#define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 120 -#define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 121 -#define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 122 -#define SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP 123 -#define SM8550_SLAVE_MNOC_SF_MEM_NOC 124 -#define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 125 -#define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 126 -#define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 127 -#define SM8550_SLAVE_MX_RDPM 128 -#define SM8550_SLAVE_NSP_QTB_CFG 129 -#define SM8550_SLAVE_PCIE_0 130 -#define SM8550_SLAVE_PCIE_0_CFG 131 -#define SM8550_SLAVE_PCIE_1 132 -#define SM8550_SLAVE_PCIE_1_CFG 133 -#define SM8550_SLAVE_PCIE_ANOC_CFG 134 -#define SM8550_SLAVE_PDM 135 -#define SM8550_SLAVE_PIMEM_CFG 136 -#define SM8550_SLAVE_PRNG 137 -#define SM8550_SLAVE_QDSS_CFG 138 -#define SM8550_SLAVE_QDSS_STM 139 -#define SM8550_SLAVE_QSPI_0 140 -#define SM8550_SLAVE_QUP_1 141 -#define SM8550_SLAVE_QUP_2 142 -#define SM8550_SLAVE_QUP_CORE_0 143 -#define SM8550_SLAVE_QUP_CORE_1 144 -#define SM8550_SLAVE_QUP_CORE_2 145 -#define SM8550_SLAVE_RBCPR_CX_CFG 146 -#define SM8550_SLAVE_RBCPR_MMCX_CFG 147 -#define SM8550_SLAVE_RBCPR_MXA_CFG 148 -#define SM8550_SLAVE_RBCPR_MXC_CFG 149 -#define SM8550_SLAVE_SDCC_2 150 -#define SM8550_SLAVE_SDCC_4 151 -#define SM8550_SLAVE_SERVICE_MNOC 152 -#define SM8550_SLAVE_SERVICE_PCIE_ANOC 153 -#define SM8550_SLAVE_SNOC_GEM_NOC_GC 154 -#define SM8550_SLAVE_SNOC_GEM_NOC_SF 155 -#define SM8550_SLAVE_SPSS_CFG 156 -#define SM8550_SLAVE_TCSR 157 -#define SM8550_SLAVE_TCU 158 -#define SM8550_SLAVE_TLMM 159 -#define SM8550_SLAVE_TME_CFG 160 -#define SM8550_SLAVE_UFS_MEM_CFG 161 -#define SM8550_SLAVE_USB3_0 162 -#define SM8550_SLAVE_VENUS_CFG 163 -#define SM8550_SLAVE_VSENSE_CTRL_CFG 164 +#define SM8550_MASTER_APPSS_PROC 3 +#define SM8550_MASTER_CAMNOC_HF 4 +#define SM8550_MASTER_CAMNOC_ICP 5 +#define SM8550_MASTER_CAMNOC_SF 6 +#define SM8550_MASTER_CDSP_HCP 7 +#define SM8550_MASTER_CDSP_PROC 8 +#define SM8550_MASTER_CNOC_CFG 9 +#define SM8550_MASTER_CNOC_MNOC_CFG 10 +#define SM8550_MASTER_COMPUTE_NOC 11 +#define SM8550_MASTER_CRYPTO 12 +#define SM8550_MASTER_GEM_NOC_CNOC 13 +#define SM8550_MASTER_GEM_NOC_PCIE_SNOC 14 +#define SM8550_MASTER_GFX3D 15 +#define SM8550_MASTER_GIC 16 +#define SM8550_MASTER_GIC_AHB 17 +#define SM8550_MASTER_GPU_TCU 18 +#define SM8550_MASTER_IPA 19 +#define SM8550_MASTER_LLCC 20 +#define SM8550_MASTER_LPASS_GEM_NOC 21 +#define SM8550_MASTER_LPASS_LPINOC 22 +#define SM8550_MASTER_LPASS_PROC 23 +#define SM8550_MASTER_LPIAON_NOC 24 +#define SM8550_MASTER_MDP 25 +#define SM8550_MASTER_MNOC_HF_MEM_NOC 26 +#define SM8550_MASTER_MNOC_SF_MEM_NOC 27 +#define SM8550_MASTER_MSS_PROC 28 +#define SM8550_MASTER_PCIE_0 29 +#define SM8550_MASTER_PCIE_1 30 +#define SM8550_MASTER_PCIE_ANOC_CFG 31 +#define SM8550_MASTER_QDSS_BAM 32 +#define SM8550_MASTER_QDSS_ETR 33 +#define SM8550_MASTER_QDSS_ETR_1 34 +#define SM8550_MASTER_QSPI_0 35 +#define SM8550_MASTER_QUP_1 36 +#define SM8550_MASTER_QUP_2 37 +#define SM8550_MASTER_QUP_CORE_0 38 +#define SM8550_MASTER_QUP_CORE_1 39 +#define SM8550_MASTER_QUP_CORE_2 40 +#define SM8550_MASTER_SDCC_2 41 +#define SM8550_MASTER_SDCC_4 42 +#define SM8550_MASTER_SNOC_GC_MEM_NOC 43 +#define SM8550_MASTER_SNOC_SF_MEM_NOC 44 +#define SM8550_MASTER_SP 45 +#define SM8550_MASTER_SYS_TCU 46 +#define SM8550_MASTER_UFS_MEM 47 +#define SM8550_MASTER_USB3_0 48 +#define SM8550_MASTER_VIDEO 49 +#define SM8550_MASTER_VIDEO_CV_PROC 50 +#define SM8550_MASTER_VIDEO_PROC 51 +#define SM8550_MASTER_VIDEO_V_PROC 52 +#define SM8550_SLAVE_A1NOC_SNOC 53 +#define SM8550_SLAVE_A2NOC_SNOC 54 +#define SM8550_SLAVE_AHB2PHY_NORTH 55 +#define SM8550_SLAVE_AHB2PHY_SOUTH 56 +#define SM8550_SLAVE_ANOC_PCIE_GEM_NOC 57 +#define SM8550_SLAVE_AOSS 58 +#define SM8550_SLAVE_APPSS 59 +#define SM8550_SLAVE_BOOT_IMEM 60 +#define SM8550_SLAVE_CAMERA_CFG 61 +#define SM8550_SLAVE_CDSP_MEM_NOC 62 +#define SM8550_SLAVE_CLK_CTL 63 +#define SM8550_SLAVE_CNOC_CFG 64 +#define SM8550_SLAVE_CNOC_MNOC_CFG 65 +#define SM8550_SLAVE_CNOC_MSS 66 +#define SM8550_SLAVE_CPR_NSPCX 67 +#define SM8550_SLAVE_CRYPTO_0_CFG 68 +#define SM8550_SLAVE_CX_RDPM 69 +#define SM8550_SLAVE_DDRSS_CFG 70 +#define SM8550_SLAVE_DISPLAY_CFG 71 +#define SM8550_SLAVE_EBI1 72 +#define SM8550_SLAVE_GEM_NOC_CNOC 73 +#define SM8550_SLAVE_GFX3D_CFG 74 +#define SM8550_SLAVE_I2C 75 +#define SM8550_SLAVE_IMEM 76 +#define SM8550_SLAVE_IMEM_CFG 77 +#define SM8550_SLAVE_IPA_CFG 78 +#define SM8550_SLAVE_IPC_ROUTER_CFG 79 +#define SM8550_SLAVE_LLCC 80 +#define SM8550_SLAVE_LPASS_GEM_NOC 81 +#define SM8550_SLAVE_LPASS_QTB_CFG 82 +#define SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC 83 +#define SM8550_SLAVE_LPICX_NOC_LPIAON_NOC 84 +#define SM8550_SLAVE_MEM_NOC_PCIE_SNOC 85 +#define SM8550_SLAVE_MNOC_HF_MEM_NOC 86 +#define SM8550_SLAVE_MNOC_SF_MEM_NOC 87 +#define SM8550_SLAVE_MX_RDPM 88 +#define SM8550_SLAVE_NSP_QTB_CFG 89 +#define SM8550_SLAVE_PCIE_0 90 +#define SM8550_SLAVE_PCIE_0_CFG 91 +#define SM8550_SLAVE_PCIE_1 92 +#define SM8550_SLAVE_PCIE_1_CFG 93 +#define SM8550_SLAVE_PCIE_ANOC_CFG 94 +#define SM8550_SLAVE_PDM 95 +#define SM8550_SLAVE_PIMEM_CFG 96 +#define SM8550_SLAVE_PRNG 97 +#define SM8550_SLAVE_QDSS_CFG 98 +#define SM8550_SLAVE_QDSS_STM 99 +#define SM8550_SLAVE_QSPI_0 100 +#define SM8550_SLAVE_QUP_1 101 +#define SM8550_SLAVE_QUP_2 102 +#define SM8550_SLAVE_QUP_CORE_0 103 +#define SM8550_SLAVE_QUP_CORE_1 104 +#define SM8550_SLAVE_QUP_CORE_2 105 +#define SM8550_SLAVE_RBCPR_CX_CFG 106 +#define SM8550_SLAVE_RBCPR_MMCX_CFG 107 +#define SM8550_SLAVE_RBCPR_MXA_CFG 108 +#define SM8550_SLAVE_RBCPR_MXC_CFG 109 +#define SM8550_SLAVE_SDCC_2 110 +#define SM8550_SLAVE_SDCC_4 111 +#define SM8550_SLAVE_SERVICE_MNOC 112 +#define SM8550_SLAVE_SERVICE_PCIE_ANOC 113 +#define SM8550_SLAVE_SNOC_GEM_NOC_GC 114 +#define SM8550_SLAVE_SNOC_GEM_NOC_SF 115 +#define SM8550_SLAVE_SPSS_CFG 116 +#define SM8550_SLAVE_TCSR 117 +#define SM8550_SLAVE_TCU 118 +#define SM8550_SLAVE_TLMM 119 +#define SM8550_SLAVE_TME_CFG 120 +#define SM8550_SLAVE_UFS_MEM_CFG 121 +#define SM8550_SLAVE_USB3_0 122 +#define SM8550_SLAVE_VENUS_CFG 123 +#define SM8550_SLAVE_VSENSE_CTRL_CFG 124 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[178.235.179.137]) by smtp.gmail.com with ESMTPSA id ts7-20020a170907c5c700b00a1dd58874b8sm14260693ejc.119.2023.12.18.08.02.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 08:02:19 -0800 (PST) From: Konrad Dybcio Date: Mon, 18 Dec 2023 17:02:03 +0100 Subject: [PATCH 02/12] interconnect: qcom: sm8550: Enable sync_state Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231218-topic-8550_fixes-v1-2-ce1272d77540@linaro.org> References: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> In-Reply-To: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> To: Bjorn Andersson , Georgi Djakov , Abel Vesa , Michael Turquette , Stephen Boyd , Taniya Das , Jagadeesh Kona , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sai Prakash Ranjan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1702915332; l=794; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=vn3HlIlPR6ucV7JF0xNr2wT4h4pXu1XpkqI9qeViBog=; b=NAyGsbdan2haOqAWOkwgUgINzfJZo+6CBBSFmKyYwJlLOaooPc8dnPr8UBAlz7a+e58XODMnH Q54QEwcjOMEDRBauJyD1DSpTyc6ddEKIPfMlu9phhAyI3PiuvN65/0C X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= To ensure the interconnect votes are actually meaningful and in order to prevent holding all buses at FMAX, introduce the sync state callback. Fixes: e6f0d6a30f73 ("interconnect: qcom: Add SM8550 interconnect provider driver") Signed-off-by: Konrad Dybcio Reviewed-by: Bjorn Andersson --- drivers/interconnect/qcom/sm8550.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c index abc52ad3d1f2..4d0e6fa9e003 100644 --- a/drivers/interconnect/qcom/sm8550.c +++ b/drivers/interconnect/qcom/sm8550.c @@ -1649,6 +1649,7 @@ static struct platform_driver qnoc_driver = { .driver = { .name = "qnoc-sm8550", .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, }, }; From patchwork Mon Dec 18 16:02:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 757217 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAF0D4FF8F for ; Mon, 18 Dec 2023 16:02:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="X+MLZ9y4" Received: by mail-ej1-f48.google.com with SMTP id a640c23a62f3a-a1ca24776c3so835752266b.0 for ; Mon, 18 Dec 2023 08:02:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702915342; x=1703520142; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=T/einnfOMlZZ67QTI1k3LN2oLp4rlOytUU6/FZwO/Q8=; b=X+MLZ9y4uNnGehAG2SpmhDtJn2VnM8iBNxYJGxRNav9EKzCGRJFrB8U8bk1BOFZWgd /IT56EcXg1gQ99OBuY0K44QMWvy1QgmHKl/bktXj0+0EzMHVMypahut5IFjQG/W2t7VW sNNGn1O7CywS+3VYup7EVaWIJGanuzHyDNT+2kb9nriDy/axukwvxaEGDxLqENmNgoEK oFEhJRw7dzNXgX8eTjGvxyNdsIreK5bVA80UcLMXHjtZr+ITKidmVSFP383F0M0yX/VG ys4cXFXrPZrcGgOYcOOxUbR+tlRKgOBqKjS5SfOzPqaOCcfNWG2z9MgtmYSaglhKjT03 8AuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702915342; x=1703520142; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T/einnfOMlZZ67QTI1k3LN2oLp4rlOytUU6/FZwO/Q8=; b=HxQ5+joSWVHiwHVuogqc6ZfPgcEikxrg3EKlGSRPxNIlTKyhd41sUDJbpXC5fUZSWl uyLYGKhDcat2SIe9gttNkbgteMqiU8KV2eNEk49YzBcI5yJ05Ba19qEzLuVcdUk6aJ0s FPjAdZW2P1mGvTpe+eYY50vqbjvM5DHNsSMI6Xm0rR4q67zLKQwJlfjLWHgVZvuphc1i iGDwy8Rl5zeRWYItMySgbXVQUkfOSSAW+uaRt2WGStwHA83Wi0Y78MW4B0up+di1h+37 WBCpWUk0j2GXBtI11tV5CVuSqcYd1cRyQcDUXlZ6di088/gmMWYubn841GEcn3HRNvs/ gMHw== X-Gm-Message-State: AOJu0Yxl+bSGDzJmssk6SqxP/EEodQD4bNXctnfziYL1bXI2tXSLqaFD fgDwSo6qBo/g+fHUwQRVao3Hew== X-Google-Smtp-Source: AGHT+IHtObdFAHPJSSw3kqb0DyxPAxgAAn4ocnx2KQ3aU2c2MIq03tw7/GR9cXWRvd99tBDrw5Cvaw== X-Received: by 2002:a17:906:4581:b0:a1f:74e7:8bdd with SMTP id qs1-20020a170906458100b00a1f74e78bddmr15873731ejc.25.1702915341867; Mon, 18 Dec 2023 08:02:21 -0800 (PST) Received: from [10.167.154.1] (178235179137.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.137]) by smtp.gmail.com with ESMTPSA id ts7-20020a170907c5c700b00a1dd58874b8sm14260693ejc.119.2023.12.18.08.02.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 08:02:21 -0800 (PST) From: Konrad Dybcio Date: Mon, 18 Dec 2023 17:02:04 +0100 Subject: [PATCH 03/12] clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flag Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231218-topic-8550_fixes-v1-3-ce1272d77540@linaro.org> References: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> In-Reply-To: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> To: Bjorn Andersson , Georgi Djakov , Abel Vesa , Michael Turquette , Stephen Boyd , Taniya Das , Jagadeesh Kona , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sai Prakash Ranjan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1702915332; l=2558; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=keR6/82q0ryYI3TMPWNKSZJMZ6EXNo8Q0Uj0Y7Gl5JI=; b=NI9KfFleXMMZcLpWmmKdvXd1fYIDFDUf1YtNoSJ+ydiG02n7+cnA+qlY+8qyADxuNXFQH/Uu2 oP5mTxkd9vuB9MbdSTwd3vHwdlNLnTOY/13dqjgUOqrnawO4zZxy3iM X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= All of the 8550's GCC GDSCs can and should use the retain registers so as not to lose their state when entering lower power modes. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm8550.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index 586126c4dd90..1c3d78500392 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -3002,7 +3002,7 @@ static struct gdsc pcie_0_gdsc = { .name = "pcie_0_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, }; static struct gdsc pcie_0_phy_gdsc = { @@ -3011,7 +3011,7 @@ static struct gdsc pcie_0_phy_gdsc = { .name = "pcie_0_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, }; static struct gdsc pcie_1_gdsc = { @@ -3020,7 +3020,7 @@ static struct gdsc pcie_1_gdsc = { .name = "pcie_1_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, }; static struct gdsc pcie_1_phy_gdsc = { @@ -3029,7 +3029,7 @@ static struct gdsc pcie_1_phy_gdsc = { .name = "pcie_1_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, }; static struct gdsc ufs_phy_gdsc = { @@ -3038,7 +3038,7 @@ static struct gdsc ufs_phy_gdsc = { .name = "ufs_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, }; static struct gdsc ufs_mem_phy_gdsc = { @@ -3047,7 +3047,7 @@ static struct gdsc ufs_mem_phy_gdsc = { .name = "ufs_mem_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, }; static struct gdsc usb30_prim_gdsc = { @@ -3056,7 +3056,7 @@ static struct gdsc usb30_prim_gdsc = { .name = "usb30_prim_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, }; static struct gdsc usb3_phy_gdsc = { @@ -3065,7 +3065,7 @@ static struct gdsc usb3_phy_gdsc = { .name = "usb3_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, }; static struct clk_regmap *gcc_sm8550_clocks[] = { From patchwork Mon Dec 18 16:02:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 755523 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C23BB42383 for ; Mon, 18 Dec 2023 16:02:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="dCrhBWow" Received: by mail-ej1-f45.google.com with SMTP id a640c23a62f3a-a1ca24776c3so835779366b.0 for ; Mon, 18 Dec 2023 08:02:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702915344; x=1703520144; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=VT6UxuEKPmgj4jLSU2GUCRPmbth0aVHzMw+IpobCJZM=; b=dCrhBWowh3/hZ0T83tgYq9ZhNjPrAZdof0dna0PXYpawAdaTtSqdGfGT/NgKBLTN4b HA6FcewY8HACN+TIMO4KWi9AZZpfPD4vJfV+VefiIPJ3AfRGFCrdC88t4hWIhY2jXKbW weiTjmoCeHMUv0KIdjzdMKFLu1f14LipufXcO7fmpA3B5VnhAC2PcE3p46YC69ui4k7V /eMq6XzZNlUH7510pldYqMqLMFzTDuiiPPWkXbiRx4PVijUDIWEeK0qO38xazr/LHfWC 0uvECNTWSgY9HuqeX4SgX2m890ekRhvFHqJNkgEo12P+C6NwANfADVDNYFVf9Sch/Zpq VIzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702915344; x=1703520144; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VT6UxuEKPmgj4jLSU2GUCRPmbth0aVHzMw+IpobCJZM=; b=E3c8HjIqnUG/hGeXNs+ML75XXRXG4YoDGu1c8dd0eEY29n/AQemXtlsEzkuGmdBK4u OLeMkZi/0BMthYhLKfxjIGouyKiGQMsCO/qFWi+v/LY0vnTPKdKJMsMOLNo7P7J9u2iX nTZMXjP2PpaAi9wCIS72pKt8X2NZiEFdsEJWy3xyXdLMWYQyyZwaXdk0tEZCPccl/Qhv Oc5j3mz3oJdNNa4uJRiq9alWi0GQib9C5u+hu8K3fAuvbXd/6sdGXDsJCgLLRmqUuAIX Pl7SJxmWtYcbr/ikweQBVYGOsQZSu94aGiAsCy2xe9x/7zoVSdnn5G4a2z75J5yenObv w7Fw== X-Gm-Message-State: AOJu0YzWy+5+pFzfd9J9dp4I6ZJbAnDM0wlPdqtRCh7U6Fi5tqkZXU+J tXHHrbCIS27lJ6W6mzbQhIU9Vw== X-Google-Smtp-Source: AGHT+IFMUg3W1ZnrrBBif7zvuPAXmotgD+6XxD9Si/YfU4KMSkMTQFW/g2o1+cOLheClBTLlwPLIqQ== X-Received: by 2002:a17:906:c6:b0:a1f:821a:11a7 with SMTP id 6-20020a17090600c600b00a1f821a11a7mr11143127eji.25.1702915344275; Mon, 18 Dec 2023 08:02:24 -0800 (PST) Received: from [10.167.154.1] (178235179137.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.137]) by smtp.gmail.com with ESMTPSA id ts7-20020a170907c5c700b00a1dd58874b8sm14260693ejc.119.2023.12.18.08.02.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 08:02:24 -0800 (PST) From: Konrad Dybcio Date: Mon, 18 Dec 2023 17:02:05 +0100 Subject: [PATCH 04/12] clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votable Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231218-topic-8550_fixes-v1-4-ce1272d77540@linaro.org> References: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> In-Reply-To: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> To: Bjorn Andersson , Georgi Djakov , Abel Vesa , Michael Turquette , Stephen Boyd , Taniya Das , Jagadeesh Kona , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sai Prakash Ranjan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1702915332; l=1748; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=P+3qldiPbBZFJ8BOsbpVXXtVoE2i4b8QX9ekzA577Gk=; b=JFonqRDRhPpQ/2YnHmDHF5ERvXSDmDhffrNQqfycNc0wNJVn91FvnKARVHGTGkWHLvphmIces sksBRdyjZc9DCPCWikRNnz2innkwqtBzoV7YCsykCMD55qtzeUVuRq5 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The PCIe GDSCs on most Qualcomm platforms expect the OS to always consider collapse requests as successful. This also concerns SM8550. Add the VOTABLE flag to the GDSCs in question to comply with these expectations. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm8550.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index 1c3d78500392..a16d07426b71 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -3002,7 +3002,7 @@ static struct gdsc pcie_0_gdsc = { .name = "pcie_0_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, }; static struct gdsc pcie_0_phy_gdsc = { @@ -3011,7 +3011,7 @@ static struct gdsc pcie_0_phy_gdsc = { .name = "pcie_0_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, }; static struct gdsc pcie_1_gdsc = { @@ -3020,7 +3020,7 @@ static struct gdsc pcie_1_gdsc = { .name = "pcie_1_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, }; static struct gdsc pcie_1_phy_gdsc = { @@ -3029,7 +3029,7 @@ static struct gdsc pcie_1_phy_gdsc = { .name = "pcie_1_phy_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, }; static struct gdsc ufs_phy_gdsc = { From patchwork Mon Dec 18 16:02:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 757216 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84EA05BFB0 for ; Mon, 18 Dec 2023 16:02:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="aCVDHbyX" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-40c2c65e6aaso41225655e9.2 for ; Mon, 18 Dec 2023 08:02:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702915347; x=1703520147; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=yeZetCZqAjDfSmYH46X1jjlV0+TjZufo6m3dLVzQ+S4=; b=aCVDHbyXp8XIpxKCqBbIKLTaXbB4yNe3M/7nwZrIWprL6XYTg0vAEn7br2DpVsHsYd 5MWeWp9MOuUAcdX3BeXxuolkvVeYHsQwMkrOegXRKa2Dq8f+PB7uvhKgXl3eqvgNi7ol ra2dD890cEwd7JpjHktH03XXzO/bj7+GZ6LPPAWAOX4hEKTVPw9ZzRhNouwoJ8Sa5DYM HmBUtQBa01ZXP0hs8pvwye8rdB3k9kdXfozk4fJnzOALvnDSWLMqZnp3YokqVfeJjvnz xY9DbB1RHHIKAcPI+M63NyLR1G1xPcHG+qWOLgsSHDjTV+NmcuIBzyOc3TeqGInZKYTy Zk0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702915347; x=1703520147; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yeZetCZqAjDfSmYH46X1jjlV0+TjZufo6m3dLVzQ+S4=; b=ElEVw1hKv4qLrQ5cipOiJDrXb7j3YXzFV18sBi8snMO6DIrumeXdJLYXt8wC2plr5A lWgAnwRDLPPntR21uufmR1kfr5JoFiDhcwlhIsW1ily1RYmIMre2rnPGfn7NaIVK0Z8p 45qeWU6sLkLLr1a2oX4/U0LvdFRLTJPk6v1QwGa4SJN6fxO0FuraTzsU7qJWOcvmzJng m2ZLh/JarAaC7VuGtvckNEJB8I4eOUi2/Gwf9trPaMgZ38QsIdCprBsAkhy+BLoBH8YD 5Rd+oyW4CJ8LdPd3IDZejrQ9LEp4BqCkJFqiC/dR7vcIu4H3MZJ/OObqBMl1qw4r+R5T OHSA== X-Gm-Message-State: AOJu0YyuuVheqRloPzHMuxALHuWDoSaJXHi7eH5tEvKk6ZUTnsYZLJxi pUIyNA1d5TTuDqBdfdKrnEbK6w== X-Google-Smtp-Source: AGHT+IEhH8Cm/7N1a2HGbuWE26iVjDxJr/RSPJj5TmO1nT/mLSPqnfvL2D5CLL3oKA1egQJFO8uxWQ== X-Received: by 2002:a05:600c:474d:b0:40c:708b:cf52 with SMTP id w13-20020a05600c474d00b0040c708bcf52mr2013391wmo.122.1702915346798; Mon, 18 Dec 2023 08:02:26 -0800 (PST) Received: from [10.167.154.1] (178235179137.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.137]) by smtp.gmail.com with ESMTPSA id ts7-20020a170907c5c700b00a1dd58874b8sm14260693ejc.119.2023.12.18.08.02.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 08:02:26 -0800 (PST) From: Konrad Dybcio Date: Mon, 18 Dec 2023 17:02:06 +0100 Subject: [PATCH 05/12] clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCs Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231218-topic-8550_fixes-v1-5-ce1272d77540@linaro.org> References: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> In-Reply-To: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> To: Bjorn Andersson , Georgi Djakov , Abel Vesa , Michael Turquette , Stephen Boyd , Taniya Das , Jagadeesh Kona , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sai Prakash Ranjan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1702915332; l=1720; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=N7ribrag25hwrEIJX+mk3d9ZiSp/Y74Ht6lzkGi4xcQ=; b=Q0hpQovWX3D9xySyJlu36S3vjYXNimLqsRXVvoDPkESrr0Tz8RPZbVIA4Ax+HmuuKblQEcaS4 pRsrNl+94xoA7LlvekJOjpLRk0zNUJWxHmDqY9i9dLummXWEoXnZ6oJ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The PCIe GDSCs can be shared with other masters and should use the APCS collapse-vote register when updating the power state. This is specifically also needed to be able to disable power domains that have been enabled by boot firmware using the vote register. Following other recent Qualcomm platforms, describe this register and the corresponding mask for the PCIe (and _phy) GDSCs. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm8550.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index a16d07426b71..73bda0d03aa7 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -2998,6 +2998,8 @@ static struct clk_branch gcc_video_axi1_clk = { static struct gdsc pcie_0_gdsc = { .gdscr = 0x6b004, + .collapse_ctrl = 0x52020, + .collapse_mask = BIT(0), .pd = { .name = "pcie_0_gdsc", }, @@ -3007,6 +3009,8 @@ static struct gdsc pcie_0_gdsc = { static struct gdsc pcie_0_phy_gdsc = { .gdscr = 0x6c000, + .collapse_ctrl = 0x52020, + .collapse_mask = BIT(3), .pd = { .name = "pcie_0_phy_gdsc", }, @@ -3016,6 +3020,8 @@ static struct gdsc pcie_0_phy_gdsc = { static struct gdsc pcie_1_gdsc = { .gdscr = 0x8d004, + .collapse_ctrl = 0x52020, + .collapse_mask = BIT(1), .pd = { .name = "pcie_1_gdsc", }, @@ -3025,6 +3031,8 @@ static struct gdsc pcie_1_gdsc = { static struct gdsc pcie_1_phy_gdsc = { .gdscr = 0x8e000, + .collapse_ctrl = 0x52020, + .collapse_mask = BIT(4), .pd = { .name = "pcie_1_phy_gdsc", }, From patchwork Mon Dec 18 16:02:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 755522 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EBDE5D74A for ; Mon, 18 Dec 2023 16:02:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="oyOsffEg" Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-a234205785dso200027466b.0 for ; Mon, 18 Dec 2023 08:02:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702915349; x=1703520149; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=QBViY7jkvTaAJEcKg65WBWL916aXSU5kT38QPvggLYk=; b=oyOsffEgMf7yOSdABgPrdag8b5JyWuSClCL9lH+3oNFtknErE0uc/qIRVCpAonVZDC XQHQlYHfRYcyWXQ2UA44AfTjBJpPX/lMhNOtP89qsJzhqbl/cglGU5f6DJNKwvG23ocQ VWwchgo/FDJ/6J0LYdLkCezAdqoN2Wt0tS29grFnvF2CinG9KJ3KZPi6VC2CR4rmuaJH cjsfYzFUwBLwKvoqQWHwwl8joerIqWKa//Aec/Ssd3WAUK4QyuWyjrdNc3AnNlZb5u23 hQ2bMhxmM2ImLCkC1a5gjpHsHmeRpeUuF4Huv9ONwWlrMzfT0PyjTgS1k1Ajh3yz3uDU b3bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702915349; x=1703520149; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QBViY7jkvTaAJEcKg65WBWL916aXSU5kT38QPvggLYk=; b=fMSq+4kq+cp4Sb/RPmuA0wqw7G1UR08LuOvNEgZEGwH4/XyDEJbitmcSS0MfrWbNbI 8K9nz7pL5ilT+yRRev+1G27qclepI0POUgVWW9xcG37XVP64fwDcKlGZvMuyyen/bfna nfYWrPEzp/4cmGBkrn70tCIhiQaI++yqOu+lfGy38XrOm5mrq6LkYRRWKztOiA50xags LFdv1DZzH0TWFszsNjcTBAXHEqiOuVAXDepSfJK6VpY5TVwjSqKbdm3j+aqkNZv+yuOv R3W7hT94sihO+Ho8hJUZbCweEaXalbxrwkpAFTQOtClmpqu+dpNJKzda25JrVxL3QBTt gnWQ== X-Gm-Message-State: AOJu0YxFDJXSO5qhINH1ZAROFYBE/Nfz2yudRnWdrvFJobMVAcORcD8A UEV6H0zd3pD0DAYGsIfKCd2ZNQ== X-Google-Smtp-Source: AGHT+IFJhWEmmbDEyESgZdxhz1O6Q1Sy/KUK84afGg33sfnlZYQApXmygM5ynm4QiKEZen7vys93Tg== X-Received: by 2002:a17:906:5d:b0:a23:463c:16ba with SMTP id 29-20020a170906005d00b00a23463c16bamr862120ejg.167.1702915349290; Mon, 18 Dec 2023 08:02:29 -0800 (PST) Received: from [10.167.154.1] (178235179137.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.137]) by smtp.gmail.com with ESMTPSA id ts7-20020a170907c5c700b00a1dd58874b8sm14260693ejc.119.2023.12.18.08.02.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 08:02:29 -0800 (PST) From: Konrad Dybcio Date: Mon, 18 Dec 2023 17:02:07 +0100 Subject: [PATCH 06/12] clk: qcom: gcc-sm8550: Mark RCGs shared where applicable Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231218-topic-8550_fixes-v1-6-ce1272d77540@linaro.org> References: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> In-Reply-To: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> To: Bjorn Andersson , Georgi Djakov , Abel Vesa , Michael Turquette , Stephen Boyd , Taniya Das , Jagadeesh Kona , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sai Prakash Ranjan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1702915332; l=12984; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=kxYppAupL1OW96Z1TBPMeVxO9s3GwWa69r4L43R8nGc=; b=X71IQrJiv8y995lHqBIDbRqHyxnH/WWyuznsnK11/1VAy3ZGGt3t+lScswtZNKgM7MboTn+1Z e/0BAnHIGdLCEThN6NNP1fEDTr98mjEFI/G1cz2k+mmC/Hpdye+Rh7d X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The vast majority of shared RCGs were not marked as such. Fix it. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm8550.c | 86 +++++++++++++++++++++---------------------- 1 file changed, 43 insertions(+), 43 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index 73bda0d03aa7..b883dffe5f7a 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -401,7 +401,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -416,7 +416,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -431,7 +431,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { .parent_data = gcc_parent_data_1, .num_parents = ARRAY_SIZE(gcc_parent_data_1), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -451,7 +451,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -471,7 +471,7 @@ static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -486,7 +486,7 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -501,7 +501,7 @@ static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -521,7 +521,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -536,7 +536,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -551,7 +551,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -566,7 +566,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -581,7 +581,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -596,7 +596,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -611,7 +611,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -626,7 +626,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -641,7 +641,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -656,7 +656,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -671,7 +671,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -700,7 +700,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { @@ -717,7 +717,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { @@ -750,7 +750,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { @@ -767,7 +767,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { @@ -784,7 +784,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { @@ -801,7 +801,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { @@ -818,7 +818,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { @@ -835,7 +835,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { @@ -852,7 +852,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { @@ -869,7 +869,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { @@ -886,7 +886,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { @@ -903,7 +903,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { @@ -920,7 +920,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { @@ -937,7 +937,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { @@ -975,7 +975,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { .parent_data = gcc_parent_data_8, .num_parents = ARRAY_SIZE(gcc_parent_data_8), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { @@ -992,7 +992,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = { @@ -1025,7 +1025,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .parent_data = gcc_parent_data_9, .num_parents = ARRAY_SIZE(gcc_parent_data_9), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1048,7 +1048,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1071,7 +1071,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1093,7 +1093,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { .parent_data = gcc_parent_data_3, .num_parents = ARRAY_SIZE(gcc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1114,7 +1114,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { .parent_data = gcc_parent_data_4, .num_parents = ARRAY_SIZE(gcc_parent_data_4), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1136,7 +1136,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1159,7 +1159,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1174,7 +1174,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { .parent_data = gcc_parent_data_0, .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1189,7 +1189,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { .parent_data = gcc_parent_data_2, .num_parents = ARRAY_SIZE(gcc_parent_data_2), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; From patchwork Mon Dec 18 16:02:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 757215 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 152C25D759 for ; Mon, 18 Dec 2023 16:02:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Q7zJpdoY" Received: by mail-ed1-f45.google.com with SMTP id 4fb4d7f45d1cf-55193d5e8cdso3841856a12.1 for ; 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[178.235.179.137]) by smtp.gmail.com with ESMTPSA id ts7-20020a170907c5c700b00a1dd58874b8sm14260693ejc.119.2023.12.18.08.02.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 08:02:31 -0800 (PST) From: Konrad Dybcio Date: Mon, 18 Dec 2023 17:02:08 +0100 Subject: [PATCH 07/12] clk: qcom: gpucc-sm8550: Update GPU PLL settings Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231218-topic-8550_fixes-v1-7-ce1272d77540@linaro.org> References: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> In-Reply-To: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> To: Bjorn Andersson , Georgi Djakov , Abel Vesa , Michael Turquette , Stephen Boyd , Taniya Das , Jagadeesh Kona , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sai Prakash Ranjan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1702915332; l=976; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=q/YWhe5rzcUAmIFXqSmcshP5410IbnXzatBPzE34Z1U=; b=ls2LT4NdvgbEWszZcqguVQIutVml18NyUafbddPc5km0Vmg6JEz8pXhPg5v3vdlrhMV2bzNZ/ 1scuV2kyQ2EBMTI8FvVLZ+iqp4nvlng2slRNpPC6i/8ziBxfIL8satV X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The settings in the driver seem to have been taken from an older release. Update them to match the latest values. Fixes: bfae40744b33 ("clk: qcom: gpucc-sm8550: Add support for graphics clock controller") Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm8550.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm8550.c b/drivers/clk/qcom/gpucc-sm8550.c index 420dcb27b47d..2fa8673424d7 100644 --- a/drivers/clk/qcom/gpucc-sm8550.c +++ b/drivers/clk/qcom/gpucc-sm8550.c @@ -35,12 +35,12 @@ enum { }; static const struct pll_vco lucid_ole_vco[] = { - { 249600000, 2300000000, 0 }, + { 249600000, 2000000000, 0 }, }; static const struct alpha_pll_config gpu_cc_pll0_config = { - .l = 0x0d, - .alpha = 0x0, + .l = 0x1e, + .alpha = 0xbaaa, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82aa299c, From patchwork Mon Dec 18 16:02:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 755521 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7522C71459 for ; Mon, 18 Dec 2023 16:02:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ehDi5kpt" Received: by mail-ej1-f51.google.com with SMTP id a640c23a62f3a-a236de428a5so18785766b.0 for ; Mon, 18 Dec 2023 08:02:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702915354; x=1703520154; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Tmy1351WhysY14MPIZnZg7MaXR9rNDaM54jz8n5nT/I=; b=ehDi5kptvKU54+C0MdUUWDTfvdiXmcjw++NvWgrg4696yxZ4A+FRzQp04CN9xNVGW7 lJg9lPMFcIBwsNabmPqMgu/LGbceAXAERljJ423p6tl+8j2NuCGz3SLy172/vBfLeoly hgQ5p8UKOczi1bqvPCebvMb/Wp3y0eerCIXMKpHbTkW7ZYn5LTsvLcWbq19/8L5p6q03 c3wZc3NBcVY0dfZMsdyMnFPVkwWZbKpsZOPZPu0xELjz9RMWCxFrJxZyLV/v96gl/3dT rMMpTeVkJMQGSfgr255nmLXl6L3gNynHz0u8Rd9Oj52bxKkBFn64BIXHtYGNGCrAkjyT bI1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702915354; x=1703520154; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tmy1351WhysY14MPIZnZg7MaXR9rNDaM54jz8n5nT/I=; b=bLIXP2iLLSOrK1TSj4Y3+fb06iJODOmBHBhnHsCVA8t6yZPO1w/87y+TeG8onsrFfT UG/o7q+u+HCaYTRYZQf40iivx8ePtR/reVuVVMicU10SFN1SA/NrbmOX5KY1Pgys7oYU OId+HETQJmghEwB81FG6l0LW/KO8P0fQGutvqA7zPA57i+c5Dyd8wziom8MgiksVQsD7 3TpXCtRNiSrVoVgdbPejciJ/CI8kBqQukfeMTYMVk1QEcWTwW8EYRSHFi2IfFT6HAL2o JYMBFtXM/8In28cipLTAI4Vz0esum60CdAdSu6SoCkQViTWU+146tGQ7ur1BWwfQgfxN JTSA== X-Gm-Message-State: AOJu0YwaiFd1fSm4s9slYI35wf7DY15yZThRT/zVddSmXgyhUzirOvsi TWidKliDPaG3g2ArSLlMuvEENw== X-Google-Smtp-Source: AGHT+IGcqpIXK1SZf3aJgxS6kUFd914bHdfsLtWun9fItQQmOUlIgZFtTPDZNi1nFZH7NOFT4IlTaw== X-Received: by 2002:a17:907:c999:b0:a23:49f7:a132 with SMTP id uj25-20020a170907c99900b00a2349f7a132mr1210916ejc.44.1702915353771; Mon, 18 Dec 2023 08:02:33 -0800 (PST) Received: from [10.167.154.1] (178235179137.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.137]) by smtp.gmail.com with ESMTPSA id ts7-20020a170907c5c700b00a1dd58874b8sm14260693ejc.119.2023.12.18.08.02.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 08:02:33 -0800 (PST) From: Konrad Dybcio Date: Mon, 18 Dec 2023 17:02:09 +0100 Subject: [PATCH 08/12] clk: qcom: dispcc-sm8550: Update disp PLL settings Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231218-topic-8550_fixes-v1-8-ce1272d77540@linaro.org> References: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> In-Reply-To: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> To: Bjorn Andersson , Georgi Djakov , Abel Vesa , Michael Turquette , Stephen Boyd , Taniya Das , Jagadeesh Kona , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sai Prakash Ranjan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1702915332; l=1329; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=5tbiuHAzVzq42DxvRzRnmc/Zm2HLv3YyRRdXfzE5DAk=; b=Ml2SoneCW7eoztQueMMtroWW6FEuyqSxKRQRSzXBES8NAlXPnbPsg4hQNwTHWSOgfF5q8Cj0e USMLm3l023jAJ13fBcautlg7huj/piY49NzF84kNnnyz5Mt5qBm41hx X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The settings in the driver seem to have been taken from an older release. Update them to match the latest values. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/dispcc-sm8550.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c index aefa19f3c2c5..0b8f0904b339 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -81,6 +81,10 @@ static const struct alpha_pll_config disp_cc_pll0_config = { .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000000, .user_ctl_hi_val = 0x00000005, }; @@ -108,6 +112,10 @@ static const struct alpha_pll_config disp_cc_pll1_config = { .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000000, .user_ctl_hi_val = 0x00000005, }; From patchwork Mon Dec 18 16:02:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 755520 Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E37F72046 for ; Mon, 18 Dec 2023 16:02:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="jdTY6RjT" Received: by mail-ed1-f48.google.com with SMTP id 4fb4d7f45d1cf-552fba34d69so2563685a12.3 for ; Mon, 18 Dec 2023 08:02:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702915356; x=1703520156; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3Lr4/3tTtpC0alkBdqQYjbL4EKBHF7J4Yz0/1JYgEAE=; b=jdTY6RjThlBQtv9E08EZFnofWPWgetFsWJSyoKs3YOpq/jCxBWtJ5lKAjvJuY1ZDRO 3Au4tDyL6yjysBY9WhDPrFG1d3yg3tnmLVDQwYFekziVagenRM1WgSe8+OlOo0UwBjas ZK5X7r3+TITJ7v8S57h3jeaqo0cuKStBUaUuc9OmmD2YSxtm+WPW0F/UhgX6gJqRf2xB VyInpPSeE1uY+zVSLwzoPVQPH3NJUHjJvzA6qnadP37dimgSxwg1+8cTYYLW7PqoIStN 5D4blLrO8YKpZhHBwlUrbYxJM335Y0sKgzn4O1I9CB1xEL5rXn1u9GIslKyLjep9AsXp sVxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702915356; x=1703520156; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3Lr4/3tTtpC0alkBdqQYjbL4EKBHF7J4Yz0/1JYgEAE=; b=prR8+Rkh+/qoj178jdRDgnmXSTQ0tA3uSBdUOMUWtX0LSyE5bzgP9j7kLK2t/+RJe5 IJFjwSGtgl6/Ik+5QjdoF8OCb6rsl2T8aBmxxQIwCdWV3lmT706S2ITRrvwqfmePe9uq zF/lcVnvnisufvCcAOEOgzFWnjD9EWmsy8vpsAjmVFWYAO+3qtImY0AIyb8LTervycVB Bi+i3gvt+88Am4f9+bG+M2hBKeFZ7WZAjD/xYqjFXW7e7lKQoOaZ8F5bvwNgWfN3CZH2 b1H7O8DNSDWI1oqS/oVWQbVnQsvx7iqzyE1ivHpV8XFifByHh7l9ka4BG7K8bCxh3CQx QuPw== X-Gm-Message-State: AOJu0Yw7E5WBVQaWkjpYit+6fly/IPcIHXF3OmujSzpn+jSbmDlWxBpV +uFcJ1Xig+D1tDf2AlSssjJpHQ== X-Google-Smtp-Source: AGHT+IFWH9gBYMv4BN//69QHcLFPlkr31TmGuhi3zUoMx4/hQzAxGzdzksTbClDwmhXy2r5Gqc30WQ== X-Received: by 2002:a17:906:738b:b0:a23:53f8:c956 with SMTP id f11-20020a170906738b00b00a2353f8c956mr1064827ejl.42.1702915356251; Mon, 18 Dec 2023 08:02:36 -0800 (PST) Received: from [10.167.154.1] (178235179137.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.137]) by smtp.gmail.com with ESMTPSA id ts7-20020a170907c5c700b00a1dd58874b8sm14260693ejc.119.2023.12.18.08.02.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 08:02:35 -0800 (PST) From: Konrad Dybcio Date: Mon, 18 Dec 2023 17:02:10 +0100 Subject: [PATCH 09/12] clk: qcom: dispcc-sm8550: Use the correct PLL configuration function Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231218-topic-8550_fixes-v1-9-ce1272d77540@linaro.org> References: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> In-Reply-To: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> To: Bjorn Andersson , Georgi Djakov , Abel Vesa , Michael Turquette , Stephen Boyd , Taniya Das , Jagadeesh Kona , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sai Prakash Ranjan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1702915332; l=1105; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=BezfhwpPbu2OXB/cs1cE9HqGLwlCqC3inKfbOziVm0c=; b=lFwlgq/K3vI5bmFpk3rOzJs15h2tiwVlS/Qhbp0zr3302E4+6rk62164CD/vcWTej6KDxsuRc NkjQvQgPr8UCQCrnXyN2VgSMEFYQttKkre1M2BcsJXZ/gUoaYd9Mqwm X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= To ensure that all fields (particularly CAL_L and CAL_L_RINGOSC) are filled properly, use the correct prepare function for OLE PLLs. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/dispcc-sm8550.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c index 0b8f0904b339..f96d8b81fd9a 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -1774,8 +1774,8 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev) goto err_put_rpm; } - clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); - clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); + clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); + clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); /* Enable clock gating for MDP clocks */ regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); From patchwork Mon Dec 18 16:02:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 757214 Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87CD37346F for ; Mon, 18 Dec 2023 16:02:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="rbrVfNMI" Received: by mail-ed1-f51.google.com with SMTP id 4fb4d7f45d1cf-54f4f7d082cso4001662a12.0 for ; Mon, 18 Dec 2023 08:02:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702915359; x=1703520159; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=68epx+8M61EWdIAHlB2jaH+zZGGljEe5sZXZT/JYXwQ=; b=rbrVfNMIVyQlidrVqwAk7nr9mwdeNMl15IDMnUl0bZapRcmb7Pg5Rgjud5VjdbdbH8 SNbKrPrbC7A3FM0mAiGTbNs8TVqA7Z80INlliPwcjlvCqsyuuiqZeU7momCtL0wWRnDE 9cOZPDpG09fjUsQl20sehykDCakZ8AkD1M5dTONXofU9YESDWtKtMOoM6UKwEURWnlXN ayc1q8oPsE0JSA2YOK4J1rFaGi6tf1qxJA1GEasE89yO1xFBJIC+/tr/s/UsBvohmAeh 7LYr+NOer3bgbMAs81d503Xor0fETV7ftu0uf/PdI2TFKPi5DUVOSTLHNGHwH7epx/my QAHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702915359; x=1703520159; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=68epx+8M61EWdIAHlB2jaH+zZGGljEe5sZXZT/JYXwQ=; b=LSn1eIvb+TX9mErO/pWNaJYN6Wdp/7IXS2gwQqWupne0LnXl+4PmO/D2AUbzJeYhce JXw8xocHRnu+5romG50i0WzHrs1sSPDjGGuN/WD8s4gJro5ZIrmwQvIu58s2oEKYwoIG guM3AUMRZdhkOkYyeQ52EdL6+cnSX0nXHyCcHDqbyZmANQXQd0Ej5FOIWWmHuVWgcq1g halwgOGt2mfy8hAN+b365MVT8h9wgiFLjUelnPeNM1jaHUTQhF/FIYvX7Es+XmA/brZg R1kR2KQVdg98TREPpJVdbKjkSnbfy/HpKDScnqndzD31F/06AWKr5w8qM4ViY7SjITCl 30rw== X-Gm-Message-State: AOJu0Yw8b/BfVcaASTST/4xtV1mJAo5OY82MKC2IpNWoBiPBEDA61ZUK 2HlfXsWjmmivRY54eQjjyxLcSw== X-Google-Smtp-Source: AGHT+IEbONXPDpir1TjSdNrOy9M3GrwpvDOaTnBEqRBp7US4qzM/6nyUiuY5QQZJYs2vuBH4FIZOvQ== X-Received: by 2002:a17:906:208a:b0:a23:32bd:d166 with SMTP id 10-20020a170906208a00b00a2332bdd166mr1900324ejq.48.1702915358698; Mon, 18 Dec 2023 08:02:38 -0800 (PST) Received: from [10.167.154.1] (178235179137.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.137]) by smtp.gmail.com with ESMTPSA id ts7-20020a170907c5c700b00a1dd58874b8sm14260693ejc.119.2023.12.18.08.02.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 08:02:38 -0800 (PST) From: Konrad Dybcio Date: Mon, 18 Dec 2023 17:02:11 +0100 Subject: [PATCH 10/12] arm64: dts: qcom: sm8550: Switch UFS from opp-table-hz to opp-v2 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231218-topic-8550_fixes-v1-10-ce1272d77540@linaro.org> References: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> In-Reply-To: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> To: Bjorn Andersson , Georgi Djakov , Abel Vesa , Michael Turquette , Stephen Boyd , Taniya Das , Jagadeesh Kona , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sai Prakash Ranjan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1702915332; l=2459; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=wNcQ3JT7sEMsU1w+gTv+f8IeE+qRg1HUjZAHm9x8uUo=; b=Tn2VqR3OuQzlYgOYCLyuUJ5lFuNNXNnfMBUCl1Uvy4X11c3bfrVFS75n0/96CCvsEOnj0ozi0 3fnv6kuQZRcBPa1nVbVDDkVfSgl9/d1C2N4x3cC2gCHBoI6SlSHtYNq X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Now that the non-legacy form of OPP is supported within the UFS driver, go ahead and switch to it, adding support for more intermediate freq/power states. In doing so, add the CX RPMhPD under GCC to make sure at least some of the power state requirements are *actually* propagated up the stack. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 50 +++++++++++++++++++++++++++++------- 1 file changed, 41 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index d707d15cea5b..d6edd54f3ad3 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1930,6 +1930,7 @@ ufs_mem_hc: ufs@1d84000 { iommus = <&apps_smmu 0x60 0x0>; dma-coherent; + operating-points-v2 = <&ufs_opp_table>; interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; @@ -1950,18 +1951,49 @@ ufs_mem_hc: ufs@1d84000 { <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <100000000 403000000>, - <0 0>, - <0 0>, - <0 0>; qcom,ice = <&ice>; status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <300000000>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; ice: crypto@1d88000 { From patchwork Mon Dec 18 16:02:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 757213 Received: from mail-lj1-f179.google.com (mail-lj1-f179.google.com [209.85.208.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6391074097 for ; Mon, 18 Dec 2023 16:02:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Wt/CvXe2" Received: by mail-lj1-f179.google.com with SMTP id 38308e7fff4ca-2cc4029dc6eso39108291fa.1 for ; Mon, 18 Dec 2023 08:02:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702915361; x=1703520161; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0legLdqA3HMiABFAk1IEGD+aB3bRG1lPUakJuX6NHbk=; b=Wt/CvXe2YjAuwwoZhsuSGlIXKA2Pfm/6sP5w+EkzUGqIfjz/80Wi1zzlcgh/knNUbH bT9u+0hIa3Ko4+AFQZkQ69Qi9H+vHBkpxfucQt//KRruG+Vu5qjuauLFEi5wlRZF7vDW wJAd27F8u01K3LJmQBzSIhuS69MIH8r8WSPXmVmHTESOuy0Hvuj2V7/FIC4yxTTORA5W 95/VLjoyld4SmuyC2vLtxBH9RqyhBcrQOJ3IIHYbjDpOfEj56X7BY58IGhi8a5XxS7Ko Vql3H4KA0KJOjBS0cKErGsRgOpNqdv8FyafohOFoOe1fk5NfXF9XLsXCn3XzjLmrnXuy pNeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702915361; x=1703520161; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0legLdqA3HMiABFAk1IEGD+aB3bRG1lPUakJuX6NHbk=; b=DLR5CA3lspcvd3VAcVt9dZeQcV7SzhCzpZ4QyLBssJ2ixNUIcIGoaBv2yiSQYjsoi6 x0f729DlFpRf32OzEgZAKxFG+4qPPhXqebXznaj2iRRKFxmgTdWtnHTj2Q7fP9uJEzt7 6AHxh+qPhjPJvIQ2YFxF6SPt2dQLvWOfkjtl0mPyX/c3/5aVRe9hWKHYs7l3Yvt9EMAk O9VCPyl09Ta9yiqDdG5X0o1qcMDF+YvJdMMgH2i1Owi9hoTg+Vrh/boEEsxqbMkyyj2H ROV9sQ48UPRACs3dPCDxfHd0lO5gI85LHvMfGrzu5Sxtc59ABP1nxL1WXEoUzpxrdqAj +jHQ== X-Gm-Message-State: AOJu0YzACG6iVCtFWeY5mwo3BEvNU1IWNGApnQ5ZSOkkpcTqysQaWroX EIGNER9DLEqjxbJmccPKjDvrZg== X-Google-Smtp-Source: AGHT+IFFsASXToWE6su/3JQTF9uVLLNzIiYmXLfRUuiPzzehkLvaC5Xk5Px32C4F5KPXt8oF5wRXDg== X-Received: by 2002:a2e:b8c9:0:b0:2cb:2bd7:38fc with SMTP id s9-20020a2eb8c9000000b002cb2bd738fcmr8080147ljp.15.1702915361417; Mon, 18 Dec 2023 08:02:41 -0800 (PST) Received: from [10.167.154.1] (178235179137.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.137]) by smtp.gmail.com with ESMTPSA id ts7-20020a170907c5c700b00a1dd58874b8sm14260693ejc.119.2023.12.18.08.02.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 08:02:41 -0800 (PST) From: Konrad Dybcio Date: Mon, 18 Dec 2023 17:02:12 +0100 Subject: [PATCH 11/12] arm64: dts: qcom: sm8550: Separate out X3 idle state Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231218-topic-8550_fixes-v1-11-ce1272d77540@linaro.org> References: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> In-Reply-To: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> To: Bjorn Andersson , Georgi Djakov , Abel Vesa , Michael Turquette , Stephen Boyd , Taniya Das , Jagadeesh Kona , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sai Prakash Ranjan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1702915332; l=1364; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=PL04FEARqu9VLzK2p2tNsar8c78v1Xz6Zm6Z8pmFlvw=; b=cOfL7ZgcpBQGzjkcau2Mz4guvK26PJFAx43Nzowi7aW94eAPfCu383h/id6jzhAQmgNKwGNws Ob1bijCWbBlAINYEcbhIzOK4F6UG2ZTv6+OCGx/DK6zbrNfd5GPwige X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The X3 core has different entry/exit/residency time requirements than the big cluster. Denote them to stop confusing the scheduler. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index d6edd54f3ad3..5143a08c4867 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -300,6 +300,16 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { min-residency-us = <4791>; local-timer-stop; }; + + PRIME_CPU_SLEEP_0: cpu-sleep-2-0 { + compatible = "arm,idle-state"; + idle-state-name = "goldplus-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <500>; + exit-latency-us = <1350>; + min-residency-us = <7480>; + local-timer-stop; + }; }; domain-idle-states { @@ -401,7 +411,7 @@ CPU_PD6: power-domain-cpu6 { CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; + domain-idle-states = <&PRIME_CPU_SLEEP_0>; }; CLUSTER_PD: power-domain-cluster { From patchwork Mon Dec 18 16:02:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 755519 Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8139C74E0B for ; Mon, 18 Dec 2023 16:02:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="T1jGvhhF" Received: by mail-ed1-f46.google.com with SMTP id 4fb4d7f45d1cf-54c7744a93fso4079231a12.2 for ; Mon, 18 Dec 2023 08:02:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702915364; x=1703520164; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=7vqnaVfXUc3+Cw3ab8YklVZAFoD7TS2H8et3g6n/n1M=; b=T1jGvhhFYMLI01YBjJiXWfbpFy+l/hCvjCQyspUxwGoQqV2yBVUyFl931zZNuxQk2l 4qos0t0OO0O2YLKXm+YKz1xT2vr8ySTQ1tW8VRqDG1AVoJAKy27PLToAXUreprJvbNvO kik/DfDnSSdkpSMZwce0Qvt62V6UAKFXXbUiW/cLLfAaNfK9MaWjBEY4RVP0lCHdgZEF j/l7nBfK2qQt6s2ok34zre2deoCG2wOcEl7fB/9HUYRWxjbAaxH50SgowiVuGpcvm8hL G+yLJcEkbMGf3Gxg7L0ZejRoneqyqHJQ0Lvlnf0zzm/gHXhFw35aPqxiWNGUSq7hYcIT ZxxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702915364; x=1703520164; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7vqnaVfXUc3+Cw3ab8YklVZAFoD7TS2H8et3g6n/n1M=; b=XlZzpDlAR+hHlkP1FxQF7sit+azQvP5uEXIXmoqo8KBSOH8yOjbzU/sidCJ0M2Lg65 Bkq2vQoUwi6sASgIMf2DqwGerZD1Y+/7WLagS6GqgCmLyZOUoohOpwuJ2oM/SB2fnYwD YBRQwNpXBTwPeSX4n+UpBxfHKzvZqgJbaVj5oBAvPOthRntoZxJWgvZbvvJzAw17535r PbuBuxu4VrvBQJ6MVQyDetGd4+/e1huH7A7n6oqstxf96w2ljH5aS54zvZvY46KF+UvX V2Zr/YPk1JFplGC8NENwwnAKHbe+hQ3K1j9zGMyfqXv0wHfsRL+AyMzNYQekBvY8+3NR vrLA== X-Gm-Message-State: AOJu0YwV4fcQvrKh1MxtVi8ECox2w9sbQ8iJ2ZukD9nnz8JZDVE7/DmX 6g3i20uEn3BBu1eaWLfpjv6PPw== X-Google-Smtp-Source: AGHT+IGNnRKVBXAyleisarX/8QiSexrXfrpnMlqCDzp/Inh+l4LMc8nVvkgqQc+KX35OdfJEHdb1Dw== X-Received: by 2002:a17:906:5c:b0:a23:660:ec5c with SMTP id 28-20020a170906005c00b00a230660ec5cmr3564518ejg.40.1702915363917; Mon, 18 Dec 2023 08:02:43 -0800 (PST) Received: from [10.167.154.1] (178235179137.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.137]) by smtp.gmail.com with ESMTPSA id ts7-20020a170907c5c700b00a1dd58874b8sm14260693ejc.119.2023.12.18.08.02.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 08:02:43 -0800 (PST) From: Konrad Dybcio Date: Mon, 18 Dec 2023 17:02:13 +0100 Subject: [PATCH 12/12] arm64: dts: qcom: sm8550: Update idle state time requirements Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231218-topic-8550_fixes-v1-12-ce1272d77540@linaro.org> References: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> In-Reply-To: <20231218-topic-8550_fixes-v1-0-ce1272d77540@linaro.org> To: Bjorn Andersson , Georgi Djakov , Abel Vesa , Michael Turquette , Stephen Boyd , Taniya Das , Jagadeesh Kona , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sai Prakash Ranjan Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1702915332; l=2164; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=9Z88FW0hsRmPlBm1BVUnqIFZHzLISLnQdKvDWpIJwf4=; b=ppRSM6dTlJsxBT50Gv31qfqBnfv3jlmcUCdVlaNY6XDUuq5HjF8k9Ls7YTXHH1MkJHv57Sstg PWmaijmoN+VBlj0oEm+XgddIIkdtdoLL2e+n8pKTbtpIlbzHcxdZSUG X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The idle state entry/exit/residency times differ from what shipped on production devices, mostly being overly optimistic in entry times and overly pessimistic in minimal residency times. Align them with downstream sources. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 5143a08c4867..6a192fb41f84 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -285,9 +285,9 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { compatible = "arm,idle-state"; idle-state-name = "silver-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <800>; + entry-latency-us = <550>; exit-latency-us = <750>; - min-residency-us = <4090>; + min-residency-us = <6700>; local-timer-stop; }; @@ -296,8 +296,8 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { idle-state-name = "gold-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; entry-latency-us = <600>; - exit-latency-us = <1550>; - min-residency-us = <4791>; + exit-latency-us = <1300>; + min-residency-us = <8136>; local-timer-stop; }; @@ -316,17 +316,17 @@ domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x41000044>; - entry-latency-us = <1050>; - exit-latency-us = <2500>; - min-residency-us = <5309>; + entry-latency-us = <750>; + exit-latency-us = <2350>; + min-residency-us = <9144>; }; CLUSTER_SLEEP_1: cluster-sleep-1 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x4100c344>; - entry-latency-us = <2700>; - exit-latency-us = <3500>; - min-residency-us = <13959>; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; }; }; };