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[73.71.176.3]) by smtp.gmail.com with ESMTPSA id 131sm6493221pge.37.2019.08.30.22.23.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2019 22:23:25 -0700 (PDT) From: Khem Raj To: openembedded-core@lists.openembedded.org Date: Fri, 30 Aug 2019 22:23:11 -0700 Message-Id: <20190831052314.19974-1-raj.khem@gmail.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 Subject: [OE-core] [PATCH 1/4] powerpc-tunes: Introduce bigendian tune X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: openembedded-core-bounces@lists.openembedded.org Errors-To: openembedded-core-bounces@lists.openembedded.org This helps in defining LE tunes and at the same time specifies endianness on compiler cmdline clearly, clang e.g. defaults to little-endian always, so unless specified with -mbig-endian won't compile the code right Signed-off-by: Khem Raj --- .../machine/include/powerpc/arch-powerpc.inc | 22 ++++++++++++++++--- .../include/powerpc/arch-powerpc64.inc | 10 +++++++-- meta/conf/machine/include/tune-power5.inc | 4 ++-- meta/conf/machine/include/tune-power6.inc | 4 ++-- meta/conf/machine/include/tune-power7.inc | 4 ++-- meta/conf/machine/include/tune-ppc476.inc | 2 +- meta/conf/machine/include/tune-ppc603e.inc | 2 +- meta/conf/machine/include/tune-ppc7400.inc | 2 +- meta/conf/machine/include/tune-ppce300c2.inc | 2 +- meta/conf/machine/include/tune-ppce500.inc | 2 +- meta/conf/machine/include/tune-ppce500mc.inc | 2 +- meta/conf/machine/include/tune-ppce500v2.inc | 2 +- meta/conf/machine/include/tune-ppce5500.inc | 4 ++-- meta/conf/machine/include/tune-ppce6500.inc | 4 ++-- 14 files changed, 44 insertions(+), 22 deletions(-) -- 2.23.0 -- _______________________________________________ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core diff --git a/meta/conf/machine/include/powerpc/arch-powerpc.inc b/meta/conf/machine/include/powerpc/arch-powerpc.inc index 9cf6b88fd1..8c0c943044 100644 --- a/meta/conf/machine/include/powerpc/arch-powerpc.inc +++ b/meta/conf/machine/include/powerpc/arch-powerpc.inc @@ -8,6 +8,11 @@ DEFAULTTUNE ?= "powerpc" TUNE_PKGARCH = "${TUNE_PKGARCH_tune-${DEFAULTTUNE}}" ABIEXTENSION ?= "" +# Endian +TUNEVALID[bigendian] = "Use PowerPC Big Endian" + +TUNE_CCARGS .= "${@bb.utils.contains("TUNE_FEATURES", "bigendian", " -mbig-endian", " -mlittle-endian", d)}" + TUNEVALID[m32] = "Power ELF32 standard ABI" TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'm32', ' -m32', '', d)}" TUNE_ARCH .= "${@bb.utils.contains('TUNE_FEATURES', 'm32', 'powerpc', '', d)}" @@ -22,13 +27,24 @@ TARGET_FPU .= "${@bb.utils.contains('TUNE_FEATURES', 'fpu-soft', 'soft', '', d)} TUNEVALID[altivec] = "Altivec" # Basic tune definitions -AVAILTUNES += "powerpc powerpc-nf" -TUNE_FEATURES_tune-powerpc-nf = "m32 fpu-soft" +AVAILTUNES += "powerpc powerpc-nf powerpcle powerpcle-nf" + +TUNE_FEATURES_tune-powerpc-nf = "m32 fpu-soft bigendian" BASE_LIB_tune-powerpc-nf = "lib" TUNE_PKGARCH_tune-powerpc-nf = "powerpc-nf" PACKAGE_EXTRA_ARCHS_tune-powerpc-nf = "powerpc-nf" -TUNE_FEATURES_tune-powerpc = "m32 fpu-hard" +TUNE_FEATURES_tune-powerpc = "m32 fpu-hard bigendian" BASE_LIB_tune-powerpc = "lib" TUNE_PKGARCH_tune-powerpc = "powerpc" PACKAGE_EXTRA_ARCHS_tune-powerpc = "powerpc" + +TUNE_FEATURES_tune-powerpcle-nf = "m32 fpu-soft" +BASE_LIB_tune-powerpcle-nf = "lib" +TUNE_PKGARCH_tune-powerpcle-nf = "powerpcle-nf" +PACKAGE_EXTRA_ARCHS_tune-powerpcle-nf = "powerpcle-nf" + +TUNE_FEATURES_tune-powerpcle = "m32 fpu-hard" +BASE_LIB_tune-powerpcle = "lib" +TUNE_PKGARCH_tune-powerpcle = "powerpcle" +PACKAGE_EXTRA_ARCHS_tune-powerpcle = "powerpcle" diff --git a/meta/conf/machine/include/powerpc/arch-powerpc64.inc b/meta/conf/machine/include/powerpc/arch-powerpc64.inc index d9916d43da..4bc5983087 100644 --- a/meta/conf/machine/include/powerpc/arch-powerpc64.inc +++ b/meta/conf/machine/include/powerpc/arch-powerpc64.inc @@ -13,8 +13,14 @@ TUNE_CCARGS .= "${@['', ' -mabi=elfv2']['libc-musl' in d.getVar('OVERRIDES').spl # user mode qemu doesn't support ppc64 MACHINE_FEATURES_BACKFILL_CONSIDERED_append = " ${@bb.utils.contains('TUNE_FEATURES', 'm64', 'qemu-usermode', '', d)}" -AVAILTUNES += "powerpc64" -TUNE_FEATURES_tune-powerpc64 = "m64 fpu-hard" +AVAILTUNES += "powerpc64 powerpc64le" + +TUNE_FEATURES_tune-powerpc64 = "m64 fpu-hard bigendian" BASE_LIB_tune-powerpc64 = "lib64" TUNE_PKGARCH_tune-powerpc64 = "powerpc64" PACKAGE_EXTRA_ARCHS_tune-powerpc64 = "powerpc64" + +TUNE_FEATURES_tune-powerpc64le = "m64 fpu-hard" +BASE_LIB_tune-powerpc64le = "lib64" +TUNE_PKGARCH_tune-powerpc64le = "powerpc64le" +PACKAGE_EXTRA_ARCHS_tune-powerpc64le = "powerpc64le" diff --git a/meta/conf/machine/include/tune-power5.inc b/meta/conf/machine/include/tune-power5.inc index 39501bd8c5..48c33fb273 100644 --- a/meta/conf/machine/include/tune-power5.inc +++ b/meta/conf/machine/include/tune-power5.inc @@ -6,12 +6,12 @@ TUNEVALID[power5] = "Enable IBM Power5 specific processor optimizations" TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'power5', ' -mcpu=power5', '', d)}" AVAILTUNES += "ppcp5 ppc64p5" -TUNE_FEATURES_tune-ppcp5 = "m32 fpu-hard power5 altivec" +TUNE_FEATURES_tune-ppcp5 = "m32 fpu-hard power5 altivec bigendian" BASE_LIB_tune-ppcp5 = "lib" TUNE_PKGARCH_tune-ppcp5 = "ppcp5" PACKAGE_EXTRA_ARCHS_tune-ppcp5 = "${PACKAGE_EXTRA_ARCHS_tune-powerpc} ppcp5" -TUNE_FEATURES_tune-ppc64p5 = "m64 fpu-hard power5 altivec" +TUNE_FEATURES_tune-ppc64p5 = "m64 fpu-hard power5 altivec bigendian" BASE_LIB_tune-ppc64p5 = "lib64" TUNE_PKGARCH_tune-ppc64p5 = "ppc64p5" PACKAGE_EXTRA_ARCHS_tune-ppc64p5 = "${PACKAGE_EXTRA_ARCHS_tune-powerpc64} ppc64p5" diff --git a/meta/conf/machine/include/tune-power6.inc b/meta/conf/machine/include/tune-power6.inc index 1d5e8ecc26..b708660217 100644 --- a/meta/conf/machine/include/tune-power6.inc +++ b/meta/conf/machine/include/tune-power6.inc @@ -6,12 +6,12 @@ TUNEVALID[power6] = "Enable IBM Power6 specific processor optimizations" TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'power6', ' -mcpu=power6', '', d)}" AVAILTUNES += "ppcp6 ppc64p6" -TUNE_FEATURES_tune-ppcp6 = "m32 fpu-hard power6 altivec" +TUNE_FEATURES_tune-ppcp6 = "m32 fpu-hard power6 altivec bigendian" BASE_LIB_tune-ppcp6 = "lib" TUNE_PKGARCH_tune-ppcp6 = "ppcp6" PACKAGE_EXTRA_ARCHS_tune-ppcp6 = "${PACKAGE_EXTRA_ARCHS_tune-powerpc} ppcp6" -TUNE_FEATURES_tune-ppc64p6 = "m64 fpu-hard power6 altivec" +TUNE_FEATURES_tune-ppc64p6 = "m64 fpu-hard power6 altivec bigendian" BASE_LIB_tune-ppc64p6 = "lib64" TUNE_PKGARCH_tune-ppc64p6 = "ppc64p6" PACKAGE_EXTRA_ARCHS_tune-ppc64p6 = "${PACKAGE_EXTRA_ARCHS_tune-powerpc64} ppc64p6" diff --git a/meta/conf/machine/include/tune-power7.inc b/meta/conf/machine/include/tune-power7.inc index 8f3f037ebb..e976cc0467 100644 --- a/meta/conf/machine/include/tune-power7.inc +++ b/meta/conf/machine/include/tune-power7.inc @@ -6,12 +6,12 @@ TUNEVALID[power7] = "Enable IBM Power7 specific processor optimizations" TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'power7', ' -mcpu=power7', '', d)}" AVAILTUNES += "ppcp7 ppc64p7" -TUNE_FEATURES_tune-ppcp7 = "m32 fpu-hard power7 altivec" +TUNE_FEATURES_tune-ppcp7 = "m32 fpu-hard power7 altivec bigendian" BASE_LIB_tune-ppcp7 = "lib" TUNE_PKGARCH_tune-ppcp7 = "ppcp7" PACKAGE_EXTRA_ARCHS_tune-ppcp7 = "${PACKAGE_EXTRA_ARCHS_tune-powerpc} ppcp7" -TUNE_FEATURES_tune-ppc64p7 = "m64 fpu-hard power7 altivec" +TUNE_FEATURES_tune-ppc64p7 = "m64 fpu-hard power7 altivec bigendian" BASE_LIB_tune-ppc64p7 = "lib64" TUNE_PKGARCH_tune-ppc64p7 = "ppc64p7" PACKAGE_EXTRA_ARCHS_tune-ppc64p7 = "${PACKAGE_EXTRA_ARCHS_tune-powerpc64} ppc64p7" diff --git a/meta/conf/machine/include/tune-ppc476.inc b/meta/conf/machine/include/tune-ppc476.inc index d0011ff213..31eecc435c 100644 --- a/meta/conf/machine/include/tune-ppc476.inc +++ b/meta/conf/machine/include/tune-ppc476.inc @@ -6,7 +6,7 @@ TUNEVALID[ppc476] = "Enable ppc476 specific processor optimizations" TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'ppc476', ' -mcpu=476', '', d)}" AVAILTUNES += "ppc476" -TUNE_FEATURES_tune-ppc476 = "m32 fpu-hard ppc476" +TUNE_FEATURES_tune-ppc476 = "m32 fpu-hard ppc476 bigendian" TUNE_PKGARCH_tune-ppc476 = "ppc476" PACKAGE_EXTRA_ARCHS_tune-ppc476 = "${PACKAGE_EXTRA_ARCHS_tune-powerpc} ppc476" diff --git a/meta/conf/machine/include/tune-ppc603e.inc b/meta/conf/machine/include/tune-ppc603e.inc index 13f60dd067..b110f13870 100644 --- a/meta/conf/machine/include/tune-ppc603e.inc +++ b/meta/conf/machine/include/tune-ppc603e.inc @@ -6,7 +6,7 @@ TUNEVALID[ppc603e] = "Enable ppc603e specific processor optimizations" TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'ppc603e', ' -mcpu=603e', '', d)}" AVAILTUNES += "ppc603e" -TUNE_FEATURES_tune-ppc603e = "m32 fpu-hard ppc603e" +TUNE_FEATURES_tune-ppc603e = "m32 fpu-hard ppc603e bigendian" TUNE_PKGARCH_tune-ppc603e = "ppc603e" PACKAGE_EXTRA_ARCHS_tune-ppc603e = "${PACKAGE_EXTRA_ARCHS_tune-powerpc} ppc603e" diff --git a/meta/conf/machine/include/tune-ppc7400.inc b/meta/conf/machine/include/tune-ppc7400.inc index 425e8bd215..92d902994b 100644 --- a/meta/conf/machine/include/tune-ppc7400.inc +++ b/meta/conf/machine/include/tune-ppc7400.inc @@ -6,7 +6,7 @@ TUNEVALID[ppc7400] = "Enable ppc7400 specific processor optimizations" TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'ppc7400', ' -mcpu=7400 -mno-spe', '', d)}" AVAILTUNES += "ppc7400" -TUNE_FEATURES_tune-ppc7400 = "m32 fpu-hard ppc7400 altivec" +TUNE_FEATURES_tune-ppc7400 = "m32 fpu-hard ppc7400 altivec bigendian" TUNE_PKGARCH_tune-ppc7400 = "ppc7400" PACKAGE_EXTRA_ARCHS_tune-ppc7400 = "${PACKAGE_EXTRA_ARCHS_tune-powerpc} ppc7400" diff --git a/meta/conf/machine/include/tune-ppce300c2.inc b/meta/conf/machine/include/tune-ppce300c2.inc index af21f601a8..6adeb4bdec 100644 --- a/meta/conf/machine/include/tune-ppce300c2.inc +++ b/meta/conf/machine/include/tune-ppce300c2.inc @@ -6,6 +6,6 @@ TUNEVALID[ppce300c2] = "Enable ppce300c2 specific processor optimizations" TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'ppce300c2', ' -mcpu=e300c2', '', d)}" AVAILTUNES += "ppce300c2" -TUNE_FEATURES_tune-ppce300c2 = "m32 fpu-soft ppce300c2" +TUNE_FEATURES_tune-ppce300c2 = "m32 fpu-soft ppce300c2 bigendian" TUNE_PKGARCH_tune-ppce300c2 = "ppce300c2" PACKAGE_EXTRA_ARCHS_tune-ppce300c2 = "${PACKAGE_EXTRA_ARCHS_tune-powerpc-nf} ppce300c2" diff --git a/meta/conf/machine/include/tune-ppce500.inc b/meta/conf/machine/include/tune-ppce500.inc index 89ec3f38a7..abf81b90c4 100644 --- a/meta/conf/machine/include/tune-ppce500.inc +++ b/meta/conf/machine/include/tune-ppce500.inc @@ -15,6 +15,6 @@ SPEABIEXTENSION = "${@bb.utils.filter('TUNE_FEATURES', 'spe', d)}" ABIEXTENSION .= "${SPEABIEXTENSION}" AVAILTUNES += "ppce500" -TUNE_FEATURES_tune-ppce500 = "m32 spe ppce500" +TUNE_FEATURES_tune-ppce500 = "m32 spe ppce500 bigendian" TUNE_PKGARCH_tune-ppce500 = "ppce500" PACKAGE_EXTRA_ARCHS_tune-ppce500 = "ppce500" diff --git a/meta/conf/machine/include/tune-ppce500mc.inc b/meta/conf/machine/include/tune-ppce500mc.inc index bc26a0f875..9f8a172804 100644 --- a/meta/conf/machine/include/tune-ppce500mc.inc +++ b/meta/conf/machine/include/tune-ppce500mc.inc @@ -6,7 +6,7 @@ TUNEVALID[ppce500mc] = "Enable ppce500mc specific processor optimizations" TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'ppce500mc', ' -mcpu=e500mc', '', d)}" AVAILTUNES += "ppce500mc" -TUNE_FEATURES_tune-ppce500mc = "m32 fpu-hard ppce500mc" +TUNE_FEATURES_tune-ppce500mc = "m32 fpu-hard ppce500mc bigendian" TUNE_PKGARCH_tune-ppce500mc = "ppce500mc" PACKAGE_EXTRA_ARCHS_tune-ppce500mc = "${PACKAGE_EXTRA_ARCHS_tune-powerpc} ppce500mc" diff --git a/meta/conf/machine/include/tune-ppce500v2.inc b/meta/conf/machine/include/tune-ppce500v2.inc index d318bba361..f6c7c17623 100644 --- a/meta/conf/machine/include/tune-ppce500v2.inc +++ b/meta/conf/machine/include/tune-ppce500v2.inc @@ -15,6 +15,6 @@ SPEABIEXTENSION = "${@bb.utils.filter('TUNE_FEATURES', 'spe', d)}" ABIEXTENSION .= "${SPEABIEXTENSION}" AVAILTUNES += "ppce500v2" -TUNE_FEATURES_tune-ppce500v2 = "m32 ppce500v2" +TUNE_FEATURES_tune-ppce500v2 = "m32 ppce500v2 bigendian" TUNE_PKGARCH_tune-ppce500v2 = "ppce500v2" PACKAGE_EXTRA_ARCHS_tune-ppce500v2 = "ppce500v2" diff --git a/meta/conf/machine/include/tune-ppce5500.inc b/meta/conf/machine/include/tune-ppce5500.inc index cebb244068..acc6a50fca 100644 --- a/meta/conf/machine/include/tune-ppce5500.inc +++ b/meta/conf/machine/include/tune-ppce5500.inc @@ -6,12 +6,12 @@ TUNEVALID[e5500] = "Enable Freescale e5500 specific processor optimizations" TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'e5500', ' -mcpu=e5500', '', d)}" AVAILTUNES += "ppce5500 ppc64e5500" -TUNE_FEATURES_tune-ppce5500 = "m32 fpu-hard e5500" +TUNE_FEATURES_tune-ppce5500 = "m32 fpu-hard e5500 bigendian" BASE_LIB_tune-ppce5500 = "lib" TUNE_PKGARCH_tune-ppce5500 = "ppce5500" PACKAGE_EXTRA_ARCHS_tune-ppce5500 = "${PACKAGE_EXTRA_ARCHS_tune-powerpc} ppce5500" -TUNE_FEATURES_tune-ppc64e5500 = "m64 fpu-hard e5500" +TUNE_FEATURES_tune-ppc64e5500 = "m64 fpu-hard e5500 bigendian" BASE_LIB_tune-ppc64e5500 = "lib64" TUNE_PKGARCH_tune-ppc64e5500 = "ppc64e5500" PACKAGE_EXTRA_ARCHS_tune-ppc64e5500 = "${PACKAGE_EXTRA_ARCHS_tune-powerpc64} ppc64e5500" diff --git a/meta/conf/machine/include/tune-ppce6500.inc b/meta/conf/machine/include/tune-ppce6500.inc index 5db7e760c3..d12d218d06 100644 --- a/meta/conf/machine/include/tune-ppce6500.inc +++ b/meta/conf/machine/include/tune-ppce6500.inc @@ -6,12 +6,12 @@ TUNEVALID[e6500] = "Enable Freescale e6500 specific processor optimizations" TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'e6500', ' -mcpu=e6500', '', d)}" AVAILTUNES += "ppce6500 ppc64e6500" -TUNE_FEATURES_tune-ppce6500 = "m32 fpu-hard e6500 altivec" +TUNE_FEATURES_tune-ppce6500 = "m32 fpu-hard e6500 altivec bigendian" BASE_LIB_tune-ppce6500 = "lib" TUNE_PKGARCH_tune-ppce6500 = "ppce6500" PACKAGE_EXTRA_ARCHS_tune-ppce6500 = "${PACKAGE_EXTRA_ARCHS_tune-powerpc} ppce6500" -TUNE_FEATURES_tune-ppc64e6500 = "m64 fpu-hard e6500 altivec" +TUNE_FEATURES_tune-ppc64e6500 = "m64 fpu-hard e6500 altivec bigendian" BASE_LIB_tune-ppc64e6500 = "lib64" TUNE_PKGARCH_tune-ppc64e6500 = "ppc64e6500" PACKAGE_EXTRA_ARCHS_tune-ppc64e6500 = "${PACKAGE_EXTRA_ARCHS_tune-powerpc64} ppc64e6500" From patchwork Sat Aug 31 05:23:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khem Raj X-Patchwork-Id: 172705 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp1556737ily; Fri, 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[73.71.176.3]) by smtp.gmail.com with ESMTPSA id 131sm6493221pge.37.2019.08.30.22.23.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2019 22:23:26 -0700 (PDT) From: Khem Raj To: openembedded-core@lists.openembedded.org Date: Fri, 30 Aug 2019 22:23:12 -0700 Message-Id: <20190831052314.19974-2-raj.khem@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190831052314.19974-1-raj.khem@gmail.com> References: <20190831052314.19974-1-raj.khem@gmail.com> MIME-Version: 1.0 Subject: [OE-core] [PATCH 2/4] tune-riscv: Drop littleendian and introduce bigendian tune X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: openembedded-core-bounces@lists.openembedded.org Errors-To: openembedded-core-bounces@lists.openembedded.org Default riscv is little-endian moreover most of other arches define bigendian as tune and treats absense as litteendian, this make risc-v fall in line Signed-off-by: Khem Raj --- meta/conf/machine/include/riscv/tune-riscv.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.23.0 -- _______________________________________________ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc index 1e3a1081e0..25d0463492 100644 --- a/meta/conf/machine/include/riscv/tune-riscv.inc +++ b/meta/conf/machine/include/riscv/tune-riscv.inc @@ -3,16 +3,16 @@ require conf/machine/include/riscv/arch-riscv.inc TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations" TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations" -TUNEVALID[littleendian] = "Little endian mode" +TUNEVALID[bigendian] = "Big endian mode" AVAILTUNES += "riscv64 riscv32" -TUNE_FEATURES_tune-riscv64 = "riscv64 littleendian" +TUNE_FEATURES_tune-riscv64 = "riscv64" TUNE_ARCH_tune-riscv64 = "riscv64" TUNE_PKGARCH_tune-riscv64 = "riscv64" PACKAGE_EXTRA_ARCHS_tune-riscv64 = "riscv64" -TUNE_FEATURES_tune-riscv32 = "riscv32 littleendian" +TUNE_FEATURES_tune-riscv32 = "riscv32" TUNE_ARCH_tune-riscv32 = "riscv32" TUNE_PKGARCH_tune-riscv32 = "riscv32" PACKAGE_EXTRA_ARCHS_tune-riscv32 = "riscv32" From patchwork Sat Aug 31 05:23:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khem Raj X-Patchwork-Id: 172706 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp1556799ily; Fri, 30 Aug 2019 22:24:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqxeTbGQPR/VLeigSfs3D6M9crVXcnpsPvg+yuRdvYBiq8rnpT9Tgy/217rMWftoZDLOclXN X-Received: by 2002:a17:902:5a1:: with SMTP id f30mr19822942plf.64.1567229062909; Fri, 30 Aug 2019 22:24:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567229062; cv=none; d=google.com; s=arc-20160816; b=08tgUH+SDNfAZxR99u+XfBkTzQjS6dLS1orPLsJ1JGAxXtM+C0+ziKYFc91Bk74HhI mNMZW+BmkT2YA2QikbsdmcMe2I4fQW+7SHA1cpw/dM61cInV0++rXePPoHgtVaYR8JCR CpK9pWOGM3EUy7gGqsevnrxvWADBCQ/t4eNOMXrJz+BfM2+bwLkF8Vwq0vFqVNJnjhAh P92C0/0MCGAARM/nrRuXEW+yYKGJJ629BNoxL4LWbna4Cd3d06+e3Z0qGev633udw4vu q6d/kbBywGxLj+hmsdw3MbgeD3aM11kmfmdQWD8IPo5+2VgrMHkmpx0idF9bcWYBjwYB vvog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:sender:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:delivered-to; bh=L6CopnRI6v33QsMc9cP5meJuSEHvH2PfAgvcMcg6FVQ=; b=XamFO2jFNm9YAW0dT5ZumR0fd/5kL5V7gEbNCFfF/0qRnT8tc0hFcRSv46vKImc9Iq pjW0TXX8ERKSot/Yy08lWPb1IHk+VV5nR++B3doHpGGl7Ll12I6gz10yRnSNCBf7JOMX 03bap+a+bCWAji/ZJslQfGNZgB8/d+8Zkxt0CnSL+7+5/O8ytHOmmxEAdS2aWBYfKRnN IfwjjfwaxKYQY+Mo9kgApib9D7VehWZHRhtjxU4X8J2AhHM/unus9+b4SrDvCsmY14VB XF8VmgdZAJvySMvHHeVmga58jRA/E/1ma7wxn84boJjSJyFfokFszXZ8CgLov8dlwbGD Ld0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@gmail.com header.s=20161025 header.b=kgCOqAmn; spf=pass (google.com: best guess record for domain of openembedded-core-bounces@lists.openembedded.org designates 140.211.169.62 as permitted sender) smtp.mailfrom=openembedded-core-bounces@lists.openembedded.org; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from mail.openembedded.org (mail.openembedded.org. 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[73.71.176.3]) by smtp.gmail.com with ESMTPSA id 131sm6493221pge.37.2019.08.30.22.23.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2019 22:23:27 -0700 (PDT) From: Khem Raj To: openembedded-core@lists.openembedded.org Date: Fri, 30 Aug 2019 22:23:13 -0700 Message-Id: <20190831052314.19974-3-raj.khem@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190831052314.19974-1-raj.khem@gmail.com> References: <20190831052314.19974-1-raj.khem@gmail.com> MIME-Version: 1.0 Subject: [OE-core] [PATCH 3/4] gcc: Move STANDARD_STARTFILE_PREFIX_1 and STANDARD_STARTFILE_PREFIX_2 back to gcc.c X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: openembedded-core-bounces@lists.openembedded.org Errors-To: openembedded-core-bounces@lists.openembedded.org when compiling for ppc64, build emits additional STANDARD_STARTFILE_PREFIX_1 and STANDARD_STARTFILE_PREFIX_2 into gcc/defaults.h which is not conditional because it really want to override others with this new value, but it ends up with two definitions since it gets emitted _after_ the definition this patch moves to default.h and ends up in duplicate defines. Signed-off-by: Khem Raj --- ...e-target-gcc-headers-can-be-included.patch | 47 +------------------ 1 file changed, 2 insertions(+), 45 deletions(-) -- 2.23.0 -- _______________________________________________ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core diff --git a/meta/recipes-devtools/gcc/gcc-9.2/0019-Ensure-target-gcc-headers-can-be-included.patch b/meta/recipes-devtools/gcc/gcc-9.2/0019-Ensure-target-gcc-headers-can-be-included.patch index af0ea5c60a..53f9e99d07 100644 --- a/meta/recipes-devtools/gcc/gcc-9.2/0019-Ensure-target-gcc-headers-can-be-included.patch +++ b/meta/recipes-devtools/gcc/gcc-9.2/0019-Ensure-target-gcc-headers-can-be-included.patch @@ -22,8 +22,6 @@ Signed-off-by: Khem Raj gcc/gcc.c | 7 ------- 4 files changed, 15 insertions(+), 7 deletions(-) -diff --git a/gcc/Makefile.in b/gcc/Makefile.in -index 0064a282488..98d1488171f 100644 --- a/gcc/Makefile.in +++ b/gcc/Makefile.in @@ -618,6 +618,7 @@ libexecdir = @libexecdir@ @@ -34,7 +32,7 @@ index 0064a282488..98d1488171f 100644 # Directory in which the compiler finds executables libexecsubdir = $(libexecdir)/gcc/$(real_target_noncanonical)/$(version)$(accel_dir_suffix) # Directory in which all plugin resources are installed -@@ -2866,6 +2867,7 @@ CFLAGS-intl.o += -DLOCALEDIR=\"$(localedir)\" +@@ -2866,6 +2867,7 @@ CFLAGS-intl.o += -DLOCALEDIR=\"$(localed PREPROCESSOR_DEFINES = \ -DGCC_INCLUDE_DIR=\"$(libsubdir)/include\" \ @@ -42,11 +40,9 @@ index 0064a282488..98d1488171f 100644 -DFIXED_INCLUDE_DIR=\"$(libsubdir)/include-fixed\" \ -DGPLUSPLUS_INCLUDE_DIR=\"$(gcc_gxx_include_dir)\" \ -DGPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT=$(gcc_gxx_include_dir_add_sysroot) \ -diff --git a/gcc/cppdefault.c b/gcc/cppdefault.c -index c4796385643..980e2bd47a7 100644 --- a/gcc/cppdefault.c +++ b/gcc/cppdefault.c -@@ -59,6 +59,10 @@ const struct default_include cpp_include_defaults[] +@@ -59,6 +59,10 @@ const struct default_include cpp_include /* This is the dir for gcc's private headers. */ { GCC_INCLUDE_DIR, "GCC", 0, 0, 0, 0 }, #endif @@ -57,42 +53,3 @@ index c4796385643..980e2bd47a7 100644 #ifdef LOCAL_INCLUDE_DIR /* /usr/local/include comes before the fixincluded header files. */ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, -diff --git a/gcc/defaults.h b/gcc/defaults.h -index b7534256119..41ca579b267 100644 ---- a/gcc/defaults.h -+++ b/gcc/defaults.h -@@ -1459,4 +1459,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - #define DWARF_GNAT_ENCODINGS_DEFAULT DWARF_GNAT_ENCODINGS_GDB - #endif - -+/* Default prefixes to attach to command names. */ -+ -+#ifndef STANDARD_STARTFILE_PREFIX_1 -+#define STANDARD_STARTFILE_PREFIX_1 "/lib/" -+#endif -+#ifndef STANDARD_STARTFILE_PREFIX_2 -+#define STANDARD_STARTFILE_PREFIX_2 "/usr/lib/" -+#endif -+ - #endif /* ! GCC_DEFAULTS_H */ -diff --git a/gcc/gcc.c b/gcc/gcc.c -index 4e7c45b268c..1a3704b2763 100644 ---- a/gcc/gcc.c -+++ b/gcc/gcc.c -@@ -1470,13 +1470,6 @@ static const char *gcc_libexec_prefix; - - /* Default prefixes to attach to command names. */ - --#ifndef STANDARD_STARTFILE_PREFIX_1 --#define STANDARD_STARTFILE_PREFIX_1 "/lib/" --#endif --#ifndef STANDARD_STARTFILE_PREFIX_2 --#define STANDARD_STARTFILE_PREFIX_2 "/usr/lib/" --#endif -- - #ifdef CROSS_DIRECTORY_STRUCTURE /* Don't use these prefixes for a cross compiler. */ - #undef MD_EXEC_PREFIX - #undef MD_STARTFILE_PREFIX --- -2.22.1 - From patchwork Sat Aug 31 05:23:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khem Raj X-Patchwork-Id: 172707 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp1556878ily; Fri, 30 Aug 2019 22:24:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqwkLFiLuPyP0G3SpCP6G1M9vuicNyg2lpM3grm3d9DLX4W9r5dvopb8zVytFRBRNm51bs5W X-Received: by 2002:a63:1020:: with SMTP id f32mr16469883pgl.203.1567229069875; Fri, 30 Aug 2019 22:24:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567229069; cv=none; d=google.com; s=arc-20160816; b=cld+AQ0eZcsARlUqPBS5hajRSK3CurhRoPNITkZQ5bwn/WMMyjGqIvX4xwA8Gpxyp4 2Q9QA34stMrTTAg5pWfjwinwZ8G6+CBvN+0ukuoHX4MYm8PaECD9B9rOMZMjblzfUUzp yOsnbdHUEMHIiCDFWxdDRyxX1kdkXtqlZSFAy2WEXfzQ4U/Pec783C23Fgl0s66sNrnx x+F+RjtxtwWPs1DouhH2yJpTQ8Y8Jn1bzOGm/CoiiKy0+WLoojfD1G2XT1ye/8y3/pIW DmEoFFRd9trtaNCk3jMj+ce/FsxhIFytClfOTFu3V2OVwoPBB3cbOrMJ8qGcuq2s0FLl f/tA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:sender:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:delivered-to; bh=X5WfCQH3EHF7PVgbIQ+Ih0OHh3aOpGoTaI2S56WB7XI=; b=SxA82LGC7ds+d31YIBp/6a2hUvmBHzeoTrqh6v5VVHmi5plE2LGcaRCAwyNsOclqcx TwTo5meemCns9xnMO7vfO1Faa18aZ6efn9aVBYR+8q78l8YVE8OhSxQzgz4FaWkpsKxy HVRU5IsARABo274RMXZGeacCeZFiNgvhjGrOm5LJLJ97qSjgH+dMHL26HoK1PNA2Q6j0 2sDeAGnSHp8omJOrRE3vecxvoCgQNcELZypYezEk+rE1eQdUwxZAMYp/OR1nOE8tUE1V vlzI/x2YyhAhdJQnsddcGeHNvgOvs3QfE+RqOImNUqmZtUZW2/aWQEgsBkqiQf7nHuq5 mhfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@gmail.com header.s=20161025 header.b=HtvJGfW4; spf=pass (google.com: best guess record for domain of openembedded-core-bounces@lists.openembedded.org designates 140.211.169.62 as permitted sender) smtp.mailfrom=openembedded-core-bounces@lists.openembedded.org; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from mail.openembedded.org (mail.openembedded.org. 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[73.71.176.3]) by smtp.gmail.com with ESMTPSA id 131sm6493221pge.37.2019.08.30.22.23.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2019 22:23:27 -0700 (PDT) From: Khem Raj To: openembedded-core@lists.openembedded.org Date: Fri, 30 Aug 2019 22:23:14 -0700 Message-Id: <20190831052314.19974-4-raj.khem@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190831052314.19974-1-raj.khem@gmail.com> References: <20190831052314.19974-1-raj.khem@gmail.com> MIME-Version: 1.0 Subject: [OE-core] [PATCH 4/4] gcc: Fix ldbl-128 support for musl X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: openembedded-core-bounces@lists.openembedded.org Errors-To: openembedded-core-bounces@lists.openembedded.org Let the patch trigger based on target triplet instead of passing via configure, this lets gcc compile for 64bit otherwise it ends up with libgcc build errors error: unable to emulate 'TF' Signed-off-by: Khem Raj --- ...bgcc-Add-knob-to-use-ldbl-128-on-ppc.patch | 178 +++++++----------- meta/recipes-devtools/gcc/gcc-common.inc | 7 - .../gcc/gcc-configure-common.inc | 1 - 3 files changed, 66 insertions(+), 120 deletions(-) -- 2.23.0 -- _______________________________________________ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core diff --git a/meta/recipes-devtools/gcc/gcc-9.2/0030-libgcc-Add-knob-to-use-ldbl-128-on-ppc.patch b/meta/recipes-devtools/gcc/gcc-9.2/0030-libgcc-Add-knob-to-use-ldbl-128-on-ppc.patch index f5769bc8e9..38eab5a083 100644 --- a/meta/recipes-devtools/gcc/gcc-9.2/0030-libgcc-Add-knob-to-use-ldbl-128-on-ppc.patch +++ b/meta/recipes-devtools/gcc/gcc-9.2/0030-libgcc-Add-knob-to-use-ldbl-128-on-ppc.patch @@ -1,125 +1,79 @@ -From baab61ae3938ee2fa9ec03a20793508516a46dae Mon Sep 17 00:00:00 2001 -From: Khem Raj -Date: Fri, 29 Apr 2016 20:03:28 +0000 -Subject: [PATCH 30/36] libgcc: Add knob to use ldbl-128 on ppc - -musl does not support ldbl 128 so we can not assume -that linux as a whole supports ldbl-128 bits, instead -act upon configure option passed to gcc and assume no -on musl and yes otherwise if no option is passed since -default behaviour is to assume ldbl128 it does not -change the defaults +From 47467f3ab0fb2f2fcede81060fe8bb339d0909eb Mon Sep 17 00:00:00 2001 +From: Szabolcs Nagy +Date: Wed, 28 Feb 2018 00:54:05 +0000 +Subject: [PATCH 10/12] ldbl128 config Upstream-Status: Pending Signed-off-by: Khem Raj --- - libgcc/Makefile.in | 1 + - libgcc/config/rs6000/t-linux | 5 ++++- - libgcc/configure | 18 ++++++++++++++++++ - libgcc/configure.ac | 12 ++++++++++++ - 4 files changed, 35 insertions(+), 1 deletion(-) - mode change 100644 => 100755 libgcc/configure + gcc/configure | 13 +++++++++++++ + gcc/configure.ac | 16 ++++++++++++++-- + 2 files changed, 27 insertions(+), 2 deletions(-) -diff --git a/libgcc/Makefile.in b/libgcc/Makefile.in -index ea390a5bbea..114c7876304 100644 ---- a/libgcc/Makefile.in -+++ b/libgcc/Makefile.in -@@ -50,6 +50,7 @@ unwind_header = @unwind_header@ - md_unwind_header = @md_unwind_header@ - sfp_machine_header = @sfp_machine_header@ - thread_header = @thread_header@ -+with_ldbl128 = @with_ldbl128@ - - host_noncanonical = @host_noncanonical@ - real_host_noncanonical = @real_host_noncanonical@ -diff --git a/libgcc/config/rs6000/t-linux b/libgcc/config/rs6000/t-linux -index 4f6d4c4a4d2..c50dd94a2da 100644 ---- a/libgcc/config/rs6000/t-linux -+++ b/libgcc/config/rs6000/t-linux -@@ -1,3 +1,6 @@ - SHLIB_MAPFILES += $(srcdir)/config/rs6000/libgcc-glibc.ver - --HOST_LIBGCC2_CFLAGS += -mlong-double-128 -mno-minimal-toc -+ifeq ($(with_ldbl128),yes) -+HOST_LIBGCC2_CFLAGS += -mlong-double-128 -+endif -+HOST_LIBGCC2_CFLAGS += -mno-minimal-toc -diff --git a/libgcc/configure b/libgcc/configure -old mode 100644 -new mode 100755 -index 36dbbc1f699..b5dd5c34e2a ---- a/libgcc/configure -+++ b/libgcc/configure -@@ -651,6 +651,7 @@ build_vendor - build_cpu - build - with_aix_soname -+with_ldbl128 - enable_vtable_verify - enable_gcov - enable_shared -@@ -702,6 +703,7 @@ with_ld - enable_shared - enable_gcov - enable_vtable_verify -+with_long_double_128 - with_aix_soname - enable_version_specific_runtime_libs - with_slibdir -@@ -1363,6 +1365,7 @@ Optional Packages: - --with-target-subdir=SUBDIR Configuring in a subdirectory for target - --with-cross-host=HOST Configuring with a cross compiler - --with-ld arrange to use the specified ld (full pathname) -+ --with-long-double-128 use 128-bit long double by default - --with-aix-soname=aix|svr4|both - shared library versioning (aka "SONAME") variant to - provide on AIX -@@ -2268,6 +2271,21 @@ fi - - +diff --git a/gcc/configure b/gcc/configure +index 6121e163259..07ff8597d48 100755 +--- a/gcc/configure ++++ b/gcc/configure +@@ -29309,6 +29309,15 @@ if test "${with_long_double_128+set}" = set; then : + withval=$with_long_double_128; gcc_cv_target_ldbl128="$with_long_double_128" + else -+# Check whether --with-long-double-128 was given. -+if test "${with_long_double_128+set}" = set; then : -+ withval=$with_long_double_128; with_ldbl128="$with_long_double_128" -+else -+ case "${host}" in -+ power*-*-musl*) -+ with_ldbl128="no";; -+ *) with_ldbl128="yes";; -+ esac -+ -+fi -+ ++ case "$target" in ++ s390*-*-linux-musl*) ++ gcc_cv_target_ldbl128=yes ++ ;; ++ powerpc*-*-linux-musl*) ++ gcc_cv_target_ldbl128=no ++ ;; ++ *) + + if test $glibc_version_major -gt 2 \ + || ( test $glibc_version_major -eq 2 && test $glibc_version_minor -ge 4 ); then : + gcc_cv_target_ldbl128=yes +@@ -29320,6 +29329,10 @@ else + && gcc_cv_target_ldbl128=yes + + fi + ++ ;; ++ esac + - # Check whether --with-aix-soname was given. - if test "${with_aix_soname+set}" = set; then : - withval=$with_aix_soname; case "${host}:${enable_shared}" in -diff --git a/libgcc/configure.ac b/libgcc/configure.ac -index 8e96cafdf8b..9247856bf24 100644 ---- a/libgcc/configure.ac -+++ b/libgcc/configure.ac -@@ -82,6 +82,18 @@ AC_ARG_ENABLE(vtable-verify, - [enable_vtable_verify=no]) - AC_SUBST(enable_vtable_verify) + fi -+AC_ARG_WITH(long-double-128, -+[AS_HELP_STRING([--with-long-double-128], -+ [use 128-bit long double by default])], -+ with_ldbl128="$with_long_double_128", -+[case "${host}" in -+ power*-*-musl*) -+ with_ldbl128="no";; -+ *) with_ldbl128="yes";; -+ esac -+]) -+AC_SUBST(with_ldbl128) -+ - AC_ARG_WITH(aix-soname, - [AS_HELP_STRING([--with-aix-soname=aix|svr4|both], - [shared library versioning (aka "SONAME") variant to provide on AIX])], + ;; +diff --git a/gcc/configure.ac b/gcc/configure.ac +index b066cc609e1..6c15ed898c0 100644 +--- a/gcc/configure.ac ++++ b/gcc/configure.ac +@@ -5971,13 +5971,25 @@ case "$target" in + AC_ARG_WITH(long-double-128, + [AS_HELP_STRING([--with-long-double-128], + [use 128-bit long double by default])], +- gcc_cv_target_ldbl128="$with_long_double_128", ++ gcc_cv_target_ldbl128="$with_long_double_128", [ ++ case "$target" in ++ s390*-*-linux-musl*) ++ gcc_cv_target_ldbl128=yes ++ ;; ++ powerpc*-*-linux-musl*) ++ gcc_cv_target_ldbl128=no ++ ;; ++ *)] + [GCC_GLIBC_VERSION_GTE_IFELSE([2], [4], [gcc_cv_target_ldbl128=yes], [ + [gcc_cv_target_ldbl128=no + grep '^[ ]*#[ ]*define[ ][ ]*__LONG_DOUBLE_MATH_OPTIONAL' \ + $target_header_dir/bits/wordsize.h > /dev/null 2>&1 \ + && gcc_cv_target_ldbl128=yes +- ]])]) ++ ]])] ++ [ ++ ;; ++ esac ++ ]) + ;; + esac + if test x$gcc_cv_target_ldbl128 = xyes; then -- -2.22.1 +2.17.1 diff --git a/meta/recipes-devtools/gcc/gcc-common.inc b/meta/recipes-devtools/gcc/gcc-common.inc index 96334e54b4..89273a7745 100644 --- a/meta/recipes-devtools/gcc/gcc-common.inc +++ b/meta/recipes-devtools/gcc/gcc-common.inc @@ -41,13 +41,6 @@ def get_gcc_ppc_plt_settings(bb, d): return "--enable-secureplt" return "" -def get_long_double_setting(bb, d): - if d.getVar('TRANSLATED_TARGET_ARCH') in [ 'powerpc', 'powerpc64' ] and d.getVar('TCLIBC') in [ 'glibc' ]: - return "--with-long-double-128" - else: - return "--without-long-double-128 libgcc_cv_powerpc_float128=no" - return "" - def get_gcc_multiarch_setting(bb, d): target_arch = d.getVar('TRANSLATED_TARGET_ARCH') multiarch_options = { diff --git a/meta/recipes-devtools/gcc/gcc-configure-common.inc b/meta/recipes-devtools/gcc/gcc-configure-common.inc index b6f2ca541d..24ba8ce75f 100644 --- a/meta/recipes-devtools/gcc/gcc-configure-common.inc +++ b/meta/recipes-devtools/gcc/gcc-configure-common.inc @@ -36,7 +36,6 @@ EXTRA_OECONF = "\ ${EXTRA_OECONF_PATHS} \ ${@get_gcc_mips_plt_setting(bb, d)} \ ${@get_gcc_ppc_plt_settings(bb, d)} \ - ${@get_long_double_setting(bb, d)} \ ${@get_gcc_multiarch_setting(bb, d)} \ "