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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/43] accel/kvm: Make kvm_has_guest_debug static Date: Tue, 19 Dec 2023 19:12:25 +0000 Message-Id: <20231219191307.2895919-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson This variable is not used or declared outside kvm-all.c. Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- accel/kvm/kvm-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index e39a810a4e9..f138e7fefe7 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -98,7 +98,7 @@ bool kvm_allowed; bool kvm_readonly_mem_allowed; bool kvm_vm_attributes_allowed; bool kvm_msi_use_devid; -bool kvm_has_guest_debug; +static bool kvm_has_guest_debug; static int kvm_sstep_flags; static bool kvm_immediate_exit; static hwaddr kvm_max_slot_size = ~0; From patchwork Tue Dec 19 19:12:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755953 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1601383wra; Tue, 19 Dec 2023 11:16:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IGyG/FjsadVtXx9aatZYWqb70sGe1S5RYWAbt92M7bL32Ca4Rp9wbEKIqAwE4Yrq1JTEakV X-Received: by 2002:a05:622a:2c1:b0:425:9e75:3c71 with SMTP id a1-20020a05622a02c100b004259e753c71mr26031777qtx.64.1703013396634; Tue, 19 Dec 2023 11:16:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013396; cv=none; d=google.com; s=arc-20160816; b=Uw/yPcmMksUs4331+Ff7UoevnqL3JFURH5AS44el2ldIetEZGThEKMSpPAhh/J0RHG w525khBfypwZinbZn1QlXmdGnw5wSzdk7kfnZs3dCxBT8JRfyvhqR/slxn4FaTMsuuVr aSiUC5/WybdMSGvSnVMS6UJnz10K3H3WI9MgP7ltn9betA3ZgXuGkecLVpD+fPXFnoo9 OsjwjXUv1Gwg6VFcYKUVGK00LbX04NR11q7JJZ3YAC2x1UJGqNMnEvuhPerfJPo9ncAN hcLnPUweBv+06PZO3eRhoZ7LG+FzS5J0LixdPZdKdnprh/oSYE5EsDKPnMolgToD1er+ PabQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=F3jDm6hsuPn369Wfm7LfYD3ZrqbNS5l6yUoiu2wnKtg=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=MXTrZQssdOc0E6TfmUte+DBgi90VOLLki9X/Jxdisv/zGSxPw33Ap3n37X9ZsivL3L pK8q/EcyJLnWpK+sxnc5CRhX7JdXfdH3Ib4XcTiAYriCrnusAbwhc3tVgIu5gCGXoq0B RpEheguCGFWMkdtWxNZ7aElW9LfDJ1yi4xHAwa7qUbQmIybAvDUzsCOTkQbKFtcoKQuh zxI2yCdre+Re1VbKEg3vqsIrWcgZtFH+LFcvGSsm7ZCYYMbgC1AUKlN32UhRJJIKSM6r vjKP6tcrrYNtQgGv0UzwLRFZVi8rLiHVi6pGtqjhf36llWDaf+SWkIzdieJqBC3KE9f/ 7VRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ORXSRtIC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/43] target/arm: kvm64: remove a redundant KVM_CAP_SET_GUEST_DEBUG probe Date: Tue, 19 Dec 2023 19:12:26 +0000 Message-Id: <20231219191307.2895919-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Chao Du The KVM_CAP_SET_GUEST_DEBUG is probed during kvm_init(). gdbserver will fail to start if the CAP is not supported. So no need to make another probe here, like other targets. Signed-off-by: Chao Du Reviewed-by: Richard Henderson Message-Id: <20231025070726.22689-1-duchao@eswincomputing.com> Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 3c175c93a7a..b8bb25a1eaa 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -32,13 +32,9 @@ #include "hw/acpi/acpi.h" #include "hw/acpi/ghes.h" -static bool have_guest_debug; void kvm_arm_init_debug(KVMState *s) { - have_guest_debug = kvm_check_extension(s, - KVM_CAP_SET_GUEST_DEBUG); - max_hw_wps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_WPS); hw_watchpoints = g_array_sized_new(true, true, sizeof(HWWatchpoint), max_hw_wps); @@ -1141,33 +1137,23 @@ static const uint32_t brk_insn = 0xd4200000; int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) { - if (have_guest_debug) { - if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) || - cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { - return -EINVAL; - } - return 0; - } else { - error_report("guest debug not supported on this kernel"); + if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) || + cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { return -EINVAL; } + return 0; } int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) { static uint32_t brk; - if (have_guest_debug) { - if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) || - brk != brk_insn || - cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { - return -EINVAL; - } - return 0; - } else { - error_report("guest debug not supported on this kernel"); + if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) || + brk != brk_insn || + cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { return -EINVAL; } + return 0; } /* See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register From patchwork Tue Dec 19 19:12:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755954 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1601517wra; Tue, 19 Dec 2023 11:16:54 -0800 (PST) X-Google-Smtp-Source: AGHT+IGkMjKsG2hhz5jkEkOgRhphd4rLi7Ip6i0Y8bfX1hj0HzPHkuiQSbYVce8xuSs0iKnoH5TE X-Received: by 2002:ac8:7d4a:0:b0:41c:c3ad:922d with SMTP id h10-20020ac87d4a000000b0041cc3ad922dmr26910047qtb.52.1703013413763; Tue, 19 Dec 2023 11:16:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013413; cv=none; d=google.com; s=arc-20160816; b=X2xONDLeFRpd4us9bAqUVJK5PSlTWJuSmh0o08WSJN8vt8k6IjPDRZUhFfePOQwlw8 IfnK9Q4ySsyvaIL+4u0HkSjaeC3Nh2jgjZ+AUVnEEnK6zh2Qoh0ugMaDF9PsipdYFHCB 6gKrnjypSPBczD9eZOdCleaPlRz4F4PMI3hd7VGTQkdXr63/2JVZhQXdaguRgpg0K+zL ArkcTJLcIlix39CpvHTS+iprr23FC9GCSoty0iziuMhv7pn5zd0vwGB0zLbB/GIZAFuT SBb7txn3fHI5bG9OcEtZ4oGb5axC6cKQkRP+ZtyOzfhTpYIujJQ14bHJcZPAgafendFA bsdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Jvn/OVUOD0Xhju1C/N/gil1Qe6DSfBId9X5CN10lS/s=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=t3MFBOsADIZXUhpzBqa7r2UAaRPLZ6KSMQdHQ9/g+1qsyWyLBnscXDzMbR9iDBQUWH wn6jwL1hHz+io0pdxAZcBu0w6pM7gCuI39PAOMVvyyyFUp4WaPP0TpycdGMzytNjB/El W2qz33/ZHAnxsG0MWVHPAViSyC8sz3/+XTEs2+k1Bc7+fOBjtn09gb4fxjQYXOrn6r3/ lWjIHBziwSf01eeaIGT4L+DTtd7CVdk0Ywbqrbd8SNtI9SMjXeg4kImYkRO7PQx45zIR RisvKAvW4j5RM4HvUHwTuM1mULh79VwKxLUZlJCXQOc1nLE021g6kxmkYOMDWTDtN3Ek 6GdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Sc/pNbIj"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/43] target/arm/kvm: Merge kvm_arm_init_debug into kvm_arch_init Date: Tue, 19 Dec 2023 19:12:27 +0000 Message-Id: <20231219191307.2895919-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 8 -------- target/arm/kvm.c | 8 +++++++- target/arm/kvm64.c | 12 ------------ 3 files changed, 7 insertions(+), 21 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 051a0da41c4..fe6d824a52c 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -18,14 +18,6 @@ #define KVM_ARM_VGIC_V2 (1 << 0) #define KVM_ARM_VGIC_V3 (1 << 1) -/** - * kvm_arm_init_debug() - initialize guest debug capabilities - * @s: KVMState - * - * Should be called only once before using guest debug capabilities. - */ -void kvm_arm_init_debug(KVMState *s); - /** * kvm_arm_vcpu_init: * @cs: CPUState diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 7903e2ddde1..b4836da6b25 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -308,7 +308,13 @@ int kvm_arch_init(MachineState *ms, KVMState *s) } } - kvm_arm_init_debug(s); + max_hw_wps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_WPS); + hw_watchpoints = g_array_sized_new(true, true, + sizeof(HWWatchpoint), max_hw_wps); + + max_hw_bps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_BPS); + hw_breakpoints = g_array_sized_new(true, true, + sizeof(HWBreakpoint), max_hw_bps); return ret; } diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index b8bb25a1eaa..40f459b7862 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -33,18 +33,6 @@ #include "hw/acpi/ghes.h" -void kvm_arm_init_debug(KVMState *s) -{ - max_hw_wps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_WPS); - hw_watchpoints = g_array_sized_new(true, true, - sizeof(HWWatchpoint), max_hw_wps); - - max_hw_bps = kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_BPS); - hw_breakpoints = g_array_sized_new(true, true, - sizeof(HWBreakpoint), max_hw_bps); - return; -} - int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) { switch (type) { From patchwork Tue Dec 19 19:12:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755964 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1601934wra; Tue, 19 Dec 2023 11:17:43 -0800 (PST) X-Google-Smtp-Source: AGHT+IHqEBnlmUSd7IX0qhvcsm9G1HyHkWHgRFwM5JNvSt14kFfrIlDAcJl90OSRn12/G4z9SpsH X-Received: by 2002:a05:6214:29ca:b0:67f:2d16:a2e4 with SMTP id gh10-20020a05621429ca00b0067f2d16a2e4mr7519180qvb.104.1703013463440; Tue, 19 Dec 2023 11:17:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013463; cv=none; d=google.com; s=arc-20160816; b=sIMo5mgHG7ra54FUzhaOtpfFpcKfL/L9483Sc1zWz0/AJErEdHHjNmE2p2qGHSxCv1 Yg4Jn0EmPXJWnx4J3vHcLHqUDOJ8DIjO+Ecxy9yMWvWPBpZLPvLNUw/ro0fS1gi2nADr mRaDwB9bDsZUCSSBRt8ECsWpPM38T/HZ5Xib83M7lYmv8M3/hkeTZxgilS3zfW5MTLht ZiQQUWpz+n0Fdv0kbc4cOVyM91c/DrD4a1R40ryndZnGcxicaYPhbSzdRSccElq7bmHz Lq6aQY397CuuyHgJpwPruhN3AEfUUStQM0mz+9q7h4W8kmgMISwOJIIRfuCPPbIUVu34 Gujw== ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/43] target/arm/kvm: Move kvm_arm_verify_ext_dabt_pending and unexport Date: Tue, 19 Dec 2023 19:12:28 +0000 Message-Id: <20231219191307.2895919-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 10 -------- target/arm/kvm.c | 57 ++++++++++++++++++++++++++++++++++++++++++++ target/arm/kvm64.c | 49 ------------------------------------- 3 files changed, 57 insertions(+), 59 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index fe6d824a52c..bb284a47de3 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -472,14 +472,4 @@ bool kvm_arm_hw_debug_active(CPUState *cs); struct kvm_guest_debug_arch; void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr); -/** - * kvm_arm_verify_ext_dabt_pending: - * @cs: CPUState - * - * Verify the fault status code wrt the Ext DABT injection - * - * Returns: true if the fault status code is as expected, false otherwise - */ -bool kvm_arm_verify_ext_dabt_pending(CPUState *cs); - #endif diff --git a/target/arm/kvm.c b/target/arm/kvm.c index b4836da6b25..696bc63e863 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -793,6 +793,63 @@ int kvm_get_vcpu_events(ARMCPU *cpu) return 0; } +#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0) +#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2) + +/* + * ESR_EL1 + * ISS encoding + * AARCH64: DFSC, bits [5:0] + * AARCH32: + * TTBCR.EAE == 0 + * FS[4] - DFSR[10] + * FS[3:0] - DFSR[3:0] + * TTBCR.EAE == 1 + * FS, bits [5:0] + */ +#define ESR_DFSC(aarch64, lpae, v) \ + ((aarch64 || (lpae)) ? ((v) & 0x3F) \ + : (((v) >> 6) | ((v) & 0x1F))) + +#define ESR_DFSC_EXTABT(aarch64, lpae) \ + ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8) + +/** + * kvm_arm_verify_ext_dabt_pending: + * @cs: CPUState + * + * Verify the fault status code wrt the Ext DABT injection + * + * Returns: true if the fault status code is as expected, false otherwise + */ +static bool kvm_arm_verify_ext_dabt_pending(CPUState *cs) +{ + uint64_t dfsr_val; + + if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64); + int lpae = 0; + + if (!aarch64_mode) { + uint64_t ttbcr; + + if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) { + lpae = arm_feature(env, ARM_FEATURE_LPAE) + && (ttbcr & TTBCR_EAE); + } + } + /* + * The verification here is based on the DFSC bits + * of the ESR_EL1 reg only + */ + return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) == + ESR_DFSC_EXTABT(aarch64_mode, lpae)); + } + return false; +} + void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) { ARMCPU *cpu = ARM_CPU(cs); diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 40f459b7862..7d937e25390 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1213,52 +1213,3 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit) return false; } - -#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0) -#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2) - -/* - * ESR_EL1 - * ISS encoding - * AARCH64: DFSC, bits [5:0] - * AARCH32: - * TTBCR.EAE == 0 - * FS[4] - DFSR[10] - * FS[3:0] - DFSR[3:0] - * TTBCR.EAE == 1 - * FS, bits [5:0] - */ -#define ESR_DFSC(aarch64, lpae, v) \ - ((aarch64 || (lpae)) ? ((v) & 0x3F) \ - : (((v) >> 6) | ((v) & 0x1F))) - -#define ESR_DFSC_EXTABT(aarch64, lpae) \ - ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8) - -bool kvm_arm_verify_ext_dabt_pending(CPUState *cs) -{ - uint64_t dfsr_val; - - if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64); - int lpae = 0; - - if (!aarch64_mode) { - uint64_t ttbcr; - - if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) { - lpae = arm_feature(env, ARM_FEATURE_LPAE) - && (ttbcr & TTBCR_EAE); - } - } - /* - * The verification here is based on the DFSC bits - * of the ESR_EL1 reg only - */ - return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) == - ESR_DFSC_EXTABT(aarch64_mode, lpae)); - } - return false; -} From patchwork Tue Dec 19 19:12:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755944 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1600184wra; Tue, 19 Dec 2023 11:14:33 -0800 (PST) X-Google-Smtp-Source: AGHT+IGRRMBxeyMeI0I9F2QrU7lQtQgQ70kX1aKJn0Ioc1vfPe7QUsOeRpxE1Agkew4nVxKECTvQ X-Received: by 2002:a05:6214:2429:b0:67f:2b7a:69ad with SMTP id gy9-20020a056214242900b0067f2b7a69admr2433223qvb.64.1703013272479; Tue, 19 Dec 2023 11:14:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013272; cv=none; d=google.com; s=arc-20160816; b=PrwegV+PfsDMu8Y31ZVRGzeVU6cDPhdZdrGxBcDo/8A+hnU8JprnPRyigP8Aq9BH/m MAaOcoJ0r/vm9glaC/smpsb5dlaM+VQH0zGBQreuVoIVVaYXy413n35wMVKwULEdD4Ct gt+xaUEbe1AUIVr/WXmyxhrnKtRQOstokurXx0dPoNadSmf1/t7g8eRGI4CMxZQ5108Q pBt0wQ9uHnX2Td5W1z6oMEIL/tZV5upSmd/PaV0Hbn/mhebPDZDUBZtJhBZe0aEJIRR9 hTIKJkDT2rIUYgmz5AKgUlnLrBuDyq/DuwSJZ94SkzXHofiyiug0SjjZCVHc2NqO+cax 6r/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=F3MrT5q0KM6MELIuaCuVzJsIz/QtvXJBno3yclja630=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=hCtmHb1AvPYWEYX0q1kfwpZDHQ/o3qT22JlcbDIZ4AcxVXyxXbKR9qm40bjlNvXToW LHg6AX9eEjEhzZM/xkQLMkrriTprVynmOHTHoRbnLa6X2lgvwzUHeEazALDMeblLedJh aVG02ih3cw2lHZM7Y/HIVz3AwMp3Z9MM82Nuwi5yjNR3h/2RCyudN2waC6ETnAy6lyiI gg8WOd3ufkSAAKAPj6VKBYU33qzKDqByv0LNgIaMNHM1V6rplYdKE9Ef2U8lQDoKJj9Y zj4xLXISg8hjhKrPnlQZMKY8Cgqxgna9CDjwaQ7ue1qnkjN38BUBGFQaoVzWTV0Mg75G T+sg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OFlced6I; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/43] target/arm/kvm: Move kvm_arm_copy_hw_debug_data and unexport Date: Tue, 19 Dec 2023 19:12:29 +0000 Message-Id: <20231219191307.2895919-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 10 ---------- target/arm/kvm.c | 24 ++++++++++++++++++++++++ target/arm/kvm64.c | 17 ----------------- 3 files changed, 24 insertions(+), 27 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index bb284a47de3..207b7f21b0a 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -462,14 +462,4 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit); */ bool kvm_arm_hw_debug_active(CPUState *cs); -/** - * kvm_arm_copy_hw_debug_data: - * @ptr: kvm_guest_debug_arch structure - * - * Copy the architecture specific debug registers into the - * kvm_guest_debug ioctl structure. - */ -struct kvm_guest_debug_arch; -void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr); - #endif diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 696bc63e863..2898e680fc5 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1021,6 +1021,30 @@ int kvm_arch_process_async_events(CPUState *cs) return 0; } +/** + * kvm_arm_copy_hw_debug_data: + * @ptr: kvm_guest_debug_arch structure + * + * Copy the architecture specific debug registers into the + * kvm_guest_debug ioctl structure. + */ +static void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr) +{ + int i; + memset(ptr, 0, sizeof(struct kvm_guest_debug_arch)); + + for (i = 0; i < max_hw_wps; i++) { + HWWatchpoint *wp = get_hw_wp(i); + ptr->dbg_wcr[i] = wp->wcr; + ptr->dbg_wvr[i] = wp->wvr; + } + for (i = 0; i < max_hw_bps; i++) { + HWBreakpoint *bp = get_hw_bp(i); + ptr->dbg_bcr[i] = bp->bcr; + ptr->dbg_bvr[i] = bp->bvr; + } +} + void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) { if (kvm_sw_breakpoints_active(cs)) { diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 7d937e25390..ac3120adaff 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -73,23 +73,6 @@ void kvm_arch_remove_all_hw_breakpoints(void) } } -void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr) -{ - int i; - memset(ptr, 0, sizeof(struct kvm_guest_debug_arch)); - - for (i = 0; i < max_hw_wps; i++) { - HWWatchpoint *wp = get_hw_wp(i); - ptr->dbg_wcr[i] = wp->wcr; - ptr->dbg_wvr[i] = wp->wvr; - } - for (i = 0; i < max_hw_bps; i++) { - HWBreakpoint *bp = get_hw_bp(i); - ptr->dbg_bcr[i] = bp->bcr; - ptr->dbg_bvr[i] = bp->bvr; - } -} - bool kvm_arm_hw_debug_active(CPUState *cs) { return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); From patchwork Tue Dec 19 19:12:30 2023 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/43] target/arm/kvm: Move kvm_arm_hw_debug_active and unexport Date: Tue, 19 Dec 2023 19:12:30 +0000 Message-Id: <20231219191307.2895919-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 8 -------- target/arm/kvm.c | 11 +++++++++++ target/arm/kvm64.c | 5 ----- 3 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 207b7f21b0a..ac4856cb46e 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -454,12 +454,4 @@ static inline uint32_t kvm_arm_sve_get_vls(CPUState *cs) */ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit); -/** - * kvm_arm_hw_debug_active: - * @cs: CPU State - * - * Return: TRUE if any hardware breakpoints in use. - */ -bool kvm_arm_hw_debug_active(CPUState *cs); - #endif diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 2898e680fc5..4608bea7df4 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1021,6 +1021,17 @@ int kvm_arch_process_async_events(CPUState *cs) return 0; } +/** + * kvm_arm_hw_debug_active: + * @cs: CPU State + * + * Return: TRUE if any hardware breakpoints in use. + */ +static bool kvm_arm_hw_debug_active(CPUState *cs) +{ + return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); +} + /** * kvm_arm_copy_hw_debug_data: * @ptr: kvm_guest_debug_arch structure diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index ac3120adaff..352643e0665 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -73,11 +73,6 @@ void kvm_arch_remove_all_hw_breakpoints(void) } } -bool kvm_arm_hw_debug_active(CPUState *cs) -{ - return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); -} - static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *attr, const char *name) { From patchwork Tue Dec 19 19:12:31 2023 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/43] target/arm/kvm: Move kvm_arm_handle_debug and unexport Date: Tue, 19 Dec 2023 19:12:31 +0000 Message-Id: <20231219191307.2895919-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 9 ------ target/arm/kvm.c | 77 ++++++++++++++++++++++++++++++++++++++++++++ target/arm/kvm64.c | 70 ---------------------------------------- 3 files changed, 77 insertions(+), 79 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index ac4856cb46e..9fa9cb7f767 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -445,13 +445,4 @@ static inline uint32_t kvm_arm_sve_get_vls(CPUState *cs) #endif -/** - * kvm_arm_handle_debug: - * @cs: CPUState - * @debug_exit: debug part of the KVM exit structure - * - * Returns: TRUE if the debug exception was handled. - */ -bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit); - #endif diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 4608bea7df4..55e1b4f26e9 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -988,6 +988,83 @@ static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, return -1; } +/** + * kvm_arm_handle_debug: + * @cs: CPUState + * @debug_exit: debug part of the KVM exit structure + * + * Returns: TRUE if the debug exception was handled. + * + * See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register + * + * To minimise translating between kernel and user-space the kernel + * ABI just provides user-space with the full exception syndrome + * register value to be decoded in QEMU. + */ +static bool kvm_arm_handle_debug(CPUState *cs, + struct kvm_debug_exit_arch *debug_exit) +{ + int hsr_ec = syn_get_ec(debug_exit->hsr); + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + + /* Ensure PC is synchronised */ + kvm_cpu_synchronize_state(cs); + + switch (hsr_ec) { + case EC_SOFTWARESTEP: + if (cs->singlestep_enabled) { + return true; + } else { + /* + * The kernel should have suppressed the guest's ability to + * single step at this point so something has gone wrong. + */ + error_report("%s: guest single-step while debugging unsupported" + " (%"PRIx64", %"PRIx32")", + __func__, env->pc, debug_exit->hsr); + return false; + } + break; + case EC_AA64_BKPT: + if (kvm_find_sw_breakpoint(cs, env->pc)) { + return true; + } + break; + case EC_BREAKPOINT: + if (find_hw_breakpoint(cs, env->pc)) { + return true; + } + break; + case EC_WATCHPOINT: + { + CPUWatchpoint *wp = find_hw_watchpoint(cs, debug_exit->far); + if (wp) { + cs->watchpoint_hit = wp; + return true; + } + break; + } + default: + error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")", + __func__, debug_exit->hsr, env->pc); + } + + /* If we are not handling the debug exception it must belong to + * the guest. Let's re-use the existing TCG interrupt code to set + * everything up properly. + */ + cs->exception_index = EXCP_BKPT; + env->exception.syndrome = debug_exit->hsr; + env->exception.vaddress = debug_exit->far; + env->exception.target_el = 1; + qemu_mutex_lock_iothread(); + arm_cpu_do_interrupt(cs); + qemu_mutex_unlock_iothread(); + + return false; +} + int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) { int ret = 0; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 352643e0665..6b6db9374c6 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1121,73 +1121,3 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) } return 0; } - -/* See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register - * - * To minimise translating between kernel and user-space the kernel - * ABI just provides user-space with the full exception syndrome - * register value to be decoded in QEMU. - */ - -bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit) -{ - int hsr_ec = syn_get_ec(debug_exit->hsr); - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - - /* Ensure PC is synchronised */ - kvm_cpu_synchronize_state(cs); - - switch (hsr_ec) { - case EC_SOFTWARESTEP: - if (cs->singlestep_enabled) { - return true; - } else { - /* - * The kernel should have suppressed the guest's ability to - * single step at this point so something has gone wrong. - */ - error_report("%s: guest single-step while debugging unsupported" - " (%"PRIx64", %"PRIx32")", - __func__, env->pc, debug_exit->hsr); - return false; - } - break; - case EC_AA64_BKPT: - if (kvm_find_sw_breakpoint(cs, env->pc)) { - return true; - } - break; - case EC_BREAKPOINT: - if (find_hw_breakpoint(cs, env->pc)) { - return true; - } - break; - case EC_WATCHPOINT: - { - CPUWatchpoint *wp = find_hw_watchpoint(cs, debug_exit->far); - if (wp) { - cs->watchpoint_hit = wp; - return true; - } - break; - } - default: - error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")", - __func__, debug_exit->hsr, env->pc); - } - - /* If we are not handling the debug exception it must belong to - * the guest. Let's re-use the existing TCG interrupt code to set - * everything up properly. - */ - cs->exception_index = EXCP_BKPT; - env->exception.syndrome = debug_exit->hsr; - env->exception.vaddress = debug_exit->far; - env->exception.target_el = 1; - qemu_mutex_lock_iothread(); - arm_cpu_do_interrupt(cs); - qemu_mutex_unlock_iothread(); - - return false; -} From patchwork Tue Dec 19 19:12:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755943 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1600179wra; Tue, 19 Dec 2023 11:14:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IEO27aipFpzfaTxW4srudHB5SoGjocM0RaZLrv0bjMzjh1+zTQ6UEQrYaoJZoxvVozU8+W7 X-Received: by 2002:a05:6122:7cf:b0:4b6:ce73:5e1 with SMTP id l15-20020a05612207cf00b004b6ce7305e1mr2477480vkr.3.1703013272323; Tue, 19 Dec 2023 11:14:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013272; cv=none; d=google.com; s=arc-20160816; b=rrOcxvH/9hXdBGf6pZKTxBxKpyl0XSO2HyyCXvHl2HlEhbVta1U78bMiNbyn4qbGAX gUjMLej74tuuWF2iZBRxOR2uP7mazBw3eEmrBlewbrqsqWTJsjgw180qZP2aOXszt08G 1IgwHkg7rdRekyJ0IPrSEDHXz6x00TzxhpzkUmTKNZEtkqjFr9tfPkwSE+ZZz7mZcVd1 cOh5wPi0z/B+gcjyKW+fiICYtBQ2yHg4sAhVjmAhfNh7jtv4qGmQBLAiLYaWZxd2dfsk 4UssfjcN786+PmocP/MtO+nn2scbmBRdtAwZPgrvJo9CmzmkjNxG69Y21Ths9pHTefvM ROxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=r1J7gC45bfq/FYNHKEltq/v3bAcoJrpQOGvO+cx208c=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=uHbKov3xPHDeEeXq679rVmab0GITw4S9UK8QWI+spwy2tnl+4iVBLA88xgOslAhZW0 9/JKeLl//FQ8InyxISsVNwpJI59BQgNCcNTatDRB0PULhXa/QLOZNi+Z9oWgRgj19YCS aiKxekKnhCIzDGCWIjo+Nvn3Q3GmjvuNY8V0Yh3zKn+LcmBQoJ6m6OvhprFBXFiOIZT+ vqtckl1wb852j+2m6k3WugGJXHqYSXGGctidXJdLMroMJnYugoGVa7H8fnbCEanyRYcc FvuePjJ90wkKQqhNaKt97pSBaRf41ciVVOZrbdizgBUrQ31Yw4nVzpOa2PLRPUYtUXE+ Zsgw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Vm0feBfw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/43] target/arm/kvm: Unexport kvm_arm_{get, put}_virtual_time Date: Tue, 19 Dec 2023 19:12:32 +0000 Message-Id: <20231219191307.2895919-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 16 ---------------- target/arm/kvm.c | 16 ++++++++++++++-- 2 files changed, 14 insertions(+), 18 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 9fa9cb7f767..e7c32f6ed07 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -335,22 +335,6 @@ int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu); */ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu); -/** - * kvm_arm_get_virtual_time: - * @cs: CPUState - * - * Gets the VCPU's virtual counter and stores it in the KVM CPU state. - */ -void kvm_arm_get_virtual_time(CPUState *cs); - -/** - * kvm_arm_put_virtual_time: - * @cs: CPUState - * - * Sets the VCPU's virtual counter to the value stored in the KVM CPU state. - */ -void kvm_arm_put_virtual_time(CPUState *cs); - void kvm_arm_vm_state_change(void *opaque, bool running, RunState state); int kvm_arm_vgic_probe(void); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 55e1b4f26e9..84f300c602b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -704,7 +704,13 @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) return 0; } -void kvm_arm_get_virtual_time(CPUState *cs) +/** + * kvm_arm_get_virtual_time: + * @cs: CPUState + * + * Gets the VCPU's virtual counter and stores it in the KVM CPU state. + */ +static void kvm_arm_get_virtual_time(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); int ret; @@ -722,7 +728,13 @@ void kvm_arm_get_virtual_time(CPUState *cs) cpu->kvm_vtime_dirty = true; } -void kvm_arm_put_virtual_time(CPUState *cs) +/** + * kvm_arm_put_virtual_time: + * @cs: CPUState + * + * Sets the VCPU's virtual counter to the value stored in the KVM CPU state. + */ +static void kvm_arm_put_virtual_time(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); int ret; From patchwork Tue Dec 19 19:12:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755956 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1601562wra; Tue, 19 Dec 2023 11:16:58 -0800 (PST) X-Google-Smtp-Source: AGHT+IH9E6fqLIcmnRA44fqoJTlPoNv+/5/JyLORotIBl+qT6D1T9h4tC1h3agN30FruDurVQiN3 X-Received: by 2002:a05:6808:3023:b0:3b8:b063:6ba6 with SMTP id ay35-20020a056808302300b003b8b0636ba6mr21497124oib.85.1703013418406; Tue, 19 Dec 2023 11:16:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/43] target/arm/kvm: Inline kvm_arm_steal_time_supported Date: Tue, 19 Dec 2023 19:12:33 +0000 Message-Id: <20231219191307.2895919-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson This function is only used once, and is quite simple. Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 13 ------------- target/arm/kvm64.c | 7 +------ 2 files changed, 1 insertion(+), 19 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index e7c32f6ed07..58c087207f5 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -274,14 +274,6 @@ void kvm_arm_add_vcpu_properties(Object *obj); */ void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp); -/** - * kvm_arm_steal_time_supported: - * - * Returns: true if KVM can enable steal time reporting - * and false otherwise. - */ -bool kvm_arm_steal_time_supported(void); - /** * kvm_arm_aarch32_supported: * @@ -374,11 +366,6 @@ static inline bool kvm_arm_sve_supported(void) return false; } -static inline bool kvm_arm_steal_time_supported(void) -{ - return false; -} - /* * These functions should never actually be called without KVM support. */ diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 6b6db9374c6..fca4864b739 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -399,7 +399,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) { - bool has_steal_time = kvm_arm_steal_time_supported(); + bool has_steal_time = kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME); if (cpu->kvm_steal_time == ON_OFF_AUTO_AUTO) { if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { @@ -437,11 +437,6 @@ bool kvm_arm_sve_supported(void) return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); } -bool kvm_arm_steal_time_supported(void) -{ - return kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME); -} - QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1); uint32_t kvm_arm_sve_get_vls(CPUState *cs) From patchwork Tue Dec 19 19:12:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755949 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1600719wra; Tue, 19 Dec 2023 11:15:26 -0800 (PST) X-Google-Smtp-Source: AGHT+IE1sL0YR70G2+umG9TlkDKMPTbb3EAAbEL6WmRgVZJGxVB9Bqca+X/AhYqc3JG8B/+nqmA7 X-Received: by 2002:a05:620a:1471:b0:781:64e:3db5 with SMTP id j17-20020a05620a147100b00781064e3db5mr1002610qkl.127.1703013325696; Tue, 19 Dec 2023 11:15:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013325; cv=none; d=google.com; s=arc-20160816; b=bnOl6yKfeYQel/IBRStRQZPabIhCs46b3y14B53y45uqkSx0KZ0FPN9iRdzRRjYktq m+o41N8YBGRKFhurIMTxUXLAdPk3/hvxqU13kmbjgvTPIJ7nuS5Nb1DO5lzjGpHduIWB 5OhxCwjcM+1KoLTNOMUR797/r7SPvgJ0sqaSHlhk68PoSMVjUArVWexoBxeAUTmR+Qod oNCUPQiRix1Euh3pI3x0xEXnxH3T/m5EdBsn1CR9skQh9ONNXvaJrMk86NbXSYzFubt6 RYE1lV8ibcOEaj7CMKpsoOl+cR1OnDvj3fkoUqwre20MZO7UIsw3AIOSUhIQoMMO5Vta 8jiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tLIB590q5UqcoLo+DPfnNLtYefVrfy0YSOc9bChAWWk=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=X8MlFz0DKu87Sgrr3GOG/hX11ucnMg+JnQUN49g4UvdTwKrMxSDcxoXK0uc4r2EgJX WIigea5RDv0vgTKv9YPKWtXPejyQ2nIZpEPYeJv+GfYibBuoQ4xPMHVoaKKCHHxccOm/ oqCMlcO1qm2TIIYhOiyHSpolCQk2cJ8NtznkkgkGEKPZRnGwJGrMKNb4zK1GQoK+VBx4 hXM/b/Cvh0DDm9qcurycncKxRQ13abRci/Tsd2zS7DZKUJBribhBFACX1SaviCpN4bn9 Tz0SM05DbQO1PcMtjKc/D+N6LUPcO+jroZFyDraDNNxrXSYb/Fhu+BZr14Vm6z/b6tf7 Ma8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XdvbYTXC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/43] target/arm/kvm: Move kvm_arm_get_host_cpu_features and unexport Date: Tue, 19 Dec 2023 19:12:34 +0000 Message-Id: <20231219191307.2895919-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 22 ---- target/arm/kvm.c | 265 +++++++++++++++++++++++++++++++++++++++++++ target/arm/kvm64.c | 254 ----------------------------------------- 3 files changed, 265 insertions(+), 276 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 58c087207f5..e59d713973c 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -214,28 +214,6 @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, */ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); -/** - * ARMHostCPUFeatures: information about the host CPU (identified - * by asking the host kernel) - */ -typedef struct ARMHostCPUFeatures { - ARMISARegisters isar; - uint64_t features; - uint32_t target; - const char *dtb_compatible; -} ARMHostCPUFeatures; - -/** - * kvm_arm_get_host_cpu_features: - * @ahcf: ARMHostCPUClass to fill in - * - * Probe the capabilities of the host kernel's preferred CPU and fill - * in the ARMHostCPUClass struct accordingly. - * - * Returns true on success and false otherwise. - */ -bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf); - /** * kvm_arm_sve_get_vls: * @cs: CPUState diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 84f300c602b..ffe0db42933 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -41,6 +41,17 @@ static bool cap_has_mp_state; static bool cap_has_inject_serror_esr; static bool cap_has_inject_ext_dabt; +/** + * ARMHostCPUFeatures: information about the host CPU (identified + * by asking the host kernel) + */ +typedef struct ARMHostCPUFeatures { + ARMISARegisters isar; + uint64_t features; + uint32_t target; + const char *dtb_compatible; +} ARMHostCPUFeatures; + static ARMHostCPUFeatures arm_host_cpu_features; int kvm_arm_vcpu_init(CPUState *cs) @@ -167,6 +178,260 @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray) } } +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) +{ + uint64_t ret; + struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret }; + int err; + + assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); + err = ioctl(fd, KVM_GET_ONE_REG, &idreg); + if (err < 0) { + return -1; + } + *pret = ret; + return 0; +} + +static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) +{ + struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret }; + + assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); + return ioctl(fd, KVM_GET_ONE_REG, &idreg); +} + +static bool kvm_arm_pauth_supported(void) +{ + return (kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_ADDRESS) && + kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); +} + +static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) +{ + /* Identify the feature bits corresponding to the host CPU, and + * fill out the ARMHostCPUClass fields accordingly. To do this + * we have to create a scratch VM, create a single CPU inside it, + * and then query that CPU for the relevant ID registers. + */ + int fdarray[3]; + bool sve_supported; + bool pmu_supported = false; + uint64_t features = 0; + int err; + + /* Old kernels may not know about the PREFERRED_TARGET ioctl: however + * we know these will only support creating one kind of guest CPU, + * which is its preferred CPU type. Fortunately these old kernels + * support only a very limited number of CPUs. + */ + static const uint32_t cpus_to_try[] = { + KVM_ARM_TARGET_AEM_V8, + KVM_ARM_TARGET_FOUNDATION_V8, + KVM_ARM_TARGET_CORTEX_A57, + QEMU_KVM_ARM_TARGET_NONE + }; + /* + * target = -1 informs kvm_arm_create_scratch_host_vcpu() + * to use the preferred target + */ + struct kvm_vcpu_init init = { .target = -1, }; + + /* + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, + * which is otherwise RAZ. + */ + sve_supported = kvm_arm_sve_supported(); + if (sve_supported) { + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; + } + + /* + * Ask for Pointer Authentication if supported, so that we get + * the unsanitized field values for AA64ISAR1_EL1. + */ + if (kvm_arm_pauth_supported()) { + init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | + 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); + } + + if (kvm_arm_pmu_supported()) { + init.features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; + pmu_supported = true; + } + + if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { + return false; + } + + ahcf->target = init.target; + ahcf->dtb_compatible = "arm,arm-v8"; + + err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, + ARM64_SYS_REG(3, 0, 0, 4, 0)); + if (unlikely(err < 0)) { + /* + * Before v4.15, the kernel only exposed a limited number of system + * registers, not including any of the interesting AArch64 ID regs. + * For the most part we could leave these fields as zero with minimal + * effect, since this does not affect the values seen by the guest. + * + * However, it could cause problems down the line for QEMU, + * so provide a minimal v8.0 default. + * + * ??? Could read MIDR and use knowledge from cpu64.c. + * ??? Could map a page of memory into our temp guest and + * run the tiniest of hand-crafted kernels to extract + * the values seen by the guest. + * ??? Either of these sounds like too much effort just + * to work around running a modern host kernel. + */ + ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */ + err = 0; + } else { + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, + ARM64_SYS_REG(3, 0, 0, 4, 1)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, + ARM64_SYS_REG(3, 0, 0, 4, 5)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, + ARM64_SYS_REG(3, 0, 0, 5, 0)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, + ARM64_SYS_REG(3, 0, 0, 5, 1)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, + ARM64_SYS_REG(3, 0, 0, 6, 0)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, + ARM64_SYS_REG(3, 0, 0, 6, 1)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2, + ARM64_SYS_REG(3, 0, 0, 6, 2)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, + ARM64_SYS_REG(3, 0, 0, 7, 0)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, + ARM64_SYS_REG(3, 0, 0, 7, 1)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, + ARM64_SYS_REG(3, 0, 0, 7, 2)); + + /* + * Note that if AArch32 support is not present in the host, + * the AArch32 sysregs are present to be read, but will + * return UNKNOWN values. This is neither better nor worse + * than skipping the reads and leaving 0, as we must avoid + * considering the values in every case. + */ + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0, + ARM64_SYS_REG(3, 0, 0, 1, 0)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1, + ARM64_SYS_REG(3, 0, 0, 1, 1)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, + ARM64_SYS_REG(3, 0, 0, 1, 2)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, + ARM64_SYS_REG(3, 0, 0, 1, 4)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, + ARM64_SYS_REG(3, 0, 0, 1, 5)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2, + ARM64_SYS_REG(3, 0, 0, 1, 6)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, + ARM64_SYS_REG(3, 0, 0, 1, 7)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, + ARM64_SYS_REG(3, 0, 0, 2, 0)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, + ARM64_SYS_REG(3, 0, 0, 2, 1)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, + ARM64_SYS_REG(3, 0, 0, 2, 2)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, + ARM64_SYS_REG(3, 0, 0, 2, 3)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, + ARM64_SYS_REG(3, 0, 0, 2, 4)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, + ARM64_SYS_REG(3, 0, 0, 2, 5)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, + ARM64_SYS_REG(3, 0, 0, 2, 6)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, + ARM64_SYS_REG(3, 0, 0, 2, 7)); + + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + ARM64_SYS_REG(3, 0, 0, 3, 0)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, + ARM64_SYS_REG(3, 0, 0, 3, 1)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, + ARM64_SYS_REG(3, 0, 0, 3, 2)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, + ARM64_SYS_REG(3, 0, 0, 3, 4)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, + ARM64_SYS_REG(3, 0, 0, 3, 5)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, + ARM64_SYS_REG(3, 0, 0, 3, 6)); + + /* + * DBGDIDR is a bit complicated because the kernel doesn't + * provide an accessor for it in 64-bit mode, which is what this + * scratch VM is in, and there's no architected "64-bit sysreg + * which reads the same as the 32-bit register" the way there is + * for other ID registers. Instead we synthesize a value from the + * AArch64 ID_AA64DFR0, the same way the kernel code in + * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does. + * We only do this if the CPU supports AArch32 at EL1. + */ + if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2) { + int wrps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS); + int brps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS); + int ctx_cmps = + FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); + int version = 6; /* ARMv8 debug architecture */ + bool has_el3 = + !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3); + uint32_t dbgdidr = 0; + + dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps); + dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps); + dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps); + dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version); + dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3); + dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3); + dbgdidr |= (1 << 15); /* RES1 bit */ + ahcf->isar.dbgdidr = dbgdidr; + } + + if (pmu_supported) { + /* PMCR_EL0 is only accessible if the vCPU has feature PMU_V3 */ + err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, + ARM64_SYS_REG(3, 3, 9, 12, 0)); + } + + if (sve_supported) { + /* + * There is a range of kernels between kernel commit 73433762fcae + * and f81cb2c3ad41 which have a bug where the kernel doesn't + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has + * enabled SVE support, which resulted in an error rather than RAZ. + * So only read the register if we set KVM_ARM_VCPU_SVE above. + */ + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, + ARM64_SYS_REG(3, 0, 0, 4, 4)); + } + } + + kvm_arm_destroy_scratch_host_vcpu(fdarray); + + if (err < 0) { + return false; + } + + /* + * We can assume any KVM supporting CPU is at least a v8 + * with VFPv4+Neon; this in turn implies most of the other + * feature bits. + */ + features |= 1ULL << ARM_FEATURE_V8; + features |= 1ULL << ARM_FEATURE_NEON; + features |= 1ULL << ARM_FEATURE_AARCH64; + features |= 1ULL << ARM_FEATURE_PMU; + features |= 1ULL << ARM_FEATURE_GENERIC_TIMER; + + ahcf->features = features; + + return true; +} + void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) { CPUARMState *env = &cpu->env; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index fca4864b739..504526b24c9 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -143,260 +143,6 @@ void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) } } -static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) -{ - uint64_t ret; - struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret }; - int err; - - assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); - err = ioctl(fd, KVM_GET_ONE_REG, &idreg); - if (err < 0) { - return -1; - } - *pret = ret; - return 0; -} - -static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) -{ - struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret }; - - assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); - return ioctl(fd, KVM_GET_ONE_REG, &idreg); -} - -static bool kvm_arm_pauth_supported(void) -{ - return (kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_ADDRESS) && - kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); -} - -bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) -{ - /* Identify the feature bits corresponding to the host CPU, and - * fill out the ARMHostCPUClass fields accordingly. To do this - * we have to create a scratch VM, create a single CPU inside it, - * and then query that CPU for the relevant ID registers. - */ - int fdarray[3]; - bool sve_supported; - bool pmu_supported = false; - uint64_t features = 0; - int err; - - /* Old kernels may not know about the PREFERRED_TARGET ioctl: however - * we know these will only support creating one kind of guest CPU, - * which is its preferred CPU type. Fortunately these old kernels - * support only a very limited number of CPUs. - */ - static const uint32_t cpus_to_try[] = { - KVM_ARM_TARGET_AEM_V8, - KVM_ARM_TARGET_FOUNDATION_V8, - KVM_ARM_TARGET_CORTEX_A57, - QEMU_KVM_ARM_TARGET_NONE - }; - /* - * target = -1 informs kvm_arm_create_scratch_host_vcpu() - * to use the preferred target - */ - struct kvm_vcpu_init init = { .target = -1, }; - - /* - * Ask for SVE if supported, so that we can query ID_AA64ZFR0, - * which is otherwise RAZ. - */ - sve_supported = kvm_arm_sve_supported(); - if (sve_supported) { - init.features[0] |= 1 << KVM_ARM_VCPU_SVE; - } - - /* - * Ask for Pointer Authentication if supported, so that we get - * the unsanitized field values for AA64ISAR1_EL1. - */ - if (kvm_arm_pauth_supported()) { - init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | - 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); - } - - if (kvm_arm_pmu_supported()) { - init.features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; - pmu_supported = true; - } - - if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { - return false; - } - - ahcf->target = init.target; - ahcf->dtb_compatible = "arm,arm-v8"; - - err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, - ARM64_SYS_REG(3, 0, 0, 4, 0)); - if (unlikely(err < 0)) { - /* - * Before v4.15, the kernel only exposed a limited number of system - * registers, not including any of the interesting AArch64 ID regs. - * For the most part we could leave these fields as zero with minimal - * effect, since this does not affect the values seen by the guest. - * - * However, it could cause problems down the line for QEMU, - * so provide a minimal v8.0 default. - * - * ??? Could read MIDR and use knowledge from cpu64.c. - * ??? Could map a page of memory into our temp guest and - * run the tiniest of hand-crafted kernels to extract - * the values seen by the guest. - * ??? Either of these sounds like too much effort just - * to work around running a modern host kernel. - */ - ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */ - err = 0; - } else { - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, - ARM64_SYS_REG(3, 0, 0, 4, 1)); - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, - ARM64_SYS_REG(3, 0, 0, 4, 5)); - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, - ARM64_SYS_REG(3, 0, 0, 5, 0)); - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, - ARM64_SYS_REG(3, 0, 0, 5, 1)); - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, - ARM64_SYS_REG(3, 0, 0, 6, 0)); - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, - ARM64_SYS_REG(3, 0, 0, 6, 1)); - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2, - ARM64_SYS_REG(3, 0, 0, 6, 2)); - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, - ARM64_SYS_REG(3, 0, 0, 7, 0)); - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, - ARM64_SYS_REG(3, 0, 0, 7, 1)); - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, - ARM64_SYS_REG(3, 0, 0, 7, 2)); - - /* - * Note that if AArch32 support is not present in the host, - * the AArch32 sysregs are present to be read, but will - * return UNKNOWN values. This is neither better nor worse - * than skipping the reads and leaving 0, as we must avoid - * considering the values in every case. - */ - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0, - ARM64_SYS_REG(3, 0, 0, 1, 0)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1, - ARM64_SYS_REG(3, 0, 0, 1, 1)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, - ARM64_SYS_REG(3, 0, 0, 1, 2)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, - ARM64_SYS_REG(3, 0, 0, 1, 4)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, - ARM64_SYS_REG(3, 0, 0, 1, 5)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2, - ARM64_SYS_REG(3, 0, 0, 1, 6)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, - ARM64_SYS_REG(3, 0, 0, 1, 7)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, - ARM64_SYS_REG(3, 0, 0, 2, 0)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, - ARM64_SYS_REG(3, 0, 0, 2, 1)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, - ARM64_SYS_REG(3, 0, 0, 2, 2)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, - ARM64_SYS_REG(3, 0, 0, 2, 3)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, - ARM64_SYS_REG(3, 0, 0, 2, 4)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, - ARM64_SYS_REG(3, 0, 0, 2, 5)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, - ARM64_SYS_REG(3, 0, 0, 2, 6)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, - ARM64_SYS_REG(3, 0, 0, 2, 7)); - - err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, - ARM64_SYS_REG(3, 0, 0, 3, 0)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, - ARM64_SYS_REG(3, 0, 0, 3, 1)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, - ARM64_SYS_REG(3, 0, 0, 3, 2)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, - ARM64_SYS_REG(3, 0, 0, 3, 4)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, - ARM64_SYS_REG(3, 0, 0, 3, 5)); - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, - ARM64_SYS_REG(3, 0, 0, 3, 6)); - - /* - * DBGDIDR is a bit complicated because the kernel doesn't - * provide an accessor for it in 64-bit mode, which is what this - * scratch VM is in, and there's no architected "64-bit sysreg - * which reads the same as the 32-bit register" the way there is - * for other ID registers. Instead we synthesize a value from the - * AArch64 ID_AA64DFR0, the same way the kernel code in - * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does. - * We only do this if the CPU supports AArch32 at EL1. - */ - if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2) { - int wrps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS); - int brps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS); - int ctx_cmps = - FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); - int version = 6; /* ARMv8 debug architecture */ - bool has_el3 = - !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3); - uint32_t dbgdidr = 0; - - dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps); - dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps); - dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps); - dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version); - dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3); - dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3); - dbgdidr |= (1 << 15); /* RES1 bit */ - ahcf->isar.dbgdidr = dbgdidr; - } - - if (pmu_supported) { - /* PMCR_EL0 is only accessible if the vCPU has feature PMU_V3 */ - err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, - ARM64_SYS_REG(3, 3, 9, 12, 0)); - } - - if (sve_supported) { - /* - * There is a range of kernels between kernel commit 73433762fcae - * and f81cb2c3ad41 which have a bug where the kernel doesn't - * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has - * enabled SVE support, which resulted in an error rather than RAZ. - * So only read the register if we set KVM_ARM_VCPU_SVE above. - */ - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, - ARM64_SYS_REG(3, 0, 0, 4, 4)); - } - } - - kvm_arm_destroy_scratch_host_vcpu(fdarray); - - if (err < 0) { - return false; - } - - /* - * We can assume any KVM supporting CPU is at least a v8 - * with VFPv4+Neon; this in turn implies most of the other - * feature bits. - */ - features |= 1ULL << ARM_FEATURE_V8; - features |= 1ULL << ARM_FEATURE_NEON; - features |= 1ULL << ARM_FEATURE_AARCH64; - features |= 1ULL << ARM_FEATURE_PMU; - features |= 1ULL << ARM_FEATURE_GENERIC_TIMER; - - ahcf->features = features; - - return true; -} - void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) { bool has_steal_time = kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME); From patchwork Tue Dec 19 19:12:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755951 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1600782wra; Tue, 19 Dec 2023 11:15:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IEWAtqGifJSNoXvdNytOSStw/07ORrRFwfcsN3z72dDx8h/rKnasTAqjgi/9WUD6XFK0Gce X-Received: by 2002:a05:6102:3565:b0:466:5d4d:ecd6 with SMTP id bh5-20020a056102356500b004665d4decd6mr6105437vsb.16.1703013332246; Tue, 19 Dec 2023 11:15:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013332; cv=none; d=google.com; s=arc-20160816; b=v/Qn6/hFy5efiFWMewLRfXJiihZrlSHJ/jSugMnRTs6sJ88Hae3K0YAMgeVCcP7Ard F4BVZRdzTu2nFKnBX3eTd913nizoOsuyzXiq/XZVx4tcOW+HE1YXkgQHVTaDLIDZCX8v As00AA7kvAwU/QhrILIQCwWxJ2UJLaxYWrw8GgHt3yWDSVeHvFPn/hpm2BdaHb3vtLMG QgatJwEValeeT2vl1bidN+/paAUJUI0P0Uvybvz969pxrea7rf/KrXbtVg2O+/ub61cu saAmhLvpc/hl9Qjgj9JER0qlI8F0jXLMI5qF2QQ2fQORgn570kkuvzwANH+bQI5c17Fh oBwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8U4Zs7qJxd6knz6FwIYeN/wpMsd6G/tgH0Hh4NzLuf8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=FJwgMVy/Ynma7a9g42J14jbSVSZj4om2B0ffi1EwqiI3ceGUtgREPzph3VMGfUBvAv x/wJVkZaGepUPFHKgLvN4Z67hYtaVZV7/k/+dYxgBN7ru+ktzm37ZGAA8Vj6YS8okJYd gShaub69UHS4dv6/vRq04AR+4R7SfbTip3tKdJPWyXvyXZ+7YOsWBt/33lB7ShRjMIvs zktAKmR5/WgDKkp1NTu5RRCpokTl8DsDtWgSpbU0tENUXqG08BFWpP0RDIBemHYru7xc 0aS1b53MZKiWOcHeEUkz0QvF460kqmqSBqLQPDAlRRUJMhkvKdoPH21H1kI6Bs+jZ4bi igzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hFRYK+EZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/43] target/arm/kvm: Use a switch for kvm_arm_cpreg_level Date: Tue, 19 Dec 2023 19:12:35 +0000 Message-Id: <20231219191307.2895919-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Use a switch instead of a linear search through data. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 32 +++++++++----------------------- 1 file changed, 9 insertions(+), 23 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 504526b24c9..61fb9dbde0e 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -361,32 +361,18 @@ bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) } } -typedef struct CPRegStateLevel { - uint64_t regidx; - int level; -} CPRegStateLevel; - -/* All system registers not listed in the following table are assumed to be - * of the level KVM_PUT_RUNTIME_STATE. If a register should be written less - * often, you must add it to this table with a state of either - * KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE. - */ -static const CPRegStateLevel non_runtime_cpregs[] = { - { KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE }, - { KVM_REG_ARM_PTIMER_CNT, KVM_PUT_FULL_STATE }, -}; - int kvm_arm_cpreg_level(uint64_t regidx) { - int i; - - for (i = 0; i < ARRAY_SIZE(non_runtime_cpregs); i++) { - const CPRegStateLevel *l = &non_runtime_cpregs[i]; - if (l->regidx == regidx) { - return l->level; - } + /* + * All system registers are assumed to be level KVM_PUT_RUNTIME_STATE. + * If a register should be written less often, you must add it here + * with a state of either KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE. + */ + switch (regidx) { + case KVM_REG_ARM_TIMER_CNT: + case KVM_REG_ARM_PTIMER_CNT: + return KVM_PUT_FULL_STATE; } - return KVM_PUT_RUNTIME_STATE; } From patchwork Tue Dec 19 19:12:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755977 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1602672wra; Tue, 19 Dec 2023 11:19:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IGXFgfaB+wWDDhkXU3JO2fSkIrmdpU7zgyUe8G6zmPgB0mIXAhoURXDlcrOO/NQZJaGEoUT X-Received: by 2002:a05:6214:483:b0:67f:5326:651d with SMTP id pt3-20020a056214048300b0067f5326651dmr3540221qvb.13.1703013552787; Tue, 19 Dec 2023 11:19:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013552; cv=none; d=google.com; s=arc-20160816; b=bSx7hiym93vgbQssSF3BmuYowhlsq+Jk1sFNcrHQ6ohKLWIJBcnu8HWoS85B/Xz8rm N0o7UEGRJYUuTf6OpAxlcXzXuVr13DFijubKxtzu3NuAs5KY+oa3YTjw0gD/t2mA0aBN C0/z/8qHJCinukEXLTeXFvigoBM4KwyOiZDFCq1eglHZrys99ZiaHvEGwhl7dv1Mb8SN Au/MEetJDASJkMFXKy7WAnslq4lhut5gSZP75g7zHRkSfXz4yWNCj7LFOY4QZE9czb7c bqpaML0/lN3DSLJtromxkJu2DtOLXiYODdCXfQDDoRWtjErOdg+EO3p/NIIm/aGnUL2Y 2Dig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DVfybjnXHAr4/V+3lIJ59fueYndSiVdNpHGHcmYVDg8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=zpf5VZhIUvpbK/3aOUsq9tAvWSqGj/FRQr8nFoCalX4LHBqb3NmbIWoHYAY26bgsY8 rZVpQfA4teXF6OWKcUGSkPBSjPohM4/YL6BrG9Asee1+/PdYnP0zwQhho1a40aPklMSe o+4xbJMmJEKcQ5n+yneYQfS7p+ymiY8ScxNyJHDv/WURfHzJ8PQ8SwZqBHivZ/hDSuDf 1agtqor9nvrHRcg3biG4jdplUf6JU1hcKg2g4aDZy3r6I2O6HgxCa40IYUwIDhykVa9J HQrmSFn8DN0T77dqEFBIWjZim1JmRglqWXd8CrxkZGNOMuXHKlDA/IOZTqKV+Yn6mQaP yEtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NVHbqSqQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/43] target/arm/kvm: Move kvm_arm_cpreg_level and unexport Date: Tue, 19 Dec 2023 19:12:36 +0000 Message-Id: <20231219191307.2895919-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 9 --------- target/arm/kvm.c | 22 ++++++++++++++++++++++ target/arm/kvm64.c | 15 --------------- 3 files changed, 22 insertions(+), 24 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index e59d713973c..2755ee83666 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -87,15 +87,6 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu); */ bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx); -/** - * kvm_arm_cpreg_level: - * @regidx: KVM register index - * - * Return the level of this coprocessor/system register. Return value is - * either KVM_PUT_RUNTIME_STATE, KVM_PUT_RESET_STATE, or KVM_PUT_FULL_STATE. - */ -int kvm_arm_cpreg_level(uint64_t regidx); - /** * write_list_to_kvmstate: * @cpu: ARMCPU diff --git a/target/arm/kvm.c b/target/arm/kvm.c index ffe0db42933..dadc3fd7552 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -817,6 +817,28 @@ out: return ret; } +/** + * kvm_arm_cpreg_level: + * @regidx: KVM register index + * + * Return the level of this coprocessor/system register. Return value is + * either KVM_PUT_RUNTIME_STATE, KVM_PUT_RESET_STATE, or KVM_PUT_FULL_STATE. + */ +static int kvm_arm_cpreg_level(uint64_t regidx) +{ + /* + * All system registers are assumed to be level KVM_PUT_RUNTIME_STATE. + * If a register should be written less often, you must add it here + * with a state of either KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE. + */ + switch (regidx) { + case KVM_REG_ARM_TIMER_CNT: + case KVM_REG_ARM_PTIMER_CNT: + return KVM_PUT_FULL_STATE; + } + return KVM_PUT_RUNTIME_STATE; +} + bool write_kvmstate_to_list(ARMCPU *cpu) { CPUState *cs = CPU(cpu); diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 61fb9dbde0e..a184cca4dc8 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -361,21 +361,6 @@ bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) } } -int kvm_arm_cpreg_level(uint64_t regidx) -{ - /* - * All system registers are assumed to be level KVM_PUT_RUNTIME_STATE. - * If a register should be written less often, you must add it here - * with a state of either KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE. - */ - switch (regidx) { - case KVM_REG_ARM_TIMER_CNT: - case KVM_REG_ARM_PTIMER_CNT: - return KVM_PUT_FULL_STATE; - } - return KVM_PUT_RUNTIME_STATE; -} - /* Callers must hold the iothread mutex lock */ static void kvm_inject_arm_sea(CPUState *c) { From patchwork Tue Dec 19 19:12:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755978 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1602875wra; Tue, 19 Dec 2023 11:19:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IEworkXCFS5s/9OZ6/0rgPorUh2DusFQYz9hBsUhbVhvyjgeji3MD2Mm94OgW+b0NFU512r X-Received: by 2002:a05:622a:201:b0:423:7060:3d5e with SMTP id b1-20020a05622a020100b0042370603d5emr2514270qtx.11.1703013575674; Tue, 19 Dec 2023 11:19:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013575; cv=none; d=google.com; s=arc-20160816; b=tSCX+8gyJkqdinsALvyF534E0M2ttD2rpT+epALJLJmJmrHX4W1dBXBQF/E9cPWYYm +y0+1Gz7w12SXf5+gt7LdlzN+tAc0zKvtCuk/7G7ebZhd2tWQCqAtU9wQoajhaZe09fp fLAGyZRh53rShXcNkUrEgWmWI9tMDdkcKzjUeDRtOBlP7CgAgLHM0/KR0gedPnniyvoy yALOwUO1kOjoWKwbXDq4iT9dVnjEXqkyj0ADCSn5PnUzBcwYR6EXhm3mZSubEsNjJ7ka iFWnaE9hI4b1jdvgFbBcEwH71ld+/cbnBGtrmNcrDIFifYLxD57Lo3Tg+3sRij+E2pMZ KeKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ejx0o35FpPOYFf9Do/QdMe6kWwuD6p6Hfkcy2GrwUgw=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=gmbJB/91/7FZjWj4N/0WsUfsZzeRWszAbIhrxx0jebZpnlXzOs4cd9r3w+udWHySX5 7Lh7LmVf816bmwPz+v7KiwW13j/hNb86vUwPFtpYA4LkqD31U60IY6M9JJUZa1gZ3ay9 BmsCc1d91sVmDOuhdnsSLoJBOVgPURBTeNGj7ysY2pB6lFE+/6OSu+Gh4ubnhD9Tl2Ix rrNNZ+TKoJqOyKLlXoyN2aa80jbb8r1AN3tgzZpwX/iSbgYxu10E+lBrjsGfCNg0QQ0+ P0yHnDWrzVrmAJxg+LG7Evsy2w26dyV4aJfcmi0IJU19s9cZQ7g9gbnDM1RLRd8FhxH2 nz2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GY2orO2K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/43] target/arm/kvm: Move kvm_arm_reg_syncs_via_cpreg_list and unexport Date: Tue, 19 Dec 2023 19:12:37 +0000 Message-Id: <20231219191307.2895919-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé [PMM: merged two duplicate comments, as suggested by Gavin] Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 10 ---------- target/arm/kvm.c | 19 +++++++++++++++++++ target/arm/kvm64.c | 15 --------------- 3 files changed, 19 insertions(+), 25 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 2755ee83666..1043123cc7a 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -77,16 +77,6 @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group, */ int kvm_arm_init_cpreg_list(ARMCPU *cpu); -/** - * kvm_arm_reg_syncs_via_cpreg_list: - * @regidx: KVM register index - * - * Return true if this KVM register should be synchronized via the - * cpreg list of arbitrary system registers, false if it is synchronized - * by hand using code in kvm_arch_get/put_registers(). - */ -bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx); - /** * write_list_to_kvmstate: * @cpu: ARMCPU diff --git a/target/arm/kvm.c b/target/arm/kvm.c index dadc3fd7552..05e06f1008b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -740,6 +740,25 @@ static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, uint64_t regidx) return &cpu->cpreg_values[res - cpu->cpreg_indexes]; } +/** + * kvm_arm_reg_syncs_via_cpreg_list: + * @regidx: KVM register index + * + * Return true if this KVM register should be synchronized via the + * cpreg list of arbitrary system registers, false if it is synchronized + * by hand using code in kvm_arch_get/put_registers(). + */ +static bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) +{ + switch (regidx & KVM_REG_ARM_COPROC_MASK) { + case KVM_REG_ARM_CORE: + case KVM_REG_ARM64_SVE: + return false; + default: + return true; + } +} + /* Initialize the ARMCPU cpreg list according to the kernel's * definition of what CPU registers it knows about (and throw away * the previous TCG-created cpreg list). diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index a184cca4dc8..52c0a6d3af5 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -346,21 +346,6 @@ int kvm_arch_destroy_vcpu(CPUState *cs) return 0; } -bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) -{ - /* Return true if the regidx is a register we should synchronize - * via the cpreg_tuples array (ie is not a core or sve reg that - * we sync by hand in kvm_arch_get/put_registers()) - */ - switch (regidx & KVM_REG_ARM_COPROC_MASK) { - case KVM_REG_ARM_CORE: - case KVM_REG_ARM64_SVE: - return false; - default: - return true; - } -} - /* Callers must hold the iothread mutex lock */ static void kvm_inject_arm_sea(CPUState *c) { From patchwork Tue Dec 19 19:12:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755986 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1603985wra; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/43] target/arm/kvm: Merge kvm64.c into kvm.c Date: Tue, 19 Dec 2023 19:12:38 +0000 Message-Id: <20231219191307.2895919-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Since kvm32.c was removed, there is no need to keep them separate. This will allow more symbols to be unexported. Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé [PMM: retain copyright lines from kvm64.c in kvm.c] Signed-off-by: Peter Maydell --- target/arm/kvm.c | 791 +++++++++++++++++++++++++++++++++++++++ target/arm/kvm64.c | 820 ----------------------------------------- target/arm/meson.build | 2 +- 3 files changed, 792 insertions(+), 821 deletions(-) delete mode 100644 target/arm/kvm64.c diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 05e06f1008b..ab797409f13 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -2,6 +2,8 @@ * ARM implementation of KVM hooks * * Copyright Christoffer Dall 2009-2010 + * Copyright Mian-M. Hamayun 2013, Virtual Open Systems + * Copyright Alex Bennée 2014, Linaro * * This work is licensed under the terms of the GNU GPL, version 2 or later. * See the COPYING file in the top-level directory. @@ -19,6 +21,7 @@ #include "qom/object.h" #include "qapi/error.h" #include "sysemu/sysemu.h" +#include "sysemu/runstate.h" #include "sysemu/kvm.h" #include "sysemu/kvm_int.h" #include "kvm_arm.h" @@ -28,10 +31,13 @@ #include "hw/pci/pci.h" #include "exec/memattrs.h" #include "exec/address-spaces.h" +#include "exec/gdbstub.h" #include "hw/boards.h" #include "hw/irq.h" #include "qapi/visitor.h" #include "qemu/log.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/ghes.h" const KVMCapabilityInfo kvm_arch_required_capabilities[] = { KVM_CAP_LAST_INFO @@ -1610,3 +1616,788 @@ void kvm_arch_accel_class_init(ObjectClass *oc) object_class_property_set_description(oc, "eager-split-size", "Eager Page Split chunk size for hugepages. (default: 0, disabled)"); } + +int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) +{ + switch (type) { + case GDB_BREAKPOINT_HW: + return insert_hw_breakpoint(addr); + break; + case GDB_WATCHPOINT_READ: + case GDB_WATCHPOINT_WRITE: + case GDB_WATCHPOINT_ACCESS: + return insert_hw_watchpoint(addr, len, type); + default: + return -ENOSYS; + } +} + +int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) +{ + switch (type) { + case GDB_BREAKPOINT_HW: + return delete_hw_breakpoint(addr); + case GDB_WATCHPOINT_READ: + case GDB_WATCHPOINT_WRITE: + case GDB_WATCHPOINT_ACCESS: + return delete_hw_watchpoint(addr, len, type); + default: + return -ENOSYS; + } +} + +void kvm_arch_remove_all_hw_breakpoints(void) +{ + if (cur_hw_wps > 0) { + g_array_remove_range(hw_watchpoints, 0, cur_hw_wps); + } + if (cur_hw_bps > 0) { + g_array_remove_range(hw_breakpoints, 0, cur_hw_bps); + } +} + +static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *attr, + const char *name) +{ + int err; + + err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); + if (err != 0) { + error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err)); + return false; + } + + err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr); + if (err != 0) { + error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err)); + return false; + } + + return true; +} + +void kvm_arm_pmu_init(CPUState *cs) +{ + struct kvm_device_attr attr = { + .group = KVM_ARM_VCPU_PMU_V3_CTRL, + .attr = KVM_ARM_VCPU_PMU_V3_INIT, + }; + + if (!ARM_CPU(cs)->has_pmu) { + return; + } + if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { + error_report("failed to init PMU"); + abort(); + } +} + +void kvm_arm_pmu_set_irq(CPUState *cs, int irq) +{ + struct kvm_device_attr attr = { + .group = KVM_ARM_VCPU_PMU_V3_CTRL, + .addr = (intptr_t)&irq, + .attr = KVM_ARM_VCPU_PMU_V3_IRQ, + }; + + if (!ARM_CPU(cs)->has_pmu) { + return; + } + if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { + error_report("failed to set irq for PMU"); + abort(); + } +} + +void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) +{ + struct kvm_device_attr attr = { + .group = KVM_ARM_VCPU_PVTIME_CTRL, + .attr = KVM_ARM_VCPU_PVTIME_IPA, + .addr = (uint64_t)&ipa, + }; + + if (ARM_CPU(cs)->kvm_steal_time == ON_OFF_AUTO_OFF) { + return; + } + if (!kvm_arm_set_device_attr(cs, &attr, "PVTIME IPA")) { + error_report("failed to init PVTIME IPA"); + abort(); + } +} + +void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) +{ + bool has_steal_time = kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME); + + if (cpu->kvm_steal_time == ON_OFF_AUTO_AUTO) { + if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + cpu->kvm_steal_time = ON_OFF_AUTO_OFF; + } else { + cpu->kvm_steal_time = ON_OFF_AUTO_ON; + } + } else if (cpu->kvm_steal_time == ON_OFF_AUTO_ON) { + if (!has_steal_time) { + error_setg(errp, "'kvm-steal-time' cannot be enabled " + "on this host"); + return; + } else if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + /* + * DEN0057A chapter 2 says "This specification only covers + * systems in which the Execution state of the hypervisor + * as well as EL1 of virtual machines is AArch64.". And, + * to ensure that, the smc/hvc calls are only specified as + * smc64/hvc64. + */ + error_setg(errp, "'kvm-steal-time' cannot be enabled " + "for AArch32 guests"); + return; + } + } +} + +bool kvm_arm_aarch32_supported(void) +{ + return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT); +} + +bool kvm_arm_sve_supported(void) +{ + return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); +} + +QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1); + +uint32_t kvm_arm_sve_get_vls(CPUState *cs) +{ + /* Only call this function if kvm_arm_sve_supported() returns true. */ + static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; + static bool probed; + uint32_t vq = 0; + int i; + + /* + * KVM ensures all host CPUs support the same set of vector lengths. + * So we only need to create the scratch VCPUs once and then cache + * the results. + */ + if (!probed) { + struct kvm_vcpu_init init = { + .target = -1, + .features[0] = (1 << KVM_ARM_VCPU_SVE), + }; + struct kvm_one_reg reg = { + .id = KVM_REG_ARM64_SVE_VLS, + .addr = (uint64_t)&vls[0], + }; + int fdarray[3], ret; + + probed = true; + + if (!kvm_arm_create_scratch_host_vcpu(NULL, fdarray, &init)) { + error_report("failed to create scratch VCPU with SVE enabled"); + abort(); + } + ret = ioctl(fdarray[2], KVM_GET_ONE_REG, ®); + kvm_arm_destroy_scratch_host_vcpu(fdarray); + if (ret) { + error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s", + strerror(errno)); + abort(); + } + + for (i = KVM_ARM64_SVE_VLS_WORDS - 1; i >= 0; --i) { + if (vls[i]) { + vq = 64 - clz64(vls[i]) + i * 64; + break; + } + } + if (vq > ARM_MAX_VQ) { + warn_report("KVM supports vector lengths larger than " + "QEMU can enable"); + vls[0] &= MAKE_64BIT_MASK(0, ARM_MAX_VQ); + } + } + + return vls[0]; +} + +static int kvm_arm_sve_set_vls(CPUState *cs) +{ + ARMCPU *cpu = ARM_CPU(cs); + uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map }; + + assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX); + + return kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_VLS, &vls[0]); +} + +#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 + +int kvm_arch_init_vcpu(CPUState *cs) +{ + int ret; + uint64_t mpidr; + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + uint64_t psciver; + + if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE || + !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) { + error_report("KVM is not supported for this guest CPU type"); + return -EINVAL; + } + + qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); + + /* Determine init features for this CPU */ + memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); + if (cs->start_powered_off) { + cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF; + } + if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) { + cpu->psci_version = QEMU_PSCI_VERSION_0_2; + cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2; + } + if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT; + } + if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) { + cpu->has_pmu = false; + } + if (cpu->has_pmu) { + cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; + } else { + env->features &= ~(1ULL << ARM_FEATURE_PMU); + } + if (cpu_isar_feature(aa64_sve, cpu)) { + assert(kvm_arm_sve_supported()); + cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE; + } + if (cpu_isar_feature(aa64_pauth, cpu)) { + cpu->kvm_init_features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | + 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); + } + + /* Do KVM_ARM_VCPU_INIT ioctl */ + ret = kvm_arm_vcpu_init(cs); + if (ret) { + return ret; + } + + if (cpu_isar_feature(aa64_sve, cpu)) { + ret = kvm_arm_sve_set_vls(cs); + if (ret) { + return ret; + } + ret = kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE); + if (ret) { + return ret; + } + } + + /* + * KVM reports the exact PSCI version it is implementing via a + * special sysreg. If it is present, use its contents to determine + * what to report to the guest in the dtb (it is the PSCI version, + * in the same 15-bits major 16-bits minor format that PSCI_VERSION + * returns). + */ + if (!kvm_get_one_reg(cs, KVM_REG_ARM_PSCI_VERSION, &psciver)) { + cpu->psci_version = psciver; + } + + /* + * When KVM is in use, PSCI is emulated in-kernel and not by qemu. + * Currently KVM has its own idea about MPIDR assignment, so we + * override our defaults with what we get from KVM. + */ + ret = kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr); + if (ret) { + return ret; + } + cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK; + + /* Check whether user space can specify guest syndrome value */ + kvm_arm_init_serror_injection(cs); + + return kvm_arm_init_cpreg_list(cpu); +} + +int kvm_arch_destroy_vcpu(CPUState *cs) +{ + return 0; +} + +/* Callers must hold the iothread mutex lock */ +static void kvm_inject_arm_sea(CPUState *c) +{ + ARMCPU *cpu = ARM_CPU(c); + CPUARMState *env = &cpu->env; + uint32_t esr; + bool same_el; + + c->exception_index = EXCP_DATA_ABORT; + env->exception.target_el = 1; + + /* + * Set the DFSC to synchronous external abort and set FnV to not valid, + * this will tell guest the FAR_ELx is UNKNOWN for this abort. + */ + same_el = arm_current_el(env) == env->exception.target_el; + esr = syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10); + + env->exception.syndrome = esr; + + arm_cpu_do_interrupt(c); +} + +#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ + KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) + +#define AARCH64_SIMD_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \ + KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) + +#define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \ + KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) + +static int kvm_arch_put_fpsimd(CPUState *cs) +{ + CPUARMState *env = &ARM_CPU(cs)->env; + int i, ret; + + for (i = 0; i < 32; i++) { + uint64_t *q = aa64_vfp_qreg(env, i); +#if HOST_BIG_ENDIAN + uint64_t fp_val[2] = { q[1], q[0] }; + ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), + fp_val); +#else + ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q); +#endif + if (ret) { + return ret; + } + } + + return 0; +} + +/* + * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits + * and PREGS and the FFR have a slice size of 256 bits. However we simply hard + * code the slice index to zero for now as it's unlikely we'll need more than + * one slice for quite some time. + */ +static int kvm_arch_put_sve(CPUState *cs) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + uint64_t tmp[ARM_MAX_VQ * 2]; + uint64_t *r; + int n, ret; + + for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { + r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2); + ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); + if (ret) { + return ret; + } + } + + for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { + r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0], + DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); + ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); + if (ret) { + return ret; + } + } + + r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0], + DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); + ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); + if (ret) { + return ret; + } + + return 0; +} + +int kvm_arch_put_registers(CPUState *cs, int level) +{ + uint64_t val; + uint32_t fpr; + int i, ret; + unsigned int el; + + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + + /* If we are in AArch32 mode then we need to copy the AArch32 regs to the + * AArch64 registers before pushing them out to 64-bit KVM. + */ + if (!is_a64(env)) { + aarch64_sync_32_to_64(env); + } + + for (i = 0; i < 31; i++) { + ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), + &env->xregs[i]); + if (ret) { + return ret; + } + } + + /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the + * QEMU side we keep the current SP in xregs[31] as well. + */ + aarch64_save_sp(env, 1); + + ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); + if (ret) { + return ret; + } + + ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); + if (ret) { + return ret; + } + + /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */ + if (is_a64(env)) { + val = pstate_read(env); + } else { + val = cpsr_read(env); + } + ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); + if (ret) { + return ret; + } + + ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); + if (ret) { + return ret; + } + + ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]); + if (ret) { + return ret; + } + + /* Saved Program State Registers + * + * Before we restore from the banked_spsr[] array we need to + * ensure that any modifications to env->spsr are correctly + * reflected in the banks. + */ + el = arm_current_el(env); + if (el > 0 && !is_a64(env)) { + i = bank_number(env->uncached_cpsr & CPSR_M); + env->banked_spsr[i] = env->spsr; + } + + /* KVM 0-4 map to QEMU banks 1-5 */ + for (i = 0; i < KVM_NR_SPSR; i++) { + ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]), + &env->banked_spsr[i + 1]); + if (ret) { + return ret; + } + } + + if (cpu_isar_feature(aa64_sve, cpu)) { + ret = kvm_arch_put_sve(cs); + } else { + ret = kvm_arch_put_fpsimd(cs); + } + if (ret) { + return ret; + } + + fpr = vfp_get_fpsr(env); + ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); + if (ret) { + return ret; + } + + fpr = vfp_get_fpcr(env); + ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); + if (ret) { + return ret; + } + + write_cpustate_to_list(cpu, true); + + if (!write_list_to_kvmstate(cpu, level)) { + return -EINVAL; + } + + /* + * Setting VCPU events should be triggered after syncing the registers + * to avoid overwriting potential changes made by KVM upon calling + * KVM_SET_VCPU_EVENTS ioctl + */ + ret = kvm_put_vcpu_events(cpu); + if (ret) { + return ret; + } + + kvm_arm_sync_mpstate_to_kvm(cpu); + + return ret; +} + +static int kvm_arch_get_fpsimd(CPUState *cs) +{ + CPUARMState *env = &ARM_CPU(cs)->env; + int i, ret; + + for (i = 0; i < 32; i++) { + uint64_t *q = aa64_vfp_qreg(env, i); + ret = kvm_get_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q); + if (ret) { + return ret; + } else { +#if HOST_BIG_ENDIAN + uint64_t t; + t = q[0], q[0] = q[1], q[1] = t; +#endif + } + } + + return 0; +} + +/* + * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits + * and PREGS and the FFR have a slice size of 256 bits. However we simply hard + * code the slice index to zero for now as it's unlikely we'll need more than + * one slice for quite some time. + */ +static int kvm_arch_get_sve(CPUState *cs) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + uint64_t *r; + int n, ret; + + for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { + r = &env->vfp.zregs[n].d[0]; + ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); + if (ret) { + return ret; + } + sve_bswap64(r, r, cpu->sve_max_vq * 2); + } + + for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { + r = &env->vfp.pregs[n].p[0]; + ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); + if (ret) { + return ret; + } + sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); + } + + r = &env->vfp.pregs[FFR_PRED_NUM].p[0]; + ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); + if (ret) { + return ret; + } + sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); + + return 0; +} + +int kvm_arch_get_registers(CPUState *cs) +{ + uint64_t val; + unsigned int el; + uint32_t fpr; + int i, ret; + + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + + for (i = 0; i < 31; i++) { + ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), + &env->xregs[i]); + if (ret) { + return ret; + } + } + + ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); + if (ret) { + return ret; + } + + ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); + if (ret) { + return ret; + } + + ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); + if (ret) { + return ret; + } + + env->aarch64 = ((val & PSTATE_nRW) == 0); + if (is_a64(env)) { + pstate_write(env, val); + } else { + cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); + } + + /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the + * QEMU side we keep the current SP in xregs[31] as well. + */ + aarch64_restore_sp(env, 1); + + ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); + if (ret) { + return ret; + } + + /* If we are in AArch32 mode then we need to sync the AArch32 regs with the + * incoming AArch64 regs received from 64-bit KVM. + * We must perform this after all of the registers have been acquired from + * the kernel. + */ + if (!is_a64(env)) { + aarch64_sync_64_to_32(env); + } + + ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]); + if (ret) { + return ret; + } + + /* Fetch the SPSR registers + * + * KVM SPSRs 0-4 map to QEMU banks 1-5 + */ + for (i = 0; i < KVM_NR_SPSR; i++) { + ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(spsr[i]), + &env->banked_spsr[i + 1]); + if (ret) { + return ret; + } + } + + el = arm_current_el(env); + if (el > 0 && !is_a64(env)) { + i = bank_number(env->uncached_cpsr & CPSR_M); + env->spsr = env->banked_spsr[i]; + } + + if (cpu_isar_feature(aa64_sve, cpu)) { + ret = kvm_arch_get_sve(cs); + } else { + ret = kvm_arch_get_fpsimd(cs); + } + if (ret) { + return ret; + } + + ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); + if (ret) { + return ret; + } + vfp_set_fpsr(env, fpr); + + ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); + if (ret) { + return ret; + } + vfp_set_fpcr(env, fpr); + + ret = kvm_get_vcpu_events(cpu); + if (ret) { + return ret; + } + + if (!write_kvmstate_to_list(cpu)) { + return -EINVAL; + } + /* Note that it's OK to have registers which aren't in CPUState, + * so we can ignore a failure return here. + */ + write_list_to_cpustate(cpu); + + kvm_arm_sync_mpstate_to_qemu(cpu); + + /* TODO: other registers */ + return ret; +} + +void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) +{ + ram_addr_t ram_addr; + hwaddr paddr; + + assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO); + + if (acpi_ghes_present() && addr) { + ram_addr = qemu_ram_addr_from_host(addr); + if (ram_addr != RAM_ADDR_INVALID && + kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { + kvm_hwpoison_page_add(ram_addr); + /* + * If this is a BUS_MCEERR_AR, we know we have been called + * synchronously from the vCPU thread, so we can easily + * synchronize the state and inject an error. + * + * TODO: we currently don't tell the guest at all about + * BUS_MCEERR_AO. In that case we might either be being + * called synchronously from the vCPU thread, or a bit + * later from the main thread, so doing the injection of + * the error would be more complicated. + */ + if (code == BUS_MCEERR_AR) { + kvm_cpu_synchronize_state(c); + if (!acpi_ghes_record_errors(ACPI_HEST_SRC_ID_SEA, paddr)) { + kvm_inject_arm_sea(c); + } else { + error_report("failed to record the error"); + abort(); + } + } + return; + } + if (code == BUS_MCEERR_AO) { + error_report("Hardware memory error at addr %p for memory used by " + "QEMU itself instead of guest system!", addr); + } + } + + if (code == BUS_MCEERR_AR) { + error_report("Hardware memory error!"); + exit(1); + } +} + +/* C6.6.29 BRK instruction */ +static const uint32_t brk_insn = 0xd4200000; + +int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) +{ + if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) || + cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { + return -EINVAL; + } + return 0; +} + +int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) +{ + static uint32_t brk; + + if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) || + brk != brk_insn || + cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { + return -EINVAL; + } + return 0; +} diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c deleted file mode 100644 index 52c0a6d3af5..00000000000 --- a/target/arm/kvm64.c +++ /dev/null @@ -1,820 +0,0 @@ -/* - * ARM implementation of KVM hooks, 64 bit specific code - * - * Copyright Mian-M. Hamayun 2013, Virtual Open Systems - * Copyright Alex Bennée 2014, Linaro - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - * - */ - -#include "qemu/osdep.h" -#include -#include - -#include -#include - -#include "qapi/error.h" -#include "cpu.h" -#include "qemu/timer.h" -#include "qemu/error-report.h" -#include "qemu/host-utils.h" -#include "qemu/main-loop.h" -#include "exec/gdbstub.h" -#include "sysemu/runstate.h" -#include "sysemu/kvm.h" -#include "sysemu/kvm_int.h" -#include "kvm_arm.h" -#include "internals.h" -#include "cpu-features.h" -#include "hw/acpi/acpi.h" -#include "hw/acpi/ghes.h" - - -int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) -{ - switch (type) { - case GDB_BREAKPOINT_HW: - return insert_hw_breakpoint(addr); - break; - case GDB_WATCHPOINT_READ: - case GDB_WATCHPOINT_WRITE: - case GDB_WATCHPOINT_ACCESS: - return insert_hw_watchpoint(addr, len, type); - default: - return -ENOSYS; - } -} - -int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) -{ - switch (type) { - case GDB_BREAKPOINT_HW: - return delete_hw_breakpoint(addr); - case GDB_WATCHPOINT_READ: - case GDB_WATCHPOINT_WRITE: - case GDB_WATCHPOINT_ACCESS: - return delete_hw_watchpoint(addr, len, type); - default: - return -ENOSYS; - } -} - - -void kvm_arch_remove_all_hw_breakpoints(void) -{ - if (cur_hw_wps > 0) { - g_array_remove_range(hw_watchpoints, 0, cur_hw_wps); - } - if (cur_hw_bps > 0) { - g_array_remove_range(hw_breakpoints, 0, cur_hw_bps); - } -} - -static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *attr, - const char *name) -{ - int err; - - err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); - if (err != 0) { - error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err)); - return false; - } - - err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr); - if (err != 0) { - error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err)); - return false; - } - - return true; -} - -void kvm_arm_pmu_init(CPUState *cs) -{ - struct kvm_device_attr attr = { - .group = KVM_ARM_VCPU_PMU_V3_CTRL, - .attr = KVM_ARM_VCPU_PMU_V3_INIT, - }; - - if (!ARM_CPU(cs)->has_pmu) { - return; - } - if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { - error_report("failed to init PMU"); - abort(); - } -} - -void kvm_arm_pmu_set_irq(CPUState *cs, int irq) -{ - struct kvm_device_attr attr = { - .group = KVM_ARM_VCPU_PMU_V3_CTRL, - .addr = (intptr_t)&irq, - .attr = KVM_ARM_VCPU_PMU_V3_IRQ, - }; - - if (!ARM_CPU(cs)->has_pmu) { - return; - } - if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { - error_report("failed to set irq for PMU"); - abort(); - } -} - -void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) -{ - struct kvm_device_attr attr = { - .group = KVM_ARM_VCPU_PVTIME_CTRL, - .attr = KVM_ARM_VCPU_PVTIME_IPA, - .addr = (uint64_t)&ipa, - }; - - if (ARM_CPU(cs)->kvm_steal_time == ON_OFF_AUTO_OFF) { - return; - } - if (!kvm_arm_set_device_attr(cs, &attr, "PVTIME IPA")) { - error_report("failed to init PVTIME IPA"); - abort(); - } -} - -void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) -{ - bool has_steal_time = kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME); - - if (cpu->kvm_steal_time == ON_OFF_AUTO_AUTO) { - if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - cpu->kvm_steal_time = ON_OFF_AUTO_OFF; - } else { - cpu->kvm_steal_time = ON_OFF_AUTO_ON; - } - } else if (cpu->kvm_steal_time == ON_OFF_AUTO_ON) { - if (!has_steal_time) { - error_setg(errp, "'kvm-steal-time' cannot be enabled " - "on this host"); - return; - } else if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - /* - * DEN0057A chapter 2 says "This specification only covers - * systems in which the Execution state of the hypervisor - * as well as EL1 of virtual machines is AArch64.". And, - * to ensure that, the smc/hvc calls are only specified as - * smc64/hvc64. - */ - error_setg(errp, "'kvm-steal-time' cannot be enabled " - "for AArch32 guests"); - return; - } - } -} - -bool kvm_arm_aarch32_supported(void) -{ - return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT); -} - -bool kvm_arm_sve_supported(void) -{ - return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); -} - -QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1); - -uint32_t kvm_arm_sve_get_vls(CPUState *cs) -{ - /* Only call this function if kvm_arm_sve_supported() returns true. */ - static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; - static bool probed; - uint32_t vq = 0; - int i; - - /* - * KVM ensures all host CPUs support the same set of vector lengths. - * So we only need to create the scratch VCPUs once and then cache - * the results. - */ - if (!probed) { - struct kvm_vcpu_init init = { - .target = -1, - .features[0] = (1 << KVM_ARM_VCPU_SVE), - }; - struct kvm_one_reg reg = { - .id = KVM_REG_ARM64_SVE_VLS, - .addr = (uint64_t)&vls[0], - }; - int fdarray[3], ret; - - probed = true; - - if (!kvm_arm_create_scratch_host_vcpu(NULL, fdarray, &init)) { - error_report("failed to create scratch VCPU with SVE enabled"); - abort(); - } - ret = ioctl(fdarray[2], KVM_GET_ONE_REG, ®); - kvm_arm_destroy_scratch_host_vcpu(fdarray); - if (ret) { - error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s", - strerror(errno)); - abort(); - } - - for (i = KVM_ARM64_SVE_VLS_WORDS - 1; i >= 0; --i) { - if (vls[i]) { - vq = 64 - clz64(vls[i]) + i * 64; - break; - } - } - if (vq > ARM_MAX_VQ) { - warn_report("KVM supports vector lengths larger than " - "QEMU can enable"); - vls[0] &= MAKE_64BIT_MASK(0, ARM_MAX_VQ); - } - } - - return vls[0]; -} - -static int kvm_arm_sve_set_vls(CPUState *cs) -{ - ARMCPU *cpu = ARM_CPU(cs); - uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map }; - - assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX); - - return kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_VLS, &vls[0]); -} - -#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 - -int kvm_arch_init_vcpu(CPUState *cs) -{ - int ret; - uint64_t mpidr; - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - uint64_t psciver; - - if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE || - !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) { - error_report("KVM is not supported for this guest CPU type"); - return -EINVAL; - } - - qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); - - /* Determine init features for this CPU */ - memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); - if (cs->start_powered_off) { - cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF; - } - if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) { - cpu->psci_version = QEMU_PSCI_VERSION_0_2; - cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2; - } - if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT; - } - if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) { - cpu->has_pmu = false; - } - if (cpu->has_pmu) { - cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3; - } else { - env->features &= ~(1ULL << ARM_FEATURE_PMU); - } - if (cpu_isar_feature(aa64_sve, cpu)) { - assert(kvm_arm_sve_supported()); - cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE; - } - if (cpu_isar_feature(aa64_pauth, cpu)) { - cpu->kvm_init_features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | - 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); - } - - /* Do KVM_ARM_VCPU_INIT ioctl */ - ret = kvm_arm_vcpu_init(cs); - if (ret) { - return ret; - } - - if (cpu_isar_feature(aa64_sve, cpu)) { - ret = kvm_arm_sve_set_vls(cs); - if (ret) { - return ret; - } - ret = kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE); - if (ret) { - return ret; - } - } - - /* - * KVM reports the exact PSCI version it is implementing via a - * special sysreg. If it is present, use its contents to determine - * what to report to the guest in the dtb (it is the PSCI version, - * in the same 15-bits major 16-bits minor format that PSCI_VERSION - * returns). - */ - if (!kvm_get_one_reg(cs, KVM_REG_ARM_PSCI_VERSION, &psciver)) { - cpu->psci_version = psciver; - } - - /* - * When KVM is in use, PSCI is emulated in-kernel and not by qemu. - * Currently KVM has its own idea about MPIDR assignment, so we - * override our defaults with what we get from KVM. - */ - ret = kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr); - if (ret) { - return ret; - } - cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK; - - /* Check whether user space can specify guest syndrome value */ - kvm_arm_init_serror_injection(cs); - - return kvm_arm_init_cpreg_list(cpu); -} - -int kvm_arch_destroy_vcpu(CPUState *cs) -{ - return 0; -} - -/* Callers must hold the iothread mutex lock */ -static void kvm_inject_arm_sea(CPUState *c) -{ - ARMCPU *cpu = ARM_CPU(c); - CPUARMState *env = &cpu->env; - uint32_t esr; - bool same_el; - - c->exception_index = EXCP_DATA_ABORT; - env->exception.target_el = 1; - - /* - * Set the DFSC to synchronous external abort and set FnV to not valid, - * this will tell guest the FAR_ELx is UNKNOWN for this abort. - */ - same_el = arm_current_el(env) == env->exception.target_el; - esr = syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10); - - env->exception.syndrome = esr; - - arm_cpu_do_interrupt(c); -} - -#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ - KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) - -#define AARCH64_SIMD_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \ - KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) - -#define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \ - KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) - -static int kvm_arch_put_fpsimd(CPUState *cs) -{ - CPUARMState *env = &ARM_CPU(cs)->env; - int i, ret; - - for (i = 0; i < 32; i++) { - uint64_t *q = aa64_vfp_qreg(env, i); -#if HOST_BIG_ENDIAN - uint64_t fp_val[2] = { q[1], q[0] }; - ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), - fp_val); -#else - ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q); -#endif - if (ret) { - return ret; - } - } - - return 0; -} - -/* - * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits - * and PREGS and the FFR have a slice size of 256 bits. However we simply hard - * code the slice index to zero for now as it's unlikely we'll need more than - * one slice for quite some time. - */ -static int kvm_arch_put_sve(CPUState *cs) -{ - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - uint64_t tmp[ARM_MAX_VQ * 2]; - uint64_t *r; - int n, ret; - - for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { - r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2); - ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); - if (ret) { - return ret; - } - } - - for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { - r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0], - DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); - ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); - if (ret) { - return ret; - } - } - - r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0], - DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); - ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); - if (ret) { - return ret; - } - - return 0; -} - -int kvm_arch_put_registers(CPUState *cs, int level) -{ - uint64_t val; - uint32_t fpr; - int i, ret; - unsigned int el; - - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - - /* If we are in AArch32 mode then we need to copy the AArch32 regs to the - * AArch64 registers before pushing them out to 64-bit KVM. - */ - if (!is_a64(env)) { - aarch64_sync_32_to_64(env); - } - - for (i = 0; i < 31; i++) { - ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), - &env->xregs[i]); - if (ret) { - return ret; - } - } - - /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the - * QEMU side we keep the current SP in xregs[31] as well. - */ - aarch64_save_sp(env, 1); - - ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); - if (ret) { - return ret; - } - - ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); - if (ret) { - return ret; - } - - /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */ - if (is_a64(env)) { - val = pstate_read(env); - } else { - val = cpsr_read(env); - } - ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); - if (ret) { - return ret; - } - - ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); - if (ret) { - return ret; - } - - ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]); - if (ret) { - return ret; - } - - /* Saved Program State Registers - * - * Before we restore from the banked_spsr[] array we need to - * ensure that any modifications to env->spsr are correctly - * reflected in the banks. - */ - el = arm_current_el(env); - if (el > 0 && !is_a64(env)) { - i = bank_number(env->uncached_cpsr & CPSR_M); - env->banked_spsr[i] = env->spsr; - } - - /* KVM 0-4 map to QEMU banks 1-5 */ - for (i = 0; i < KVM_NR_SPSR; i++) { - ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]), - &env->banked_spsr[i + 1]); - if (ret) { - return ret; - } - } - - if (cpu_isar_feature(aa64_sve, cpu)) { - ret = kvm_arch_put_sve(cs); - } else { - ret = kvm_arch_put_fpsimd(cs); - } - if (ret) { - return ret; - } - - fpr = vfp_get_fpsr(env); - ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); - if (ret) { - return ret; - } - - fpr = vfp_get_fpcr(env); - ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); - if (ret) { - return ret; - } - - write_cpustate_to_list(cpu, true); - - if (!write_list_to_kvmstate(cpu, level)) { - return -EINVAL; - } - - /* - * Setting VCPU events should be triggered after syncing the registers - * to avoid overwriting potential changes made by KVM upon calling - * KVM_SET_VCPU_EVENTS ioctl - */ - ret = kvm_put_vcpu_events(cpu); - if (ret) { - return ret; - } - - kvm_arm_sync_mpstate_to_kvm(cpu); - - return ret; -} - -static int kvm_arch_get_fpsimd(CPUState *cs) -{ - CPUARMState *env = &ARM_CPU(cs)->env; - int i, ret; - - for (i = 0; i < 32; i++) { - uint64_t *q = aa64_vfp_qreg(env, i); - ret = kvm_get_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q); - if (ret) { - return ret; - } else { -#if HOST_BIG_ENDIAN - uint64_t t; - t = q[0], q[0] = q[1], q[1] = t; -#endif - } - } - - return 0; -} - -/* - * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits - * and PREGS and the FFR have a slice size of 256 bits. However we simply hard - * code the slice index to zero for now as it's unlikely we'll need more than - * one slice for quite some time. - */ -static int kvm_arch_get_sve(CPUState *cs) -{ - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - uint64_t *r; - int n, ret; - - for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { - r = &env->vfp.zregs[n].d[0]; - ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); - if (ret) { - return ret; - } - sve_bswap64(r, r, cpu->sve_max_vq * 2); - } - - for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { - r = &env->vfp.pregs[n].p[0]; - ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); - if (ret) { - return ret; - } - sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); - } - - r = &env->vfp.pregs[FFR_PRED_NUM].p[0]; - ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); - if (ret) { - return ret; - } - sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); - - return 0; -} - -int kvm_arch_get_registers(CPUState *cs) -{ - uint64_t val; - unsigned int el; - uint32_t fpr; - int i, ret; - - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - - for (i = 0; i < 31; i++) { - ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), - &env->xregs[i]); - if (ret) { - return ret; - } - } - - ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); - if (ret) { - return ret; - } - - ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); - if (ret) { - return ret; - } - - ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); - if (ret) { - return ret; - } - - env->aarch64 = ((val & PSTATE_nRW) == 0); - if (is_a64(env)) { - pstate_write(env, val); - } else { - cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); - } - - /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the - * QEMU side we keep the current SP in xregs[31] as well. - */ - aarch64_restore_sp(env, 1); - - ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); - if (ret) { - return ret; - } - - /* If we are in AArch32 mode then we need to sync the AArch32 regs with the - * incoming AArch64 regs received from 64-bit KVM. - * We must perform this after all of the registers have been acquired from - * the kernel. - */ - if (!is_a64(env)) { - aarch64_sync_64_to_32(env); - } - - ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]); - if (ret) { - return ret; - } - - /* Fetch the SPSR registers - * - * KVM SPSRs 0-4 map to QEMU banks 1-5 - */ - for (i = 0; i < KVM_NR_SPSR; i++) { - ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(spsr[i]), - &env->banked_spsr[i + 1]); - if (ret) { - return ret; - } - } - - el = arm_current_el(env); - if (el > 0 && !is_a64(env)) { - i = bank_number(env->uncached_cpsr & CPSR_M); - env->spsr = env->banked_spsr[i]; - } - - if (cpu_isar_feature(aa64_sve, cpu)) { - ret = kvm_arch_get_sve(cs); - } else { - ret = kvm_arch_get_fpsimd(cs); - } - if (ret) { - return ret; - } - - ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); - if (ret) { - return ret; - } - vfp_set_fpsr(env, fpr); - - ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); - if (ret) { - return ret; - } - vfp_set_fpcr(env, fpr); - - ret = kvm_get_vcpu_events(cpu); - if (ret) { - return ret; - } - - if (!write_kvmstate_to_list(cpu)) { - return -EINVAL; - } - /* Note that it's OK to have registers which aren't in CPUState, - * so we can ignore a failure return here. - */ - write_list_to_cpustate(cpu); - - kvm_arm_sync_mpstate_to_qemu(cpu); - - /* TODO: other registers */ - return ret; -} - -void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) -{ - ram_addr_t ram_addr; - hwaddr paddr; - - assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO); - - if (acpi_ghes_present() && addr) { - ram_addr = qemu_ram_addr_from_host(addr); - if (ram_addr != RAM_ADDR_INVALID && - kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { - kvm_hwpoison_page_add(ram_addr); - /* - * If this is a BUS_MCEERR_AR, we know we have been called - * synchronously from the vCPU thread, so we can easily - * synchronize the state and inject an error. - * - * TODO: we currently don't tell the guest at all about - * BUS_MCEERR_AO. In that case we might either be being - * called synchronously from the vCPU thread, or a bit - * later from the main thread, so doing the injection of - * the error would be more complicated. - */ - if (code == BUS_MCEERR_AR) { - kvm_cpu_synchronize_state(c); - if (!acpi_ghes_record_errors(ACPI_HEST_SRC_ID_SEA, paddr)) { - kvm_inject_arm_sea(c); - } else { - error_report("failed to record the error"); - abort(); - } - } - return; - } - if (code == BUS_MCEERR_AO) { - error_report("Hardware memory error at addr %p for memory used by " - "QEMU itself instead of guest system!", addr); - } - } - - if (code == BUS_MCEERR_AR) { - error_report("Hardware memory error!"); - exit(1); - } -} - -/* C6.6.29 BRK instruction */ -static const uint32_t brk_insn = 0xd4200000; - -int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) -{ - if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) || - cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { - return -EINVAL; - } - return 0; -} - -int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) -{ - static uint32_t brk; - - if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) || - brk != brk_insn || - cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { - return -EINVAL; - } - return 0; -} diff --git a/target/arm/meson.build b/target/arm/meson.build index 5d04a8e94f2..d6c3902e676 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -8,7 +8,7 @@ arm_ss.add(files( )) arm_ss.add(zlib) -arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c')) +arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'), if_false: files('kvm-stub.c')) arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( From patchwork Tue Dec 19 19:12:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755975 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1602443wra; Tue, 19 Dec 2023 11:18:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IG+OFeMx7MJlo//zb63ckezVuMKvNbdd7M0UO49r788DOqzJJ3Xin6d8IniYmufeq5krJiL X-Received: by 2002:a05:620a:4688:b0:77f:983d:960c with SMTP id bq8-20020a05620a468800b0077f983d960cmr14084595qkb.5.1703013524320; Tue, 19 Dec 2023 11:18:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013524; cv=none; d=google.com; s=arc-20160816; b=uiidXzqj+RUOXP69gKHNAS8ZQtEhNvP9z8QLyhrXr4gWqyUjOGoJMxVwiUETEFBOrJ 5fAxRbQpJP4lP9fBAyoHxtxpkSggayTxK5p5Mlzs6XhrszyieMleMmtirpPL5SOt/iHV +gViyczjcuHqMNbmrDyD7EAIiOO10kvAmJG+meLSjYgaxwadQIDNEe84Qh8AQeWo+rID ZUgrNxTIQMVA5Ucw6q5rTTqPFgQXXJ1IuUr8sKjIVOfzYKxU9u5WhAHchjYGe43lu56g b6Wpo3plqW6fsnwGIX8vpbPy/408QUhhDG6LsbKpA+wqCvqIMRp7NDCk1jYHkFBBjwOp 9EMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CIBsZGE1WWySZas0ZHGeHbBmxpd7vxCJhDZi0elDoIo=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=b8GKrFsJT0hxVAqNJgfOaVwjfRjqFmzZQODB7ikps3BUTfUBj8C9xteo0Tkma+87IR VRp9R5TgGp9cUNmakK0pQGBXuDwl1PxbvnzhGk3KaCYJTpIS+wl2Ja4E3wwaVsmcJNr+ lNmENwoGhEvDEhfWzhvj1h/gphUKaZkaWgnAV7DgR4lohrhCYVwwD6ExmSFtq9yvQxF1 hW/fijsZVHajYFTOGsgmA3i/Bg3KU6O2BC9lwGS0ViKpb5mUXZAhzvxKs2HlIAP+BvOw X+jMdpxl29WGHj7eBK7juH7cUOxTppNe9XvHHsulGAJ3zoC6AdCOjBLiDPkvbJUXIHNr Pd4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kIE+YcBm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/43] target/arm/kvm: Unexport kvm_arm_vcpu_init Date: Tue, 19 Dec 2023 19:12:39 +0000 Message-Id: <20231219191307.2895919-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 12 ------------ target/arm/kvm.c | 12 +++++++++++- 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 1043123cc7a..b96ff35e34a 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -18,18 +18,6 @@ #define KVM_ARM_VGIC_V2 (1 << 0) #define KVM_ARM_VGIC_V3 (1 << 1) -/** - * kvm_arm_vcpu_init: - * @cs: CPUState - * - * Initialize (or reinitialize) the VCPU by invoking the - * KVM_ARM_VCPU_INIT ioctl with the CPU type and feature - * bitmask specified in the CPUState. - * - * Returns: 0 if success else < 0 error code - */ -int kvm_arm_vcpu_init(CPUState *cs); - /** * kvm_arm_vcpu_finalize: * @cs: CPUState diff --git a/target/arm/kvm.c b/target/arm/kvm.c index ab797409f13..d1edb9bd67c 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -60,7 +60,17 @@ typedef struct ARMHostCPUFeatures { static ARMHostCPUFeatures arm_host_cpu_features; -int kvm_arm_vcpu_init(CPUState *cs) +/** + * kvm_arm_vcpu_init: + * @cs: CPUState + * + * Initialize (or reinitialize) the VCPU by invoking the + * KVM_ARM_VCPU_INIT ioctl with the CPU type and feature + * bitmask specified in the CPUState. + * + * Returns: 0 if success else < 0 error code + */ +static int kvm_arm_vcpu_init(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); struct kvm_vcpu_init init; From patchwork Tue Dec 19 19:12:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755972 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1602246wra; Tue, 19 Dec 2023 11:18:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IEnDLkOvhEud+BcS80odfcTY/VQ43sKDu3lLWSJyhgEUUsxKsFQ6Qeu6LptxqNIsar8NFF2 X-Received: by 2002:ad4:5aaf:0:b0:67f:3a14:2e62 with SMTP id u15-20020ad45aaf000000b0067f3a142e62mr7050622qvg.39.1703013499618; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/43] target/arm/kvm: Unexport kvm_arm_vcpu_finalize Date: Tue, 19 Dec 2023 19:12:40 +0000 Message-Id: <20231219191307.2895919-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 14 -------------- target/arm/kvm.c | 14 +++++++++++++- 2 files changed, 13 insertions(+), 15 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index b96ff35e34a..9b630a1631e 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -18,20 +18,6 @@ #define KVM_ARM_VGIC_V2 (1 << 0) #define KVM_ARM_VGIC_V3 (1 << 1) -/** - * kvm_arm_vcpu_finalize: - * @cs: CPUState - * @feature: feature to finalize - * - * Finalizes the configuration of the specified VCPU feature by - * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring - * this are documented in the "KVM_ARM_VCPU_FINALIZE" section of - * KVM's API documentation. - * - * Returns: 0 if success else < 0 error code - */ -int kvm_arm_vcpu_finalize(CPUState *cs, int feature); - /** * kvm_arm_register_device: * @mr: memory region for this device diff --git a/target/arm/kvm.c b/target/arm/kvm.c index d1edb9bd67c..5bc96f469e1 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -81,7 +81,19 @@ static int kvm_arm_vcpu_init(CPUState *cs) return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init); } -int kvm_arm_vcpu_finalize(CPUState *cs, int feature) +/** + * kvm_arm_vcpu_finalize: + * @cs: CPUState + * @feature: feature to finalize + * + * Finalizes the configuration of the specified VCPU feature by + * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring + * this are documented in the "KVM_ARM_VCPU_FINALIZE" section of + * KVM's API documentation. + * + * Returns: 0 if success else < 0 error code + */ +static int kvm_arm_vcpu_finalize(CPUState *cs, int feature) { return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_FINALIZE, &feature); } From patchwork Tue Dec 19 19:12:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755955 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1601545wra; Tue, 19 Dec 2023 11:16:57 -0800 (PST) X-Google-Smtp-Source: AGHT+IFrfxSEAAzIORYG6tOGXjE7/T58HC504o5gUmLz0RuMUdcxDIIdGcpwCgvCqeSsv4Gs/HB2 X-Received: by 2002:a05:6358:7254:b0:170:1be0:34b0 with SMTP id i20-20020a056358725400b001701be034b0mr19019075rwa.55.1703013416680; Tue, 19 Dec 2023 11:16:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013416; cv=none; d=google.com; s=arc-20160816; b=ypm0jZH/4fiaVxF6aRPjhEl65PE+/pqh2NdXE+v7iebFgAaYSDKJzK2BNhNv1YGakX J8Sui8rnM5q2oaP/efP3JoIxAu/VuGHfWsobE4rkkjQqg86c1vLSYoZMuz/vgsvAv8lE vT2kDIH/0hSelaYO+d3HLa/E3qJKeh5LZkFwO9ZxVwHbRVRo6f/NRdBPu2B5UUSmuAcL tuSy+dQj1wbDHmt6aybQDlQdj2XVpGsLBbaHXnW0XhGCeH8mJD+wGsxBZ3afBZt17Gq3 gOvYfova66gkQXFVCOcAzaBwgpJE5bV2gz0vboUI+7Z2v7t9NUWuXU1CYj/kpDDhTGt6 HPIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Q+JqI01nncfSjIKYc0Twd9PO0mRP3lelRgIHx6yJ+Vs=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=w3c2eEcaUI5x8InOHYeBXAHCQLmK3Oo6uyFhNA47UKQFImcrNOwFjDC8L4OdhKFbPh j/NavEFtArwchfl0kUyfS2Z+AqmPdQFjJFn1OB4sJWQLtJIZ4GNq383gUakOBQYPCYM8 7clRYJU1zllr0Okw0R9LrHsvmUc/F2KBYiyO0OmVe9aHMDLRzbSz2A61svStkt+JDoDV +FOIIAULMzjev8ajmaPDu28O+08EZqcbTv5c9yKt1lMXRG1Sop7OuznUL3Y3aa62GdWc BVu8x9D7npxM/ODi7aMFkkFjdgDW54Xk2ZCVM4tStRm2pM4md0RCz9AHILwRW1sr5C9l LTzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M1thYfq1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/43] target/arm/kvm: Unexport kvm_arm_init_cpreg_list Date: Tue, 19 Dec 2023 19:12:41 +0000 Message-Id: <20231219191307.2895919-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 12 ------------ target/arm/kvm.c | 10 ++++++++-- 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 9b630a1631e..350ba6cb967 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -39,18 +39,6 @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group, uint64_t attr, int dev_fd, uint64_t addr_ormask); -/** - * kvm_arm_init_cpreg_list: - * @cpu: ARMCPU - * - * Initialize the ARMCPU cpreg list according to the kernel's - * definition of what CPU registers it knows about (and throw away - * the previous TCG-created cpreg list). - * - * Returns: 0 if success, else < 0 error code - */ -int kvm_arm_init_cpreg_list(ARMCPU *cpu); - /** * write_list_to_kvmstate: * @cpu: ARMCPU diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 5bc96f469e1..d87d3e53e02 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -787,11 +787,17 @@ static bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) } } -/* Initialize the ARMCPU cpreg list according to the kernel's +/** + * kvm_arm_init_cpreg_list: + * @cpu: ARMCPU + * + * Initialize the ARMCPU cpreg list according to the kernel's * definition of what CPU registers it knows about (and throw away * the previous TCG-created cpreg list). + * + * Returns: 0 if success, else < 0 error code */ -int kvm_arm_init_cpreg_list(ARMCPU *cpu) +static int kvm_arm_init_cpreg_list(ARMCPU *cpu) { struct kvm_reg_list rl; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/43] target/arm/kvm: Init cap_has_inject_serror_esr in kvm_arch_init Date: Tue, 19 Dec 2023 19:12:42 +0000 Message-Id: <20231219191307.2895919-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson There is no need to do this in kvm_arch_init_vcpu per vcpu. Inline kvm_arm_init_serror_injection rather than keep separate. Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 8 -------- target/arm/kvm.c | 13 ++++--------- 2 files changed, 4 insertions(+), 17 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 350ba6cb967..1ec2476de7b 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -98,14 +98,6 @@ void kvm_arm_cpu_post_load(ARMCPU *cpu); */ void kvm_arm_reset_vcpu(ARMCPU *cpu); -/** - * kvm_arm_init_serror_injection: - * @cs: CPUState - * - * Check whether KVM can set guest SError syndrome. - */ -void kvm_arm_init_serror_injection(CPUState *cs); - /** * kvm_get_vcpu_events: * @cpu: ARMCPU diff --git a/target/arm/kvm.c b/target/arm/kvm.c index d87d3e53e02..4a5553864a0 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -98,12 +98,6 @@ static int kvm_arm_vcpu_finalize(CPUState *cs, int feature) return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_FINALIZE, &feature); } -void kvm_arm_init_serror_injection(CPUState *cs) -{ - cap_has_inject_serror_esr = kvm_check_extension(cs->kvm_state, - KVM_CAP_ARM_INJECT_SERROR_ESR); -} - bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, int *fdarray, struct kvm_vcpu_init *init) @@ -564,6 +558,10 @@ int kvm_arch_init(MachineState *ms, KVMState *s) cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); + /* Check whether user space can specify guest syndrome value */ + cap_has_inject_serror_esr = + kvm_check_extension(s, KVM_CAP_ARM_INJECT_SERROR_ESR); + if (ms->smp.cpus > 256 && !kvm_check_extension(s, KVM_CAP_ARM_IRQ_LINE_LAYOUT_2)) { error_report("Using more than 256 vcpus requires a host kernel " @@ -1946,9 +1944,6 @@ int kvm_arch_init_vcpu(CPUState *cs) } cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK; - /* Check whether user space can specify guest syndrome value */ - kvm_arm_init_serror_injection(cs); - return kvm_arm_init_cpreg_list(cpu); } From patchwork Tue Dec 19 19:12:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755985 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1603980wra; Tue, 19 Dec 2023 11:22:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IHMzfWAT+Gpl3INBn2a8emH0UpBmouD+ahR3GobD1RxtBRYUiRwIy97+zDuvZ/v7v2wdbKM X-Received: by 2002:a05:620a:1d94:b0:77f:9540:56ab with SMTP id pj20-20020a05620a1d9400b0077f954056abmr11700629qkn.123.1703013730697; Tue, 19 Dec 2023 11:22:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013730; cv=none; d=google.com; s=arc-20160816; b=L9HHRnuFw/yM54rAs4W3JlvupQTyeqKv4k/sEfM+hWe/oKdl1mrrVSbqPMb5scuyfw 4PGEur9amE2+SYDDVGE5TGAP9PZuE2TqDXEFZ3AhjrDCMWtJStvV6gvXC2EEORtLfYc9 /vcGIIR60b2DVBlDcBBnUV2WmoKR54Tlv0vjLuhhGFokCa9jQwY8xf6qOxl3Qu54aI68 rymItQo/TQJBkoR7iUkCdh07MzKBki5AHXU1yJBJfoEtPLX5v556lfvrrEqBEzcLNQpo W/zUgHEAyWR30Vx3skDX1hDyMlFEwE7kb10MJxR+fc6BTUXcSwPoZ1JM2ZGTVaSDo9pS VKdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ak4CxhUk6h6TwjSSh7FmGz1AnjJa6mERKfsGXTlTv5I=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=jS/zdNIA+REDRrLtSlOvF9j1EQntg5KgFJwUJheHYNYdNqiwMD0jL5WfmqrjXmQl5b ol0PQrVANZtVV/N5DrwuYR+wSEoI+6mSOOmFcd9kdatu9KaLn96lZOR+k4/tmlJj+Cxc 0R6xUl5+rdq5V5ArgaIsTfcY9gcZxWqJcS7i3ZbYfarK+TERrVl/9UESwosFCtfmVNaA YOYb0xnCvLluBzF2Zqmh1lY4eKfKtf3A8Wfhsk0eH0JM8gCPH0VW6WedSqFKTBrqh3/d SVjh3+SQYE6s3gLYwcyGdvvhcSeHq84yzFUEB5qdKoz0q4S+JLSCiYRC3/ddbxfCUX8r JMHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iU+Oe0L0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/43] target/arm/kvm: Unexport kvm_{get,put}_vcpu_events Date: Tue, 19 Dec 2023 19:12:43 +0000 Message-Id: <20231219191307.2895919-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 20 -------------------- target/arm/kvm.c | 20 ++++++++++++++++++-- 2 files changed, 18 insertions(+), 22 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 1ec2476de7b..b4339d49d11 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -98,26 +98,6 @@ void kvm_arm_cpu_post_load(ARMCPU *cpu); */ void kvm_arm_reset_vcpu(ARMCPU *cpu); -/** - * kvm_get_vcpu_events: - * @cpu: ARMCPU - * - * Get VCPU related state from kvm. - * - * Returns: 0 if success else < 0 error code - */ -int kvm_get_vcpu_events(ARMCPU *cpu); - -/** - * kvm_put_vcpu_events: - * @cpu: ARMCPU - * - * Put VCPU related state to kvm. - * - * Returns: 0 if success else < 0 error code - */ -int kvm_put_vcpu_events(ARMCPU *cpu); - #ifdef CONFIG_KVM /** * kvm_arm_create_scratch_host_vcpu: diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 4a5553864a0..b8923fe1776 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1090,7 +1090,15 @@ static void kvm_arm_put_virtual_time(CPUState *cs) cpu->kvm_vtime_dirty = false; } -int kvm_put_vcpu_events(ARMCPU *cpu) +/** + * kvm_put_vcpu_events: + * @cpu: ARMCPU + * + * Put VCPU related state to kvm. + * + * Returns: 0 if success else < 0 error code + */ +static int kvm_put_vcpu_events(ARMCPU *cpu) { CPUARMState *env = &cpu->env; struct kvm_vcpu_events events; @@ -1119,7 +1127,15 @@ int kvm_put_vcpu_events(ARMCPU *cpu) return ret; } -int kvm_get_vcpu_events(ARMCPU *cpu) +/** + * kvm_get_vcpu_events: + * @cpu: ARMCPU + * + * Get VCPU related state from kvm. + * + * Returns: 0 if success else < 0 error code + */ +static int kvm_get_vcpu_events(ARMCPU *cpu) { CPUARMState *env = &cpu->env; struct kvm_vcpu_events events; From patchwork Tue Dec 19 19:12:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755974 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1602332wra; Tue, 19 Dec 2023 11:18:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IED3yuBvzl+e9dNIGPdl+fYNwhrU7oK1KPCkFgxCQwXro0sR5xYw9v/eN/3izZTgMJ65/rh X-Received: by 2002:ac8:7f0d:0:b0:423:a495:e9c5 with SMTP id f13-20020ac87f0d000000b00423a495e9c5mr26247259qtk.11.1703013511824; Tue, 19 Dec 2023 11:18:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013511; cv=none; d=google.com; s=arc-20160816; b=dD3cDi0qnC/ULzwBdozjAZ+cvDFZBujoKWfmSwPfo0cfdXyQOZKxiF4WXn5EIeg1vr U7Pi3tQFh904Fh+U0Q0GxIxz7tijd9h6ChaMYGddXe3gXXT95twO5ouUpelBWnji4h0F x3YlrVNO4+k3VrquAfadXbV+ToYV4Y40dZTcutfjl3pyqe7JePP9Fn+DXeZ0lQ5J+47H PrzV17/siuZD8dOsVUxm8qiNx6BLyUC4ymmaLatBO+H8HND/BaY3g/LsGuqK9Ra9iMDT Y3o3/TJx+EHOqm6cQfAU8DBpN8Tk3Q3WREra7ZZIfGHKPN6g/3Jj/rZ3Xkhnitfzt1Z/ Hlyg== ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/43] target/arm/kvm: Unexport and tidy kvm_arm_sync_mpstate_to_{kvm, qemu} Date: Tue, 19 Dec 2023 19:12:44 +0000 Message-Id: <20231219191307.2895919-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Drop fprintfs and actually use the return values in the callers. This is OK to do since commit 7191f24c7fcf which added the error-check to the generic accel/kvm functions that eventually call into these ones. Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé [PMM: tweak commit message] Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 20 -------------------- target/arm/kvm.c | 23 ++++++----------------- 2 files changed, 6 insertions(+), 37 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index b4339d49d11..8a44a6b762f 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -200,26 +200,6 @@ bool kvm_arm_sve_supported(void); */ int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa); -/** - * kvm_arm_sync_mpstate_to_kvm: - * @cpu: ARMCPU - * - * If supported set the KVM MP_STATE based on QEMU's model. - * - * Returns 0 on success and -1 on failure. - */ -int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu); - -/** - * kvm_arm_sync_mpstate_to_qemu: - * @cpu: ARMCPU - * - * If supported get the MP_STATE from KVM and store in QEMU's model. - * - * Returns 0 on success and aborts on failure. - */ -int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu); - void kvm_arm_vm_state_change(void *opaque, bool running, RunState state); int kvm_arm_vgic_probe(void); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index b8923fe1776..db6d208cf03 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1004,41 +1004,32 @@ void kvm_arm_reset_vcpu(ARMCPU *cpu) /* * Update KVM's MP_STATE based on what QEMU thinks it is */ -int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu) +static int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu) { if (cap_has_mp_state) { struct kvm_mp_state mp_state = { .mp_state = (cpu->power_state == PSCI_OFF) ? KVM_MP_STATE_STOPPED : KVM_MP_STATE_RUNNABLE }; - int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); - if (ret) { - fprintf(stderr, "%s: failed to set MP_STATE %d/%s\n", - __func__, ret, strerror(-ret)); - return -1; - } + return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); } - return 0; } /* * Sync the KVM MP_STATE into QEMU */ -int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) +static int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) { if (cap_has_mp_state) { struct kvm_mp_state mp_state; int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state); if (ret) { - fprintf(stderr, "%s: failed to get MP_STATE %d/%s\n", - __func__, ret, strerror(-ret)); - abort(); + return ret; } cpu->power_state = (mp_state.mp_state == KVM_MP_STATE_STOPPED) ? PSCI_OFF : PSCI_ON; } - return 0; } @@ -2182,9 +2173,7 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } - kvm_arm_sync_mpstate_to_kvm(cpu); - - return ret; + return kvm_arm_sync_mpstate_to_kvm(cpu); } static int kvm_arch_get_fpsimd(CPUState *cs) @@ -2365,7 +2354,7 @@ int kvm_arch_get_registers(CPUState *cs) */ write_list_to_cpustate(cpu); - kvm_arm_sync_mpstate_to_qemu(cpu); + ret = kvm_arm_sync_mpstate_to_qemu(cpu); /* TODO: other registers */ return ret; From patchwork Tue Dec 19 19:12:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755979 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1603438wra; Tue, 19 Dec 2023 11:20:51 -0800 (PST) X-Google-Smtp-Source: AGHT+IFNBqjQbMmqAnreXurUh6v9whedRyegGvvEkScoCn9G4JPdxekrNXlJn4iD5MuvSJ9N83Un X-Received: by 2002:a05:622a:83:b0:423:9512:4bab with SMTP id o3-20020a05622a008300b0042395124babmr25434563qtw.23.1703013651241; Tue, 19 Dec 2023 11:20:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013651; cv=none; d=google.com; s=arc-20160816; b=aCCgkAOVS63s2H2dW0xeVCUfAfJxSgOhpJhirA4XBTygOTMX1H/e9zqzHvd1QO/L1u nE6381gAR51p4WNcLEynjaQ1eaXlYeV9h2jqJLqxuuaABS+9L4iiurod8HfiQjjX0qXQ QvSAa4cybd4HbKgS3G4uZ6Y2CnuTkP1bAM6etvf0mFeOKASApJBxKqOC0H4rEGLSppQG suZwaHQU8+Q/RWXIEdKU70alSmOornZCup/k2RS2kXlaG3uWZF3eg7Tu7bsnuqYlJGPW HNBhm9ZzVjD2YtsAiKWUMUo/xJ5fkx0ZV8YBqMO5BZT9CafsO1+/98zyUywf8lk0hpWj 71sQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hLgC4WHbF5gkYYbt5891jJq9lfv3cmnzjy976cgpXIk=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=WoitEppJgAVBOw/9KajEf4yJr3s/eY0u57uYwW7ge3gBPx/1Y3/8rYU/OMkAMCcteh EXZoDRF8ZC1Lj8L/eDLK8qCYQTiMpaftgPiMq9iPRoxjn06/aY9bIFdXOyDdboPh3ak5 zSYJAinA8OQDgZOh+RQFj5+chheEz8rKp9aV5F7Ix/1XjpEwS8TtnloKl1G1TLsLzy+v O4N8SAbR8kQg+1QZaod8G+3e6cgbdvYBxcoeVjRSqeqdctmdBKCpdDUl6VxnN/RINlqe C/gpuGoRidcq5gzk8PQ7pV4Ge4OY5nZCyRGIqzgK1xsVtekDxgWK0sTW9RF8BIhzZUgV k2HQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GFu0xqpB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/43] target/arm/kvm: Unexport kvm_arm_vm_state_change Date: Tue, 19 Dec 2023 19:12:45 +0000 Message-Id: <20231219191307.2895919-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 2 -- target/arm/kvm.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 8a44a6b762f..2037b2d7ea8 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -200,8 +200,6 @@ bool kvm_arm_sve_supported(void); */ int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa); -void kvm_arm_vm_state_change(void *opaque, bool running, RunState state); - int kvm_arm_vgic_probe(void); void kvm_arm_pmu_set_irq(CPUState *cs, int irq); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index db6d208cf03..41fffef5ef1 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1288,7 +1288,7 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) return MEMTXATTRS_UNSPECIFIED; } -void kvm_arm_vm_state_change(void *opaque, bool running, RunState state) +static void kvm_arm_vm_state_change(void *opaque, bool running, RunState state) { CPUState *cs = opaque; ARMCPU *cpu = ARM_CPU(cs); From patchwork Tue Dec 19 19:12:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755982 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1603543wra; Tue, 19 Dec 2023 11:21:05 -0800 (PST) X-Google-Smtp-Source: AGHT+IG/2C36ifLpSeVe6xNexg/mMJtrYRVNodVW2Mx8JPk8Q7F5qtbqvhNgjefPz6H/fOzN1fOT X-Received: by 2002:a05:620a:4145:b0:77f:428:a787 with SMTP id k5-20020a05620a414500b0077f0428a787mr21359482qko.0.1703013665618; Tue, 19 Dec 2023 11:21:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013665; cv=none; d=google.com; s=arc-20160816; b=v2/5zZM2qUYdDEUAXBN864VfdSCW4rdIiONOoLm9tG/Trk0WsIvkcE+7L/dsTuBTLl MsJaqEdf3cI0f+QXJph0byQqOnuw1jiC6LyyxUC3HJqeUXVb49vM0cK4GJp5Zr3lQdHk nH/la+caymU6KwClp5ERoOQQgLmTCPGKqmdDowsTcyRInPvOuu+mHzmshCQgJNyzGfnG lVdiqZxJgbaBvUmMO1VgsL7wcjfM59fe8gfD8gkitSSpWpKSgNly+XOIW5qjQuEBJhn0 Kn0PlbMk0ldWrrWhwnytZHLWwkasJGdy7QdMtx5LBVE4/SFr3kAL/DjolY7jMRXL8N/R TQ7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tjJ6DjjrNF4YS1GYLScIKt9PiPvca+RdqzW7lzNYdLU=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=xOz5t0srp2PW808zqWJ4tNZe2HHuOdm9uiGe5qagGNwZTxWwVClGw7zdt21fBKi+iv Q3yZnw8FdHNLBROw2m2E0HHU9FIB3qfQQyMMo+SbMoPapK5gCdoBzu8B5I2uERW3P6pQ 02sD6G0QZMneWgpecOcgErQ/DyEV4f8IVPDx16LOhuVi0I2FgcspsqWqkKvKcet7TAXK 5kVT8Dn+X7kYlU/1liMzvpidlyqt6DcG5KrLoF/QsHb2WRz2xsr9nACWacn8ZhWkO9Dw GTvFh+IkQNt40wjG/p9vauQWjJ7REhXRx1uRnFJ0OcBwc5DlomO4Y4TSZa5imAla0fDV AVdQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OIjeD+r8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/43] hw/intc/arm_gicv3: Include missing 'qemu/error-report.h' header Date: Tue, 19 Dec 2023 19:12:46 +0000 Message-Id: <20231219191307.2895919-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SPACE_RATIO=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé kvm_arm_its_reset_hold() calls warn_report(), itself declared in "qemu/error-report.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-2-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_its_kvm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index f7df602cfff..3befc960db2 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/error-report.h" #include "hw/intc/arm_gicv3_its_common.h" #include "hw/qdev-properties.h" #include "sysemu/runstate.h" From patchwork Tue Dec 19 19:12:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755946 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1600248wra; Tue, 19 Dec 2023 11:14:41 -0800 (PST) X-Google-Smtp-Source: AGHT+IEMMfj+Y/VxqG0HsRPoFLltwG9sUPw9DcajXJyrEhEHs9z8n+L+l4G6WK8aGNj9qWEFagaS X-Received: by 2002:a05:6830:1503:b0:6d9:e667:d462 with SMTP id k3-20020a056830150300b006d9e667d462mr17832473otp.30.1703013280687; Tue, 19 Dec 2023 11:14:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013280; cv=none; d=google.com; s=arc-20160816; b=ODNQnwKWXs160oWa5vUqJpOCitvn9kULFB/ipptevcnU5OMYSOk/hOr5Hue4f92q0j Qs/RCKIsGDiJslDXihFm8TJPd5yflq1vj/lrlpB2OyKhbd7OW/lcjewhHYuc/DVwp0jI I1QJLuyglcHYNI0QlYstR92jcajkkdOceU/CgX2RrQBCtSzDNh86jiKxRJRYxM/CT/85 ky9U7vNjOUIz3P9ZK+UMHZYlnVxZ1qa5En0vQ2Juf4M2mt7l0WpJRnyCcA7SJBpCdttU qAWrFmCREHxclFap4M5JCj9jjxA2B5xL75a3oc8VBNxrp+pHDRgShMIh7E7nudh90Sm7 aY9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RDIBMPpY2c044rUIduHvSX5HNjBWclM55GKfwRyQOZQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=cjTvaw0f5EAc3Bj/ZV18ZxRA8D14akw7rRsV6muq0Ll1/oqAJnxSk4kiDGQ3LfX6bS sk7rwMTplCb4zJliEVYAISFZlsxkZ+hrVtIBvfGvfNSHBHjRb7my7M9NlazKe7paQf5F Xf2IJNVl2EMSMjCpeQ2PB522o0DDD3OiEXlCoi3ItBFJtaknB4ifASFuJilwUZ9I2eHV j9oANV3F9vRQaEzeJTgOKs9QAeZ2f1csehjp3n95OZKNFaxQc090rBF9As3vVMFcQfxT yQueK4uT3ifzTTRrz7OQzS7JKPZMTqsFIa/mlqVXE8oh5n84soZsRAlv3g37di7wBbYN iVrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XIR+c8Uq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/43] target/arm/kvm: Remove unused includes Date: Tue, 19 Dec 2023 19:12:47 +0000 Message-Id: <20231219191307.2895919-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Both MemoryRegion and Error types are forward declared in "qemu/typedefs.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-3-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 2037b2d7ea8..50967f4ae9c 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -12,8 +12,6 @@ #define QEMU_KVM_ARM_H #include "sysemu/kvm.h" -#include "exec/memory.h" -#include "qemu/error-report.h" #define KVM_ARM_VGIC_V2 (1 << 0) #define KVM_ARM_VGIC_V3 (1 << 1) From patchwork Tue Dec 19 19:12:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755958 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1601591wra; Tue, 19 Dec 2023 11:17:01 -0800 (PST) X-Google-Smtp-Source: AGHT+IFP+jEHmYpNc2TsggdqV7TCQrMiFxR3lRFvwmgTlbg0/avggvKzSNT3c9hrE27nxiRmbXPe X-Received: by 2002:a05:620a:29d6:b0:77d:c890:6b68 with SMTP id s22-20020a05620a29d600b0077dc8906b68mr24310312qkp.32.1703013420977; Tue, 19 Dec 2023 11:17:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013420; cv=none; d=google.com; s=arc-20160816; b=xxEcjOIvoRBkwxzex8lw0WZnpW/gFAGB/ZR1t6UJVAvmu/VMXXBNa/8+lQNn7Q9ixB C4tuimYLvJ76LVI7IB7wj+SSII01UzqlgMD0CPsZ5aheSnclXRoQNGBW3gR1lJWPPEri 4GEsDlgneizw0JDgj3GGLxe4LrYMnzASl9mMezh2VUpMPNLD1e5cQiq8aHEyHLgq3LUC uAbcjwMHUjpnV20jWHPLfNR1ySfheGucw/Kt1VxUH/+KSl3j+pEEAS1jSaDN6E90HajW LiYqSWVLTZMQDCiEOZMrtKs97y0EfLeeyGi6cdHOJgcDJ2n02GQycjWDwummT+WAYGB8 bLbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=f99Ujt99QMeF21Uqr8srLUFwBNPf96V7ucD7nm9URUA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=n3nvPhHd83va7THY1ctvYiJHEq0b8RJElKm5dQxJiY0w0z8seRO7NdpiZ8xsobWXL2 z45jIr8xvCrobkQ8pwq3qNO2SwvFMC6SpNYDoC1RIGzvKoGtROzqvshNks1em5m7zEbV 660E+nxLI0BCzE7a08KSj6GqVOq3DG1pTCxot1wNkGnEazJf99B07wl4lt7ghEHnEa9D cqFhJ1nLWA/H6SYY0HJrFnqD2yVq+FSjA5AfALaPznKuzTY+BF82g4Mn/e/FMZpeOT9W +53Xx1WjDYddQaZtD48VIF4y2C6lPUnUH4/2/cmYyc6QGJW0Z29lQK+4L0W8dgxYhHr0 YEmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ctw0gsEQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/43] target/arm/kvm: Have kvm_arm_add_vcpu_properties take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:48 +0000 Message-Id: <20231219191307.2895919-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-4-philmd@linaro.org [PMM: fix parameter name in doc comment too] Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 6 +++--- target/arm/cpu.c | 2 +- target/arm/kvm.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 50967f4ae9c..3abbef02601 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -148,12 +148,12 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); /** * kvm_arm_add_vcpu_properties: - * @obj: The CPU object to add the properties to + * @cpu: The CPU object to add the properties to * * Add all KVM specific CPU properties to the CPU object. These * are the CPU properties with "kvm-" prefixed names. */ -void kvm_arm_add_vcpu_properties(Object *obj); +void kvm_arm_add_vcpu_properties(ARMCPU *cpu); /** * kvm_arm_steal_time_finalize: @@ -243,7 +243,7 @@ static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) g_assert_not_reached(); } -static inline void kvm_arm_add_vcpu_properties(Object *obj) +static inline void kvm_arm_add_vcpu_properties(ARMCPU *cpu) { g_assert_not_reached(); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index efb22a87f9e..650e09b29c5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1686,7 +1686,7 @@ void arm_cpu_post_init(Object *obj) } if (kvm_enabled()) { - kvm_arm_add_vcpu_properties(obj); + kvm_arm_add_vcpu_properties(cpu); } #ifndef CONFIG_USER_ONLY diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 41fffef5ef1..e5a2596890b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -497,10 +497,10 @@ static void kvm_steal_time_set(Object *obj, bool value, Error **errp) } /* KVM VCPU properties should be prefixed with "kvm-". */ -void kvm_arm_add_vcpu_properties(Object *obj) +void kvm_arm_add_vcpu_properties(ARMCPU *cpu) { - ARMCPU *cpu = ARM_CPU(obj); CPUARMState *env = &cpu->env; + Object *obj = OBJECT(cpu); if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { cpu->kvm_adjvtime = true; From patchwork Tue Dec 19 19:12:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755950 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1600781wra; Tue, 19 Dec 2023 11:15:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IFKvMGiVS0ejEylJ8+RqCxDTxjf7vhh1sgBNBur28BN9Bfx7/4YnQO/n6evoSSx39V6b1kU X-Received: by 2002:a05:620a:4891:b0:77d:cfff:3420 with SMTP id ea17-20020a05620a489100b0077dcfff3420mr26469576qkb.9.1703013332062; Tue, 19 Dec 2023 11:15:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013332; cv=none; d=google.com; s=arc-20160816; b=Upts4ZdD3UVArvC7+n5HPgOvbUPkIU60iQ4Zn60t5nnI98R7AHQtEOjOiTq3G1np6B eOck7WtG0fwT2O1Bby6S48Jr2GVvxjCcLejdryjKUF974940wTYITgkpq6TscxsuRHD7 JCLtokZVoyNpOM7fGlB1PG0PXR7pGMBlxtipLSebUTKza+Qb9KVkAesa7FEExFWqyQJc 3FxlZugWWVk1VCunMaF4VsWZHX/GDtWjKESdXxOicSPPlxj/uiwPDZWXwcHC29YW4EdV 0BPj8NrT3qJXD5zJRTVv6oij6LuiKEx2LE/WLZGjiXBPZ9H8DcFzvGsNa72RLcNLw60k ZC4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=d/ifw9z6r6bmX0fdH0IVqZ7YqgrTTUGMwKeFbCj1mN8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=qhfng6VLuNP/DeoLZRyPO/AtuqO5lWUBcJ7JaMRo0XkkPLWCn2vnC8Ga98uygtQj4c WxQ/TeO5ZpjhhQtRUBBFxhsbwICQfUnKGay2kHzhc4R8QUZPpp7AqLi4vImz658/GG7q vh0+K8FmWhOLCYZ93xnKuLCuChTtEXdQ0lpr+Qi9ZKFGKQ6j1kvVPcgupkId4aI73E7l c4I92TPtd3y/KEnyWMrg+XYSobkuSpquXzLOyhI+kYUfYXUqNjvcUTyZz1y8/d3M91GN JsDRbXIsBRA8mafAQ6osKj0exXA5E1cg9tJEWUYpu4zzqxmkbxY4Bja9abvfND3051Et aGmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lUHh8iXg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/43] target/arm/kvm: Have kvm_arm_sve_set_vls take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:49 +0000 Message-Id: <20231219191307.2895919-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-5-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index e5a2596890b..e9c6e2e17c1 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1855,14 +1855,13 @@ uint32_t kvm_arm_sve_get_vls(CPUState *cs) return vls[0]; } -static int kvm_arm_sve_set_vls(CPUState *cs) +static int kvm_arm_sve_set_vls(ARMCPU *cpu) { - ARMCPU *cpu = ARM_CPU(cs); uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map }; assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX); - return kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_VLS, &vls[0]); + return kvm_set_one_reg(CPU(cpu), KVM_REG_ARM64_SVE_VLS, &vls[0]); } #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 @@ -1919,7 +1918,7 @@ int kvm_arch_init_vcpu(CPUState *cs) } if (cpu_isar_feature(aa64_sve, cpu)) { - ret = kvm_arm_sve_set_vls(cs); + ret = kvm_arm_sve_set_vls(cpu); if (ret) { return ret; } From patchwork Tue Dec 19 19:12:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755959 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1601866wra; Tue, 19 Dec 2023 11:17:37 -0800 (PST) X-Google-Smtp-Source: AGHT+IE+EmZzOBxN4mejsWfvR/XcUdC4wWykWEfmBdoS5F47Cby5JDwFgWJmPlk4Q+JepOo/xASU X-Received: by 2002:ae9:f510:0:b0:77f:37e2:1726 with SMTP id o16-20020ae9f510000000b0077f37e21726mr2194263qkg.71.1703013457384; Tue, 19 Dec 2023 11:17:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013457; cv=none; d=google.com; s=arc-20160816; b=nwowK1tEIruCCFk/NoFcbVIp2gnoRn4KpDJgN1ClmdeBdzu3R+XNaDaSva9rQlkgUU YLxJKqdCEE4wFyW8aVQQ3+i81VxaP14wLF7X3burFWmN1s4vENTUWASzCz6DKHfLVW8h tZcHQBtyhmz4G/Ewls7k69mXJQyc/WNmfPHUtTuxRF3woPYetQzGVf75lhoi3xG/KrSi BTqgwKhig/Mt2LZlUYwY8oJzfvkVHSYwgDGAoJ21n7J/1EBaUwfaX1/yAzxwqRhlC4Vt jwcHdLbotVXZW8HwpD5BpLW0g/XNY9MCa7b9I1olQojYD8u7OK5o4fAKM/AqAumsJmOI Tatw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=h3V71XAx3UDA0zBtoUkIA2yNtSzC2BWFrBTkEOk1jT4=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=FUbdNHn/qJkxd5JAqypNpsG3q3FRuTQW/6z3QQKFjM6kxpj5mTHeFzsDDkiqUFvXxh FPsjUh6zL+/EamtaG5CW9i6NplDM63TF2UZpsb3MGh5HhHIeIBLwJL8WAnop8/m7nzs6 tgkFcoXJkBXcIlOLzj5LyyLKMfZaR+Nc/npYO8HaJ4cojyImxJJt60WeiFrD9S5Rc0yM FamWkvT+6DOqsmHd9ZDBN2PI9pM5OJ3f8OYF+EwGB8sXi/LAPsnNKO9fuM11myH9hmef LoCT4ty1P9PlVyjLBcbsDKgFa0YK/1fcYfu2xyxPkI4OdbvDaeKsj90fbVfpu+6gFN+S FUiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rHYclgNF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/43] target/arm/kvm: Have kvm_arm_sve_get_vls take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:50 +0000 Message-Id: <20231219191307.2895919-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-6-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 6 +++--- target/arm/cpu64.c | 2 +- target/arm/kvm.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 3abbef02601..d6d999b1ff8 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -129,13 +129,13 @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); /** * kvm_arm_sve_get_vls: - * @cs: CPUState + * @cpu: ARMCPU * * Get all the SVE vector lengths supported by the KVM host, setting * the bits corresponding to their length in quadwords minus one * (vq - 1) up to ARM_MAX_VQ. Return the resulting map. */ -uint32_t kvm_arm_sve_get_vls(CPUState *cs); +uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu); /** * kvm_arm_set_cpu_features_from_host: @@ -278,7 +278,7 @@ static inline void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) g_assert_not_reached(); } -static inline uint32_t kvm_arm_sve_get_vls(CPUState *cs) +static inline uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu) { g_assert_not_reached(); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1e9c6c85aec..8e30a7993ea 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -66,7 +66,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) */ if (kvm_enabled()) { if (kvm_arm_sve_supported()) { - cpu->sve_vq.supported = kvm_arm_sve_get_vls(CPU(cpu)); + cpu->sve_vq.supported = kvm_arm_sve_get_vls(cpu); vq_supported = cpu->sve_vq.supported; } else { assert(!cpu_isar_feature(aa64_sve, cpu)); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index e9c6e2e17c1..132a1b47d04 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1801,7 +1801,7 @@ bool kvm_arm_sve_supported(void) QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1); -uint32_t kvm_arm_sve_get_vls(CPUState *cs) +uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu) { /* Only call this function if kvm_arm_sve_supported() returns true. */ static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; From patchwork Tue Dec 19 19:12:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755947 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1600429wra; Tue, 19 Dec 2023 11:15:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IF5LyXA85vx73aA4uAv/34phEGmmdHO5XAh8+jsFp2sw4ocfPrda3QLqewA2hMixmSRxKfH X-Received: by 2002:a05:6214:400d:b0:67f:33e3:7645 with SMTP id kd13-20020a056214400d00b0067f33e37645mr6523137qvb.102.1703013299974; Tue, 19 Dec 2023 11:14:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013299; cv=none; d=google.com; s=arc-20160816; b=EYvc/f34ENF1Xyx6G3GEVo8vKhQz2cjL708ZP5TmCn9tGmotsyipXDXewVHG4spLeI nbfqQReMHf0D5cufA2qzJtg4rFCBvcDjtiVTImTO8dGvfsgp7r0KlGXw7rvg3RcKC6NM U2fKKlb7akEZWD4LuyBdIiPKFGntMG4SdUjouCA0zqNdnGxC3kUP9XxcKgF6Jwcz6gGs AGozM5MgZLaSGQ2y5A5yeaXuTm3wbb1jvrwbgctLkbOAY08c9pB+1xNqnRE0o6bSmIod hwi7pwFFyxAeNVGl2QRGtr2M/r6Lj3rAaGX73nh3yxkC+GCDwT0yLEJdfbRCSvTvNgzN 1btA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3ZO8ztgowbV18Gzw4fuVGRHf6IPf5T0BjvZrFbeykXA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=RyquLje1tfFrbbWaB+VtKLCj8Vxu7JGL2qM6ODnMysXcqiyyRa2Bm4r1HpI2sz0vMZ mJnmTehEf3m5z/03upVDm6ODylmp5dW7wFZW8FHggz6oxSNDuDcMI3HSo5x5N2aKmhJh ZsTQ66nV0S1PMnFAG+mD9DvehW/XzQJHPnUSM7ZcUcdaqxBxjEVMn486X6+rvmYACYyx gjk5n27trnHM7IdacG4WibHMVY/MMrMg+95Ea9Hfpoi25B5W/jx5BVgCyRka2/TCE8Fb aCZTZFJGgKiAgjY0Ewoiu081WIUaQrPGcTQNSUPtO12h/d6NtowxGPaXNdU6D2XhrH2x Tn6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vXgcGQWm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/43] target/arm/kvm: Have kvm_arm_set_device_attr take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:51 +0000 Message-Id: <20231219191307.2895919-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-7-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 132a1b47d04..e6423d2720b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1689,18 +1689,18 @@ void kvm_arch_remove_all_hw_breakpoints(void) } } -static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *attr, +static bool kvm_arm_set_device_attr(ARMCPU *cpu, struct kvm_device_attr *attr, const char *name) { int err; - err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); + err = kvm_vcpu_ioctl(CPU(cpu), KVM_HAS_DEVICE_ATTR, attr); if (err != 0) { error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err)); return false; } - err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr); + err = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEVICE_ATTR, attr); if (err != 0) { error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err)); return false; @@ -1719,7 +1719,7 @@ void kvm_arm_pmu_init(CPUState *cs) if (!ARM_CPU(cs)->has_pmu) { return; } - if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { + if (!kvm_arm_set_device_attr(ARM_CPU(cs), &attr, "PMU")) { error_report("failed to init PMU"); abort(); } @@ -1736,7 +1736,7 @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq) if (!ARM_CPU(cs)->has_pmu) { return; } - if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { + if (!kvm_arm_set_device_attr(ARM_CPU(cs), &attr, "PMU")) { error_report("failed to set irq for PMU"); abort(); } @@ -1753,7 +1753,7 @@ void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) if (ARM_CPU(cs)->kvm_steal_time == ON_OFF_AUTO_OFF) { return; } - if (!kvm_arm_set_device_attr(cs, &attr, "PVTIME IPA")) { + if (!kvm_arm_set_device_attr(ARM_CPU(cs), &attr, "PVTIME IPA")) { error_report("failed to init PVTIME IPA"); abort(); } From patchwork Tue Dec 19 19:12:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755952 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1600932wra; Tue, 19 Dec 2023 11:15:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IHBWpMybh/oDULSd7i9wEhNtp9NVJxszmt+uurD4ubTx5EhuP33985sSR2CXHIi+0jycWUq X-Received: by 2002:a05:620a:563a:b0:77e:fba3:a20b with SMTP id vv26-20020a05620a563a00b0077efba3a20bmr20317472qkn.101.1703013346374; Tue, 19 Dec 2023 11:15:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013346; cv=none; d=google.com; s=arc-20160816; b=LBRGHD++K3LLunmGHDjd66fuiRgU12VYywhADsdsfzxcRiey7EZqeJZA9toL7MSW4h EWPF6RnXL6zOpmgR9+uAM3GPTyLHfgy4vDQGB32jDgIYpN2OJ3QT5mjufoujzUQz/749 jrtrrgnkJ07B0yIf3+d9k5f56t1ZHmzHiyp2kMocZdaLKeUAAHevWQnhSBvUghTLnLN5 V29fzFQ6Jznfn7r11Us+0mg2g/QbGcV/tvYwlD0z0Unc8Q2k2Q01Gj/pIhFzdx1tDAi/ FQirE2yf1hkOM5ItQWY/8lVjqheqs5Lh+s5cHZnlEhWWyoxd49WbyIgUqVG+EpQ309fb DiJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6zD6GqgpYlUbqN0SJRkAPG9ZDb0+QKHBj7N0uvLGJQI=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=tSudIWRJVP8O1mSgjDJdms61KN8YlnDIRuhGcUOs5Mp1pgmDfsWu41aDYeVZqqrWev BTvAxKbBfxIzOIcOxy5tn/LZRWFoirH1QdZO0TXYUgnv6Pw4gJnrhIwpywDEvABdTMCO ZgWND6VEZ/mPTPxgS0bayH1PX+ZeqSRaNonKOar5GuybfQ2V+mHEs0DWB1ZdmbwCGSOP AmL8CtjBAbcTw3oemajhJGhbEFjj4Yh5rgprlFCjjVWBfPz2slwZvnOSsQjf2hHst4vu HttPGPpJV2NHf+A7YC7zKrsRE+gA83f3ZUgxsB3WkI2dQtrRs9S5W7xlhvBeo3+pgJQN mUOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=V1pOi+0O; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/43] target/arm/kvm: Have kvm_arm_pvtime_init take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:52 +0000 Message-Id: <20231219191307.2895919-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-8-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 6 +++--- hw/arm/virt.c | 5 +++-- target/arm/kvm.c | 6 +++--- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index d6d999b1ff8..4404ffeb1e3 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -205,12 +205,12 @@ void kvm_arm_pmu_init(CPUState *cs); /** * kvm_arm_pvtime_init: - * @cs: CPUState + * @cpu: ARMCPU * @ipa: Per-vcpu guest physical base address of the pvtime structures * * Initializes PVTIME for the VCPU, setting the PVTIME IPA to @ipa. */ -void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa); +void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa); int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); @@ -268,7 +268,7 @@ static inline void kvm_arm_pmu_init(CPUState *cs) g_assert_not_reached(); } -static inline void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) +static inline void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa) { g_assert_not_reached(); } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index be2856c018a..b6efe9da4dd 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2003,8 +2003,9 @@ static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) kvm_arm_pmu_init(cpu); } if (steal_time) { - kvm_arm_pvtime_init(cpu, pvtime_reg_base + - cpu->cpu_index * PVTIME_SIZE_PER_CPU); + kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base + + cpu->cpu_index + * PVTIME_SIZE_PER_CPU); } } } else { diff --git a/target/arm/kvm.c b/target/arm/kvm.c index e6423d2720b..dbaebe9cd2c 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1742,7 +1742,7 @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq) } } -void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) +void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa) { struct kvm_device_attr attr = { .group = KVM_ARM_VCPU_PVTIME_CTRL, @@ -1750,10 +1750,10 @@ void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) .addr = (uint64_t)&ipa, }; - if (ARM_CPU(cs)->kvm_steal_time == ON_OFF_AUTO_OFF) { + if (cpu->kvm_steal_time == ON_OFF_AUTO_OFF) { return; } - if (!kvm_arm_set_device_attr(ARM_CPU(cs), &attr, "PVTIME IPA")) { + if (!kvm_arm_set_device_attr(cpu, &attr, "PVTIME IPA")) { error_report("failed to init PVTIME IPA"); abort(); } From patchwork Tue Dec 19 19:12:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755963 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1601932wra; Tue, 19 Dec 2023 11:17:43 -0800 (PST) X-Google-Smtp-Source: AGHT+IFW7Tw9w7cd0z0QrtWQwRJ9Gdx/qGmjWJhgmweVMeM4ZQi2ep/56D3WSXyYAMwt5Auz889f X-Received: by 2002:a05:620a:5346:b0:77f:c0b4:8ad3 with SMTP id op6-20020a05620a534600b0077fc0b48ad3mr6723624qkn.90.1703013463164; Tue, 19 Dec 2023 11:17:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013463; cv=none; d=google.com; s=arc-20160816; b=P0w6unmBk8auJbandy38vKNnqUWOkEDg9SldxJ6rhIUOEP7Qz4iT80A8rePb7aXAj0 c0ko9bfFQqQAeTWXShCbuOo/G3c8AMgudbDHiCyQ8u38pQpwkYrwnP0uou90h1kds6do MzuS48LEYmI4rkpeKcwmPCJ15ai/4tu+u80nX6thO6C+GBRx5GP4q512iRSUIbziwWMA TlsZZdoa2lDjRwKuehpdno8K523iS3G4gYlHyR25eUQmJ/aV1zYO3mcZgn7QBgi/bZQ1 rSaVuF8BJDFW5fywV02FDe6NSI+ly+wenQCxGDTOSdVlc0nv5RPLuNVGKo+jakrTQL8T KqDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IYhSIE/aRJaOrscSujAdKlBizLG69eYQKoHwvZcrqCs=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=KPqVQndnWiqEKb38XTIjEJBGBxWgJ900SuqubTEpqK5olrGPSo4thPOrcLGrvECWLx tU9itQs2HmebNVUW9oKT2BfANG+CTgpCJKuyfEg10NInG6y++juAa+RdazJ+w/xvyObd wnutFcdJ/KlFy5YEa79ZoOcVOnMRM7k/RXvH4T2C9ovCHKcLn7jMPmAQeFkjLX1sKddZ JV6PnAYE8+4/M/PV+Zv03pW13J6xz7YZs+TYvf/gmQvvPai1E42nL/0JTdRr4V82Bwbj PIkTUnwMa2p+5jdBoKQTfJ9RXk1LLPraODoLyDC6HZ3giUsmxRyn/O4UKRcM4Ox45j77 BuiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mfoFwr0y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/43] target/arm/kvm: Have kvm_arm_pmu_init take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:53 +0000 Message-Id: <20231219191307.2895919-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-9-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 4 ++-- hw/arm/virt.c | 2 +- target/arm/kvm.c | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 4404ffeb1e3..0a79545aa12 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -200,8 +200,8 @@ int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa); int kvm_arm_vgic_probe(void); +void kvm_arm_pmu_init(ARMCPU *cpu); void kvm_arm_pmu_set_irq(CPUState *cs, int irq); -void kvm_arm_pmu_init(CPUState *cs); /** * kvm_arm_pvtime_init: @@ -263,7 +263,7 @@ static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) g_assert_not_reached(); } -static inline void kvm_arm_pmu_init(CPUState *cs) +static inline void kvm_arm_pmu_init(ARMCPU *cpu) { g_assert_not_reached(); } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b6efe9da4dd..63f3c0b7502 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2000,7 +2000,7 @@ static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) if (kvm_irqchip_in_kernel()) { kvm_arm_pmu_set_irq(cpu, VIRTUAL_PMU_IRQ); } - kvm_arm_pmu_init(cpu); + kvm_arm_pmu_init(ARM_CPU(cpu)); } if (steal_time) { kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base diff --git a/target/arm/kvm.c b/target/arm/kvm.c index dbaebe9cd2c..1e52077a9ce 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1709,17 +1709,17 @@ static bool kvm_arm_set_device_attr(ARMCPU *cpu, struct kvm_device_attr *attr, return true; } -void kvm_arm_pmu_init(CPUState *cs) +void kvm_arm_pmu_init(ARMCPU *cpu) { struct kvm_device_attr attr = { .group = KVM_ARM_VCPU_PMU_V3_CTRL, .attr = KVM_ARM_VCPU_PMU_V3_INIT, }; - if (!ARM_CPU(cs)->has_pmu) { + if (!cpu->has_pmu) { return; } - if (!kvm_arm_set_device_attr(ARM_CPU(cs), &attr, "PMU")) { + if (!kvm_arm_set_device_attr(cpu, &attr, "PMU")) { error_report("failed to init PMU"); abort(); } From patchwork Tue Dec 19 19:12:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755981 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1603522wra; Tue, 19 Dec 2023 11:21:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IGY6QjabWLKOusb9l4Me0+kisFBFRErFB9m4lZqga1Kd0YfeXr9JYhBPcigod0ZRfSz1cl3 X-Received: by 2002:ae9:f443:0:b0:781:f1f:7e74 with SMTP id z3-20020ae9f443000000b007810f1f7e74mr287007qkl.15.1703013663311; Tue, 19 Dec 2023 11:21:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013663; cv=none; d=google.com; s=arc-20160816; b=Xrtvf6uv74NInGQ6PCp4XHjFq26Ei5jZaKMRJ7Rsd+YXWGGAhJEcFAB+MF3zb3xkAK XP3yteJwBX38/ytq+jf6Nmvo+EbREyaHMePqh5abWwxc+LoJhRiAzWFPjS7qwQxhdi7Q uSNwcSLXS6Paxwo4SnQA4jN/QHotwtFm76Cc44LELhkCbZDLA0KU7fOHTRYkmhXeZY/a oL1lqzSZYMZ4nwyTtnEXEJZPMA4coYLSo4MpgGoPAFM3TuWr6nTJAfI6dNXwKrRO25xP jXMMFnKTREyDj/R3s/8zZu1IPyv5OT8JySOMBJA3rqFOOggbQMsKx6T93B1LTbdlrCru Ef6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=oMXiDjXN47Sje7EpZy9Ne96GwzFBEmIGwHarjbgxxck=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=PdGzi6+PfEZF6SAdpDaQFDvOYCed+uyyMVPhn1kpKFZfSfgEXiPx/KxHR+m7fXPhgW 2ySSDJYbXCTlTBLZ0sNIHOn1WePxZrmvWtqa8Lr+qQpbjwA/inviPnXJMG1VGieYDm5w rJlnoqOK5hQKg3/CcI0Fr5qaZQmOZTdUy8AH5QtMp9JMDw4eRX8SYu777H1ztf9ro1dG sIf6tcUEcPFLbWLGI6OCord5jOqNeEJjl6TgKJSwZ48wcKuInLv4O0D/2Ya1DMoE+etQ MRNVfgcE+P2Qn4Wu2G2GO7LnPvMES6uPpoFeznsOlrXOfPEUVCgc14mc2WyMt67fE+FI 5EOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fYUZ6NC8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/43] target/arm/kvm: Have kvm_arm_pmu_set_irq take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:54 +0000 Message-Id: <20231219191307.2895919-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-10-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 4 ++-- hw/arm/virt.c | 2 +- target/arm/kvm.c | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 0a79545aa12..cfaa0d9bc71 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -201,7 +201,7 @@ int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa); int kvm_arm_vgic_probe(void); void kvm_arm_pmu_init(ARMCPU *cpu); -void kvm_arm_pmu_set_irq(CPUState *cs, int irq); +void kvm_arm_pmu_set_irq(ARMCPU *cpu, int irq); /** * kvm_arm_pvtime_init: @@ -258,7 +258,7 @@ static inline int kvm_arm_vgic_probe(void) g_assert_not_reached(); } -static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) +static inline void kvm_arm_pmu_set_irq(ARMCPU *cpu, int irq) { g_assert_not_reached(); } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 63f3c0b7502..040ca2d7948 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1998,7 +1998,7 @@ static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) if (pmu) { assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); if (kvm_irqchip_in_kernel()) { - kvm_arm_pmu_set_irq(cpu, VIRTUAL_PMU_IRQ); + kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ); } kvm_arm_pmu_init(ARM_CPU(cpu)); } diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 1e52077a9ce..45ee491a56b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1725,7 +1725,7 @@ void kvm_arm_pmu_init(ARMCPU *cpu) } } -void kvm_arm_pmu_set_irq(CPUState *cs, int irq) +void kvm_arm_pmu_set_irq(ARMCPU *cpu, int irq) { struct kvm_device_attr attr = { .group = KVM_ARM_VCPU_PMU_V3_CTRL, @@ -1733,10 +1733,10 @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq) .attr = KVM_ARM_VCPU_PMU_V3_IRQ, }; - if (!ARM_CPU(cs)->has_pmu) { + if (!cpu->has_pmu) { return; } - if (!kvm_arm_set_device_attr(ARM_CPU(cs), &attr, "PMU")) { + if (!kvm_arm_set_device_attr(cpu, &attr, "PMU")) { error_report("failed to set irq for PMU"); abort(); } From patchwork Tue Dec 19 19:12:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755945 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1600240wra; Tue, 19 Dec 2023 11:14:39 -0800 (PST) X-Google-Smtp-Source: AGHT+IHPyKh6+ionn4u8QBKLZft1xsUbSd2LvKbamXEgLB7zrc+5xiJHspP1p74gu5JYz1etV294 X-Received: by 2002:a05:620a:800a:b0:77f:16e:8df1 with SMTP id ee10-20020a05620a800a00b0077f016e8df1mr24089037qkb.58.1703013279577; Tue, 19 Dec 2023 11:14:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013279; cv=none; d=google.com; s=arc-20160816; b=vP6BBqxme5eziQP9t5fhRLGhSXdxuuSAM6gCjYlCyTTHWdMYDg8AF4F0cRQgu2nPJ+ il2+dsUi1kLwq/AjdXBqD+WkH+9F0S8c+rwlvEeTn1CS7dcmT8uyMQKldKWb074lEukS N5CUdRubI/yjLY2dScXVI05p4JHL02DIbW7g6pa4y+oWgjGrPBfE0p6ZFeqykHvX8amB 1jPCMikFQIJBNBm32u0VMQ656XY27GuN+pQ9xd+tdJnFA3M6uCCLj1ukZkNUPJNBGWdm 5nJp4gcGbt3MkT+sVVJk4HDLA3KQUIm/IPUVyxjXhq1zmFPTBqNhUwrL2JHYiarE+Phj 63Yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WTa4ndbkRJ7n5XD1OTvmDhz9DP3vcZ/79akTztoRHzs=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=V6TIApPzDjVI97JqofssgyYTUXMqdWX5BvqCYa1Pe+ErGgTTr093/yEF2YnNL5Malq 8ydV9WEVTGCe6GPphLTHTvvJYpaWhdevxL4/DBJpquZyy1K0V1UY/mJpfEkqx73qGg6q E3faNvO0OtYnm7c8Hxg+Y/oLR2eLnlonNaaW1TMe/y0U8LBFT2VH6Kpq2IFoZauzXTTl MKxSAkkOY3h+j0bl2pOQ+JPwZLAmosEM0DejffISRJNlMUntUS1KJwbp0HkGdBvhLY4U X6AtkKeszNTSM1jo9xLUTX8MGipHqWMy81wB617kwb6znMpWiMOkYXW34IO8bcsYmYQ+ PmWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="sGbsg/U7"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/43] target/arm/kvm: Have kvm_arm_vcpu_init take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:55 +0000 Message-Id: <20231219191307.2895919-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-11-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 45ee491a56b..9540d3cb618 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -62,7 +62,7 @@ static ARMHostCPUFeatures arm_host_cpu_features; /** * kvm_arm_vcpu_init: - * @cs: CPUState + * @cpu: ARMCPU * * Initialize (or reinitialize) the VCPU by invoking the * KVM_ARM_VCPU_INIT ioctl with the CPU type and feature @@ -70,15 +70,14 @@ static ARMHostCPUFeatures arm_host_cpu_features; * * Returns: 0 if success else < 0 error code */ -static int kvm_arm_vcpu_init(CPUState *cs) +static int kvm_arm_vcpu_init(ARMCPU *cpu) { - ARMCPU *cpu = ARM_CPU(cs); struct kvm_vcpu_init init; init.target = cpu->kvm_target; memcpy(init.features, cpu->kvm_init_features, sizeof(init.features)); - return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init); + return kvm_vcpu_ioctl(CPU(cpu), KVM_ARM_VCPU_INIT, &init); } /** @@ -982,7 +981,7 @@ void kvm_arm_reset_vcpu(ARMCPU *cpu) /* Re-init VCPU so that all registers are set to * their respective reset values. */ - ret = kvm_arm_vcpu_init(CPU(cpu)); + ret = kvm_arm_vcpu_init(cpu); if (ret < 0) { fprintf(stderr, "kvm_arm_vcpu_init failed: %s\n", strerror(-ret)); abort(); @@ -1912,7 +1911,7 @@ int kvm_arch_init_vcpu(CPUState *cs) } /* Do KVM_ARM_VCPU_INIT ioctl */ - ret = kvm_arm_vcpu_init(cs); + ret = kvm_arm_vcpu_init(cpu); if (ret) { return ret; } From patchwork Tue Dec 19 19:12:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755968 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1602055wra; Tue, 19 Dec 2023 11:17:58 -0800 (PST) X-Google-Smtp-Source: AGHT+IF5ysMCKxhAnY1AdouAr+Z8Wl1ZV/2Aac542EZSbjQS9s+iImfOrPyCkZ74Pw26jX6Mvz74 X-Received: by 2002:a05:6214:4119:b0:67f:f78:a509 with SMTP id kc25-20020a056214411900b0067f0f78a509mr12902500qvb.13.1703013477884; Tue, 19 Dec 2023 11:17:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013477; cv=none; d=google.com; s=arc-20160816; b=uobMPXGn5+Y3TfRN9iGBF5AJlSv7ITXNa+1+cWQNjlW2Di3ARr99KwpSTg6pVDOGNi hzajTb0HKZW7hcVLGwDdOIBi9FIKjEldPw47JlYOYNkH/cJe+xDCpD20PpQcqH/AupU5 pWlsBlweaaSCtguffa0XHop82gFbH/pO6bMUKX4G1nxqDNn5Zt0ussPBezxKpzfAOTsK xoL2z0JGoS0tDmM0rvrfJONV97B/zlihAXoCrXI6w7xH2R8HGJiAPb4YgUvRBCj2hjdA i1lKohXtiyFPmGKytLNfUxTa+Ys0o72xy8+fkx6gSMf6J2YWjau2lFqkBzMphn65F6Kf jMQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=u7RSwDz13+9sv6W+3QlIzSQPKzKTiI3ycp67owFhcNM=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=ahFqcIOgYfI1h8AuXsrPIUijXf3bRR3rfFa7KaKGN1NNn5qLtuJVzed2wRXEb4NXBs 1OrpiPm6UfEF8gB7Yur4e7U43a6nWkSUG4sYvOlqAYfwQsaYjNXHfd6FQQ/3vOsfAMsd gHLTtGZk5YgT+XFpOwFxsgaM9A5pukR6LuG3lfBXRzioZNpwzmxVPKhON4ay2YUqlj9e 1P7XOYElQZrYjA2Om8JMfZLn61AOlaubZbBcNx2Rq8n8zRZZx3yLuz7S9piolZmHgV1z Iz4oBv9NrfN3OBrLP8Fyn45oRIiBiCYbm4PtS/coVMmDFoY5xRtrnMKENymMPcIBHOp0 NHyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gA5uj+lX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/43] target/arm/kvm: Have kvm_arm_vcpu_finalize take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:56 +0000 Message-Id: <20231219191307.2895919-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-12-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 9540d3cb618..a2370bc5747 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -82,7 +82,7 @@ static int kvm_arm_vcpu_init(ARMCPU *cpu) /** * kvm_arm_vcpu_finalize: - * @cs: CPUState + * @cpu: ARMCPU * @feature: feature to finalize * * Finalizes the configuration of the specified VCPU feature by @@ -92,9 +92,9 @@ static int kvm_arm_vcpu_init(ARMCPU *cpu) * * Returns: 0 if success else < 0 error code */ -static int kvm_arm_vcpu_finalize(CPUState *cs, int feature) +static int kvm_arm_vcpu_finalize(ARMCPU *cpu, int feature) { - return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_FINALIZE, &feature); + return kvm_vcpu_ioctl(CPU(cpu), KVM_ARM_VCPU_FINALIZE, &feature); } bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, @@ -1921,7 +1921,7 @@ int kvm_arch_init_vcpu(CPUState *cs) if (ret) { return ret; } - ret = kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE); + ret = kvm_arm_vcpu_finalize(cpu, KVM_ARM_VCPU_SVE); if (ret) { return ret; } From patchwork Tue Dec 19 19:12:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755969 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1602093wra; Tue, 19 Dec 2023 11:18:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IH7ubOC7FHL4Hr/2Vhbzxu0RNwzNilAliRLqIe3Ed52q9q+9pohFtfOzgngUaFO7jYROYIK X-Received: by 2002:ac8:5bc3:0:b0:427:8436:5b56 with SMTP id b3-20020ac85bc3000000b0042784365b56mr326895qtb.38.1703013483240; Tue, 19 Dec 2023 11:18:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013483; cv=none; d=google.com; s=arc-20160816; b=bpHNjHbjl/tU4z32/X7bOU2zfA28BvllpYqvQsbDB/YVZiHEo/vJLRg4K4VwVMyMt8 Wo8rjWdKKUa9riNaVaFVmUxidia+qcVUVOCtQBB28wmM81OHWKcoDK9pXUL84jlEtIfL KbZ304mvl1LgSBAmuS1U+g3BMGiSW3IDuRbSotq9SM/a/5YsEyWTi8Odiqwz9LHGX5+5 0h4RsWHrZv7M3+R1EbeH711baMO94VSttsfItDeqe8u89mFhIC40tXgBPpjbjTVYzP+4 B09ah+y1K/q2tgrfRCqcSAkVWcp5bcBqOWintxPCIR97iDWNLTVLPDYClsexfhpydTvG iovg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DxeuhpipM3BEPBaMclMGluLt2DuQa6fF5XvciTbwcOc=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=HEB4KFJ1RFIMc5krRxuwo57L8el0DJpyz9OArtvrSOWf20hnON7moigOUdgKA1Rfzo k78f6kEWp8vQfwunz2Aw11Q5R5A70R62BZpWA0hb+iFpgiZO3wLbzj+AAqPRz6xjTGW5 ylHE+BXKeogB6vgoluGgAlASDmJeJP/t4e/j4c6r6lz68qXhz03IrM1ghoF/O0ptbJp0 bKLp7x2zAISTcHTODXp/bLp5GB07okXD2WbCRw0155rHne6RfLAM1ihXgyerXn96lrm+ mS7PE4wGCQrFkGVTYrDN+6okb/zIqJhUCVTAypfKlf0SaCtf6miBpZch4aPn1XuBWUv3 244g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jPP4v1YF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/43] target/arm/kvm: Have kvm_arm_[get|put]_virtual_time take ARMCPU argument Date: Tue, 19 Dec 2023 19:12:57 +0000 Message-Id: <20231219191307.2895919-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-13-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index a2370bc5747..5973fbedde1 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1034,20 +1034,19 @@ static int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) /** * kvm_arm_get_virtual_time: - * @cs: CPUState + * @cpu: ARMCPU * * Gets the VCPU's virtual counter and stores it in the KVM CPU state. */ -static void kvm_arm_get_virtual_time(CPUState *cs) +static void kvm_arm_get_virtual_time(ARMCPU *cpu) { - ARMCPU *cpu = ARM_CPU(cs); int ret; if (cpu->kvm_vtime_dirty) { return; } - ret = kvm_get_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); + ret = kvm_get_one_reg(CPU(cpu), KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); if (ret) { error_report("Failed to get KVM_REG_ARM_TIMER_CNT"); abort(); @@ -1058,20 +1057,19 @@ static void kvm_arm_get_virtual_time(CPUState *cs) /** * kvm_arm_put_virtual_time: - * @cs: CPUState + * @cpu: ARMCPU * * Sets the VCPU's virtual counter to the value stored in the KVM CPU state. */ -static void kvm_arm_put_virtual_time(CPUState *cs) +static void kvm_arm_put_virtual_time(ARMCPU *cpu) { - ARMCPU *cpu = ARM_CPU(cs); int ret; if (!cpu->kvm_vtime_dirty) { return; } - ret = kvm_set_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); + ret = kvm_set_one_reg(CPU(cpu), KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); if (ret) { error_report("Failed to set KVM_REG_ARM_TIMER_CNT"); abort(); @@ -1289,16 +1287,15 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) static void kvm_arm_vm_state_change(void *opaque, bool running, RunState state) { - CPUState *cs = opaque; - ARMCPU *cpu = ARM_CPU(cs); + ARMCPU *cpu = opaque; if (running) { if (cpu->kvm_adjvtime) { - kvm_arm_put_virtual_time(cs); + kvm_arm_put_virtual_time(cpu); } } else { if (cpu->kvm_adjvtime) { - kvm_arm_get_virtual_time(cs); + kvm_arm_get_virtual_time(cpu); } } } @@ -1879,7 +1876,7 @@ int kvm_arch_init_vcpu(CPUState *cs) return -EINVAL; } - qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); + qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cpu); /* Determine init features for this CPU */ memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); From patchwork Tue Dec 19 19:12:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755971 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1602112wra; Tue, 19 Dec 2023 11:18:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IE9oE7i/7QD0lbxZ/AdT25eV+yFHAWH/NJTP8ZBwGn1KSHOS3tF7CmKijEc+Bi+s0qvSEza X-Received: by 2002:a05:620a:3884:b0:77f:9540:56a5 with SMTP id qp4-20020a05620a388400b0077f954056a5mr9992874qkn.135.1703013486270; Tue, 19 Dec 2023 11:18:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013486; cv=none; d=google.com; s=arc-20160816; b=DVCOA5pgL7iFvu2+IPUTykQt2XEfBfGxPkX/w+bB2TsD2O4aHH/6t02/bIjO52OjW6 Qyvj0YgwiEaG/0QSsVqNbLSACrbpPdhbUtZR+uwDFzx0YeBSFw5yocybbWE3ksQNJMdb OLKdFCwy1cliBw/vfpvEkhcis9rIyn2p7UnLgTHSG5bLZrUW5DHylcwDu/6cNbwCCVOm xmWTyGYOBKjF5yorlkvme9jgDokgk7mpKLA/jFQVaT9KhZT/DZqQReD2k4GZwV+lXlQu L9zbJ8LMhrT5X0+Cz4vsgGV0XDum6tBd3bBdWUqBds2EVLoKqYeIRRSfmpjia8juALFs Ktqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ttQrBvB/20bRVa3vwR6cfQBa/oaIBUExjVmg1GHCzFA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=z1f6DZUzNgxbsNZAf0Hd+Sh2T80iCoMWVGHMwD5hVkVZ241IVu9YzuT/gUKQDTAKpa OGBIg7U1P+UxcFIIvmBJwA3MXOQHT1ekFuaWfIXSzAirxhHeHt4a7tKv0G+r9grKBWnq 3AMHukNXyEkEkD2FiVCx1Fwbdj8P2PoNkJA71x1W4MPHgXM0FO+0qFQwYomjOB+67Hf/ vn6KWEGQl80PHKEbCdDPpy50x1OX2x5Bsy8swMh8QC/CnhJ7Tie+CdAGtTwq2YVZ3cf1 GKei+TKqX0NwWiE/GjqOTD19C5kfI18Eo1FosotEXBwIIbq4UEgoISGVrILJWwFyqEiC xb1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vmEzDX3+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/43] target/arm/kvm: Have kvm_arm_verify_ext_dabt_pending take a ARMCPU arg Date: Tue, 19 Dec 2023 19:12:58 +0000 Message-Id: <20231219191307.2895919-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-14-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 5973fbedde1..e4cd21caefc 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1170,18 +1170,18 @@ static int kvm_get_vcpu_events(ARMCPU *cpu) /** * kvm_arm_verify_ext_dabt_pending: - * @cs: CPUState + * @cpu: ARMCPU * * Verify the fault status code wrt the Ext DABT injection * * Returns: true if the fault status code is as expected, false otherwise */ -static bool kvm_arm_verify_ext_dabt_pending(CPUState *cs) +static bool kvm_arm_verify_ext_dabt_pending(ARMCPU *cpu) { + CPUState *cs = CPU(cpu); uint64_t dfsr_val; if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) { - ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64); int lpae = 0; @@ -1218,7 +1218,7 @@ void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) * an IMPLEMENTATION DEFINED exception (for 32-bit EL1) */ if (!arm_feature(env, ARM_FEATURE_AARCH64) && - unlikely(!kvm_arm_verify_ext_dabt_pending(cs))) { + unlikely(!kvm_arm_verify_ext_dabt_pending(cpu))) { error_report("Data abort exception with no valid ISS generated by " "guest memory access. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/43] target/arm/kvm: Have kvm_arm_handle_dabt_nisv take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:59 +0000 Message-Id: <20231219191307.2895919-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-15-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index e4cd21caefc..075487e62f1 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1302,17 +1302,16 @@ static void kvm_arm_vm_state_change(void *opaque, bool running, RunState state) /** * kvm_arm_handle_dabt_nisv: - * @cs: CPUState + * @cpu: ARMCPU * @esr_iss: ISS encoding (limited) for the exception from Data Abort * ISV bit set to '0b0' -> no valid instruction syndrome * @fault_ipa: faulting address for the synchronous data abort * * Returns: 0 if the exception has been handled, < 0 otherwise */ -static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, +static int kvm_arm_handle_dabt_nisv(ARMCPU *cpu, uint64_t esr_iss, uint64_t fault_ipa) { - ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; /* * Request KVM to inject the external data abort into the guest @@ -1328,7 +1327,7 @@ static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, */ events.exception.ext_dabt_pending = 1; /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */ - if (!kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events)) { + if (!kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events)) { env->ext_dabt_raised = 1; return 0; } @@ -1420,6 +1419,7 @@ static bool kvm_arm_handle_debug(CPUState *cs, int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) { + ARMCPU *cpu = ARM_CPU(cs); int ret = 0; switch (run->exit_reason) { @@ -1430,7 +1430,7 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) break; case KVM_EXIT_ARM_NISV: /* External DABT with no valid iss to decode */ - ret = kvm_arm_handle_dabt_nisv(cs, run->arm_nisv.esr_iss, + ret = kvm_arm_handle_dabt_nisv(cpu, run->arm_nisv.esr_iss, run->arm_nisv.fault_ipa); break; default: From patchwork Tue Dec 19 19:13:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755966 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1602004wra; Tue, 19 Dec 2023 11:17:54 -0800 (PST) X-Google-Smtp-Source: AGHT+IEMvM+6f9ru4OuIcQUorLko4XrlHkqXhQQtwiT2OG2qHNNhKdFSkLq5Gn5K1eNA7ZgycGfm X-Received: by 2002:a05:620a:2945:b0:77f:5f4a:24ea with SMTP id n5-20020a05620a294500b0077f5f4a24eamr21856253qkp.117.1703013474165; Tue, 19 Dec 2023 11:17:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013474; cv=none; d=google.com; s=arc-20160816; b=iJTK4yJUOhjTyEJgQ/BhJOdpA+vowe3Nvd+JKBezs6xXY3Whqygn5FB7GlH4pnv+68 GDixpdidpQEA2nPviOBQV8IHM0JFfD/HjHK6aG1ojuN3RkbvzjxP84/rioEML+u4p7L1 rc3g4/JRX4XMzhMpPSxAzBvqteMLiYxN8mFQ6drjX+DX2g0T03g3gU0pYGcpwSBuntAC zGAebVoBWV/dpUxzv2ZXyGPESCeGmix8pla5CbDDmUDcfuji9z5RaNxptxOLyHDzLovL KhOjNBV+rP16HUIlkFR/F+VVcuO33xysaDSJeyrFYyUM+xsOOv1H2Gk+m+m6qlKw5raa RsyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hXHi71kEAlJCpqi9ahK7azGhnduyvRCji9I/qeZQJBk=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=p6oDiXJZDSFgFJ5PjiqHNeABIfUwEsm1h2qYn/7ixC+cgsip3whWtxp3P31swNxOAx cp+kujBFOTBFD+T2BmWEnv1RIC266VobO6XivkYEcj0KkLnFmVxORFbMmmGQXc0WYGjh B+tBgJuIIqgb+0kXxLyh+KmD5Z1ukct4thk5Oh+xkM7yAgUWBDp/9xaVS3RcHSNxABER m28YkLLwHnuVlWy9lFantwMokjymRNjH+8Lu3Z3a3DkEypaED3qncppD6lg1tj6yBWwS cAsdiw0raA15o5Ab2/8mOm51uLhI3rvkC6bC0rBZIKU+RCkinCrCU1IFbBDy11vSG8Kt Axsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Vsd3gANf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/43] target/arm/kvm: Have kvm_arm_handle_debug take a ARMCPU argument Date: Tue, 19 Dec 2023 19:13:00 +0000 Message-Id: <20231219191307.2895919-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-16-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 075487e62f1..6794dc8ad61 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1342,7 +1342,7 @@ static int kvm_arm_handle_dabt_nisv(ARMCPU *cpu, uint64_t esr_iss, /** * kvm_arm_handle_debug: - * @cs: CPUState + * @cpu: ARMCPU * @debug_exit: debug part of the KVM exit structure * * Returns: TRUE if the debug exception was handled. @@ -1353,11 +1353,11 @@ static int kvm_arm_handle_dabt_nisv(ARMCPU *cpu, uint64_t esr_iss, * ABI just provides user-space with the full exception syndrome * register value to be decoded in QEMU. */ -static bool kvm_arm_handle_debug(CPUState *cs, +static bool kvm_arm_handle_debug(ARMCPU *cpu, struct kvm_debug_exit_arch *debug_exit) { int hsr_ec = syn_get_ec(debug_exit->hsr); - ARMCPU *cpu = ARM_CPU(cs); + CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; /* Ensure PC is synchronised */ @@ -1424,7 +1424,7 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) switch (run->exit_reason) { case KVM_EXIT_DEBUG: - if (kvm_arm_handle_debug(cs, &run->debug.arch)) { + if (kvm_arm_handle_debug(cpu, &run->debug.arch)) { ret = EXCP_DEBUG; } /* otherwise return to guest */ break; From patchwork Tue Dec 19 19:13:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755976 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1602648wra; Tue, 19 Dec 2023 11:19:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IGZZthnHMzD55XO5PIrI2RGSPl2DacotRN/B+X1H98ypCIpwlz+xJl6Yc9c4t/ZrfQ/4q2+ X-Received: by 2002:a05:6830:438b:b0:6d8:7aed:dfeb with SMTP id s11-20020a056830438b00b006d87aeddfebmr13542124otv.4.1703013550191; Tue, 19 Dec 2023 11:19:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013550; cv=none; d=google.com; s=arc-20160816; b=dtMkBAhJcChnOv9xC/JaWL/AQg7Gy8h9o2RAeqngLAKB9vMySVyB1KRlqRfAZg1Rg2 wmFSQh5EI68NklfwheVI1zKKnv82QCeih2A6uwJSUJsFKstykh1GbGnUzugtdiTo+TUy e9Ncfx94LZeCeaBPkU7b2qq9dJ59eNd8GIbmZLpFGUTbbIEPENkznHOc1785ajpFevzw UbnE7SB44G6sRWV6eDbvkLer6TImwxIy7YRN9/j2QSX+ikRRYaLfw2PpCmIVgFoRdAvS JvEXTgPpwDOIaD2gx9fjBhHNg+z87BEgJ74/efhohVoluOVr9YHQRxQ7ZTdAufGkQHi7 iKzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3OdKUaJzJak2eJQTHO6VMVDhLUVUEOXkAdntoItIO00=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=cxQLbvNFAoJuB2ROn0Roj6eSWw/6UWV80F5jQs3rAGBARgvOsl5SgSkmC5vbOIZk6P 54Ohniw77hd2UfZxdkypbxGe2ogUJ1tol3IqZ/JKY+R+GVswLdkBHoOXwt0/4B/b7nha exXQpnroeZWUfP80q/z7UBaODvnyXOUFzBzkTkEpn7S2ojdNFhhr2H8pz+gHtWrTadwr jfmVfMa6Tp/LbBUY0b8rdajoiRXYI1wXJx21gRH3LTQli/bnW0mTtaF8KQjdGal+EINZ xwT6j4vvZxNPVY8wA4Pa3FITswYzgTJeSvs0gF07w9f2sq7ZhoAY1TtNSgDWaf7/JBMX qzXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mqgwWU7d; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/43] target/arm/kvm: Have kvm_arm_hw_debug_active take a ARMCPU argument Date: Tue, 19 Dec 2023 19:13:01 +0000 Message-Id: <20231219191307.2895919-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-17-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 6794dc8ad61..c5a31838437 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1453,11 +1453,11 @@ int kvm_arch_process_async_events(CPUState *cs) /** * kvm_arm_hw_debug_active: - * @cs: CPU State + * @cpu: ARMCPU * * Return: TRUE if any hardware breakpoints in use. */ -static bool kvm_arm_hw_debug_active(CPUState *cs) +static bool kvm_arm_hw_debug_active(ARMCPU *cpu) { return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); } @@ -1491,7 +1491,7 @@ void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) if (kvm_sw_breakpoints_active(cs)) { dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; } - if (kvm_arm_hw_debug_active(cs)) { + if (kvm_arm_hw_debug_active(ARM_CPU(cs))) { dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW; kvm_arm_copy_hw_debug_data(&dbg->arch); } From patchwork Tue Dec 19 19:13:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755984 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1603609wra; Tue, 19 Dec 2023 11:21:14 -0800 (PST) X-Google-Smtp-Source: AGHT+IEbho+vg0cE5RbG/82qHT7r+TFi+QrrRN1sXe2uX9PTaY8jgbvd7i31pbP0X8kStsXg+4y3 X-Received: by 2002:a05:6808:114f:b0:3b8:4023:86e2 with SMTP id u15-20020a056808114f00b003b8402386e2mr27226035oiu.29.1703013674317; Tue, 19 Dec 2023 11:21:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013674; cv=none; d=google.com; s=arc-20160816; b=zY7UW5faGI40bY4FuNCkpDlLD+9LE2VdXBKFoW1YxY/Dz4i7UJ5j8xVJIi2DLcjAky EVh4LkE27/wEWrurDEcFBqO/tk6BZdocxBV6mr3Rqnftc2/gWc+p5SPsxOv5Vu/x6YxY peVKgHBYkV+sw2hXtPbRMPAHuazxzMvBSAmbbia/OVVRgj6E0jUhXzJnyy6BLQLs6xp2 UMoi/kjNhc14UeGkxV4q5E3IfuaShd2gItxTbM85OFhHEIIed9yPljfo0aWqDD165VDI BFdIsA/i+wTd5/F+cmnLYR3uLEsoQQYltlEclklTwlrh2o3LyCO1nbJPwNmThDwpqpZS nw9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0gBHCNexdbG+zEv+b4Ytrqor1JdvLFRCIBJ8HsM7maA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=O5Bg2csfKFU0OLNglguPmmYqPhow/5x8bcQLtome1pnw9Z2XtPfg5ErPxZyEmD5O5N pE3PTxspgRa/0QruZno9K+m5u0D2h5RmufLhd4f8Fv1WjmOctVOIjvAciyImyfv/vzvW L6YDgNoCw5QoXxFUkGIVH/t8UB9U+9NHgMdE7bUKXPKLIDowcuj/GdrYUTG7bWlTSRXJ qj9MhDz8n7cEAbOJiDNZ5+kmGngr25xQgM+2Yslka3+b9Tu2Y3H2PYhu24OwZmvWAu38 fssNvN79i5WlrMsJiSOmRk9BuFStsNR+oihcZR8IG2Hzwb3RVNlf0vI3y9PORM4LQddI 0ulQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="xLsc6S/a"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/43] target/arm: Don't implement *32_EL2 registers when EL1 is AArch64 only Date: Tue, 19 Dec 2023 19:13:02 +0000 Message-Id: <20231219191307.2895919-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The system registers DBGVCR32_EL2, FPEXC32_EL2, DACR32_EL2 and IFSR32_EL2 are present only to allow an AArch64 EL2 or EL3 to read and write the contents of an AArch32-only system register. The architecture requires that they are present only when EL1 can be AArch32, but we implement them unconditionally. This was OK when all our CPUs supported AArch32 EL1, but we have quite a lot of CPU models now which only support AArch64 at EL1: a64fx cortex-a76 cortex-a710 neoverse-n1 neoverse-n2 neoverse-v1 Only define these registers for CPUs which allow AArch32 EL1. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20231121144605.3980419-1-peter.maydell@linaro.org --- target/arm/debug_helper.c | 23 +++++++++++++++-------- target/arm/helper.c | 35 +++++++++++++++++++++-------------- 2 files changed, 36 insertions(+), 22 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index cbfba532f50..83d2619080f 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -1026,14 +1026,6 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, .access = PL1_RW, .accessfn = access_tda, .type = ARM_CP_NOP }, - /* - * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor - * to save and restore a 32-bit guest's DBGVCR) - */ - { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, - .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, - .access = PL2_RW, .accessfn = access_tda, - .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, /* * Dummy MDCCINT_EL1, since we don't implement the Debug Communications * Channel but Linux may try to access this register. The 32-bit @@ -1062,6 +1054,18 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.dbgclaim) }, }; +/* These are present only when EL1 supports AArch32 */ +static const ARMCPRegInfo debug_aa32_el1_reginfo[] = { + /* + * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor + * to save and restore a 32-bit guest's DBGVCR) + */ + { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, + .access = PL2_RW, .accessfn = access_tda, + .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, +}; + static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { /* 64 bit access versions of the (dummy) debug registers */ { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, @@ -1207,6 +1211,9 @@ void define_debug_regs(ARMCPU *cpu) assert(ctx_cmps <= brps); define_arm_cp_regs(cpu, debug_cp_reginfo); + if (cpu_isar_feature(aa64_aa32_el1, cpu)) { + define_arm_cp_regs(cpu, debug_aa32_el1_reginfo); + } if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); diff --git a/target/arm/helper.c b/target/arm/helper.c index 2746d3fdac8..39830c7f948 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5698,20 +5698,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, .type = ARM_CP_NO_RAW, .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, - { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, - .access = PL2_RW, - .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, - .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, - { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, - .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, - .writefn = dacr_write, .raw_writefn = raw_write, - .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, - { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, - .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, - .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, @@ -5746,6 +5732,24 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, }; +/* These are present only when EL1 supports AArch32 */ +static const ARMCPRegInfo v8_aa32_el1_reginfo[] = { + { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, + .access = PL2_RW, + .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, + .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, + { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, + .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, + .writefn = dacr_write, .raw_writefn = raw_write, + .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, + { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, + .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, + .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, +}; + static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) { ARMCPU *cpu = env_archcpu(env); @@ -8716,6 +8720,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) } define_arm_cp_regs(cpu, v8_idregs); define_arm_cp_regs(cpu, v8_cp_reginfo); + if (cpu_isar_feature(aa64_aa32_el1, cpu)) { + define_arm_cp_regs(cpu, v8_aa32_el1_reginfo); + } for (i = 4; i < 16; i++) { /* From patchwork Tue Dec 19 19:13:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755967 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1602056wra; Tue, 19 Dec 2023 11:17:58 -0800 (PST) X-Google-Smtp-Source: AGHT+IH9xlAs/jbT6mYE787FLQJxFirZFe6c677V9HmK7pZRR1NvhiEqOrqkEQyIfB6PLoaXl01+ X-Received: by 2002:a05:6214:f0a:b0:67f:470e:ed95 with SMTP id gw10-20020a0562140f0a00b0067f470eed95mr4027285qvb.24.1703013478001; Tue, 19 Dec 2023 11:17:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013477; cv=none; d=google.com; s=arc-20160816; b=K6kuzgH7ZW8ogQypmu/SnFZz8ZKFWQ161N1/CKfxrPURvqBN/tC2MmhUJYI9P/sxzW yL+FiwcJbv0dd++EGffl6l4FGx6l3Z+Ps/LIeoBE81RdiocsexPKm2QyLKN8T4puCjeF YFf//Nxyx0mbFHTmRJ8zuCEvy4cNOQIGPahhbJWZObSpHyjKI1xjuCegyBFvEbekSsFB X3VJDBaPoT1AhyO0DpUtIafE7qNADt9hZJfXHm3rmFNFyS7v+8Kaov2J5uXDhYEtNuYO yy6hsv0wfCpgsreHPvWzXaWl0i9gH6rGZ9NNnHaD5+pnymcGkBfFNFK7k6xTzSxMWZCM i7Gg== ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/43] target/arm: Restrict TCG specific helpers Date: Tue, 19 Dec 2023 19:13:03 +0000 Message-Id: <20231219191307.2895919-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20231130142519.28417-2-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 55 -------------------------------------- target/arm/tcg/op_helper.c | 55 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+), 55 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 39830c7f948..5d4796b99a8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10142,61 +10142,6 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, } } -/* Sign/zero extend */ -uint32_t HELPER(sxtb16)(uint32_t x) -{ - uint32_t res; - res = (uint16_t)(int8_t)x; - res |= (uint32_t)(int8_t)(x >> 16) << 16; - return res; -} - -static void handle_possible_div0_trap(CPUARMState *env, uintptr_t ra) -{ - /* - * Take a division-by-zero exception if necessary; otherwise return - * to get the usual non-trapping division behaviour (result of 0) - */ - if (arm_feature(env, ARM_FEATURE_M) - && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { - raise_exception_ra(env, EXCP_DIVBYZERO, 0, 1, ra); - } -} - -uint32_t HELPER(uxtb16)(uint32_t x) -{ - uint32_t res; - res = (uint16_t)(uint8_t)x; - res |= (uint32_t)(uint8_t)(x >> 16) << 16; - return res; -} - -int32_t HELPER(sdiv)(CPUARMState *env, int32_t num, int32_t den) -{ - if (den == 0) { - handle_possible_div0_trap(env, GETPC()); - return 0; - } - if (num == INT_MIN && den == -1) { - return INT_MIN; - } - return num / den; -} - -uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den) -{ - if (den == 0) { - handle_possible_div0_trap(env, GETPC()); - return 0; - } - return num / den; -} - -uint32_t HELPER(rbit)(uint32_t x) -{ - return revbit32(x); -} - #ifdef CONFIG_USER_ONLY static void switch_mode(CPUARMState *env, int mode) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index ea08936a852..9de0fa2d1f6 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -121,6 +121,61 @@ void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue) } } +/* Sign/zero extend */ +uint32_t HELPER(sxtb16)(uint32_t x) +{ + uint32_t res; + res = (uint16_t)(int8_t)x; + res |= (uint32_t)(int8_t)(x >> 16) << 16; + return res; +} + +static void handle_possible_div0_trap(CPUARMState *env, uintptr_t ra) +{ + /* + * Take a division-by-zero exception if necessary; otherwise return + * to get the usual non-trapping division behaviour (result of 0) + */ + if (arm_feature(env, ARM_FEATURE_M) + && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { + raise_exception_ra(env, EXCP_DIVBYZERO, 0, 1, ra); + } +} + +uint32_t HELPER(uxtb16)(uint32_t x) +{ + uint32_t res; + res = (uint16_t)(uint8_t)x; + res |= (uint32_t)(uint8_t)(x >> 16) << 16; + return res; +} + +int32_t HELPER(sdiv)(CPUARMState *env, int32_t num, int32_t den) +{ + if (den == 0) { + handle_possible_div0_trap(env, GETPC()); + return 0; + } + if (num == INT_MIN && den == -1) { + return INT_MIN; + } + return num / den; +} + +uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den) +{ + if (den == 0) { + handle_possible_div0_trap(env, GETPC()); + return 0; + } + return num / den; +} + +uint32_t HELPER(rbit)(uint32_t x) +{ + return revbit32(x); +} + uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) { uint32_t res = a + b; From patchwork Tue Dec 19 19:13:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755948 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1600724wra; Tue, 19 Dec 2023 11:15:26 -0800 (PST) X-Google-Smtp-Source: AGHT+IFf5x5QhT69uoGNkhrJ6o6806aL707QU8YQ4KmrvaXFC/pzfSJzMcwGvdcnv/5CAdZ7UDFr X-Received: by 2002:a05:6122:1681:b0:4b6:e45d:11cc with SMTP id 1-20020a056122168100b004b6e45d11ccmr956116vkl.33.1703013326088; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/43] target/arm: Restrict DC CVAP & DC CVADP instructions to TCG accel Date: Tue, 19 Dec 2023 19:13:04 +0000 Message-Id: <20231219191307.2895919-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Hardware accelerators handle that in *hardware*. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20231130142519.28417-3-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5d4796b99a8..436a43a4b7b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7649,6 +7649,7 @@ static const ARMCPRegInfo rndr_reginfo[] = { static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, uint64_t value) { +#ifdef CONFIG_TCG ARMCPU *cpu = env_archcpu(env); /* CTR_EL0 System register -> DminLine, bits [19:16] */ uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF); @@ -7673,6 +7674,10 @@ static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, } #endif /*CONFIG_USER_ONLY*/ } +#else + /* Handled by hardware accelerator. */ + g_assert_not_reached(); +#endif /* CONFIG_TCG */ } static const ARMCPRegInfo dcpop_reg[] = { From patchwork Tue Dec 19 19:13:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755960 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1601873wra; Tue, 19 Dec 2023 11:17:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IFI1rXs5BVShJsRahEqVJmuu5v2GqUMaBaXY+8d0IyngCdDJ3iqGoLxFcroAKffGibzIuHD X-Received: by 2002:a05:6102:374a:b0:466:6f:9b0e with SMTP id u10-20020a056102374a00b00466006f9b0emr7137801vst.17.1703013457999; Tue, 19 Dec 2023 11:17:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013457; cv=none; d=google.com; s=arc-20160816; b=tAGOFCJD9zHmSIm5GeQ6/HG9Y7NNSAdQYcKh5RPH+Q/X/TtGfRX+UP7GgD+vw9sMXQ +tyI+0tO+Mo7M6mvOmK3/3irSvFhFYOIHp5O/4zMIW6kb21WYanecVTPZJ5heE2TJ6+W QqSpTqvOEEUd9+6ZfCywayjKO+W1FbtcCk3VFT/+7LjIfsmh5TLP+DzBzNS3pIV0VSWy 6ZB10+Qyv2WNe2VtzfXF5l7WzoTdrV7zxnIjTx/b8pjeA9TWrObofjueF8n0O7gU8P0C 7++8AdYpdO4mOQXiH3XLjiWYdQRxt1+Jjyzvk3tas6P8i2mgQT001NesrylIF14x7S1c SY3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0NHBQEa3FZkeVazUjrvD8hJIhg1weYMkC8vKZ2fiVRE=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=gBUqSwoxY1hcJIyjHoaLkSVRbzhcIFsAfa3kBGep0cKYgfhGZuRJ0rGAMJu0lO/gjT ZFj4S3Dt+MBHcUWnZE/pBLHxLYzL405zOerS84/37dr+rGbU3p4QPymkhEQrNAVXNP0w wlUNFPvhBFr4Y88EVM+s4yQWPsuKGrHKKrhXr9BrlHhYRr7KdyW4FMXBVTsGfbz9WcgQ psEDoQZ4o+93kYS1HwF5CVzGbncZUF6KFyozJkfNIZ1uW9EOBs2Zp2cDZGyg5JPJnZiS VP6ChU7uOIhAKuQgOIdmKJ+1Va82Ici5n6xonjSKmLAK2qwjewtaMMyoqrDuQCQjTjap 0flQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Uib49gWL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 41/43] target/arm/tcg: Including missing 'exec/exec-all.h' header Date: Tue, 19 Dec 2023 19:13:05 +0000 Message-Id: <20231219191307.2895919-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SPACE_RATIO=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé translate_insn() ends up calling probe_access_full(), itself declared in "exec/exec-all.h": TranslatorOps::translate_insn -> aarch64_tr_translate_insn() -> is_guarded_page() -> probe_access_full() Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20231130142519.28417-4-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index a2e49c39f9f..f3b5b9124d0 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "exec/exec-all.h" #include "translate.h" #include "translate-a64.h" #include "qemu/log.h" From patchwork Tue Dec 19 19:13:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755965 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1601968wra; Tue, 19 Dec 2023 11:17:49 -0800 (PST) X-Google-Smtp-Source: AGHT+IHYkRYfkokU3EgaiO/qzFwgEofQ4iBSffm+zDR3L3RlLk+xHvsMZOUjv1jrrnN3dj+DMbBT X-Received: by 2002:a05:620a:640f:b0:77d:cb8c:38af with SMTP id pz15-20020a05620a640f00b0077dcb8c38afmr24229390qkn.4.1703013469515; Tue, 19 Dec 2023 11:17:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013469; cv=none; d=google.com; s=arc-20160816; b=01Q6BMvoDkCgtgpaupVgTU8VdkcfUEE1LxfjoYnLF+jCw5NG4P7wRe0NyyuAZW+hSF mXZ/OX7vK7ijPV5asQLJZk8tRMUG9Ah/Vn3V2WD1NUWq0WJBopJ1aR4zJKtwdMS2cDBk 4RwYZyqDzZ3vANL4Iqo7jUHjXwyuILvl8FMumvKYcLP1gKRWlVzudNVi4Z90xF6zBADF lPaSlArf/g8ZQAMFsPNwt5yxXsIytRspV5bEt0y2NxbxkxtpS+9GGOwNiUKfu49w28JZ 7IgRsoPgZE9Ro15fwvvVJ0KfqsKez5LqAa+2BlFKFKLZpH1Pceym1xVINeJ0LCxCxRr/ X/pw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/gf8/3mTDB0itjVLwlHBVzUhArBcmJcd155HpJsvLVw=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=FfECYIBDbnGtxwzYGyYIBAEouqXsq85qztYaMatU7M5ZE6iSN4UScVHw5V9GTlGKAH xTPsWUXJhTcBTNGz93ZZa4YXE7M+eX69MiVBVvGzUxwALjVWIetlAIZ16iaPl0N1s/0Q Nufwa69E8KO6hR6v4fkQCe8uC7nP1nwy7Mx75jC8NGo5P26Vbe3R9E05d0DqiINXcyIk st6GICNPxW7vdtmwfPjPJc9Fx/IGy3vSTNydxjNlL2ntOpZmzfVt2glujartu1Gm3KbE bOZB6V5ReibBjM37vU1/Fi+GsRvTvrtTlWxdENQNZG75Ebpo/NnF5smZ6RVRs8jN+OR4 yfNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="GL/Mvyql"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/43] target/arm/helper: Propagate MDCR_EL2.HPMN into PMCR_EL0.N Date: Tue, 19 Dec 2023 19:13:06 +0000 Message-Id: <20231219191307.2895919-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Jean-Philippe Brucker MDCR_EL2.HPMN allows an hypervisor to limit the number of PMU counters available to EL1 and EL0 (to keep the others to itself). QEMU already implements this split correctly, except for PMCR_EL0.N reads: the number of counters read by EL1 or EL0 should be the one configured in MDCR_EL2.HPMN. Cc: qemu-stable@nongnu.org Signed-off-by: Jean-Philippe Brucker Message-id: 20231215144652.4193815-2-jean-philippe@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 436a43a4b7b..fc546df5c70 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1475,6 +1475,22 @@ static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, pmu_op_finish(env); } +static uint64_t pmcr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t pmcr = env->cp15.c9_pmcr; + + /* + * If EL2 is implemented and enabled for the current security state, reads + * of PMCR.N from EL1 or EL0 return the value of MDCR_EL2.HPMN or HDCR.HPMN. + */ + if (arm_current_el(env) <= 1 && arm_is_el2_enabled(env)) { + pmcr &= ~PMCRN_MASK; + pmcr |= (env->cp15.mdcr_el2 & MDCR_HPMN) << PMCRN_SHIFT; + } + + return pmcr; +} + static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -7158,8 +7174,9 @@ static void define_pmu_regs(ARMCPU *cpu) .fgt = FGT_PMCR_EL0, .type = ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), - .accessfn = pmreg_access, .writefn = pmcr_write, - .raw_writefn = raw_write, + .accessfn = pmreg_access, + .readfn = pmcr_read, .raw_readfn = raw_read, + .writefn = pmcr_write, .raw_writefn = raw_write, }; ARMCPRegInfo pmcr64 = { .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, @@ -7169,6 +7186,7 @@ static void define_pmu_regs(ARMCPU *cpu) .type = ARM_CP_IO, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), .resetvalue = cpu->isar.reset_pmcr_el0, + .readfn = pmcr_read, .raw_readfn = raw_read, .writefn = pmcr_write, .raw_writefn = raw_write, }; From patchwork Tue Dec 19 19:13:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 755980 Delivered-To: patch@linaro.org Received: by 2002:adf:b181:0:b0:336:6142:bf13 with SMTP id q1csp1603509wra; Tue, 19 Dec 2023 11:21:02 -0800 (PST) X-Google-Smtp-Source: AGHT+IE+eBHSECdNNVRduTzKLIty4zwHOcoPRuQIX60q4YEhw+ONWTy9MTSWpoZKHh3e0qjmCrcf X-Received: by 2002:a05:6102:3d21:b0:466:b776:61ab with SMTP id i33-20020a0561023d2100b00466b77661abmr723058vsv.68.1703013662049; Tue, 19 Dec 2023 11:21:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1703013662; cv=none; d=google.com; s=arc-20160816; b=QfDIj2Mb2vnkaQkT7a2sEqPWYsBDYySu1MOqiuECJNaxMuJrjL3bSd92rTVKbpY3ZL wQReKHSvQJU9/FbXoMxzR5coyKFEqARFeMyvgFxXyTNkw3SNBT1Ph1fjQf8OQ5WkykVf CuUi7u8htL7esW8qnOtChAAbBGXDDoZpJXb3RHusNwpf4rnYwnuPFb1zAOacJa3cNhVP /bHZxCIaV46ANFakJzlI5VT4Z7Or4325sRXbfyu3o/l6DshN7owbMFsN/ZZeC0lp1Owe HvErDwzSazR+zKdT4BTAQVPDJAQtP6qwSb5y+GOnLYFsqadfZZbafxuuxWSBGkf3OIKu b8OA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=00hMtN5BXevzRJATDfX8VsM5S59s6M4RCIFrJXcR5Q4=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=urqyc317pss43A2qpHbhF5EwCv6thX5+fqS/D0+pNXS+7qjGKa3slxl31FVzCTFqD1 o1Csvq7247dh+w1gboUFaQUag6qm00jfPTshfyc7PKR797lng3D9za6d1v7FpwvyMEJi 9gRzEscfWyIhY4aTZi2HywI3s51LjBkAMt+X6LoLRXGiNBEnBY6vdBS2JzUJhyYwFaTS 4w1KPUnSKMGVUzxaLaWtw2bBF4nUUY729gBggljwxOA2KsJRmju07gDYg+IvIRrEibtg 0AHxk4SD5sgcPfpTmIUc8v91otffHY11fVG5k0glQoG/XYaJnHcvNgWVGEAvX6ypxfj8 jmyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Vsq/aVVN"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 43/43] fsl-imx: add simple RTC emulation for i.MX6 and i.MX7 boards Date: Tue, 19 Dec 2023 19:13:07 +0000 Message-Id: <20231219191307.2895919-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Nikita Ostrenkov Signed-off-by: Nikita Ostrenkov Message-id: 20231216133408.2884-1-n.ostrenkov@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/misc/imx7_snvs.h | 7 ++- hw/misc/imx7_snvs.c | 93 ++++++++++++++++++++++++++++++++++--- hw/misc/trace-events | 4 +- 3 files changed, 94 insertions(+), 10 deletions(-) diff --git a/include/hw/misc/imx7_snvs.h b/include/hw/misc/imx7_snvs.h index 14a1d6fe6b0..1272076086a 100644 --- a/include/hw/misc/imx7_snvs.h +++ b/include/hw/misc/imx7_snvs.h @@ -20,7 +20,9 @@ enum IMX7SNVSRegisters { SNVS_LPCR = 0x38, SNVS_LPCR_TOP = BIT(6), - SNVS_LPCR_DP_EN = BIT(5) + SNVS_LPCR_DP_EN = BIT(5), + SNVS_LPSRTCMR = 0x050, /* Secure Real Time Counter MSB Register */ + SNVS_LPSRTCLR = 0x054, /* Secure Real Time Counter LSB Register */ }; #define TYPE_IMX7_SNVS "imx7.snvs" @@ -31,6 +33,9 @@ struct IMX7SNVSState { SysBusDevice parent_obj; MemoryRegion mmio; + + uint64_t tick_offset; + uint64_t lpcr; }; #endif /* IMX7_SNVS_H */ diff --git a/hw/misc/imx7_snvs.c b/hw/misc/imx7_snvs.c index a245f96cd4e..8e7f43187f6 100644 --- a/hw/misc/imx7_snvs.c +++ b/hw/misc/imx7_snvs.c @@ -13,28 +13,100 @@ */ #include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "qemu/timer.h" +#include "migration/vmstate.h" #include "hw/misc/imx7_snvs.h" +#include "qemu/cutils.h" #include "qemu/module.h" +#include "sysemu/sysemu.h" +#include "sysemu/rtc.h" #include "sysemu/runstate.h" #include "trace.h" +#define RTC_FREQ 32768ULL + +static const VMStateDescription vmstate_imx7_snvs = { + .name = TYPE_IMX7_SNVS, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT64(tick_offset, IMX7SNVSState), + VMSTATE_UINT64(lpcr, IMX7SNVSState), + VMSTATE_END_OF_LIST() + } +}; + +static uint64_t imx7_snvs_get_count(IMX7SNVSState *s) +{ + uint64_t ticks = muldiv64(qemu_clock_get_ns(rtc_clock), RTC_FREQ, + NANOSECONDS_PER_SECOND); + return s->tick_offset + ticks; +} + static uint64_t imx7_snvs_read(void *opaque, hwaddr offset, unsigned size) { - trace_imx7_snvs_read(offset, 0); + IMX7SNVSState *s = IMX7_SNVS(opaque); + uint64_t ret = 0; - return 0; + switch (offset) { + case SNVS_LPSRTCMR: + ret = extract64(imx7_snvs_get_count(s), 32, 15); + break; + case SNVS_LPSRTCLR: + ret = extract64(imx7_snvs_get_count(s), 0, 32); + break; + case SNVS_LPCR: + ret = s->lpcr; + break; + } + + trace_imx7_snvs_read(offset, ret, size); + + return ret; +} + +static void imx7_snvs_reset(DeviceState *dev) +{ + IMX7SNVSState *s = IMX7_SNVS(dev); + + s->lpcr = 0; } static void imx7_snvs_write(void *opaque, hwaddr offset, uint64_t v, unsigned size) { - const uint32_t value = v; - const uint32_t mask = SNVS_LPCR_TOP | SNVS_LPCR_DP_EN; + trace_imx7_snvs_write(offset, v, size); - trace_imx7_snvs_write(offset, value); + IMX7SNVSState *s = IMX7_SNVS(opaque); - if (offset == SNVS_LPCR && ((value & mask) == mask)) { - qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + uint64_t new_value = 0, snvs_count = 0; + + if (offset == SNVS_LPSRTCMR || offset == SNVS_LPSRTCLR) { + snvs_count = imx7_snvs_get_count(s); + } + + switch (offset) { + case SNVS_LPSRTCMR: + new_value = deposit64(snvs_count, 32, 32, v); + break; + case SNVS_LPSRTCLR: + new_value = deposit64(snvs_count, 0, 32, v); + break; + case SNVS_LPCR: { + s->lpcr = v; + + const uint32_t mask = SNVS_LPCR_TOP | SNVS_LPCR_DP_EN; + + if ((v & mask) == mask) { + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + } + break; + } + } + + if (offset == SNVS_LPSRTCMR || offset == SNVS_LPSRTCLR) { + s->tick_offset += new_value - snvs_count; } } @@ -59,17 +131,24 @@ static void imx7_snvs_init(Object *obj) { SysBusDevice *sd = SYS_BUS_DEVICE(obj); IMX7SNVSState *s = IMX7_SNVS(obj); + struct tm tm; memory_region_init_io(&s->mmio, obj, &imx7_snvs_ops, s, TYPE_IMX7_SNVS, 0x1000); sysbus_init_mmio(sd, &s->mmio); + + qemu_get_timedate(&tm, 0); + s->tick_offset = mktimegm(&tm) - + qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; } static void imx7_snvs_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + dc->reset = imx7_snvs_reset; + dc->vmsd = &vmstate_imx7_snvs; dc->desc = "i.MX7 Secure Non-Volatile Storage Module"; } diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 05ff692441b..85725506bff 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -116,8 +116,8 @@ imx7_gpr_read(uint64_t offset) "addr 0x%08" PRIx64 imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx64 # imx7_snvs.c -imx7_snvs_read(uint64_t offset, uint32_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx32 -imx7_snvs_write(uint64_t offset, uint32_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx32 +imx7_snvs_read(uint64_t offset, uint64_t value, unsigned size) "i.MX SNVS read: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u" +imx7_snvs_write(uint64_t offset, uint64_t value, unsigned size) "i.MX SNVS write: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u" # mos6522.c mos6522_set_counter(int index, unsigned int val) "T%d.counter=%d"