From patchwork Thu Dec 21 03:50:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 758035 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6206F8C01; Thu, 21 Dec 2023 03:51:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="J6SoQsTV" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BL2IatL017801; Thu, 21 Dec 2023 03:50:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:date:subject:mime-version:content-type :content-transfer-encoding:message-id:references:in-reply-to:to :cc; s=qcppdkim1; bh=qxoKW4bRzJoxnQGhW8Ud6uaUciCN2bKlX/uk+24M/+4 =; b=J6SoQsTV/ln8c1K0+luNTrgD8uTBspUCAkkdFR81mMv2vqKnGqZZh+bOCcg n9A4UpSjdZUmu5jdydNu0XOCh+5FYvGZug/di/1ds3IMLOzrLAzuw2L5UtcgdKDE k2HM4xB3/uLJulfDPCGVdO5wgVm1KEjctokK0opZpJHxU5EBnJ9QoJ956tFNC2VY NS4qhX0rzA4j69lBdc1mNOPhAye1WCXDml/6EJRYpGbcMyJIBBMZybXeh4jY6C2B GwOsyNdbJ8K2ib0dqpSJMfi5ytSEq6kf24RR2VO6WZ1IffjrmRjJjvqHoA3YHjWV 5T10AloWKquX4MMdjuRoLk2IoZQ== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3v4b5u8dks-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Dec 2023 03:50:51 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BL3oonr003636 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Dec 2023 03:50:50 GMT Received: from [169.254.0.1] (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 20 Dec 2023 19:50:49 -0800 From: Bjorn Andersson Date: Wed, 20 Dec 2023 19:50:35 -0800 Subject: [PATCH 1/8] dt-bindings: clock: qcom: Allow VDD_GFX supply to GX Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231220-sa8295p-gpu-v1-1-d8cdf2257f97@quicinc.com> References: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> In-Reply-To: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Taniya Das , Ulf Hansson , Johan Hovold , "Catalin Marinas" , Will Deacon CC: , , , , , , "Bjorn Andersson" X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703130649; l=841; i=quic_bjorande@quicinc.com; s=20230915; h=from:subject:message-id; bh=gsLSzEtTNvvjs9aLDTb4B3w5KFCxmior5IC60emfAk4=; b=7KZMkkOYfPdl/o2/c7khRGaRw8a5OOlkrlJLkcyB6UDJ2bpf82xRPyr6w6YKEkC8xgyec/QsI/vs Inmml+nBCvduDR2gpL4ZSF/HC2zCC8UJFWrjIW+6HuP099y7GDz+ X-Developer-Key: i=quic_bjorande@quicinc.com; a=ed25519; pk=VkhObtljigy9k0ZUIE1Mvr0Y+E1dgBEH9WoLQnUtbIM= X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: u2tG44NJ6BpkQtlUBQGpEa8IqcN6OXBu X-Proofpoint-ORIG-GUID: u2tG44NJ6BpkQtlUBQGpEa8IqcN6OXBu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 phishscore=0 mlxscore=0 suspectscore=0 bulkscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 mlxlogscore=999 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312210026 In some designs the SoC's VDD_GFX pads are supplied by an external regulator, rather than a power-domain. Allow this to be described in the GPU clock controller binding. Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/clock/qcom,gpucc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index f369fa34e00c..013ef78d2b31 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -53,6 +53,9 @@ properties: power-domains: maxItems: 1 + vdd-gfx-supply: + description: Regulator supply for the VDD_GFX pads + '#clock-cells': const: 1 From patchwork Thu Dec 21 03:50:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 757374 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B18D45249; 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Thu, 21 Dec 2023 03:50:51 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BL3oonV011706 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Dec 2023 03:50:50 GMT Received: from [169.254.0.1] (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 20 Dec 2023 19:50:50 -0800 From: Bjorn Andersson Date: Wed, 20 Dec 2023 19:50:36 -0800 Subject: [PATCH 2/8] clk: qcom: gdsc: Enable supply reglator in GPU GX handler Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231220-sa8295p-gpu-v1-2-d8cdf2257f97@quicinc.com> References: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> In-Reply-To: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Taniya Das , Ulf Hansson , Johan Hovold , "Catalin Marinas" , Will Deacon CC: , , , , , , "Bjorn Andersson" X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703130649; l=1170; i=quic_bjorande@quicinc.com; s=20230915; h=from:subject:message-id; bh=NRcjjCsDovL9I1ze2bc9Mx0aQssR4APji3KJJF2CHFc=; b=+IIJYZC7MtZAIxx8g+S8H7rfx+fxUQ/rQ/1F9o5CXT11uGqEfmW5vC6m8i11QxyUkdh0etMIcUMz uio/xpvfBuxjbWu7NwmGTrLqPUEXJ1zLkU7lGam7BCiU4Nx16kvD X-Developer-Key: i=quic_bjorande@quicinc.com; a=ed25519; pk=VkhObtljigy9k0ZUIE1Mvr0Y+E1dgBEH9WoLQnUtbIM= X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: msi8icBqaIBCMa-5gcEzsM1rMbyGclam X-Proofpoint-ORIG-GUID: msi8icBqaIBCMa-5gcEzsM1rMbyGclam X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 impostorscore=0 suspectscore=0 phishscore=0 bulkscore=0 clxscore=1015 mlxlogscore=976 lowpriorityscore=0 adultscore=0 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312210025 The GX GDSC is modelled to aid the GMU in powering down the GPU in the event that the GPU crashes, so that it can be restarted again. But in the event that the power-domain is supplied through a dedicated regulator (in contrast to being a subdomin of another power-domain), something needs to turn that regulator on, both to make sure things are powered and to match the operation in gdsc_disable(). Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gdsc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 5358e28122ab..d1139c895503 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -557,7 +557,13 @@ void gdsc_unregister(struct gdsc_desc *desc) */ int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain) { + struct gdsc *sc = domain_to_gdsc(domain); + int ret = 0; + /* Do nothing but give genpd the impression that we were successful */ - return 0; + if (sc->rsupply) + ret = regulator_enable(sc->rsupply); + + return ret; } EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable); From patchwork Thu Dec 21 03:50:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 757377 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 620428BED; 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Thu, 21 Dec 2023 03:50:51 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BL3ooN6003639 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Dec 2023 03:50:50 GMT Received: from [169.254.0.1] (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 20 Dec 2023 19:50:50 -0800 From: Bjorn Andersson Date: Wed, 20 Dec 2023 19:50:37 -0800 Subject: [PATCH 3/8] clk: qcom: gpucc-sc8280xp: Add external supply for GX gdsc Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231220-sa8295p-gpu-v1-3-d8cdf2257f97@quicinc.com> References: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> In-Reply-To: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Taniya Das , Ulf Hansson , Johan Hovold , "Catalin Marinas" , Will Deacon CC: , , , , , , "Bjorn Andersson" X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; 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Define the "vdd-gfx" as the supply regulator for the GDSC, to cause the gdsc logic to look for, and control, this external power supply. Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/gpucc-sc8280xp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gpucc-sc8280xp.c b/drivers/clk/qcom/gpucc-sc8280xp.c index 8e147ee294ee..e2b3bc000c71 100644 --- a/drivers/clk/qcom/gpucc-sc8280xp.c +++ b/drivers/clk/qcom/gpucc-sc8280xp.c @@ -399,6 +399,7 @@ static struct gdsc gx_gdsc = { }, .pwrsts = PWRSTS_OFF_ON, .flags = CLAMP_IO | RETAIN_FF_ENABLE, + .supply = "vdd-gfx", }; static struct gdsc *gpu_cc_sc8280xp_gdscs[] = { From patchwork Thu Dec 21 03:50:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 758034 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6AF98C17; Thu, 21 Dec 2023 03:51:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="dZlzy3k9" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BL3oqd9014503; Thu, 21 Dec 2023 03:50:52 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:date:subject:mime-version:content-type :content-transfer-encoding:message-id:references:in-reply-to:to :cc; s=qcppdkim1; bh=pyo/7sTw5M8v3OoXaYpbrVLNBeRjx0rU67xrb1AgwAo =; b=dZlzy3k9EaUAn2PXQeyIPyQ017d2OxeeBnG4QaRBETDLuqmxMBZBh8rVDZC rm2WH8+YIoS+SEdASNyWr+PUN6i+bcE2P4uicMTchRuE/v+aQ5wAc5SmjA08U3mr Jt3+t2l5xcWd+3DEc108gao3mpzloKNGnJqM5vYozyLWA+2f8gDLEQCOTxb5tVSg umPGHomHV86VI1UBn2UXLAEmYesgbcgcNQa5+2DCs1+Xmf77Gv3K6jPI0q09RIFV 3bRgQrALtc6oQBC6+dte9EDziA8VstCkq1vHfF0MRnLsole8gsXlkXhjX2x0HoR+ KsSyp4YI7H+7Ze/vqoExNrSI8ZA== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3v4234huxj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Dec 2023 03:50:52 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BL3oppI011714 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Dec 2023 03:50:51 GMT Received: from [169.254.0.1] (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 20 Dec 2023 19:50:50 -0800 From: Bjorn Andersson Date: Wed, 20 Dec 2023 19:50:38 -0800 Subject: [PATCH 4/8] soc: qcom: rpmhpd: Drop SA8540P gfx.lvl Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231220-sa8295p-gpu-v1-4-d8cdf2257f97@quicinc.com> References: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> In-Reply-To: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Taniya Das , Ulf Hansson , Johan Hovold , "Catalin Marinas" , Will Deacon CC: , , , , , , "Bjorn Andersson" X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703130649; l=875; i=quic_bjorande@quicinc.com; s=20230915; h=from:subject:message-id; bh=zKM1tJ2bwLaUFYNjSeQF8Ps0X67w9IK/SdhRZin2yfM=; b=5U5q3V8oo5buTX466+jtHinXn9Pjc1uLJl0SH2t4VGZoE4nUeKpr2B48XjVkcupkFc1ntoRrZONn jpwAte8sCTL86cYC3zuotgjePtQodmR4q4r9pG6t7C7Q8K/NW0/q X-Developer-Key: i=quic_bjorande@quicinc.com; a=ed25519; pk=VkhObtljigy9k0ZUIE1Mvr0Y+E1dgBEH9WoLQnUtbIM= X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Sx-bgnsO9QoMeoNuVRIl9JeUX-KpQVZB X-Proofpoint-GUID: Sx-bgnsO9QoMeoNuVRIl9JeUX-KpQVZB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 bulkscore=0 mlxscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 spamscore=0 suspectscore=0 impostorscore=0 mlxlogscore=937 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312210026 On SA8295P and SA8540P gfx.lvl is not provdied by rpmh, but rather is handled by an external regulator (max20411). Drop gfx.lvl from the list of power-domains exposed on this platform. Fixes: f68f1cb3437d ("soc: qcom: rpmhpd: add sc8280xp & sa8540p rpmh power-domains") Signed-off-by: Bjorn Andersson --- drivers/pmdomain/qcom/rpmhpd.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pmdomain/qcom/rpmhpd.c b/drivers/pmdomain/qcom/rpmhpd.c index 3078896b1300..27a73ff72614 100644 --- a/drivers/pmdomain/qcom/rpmhpd.c +++ b/drivers/pmdomain/qcom/rpmhpd.c @@ -217,7 +217,6 @@ static struct rpmhpd *sa8540p_rpmhpds[] = { [SC8280XP_CX] = &cx, [SC8280XP_CX_AO] = &cx_ao, [SC8280XP_EBI] = &ebi, - [SC8280XP_GFX] = &gfx, [SC8280XP_LCX] = &lcx, [SC8280XP_LMX] = &lmx, [SC8280XP_MMCX] = &mmcx, From patchwork Thu Dec 21 03:50:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 757376 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C811553B2; 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Thu, 21 Dec 2023 03:50:52 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BL3oplK029598 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Dec 2023 03:50:51 GMT Received: from [169.254.0.1] (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 20 Dec 2023 19:50:51 -0800 From: Bjorn Andersson Date: Wed, 20 Dec 2023 19:50:39 -0800 Subject: [PATCH 5/8] arm64: dts: qcom: sa8540p: Drop gfx.lvl as power-domain for gpucc Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231220-sa8295p-gpu-v1-5-d8cdf2257f97@quicinc.com> References: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> In-Reply-To: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Taniya Das , Ulf Hansson , Johan Hovold , "Catalin Marinas" , Will Deacon CC: , , , , , , "Bjorn Andersson" X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; 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Drop the power-domains property of the gpucc node to reflect this. Fixes: eec51ab2fd6f ("arm64: dts: qcom: sc8280xp: Add GPU related nodes") Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sa8540p.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi index 96b2c59ad02b..b604404ebf64 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi @@ -168,6 +168,8 @@ opp-2592000000 { }; &gpucc { + /delete-property/ power-domains; + status = "disabled"; }; From patchwork Thu Dec 21 03:50:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 757375 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9EE579DC; Thu, 21 Dec 2023 03:51:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ZZtfraEM" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BL3nDES020761; Thu, 21 Dec 2023 03:50:52 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:date:subject:mime-version:content-type :content-transfer-encoding:message-id:references:in-reply-to:to :cc; s=qcppdkim1; bh=rr9r9gWxhO4lMOjEkKreNfvWKgKBiYqYX4s9TmL7zcQ =; b=ZZtfraEMM+C9hJeHXHu0wsytwhZK/1knz38pGjYDyVntREPd2bKCgJDquDm f6Ia2tBGaCvZth9rdd7Il8u8Q2UtxRaDT/LxxQ0/flHVCNNWcVi+APikkWmyGtTB cvu5zygqR1+3m/67sA8JgOLRyco5W4z/PDaGWCsMcUGiLUXTgZktgpCp/ecOZq90 Fr5Z+i6jHOOBIQSiISZZ7g6xbcsakHgp8k9KQj3fJgCx6cadu9qyLLHELL4lu41q oOC7LXDlMQpzZlxGW8LTuvmu2TVkjq4c+rKrq8N7eyuttdxtbRtO37aOH1cDYRk3 WKAEX8ohqfk5+AKejMKd/xr+LyQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3v3r6ru9m7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Dec 2023 03:50:52 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BL3opK2020560 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Dec 2023 03:50:51 GMT Received: from [169.254.0.1] (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 20 Dec 2023 19:50:51 -0800 From: Bjorn Andersson Date: Wed, 20 Dec 2023 19:50:40 -0800 Subject: [PATCH 6/8] arm64: dts: qcom: sa8295p-adp: add max20411 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231220-sa8295p-gpu-v1-6-d8cdf2257f97@quicinc.com> References: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> In-Reply-To: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Taniya Das , Ulf Hansson , Johan Hovold , "Catalin Marinas" , Will Deacon CC: , , , , , , "Bjorn Andersson" , Bjorn Andersson X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703130649; l=1576; i=quic_bjorande@quicinc.com; s=20230915; h=from:subject:message-id; bh=iuhv7P68f++bs7xsess+Ut/fTJIye+b8NI9cCDTyLVc=; b=up+NYbS/7WM3RyIz183b67hkzTM4B+OxT3FeiOsRy7DKP/j7O7czuFnmznVDSKWIy3nQMV/XgEDy erOT+Ci2DAPf4unP6aUx+vpjqUlXheYer2PriM2JqsGSTG8WGsfU X-Developer-Key: i=quic_bjorande@quicinc.com; a=ed25519; pk=VkhObtljigy9k0ZUIE1Mvr0Y+E1dgBEH9WoLQnUtbIM= X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: TaqN9-nB1Vy7tNOm2EgLwry4Nc5tp4yW X-Proofpoint-GUID: TaqN9-nB1Vy7tNOm2EgLwry4Nc5tp4yW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 mlxscore=0 mlxlogscore=988 clxscore=1015 malwarescore=0 suspectscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312210026 From: Bjorn Andersson The SA8295P ADP has a MAX20411 LDO regulator on I2C 12, supplying the VDD_GFX pads. Enable the bus and add the maxim,max20411 device on the bus. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index fd253942e5e5..e16406c9c19d 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -266,6 +266,26 @@ &dispcc1 { status = "okay"; }; +&i2c12 { + pinctrl-names = "default"; + pinctrl-0 = <&qup1_i2c4_state>; + + status = "okay"; + + vdd_gfx: regulator@39 { + compatible = "maxim,max20411"; + reg = <0x39>; + + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <968750>; + + enable-gpios = <&pmm8540a_gpios 2 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&max20411_en>; + }; +}; + &mdss0 { status = "okay"; }; @@ -476,6 +496,10 @@ &pcie4_phy { status = "okay"; }; +&qup1 { + status = "okay"; +}; + &qup2 { status = "okay"; }; @@ -728,4 +752,20 @@ wake-n-pins { bias-pull-up; }; }; + + qup1_i2c4_state: qup1-i2c4-state { + pins = "gpio0", "gpio1"; + function = "qup12"; + + drive-strength = <2>; + bias-pull-up; + }; +}; + +&pmm8540a_gpios { + max20411_en: max20411-en-state { + pins = "gpio2"; + function = "normal"; + output-enable; + }; }; From patchwork Thu Dec 21 03:50:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 758032 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0C525247; Thu, 21 Dec 2023 03:51:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="lcrD0ujm" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BL3NegA004437; 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Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index e16406c9c19d..7775c5f4d2e8 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -108,6 +108,13 @@ edp3_connector_in: endpoint { }; }; }; + + reserved-memory { + gpu_mem: gpu-mem@8bf00000 { + reg = <0 0x8bf00000 0 0x2000>; + no-map; + }; + }; }; &apps_rsc { @@ -286,6 +293,28 @@ vdd_gfx: regulator@39 { }; }; +&gpucc { + vdd-gfx-supply = <&vdd_gfx>; + status = "okay"; +}; + +&gmu { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sa8295p/a690_zap.mdt"; + }; +}; + +&gpu_smmu { + status = "okay"; +}; + &mdss0 { status = "okay"; }; From patchwork Thu Dec 21 03:50:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 758031 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62A0AB654; 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Thu, 21 Dec 2023 03:50:53 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BL3oqrJ004602 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Dec 2023 03:50:52 GMT Received: from [169.254.0.1] (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 20 Dec 2023 19:50:51 -0800 From: Bjorn Andersson Date: Wed, 20 Dec 2023 19:50:42 -0800 Subject: [PATCH 8/8] arm64: defconfig: Enable MAX20411 regulator driver Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20231220-sa8295p-gpu-v1-8-d8cdf2257f97@quicinc.com> References: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> In-Reply-To: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Taniya Das , Ulf Hansson , Johan Hovold , "Catalin Marinas" , Will Deacon CC: , , , , , , "Bjorn Andersson" X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; 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Signed-off-by: Bjorn Andersson --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index ef1061089548..ec94a0c4fd03 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -751,6 +751,7 @@ CONFIG_REGULATOR_HI6421V530=y CONFIG_REGULATOR_HI655X=y CONFIG_REGULATOR_MAX77620=y CONFIG_REGULATOR_MAX8973=y +CONFIG_REGULATOR_MAX20411=m CONFIG_REGULATOR_MP8859=y CONFIG_REGULATOR_MT6315=m CONFIG_REGULATOR_MT6357=y