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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:13 +0100 Message-Id: <20190903153633.6651-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c Subject: [Qemu-devel] [PULL 01/21] Revert "target/arm: Use unallocated_encoding for aarch32" X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This reverts commit 3cb36637157088892e9e33ddb1034bffd1251d3b. Despite the fact that the text for the call to gen_exception_insn is identical for aarch64 and aarch32, the implementation inside gen_exception_insn is totally different. This fixes exceptions raised from aarch64. Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson Reviewed-by: Laurent Desnogues Message-id: 20190826151536.6771-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.h | 2 ++ target/arm/translate.h | 2 -- target/arm/translate-a64.c | 7 +++++++ target/arm/translate-vfp.inc.c | 3 ++- target/arm/translate.c | 22 ++++++++++------------ 5 files changed, 21 insertions(+), 15 deletions(-) -- 2.20.1 diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 12ad8ac6ed1..9cd2b3d2389 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -18,6 +18,8 @@ #ifndef TARGET_ARM_TRANSLATE_A64_H #define TARGET_ARM_TRANSLATE_A64_H +void unallocated_encoding(DisasContext *s); + #define unsupported_encoding(s, insn) \ do { \ qemu_log_mask(LOG_UNIMP, \ diff --git a/target/arm/translate.h b/target/arm/translate.h index 92ef790be9e..64304c957ee 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -99,8 +99,6 @@ typedef struct DisasCompare { bool value_global; } DisasCompare; -void unallocated_encoding(DisasContext *s); - /* Share the TCG temporaries common between 32 and 64 bit modes. */ extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; extern TCGv_i64 cpu_exclusive_addr; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6fd0b779d37..9183f89ba39 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -338,6 +338,13 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) } } +void unallocated_encoding(DisasContext *s) +{ + /* Unallocated and reserved encodings are uncategorized */ + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); +} + static void init_tmp_a64_array(DisasContext *s) { #ifdef CONFIG_DEBUG_TCG diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 3e8ea80493b..5065d4524cd 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -108,7 +108,8 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) if (!s->vfp_enabled && !ignore_vfp_enabled) { assert(!arm_dc_feature(s, ARM_FEATURE_M)); - unallocated_encoding(s); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); return false; } diff --git a/target/arm/translate.c b/target/arm/translate.c index cbe19b7a625..2aac9aae681 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1231,13 +1231,6 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) s->base.is_jmp = DISAS_NORETURN; } -void unallocated_encoding(DisasContext *s) -{ - /* Unallocated and reserved encodings are uncategorized */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); -} - /* Force a TB lookup after an instruction that changes the CPU state. */ static inline void gen_lookup_tb(DisasContext *s) { @@ -1268,7 +1261,8 @@ static inline void gen_hlt(DisasContext *s, int imm) return; } - unallocated_encoding(s); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); } static inline void gen_add_data_offset(DisasContext *s, unsigned int insn, @@ -7580,7 +7574,8 @@ static void gen_srs(DisasContext *s, } if (undef) { - unallocated_encoding(s); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); return; } @@ -9201,7 +9196,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) break; default: illegal_op: - unallocated_encoding(s); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); break; } } @@ -10886,7 +10882,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } return; illegal_op: - unallocated_encoding(s); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); } static void disas_thumb_insn(DisasContext *s, uint32_t insn) @@ -11709,7 +11706,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) return; illegal_op: undef: - unallocated_encoding(s); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); } static bool insn_crosses_page(CPUARMState *env, DisasContext *s) From patchwork Tue Sep 3 15:36:14 2019 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:14 +0100 Message-Id: <20190903153633.6651-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 Subject: [Qemu-devel] [PULL 02/21] target/arm: Factor out unallocated_encoding for aarch32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Make this a static function private to translate.c. Thus we can use the same idiom between aarch64 and aarch32 without actually sharing function implementations. Signed-off-by: Richard Henderson Reviewed-by: Laurent Desnogues Message-id: 20190826151536.6771-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-vfp.inc.c | 3 +-- target/arm/translate.c | 22 ++++++++++++---------- 2 files changed, 13 insertions(+), 12 deletions(-) -- 2.20.1 diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 5065d4524cd..3e8ea80493b 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -108,8 +108,7 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) if (!s->vfp_enabled && !ignore_vfp_enabled) { assert(!arm_dc_feature(s, ARM_FEATURE_M)); - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + unallocated_encoding(s); return false; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 2aac9aae681..66311580c05 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1231,6 +1231,13 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) s->base.is_jmp = DISAS_NORETURN; } +static void unallocated_encoding(DisasContext *s) +{ + /* Unallocated and reserved encodings are uncategorized */ + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); +} + /* Force a TB lookup after an instruction that changes the CPU state. */ static inline void gen_lookup_tb(DisasContext *s) { @@ -1261,8 +1268,7 @@ static inline void gen_hlt(DisasContext *s, int imm) return; } - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + unallocated_encoding(s); } static inline void gen_add_data_offset(DisasContext *s, unsigned int insn, @@ -7574,8 +7580,7 @@ static void gen_srs(DisasContext *s, } if (undef) { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + unallocated_encoding(s); return; } @@ -9196,8 +9201,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) break; default: illegal_op: - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + unallocated_encoding(s); break; } } @@ -10882,8 +10886,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } return; illegal_op: - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + unallocated_encoding(s); } static void disas_thumb_insn(DisasContext *s, uint32_t insn) @@ -11706,8 +11709,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) return; illegal_op: undef: - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + unallocated_encoding(s); } static bool insn_crosses_page(CPUARMState *env, DisasContext *s) From patchwork Tue Sep 3 15:36:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 172811 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp19679ily; Tue, 3 Sep 2019 08:41:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqze1oH+258DOzbLjPc0KCfJGz3KDUHJA6K9UBV2Cv9IHUlNbJfu/YmOzkzigdwEZWFVDje4 X-Received: by 2002:a17:906:6792:: with SMTP id q18mr21375461ejp.80.1567525306247; Tue, 03 Sep 2019 08:41:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567525306; cv=none; d=google.com; s=arc-20160816; b=CBj4BuJqhCrzhAOJikEus63TQVNHqcfbMIRpnqUT+bRtKvw/8TmQBQUvvkdOCPYGMG 0xFZO5BNnZLH2YIE6BHxxkM29JYACeo1Oa8wQIiNmkR4LJvWvHHPtN3NYn+vDErH53Yz EAn4dKtgJ6Il4F+PjF4/zjysi77D3RorLeruBjE52pGyTb5dg0wrSePAo1OAbWnfQn1F 7RxXp07bE7QPrXg/RoZO5Yy41yoC1gltOH3UXyatP8gWTiQUNCyeDUogfXsjesXuOvkY k/9Kx3N5Nb3qeWb/rZe/ikpAkb9jxE8t35LxNGWV8CurBD6ebZUVCaC59HaISPeGISQc MPxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=bIBiqHwLNlw6akaBX7exBs2n/dBWc3wYnn3LUfBBjxw=; b=cJMMxF+MOHNAfOfL8JxbgotwVsSLtKYZEw5Y0vUMDENQJMpecRj+D5LyHL0aZT6RsG nHI5c3gkhGt/ZqjuySUqAdqvH5p0ngkfgtYDnK6rmaYs8aX8aEpujpm8m3Q7IW65wBob FazgmRul++cLGmbRxZm6kbnlJLXypac0EzoQ69nREXXQVUB1tRAKyzBDH49/PaNRSI/E EZVqbzUpcGlfeIwx2Flg7hyunS1RSj9cpmswM22kYSkT4si91Xk0jFXPqy0dZqfhSzPb +wmkcm/J7DPxPd4PR+bYjtjt7NajDiCWTTELELPQe68PMFetQ45noRfJZx2kOgTb84rg E2RA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="bJj/rovf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c15si8466347ejd.49.2019.09.03.08.41.45 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 03 Sep 2019 08:41:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="bJj/rovf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47702 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5AwC-0006Ul-Io for patch@linaro.org; Tue, 03 Sep 2019 11:41:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59140) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5ArK-0002h8-Jn for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5ArJ-0005sB-8f for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:42 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:53451) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5ArJ-0005ra-2M for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:41 -0400 Received: by mail-wm1-x341.google.com with SMTP id q19so9923449wmc.3 for ; Tue, 03 Sep 2019 08:36:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bIBiqHwLNlw6akaBX7exBs2n/dBWc3wYnn3LUfBBjxw=; b=bJj/rovfgKg8U81FEH4qt3vzVDA/yiq2X0ciAAwJsr0WM1L697GLHT1lvL/+It5ndd CfoG4ejG3laP3spJI9yywP8PV4wTHXEq/8Rh4Bqul7PAVJAPCW65nTDoL1UTlCZaXSW8 A4TpQDaF/j/BUWH/JBBG5Orx2Eel7cQUVTNOJWfyNSVBi6kCMgcrNGthcqLZbCXE1PJt 601FSERVzMYasqGCS3P8Aix1f+oQC1FX1uEcj8K0aF6Axt5Xl2PN210Z1OFSmoVbXVBr yK4cw6AwUnvHCP8qbdskAW3O3/DXY9C7yUDJa8nHkmdfU28oHBnx/LxLfV02bo3Eq5fV 6+NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bIBiqHwLNlw6akaBX7exBs2n/dBWc3wYnn3LUfBBjxw=; b=k5XS7UF7uAf7XV+UhP5in61d5l8CTcia9RVxmv3+iBhWR30mHMkV9Spmd33c+VTGGF 8mG3ahLo2dgWb92zziVge6c44O0o7zhtLz9po5Yie17ZLUlgaUxybcew+RHGjmlT6Hfd 3QDZ5umiI8nP4v2TcPMuhWAH8mz0znpyikMyGbpeyLuVFPPsw0Q/fCCOQn63999F10UG okt4+o/o6rsQVlQoxeUYegx218dRYDE4KklDGAMqJUUXx80atd35OnA+0O8PX4kMbk97 I1Dv4JwpCMjxxCYlaYllFS6wIK0MevwWm9Q0236HMj6Mt7vvrbAAxSJP+YEwyQQOGkIW CUWQ== X-Gm-Message-State: APjAAAVW9EJfsxNg/cORue9eo9DU1xWoBiMdZaI5o+qKf85HSRZiTgFN q0vLxks7VH5FUCGm93ba+lzHt3iabee8Ew== X-Received: by 2002:a1c:a404:: with SMTP id n4mr796752wme.41.1567524999788; Tue, 03 Sep 2019 08:36:39 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:15 +0100 Message-Id: <20190903153633.6651-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PULL 03/21] target/arm: Allow ARMCPRegInfo read/write functions to throw exceptions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently the only part of an ARMCPRegInfo which is allowed to cause a CPU exception is the access function, which returns a value indicating that some flavour of UNDEF should be generated. For the ATS system instructions, we would like to conditionally generate exceptions as part of the writefn, because some faults during the page table walk (like external aborts) should cause an exception to be raised rather than returning a value. There are several ways we could do this: * plumb the GETPC() value from the top level set_cp_reg/get_cp_reg helper functions through into the readfn and writefn hooks * add extra readfn_with_ra/writefn_with_ra hooks that take the GETPC() value * require the ATS instructions to provide a dummy accessfn, which serves no purpose except to cause the code generation to emit TCG ops to sync the CPU state * add an ARM_CP_ flag to mark the ARMCPRegInfo as possibly throwing an exception in its read/write hooks, and make the codegen sync the CPU state before calling the hooks if the flag is set This patch opts for the last of these, as it is fairly simple to implement and doesn't require invasive changes like updating the readfn/writefn hook function prototype signature. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Edgar E. Iglesias Message-id: 20190816125802.25877-2-peter.maydell@linaro.org --- target/arm/cpu.h | 6 +++++- target/arm/translate-a64.c | 6 ++++++ target/arm/translate.c | 7 +++++++ 3 files changed, 18 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0981303170a..297ad5e47ad 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2212,6 +2212,9 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) * IO indicates that this register does I/O and therefore its accesses * need to be surrounded by gen_io_start()/gen_io_end(). In particular, * registers which implement clocks or timers require this. + * RAISES_EXC is for when the read or write hook might raise an exception; + * the generated code will synchronize the CPU state before calling the hook + * so that it is safe for the hook to call raise_exception(). */ #define ARM_CP_SPECIAL 0x0001 #define ARM_CP_CONST 0x0002 @@ -2230,10 +2233,11 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 #define ARM_CP_NO_GDB 0x4000 +#define ARM_CP_RAISES_EXC 0x8000 /* Used only as a terminator for ARMCPRegInfo lists */ #define ARM_CP_SENTINEL 0xffff /* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x70ff +#define ARM_CP_FLAG_MASK 0xf0ff /* Valid values for ARMCPRegInfo state field, indicating which of * the AArch32 and AArch64 execution states this register is visible in. diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9183f89ba39..4d09ae6f424 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1714,6 +1714,12 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, tcg_temp_free_ptr(tmpptr); tcg_temp_free_i32(tcg_syn); tcg_temp_free_i32(tcg_isread); + } else if (ri->type & ARM_CP_RAISES_EXC) { + /* + * The readfn or writefn might raise an exception; + * synchronize the CPU state in case it does. + */ + gen_a64_set_pc_im(s->pc_curr); } /* Handle special cases first */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 66311580c05..78d93f63cab 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7191,6 +7191,13 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) tcg_temp_free_ptr(tmpptr); tcg_temp_free_i32(tcg_syn); tcg_temp_free_i32(tcg_isread); + } else if (ri->type & ARM_CP_RAISES_EXC) { + /* + * The readfn or writefn might raise an exception; + * synchronize the CPU state in case it does. + */ + gen_set_condexec(s); + gen_set_pc_im(s, s->pc_curr); } /* Handle special cases first */ From patchwork Tue Sep 3 15:36:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 172813 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp19757ily; Tue, 3 Sep 2019 08:41:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqx4MocqWdKqXz8674Gbcl+n8JSC4V6rqdNw39f6uj5SWD7JkoomD4xgrl+vGY4FzaXoyD8I X-Received: by 2002:aa7:d5cf:: with SMTP id d15mr36792197eds.67.1567525310727; Tue, 03 Sep 2019 08:41:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567525310; cv=none; d=google.com; s=arc-20160816; b=N/dvMI0o5/vi+j3zAIFtGC9pBu1XxT1K1oIBxXosAgXl3Tk4zI5bXfl3QpYnFnheGT IbKW6AFtsn2utEd70nFV4mENQH+/X7lS0IbM9N2v6GaD3VAEvtfKMFxMOjqqX1hGpLOH nZ05pcoiRyad33pCGljLM6gVQjrcD34v8BzLTdX8eY2BdL5bHh8NRa4F9UJSuokNp3jm 2r6MUjzqQCRr8s4A/44Kh5FFvlI3SZ/0xG0M80LeyJRNXC3d51KHaKR29noqOUpftv0t 6oW8ZULfjnNyFqsAOoUwTxE56d/JlsjUS9YLLcMsTL2MAsu5gM82c+1RDc+n45j63RXc BlVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=JQypItX8vVnzNLFYqeVXMmrdJt6+8bMgnIYYXwlAvtw=; b=BNgxOsiiV3qYdPpmYavhh3VjGBajei5czbPCHNmdjlcB436R2lcF110nA9hgkmBDsP QXoe8k+B0XfFi8OkDz9fHZ2P5c7w2GoIhluY4SbVAVcKqeX/MGq/QVLhHEzzSONauMUy 0jblHhKkawhlP9UoQ9ZJ2pBzyDfKsiqkIs8lSFgQBOy1TxLF+q019PIKnMIlBWA10qjw K766aUNCAFTJWSHFG/PpmdLddWd5PO+cE10dX1rUuvm4tqNAie4wWwTU2jYtvqhmmSnD QS4d5xcLqSrJfH04GFyizBLdIBKkP1kB7S/94NQf1JoQpHRVa8Hc0vF4lwWf/mjdAbr1 rdTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bJs6LA08; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:16 +0100 Message-Id: <20190903153633.6651-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PULL 04/21] target/arm: Take exceptions on ATS instructions when needed X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The translation table walk for an ATS instruction can result in various faults. In general these are just reported back via the PAR_EL1 fault status fields, but in some cases the architecture requires that the fault is turned into an exception: * synchronous stage 2 faults of any kind during AT S1E0* and AT S1E1* instructions executed from NS EL1 fault to EL2 or EL3 * synchronous external aborts are taken as Data Abort exceptions (This is documented in the v8A Arm ARM DDI0487A.e D5.2.11 and G5.13.4.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Edgar E. Iglesias Message-id: 20190816125802.25877-3-peter.maydell@linaro.org --- target/arm/helper.c | 107 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 92 insertions(+), 15 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 7e0d5398ab8..507026c9154 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2946,6 +2946,73 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, &prot, &page_size, &fi, &cacheattrs); + if (ret) { + /* + * Some kinds of translation fault must cause exceptions rather + * than being reported in the PAR. + */ + int current_el = arm_current_el(env); + int target_el; + uint32_t syn, fsr, fsc; + bool take_exc = false; + + if (fi.s1ptw && current_el == 1 && !arm_is_secure(env) + && (mmu_idx == ARMMMUIdx_S1NSE1 || mmu_idx == ARMMMUIdx_S1NSE0)) { + /* + * Synchronous stage 2 fault on an access made as part of the + * translation table walk for AT S1E0* or AT S1E1* insn + * executed from NS EL1. If this is a synchronous external abort + * and SCR_EL3.EA == 1, then we take a synchronous external abort + * to EL3. Otherwise the fault is taken as an exception to EL2, + * and HPFAR_EL2 holds the faulting IPA. + */ + if (fi.type == ARMFault_SyncExternalOnWalk && + (env->cp15.scr_el3 & SCR_EA)) { + target_el = 3; + } else { + env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; + target_el = 2; + } + take_exc = true; + } else if (fi.type == ARMFault_SyncExternalOnWalk) { + /* + * Synchronous external aborts during a translation table walk + * are taken as Data Abort exceptions. + */ + if (fi.stage2) { + if (current_el == 3) { + target_el = 3; + } else { + target_el = 2; + } + } else { + target_el = exception_target_el(env); + } + take_exc = true; + } + + if (take_exc) { + /* Construct FSR and FSC using same logic as arm_deliver_fault() */ + if (target_el == 2 || arm_el_is_aa64(env, target_el) || + arm_s1_regime_using_lpae_format(env, mmu_idx)) { + fsr = arm_fi_to_lfsc(&fi); + fsc = extract32(fsr, 0, 6); + } else { + fsr = arm_fi_to_sfsc(&fi); + fsc = 0x3f; + } + /* + * Report exception with ESR indicating a fault due to a + * translation table walk for a cache maintenance instruction. + */ + syn = syn_data_abort_no_iss(current_el == target_el, + fi.ea, 1, fi.s1ptw, 1, fsc); + env->exception.vaddress = value; + env->exception.fsr = fsr; + raise_exception(env, EXCP_DATA_ABORT, syn, target_el); + } + } + if (is_a64(env)) { format64 = true; } else if (arm_feature(env, ARM_FEATURE_LPAE)) { @@ -3150,7 +3217,7 @@ static const ARMCPRegInfo vapa_cp_reginfo[] = { /* This underdecoding is safe because the reginfo is NO_RAW. */ { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .accessfn = ats_access, - .writefn = ats_write, .type = ARM_CP_NO_RAW }, + .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, #endif REGINFO_SENTINEL }; @@ -4283,35 +4350,45 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { /* 64 bit address translation operations */ { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, - .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, - .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, - .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, - .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, - .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, - .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, - .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, - .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, - .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, - .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, @@ -4893,11 +4970,11 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, .access = PL2_W, .accessfn = at_s1e2_access, - .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, .access = PL2_W, .accessfn = at_s1e2_access, - .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, + .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose @@ -4905,10 +4982,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { */ { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, .access = PL2_W, - .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, + .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, .access = PL2_W, - .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, + .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the From patchwork Tue Sep 3 15:36:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 172812 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp19710ily; Tue, 3 Sep 2019 08:41:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqz8PwQdFpE6oHYSpXqolks8laTNXQOEB59fZSCaobZWJexKCTPw6HMRXq7tVziWVJBLHcGK X-Received: by 2002:a50:de08:: with SMTP id z8mr36633235edk.121.1567525307738; Tue, 03 Sep 2019 08:41:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567525307; cv=none; d=google.com; s=arc-20160816; b=LcLsPtm6XP67LQAmVjF1hGZ87qka9PH+jhsw3AwaWNl/XP+Rx0eHagAEZc92eDOFY2 S0kv/VQPNsMYFwYB6WByx53XHLjs+xPlpOQLwR3ZYJelOxkgdYg2pqiXMmOU+D+HMZrY EmGfzcq2JVFsxZ5Fky/9XiR0PaXonkzmmvQRWyYwADO057T8HgDCkg4zulp0ZSKhGD4I gbCkzZ/UlQ0vrbxAp371EqL9QHvVE5PdFrgEWdCXnZp15mVjorkzS7b0mIY2nSfquq9l MyG5fQb4YfY2wrTJ8I1UeP5a/yLEaE3sSyzHtQj5FhryrpTFw4qjQ1CS+bPgODE7dW4/ V7Gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=m+TKKTWvRC4vo5fFotjFs4jfzAaPam+tpeNKcBhEHyY=; b=i62dlPBm7ZBFgsFnkFqCCawBVu/QWIv+PW1ZQOz+QMlc7MlceckVnB8A16hJGr5/Jq MFYvh8D/kJmsq98IQL59rlzna6jsCFS2N/Oi9exKQxSjFMn1Jx2diAII3w1lYPIbHo8O gYPWystpceUqQPrri/Mh9tPm3iUlH/kHx0C9s2D6I4+7qdElXT3CndjXJ1sY8wustO6Z ERQ3JM5/5MLOi787t9yv5ik/T1jxpH/KJH0FXe52JPN7OFGnVPskVGB/eFYWeP8xbajy NvCRFj6QvBwNg8Pz3IpdxIYQN5W/NhjiYwv1zAN6wnZwzuAQHb0DGxa9n4AM6HtF4303 5prQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LtU2+jem; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:17 +0100 Message-Id: <20190903153633.6651-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42b Subject: [Qemu-devel] [PULL 05/21] aspeed/timer: Provide back-pressure information for short periods X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jeffery First up: This is not the way the hardware behaves. However, it helps resolve real-world problems with short periods being used under Linux. Commit 4451d3f59f2a ("clocksource/drivers/fttmr010: Fix set_next_event handler") in Linux fixed the timer driver to correctly schedule the next event for the Aspeed controller, and in combination with 5daa8212c08e ("ARM: dts: aspeed: Describe random number device") Linux will now set a timer with a period as low as 1us. Configuring a qemu timer with such a short period results in spending time handling the interrupt in the model rather than executing guest code, leading to noticeable "sticky" behaviour in the guest. The behaviour of Linux is correct with respect to the hardware, so we need to improve our handling under emulation. The approach chosen is to provide back-pressure information by calculating an acceptable minimum number of ticks to be set on the model. Under Linux an additional read is added in the timer configuration path to detect back-pressure, which will never occur on hardware. However if back-pressure is observed, the driver alerts the clock event subsystem, which then performs its own next event dilation via a config option - d1748302f70b ("clockevents: Make minimum delay adjustments configurable") A minimum period of 5us was experimentally determined on a Lenovo T480s, which I've increased to 20us for "safety". Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Reviewed-by: Philippe Mathieu-Daudé Tested-by: Joel Stanley Signed-off-by: Cédric Le Goater Message-id: 20190704055150.4899-1-clg@kaod.org [clg: - changed the computation of min_ticks to be done each time the timer value is reloaded. It removes the ordering issue of the timer and scu reset handlers but is slightly slower ] - introduced TIMER_MIN_NS - introduced calculate_min_ticks() ] Signed-off-by: Cédric Le Goater Signed-off-by: Peter Maydell --- hw/timer/aspeed_timer.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index ed81d5c44c7..59c2bbeee60 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -44,6 +44,13 @@ enum timer_ctrl_op { op_pulse_enable }; +/* + * Minimum value of the reload register to filter out short period + * timers which have a noticeable impact in emulation. 5us should be + * enough, use 20us for "safety". + */ +#define TIMER_MIN_NS (20 * SCALE_US) + /** * Avoid mutual references between AspeedTimerCtrlState and AspeedTimer * structs, as it's a waste of memory. The ptimer BH callback needs to know @@ -98,6 +105,14 @@ static inline uint32_t calculate_ticks(struct AspeedTimer *t, uint64_t now_ns) return t->reload - MIN(t->reload, ticks); } +static uint32_t calculate_min_ticks(AspeedTimer *t, uint32_t value) +{ + uint32_t rate = calculate_rate(t); + uint32_t min_ticks = muldiv64(TIMER_MIN_NS, rate, NANOSECONDS_PER_SECOND); + + return value < min_ticks ? min_ticks : value; +} + static inline uint64_t calculate_time(struct AspeedTimer *t, uint32_t ticks) { uint64_t delta_ns; @@ -261,7 +276,7 @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg, switch (reg) { case TIMER_REG_RELOAD: old_reload = t->reload; - t->reload = value; + t->reload = calculate_min_ticks(t, value); /* If the reload value was not previously set, or zero, and * the current value is valid, try to start the timer if it is From patchwork Tue Sep 3 15:36:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 172815 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp22330ily; Tue, 3 Sep 2019 08:44:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqx4gM/P0IKjJ5eE3b0W7FMVj2Xt5GRDeG8ECLVng02mpGjCnRnYOYOj2swLf0cLOA/wrOWG X-Received: by 2002:a17:906:a03:: with SMTP id w3mr14462695ejf.218.1567525443412; Tue, 03 Sep 2019 08:44:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567525443; cv=none; d=google.com; s=arc-20160816; b=SevPsONX+YGRYJnJhRVxbARaH98fqbXZdEgWwd1mS1DV/wFtqHLbiKph4Xq7UNQOB4 bjBqkJEYEdEFTI/MfsBH4dH+vZg6nMIPhjSLR4Wg9YOFiI4ivmj3U62VCkEo333QU2ny MqJlhbx0bYCwgglkeI/6fzadCQjUFt2l9hXeGI5sCejIHHtFp4aJzL7JSEzHe8MNgman oSvU0+X+2vgolTtf9gGhDyvhhpvCVvuSCpHYKtD8DfbAflzlDA1/bTB6DMREUMNt3XSf NaP1jysegeHd/D5Rb+B+klBPFaBkR7DhlZukEC8+RIWEJEUIfcE9vIUDV66VEztiG7XW NZSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=NH3h4g6hlFhS6RKG3sIpGzTOMf5SCVInEe1V7vBG3qg=; b=vfIRPh9TVZuafxg9ajPceI3wa8ibv+3U3P8aDL/s8ccaBxwYFAOA31Ffv9VaQvmlFq VIwl7hxMR0b5yQ3gM+CFVZ2kc630Ghscw12lq9rUzaVX2zHWjlfvWIhDzdX7kxpf6cwP aJNazcrDcyottgi+SUKEoUguhF5jg93+eEsxBpS+BX6RJBrUQFQjXZdNRPHtSRTlLb4R oosB0S1ZqYdfygCfCaHzXeMKElLnvixjfEhGqPu9AZj98T0XZHDe1J5I+JA7hNcHfKoo xJj2/WfVDBUllvAwL6S5S9sLOE3XZo9JyWHnzcd8FRJw7NLGP1mLShESZpUEaxgpIneo IWWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jtOX8o8a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:18 +0100 Message-Id: <20190903153633.6651-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::435 Subject: [Qemu-devel] [PULL 06/21] memory: Remove unused memory_region_iommu_replay_all() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger memory_region_iommu_replay_all is not used. Remove it. Signed-off-by: Eric Auger Reported-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Xu Message-id: 20190822172350.12008-2-eric.auger@redhat.com Signed-off-by: Peter Maydell --- include/exec/memory.h | 10 ---------- memory.c | 9 --------- 2 files changed, 19 deletions(-) -- 2.20.1 diff --git a/include/exec/memory.h b/include/exec/memory.h index fddc2ff48a7..ecca388e69d 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1086,16 +1086,6 @@ void memory_region_register_iommu_notifier(MemoryRegion *mr, */ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n); -/** - * memory_region_iommu_replay_all: replay existing IOMMU translations - * to all the notifiers registered. - * - * Note: this is not related to record-and-replay functionality. - * - * @iommu_mr: the memory region to observe - */ -void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr); - /** * memory_region_unregister_iommu_notifier: unregister a notifier for * changes to IOMMU translation entries. diff --git a/memory.c b/memory.c index 7fd93b1d42d..a23ff3cc2ac 100644 --- a/memory.c +++ b/memory.c @@ -1922,15 +1922,6 @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n) } } -void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr) -{ - IOMMUNotifier *notifier; - - IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) { - memory_region_iommu_replay(iommu_mr, notifier); - } -} - void memory_region_unregister_iommu_notifier(MemoryRegion *mr, IOMMUNotifier *n) { From patchwork Tue Sep 3 15:36:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 172816 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp24758ily; Tue, 3 Sep 2019 08:46:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqyQMF9DnY41p/CLCHbzVXswREi/dVXdyXOC7H2SVC+2/OQd/fc0pnVc6oMkNFKAJMvHAMrp X-Received: by 2002:a17:906:4ac1:: with SMTP id u1mr19118225ejt.293.1567525571252; Tue, 03 Sep 2019 08:46:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567525571; cv=none; d=google.com; s=arc-20160816; b=SwUp6P0rtSKzt+zhnxGIFOCL6GSPQshb05WmvhBZEeiQdPOKhY7a/016uwFonjYWUI SQ/+Vbr+w284S4yPDggsCIzDDD51+mAK+aNIDi148RHk9sGetTKcqeec8d6nRJ0JIdSp jcfoJ/390zZBsc7gUPd47r1Vj8RsEJLHcfpzFCb3weaPbcw5eDCQKVtJzXeVeiq4neYn TZvsvLLBNSYwtLtL6c1KiD9Nf7rvSXoTjEZEphAGgKj9ZHRMWoR9/+1oSri285F8xfD/ VmZDxCIiX+MMh77w1P+3ZA5qbAvH7pXSOgoFOC4oJ61T5Hy8s/T2+J6j7Xkm8CmCdTzF LybA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=E0RGpyIRgwmsLzuSGhRDQK2g3xA+f5Ux3QZOYd+L+vg=; b=tdWsN3/tjFiem7Edd14dtNHRWOnGBa4hgnWjG31v8WwuMQwovUT525jxJI5H9GXBc6 zWEPbcrqC+Lmn2ForveEzmOf3uYJjTgZSfcROJOlt7589qw6dlAA377Y2TiMU6iVEQzE G6wn+WpYrXG5j2Sgevu6xQH8Egfb5VUlZCPimxZ6O4YOEGrjrar0A++CCYLlATCM7NbH Xuk0Rx/epkS4b4aC9cP2Fng/AVeBcPxwCIYR8pa6MH2MEDdn2LVCMaiewM4OuzQviy5V ti3wy768v+IQdmcSOo0h6JfAP9UivqWpr8p/fZLbbtoo7c7iYmPhZ46n82ylFokY3dpJ VjEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=X4G4gp8m; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:19 +0100 Message-Id: <20190903153633.6651-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 Subject: [Qemu-devel] [PULL 07/21] hw/arm/smmuv3: Log a guest error when decoding an invalid STE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger Log a guest error when encountering an invalid STE. Signed-off-by: Eric Auger Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190822172350.12008-5-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 1 + 1 file changed, 1 insertion(+) -- 2.20.1 diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 2eaf07fb5f6..31ac4b15c30 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -320,6 +320,7 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, uint32_t config; if (!STE_VALID(ste)) { + qemu_log_mask(LOG_GUEST_ERROR, "invalid STE\n"); goto bad_ste; } From patchwork Tue Sep 3 15:36:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 172819 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp30256ily; Tue, 3 Sep 2019 08:50:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqw9O2R8MsUTrKGIk6z3WH61V2ZaUsmg8oSDW43yrsjwojHU7zsCCEqC/il5RPQ3tU+OnVt6 X-Received: by 2002:ae9:e117:: with SMTP id g23mr35752006qkm.100.1567525837569; Tue, 03 Sep 2019 08:50:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567525837; cv=none; d=google.com; s=arc-20160816; b=yU7Mj+vgPHotJn9J6p/UBOQB+PEQbWiBZCg2mcaGPwnmBGKkQQAYUqWF1uS60I+Xez mazsITePiWTHIecbyqgsmMfegDkIM1NpQaXfsaQ4IDHRBA3393hfLLokWokt9hKrZTjx OdKfcw7KIauuOrLYS7/xExVjs1w0w4ZHeFtO0pXZg7S651sDHILLBbH+lNAligT+tMja mHs2ogU5vgFkLNC6UxnUxwapfLn3Kt4pHSNgXq+P94x0UlYpre+RramkkcNfts6Ie2+i oqcZcGLpYsDsJzA4QIyC/DsAR09rjzwL0wPywPXdUH8k+KlhWK8Pz91+HBL/70lhzFXP M/MQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=zwgsbRC7S/9tqfeU7JxypMKTOKpf8DEKt23oGutI3as=; b=ywj7BjxHb44SVmb1PyZy8GrDHh7CPdeKK4uDW5tQL6eQPRyGdiQaQaNHWj/l7p+f4h cykDGowdZE40mei+J0kmBfq3hs+XLPbYq5SxsTJN/LrtU09T6UnRuQ4SF1pU0yjDUGFp 6A4dU7r35mdog2qPNWJ0QXY+t0AxVa63EFLakppKxw9VXrxxpwAO4BdZvjX9v/nvHpdP 7u4XjlXyPqTqr/rjEpfbsQPec6fOWGIAW7m2LgEIVr1zREJyxo4LZOBm7NY5b6QLwRHq n9nm437yPr0lqBgOc5Tp2na25VS76flD0hWszDjZh5neJYnBP8WnwOJ+xj4IXU4AXoMf eLkw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=o91Y+kEZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x14si10453135qtf.96.2019.09.03.08.50.37 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 03 Sep 2019 08:50:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=o91Y+kEZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47849 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5B4m-0005dg-8t for patch@linaro.org; Tue, 03 Sep 2019 11:50:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59220) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5ArQ-0002ov-7f for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5ArO-0005wO-Uf for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:48 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:37757) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5ArO-0005w0-ON for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:46 -0400 Received: by mail-wr1-x434.google.com with SMTP id z11so17998295wrt.4 for ; Tue, 03 Sep 2019 08:36:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zwgsbRC7S/9tqfeU7JxypMKTOKpf8DEKt23oGutI3as=; b=o91Y+kEZ9ekJhZ76S0+e42h5hPE+3kvnLpVzMB6dhI+DFwhhNUYHILeaREJX1UJzKl oVdSpgzLxEAdhulwoDfUTWicwSlMXkWsMT2J3OZ1oKmi2FAQsaeluiatxD5Y4+Lvyqi1 o+7XHPB8iWqEEeefzKQpvmudreDJ0UYXfrviw+EAFct0zrOG/YgMUE39nhZ59LuxPzdu TSC+g8j1KOtChSr1V97Im4Q6/VH0bsaeyKkHc+Og7rYiXBy8KGEndtSfJFPZ3hZNZQWO Cac6bQVFLX9jwi9BkBMufl5/48Nm9zMN3P5PLzMbqSgrSfsfzUYU9Lr0GmZHEzA7Ll27 mhaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zwgsbRC7S/9tqfeU7JxypMKTOKpf8DEKt23oGutI3as=; b=pr77NqenQARtAYF08SKV+iOuYlFHnHYmfSwD8OpdULhQIQPBk3dARc59ZF1oyagKzl IoUxhIGD3E4xMC8c8e/IfOqPaZ9I9aSE+uv7FrMzCpE8PUrKKlHHtuC+H3Q9Nbxvwy8m Yxa0XOBXKHS0buCydCAo28ulLFjORpz+pcL79ptcBx2nj+QLpNj7AhMaDctD58FG4fxy w/Zh7WckMQg+1EvlRU4kTvD5uf5mnosiZfOuWFiHzFCJYaH8z1bmN+8/wBtEhC9MMSjy 8iVpnqz7weKI5ka694nkEXgH4EugBh7PGIvrIOYL0fUVuZuq16Ft65YqNxSK86UNN8p3 VaCQ== X-Gm-Message-State: APjAAAV3XaOlFuu1trcJckr0Lb+CPcVmyRWJM3Lap5nv6q3PeofBlL/G OBHyFeu/lagQDQMIAdUeXciyWUHHF5E2AA== X-Received: by 2002:adf:fb11:: with SMTP id c17mr1500573wrr.0.1567525005632; Tue, 03 Sep 2019 08:36:45 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:20 +0100 Message-Id: <20190903153633.6651-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 Subject: [Qemu-devel] [PULL 08/21] hw/arm/smmuv3: Remove spurious error messages on IOVA invalidations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger An IOVA/ASID invalidation is notified to all IOMMU Memory Regions through smmuv3_inv_notifiers_iova/smmuv3_notify_iova. When the notification occurs it is possible that some of the PCIe devices associated to the notified regions do not have a valid stream table entry. In that case we output a LOG_GUEST_ERROR message, for example: invalid sid= (L1STD span=0) "smmuv3_notify_iova error decoding the configuration for iommu mr= This is unfortunate as the user gets the impression that there are some translation decoding errors whereas there are not. This patch adds a new field in SMMUEventInfo that tells whether the detection of an invalid STE must lead to an error report. invalid_ste_allowed is set before doing the invalidations and kept unset on actual translation. The other configuration decoding error messages are kept since if the STE is valid then the rest of the config must be correct. Signed-off-by: Eric Auger Message-id: 20190822172350.12008-6-eric.auger@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 1 + hw/arm/smmuv3.c | 19 +++++++++++-------- 2 files changed, 12 insertions(+), 8 deletions(-) -- 2.20.1 diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index b160289cd12..d190181ef1b 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -381,6 +381,7 @@ typedef struct SMMUEventInfo { uint32_t sid; bool recorded; bool record_trans_faults; + bool inval_ste_allowed; union { struct { uint32_t ssid; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 31ac4b15c30..db051dcac87 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -320,7 +320,9 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, uint32_t config; if (!STE_VALID(ste)) { - qemu_log_mask(LOG_GUEST_ERROR, "invalid STE\n"); + if (!event->inval_ste_allowed) { + qemu_log_mask(LOG_GUEST_ERROR, "invalid STE\n"); + } goto bad_ste; } @@ -407,8 +409,10 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, if (!span) { /* l2ptr is not valid */ - qemu_log_mask(LOG_GUEST_ERROR, - "invalid sid=%d (L1STD span=0)\n", sid); + if (!event->inval_ste_allowed) { + qemu_log_mask(LOG_GUEST_ERROR, + "invalid sid=%d (L1STD span=0)\n", sid); + } event->type = SMMU_EVT_C_BAD_STREAMID; return -EINVAL; } @@ -603,7 +607,9 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); SMMUv3State *s = sdev->smmu; uint32_t sid = smmu_get_sid(sdev); - SMMUEventInfo event = {.type = SMMU_EVT_NONE, .sid = sid}; + SMMUEventInfo event = {.type = SMMU_EVT_NONE, + .sid = sid, + .inval_ste_allowed = false}; SMMUPTWEventInfo ptw_info = {}; SMMUTranslationStatus status; SMMUState *bs = ARM_SMMU(s); @@ -796,16 +802,13 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, dma_addr_t iova) { SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); - SMMUEventInfo event = {}; + SMMUEventInfo event = {.inval_ste_allowed = true}; SMMUTransTableInfo *tt; SMMUTransCfg *cfg; IOMMUTLBEntry entry; cfg = smmuv3_get_config(sdev, &event); if (!cfg) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s error decoding the configuration for iommu mr=%s\n", - __func__, mr->parent_obj.name); return; } From patchwork Tue Sep 3 15:36:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 172810 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp16901ily; Tue, 3 Sep 2019 08:39:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqy70UfRzERgDiVucFrgl08FL5Rh5MHRJcU8a9YTXWWrvk/iaJO14WDnjpDEiLOH0Ie3xL/8 X-Received: by 2002:ac8:67c7:: with SMTP id r7mr34352666qtp.372.1567525185287; Tue, 03 Sep 2019 08:39:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567525185; cv=none; d=google.com; s=arc-20160816; b=iEGhFbqUtfRtwtBB1bafdm4BOUBUme9Uke/wD6AkPerkvOfHe+guPuwsgTVvxkpDZv 7MlUFAYmJwnxEq60GZp+iCVCOxi4m7YRJXNs5gjBSr/bE3M81Vz2ZrA9AZt1E4hky/U8 z5HYvedX1F1BsrBFJN6brCMRX493Yzbp2AXSnwkZbxF533umCl4LQO8Pk/pdpOxxfA0+ YvPi7+kQCC769i8Ne/RqvIaUB+bsaaKOD++168fB5/bXwF5Gg1/6NxafiCN6NNIltaQO RkcKHqFdjfEcLpnt8Zq8pUOnswww50O9wNHIv5vU7m5fqdgIOLexVV5Loot/7cJqeuCB 0bgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=NjtHLR890FdwVKLAyT2SN75yV6fIIwqW8EkRht8FO+8=; b=pehflqHcE8zwOYjE/Z7TCNimYykbYsWuZQGNVr7Hn1YnMF0tR5cwHqzjqcbBPP2yeu 83o9JEocNI6eL5mnSrXSb4hl9Z2WKNI2davUAMVGoh6qJAPslvBBjehzAMY7UoLySJBZ IYPa8P0K1VY9ZWkVi1Huc4Oyr6Y6QcJ3a8b67aiN83FOFZi+quDa3LXIJJjwYY7lmvco 5SlLRPf/+V7HNuwEvp9uZUgi8P+XYCXx41AuLAS9jWeAazzKMOln+bmVAAiz/kpkLCNh qzIJP4S+mcsF8sKlj8TNroXSVvRyCSxPW8IBY4QgUq9FMFypSM3obS6zoQGrtzFoD2Fn g90g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Zkenw7tN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:21 +0100 Message-Id: <20190903153633.6651-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::429 Subject: [Qemu-devel] [PULL 09/21] target/arm: Fix SMMLS argument order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The previous simplification got the order of operands to the subtraction wrong. Since the 64-bit product is the subtrahend, we must use a 64-bit subtract to properly compute the borrow from the low-part of the product. Fixes: 5f8cd06ebcf5 ("target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR") Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson Tested-by: Laurent Desnogues Message-id: 20190829013258.16102-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 78d93f63cab..cfebd35d268 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8831,7 +8831,16 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) if (rd != 15) { tmp3 = load_reg(s, rd); if (insn & (1 << 6)) { - tcg_gen_sub_i32(tmp, tmp, tmp3); + /* + * For SMMLS, we need a 64-bit subtract. + * Borrow caused by a non-zero multiplicand + * lowpart, and the correct result lowpart + * for rounding. + */ + TCGv_i32 zero = tcg_const_i32(0); + tcg_gen_sub2_i32(tmp2, tmp, zero, tmp3, + tmp2, tmp); + tcg_temp_free_i32(zero); } else { tcg_gen_add_i32(tmp, tmp, tmp3); } @@ -10075,7 +10084,14 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) if (insn & (1 << 20)) { tcg_gen_add_i32(tmp, tmp, tmp3); } else { - tcg_gen_sub_i32(tmp, tmp, tmp3); + /* + * For SMMLS, we need a 64-bit subtract. + * Borrow caused by a non-zero multiplicand lowpart, + * and the correct result lowpart for rounding. + */ + TCGv_i32 zero = tcg_const_i32(0); + tcg_gen_sub2_i32(tmp2, tmp, zero, tmp3, tmp2, tmp); + tcg_temp_free_i32(zero); } tcg_temp_free_i32(tmp3); } From patchwork Tue Sep 3 15:36:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 172823 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp33106ily; Tue, 3 Sep 2019 08:53:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqxFaiqTxcJI3jwhtqItzGxsf5mGRSNJ7FAsSd8e7aXrCwXaqjzUXsRbQOh8t2j2VPu0z8ts X-Received: by 2002:ae9:dec7:: with SMTP id s190mr34058043qkf.277.1567526005927; Tue, 03 Sep 2019 08:53:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567526005; cv=none; d=google.com; s=arc-20160816; b=VHHWo5TsJlDII6uFAw7Png5HQP5bPinxFrxbMdFZ5bt2pNkZ6IlTDYiN6GjPV4egp6 yLK3TGcYHzeaBDo8TlriVhcJZo6MQ8Ct63KOxqRKr/0Eo9ZnPDYQ+VbCj3CG/x1AMCMn W66mgBj8Hl5aRfMgtT5Fj+sMK+95Fwo2R8pSiCtdlFEFZs96wpVodbcpHNxAbmKCvbV9 v4dKO2S6QQ+A3rIPqWTwVKlbdc8OXcACeypkP6usdHRumJWbit+V2I5PBLU7IcmODF2O JvUUuZ7FV8u1dgMuH5rZ/rV9ziitzuG8EVFVO1XlgqteizxhSACfUBRGXxqxW2x8UaFL lsEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=9p80byA17XEFVio6ya05QPInVcwQ5DP56dNO6ng3AT0=; b=OdJ5jmQqm5JfL47ky4Q4+yxMSLTMS1Nmz5lJSX7WpHhpOsbyNUEKpYymRJI9mr7J4d H2U8iPnt5hwE3S6vI2UJ7ilXZU2SzBBeR1yQY9OtUTM9QlvZW7fkx6Xf/2mTHRWs2TCp GpEqMHlMPrfoMLby6w7OyS1FxrLe+j87XmqmPHdR+8MySJ00lp+ow//+riHpoYX320bA F6mgeAUFpjXtEQQLuPsIm2Hl09tNyDi24tcaKe9CaivCqBbZtPUv1woYq00C2dKrJeXu JUs1R5/mtfad6jn6hXmRcoxrJjQ7SZAhEghEhBEumBCBEZpeTnFlINHMFlbM7RNZnA4S VNnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aY3Iwa0I; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::32d Subject: [Qemu-devel] [PULL 10/21] hw/arm: Use ARM_CPU_TYPE_NAME() macro when appropriate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Commit ba1ba5cca introduce the ARM_CPU_TYPE_NAME() macro. Unify the code base by use it in all places. Reviewed-by: Alistair Francis Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20190823143249.8096-2-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/arm/allwinner-a10.c | 3 ++- hw/arm/cubieboard.c | 3 ++- hw/arm/digic.c | 3 ++- hw/arm/fsl-imx25.c | 2 +- hw/arm/fsl-imx31.c | 2 +- hw/arm/fsl-imx6.c | 3 ++- hw/arm/fsl-imx6ul.c | 2 +- hw/arm/xlnx-zynqmp.c | 8 ++++---- 8 files changed, 15 insertions(+), 11 deletions(-) -- 2.20.1 diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index 73810a44402..118032c8c72 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -30,7 +30,8 @@ static void aw_a10_init(Object *obj) AwA10State *s = AW_A10(obj); object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu), - "cortex-a8-" TYPE_ARM_CPU, &error_abort, NULL); + ARM_CPU_TYPE_NAME("cortex-a8"), + &error_abort, NULL); sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc), TYPE_AW_A10_PIC); diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index 38e0ca0f533..ed8d2333a07 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -81,7 +81,8 @@ static void cubieboard_init(MachineState *machine) static void cubieboard_machine_init(MachineClass *mc) { - mc->desc = "cubietech cubieboard"; + mc->desc = "cubietech cubieboard (Cortex-A9)"; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); mc->init = cubieboard_init; mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; diff --git a/hw/arm/digic.c b/hw/arm/digic.c index 4f524658756..22434a65a28 100644 --- a/hw/arm/digic.c +++ b/hw/arm/digic.c @@ -37,7 +37,8 @@ static void digic_init(Object *obj) int i; object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu), - "arm946-" TYPE_ARM_CPU, &error_abort, NULL); + ARM_CPU_TYPE_NAME("arm946"), + &error_abort, NULL); for (i = 0; i < DIGIC4_NB_TIMERS; i++) { #define DIGIC_TIMER_NAME_MLEN 11 diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 532d088298b..2b2fdb203a2 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -36,7 +36,7 @@ static void fsl_imx25_init(Object *obj) FslIMX25State *s = FSL_IMX25(obj); int i; - object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU); + object_initialize(&s->cpu, sizeof(s->cpu), ARM_CPU_TYPE_NAME("arm926")); sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic), TYPE_IMX_AVIC); diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index 1a37a7b997c..6760de3c8c1 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -33,7 +33,7 @@ static void fsl_imx31_init(Object *obj) FslIMX31State *s = FSL_IMX31(obj); int i; - object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU); + object_initialize(&s->cpu, sizeof(s->cpu), ARM_CPU_TYPE_NAME("arm1136")); sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic), TYPE_IMX_AVIC); diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 8c397ef04ba..552145b24ec 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -43,7 +43,8 @@ static void fsl_imx6_init(Object *obj) for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) { snprintf(name, NAME_SIZE, "cpu%d", i); object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]), - "cortex-a9-" TYPE_ARM_CPU, &error_abort, NULL); + ARM_CPU_TYPE_NAME("cortex-a9"), + &error_abort, NULL); } sysbus_init_child_obj(obj, "a9mpcore", &s->a9mpcore, sizeof(s->a9mpcore), diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index b074177a71d..c405b68d1dd 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -34,7 +34,7 @@ static void fsl_imx6ul_init(Object *obj) int i; object_initialize_child(obj, "cpu0", &s->cpu, sizeof(s->cpu), - "cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL); + ARM_CPU_TYPE_NAME("cortex-a7"), &error_abort, NULL); /* * A7MPCORE diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 0f587e63d35..fb03c60ebb8 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -196,8 +196,8 @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", &s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), - "cortex-r5f-" TYPE_ARM_CPU, &error_abort, - NULL); + ARM_CPU_TYPE_NAME("cortex-r5f"), + &error_abort, NULL); name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); if (strcmp(name, boot_cpu)) { @@ -237,8 +237,8 @@ static void xlnx_zynqmp_init(Object *obj) for (i = 0; i < num_apus; i++) { object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", &s->apu_cpu[i], sizeof(s->apu_cpu[i]), - "cortex-a53-" TYPE_ARM_CPU, &error_abort, - NULL); + ARM_CPU_TYPE_NAME("cortex-a53"), + &error_abort, NULL); } sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), From patchwork Tue Sep 3 15:36:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 172820 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp30288ily; Tue, 3 Sep 2019 08:50:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqwFYvNvELo7MjiLa8L+T8PUvS5//EM2ED2WPtQZwXvzNL808VonkmGHyS74BsGvzlFH1aPK X-Received: by 2002:a05:6214:1463:: with SMTP id c3mr5036226qvy.48.1567525838704; Tue, 03 Sep 2019 08:50:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567525838; cv=none; d=google.com; s=arc-20160816; b=EwX1DKDKqZ/0Q8oxsq7Wmt/KVBnloX1W8NrC8FSRTcRGFG0m8WIskDvAD4jnoNbJ8l KZyaKvzlfMokG6RmxxU6ctyME5MxutQoryEchYjZM4oGSvFz83q8Ls/LnqPMcFiZ2INg p0FCefeyYMyD/64N0fPGphLf2JB5ciJjRQqeYOu2dIFEnIUSZriZEMZai2NpQJVcESyL cZzbOlKsSU65s5hAAGzcwt8isvHAb7jssSML/Ig/8yfPnW0koAK7o0NzIFFxvAkI3E+Y oa/je1zsFc0iZsslXaqvAL7HDdyJP1tcIjPHxAktqsuPBeyJhJ4kzSXK5HDviucGTid3 a7kg== ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:23 +0100 Message-Id: <20190903153633.6651-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::336 Subject: [Qemu-devel] [PULL 11/21] hw/arm: Use object_initialize_child for correct reference counting X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé As explained in commit aff39be0ed97: Both functions, object_initialize() and object_property_add_child() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. Otherwise the child object will not be properly cleaned up when the parent gets destroyed. Thus let's use now object_initialize_child() instead to get the reference counting here right. Reviewed-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Message-id: 20190823143249.8096-3-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/arm/mcimx7d-sabre.c | 9 ++++----- hw/arm/mps2-tz.c | 15 +++++++-------- hw/arm/musca.c | 9 +++++---- 3 files changed, 16 insertions(+), 17 deletions(-) -- 2.20.1 diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index 97b8bb788a1..78b87c502fc 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -30,7 +30,6 @@ static void mcimx7d_sabre_init(MachineState *machine) { static struct arm_boot_info boot_info; MCIMX7Sabre *s = g_new0(MCIMX7Sabre, 1); - Object *soc; int i; if (machine->ram_size > FSL_IMX7_MMDC_SIZE) { @@ -49,10 +48,10 @@ static void mcimx7d_sabre_init(MachineState *machine) .nb_cpus = machine->smp.cpus, }; - object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX7); - soc = OBJECT(&s->soc); - object_property_add_child(OBJECT(machine), "soc", soc, &error_fatal); - object_property_set_bool(soc, true, "realized", &error_fatal); + object_initialize_child(OBJECT(machine), "soc", + &s->soc, sizeof(s->soc), + TYPE_FSL_IMX7, &error_fatal, NULL); + object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal); memory_region_allocate_system_memory(&s->ram, NULL, "mcimx7d-sabre.ram", machine->ram_size); diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index d85dc2c4bd8..6b24aaacded 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -427,10 +427,10 @@ static void mps2tz_common_init(MachineState *machine) /* The sec_resp_cfg output from the IoTKit must be split into multiple * lines, one for each of the PPCs we create here, plus one per MSC. */ - object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter), - TYPE_SPLIT_IRQ); - object_property_add_child(OBJECT(machine), "sec-resp-splitter", - OBJECT(&mms->sec_resp_splitter), &error_abort); + object_initialize_child(OBJECT(machine), "sec-resp-splitter", + &mms->sec_resp_splitter, + sizeof(mms->sec_resp_splitter), + TYPE_SPLIT_IRQ, &error_abort, NULL); object_property_set_int(OBJECT(&mms->sec_resp_splitter), ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc), "num-lines", &error_fatal); @@ -465,10 +465,9 @@ static void mps2tz_common_init(MachineState *machine) * Tx, Rx and "combined" IRQs are sent to the NVIC separately. * Create the OR gate for this. */ - object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate), - TYPE_OR_IRQ); - object_property_add_child(OBJECT(mms), "uart-irq-orgate", - OBJECT(&mms->uart_irq_orgate), &error_abort); + object_initialize_child(OBJECT(mms), "uart-irq-orgate", + &mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate), + TYPE_OR_IRQ, &error_abort, NULL); object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines", &error_fatal); object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true, diff --git a/hw/arm/musca.c b/hw/arm/musca.c index ddd8842732c..68db4b5b387 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -424,10 +424,11 @@ static void musca_init(MachineState *machine) * The sec_resp_cfg output from the SSE-200 must be split into multiple * lines, one for each of the PPCs we create here. */ - object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter), - TYPE_SPLIT_IRQ); - object_property_add_child(OBJECT(machine), "sec-resp-splitter", - OBJECT(&mms->sec_resp_splitter), &error_fatal); + object_initialize_child(OBJECT(machine), "sec-resp-splitter", + &mms->sec_resp_splitter, + sizeof(mms->sec_resp_splitter), + TYPE_SPLIT_IRQ, &error_fatal, NULL); + object_property_set_int(OBJECT(&mms->sec_resp_splitter), ARRAY_SIZE(mms->ppc), "num-lines", &error_fatal); object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true, From patchwork Tue Sep 3 15:36:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 172817 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp24815ily; Tue, 3 Sep 2019 08:46:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqxMdDidqPMzwnXcYOGH50pYTLfx1f35MIWCxnS8n2YobfQPiwxvgGHSowJStrqS9I24KOti X-Received: by 2002:a17:906:58f:: with SMTP id 15mr29303939ejn.19.1567525575067; Tue, 03 Sep 2019 08:46:15 -0700 (PDT) ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:24 +0100 Message-Id: <20190903153633.6651-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32f Subject: [Qemu-devel] [PULL 12/21] hw/arm: Use sysbus_init_child_obj for correct reference counting X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Both object_initialize() and qdev_set_parent_bus() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. In machine model code this refcount leak is not particularly problematic because (unlike devices) machines will never be created on demand via QMP, and they are never destroyed. But in any case let's use the new sysbus_init_child_obj() instead to get the reference counting here right. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20190823143249.8096-4-philmd@redhat.com [PMM: rewrote commit message] Signed-off-by: Peter Maydell --- hw/arm/exynos4_boards.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index f69358a5ba8..2781d8bd419 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -131,8 +131,8 @@ exynos4_boards_init_common(MachineState *machine, exynos4_boards_init_ram(s, get_system_memory(), exynos4_board_ram_size[board_type]); - object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC); - qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default()); + sysbus_init_child_obj(OBJECT(machine), "soc", + &s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC); object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal); From patchwork Tue Sep 3 15:36:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 172821 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp31308ily; Tue, 3 Sep 2019 08:51:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqywNsgCdtgmPZT03bkk5GR6ldTWvn96+SpfQobIaL6Ckm9vMJdIgMeD0dJZ385ZGvDoK2ru X-Received: by 2002:aa7:df81:: with SMTP id b1mr13497528edy.281.1567525897455; Tue, 03 Sep 2019 08:51:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567525897; cv=none; d=google.com; s=arc-20160816; b=sH+sGfFVPXysP2kMKXEtz5p7fbN9U8er01GBV9cFju88t0cJcE47aX5VIzU/lifbMq zjj8m/vQ/wgSkhcgnGtBKrnK59xcTzblD/rHql6JiQxkjW/XDN4Ei2bEWbJ8gAob0GHc DEBrWvyYsmAc2sYuBtWjd3yPR32QoOOtbKunrqj9Pi0TX8UPoUTalqEOWEjbm4L+rrGI M5eHMM/jMK1aR0G6irkf+uCr3yQgjw0t7Za8M2P9VLwKGuA7Ei67ZKd2HLEaKmXs3+1K aebbr7jZrmEgzk1KYfLIv7F833PhjgR0Rk47qErThaqlVR+Q0fpZIHCUVKf9Rv5imIcX cIaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=xlVfa4X6hgu0Qn72UxF4DtuCgLqcTN2WoNHXseq96d4=; b=Gpy6UTQWRtaglw+mgoq6JV3Sg3d506ZiVyOi8W4xbkMA12DXDm4E/q6eEO2gMWCGyk 07w+jsoL4MAbmjmOfIuAXk4IyWIkHptAlgCRxdXfUnZD/w4C2UAv0m3bhDfTKYcYgHmC /RxiFgICvCyabHs0FLFy6quaCAGX3x2sd0lrzUqEAz5ehz27hFQ6OYh4xM0+him8KtvP NCwM8LX3vFrdLne7jQAVMbYaJuny654ey2zEv2P7kxx4e/+dflq5yIt5fCrpB7tt2ANo oFrNTdmTg6dA/MGcgQJABzc02wmEB0px+Fl14uvwkHWHeb9RDZShiNs/OP7PAGDK15Gb cnFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ujKY9P2v; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:25 +0100 Message-Id: <20190903153633.6651-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::330 Subject: [Qemu-devel] [PULL 13/21] hw/arm/fsl-imx: Add the cpu as child of the SoC object X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Child properties form the composition tree. All objects need to be a child of another object. Objects can only be a child of one object. Respect this with the i.MX SoC, to get a cleaner composition tree. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20190823143249.8096-5-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/arm/fsl-imx25.c | 4 +++- hw/arm/fsl-imx31.c | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 2b2fdb203a2..3cb5a8fdfd7 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -36,7 +36,9 @@ static void fsl_imx25_init(Object *obj) FslIMX25State *s = FSL_IMX25(obj); int i; - object_initialize(&s->cpu, sizeof(s->cpu), ARM_CPU_TYPE_NAME("arm926")); + object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu), + ARM_CPU_TYPE_NAME("arm926"), + &error_abort, NULL); sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic), TYPE_IMX_AVIC); diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index 6760de3c8c1..55e90d104bc 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -33,7 +33,9 @@ static void fsl_imx31_init(Object *obj) FslIMX31State *s = FSL_IMX31(obj); int i; - object_initialize(&s->cpu, sizeof(s->cpu), ARM_CPU_TYPE_NAME("arm1136")); + object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu), + ARM_CPU_TYPE_NAME("arm1136"), + &error_abort, NULL); sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic), TYPE_IMX_AVIC); From patchwork Tue Sep 3 15:36:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 172814 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp19991ily; Tue, 3 Sep 2019 08:42:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqzRT1i0FpfkBnrOH0bNqkNEwMOAA6lpojOysLDofXnJ1zwwIZfUcjftg99D1P+M2gDOj0VH X-Received: by 2002:a50:d6db:: with SMTP id l27mr14488274edj.164.1567525321968; Tue, 03 Sep 2019 08:42:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567525321; cv=none; d=google.com; s=arc-20160816; b=zcHq5PMhKNjatKpwmta2AtumEoEgNMCcIbC4iV3BlLusYg0NimLSoIbFCEm9AksMO5 f3mWB5XtIQwWD17qm1pxOMHuzcarBtM48eoWsyCssfX/H6VbhvwwrBKynvHSfqdF3JC6 cR61QTMO47a8IvgNeprkPKsAvNoVIZ4r05opclvVTbtkuWoIxTsP0D7F4g0/mbzEcIOn zNgrEfNOBX9I+3p3iuVZb4yYTnWzFllSJf/ZO6mruQLU7KuLfonglkTswmg4pIsUz228 zqJSaooHJDhhI8NrtecrONI9ECJeBg27KS1qigZWvykUSWZFvta9tgRWdE5sId4xL6Zh TvSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Jh428xFMZspE9pzmT4T/vs6lA+3UmLCdDqsT/xMT5PA=; b=VFw4hu0TRYM/cGMqniFkQ20eiOr6m2TtCiPI2zXgk8XnEk9ankRvr85+6eoK/735IS 2MqIPfUwX03yAIudb40hLpfDHKU6+QZUGOS0UKzYQNkHRmgD1VrKGXTU/VfhOP5ftO0Q vYJA+0z4sILZx+aG3swGWGEZXs5u5+gQjXw38ZsUdH/DrSVvQdUy+RVFeQ85lU+leTRn qXNVuEg1KWY3jSDNKTkUAFe1NO2KsLGATpxzzhRsYOkWnjgv6yt6tIbDMVJYaZlC/byJ EbPqvC3PXtEa4Xnimc/qav4gxD6BKnmWT8TWLLsxitDyLquGHdsRm+wZrhZnY6ERqQ5d ceBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rPK2hf4T; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b27si4809567eje.123.2019.09.03.08.42.01 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 03 Sep 2019 08:42:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rPK2hf4T; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47722 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5AwS-0007yn-Ar for patch@linaro.org; Tue, 03 Sep 2019 11:42:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59294) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5ArW-0002yB-Hy for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5ArV-00060q-CY for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:54 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:53089) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5ArV-00060F-6C for qemu-devel@nongnu.org; Tue, 03 Sep 2019 11:36:53 -0400 Received: by mail-wm1-x329.google.com with SMTP id t17so18753650wmi.2 for ; Tue, 03 Sep 2019 08:36:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Jh428xFMZspE9pzmT4T/vs6lA+3UmLCdDqsT/xMT5PA=; b=rPK2hf4Tm3a3xnzX1tqtxXub5x15pPJcI11sH/pYEdjJd7Vy+LC5W4UsULfAUXDnMD G60b3LkNc7BxVSKh2wjvodE/SxtrWKQhWuyGChggHeundz6Zhkv555z0VDhAgviIjzSY DYgjsNFXUYpomxw1k1zXyySCTj01a9XGQ5j9WqqEYTfQRYqh0FkwT0rsKmaF6gIVXqW5 /5Zp4/1G1BO/q6vz2BWnxbzL64E3xCvOyyhoKDUJwPzbt0A/61+lsNQxfWadS5P7qMZd 6g/3sB31q74KZft20MC/cxOCiBoZIuZUtO3XErk/v2xjspGEqs+k1KEY3dlpIGG4lmgV mZPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Jh428xFMZspE9pzmT4T/vs6lA+3UmLCdDqsT/xMT5PA=; b=p5VEyZiz7aoHEgMYLuNYtcv702FQIuiVZAEmDqdnw5mecESQbkYfsxNUOtHaPV9Zwi 7mc1ff1y+0suyy3ItHV/tNcCmYlpVLBSUFzjzqagwYrkNW1hu7bBR2C2WuaGQ2dJMjKf iTMniYzfgti4yQ78j+P2AeDRsEAkPPCLyZzVQTKYjXxA7EjxwIfaXQDnYO8iBkhflmEE yT04S5/HtGyASC9Q6OiF05FDSmmtKBwvzAmQHzOT1n1IQBi6K/h7/RWVjJOxAXBFYEsA 0eBwgF2EJdmgC1/OE79CmbaTgfiL/32s12Fp7XjumOK/dA76sQBS/KzaF/OzbnxxsYWl 2NNw== X-Gm-Message-State: APjAAAXsO08f4iuQaAyBOakIkveWDvNTU6vJA6bubhSRbpDjnfAUHUc/ Edh4Qq5e6w+5k2JAGDW1aSMDYqq895Vlbw== X-Received: by 2002:a7b:cb0f:: with SMTP id u15mr717576wmj.173.1567525011888; Tue, 03 Sep 2019 08:36:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:26 +0100 Message-Id: <20190903153633.6651-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::329 Subject: [Qemu-devel] [PULL 14/21] hw/dma/xilinx_axi: Use object_initialize_child for correct ref. counting X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé As explained in commit aff39be0ed97: Both functions, object_initialize() and object_property_add_child() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. Otherwise the child object will not be properly cleaned up when the parent gets destroyed. Thus let's use now object_initialize_child() instead to get the reference counting here right. Reviewed-by: Alistair Francis Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Message-id: 20190823143249.8096-6-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/dma/xilinx_axidma.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) -- 2.20.1 diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index d176df6d449..a254275b64e 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -566,14 +566,14 @@ static void xilinx_axidma_init(Object *obj) XilinxAXIDMA *s = XILINX_AXI_DMA(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev), - TYPE_XILINX_AXI_DMA_DATA_STREAM); - object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev), - TYPE_XILINX_AXI_DMA_CONTROL_STREAM); - object_property_add_child(OBJECT(s), "axistream-connected-target", - (Object *)&s->rx_data_dev, &error_abort); - object_property_add_child(OBJECT(s), "axistream-control-connected-target", - (Object *)&s->rx_control_dev, &error_abort); + object_initialize_child(OBJECT(s), "axistream-connected-target", + &s->rx_data_dev, sizeof(s->rx_data_dev), + TYPE_XILINX_AXI_DMA_DATA_STREAM, &error_abort, + NULL); + object_initialize_child(OBJECT(s), "axistream-control-connected-target", + &s->rx_control_dev, sizeof(s->rx_control_dev), + TYPE_XILINX_AXI_DMA_CONTROL_STREAM, &error_abort, + NULL); sysbus_init_irq(sbd, &s->streams[0].irq); sysbus_init_irq(sbd, &s->streams[1].irq); From patchwork Tue Sep 3 15:36:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 172818 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp27693ily; Tue, 3 Sep 2019 08:48:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqxmdJq+Lqz/r4uE3h63sk5t+rxp+c0LxF7PjDHkEHW2GzTZhPOWD4Bm2tMuOgdEdeMRmjCn X-Received: by 2002:ac8:75c1:: with SMTP id z1mr10319941qtq.301.1567525709240; Tue, 03 Sep 2019 08:48:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567525709; cv=none; d=google.com; s=arc-20160816; b=IfVZnI3247ynXhZx4989/CyonVkXbonTb3Ij9trhvb4ryHrg0pp8nqKtbjoZj5nJpM QiihxI5Zl4iNNLK+rYIiAqyvMFGF8/jGL/f9dgefE8IL1WhiuefbJ/584xYyMRdXjXiz PNGfHqPXhm+9/zldK15Dv0ifoMw/szT4OafMdPGxVilyDZ43WiyDOq0lYTOoNeVKHmpY XNqxCY5IWSjo3nTYr4aogK2TghawJo165h2BUa+FZ3oMNmx9VmMUZNWXHatiDRz8cA05 nDCoYA+zlQS7e8G8xNRFNotsG3LLuwl7xKX9fY2Kk55pAd0DizDjfTjyOArFAUJjL9ep N2fQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=8/T9mmX0W7AG1ACKL4IcYUCZwX8sRH9ZWIp1nKl2B4A=; b=Kdg5qSxlDv2GxtBM4Ef/EWApA7f3etWoAwzA4d79r0G4oFjbkuvBSrCWj422XqIPIm LwPeUMlVRS2YYjnJIm8gUmOAsyOKYSDrL9n79v4446L4JjkZOny1AItEAN90n6dYCg6F XY3uaaKt/f3SYNbXu/s/6tTBBvEqP2ZHGNEs0GzietoH7/CNnHQrVKtZXySknQqdO7Pr fCNIHg7QCjG9nEm2j1H4cPW7/rGrDhO3hvYbY1lM4n3+HxD9d2Pdr3LBmkHogHvEkfZ1 1JhCnwVskvZ8sCf0n+vrTvTbZXpHOnJMaIBEGglhpMMBJCKda7IgWqyF+YAkwvmyRKvv sAEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AAuRoDL5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:27 +0100 Message-Id: <20190903153633.6651-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e Subject: [Qemu-devel] [PULL 15/21] hw/net/xilinx_axi: Use object_initialize_child for correct ref. counting X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé As explained in commit aff39be0ed97: Both functions, object_initialize() and object_property_add_child() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. Otherwise the child object will not be properly cleaned up when the parent gets destroyed. Thus let's use now object_initialize_child() instead to get the reference counting here right. Reviewed-by: Alistair Francis Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Message-id: 20190823143249.8096-7-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/net/xilinx_axienet.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) -- 2.20.1 diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index d8716a1f737..2c8c065401a 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -994,15 +994,14 @@ static void xilinx_enet_init(Object *obj) XilinxAXIEnet *s = XILINX_AXI_ENET(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev), - TYPE_XILINX_AXI_ENET_DATA_STREAM); - object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev), - TYPE_XILINX_AXI_ENET_CONTROL_STREAM); - object_property_add_child(OBJECT(s), "axistream-connected-target", - (Object *)&s->rx_data_dev, &error_abort); - object_property_add_child(OBJECT(s), "axistream-control-connected-target", - (Object *)&s->rx_control_dev, &error_abort); - + object_initialize_child(OBJECT(s), "axistream-connected-target", + &s->rx_data_dev, sizeof(s->rx_data_dev), + TYPE_XILINX_AXI_ENET_DATA_STREAM, &error_abort, + NULL); + object_initialize_child(OBJECT(s), "axistream-control-connected-target", + &s->rx_control_dev, sizeof(s->rx_control_dev), + TYPE_XILINX_AXI_ENET_CONTROL_STREAM, &error_abort, + NULL); sysbus_init_irq(sbd, &s->irq); memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000); From patchwork Tue Sep 3 15:36:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 172822 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp31443ily; Tue, 3 Sep 2019 08:51:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqwhFXxh6ZQ+cFCNCqBlTDU3Z32VrOmz1VzGSD5qg9twB6x/NAcmlIBY2FqbkJVnNzvFlgve X-Received: by 2002:a50:f5f2:: with SMTP id x47mr8493719edm.203.1567525906166; Tue, 03 Sep 2019 08:51:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567525906; cv=none; d=google.com; s=arc-20160816; b=zVB1z0+ABED+1ps9I+Rs3W/oYCbuDy/Jwh/NV+jD0tPJWNv1tFHfHLpIoVeUR1tDi3 Iwta7wgwugLFmQsAPY+pm3TOxsrbfoacV33jchVMC9FFFUc4l5wdvocdSFyRtIEB3IwF MurhzpLYfEorfdG5xYycLFbA0k3NWM3evBccwsHzvwbznPGqPz9/u/day57yNL4FbEKj D2wY4zvVeGlsYYz+FAesPYKjICFYBEXQQ2oEigTh/H1rhcXBooLWrSI8750L4ZDe3bQ1 p2RJMHW+s3yNKd7ffOlYT/5WNH5egC0/FL5gliwDQGUorPtGXHJjhyfA2fC8gmkL5OOZ UkeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=zfQZN+w0EL38uUZUufAKEIUIh1fjw2w5B/j+/inz4Vo=; b=BwIm2N+cfPoOPCI7/IwaDMosidzsChVEhL/pZK+9mdbzq9z+rVI8YDZP1Zr6YZXiav huBT1QZ1Mlr5JGXp2zjbr7pHd4l4ilvnbMsT9xy5fOxFKPqC2r/IUW61UsFX+FcvOODs FF+biBEpuRM8R2PyMQEneYQx2JrD1YborzbP5o7eAaF0BZkorbtCs+c6mvQZHQfLpE15 56OlMjq9bKe3aqoLdQ25mF/y10aBV3xQcxvv0YQhpLTfSsjkyryCGXlNsnTndyRotuA/ nisaV2/RL7K+KJQV9lq9jeS3XPxlYOashdQ1zoF7QDaR6si2TTHG4qjohO3ojh4E7t6Z Er4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Qun0RvSY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:28 +0100 Message-Id: <20190903153633.6651-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32d Subject: [Qemu-devel] [PULL 16/21] includes: remove stale [smp|max]_cpus externs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée Commit a5e0b3311 removed these in favour of querying machine properties. Remove the extern declarations as well. Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20190828165307.18321-6-alex.bennee@linaro.org Cc: Like Xu Message-Id: <20190711130546.18578-1-alex.bennee@linaro.org> Signed-off-by: Peter Maydell --- include/sysemu/sysemu.h | 2 -- 1 file changed, 2 deletions(-) -- 2.20.1 diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h index d2c38f611a3..44f18eb7394 100644 --- a/include/sysemu/sysemu.h +++ b/include/sysemu/sysemu.h @@ -42,8 +42,6 @@ extern const char *keyboard_layout; extern int win2k_install_hack; extern int alt_grab; extern int ctrl_grab; -extern int smp_cpus; -extern unsigned int max_cpus; extern int cursor_hide; extern int graphic_rotate; extern int no_quit; From patchwork Tue Sep 3 15:36:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 172824 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp33398ily; Tue, 3 Sep 2019 08:53:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqx3PiokRBQJZM/XSFsqR/tbEZWPSo9bL/Cfkzz5e7zr+vKwlXMvXoSKe9+LgXGo5Y3Bb7Pe X-Received: by 2002:a37:5f87:: with SMTP id t129mr35164163qkb.183.1567526020558; Tue, 03 Sep 2019 08:53:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567526020; cv=none; d=google.com; s=arc-20160816; b=phB+rBQWevs7fltb9gL7dIE2eec3b87iJW/l0XylqGarmJzQgP2Ozz1pfplXjdAl3K xvcrqxIuV3+JNW+TLHFMWcOlqqy+JaM/EX14XdFRlL3T+HlzbVD6Fg4aIiM6+TWIJvnc 0vPtiCqNxBsQyCtSM90hp1W4KukmyAwCfTsgP9P3WpAXIPZANloiPeO9z2mr1HQ9XYl0 ELo0NTNfHldSIhXpFgmS96GZ25xqIUj6wGeYRbdRl9BwwjWTMcoOzubBvlHMUJKCRdvn zjkdGpPpN8Y9uptRqej/YVZfnxRddQruv+N8qW3kYcf5ZDzroR4LTGMskkzvkeZWpagK g95g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=nR0JGIs4B0XqG/9nvKTr4WHZcNIZDzXugHm2rJffA5M=; b=puTqvminVQMO6n2lvVLPShKzsW1R6kwQYUx/SVBrk4Wk3lCH/SYfzjwhmhAuTNRRjM prBDaU/jrox4EHZiRoArGj8iFPZ5L6sEf6g+3E1UCUnq2f4Zyd+aXwlKcRRpjccuZpLz 1YNT2QRBLjEX+rN1rcQ4FCEmwGVs9xt9O9XAPYVXpNvTeigMY5UHhYS7BC/dw78XHeyU UyDsjIBHka3u1XUsOgFRSi297CSapzzBKSbf1EQhi76b+VirMPX0Rl2HVFU0v9k1p9Y2 mqM46ctIh4LFYvhC0giHHA7fxavz6voMRUuQsfvbAe6cSUCtALGvMSlZYMO8hHREzHiS MUdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BibhaDgh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:29 +0100 Message-Id: <20190903153633.6651-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::432 Subject: [Qemu-devel] [PULL 17/21] tcg/README: fix typo s/afterwise/afterwards/ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Afterwise is "wise after the fact", as in "hindsight". Here we meant "afterwards" (as in "subsequently"). Fix it. Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190828165307.18321-7-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- tcg/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/tcg/README b/tcg/README index 21fcdf737ff..ef9be5ba90e 100644 --- a/tcg/README +++ b/tcg/README @@ -101,7 +101,7 @@ This can be overridden using the following function modifiers: canonical locations before calling the helper. - TCG_CALL_NO_WRITE_GLOBALS means that the helper does not modify any globals. They will only be saved to their canonical location before calling helpers, - but they won't be reloaded afterwise. + but they won't be reloaded afterwards. - TCG_CALL_NO_SIDE_EFFECTS means that the call to the function is removed if the return value is not used. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:30 +0100 Message-Id: <20190903153633.6651-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::330 Subject: [Qemu-devel] [PULL 18/21] atomic_template: fix indentation in GEN_ATOMIC_HELPER X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190828165307.18321-8-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- accel/tcg/atomic_template.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index 5aaf1862539..df9c8388178 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -284,7 +284,7 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, #define GEN_ATOMIC_HELPER(X) \ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ - ABI_TYPE val EXTRA_ARGS) \ + ABI_TYPE val EXTRA_ARGS) \ { \ ATOMIC_MMU_DECLS; \ DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \ From patchwork Tue Sep 3 15:36:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 172826 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp35140ily; Tue, 3 Sep 2019 08:55:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqwEopwf/2HzOLEZqJva1pVsbJdpVcWdqcV6yZEQJSYaCtge9HjzULz99E96RDIz1JY6NFbK X-Received: by 2002:ae9:eb46:: with SMTP id b67mr21577888qkg.401.1567526126902; Tue, 03 Sep 2019 08:55:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567526126; cv=none; d=google.com; s=arc-20160816; b=oRA9lvC9h7apKhK/VFVhQyXNRmmvQIyywAOESsPTMEkgKsokvbROmPZBhj/XEUh69K k6BqEloJO2UZ/J9AyKDOwKbgFRIum2byZ6hBmvubxCr5Fax0ft1Zx/ZoBl2u6kfPazvR Iqz3wJwWklDLZw6DCosdBTfTbxydskIt3v7o0WM9D8vyegIe3DAG88qtWt/nBKCjaGv8 H24kRcmP8oEGCYsD3Yajjg8X1C7+uuqo4Hw4y8CjhNFCG6B34kEXtfIzu7t7Z437L0yC p99hfNX8cAMqnnaVZwvbE6nZUcp74gnA2+wYVEZjM27o28CkMFjPcEZ4qaNqqtgDyv1+ ZqAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=kAtyZQk6NvWQZv/UvMqc94DjvSUcAjVyZvv+e5jcwsg=; b=deBPQ1vUwm8mPgyBqDqTvylg63Z7QqmuRrpkbN7nsoQhdkbN2BE0Pe0F9AMFdrSUzt uivGlNU5AZKIB8XUMLlBV3ENc5K9N/nbo7E53OLkn3wgyhrpQX71g4U8hfcElcdXT1wo CTXaE5EWo7BrNtg0KDS3CKTjCu2dC1payihKaekioZuc65OGcrbm03Vo3cSVEsdLvhnB UcIs7PcsY3YohOXMnK0C5W2YxPIJNVFo+lgTZG64J51CLGOLTPuM1CJfuwNybLpnnwaQ 0KgjLr8Vrp6bJMuzZpE/aYVqdivGfhnQTqg+07ehNIuqyXrMT5gd+Om6vGuCy5uh2d/+ TbiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ufVRrbvm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::32d Subject: [Qemu-devel] [PULL 19/21] include/exec/cpu-defs.h: fix typo X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190828165307.18321-10-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu-defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 189709b6deb..be946ba1ce5 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -231,7 +231,7 @@ typedef struct CPUTLB { } CPUTLB; #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ /* - * This structure must be placed in ArchCPU immedately + * This structure must be placed in ArchCPU immediately * before CPUArchState, as a field named "neg". */ typedef struct CPUNegativeOffsetState { From patchwork Tue Sep 3 15:36:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 172825 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp33959ily; Tue, 3 Sep 2019 08:54:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqz64O/qycdHokFpA+dpu61yQiTdYaMLGHI4z81Wx8ZDQaz1XETwoYLqI2rQv/AHgksKS14V X-Received: by 2002:ae9:ea0d:: with SMTP id f13mr33424271qkg.4.1567526056940; Tue, 03 Sep 2019 08:54:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567526056; cv=none; d=google.com; s=arc-20160816; b=DicBaldYebQJjlV8+lZ3H27AoaSq5ZiKAs0WuUXZfC7iqpkMckaGoD2mBrwlpInrst qjZx2rS8NcxZYuRtwxe7McmD36EMjSCrdNrdPoOfqOUW6kbgkNIjZF9dRAH2P+biqpFh gOQcqx/VXAMHsD7WZBG7V9ipn0ijBset8HykhZue+kyS2oIwLsykj6T/U748jI8CQudS 4dU1gcTrqlSkPHekwS/aL6+HvCPdI+UPOnRj8ImJHYtGhsMkJ9b++GMKYNdNbTZ5hwW8 bWJ/WeWylgV5VKE+liGQKADNTQ3Q+xzaVA+27rlj7M3MQn68LW/0eWdAClC1mjk+VB7l ML7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=PQwumxLD0naoGLveJArJ+0uz+trgPMLG7ByeUUTiw3c=; b=Gx1whOmApaMUCc6GJEqELLdOz9AJYZKXQHk/QTg3KyJL2vVQnVtCD4LrZMCX3TqlR0 Avm/u4RtGRqueLIDj9DyPAM4oHnoUvDk0+D2cWqy5ZNYV9jZcgYCAzAi8Yxsbh1kaQuN NfDF5gYyBlBItKBWoNSCDEmybCjd+UVCTaYD0S3QLqOcQ15L6qJ6+RbRUUN0XqVs46jw uj4NyWg8iqEz4McC091zNPOtNTsG2BkWlPWMOliybdUZE1wt5cidJ/LsWNyghPqdEryk jUHaf936r+WTrFBADybVi9B6tnDYY7iIjB9qAEudh2kBqVqDxeq2Dn0qZjOPDO2zg3tm igIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hqVt7v0A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:32 +0100 Message-Id: <20190903153633.6651-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PULL 20/21] target/arm: Free TCG temps in trans_VMOV_64_sp() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The function neon_store_reg32() doesn't free the TCG temp that it is passed, so the caller must do that. We got this right in most places but forgot to free the TCG temps in trans_VMOV_64_sp(). Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190827121931.26836-1-peter.maydell@linaro.org --- target/arm/translate-vfp.inc.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.20.1 diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 3e8ea80493b..9ae980bef63 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -880,8 +880,10 @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a) /* gpreg to fpreg */ tmp = load_reg(s, a->rt); neon_store_reg32(tmp, a->vm); + tcg_temp_free_i32(tmp); tmp = load_reg(s, a->rt2); neon_store_reg32(tmp, a->vm + 1); + tcg_temp_free_i32(tmp); } return true; From patchwork Tue Sep 3 15:36:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 172828 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp39431ily; Tue, 3 Sep 2019 08:59:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqyfn8Q+jb0N8J0zYlt0nHjvcJ9E1PdLHdbbwnds3I0HQAfiSYoes2ZiNAheJtDrMLzzQRLr X-Received: by 2002:a37:4f46:: with SMTP id d67mr36085945qkb.367.1567526381099; Tue, 03 Sep 2019 08:59:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567526381; cv=none; d=google.com; s=arc-20160816; b=BhLD/IN+GmOZAT90qQnoSaA/wUY55DgLOsSIsqElIt8H4Yj9gt1UGVoDj4PUwM36dl +VDOGSitF6XQjR8AWJr1ww/2kp2SFYmGex6U5QseX2HQvqjvxP3CAtTmpZG6eXDjuKGM leTTFcdsQLckhyAKEBdn/Jb7WvIwAi7dnIRACFa/7X+t4mnMnsgu3BcBdG8WnG7bVPp0 S9H3mY2TPvuiAy6Tt9BEBCNkCcThGjd8coW3NJNV/52O69W4KCDBoWum9idTZ/QlOmM8 LDhUzsImye/t8X7cT0fSw4V2YqZQ/wgb88Ml2wiB8ifJXcNhbQimhm/wkVlLLYKuEGX/ 0klQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ajJo8M0JKSN4/WIzHMm40PvDhk2VCRR0BAjSpMU/81k=; b=PbTJ8KUBEbdX+sDFZ0GcyX4+xXiRXlpB5foMUDK6jCcGF1tn+NCuLC9QycUz5UYRnP a6Sao9hGqV1SVa+qZyUImSHP+Hi11o0Lcw0VePEfGDKDDE+PcfJFnkdbNe2oDMZzrANU PJ7F2HQtB06JJ+mqxo1B6Lz2ED1ZfUiuABk1NgthacWpF2d8PZTtZA/KjohzLyFx0l+w wHmcifaR+2RSEefs3BRffRrii2rXPJpOzF9Fy/jNZKazDXdmx09b7p37XFqwjMabZLCe +9HwlogxDIqjLNB3duZIpUMqS5Nw7jCWS06N5sN0phi0hk2q9SSFZlndL/aW9TqQdiNE BgDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=P4QFAkZQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a18sm24435188wrt.18.2019.09.03.08.36.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 08:36:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 16:36:33 +0100 Message-Id: <20190903153633.6651-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190903153633.6651-1-peter.maydell@linaro.org> References: <20190903153633.6651-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PULL 21/21] target/arm: Don't abort on M-profile exception return in linux-user mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" An attempt to do an exception-return (branch to one of the magic addresses) in linux-user mode for M-profile should behave like a normal branch, because linux-user mode is always going to be in 'handler' mode. This used to work, but we broke it when we added support for the M-profile security extension in commit d02a8698d7ae2bfed. In that commit we allowed even handler-mode calls to magic return values to be checked for and dealt with by causing an EXCP_EXCEPTION_EXIT exception to be taken, because this is needed for the FNC_RETURN return-from-non-secure-function-call handling. For system mode we added a check in do_v7m_exception_exit() to make any spurious calls from Handler mode behave correctly, but forgot that linux-user mode would also be affected. How an attempted return-from-non-secure-function-call in linux-user mode should be handled is not clear -- on real hardware it would result in return to secure code (not to the Linux kernel) which could then handle the error in any way it chose. For QEMU we take the simple approach of treating this erroneous return the same way it would be handled on a CPU without the security extensions -- treat it as a normal branch. The upshot of all this is that for linux-user mode we should never do any of the bx_excret magic, so the code change is simple. This ought to be a weird corner case that only affects broken guest code (because Linux user processes should never be attempting to do exception returns or NS function returns), except that the code that assigns addresses in RAM for the process and stack in our linux-user code does not attempt to avoid this magic address range, so legitimate code attempting to return to a trampoline routine on the stack can fall into this case. This change fixes those programs, but we should also look at restricting the range of memory we use for M-profile linux-user guests to the area that would be real RAM in hardware. Cc: qemu-stable@nongnu.org Reported-by: Christophe Lyon Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20190822131534.16602-1-peter.maydell@linaro.org Fixes: https://bugs.launchpad.net/qemu/+bug/1840922 Signed-off-by: Peter Maydell --- target/arm/translate.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index cfebd35d268..615859e23c5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -915,10 +915,27 @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var) store_cpu_field(var, thumb); } -/* Set PC and Thumb state from var. var is marked as dead. +/* + * Set PC and Thumb state from var. var is marked as dead. * For M-profile CPUs, include logic to detect exception-return * branches and handle them. This is needed for Thumb POP/LDM to PC, LDR to PC, * and BX reg, and no others, and happens only for code in Handler mode. + * The Security Extension also requires us to check for the FNC_RETURN + * which signals a function return from non-secure state; this can happen + * in both Handler and Thread mode. + * To avoid having to do multiple comparisons in inline generated code, + * we make the check we do here loose, so it will match for EXC_RETURN + * in Thread mode. For system emulation do_v7m_exception_exit() checks + * for these spurious cases and returns without doing anything (giving + * the same behaviour as for a branch to a non-magic address). + * + * In linux-user mode it is unclear what the right behaviour for an + * attempted FNC_RETURN should be, because in real hardware this will go + * directly to Secure code (ie not the Linux kernel) which will then treat + * the error in any way it chooses. For QEMU we opt to make the FNC_RETURN + * attempt behave the way it would on a CPU without the security extension, + * which is to say "like a normal branch". That means we can simply treat + * all branches as normal with no magic address behaviour. */ static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var) { @@ -926,10 +943,12 @@ static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var) * s->base.is_jmp that we need to do the rest of the work later. */ gen_bx(s, var); +#ifndef CONFIG_USER_ONLY if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY) || (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M))) { s->base.is_jmp = DISAS_BX_EXCRET; } +#endif } static inline void gen_bx_excret_final_code(DisasContext *s)