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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:29:51 -0700 Message-Id: <20190904193059.26202-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v4 01/69] target/arm: Use store_reg_from_load in thumb2 code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function already includes the test for an interworking write to PC from a load. Change the T32 LDM implementation to match the A32 LDM implementation. For LDM, the reordering of the tests does not change valid behaviour because the only case that differs is has rn == 15, which is UNPREDICTABLE. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index b0d32ff8c9..a39f792463 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9742,13 +9742,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) /* Load. */ tmp = tcg_temp_new_i32(); gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i == 15) { - gen_bx_excret(s, tmp); - } else if (i == rn) { + if (i == rn) { loaded_var = tmp; loaded_base = 1; } else { - store_reg(s, i, tmp); + store_reg_from_load(s, i, tmp); } } else { /* Store. */ @@ -10889,11 +10887,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(addr); goto illegal_op; } - if (rs == 15) { - gen_bx_excret(s, tmp); - } else { - store_reg(s, rs, tmp); - } + store_reg_from_load(s, rs, tmp); } else { /* Store. */ tmp = load_reg(s, rs); From patchwork Wed Sep 4 19:29:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172963 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp351180ilq; Wed, 4 Sep 2019 12:32:14 -0700 (PDT) X-Google-Smtp-Source: APXvYqzpG4alZsUyyXrVwG0uu+h6J95sCzfhiMv+I2XWHjb6G1XXuCil2IINdnaNJ979gHqmhFL2 X-Received: by 2002:ac8:549:: with SMTP id c9mr40780004qth.223.1567625534437; Wed, 04 Sep 2019 12:32:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567625534; cv=none; d=google.com; s=arc-20160816; b=l5nVwgOQAbNzLprj6bDZSeW/vtzrQiCo1rd2zqgTcJj74mZDFXdcLrmDgIGTMcz40I ZO0VC8hsalmhtgGHd++1eHEPN0dvwbB9nxZIrAWaYEoYGZgfMs8N+BHV+/lUqjTbIGJu 0+BZJG1Ob/WR6rHiQOW0OBZ/Iuoy/kTncGWAP1OF66FNcVB9scfYhUKHQZqsJlbIK+a5 mPOtmzxli+NoiLM3wEy8C03nYan/8c2nbWRAzfQFnFAHNNKfr30YUGHISzI3zupoNMX4 zHCPEz26ypjaUTPD16z51ohAw1Ei7+rMexCHFBrbxG/UHkJQV+UHOTS8vSL8YlxDG9Pl sJ0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=NBzAHUlZzheDevf0bsXniXn3jInVmGNWWYOMzwYImOs=; b=FKh6IH8eEt0BZpeDijsgxvXCfwYNGtAXvIcQLDixvF8Lo06IJ8w9Xl8eJSHX9kqv6Y WY6HwR8POuqJz/hP7x2VG8HPp6ZnhExxsI7f1qDHa4MGSmZibbUZ/EN9TI1pOKCKl8fP 2Xeqx5Kc5pTVAkqb1kRsx+OWnzCjheojafS9UCLfr5KrX9LJEXjuJnnrpvaunDrnfjsy CLfXnSmOeVmrzx+ebqHq3AEMqKqXtQGO4WWklUAJKNU3B4Jnwxogb+28Fn6bDRCAbOhg 5ijR+6B+35UFozWZncg3SQTXC1qn1hO5v5gBoCTxAYd3cHqWU1CqIXypJ2ld4T86VvBj xN9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PKPWhUOf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:29:52 -0700 Message-Id: <20190904193059.26202-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62f Subject: [Qemu-devel] [PATCH v4 02/69] target/arm: Add stubs for aa32 decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add the infrastructure that will become the new decoder. No instructions adjusted so far. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/translate.c | 31 ++++++++++++++++++++++++++++++- target/arm/Makefile.objs | 18 ++++++++++++++++++ target/arm/a32-uncond.decode | 23 +++++++++++++++++++++++ target/arm/a32.decode | 23 +++++++++++++++++++++++ target/arm/t32.decode | 20 ++++++++++++++++++++ 5 files changed, 114 insertions(+), 1 deletion(-) create mode 100644 target/arm/a32-uncond.decode create mode 100644 target/arm/a32.decode create mode 100644 target/arm/t32.decode -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index a39f792463..07674d223c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7683,6 +7683,18 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond) arm_gen_test_cc(cond ^ 1, s->condlabel); } +/* + * Include the generated decoders. + */ + +#include "decode-a32.inc.c" +#include "decode-a32-uncond.inc.c" +#include "decode-t32.inc.c" + +/* + * Legacy decoder. + */ + static void disas_arm_insn(DisasContext *s, unsigned int insn) { unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh; @@ -7701,7 +7713,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) return; } cond = insn >> 28; - if (cond == 0xf){ + + if (cond == 0xf) { /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we * choose to UNDEF. In ARMv5 and above the space is used * for miscellaneous unconditional instructions. @@ -7709,6 +7722,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) ARCH(5); /* Unconditional instructions. */ + if (disas_a32_uncond(s, insn)) { + return; + } + /* fall back to legacy decoder */ + if (((insn >> 25) & 7) == 1) { /* NEON Data processing. */ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { @@ -7923,6 +7941,12 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) next instruction */ arm_skip_unless(s, cond); } + + if (disas_a32(s, insn)) { + return; + } + /* fall back to legacy decoder */ + if ((insn & 0x0f900000) == 0x03000000) { if ((insn & (1 << 21)) == 0) { ARCH(6T2); @@ -9414,6 +9438,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) ARCH(6T2); } + if (disas_t32(s, insn)) { + return; + } + /* fall back to legacy decoder */ + rn = (insn >> 16) & 0xf; rs = (insn >> 12) & 0xf; rd = (insn >> 8) & 0xf; diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 5cafc1eb6c..7806b4dac0 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -28,9 +28,27 @@ target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/arm/vfp-uncond.decode $(D $(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\ "GEN", $(TARGET_DIR)$@) +target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/decode-a32-uncond.inc.c: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + target/arm/translate-sve.o: target/arm/decode-sve.inc.c target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c +target/arm/translate.o: target/arm/decode-a32.inc.c +target/arm/translate.o: target/arm/decode-a32-uncond.inc.c +target/arm/translate.o: target/arm/decode-t32.inc.c obj-y += tlb_helper.o debug_helper.o obj-y += translate.o op_helper.o diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode new file mode 100644 index 0000000000..8dee26d3b6 --- /dev/null +++ b/target/arm/a32-uncond.decode @@ -0,0 +1,23 @@ +# A32 unconditional instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# +# All insns that have 0xf in insn[31:28] are decoded here. +# All of those that have a COND field in insn[31:28] are in a32.decode +# diff --git a/target/arm/a32.decode b/target/arm/a32.decode new file mode 100644 index 0000000000..a3e6e8c1c2 --- /dev/null +++ b/target/arm/a32.decode @@ -0,0 +1,23 @@ +# A32 conditional instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# +# All of the insn that have a COND field in insn[31:28] are here. +# All insns that have 0xf in insn[31:28] are in a32-uncond.decode. +# diff --git a/target/arm/t32.decode b/target/arm/t32.decode new file mode 100644 index 0000000000..ac01fb6958 --- /dev/null +++ b/target/arm/t32.decode @@ -0,0 +1,20 @@ +# Thumb2 instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# From patchwork Wed Sep 4 19:29:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172965 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp353073ilq; Wed, 4 Sep 2019 12:34:10 -0700 (PDT) X-Google-Smtp-Source: APXvYqw6Gr/PaapYo2J/fnRO+2hK7gQ/3Q26ld6XZNY2PTdCipdkr4gDXC+NLPmg3YxeY3RSHPwJ X-Received: by 2002:a17:906:3406:: with SMTP id c6mr11613701ejb.89.1567625650031; Wed, 04 Sep 2019 12:34:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567625650; cv=none; d=google.com; s=arc-20160816; b=qaCH43mXR7+s9P/e73NdIEAO7Th3mmiN6Bt0cybNdzRuxyhhx414FC3nA6X4ChveaC 3o7I067PUCnmThKtxOegIVuhs0QQBItSgLOx2yjkEja2y8oWc58G9/8dWJh0iQDNS0FA 77RcoXoONVop0PoNI3QJCo4yNFwF23td32TF2kuU3Zr8XqcqHHvPeAa1WjnYo2jJ572g OpWeQ9Gkd+RaX9UFccqFUsyJULnKVACe73QQcKbHPyzZkwGpHOCBPblOw7mUcJDC81hO AVQ67mmmEK81HQdwlI7cMKkxlCYfwtynrYxjt7PMjV9pAJI6+gYRN3jBkWe+nfmWv22n Kbzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=IYs4/Iy+m5flK8PpSYLGsEq72fMMXSyXbIuQC71eMFA=; b=KRakr5GEXazETo15eAYmGQSnPpB7jrjPjax1pu94S8ktl75mAJLdDTHq7hWB0gJYTT WSRHw6JUZW9ruDlDZ8EZT8xHDwEmaSbvmEZ3I7S1QRSacgJzon4Sm9sO4Cqyg4dD4c3Q oDfaWYRQPh/McvH4O4lUM9UWfjItBreK3Mdt6Wpe08jz6cEOmb9lR1npVJlCLubRmEn2 0Co7wRsgYsa6AeO0R/V/enDVfe8HR2xtIcckGSVL2LFfGsTXkYWc4Xp0E7s070pSLzKz PjnA7PCFzzODb+IUZRjAFIS+VX3EwCcYvT0K3a5JuTHGRxaOvqO3kd5meKwqC1OBZQP5 b3CA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MJZSDnSe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:29:53 -0700 Message-Id: <20190904193059.26202-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v4 03/69] target/arm: Convert Data Processing (register) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the register shifted by immediate form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the reg-shifted-reg and immediate forms. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use unallocated_encoding for user/hyp check. --- target/arm/translate.c | 236 ++++++++++++++++++++++++++++++++++------- target/arm/a32.decode | 28 +++++ target/arm/t32.decode | 43 ++++++++ 3 files changed, 271 insertions(+), 36 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 07674d223c..cb97f5b22d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7691,6 +7691,204 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond) #include "decode-a32-uncond.inc.c" #include "decode-t32.inc.c" +/* Helpers to swap operands for reverse-subtract. */ +static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_sub_i32(dst, b, a); +} + +static void gen_rsb_CC(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) +{ + gen_sub_CC(dst, b, a); +} + +static void gen_rsc(TCGv_i32 dest, TCGv_i32 a, TCGv_i32 b) +{ + gen_sub_carry(dest, b, a); +} + +static void gen_rsc_CC(TCGv_i32 dest, TCGv_i32 a, TCGv_i32 b) +{ + gen_sbc_CC(dest, b, a); +} + +/* + * Helpers for the data processing routines. + * + * After the computation store the results back. + * This may be suppressed altogether (STREG_NONE), require a runtime + * check against the stack limits (STREG_SP_CHECK), or generate an + * exception return. Oh, or store into a register. + * + * Always return true, indicating success for a trans_* function. + */ +typedef enum { + STREG_NONE, + STREG_NORMAL, + STREG_SP_CHECK, + STREG_EXC_RET, +} StoreRegKind; + +static bool store_reg_kind(DisasContext *s, int rd, + TCGv_i32 val, StoreRegKind kind) +{ + switch (kind) { + case STREG_NONE: + tcg_temp_free_i32(val); + return true; + case STREG_NORMAL: + /* See ALUWritePC: Interworking only from a32 mode. */ + if (s->thumb) { + store_reg(s, rd, val); + } else { + store_reg_bx(s, rd, val); + } + return true; + case STREG_SP_CHECK: + store_sp_checked(s, val); + return true; + case STREG_EXC_RET: + gen_exception_return(s, val); + return true; + } + g_assert_not_reached(); +} + +/* + * Data Processing (register) + * + * Operate, with set flags, one register source, + * one immediate shifted register source, and a destination. + */ +static bool op_s_rrr_shi(DisasContext *s, arg_s_rrr_shi *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + + tmp2 = load_reg(s, a->rm); + gen_arm_shift_im(tmp2, a->shty, a->shim, logic_cc); + tmp1 = load_reg(s, a->rn); + + gen(tmp1, tmp1, tmp2); + tcg_temp_free_i32(tmp2); + + if (logic_cc) { + gen_logic_CC(tmp1); + } + return store_reg_kind(s, a->rd, tmp1, kind); +} + +static bool op_s_rxr_shi(DisasContext *s, arg_s_rrr_shi *a, + void (*gen)(TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp; + + tmp = load_reg(s, a->rm); + gen_arm_shift_im(tmp, a->shty, a->shim, logic_cc); + + gen(tmp, tmp); + if (logic_cc) { + gen_logic_CC(tmp); + } + return store_reg_kind(s, a->rd, tmp, kind); +} + +#define DO_ANY3(NAME, OP, L, K) \ + static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \ + { StoreRegKind k = (K); return op_s_rrr_shi(s, a, OP, L, k); } + +#define DO_ANY2(NAME, OP, L, K) \ + static bool trans_##NAME##_rxri(DisasContext *s, arg_s_rrr_shi *a) \ + { StoreRegKind k = (K); return op_s_rxr_shi(s, a, OP, L, k); } + +#define DO_CMP2(NAME, OP, L) \ + static bool trans_##NAME##_xrri(DisasContext *s, arg_s_rrr_shi *a) \ + { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } + +DO_ANY3(AND, tcg_gen_and_i32, a->s, STREG_NORMAL) +DO_ANY3(EOR, tcg_gen_xor_i32, a->s, STREG_NORMAL) +DO_ANY3(ORR, tcg_gen_or_i32, a->s, STREG_NORMAL) +DO_ANY3(BIC, tcg_gen_andc_i32, a->s, STREG_NORMAL) + +DO_ANY3(RSB, a->s ? gen_rsb_CC : gen_rsb, false, STREG_NORMAL) +DO_ANY3(ADC, a->s ? gen_adc_CC : gen_add_carry, false, STREG_NORMAL) +DO_ANY3(SBC, a->s ? gen_sbc_CC : gen_sub_carry, false, STREG_NORMAL) +DO_ANY3(RSC, a->s ? gen_rsc_CC : gen_rsc, false, STREG_NORMAL) + +DO_CMP2(TST, tcg_gen_and_i32, true) +DO_CMP2(TEQ, tcg_gen_xor_i32, true) +DO_CMP2(CMN, gen_add_CC, false) +DO_CMP2(CMP, gen_sub_CC, false) + +DO_ANY3(ADD, a->s ? gen_add_CC : tcg_gen_add_i32, false, + a->rd == 13 && a->rn == 13 ? STREG_SP_CHECK : STREG_NORMAL) + +/* + * Note for the computation of StoreRegKind we return out of the + * middle of the functions that are expanded by DO_ANY3, and that + * we modify a->s via that parameter before it is used by OP. + */ +DO_ANY3(SUB, a->s ? gen_sub_CC : tcg_gen_sub_i32, false, + ({ + StoreRegKind ret = STREG_NORMAL; + if (a->rd == 15 && a->s) { + /* + * See ALUExceptionReturn: + * In User mode, UNPREDICTABLE; we choose UNDEF. + * In Hyp mode, UNDEFINED. + */ + if (IS_USER(s) || s->current_el == 2) { + unallocated_encoding(s); + return true; + } + /* There is no writeback of nzcv to PSTATE. */ + a->s = 0; + ret = STREG_EXC_RET; + } else if (a->rd == 13 && a->rn == 13) { + ret = STREG_SP_CHECK; + } + ret; + })) + +DO_ANY2(MOV, tcg_gen_mov_i32, a->s, + ({ + StoreRegKind ret = STREG_NORMAL; + if (a->rd == 15 && a->s) { + /* + * See ALUExceptionReturn: + * In User mode, UNPREDICTABLE; we choose UNDEF. + * In Hyp mode, UNDEFINED. + */ + if (IS_USER(s) || s->current_el == 2) { + unallocated_encoding(s); + return true; + } + /* There is no writeback of nzcv to PSTATE. */ + a->s = 0; + ret = STREG_EXC_RET; + } else if (a->rd == 13) { + ret = STREG_SP_CHECK; + } + ret; + })) + +DO_ANY2(MVN, tcg_gen_not_i32, a->s, STREG_NORMAL) + +/* + * ORN is only available with T32, so there is no register-shifted-register + * form of the insn. Using the DO_ANY3 macro would create an unused function. + */ +static bool trans_ORN_rrri(DisasContext *s, arg_s_rrr_shi *a) +{ + return op_s_rrr_shi(s, a, tcg_gen_orc_i32, a->s, STREG_NORMAL); +} + +#undef DO_ANY3 +#undef DO_ANY2 +#undef DO_CMP2 + /* * Legacy decoder. */ @@ -9305,13 +9503,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn) return true; } -/* Return true if this is a Thumb-2 logical op. */ -static int -thumb2_logic_op(int op) -{ - return (op < 8); -} - /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero then set condition code flags based on the result of the operation. If SHIFTER_OUT is nonzero then set the carry flag for logical operations @@ -9399,8 +9590,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) TCGv_i32 addr; TCGv_i64 tmp64; int op; - int shiftop; - int conds; int logic_cc; /* @@ -9830,33 +10019,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) store_reg(s, rd, tmp); } else { /* Data processing register constant shift. */ - if (rn == 15) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp = load_reg(s, rn); - } - tmp2 = load_reg(s, rm); - - shiftop = (insn >> 4) & 3; - shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); - conds = (insn & (1 << 20)) != 0; - logic_cc = (conds && thumb2_logic_op(op)); - gen_arm_shift_im(tmp2, shiftop, shift, logic_cc); - if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2)) - goto illegal_op; - tcg_temp_free_i32(tmp2); - if (rd == 13 && - ((op == 2 && rn == 15) || - (op == 8 && rn == 13) || - (op == 13 && rn == 13))) { - /* MOV SP, ... or ADD SP, SP, ... or SUB SP, SP, ... */ - store_sp_checked(s, tmp); - } else if (rd != 15) { - store_reg(s, rd, tmp); - } else { - tcg_temp_free_i32(tmp); - } + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } break; case 13: /* Misc data processing. */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index a3e6e8c1c2..b23e83f17c 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -21,3 +21,31 @@ # All of the insn that have a COND field in insn[31:28] are here. # All insns that have 0xf in insn[31:28] are in a32-uncond.decode. # + +&s_rrr_shi s rd rn rm shim shty + +# Data-processing (register) + +@s_rrr_shi ---- ... .... s:1 rn:4 rd:4 shim:5 shty:2 . rm:4 \ + &s_rrr_shi +@s_rxr_shi ---- ... .... s:1 .... rd:4 shim:5 shty:2 . rm:4 \ + &s_rrr_shi rn=0 +@S_xrr_shi ---- ... .... . rn:4 .... shim:5 shty:2 . rm:4 \ + &s_rrr_shi s=1 rd=0 + +AND_rrri .... 000 0000 . .... .... ..... .. 0 .... @s_rrr_shi +EOR_rrri .... 000 0001 . .... .... ..... .. 0 .... @s_rrr_shi +SUB_rrri .... 000 0010 . .... .... ..... .. 0 .... @s_rrr_shi +RSB_rrri .... 000 0011 . .... .... ..... .. 0 .... @s_rrr_shi +ADD_rrri .... 000 0100 . .... .... ..... .. 0 .... @s_rrr_shi +ADC_rrri .... 000 0101 . .... .... ..... .. 0 .... @s_rrr_shi +SBC_rrri .... 000 0110 . .... .... ..... .. 0 .... @s_rrr_shi +RSC_rrri .... 000 0111 . .... .... ..... .. 0 .... @s_rrr_shi +TST_xrri .... 000 1000 1 .... 0000 ..... .. 0 .... @S_xrr_shi +TEQ_xrri .... 000 1001 1 .... 0000 ..... .. 0 .... @S_xrr_shi +CMP_xrri .... 000 1010 1 .... 0000 ..... .. 0 .... @S_xrr_shi +CMN_xrri .... 000 1011 1 .... 0000 ..... .. 0 .... @S_xrr_shi +ORR_rrri .... 000 1100 . .... .... ..... .. 0 .... @s_rrr_shi +MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi +BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi +MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ac01fb6958..7068596b99 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -18,3 +18,46 @@ # # This file is processed by scripts/decodetree.py # + +&s_rrr_shi !extern s rd rn rm shim shty + +# Data-processing (register) + +%imm5_12_6 12:3 6:2 + +@s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \ + &s_rrr_shi shim=%imm5_12_6 +@s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \ + &s_rrr_shi shim=%imm5_12_6 rn=0 +@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \ + &s_rrr_shi shim=%imm5_12_6 s=1 rd=0 + +{ + TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi + AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi +} +BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi +{ + MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi + ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi +} +{ + MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi + ORN_rrri 1110101 0011 . .... 0 ... .... .... .... @s_rrr_shi +} +{ + TEQ_xrri 1110101 0100 1 .... 0 ... 1111 .... .... @S_xrr_shi + EOR_rrri 1110101 0100 . .... 0 ... .... .... .... @s_rrr_shi +} +# PKHBT, PKHTB at opc1 = 0110 +{ + CMN_xrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi + ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi +} +ADC_rrri 1110101 1010 . .... 0 ... .... .... .... @s_rrr_shi +SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi +{ + CMP_xrri 1110101 1101 1 .... 0 ... 1111 .... .... @S_xrr_shi + SUB_rrri 1110101 1101 . .... 0 ... .... .... .... @s_rrr_shi +} +RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi From patchwork Wed Sep 4 19:29:54 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:29:54 -0700 Message-Id: <20190904193059.26202-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 04/69] target/arm: Convert Data Processing (reg-shifted-reg) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the register shifted by register form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the immediate form. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 74 ++++++++++++++++++++++++++++++------------ target/arm/a32.decode | 27 +++++++++++++++ target/arm/t32.decode | 6 ++++ 3 files changed, 87 insertions(+), 20 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index cb97f5b22d..ff78b1bb74 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7795,17 +7795,66 @@ static bool op_s_rxr_shi(DisasContext *s, arg_s_rrr_shi *a, return store_reg_kind(s, a->rd, tmp, kind); } +/* + * Data-processing (register-shifted register) + * + * Operate, with set flags, one register source, + * one register shifted register source, and a destination. + */ +static bool op_s_rrr_shr(DisasContext *s, arg_s_rrr_shr *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + + tmp1 = load_reg(s, a->rs); + tmp2 = load_reg(s, a->rm); + gen_arm_shift_reg(tmp2, a->shty, tmp1, logic_cc); + tmp1 = load_reg(s, a->rn); + + gen(tmp1, tmp1, tmp2); + tcg_temp_free_i32(tmp2); + + if (logic_cc) { + gen_logic_CC(tmp1); + } + return store_reg_kind(s, a->rd, tmp1, kind); +} + +static bool op_s_rxr_shr(DisasContext *s, arg_s_rrr_shr *a, + void (*gen)(TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + + tmp1 = load_reg(s, a->rs); + tmp2 = load_reg(s, a->rm); + gen_arm_shift_reg(tmp2, a->shty, tmp1, logic_cc); + + gen(tmp2, tmp2); + if (logic_cc) { + gen_logic_CC(tmp2); + } + return store_reg_kind(s, a->rd, tmp2, kind); +} + #define DO_ANY3(NAME, OP, L, K) \ static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \ - { StoreRegKind k = (K); return op_s_rrr_shi(s, a, OP, L, k); } + { StoreRegKind k = (K); return op_s_rrr_shi(s, a, OP, L, k); } \ + static bool trans_##NAME##_rrrr(DisasContext *s, arg_s_rrr_shr *a) \ + { StoreRegKind k = (K); return op_s_rrr_shr(s, a, OP, L, k); } #define DO_ANY2(NAME, OP, L, K) \ static bool trans_##NAME##_rxri(DisasContext *s, arg_s_rrr_shi *a) \ - { StoreRegKind k = (K); return op_s_rxr_shi(s, a, OP, L, k); } + { StoreRegKind k = (K); return op_s_rxr_shi(s, a, OP, L, k); } \ + static bool trans_##NAME##_rxrr(DisasContext *s, arg_s_rrr_shr *a) \ + { StoreRegKind k = (K); return op_s_rxr_shr(s, a, OP, L, k); } #define DO_CMP2(NAME, OP, L) \ static bool trans_##NAME##_xrri(DisasContext *s, arg_s_rrr_shi *a) \ - { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } + { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } \ + static bool trans_##NAME##_xrrr(DisasContext *s, arg_s_rrr_shr *a) \ + { return op_s_rrr_shr(s, a, OP, L, STREG_NONE); } DO_ANY3(AND, tcg_gen_and_i32, a->s, STREG_NORMAL) DO_ANY3(EOR, tcg_gen_xor_i32, a->s, STREG_NORMAL) @@ -9590,7 +9639,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) TCGv_i32 addr; TCGv_i64 tmp64; int op; - int logic_cc; /* * ARMv6-M supports a limited subset of Thumb2 instructions. @@ -10028,22 +10076,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) if (op < 4 && (insn & 0xf000) != 0xf000) goto illegal_op; switch (op) { - case 0: /* Register controlled shift. */ - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - if ((insn & 0x70) != 0) - goto illegal_op; - /* - * 0b1111_1010_0xxx_xxxx_1111_xxxx_0000_xxxx: - * - MOV, MOVS (register-shifted register), flagsetting - */ - op = (insn >> 21) & 3; - logic_cc = (insn & (1 << 20)) != 0; - gen_arm_shift_reg(tmp, op, tmp2, logic_cc); - if (logic_cc) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - break; + case 0: /* Register controlled shift, in decodetree */ + goto illegal_op; case 1: /* Sign/zero extend. */ op = (insn >> 20) & 7; switch (op) { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index b23e83f17c..8e0fb06d05 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -23,6 +23,7 @@ # &s_rrr_shi s rd rn rm shim shty +&s_rrr_shr s rn rd rm rs shty # Data-processing (register) @@ -49,3 +50,29 @@ ORR_rrri .... 000 1100 . .... .... ..... .. 0 .... @s_rrr_shi MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi + +# Data-processing (register-shifted register) + +@s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \ + &s_rrr_shr +@s_rxr_shr ---- ... .... s:1 .... rd:4 rs:4 . shty:2 . rm:4 \ + &s_rrr_shr rn=0 +@S_xrr_shr ---- ... .... . rn:4 .... rs:4 . shty:2 . rm:4 \ + &s_rrr_shr rd=0 s=1 + +AND_rrrr .... 000 0000 . .... .... .... 0 .. 1 .... @s_rrr_shr +EOR_rrrr .... 000 0001 . .... .... .... 0 .. 1 .... @s_rrr_shr +SUB_rrrr .... 000 0010 . .... .... .... 0 .. 1 .... @s_rrr_shr +RSB_rrrr .... 000 0011 . .... .... .... 0 .. 1 .... @s_rrr_shr +ADD_rrrr .... 000 0100 . .... .... .... 0 .. 1 .... @s_rrr_shr +ADC_rrrr .... 000 0101 . .... .... .... 0 .. 1 .... @s_rrr_shr +SBC_rrrr .... 000 0110 . .... .... .... 0 .. 1 .... @s_rrr_shr +RSC_rrrr .... 000 0111 . .... .... .... 0 .. 1 .... @s_rrr_shr +TST_xrrr .... 000 1000 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +TEQ_xrrr .... 000 1001 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +CMP_xrrr .... 000 1010 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +CMN_xrrr .... 000 1011 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +ORR_rrrr .... 000 1100 . .... .... .... 0 .. 1 .... @s_rrr_shr +MOV_rxrr .... 000 1101 . 0000 .... .... 0 .. 1 .... @s_rxr_shr +BIC_rrrr .... 000 1110 . .... .... .... 0 .. 1 .... @s_rrr_shr +MVN_rxrr .... 000 1111 . 0000 .... .... 0 .. 1 .... @s_rxr_shr diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 7068596b99..f0a73fa003 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -20,6 +20,7 @@ # &s_rrr_shi !extern s rd rn rm shim shty +&s_rrr_shr !extern s rn rd rm rs shty # Data-processing (register) @@ -61,3 +62,8 @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi SUB_rrri 1110101 1101 . .... 0 ... .... .... .... @s_rrr_shi } RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi + +# Data-processing (register-shifted register) + +MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \ + &s_rrr_shr rn=0 From patchwork Wed Sep 4 19:29:55 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:29:55 -0700 Message-Id: <20190904193059.26202-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v4 05/69] target/arm: Convert Data Processing (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the modified immediate form of the data processing insns. For A32, we can finally remove any code that was intertwined with the register and register-shifted-register forms. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 449 +++++++++++------------------------------ target/arm/a32.decode | 29 +++ target/arm/t32.decode | 42 ++++ 3 files changed, 186 insertions(+), 334 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index ff78b1bb74..1222946ba4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -439,12 +439,6 @@ static void gen_add16(TCGv_i32 t0, TCGv_i32 t1) tcg_temp_free_i32(t1); } -/* Set CF to the top bit of var. */ -static void gen_set_CF_bit31(TCGv_i32 var) -{ - tcg_gen_shri_i32(cpu_CF, var, 31); -} - /* Set N and Z flags from var. */ static inline void gen_logic_CC(TCGv_i32 var) { @@ -857,25 +851,6 @@ void arm_gen_test_cc(int cc, TCGLabel *label) arm_free_cc(&cmp); } -static const uint8_t table_logic_cc[16] = { - 1, /* and */ - 1, /* xor */ - 0, /* sub */ - 0, /* rsb */ - 0, /* add */ - 0, /* adc */ - 0, /* sbc */ - 0, /* rsc */ - 1, /* andl */ - 1, /* xorl */ - 0, /* cmp */ - 0, /* cmn */ - 1, /* orr */ - 1, /* mov */ - 1, /* bic */ - 1, /* mvn */ -}; - static inline void gen_set_condexec(DisasContext *s) { if (s->condexec_mask) { @@ -7683,6 +7658,48 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond) arm_gen_test_cc(cond ^ 1, s->condlabel); } + +/* + * Constant expanders for the decoders. + */ + +static int times_2(DisasContext *s, int x) +{ + return x * 2; +} + +/* Return only the rotation part of T32ExpandImm. */ +static int t32_expandimm_rot(DisasContext *s, int x) +{ + return x & 0xc00 ? extract32(x, 7, 5) : 0; +} + +/* Return the unrotated immediate from T32ExpandImm. */ +static int t32_expandimm_imm(DisasContext *s, int x) +{ + int imm = extract32(x, 0, 8); + + switch (extract32(x, 8, 4)) { + case 0: /* XY */ + /* Nothing to do. */ + break; + case 1: /* 00XY00XY */ + imm *= 0x00010001; + break; + case 2: /* XY00XY00 */ + imm *= 0x01000100; + break; + case 3: /* XYXYXYXY */ + imm *= 0x01010101; + break; + default: + /* Rotated constant. */ + imm |= 0x80; + break; + } + return imm; +} + /* * Include the generated decoders. */ @@ -7838,23 +7855,82 @@ static bool op_s_rxr_shr(DisasContext *s, arg_s_rrr_shr *a, return store_reg_kind(s, a->rd, tmp2, kind); } +/* + * Data-processing (immediate) + * + * Operate, with set flags, one register source, + * one rotated immediate, and a destination. + * + * Note that logic_cc && a->rot setting CF based on the msb of the + * immediate is the reason why we must pass in the unrotated form + * of the immediate. + */ +static bool op_s_rri_rot(DisasContext *s, arg_s_rri_rot *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + uint32_t imm; + + imm = ror32(a->imm, a->rot); + if (logic_cc && a->rot) { + tcg_gen_movi_i32(cpu_CF, imm >> 31); + } + tmp2 = tcg_const_i32(imm); + tmp1 = load_reg(s, a->rn); + + gen(tmp1, tmp1, tmp2); + tcg_temp_free_i32(tmp2); + + if (logic_cc) { + gen_logic_CC(tmp1); + } + return store_reg_kind(s, a->rd, tmp1, kind); +} + +static bool op_s_rxi_rot(DisasContext *s, arg_s_rri_rot *a, + void (*gen)(TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp; + uint32_t imm; + + imm = ror32(a->imm, a->rot); + if (logic_cc && a->rot) { + tcg_gen_movi_i32(cpu_CF, imm >> 31); + } + tmp = tcg_const_i32(imm); + + gen(tmp, tmp); + if (logic_cc) { + gen_logic_CC(tmp); + } + return store_reg_kind(s, a->rd, tmp, kind); +} + #define DO_ANY3(NAME, OP, L, K) \ static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \ { StoreRegKind k = (K); return op_s_rrr_shi(s, a, OP, L, k); } \ static bool trans_##NAME##_rrrr(DisasContext *s, arg_s_rrr_shr *a) \ - { StoreRegKind k = (K); return op_s_rrr_shr(s, a, OP, L, k); } + { StoreRegKind k = (K); return op_s_rrr_shr(s, a, OP, L, k); } \ + static bool trans_##NAME##_rri(DisasContext *s, arg_s_rri_rot *a) \ + { StoreRegKind k = (K); return op_s_rri_rot(s, a, OP, L, k); } #define DO_ANY2(NAME, OP, L, K) \ static bool trans_##NAME##_rxri(DisasContext *s, arg_s_rrr_shi *a) \ { StoreRegKind k = (K); return op_s_rxr_shi(s, a, OP, L, k); } \ static bool trans_##NAME##_rxrr(DisasContext *s, arg_s_rrr_shr *a) \ - { StoreRegKind k = (K); return op_s_rxr_shr(s, a, OP, L, k); } + { StoreRegKind k = (K); return op_s_rxr_shr(s, a, OP, L, k); } \ + static bool trans_##NAME##_rxi(DisasContext *s, arg_s_rri_rot *a) \ + { StoreRegKind k = (K); return op_s_rxi_rot(s, a, OP, L, k); } #define DO_CMP2(NAME, OP, L) \ static bool trans_##NAME##_xrri(DisasContext *s, arg_s_rrr_shi *a) \ { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } \ static bool trans_##NAME##_xrrr(DisasContext *s, arg_s_rrr_shr *a) \ - { return op_s_rrr_shr(s, a, OP, L, STREG_NONE); } + { return op_s_rrr_shr(s, a, OP, L, STREG_NONE); } \ + static bool trans_##NAME##_xri(DisasContext *s, arg_s_rri_rot *a) \ + { return op_s_rri_rot(s, a, OP, L, STREG_NONE); } DO_ANY3(AND, tcg_gen_and_i32, a->s, STREG_NORMAL) DO_ANY3(EOR, tcg_gen_xor_i32, a->s, STREG_NORMAL) @@ -7934,6 +8010,11 @@ static bool trans_ORN_rrri(DisasContext *s, arg_s_rrr_shi *a) return op_s_rrr_shi(s, a, tcg_gen_orc_i32, a->s, STREG_NORMAL); } +static bool trans_ORN_rri(DisasContext *s, arg_s_rri_rot *a) +{ + return op_s_rri_rot(s, a, tcg_gen_orc_i32, a->s, STREG_NORMAL); +} + #undef DO_ANY3 #undef DO_ANY2 #undef DO_CMP2 @@ -8471,182 +8552,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } else if (((insn & 0x0e000000) == 0 && (insn & 0x00000090) != 0x90) || ((insn & 0x0e000000) == (1 << 25))) { - int set_cc, logic_cc, shiftop; - - op1 = (insn >> 21) & 0xf; - set_cc = (insn >> 20) & 1; - logic_cc = table_logic_cc[op1] & set_cc; - - /* data processing instruction */ - if (insn & (1 << 25)) { - /* immediate operand */ - val = insn & 0xff; - shift = ((insn >> 8) & 0xf) * 2; - val = ror32(val, shift); - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, val); - if (logic_cc && shift) { - gen_set_CF_bit31(tmp2); - } - } else { - /* register */ - rm = (insn) & 0xf; - tmp2 = load_reg(s, rm); - shiftop = (insn >> 5) & 3; - if (!(insn & (1 << 4))) { - shift = (insn >> 7) & 0x1f; - gen_arm_shift_im(tmp2, shiftop, shift, logic_cc); - } else { - rs = (insn >> 8) & 0xf; - tmp = load_reg(s, rs); - gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc); - } - } - if (op1 != 0x0f && op1 != 0x0d) { - rn = (insn >> 16) & 0xf; - tmp = load_reg(s, rn); - } else { - tmp = NULL; - } - rd = (insn >> 12) & 0xf; - switch(op1) { - case 0x00: - tcg_gen_and_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x01: - tcg_gen_xor_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x02: - if (set_cc && rd == 15) { - /* SUBS r15, ... is used for exception return. */ - if (IS_USER(s)) { - goto illegal_op; - } - gen_sub_CC(tmp, tmp, tmp2); - gen_exception_return(s, tmp); - } else { - if (set_cc) { - gen_sub_CC(tmp, tmp, tmp2); - } else { - tcg_gen_sub_i32(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - } - break; - case 0x03: - if (set_cc) { - gen_sub_CC(tmp, tmp2, tmp); - } else { - tcg_gen_sub_i32(tmp, tmp2, tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x04: - if (set_cc) { - gen_add_CC(tmp, tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - break; - case 0x05: - if (set_cc) { - gen_adc_CC(tmp, tmp, tmp2); - } else { - gen_add_carry(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - break; - case 0x06: - if (set_cc) { - gen_sbc_CC(tmp, tmp, tmp2); - } else { - gen_sub_carry(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - break; - case 0x07: - if (set_cc) { - gen_sbc_CC(tmp, tmp2, tmp); - } else { - gen_sub_carry(tmp, tmp2, tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x08: - if (set_cc) { - tcg_gen_and_i32(tmp, tmp, tmp2); - gen_logic_CC(tmp); - } - tcg_temp_free_i32(tmp); - break; - case 0x09: - if (set_cc) { - tcg_gen_xor_i32(tmp, tmp, tmp2); - gen_logic_CC(tmp); - } - tcg_temp_free_i32(tmp); - break; - case 0x0a: - if (set_cc) { - gen_sub_CC(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp); - break; - case 0x0b: - if (set_cc) { - gen_add_CC(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp); - break; - case 0x0c: - tcg_gen_or_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x0d: - if (logic_cc && rd == 15) { - /* MOVS r15, ... is used for exception return. */ - if (IS_USER(s)) { - goto illegal_op; - } - gen_exception_return(s, tmp2); - } else { - if (logic_cc) { - gen_logic_CC(tmp2); - } - store_reg_bx(s, rd, tmp2); - } - break; - case 0x0e: - tcg_gen_andc_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - default: - case 0x0f: - tcg_gen_not_i32(tmp2, tmp2); - if (logic_cc) { - gen_logic_CC(tmp2); - } - store_reg_bx(s, rd, tmp2); - break; - } - if (op1 != 0x0f && op1 != 0x0d) { - tcg_temp_free_i32(tmp2); - } + /* Data-processing (reg, reg-shift-reg, imm). */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } else { /* other instructions */ op1 = (insn >> 24) & 0xf; @@ -9552,82 +9460,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn) return true; } -/* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero - then set condition code flags based on the result of the operation. - If SHIFTER_OUT is nonzero then set the carry flag for logical operations - to the high bit of T1. - Returns zero if the opcode is valid. */ - -static int -gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, - TCGv_i32 t0, TCGv_i32 t1) -{ - int logic_cc; - - logic_cc = 0; - switch (op) { - case 0: /* and */ - tcg_gen_and_i32(t0, t0, t1); - logic_cc = conds; - break; - case 1: /* bic */ - tcg_gen_andc_i32(t0, t0, t1); - logic_cc = conds; - break; - case 2: /* orr */ - tcg_gen_or_i32(t0, t0, t1); - logic_cc = conds; - break; - case 3: /* orn */ - tcg_gen_orc_i32(t0, t0, t1); - logic_cc = conds; - break; - case 4: /* eor */ - tcg_gen_xor_i32(t0, t0, t1); - logic_cc = conds; - break; - case 8: /* add */ - if (conds) - gen_add_CC(t0, t0, t1); - else - tcg_gen_add_i32(t0, t0, t1); - break; - case 10: /* adc */ - if (conds) - gen_adc_CC(t0, t0, t1); - else - gen_adc(t0, t1); - break; - case 11: /* sbc */ - if (conds) { - gen_sbc_CC(t0, t0, t1); - } else { - gen_sub_carry(t0, t0, t1); - } - break; - case 13: /* sub */ - if (conds) - gen_sub_CC(t0, t0, t1); - else - tcg_gen_sub_i32(t0, t0, t1); - break; - case 14: /* rsb */ - if (conds) - gen_sub_CC(t0, t1, t0); - else - tcg_gen_sub_i32(t0, t1, t0); - break; - default: /* 5, 6, 7, 9, 12, 15. */ - return 1; - } - if (logic_cc) { - gen_logic_CC(t0); - if (shifter_out) - gen_set_CF_bit31(t1); - } - return 0; -} - /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { @@ -10909,60 +10741,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } } } else { - /* - * 0b1111_0x0x_xxxx_0xxx_xxxx_xxxx - * - Data-processing (modified immediate) - */ - int shifter_out = 0; - /* modified 12-bit immediate. */ - shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12); - imm = (insn & 0xff); - switch (shift) { - case 0: /* XY */ - /* Nothing to do. */ - break; - case 1: /* 00XY00XY */ - imm |= imm << 16; - break; - case 2: /* XY00XY00 */ - imm |= imm << 16; - imm <<= 8; - break; - case 3: /* XYXYXYXY */ - imm |= imm << 16; - imm |= imm << 8; - break; - default: /* Rotated constant. */ - shift = (shift << 1) | (imm >> 7); - imm |= 0x80; - imm = imm << (32 - shift); - shifter_out = 1; - break; - } - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, imm); - rn = (insn >> 16) & 0xf; - if (rn == 15) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp = load_reg(s, rn); - } - op = (insn >> 21) & 0xf; - if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0, - shifter_out, tmp, tmp2)) - goto illegal_op; - tcg_temp_free_i32(tmp2); - rd = (insn >> 8) & 0xf; - if (rd == 13 && rn == 13 - && (op == 8 || op == 13)) { - /* ADD(S) SP, SP, imm or SUB(S) SP, SP, imm */ - store_sp_checked(s, tmp); - } else if (rd != 15) { - store_reg(s, rd, tmp); - } else { - tcg_temp_free_i32(tmp); - } + /* Data-processing (modified immediate) */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } } break; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 8e0fb06d05..286adcbf89 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -24,6 +24,7 @@ &s_rrr_shi s rd rn rm shim shty &s_rrr_shr s rn rd rm rs shty +&s_rri_rot s rn rd imm rot # Data-processing (register) @@ -76,3 +77,31 @@ ORR_rrrr .... 000 1100 . .... .... .... 0 .. 1 .... @s_rrr_shr MOV_rxrr .... 000 1101 . 0000 .... .... 0 .. 1 .... @s_rxr_shr BIC_rrrr .... 000 1110 . .... .... .... 0 .. 1 .... @s_rrr_shr MVN_rxrr .... 000 1111 . 0000 .... .... 0 .. 1 .... @s_rxr_shr + +# Data-processing (immediate) + +%a32extrot 8:4 !function=times_2 + +@s_rri_rot ---- ... .... s:1 rn:4 rd:4 .... imm:8 \ + &s_rri_rot rot=%a32extrot +@s_rxi_rot ---- ... .... s:1 .... rd:4 .... imm:8 \ + &s_rri_rot rot=%a32extrot rn=0 +@S_xri_rot ---- ... .... . rn:4 .... .... imm:8 \ + &s_rri_rot rot=%a32extrot rd=0 s=1 + +AND_rri .... 001 0000 . .... .... ............ @s_rri_rot +EOR_rri .... 001 0001 . .... .... ............ @s_rri_rot +SUB_rri .... 001 0010 . .... .... ............ @s_rri_rot +RSB_rri .... 001 0011 . .... .... ............ @s_rri_rot +ADD_rri .... 001 0100 . .... .... ............ @s_rri_rot +ADC_rri .... 001 0101 . .... .... ............ @s_rri_rot +SBC_rri .... 001 0110 . .... .... ............ @s_rri_rot +RSC_rri .... 001 0111 . .... .... ............ @s_rri_rot +TST_xri .... 001 1000 1 .... 0000 ............ @S_xri_rot +TEQ_xri .... 001 1001 1 .... 0000 ............ @S_xri_rot +CMP_xri .... 001 1010 1 .... 0000 ............ @S_xri_rot +CMN_xri .... 001 1011 1 .... 0000 ............ @S_xri_rot +ORR_rri .... 001 1100 . .... .... ............ @s_rri_rot +MOV_rxi .... 001 1101 . 0000 .... ............ @s_rxi_rot +BIC_rri .... 001 1110 . .... .... ............ @s_rri_rot +MVN_rxi .... 001 1111 . 0000 .... ............ @s_rxi_rot diff --git a/target/arm/t32.decode b/target/arm/t32.decode index f0a73fa003..50cbe48cc8 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -21,6 +21,7 @@ &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty +&s_rri_rot !extern s rn rd imm rot # Data-processing (register) @@ -67,3 +68,44 @@ RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \ &s_rrr_shr rn=0 + +# Data-processing (immediate) + +%t32extrot 26:1 12:3 0:8 !function=t32_expandimm_rot +%t32extimm 26:1 12:3 0:8 !function=t32_expandimm_imm + +@s_rri_rot ....... .... s:1 rn:4 . ... rd:4 ........ \ + &s_rri_rot imm=%t32extimm rot=%t32extrot +@s_rxi_rot ....... .... s:1 .... . ... rd:4 ........ \ + &s_rri_rot imm=%t32extimm rot=%t32extrot rn=0 +@S_xri_rot ....... .... . rn:4 . ... .... ........ \ + &s_rri_rot imm=%t32extimm rot=%t32extrot s=1 rd=0 + +{ + TST_xri 1111 0.0 0000 1 .... 0 ... 1111 ........ @S_xri_rot + AND_rri 1111 0.0 0000 . .... 0 ... .... ........ @s_rri_rot +} +BIC_rri 1111 0.0 0001 . .... 0 ... .... ........ @s_rri_rot +{ + MOV_rxi 1111 0.0 0010 . 1111 0 ... .... ........ @s_rxi_rot + ORR_rri 1111 0.0 0010 . .... 0 ... .... ........ @s_rri_rot +} +{ + MVN_rxi 1111 0.0 0011 . 1111 0 ... .... ........ @s_rxi_rot + ORN_rri 1111 0.0 0011 . .... 0 ... .... ........ @s_rri_rot +} +{ + TEQ_xri 1111 0.0 0100 1 .... 0 ... 1111 ........ @S_xri_rot + EOR_rri 1111 0.0 0100 . .... 0 ... .... ........ @s_rri_rot +} +{ + CMN_xri 1111 0.0 1000 1 .... 0 ... 1111 ........ @S_xri_rot + ADD_rri 1111 0.0 1000 . .... 0 ... .... ........ @s_rri_rot +} +ADC_rri 1111 0.0 1010 . .... 0 ... .... ........ @s_rri_rot +SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot +{ + CMP_xri 1111 0.0 1101 1 .... 0 ... 1111 ........ @S_xri_rot + SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot +} +RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot From patchwork Wed Sep 4 19:29:56 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:29:56 -0700 Message-Id: <20190904193059.26202-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52a Subject: [Qemu-devel] [PATCH v4 06/69] target/arm: Convert multiply and multiply accumulate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 248 +++++++++++++++++++++++------------------ target/arm/a32.decode | 17 +++ target/arm/t32.decode | 19 ++++ 3 files changed, 177 insertions(+), 107 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 1222946ba4..9bcf1e0964 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8019,6 +8019,125 @@ static bool trans_ORN_rri(DisasContext *s, arg_s_rri_rot *a) #undef DO_ANY2 #undef DO_CMP2 +/* + * Multiply and multiply accumulate + */ + +static bool op_mla(DisasContext *s, arg_s_rrrr *a, bool add) +{ + TCGv_i32 t1, t2; + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + tcg_gen_mul_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + if (add) { + t2 = load_reg(s, a->ra); + tcg_gen_add_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + } + if (a->s) { + gen_logic_CC(t1); + } + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_MUL(DisasContext *s, arg_MUL *a) +{ + return op_mla(s, a, false); +} + +static bool trans_MLA(DisasContext *s, arg_MLA *a) +{ + return op_mla(s, a, true); +} + +static bool trans_MLS(DisasContext *s, arg_MLS *a) +{ + TCGv_i32 t1, t2; + + if (!ENABLE_ARCH_6T2) { + return false; + } + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + tcg_gen_mul_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + t2 = load_reg(s, a->ra); + tcg_gen_sub_i32(t1, t2, t1); + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool op_mlal(DisasContext *s, arg_s_rrrr *a, bool uns, bool add) +{ + TCGv_i32 t0, t1, t2, t3; + + t0 = load_reg(s, a->rm); + t1 = load_reg(s, a->rn); + if (uns) { + tcg_gen_mulu2_i32(t0, t1, t0, t1); + } else { + tcg_gen_muls2_i32(t0, t1, t0, t1); + } + if (add) { + t2 = load_reg(s, a->ra); + t3 = load_reg(s, a->rd); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, t3); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + } + if (a->s) { + gen_logicq_cc(t0, t1); + } + store_reg(s, a->ra, t0); + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_UMULL(DisasContext *s, arg_UMULL *a) +{ + return op_mlal(s, a, true, false); +} + +static bool trans_SMULL(DisasContext *s, arg_SMULL *a) +{ + return op_mlal(s, a, false, false); +} + +static bool trans_UMLAL(DisasContext *s, arg_UMLAL *a) +{ + return op_mlal(s, a, true, true); +} + +static bool trans_SMLAL(DisasContext *s, arg_SMLAL *a) +{ + return op_mlal(s, a, false, true); +} + +static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) +{ + TCGv_i32 t0, t1; + TCGv_i64 t64; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t0 = load_reg(s, a->rm); + t1 = load_reg(s, a->rn); + t64 = gen_mulu_i64_i32(t0, t1); + gen_addq_lo(s, t64, a->ra); + gen_addq_lo(s, t64, a->rd); + gen_storeq_reg(s, a->ra, a->rd, t64); + tcg_temp_free_i64(t64); + return true; +} + /* * Legacy decoder. */ @@ -8565,71 +8684,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) sh = (insn >> 5) & 3; if (sh == 0) { if (op1 == 0x0) { - rd = (insn >> 16) & 0xf; - rn = (insn >> 12) & 0xf; - rs = (insn >> 8) & 0xf; - rm = (insn) & 0xf; - op1 = (insn >> 20) & 0xf; - switch (op1) { - case 0: case 1: case 2: case 3: case 6: - /* 32 bit mul */ - tmp = load_reg(s, rs); - tmp2 = load_reg(s, rm); - tcg_gen_mul_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (insn & (1 << 22)) { - /* Subtract (mls) */ - ARCH(6T2); - tmp2 = load_reg(s, rn); - tcg_gen_sub_i32(tmp, tmp2, tmp); - tcg_temp_free_i32(tmp2); - } else if (insn & (1 << 21)) { - /* Add */ - tmp2 = load_reg(s, rn); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - if (insn & (1 << 20)) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - break; - case 4: - /* 64 bit mul double accumulate (UMAAL) */ - ARCH(6); - tmp = load_reg(s, rs); - tmp2 = load_reg(s, rm); - tmp64 = gen_mulu_i64_i32(tmp, tmp2); - gen_addq_lo(s, tmp64, rn); - gen_addq_lo(s, tmp64, rd); - gen_storeq_reg(s, rn, rd, tmp64); - tcg_temp_free_i64(tmp64); - break; - case 8: case 9: case 10: case 11: - case 12: case 13: case 14: case 15: - /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */ - tmp = load_reg(s, rs); - tmp2 = load_reg(s, rm); - if (insn & (1 << 22)) { - tcg_gen_muls2_i32(tmp, tmp2, tmp, tmp2); - } else { - tcg_gen_mulu2_i32(tmp, tmp2, tmp, tmp2); - } - if (insn & (1 << 21)) { /* mult accumulate */ - TCGv_i32 al = load_reg(s, rn); - TCGv_i32 ah = load_reg(s, rd); - tcg_gen_add2_i32(tmp, tmp2, tmp, tmp2, al, ah); - tcg_temp_free_i32(al); - tcg_temp_free_i32(ah); - } - if (insn & (1 << 20)) { - gen_logicq_cc(tmp, tmp2); - } - store_reg(s, rn, tmp); - store_reg(s, rd, tmp2); - break; - default: - goto illegal_op; - } + /* Multiply and multiply accumulate. */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } else { rn = (insn >> 16) & 0xf; rd = (insn >> 12) & 0xf; @@ -10075,7 +10132,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) break; case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */ switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32 */ + case 0: /* 32 x 32 -> 32, in decodetree */ + goto illegal_op; case 7: /* Unsigned sum of absolute differences. */ break; case 1: /* 16 x 16 -> 32 */ @@ -10092,18 +10150,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tmp = load_reg(s, rn); tmp2 = load_reg(s, rm); switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32 */ - tcg_gen_mul_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rs != 15) { - tmp2 = load_reg(s, rs); - if (op) - tcg_gen_sub_i32(tmp, tmp2, tmp); - else - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; case 1: /* 16 x 16 -> 32 */ gen_mulxy(tmp, tmp2, op & 2, op & 1); tcg_temp_free_i32(tmp2); @@ -10233,36 +10279,24 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) gen_storeq_reg(s, rs, rd, tmp64); tcg_temp_free_i64(tmp64); } else { - if (op & 0x20) { - /* Unsigned 64-bit multiply */ - tmp64 = gen_mulu_i64_i32(tmp, tmp2); - } else { - if (op & 8) { - /* smlalxy */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - gen_mulxy(tmp, tmp2, op & 2, op & 1); - tcg_temp_free_i32(tmp2); - tmp64 = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_temp_free_i32(tmp); - } else { - /* Signed 64-bit multiply */ - tmp64 = gen_muls_i64_i32(tmp, tmp2); - } + if ((op & 0x20) || !(op & 8)) { + /* Signed/unsigned 64-bit multiply, in decodetree */ + tcg_temp_free_i32(tmp2); + tcg_temp_free_i32(tmp); + goto illegal_op; } - if (op & 4) { - /* umaal */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i64(tmp64); - goto illegal_op; - } - gen_addq_lo(s, tmp64, rs); - gen_addq_lo(s, tmp64, rd); - } else if (op & 0x40) { + /* smlalxy */ + if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + tcg_temp_free_i32(tmp2); + tcg_temp_free_i32(tmp); + goto illegal_op; + } + gen_mulxy(tmp, tmp2, op & 2, op & 1); + tcg_temp_free_i32(tmp2); + tmp64 = tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(tmp64, tmp); + tcg_temp_free_i32(tmp); + if (op & 0x40) { /* 64-bit accumulate. */ gen_addq(s, tmp64, rs, rd); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 286adcbf89..87bbb2eec2 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -25,6 +25,8 @@ &s_rrr_shi s rd rn rm shim shty &s_rrr_shr s rn rd rm rs shty &s_rri_rot s rn rd imm rot +&s_rrrr s rd rn rm ra +&rrrr rd rn rm ra # Data-processing (register) @@ -105,3 +107,18 @@ ORR_rri .... 001 1100 . .... .... ............ @s_rri_rot MOV_rxi .... 001 1101 . 0000 .... ............ @s_rxi_rot BIC_rri .... 001 1110 . .... .... ............ @s_rri_rot MVN_rxi .... 001 1111 . 0000 .... ............ @s_rxi_rot + +# Multiply and multiply accumulate + +@s_rdamn ---- .... ... s:1 rd:4 ra:4 rm:4 .... rn:4 &s_rrrr +@s_rd0mn ---- .... ... s:1 rd:4 .... rm:4 .... rn:4 &s_rrrr ra=0 +@rdamn ---- .... ... . rd:4 ra:4 rm:4 .... rn:4 &rrrr + +MUL .... 0000 000 . .... 0000 .... 1001 .... @s_rd0mn +MLA .... 0000 001 . .... .... .... 1001 .... @s_rdamn +UMAAL .... 0000 010 0 .... .... .... 1001 .... @rdamn +MLS .... 0000 011 0 .... .... .... 1001 .... @rdamn +UMULL .... 0000 100 . .... .... .... 1001 .... @s_rdamn +UMLAL .... 0000 101 . .... .... .... 1001 .... @s_rdamn +SMULL .... 0000 110 . .... .... .... 1001 .... @s_rdamn +SMLAL .... 0000 111 . .... .... .... 1001 .... @s_rdamn diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 50cbe48cc8..40cc69aee3 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -22,6 +22,8 @@ &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot +&s_rrrr !extern s rd rn rm ra +&rrrr !extern rd rn rm ra # Data-processing (register) @@ -109,3 +111,20 @@ SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot } RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot + +# Multiply and multiply accumulate + +@s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0 +@s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra=0 s=0 +@rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr + +{ + MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm + MLA 1111 1011 0000 .... .... .... 0000 .... @s0_rnadm +} +MLS 1111 1011 0000 .... .... .... 0001 .... @rnadm +SMULL 1111 1011 1000 .... .... .... 0000 .... @s0_rnadm +UMULL 1111 1011 1010 .... .... .... 0000 .... @s0_rnadm +SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm +UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm +UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm From patchwork Wed Sep 4 19:29:57 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:29:57 -0700 Message-Id: <20190904193059.26202-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v4 07/69] target/arm: Simplify UMAAL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since all of the inputs and outputs are i32, dispense with the intermediate promotion to i64 and use tcg_gen_mulu2_i32 and tcg_gen_add2_i32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 34 ++++++++++++---------------------- 1 file changed, 12 insertions(+), 22 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 9bcf1e0964..8d70f15a4f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7346,21 +7346,6 @@ static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val) store_reg(s, rhigh, tmp); } -/* load a 32-bit value from a register and perform a 64-bit accumulate. */ -static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow) -{ - TCGv_i64 tmp; - TCGv_i32 tmp2; - - /* Load value and extend to 64 bits. */ - tmp = tcg_temp_new_i64(); - tmp2 = load_reg(s, rlow); - tcg_gen_extu_i32_i64(tmp, tmp2); - tcg_temp_free_i32(tmp2); - tcg_gen_add_i64(val, val, tmp); - tcg_temp_free_i64(tmp); -} - /* load and add a 64-bit value from a register pair. */ static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh) { @@ -8119,8 +8104,7 @@ static bool trans_SMLAL(DisasContext *s, arg_SMLAL *a) static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) { - TCGv_i32 t0, t1; - TCGv_i64 t64; + TCGv_i32 t0, t1, t2, zero; if (s->thumb ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) @@ -8130,11 +8114,17 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) t0 = load_reg(s, a->rm); t1 = load_reg(s, a->rn); - t64 = gen_mulu_i64_i32(t0, t1); - gen_addq_lo(s, t64, a->ra); - gen_addq_lo(s, t64, a->rd); - gen_storeq_reg(s, a->ra, a->rd, t64); - tcg_temp_free_i64(t64); + tcg_gen_mulu2_i32(t0, t1, t0, t1); + zero = tcg_const_i32(0); + t2 = load_reg(s, a->ra); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); + tcg_temp_free_i32(t2); + t2 = load_reg(s, a->rd); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(zero); + store_reg(s, a->ra, t0); + store_reg(s, a->rd, t1); return true; } From patchwork Wed Sep 4 19:29:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172972 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp359668ilq; Wed, 4 Sep 2019 12:41:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqyd5YmL7j3PCSIFDSL6RtZzZfq5BpQ6+VIJSiZHZkOrUCHVwJRPXFT7gc5l1KDrbJldIVF9 X-Received: by 2002:a50:fd95:: with SMTP id o21mr13917059edt.6.1567626117713; Wed, 04 Sep 2019 12:41:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567626117; cv=none; d=google.com; s=arc-20160816; b=k1vhkAZWLOkrBlDsmD0IaI/JtKzh4jzXAgHwQitw44Fyb49HbbQ5zH5KMGZlHTJtnY O83lbc4j1TfbOfA8SHYm/nnMR6odWNY8tu+e/BhSKPliBKodo7G+QqUBL5EN/giMhXOG sf6JIbhIGIFk0RNA5EGu/vEdnsB/AKO2rWKbMPTp7f+fiZKHYoWvg7/T8w0yRXtSiF1x sv0O1CdgRc/FU5iEmumX/R64Cr5ID32YXsM2G9/ID6z/hpe1myeF3LPKT2U0S64Q/iJe nggizj9Mv1anDXuRK+Sb+BfgGumKDsYIzgFmk8x6/yi6u5gvZwFoXbnftUbVQJHWe2QF PBSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=qTBjneugtZF+JoWXJ5FX48BYqpDgfu4BcdXmC9Vl7mc=; b=V29mEjAFonRVVQwCq1z7hn+1f9uF/1A06oDMOVtJbfLI9ARPHBaYsheXbW2fDhoM0l dUpUqBYpHib6IuZVQi97iu4OUSy7MFL4NoHT5JDilIAxUo4qIYXVW9qlVBZDYG8DUHW/ koFzA0MPsrCHXwwBFXgLsnEaCjdZGSlbNWIX/uYt3UoQOruTC9tEqRtTr8PoncBoa/vn 7QppI4L5GwXG5hhLg0r81ZqCVbYgH6XLr2kZZLckIAIr4fXanmhCgd7/sINoxW+UCL9H j0sqBbDdBB+Ms+V3WCMhkN5MarCzVawdltHO19JZf6skbdrDfXPT8BKrPvT4GrvPanft h1Cw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DThbwQFo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:29:58 -0700 Message-Id: <20190904193059.26202-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::430 Subject: [Qemu-devel] [PATCH v4 08/69] target/arm: Convert Saturating addition and subtraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/translate.c | 75 +++++++++++++++++++++++++++--------------- target/arm/a32.decode | 10 ++++++ target/arm/t32.decode | 9 +++++ 3 files changed, 67 insertions(+), 27 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 8d70f15a4f..ddb2c764a1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8128,6 +8128,48 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) return true; } +/* + * Saturating addition and subtraction + */ + +static bool op_qaddsub(DisasContext *s, arg_rrr *a, bool add, bool doub) +{ + TCGv_i32 t0, t1; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_5TE) { + return false; + } + + t0 = load_reg(s, a->rm); + t1 = load_reg(s, a->rn); + if (doub) { + gen_helper_add_saturate(t1, cpu_env, t1, t1); + } + if (add) { + gen_helper_add_saturate(t0, cpu_env, t0, t1); + } else { + gen_helper_sub_saturate(t0, cpu_env, t0, t1); + } + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +#define DO_QADDSUB(NAME, ADD, DOUB) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_qaddsub(s, a, ADD, DOUB); \ +} + +DO_QADDSUB(QADD, true, false) +DO_QADDSUB(QSUB, false, false) +DO_QADDSUB(QDADD, true, true) +DO_QADDSUB(QDSUB, false, true) + +#undef DO_QADDSUB + /* * Legacy decoder. */ @@ -8537,21 +8579,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) store_reg(s, rd, tmp); break; } - case 0x5: /* saturating add/subtract */ - ARCH(5TE); - rd = (insn >> 12) & 0xf; - rn = (insn >> 16) & 0xf; - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rn); - if (op1 & 2) - gen_helper_add_saturate(tmp2, cpu_env, tmp2, tmp2); - if (op1 & 1) - gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2); - else - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + case 0x5: + /* Saturating addition and subtraction. */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0x6: /* ERET */ if (op1 != 3) { goto illegal_op; @@ -10024,18 +10055,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7); if (op < 4) { /* Saturating add/subtract. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - if (op & 1) - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp); - if (op & 2) - gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp); - else - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } else { switch (op) { case 0x0a: /* rbit */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 87bbb2eec2..7791be5590 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -27,6 +27,7 @@ &s_rri_rot s rn rd imm rot &s_rrrr s rd rn rm ra &rrrr rd rn rm ra +&rrr rd rn rm # Data-processing (register) @@ -122,3 +123,12 @@ UMULL .... 0000 100 . .... .... .... 1001 .... @s_rdamn UMLAL .... 0000 101 . .... .... .... 1001 .... @s_rdamn SMULL .... 0000 110 . .... .... .... 1001 .... @s_rdamn SMLAL .... 0000 111 . .... .... .... 1001 .... @s_rdamn + +# Saturating addition and subtraction + +@rndm ---- .... .... rn:4 rd:4 .... .... rm:4 &rrr + +QADD .... 0001 0000 .... .... 0000 0101 .... @rndm +QSUB .... 0001 0010 .... .... 0000 0101 .... @rndm +QDADD .... 0001 0100 .... .... 0000 0101 .... @rndm +QDSUB .... 0001 0110 .... .... 0000 0101 .... @rndm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 40cc69aee3..7c6226e0af 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra +&rrr !extern rd rn rm # Data-processing (register) @@ -117,6 +118,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0 @s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra=0 s=0 @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr +@rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr { MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm @@ -128,3 +130,10 @@ UMULL 1111 1011 1010 .... .... .... 0000 .... @s0_rnadm SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm + +# Data-processing (two source registers) + +QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm +QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm +QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm +QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm From patchwork Wed Sep 4 19:29:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172968 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp355556ilq; Wed, 4 Sep 2019 12:37:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqzvLr39QxdxqIEYjZ4Fp7Yk/2Sb8riuOzgpVdKytcDclLnVf8EyHEe9IdPNx9cTeTwB4qAU X-Received: by 2002:a0c:e88e:: with SMTP id b14mr1768154qvo.122.1567625827397; Wed, 04 Sep 2019 12:37:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567625827; cv=none; d=google.com; s=arc-20160816; b=QSjpxprv9AdF6vVcwgX9IsGegxJq99Q4k6AJC15W0GLB45g0XZuW1m+V5Lcagxael6 gEPskMxy6w198gV9XgJQjqEH0NmIJmbz6nQ0poSjVAjILErQf9KZdlJ0OwFq06DSLFT3 l9jt6H6W2wIdz9OgW07hVGP1EbPCFXlE9UmZPyRRXh+5Fmx8cLQZgGslA8o77vyxTfZg oFf7EtAQjfJQwSoT7ueaBCJFqpgo4+pd/IOVOlVTF1i2tGwJs6/XOwQSYuyriX9JW59I A1TLAoCyD1wuw2SrMqAHnB7qbTNzNbMdqwKLHUHwWlCK3UqUTcYiZWtFQLK+cD3HlIrl xtug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=iwMY4Va0yfoxKscjE8xig8J8a9Pr7U82PT5LI3ovLKI=; b=sXl2yZNFNGGWhrccKK65LIH8p5cqBcH3coi6OT1UC70zVoCcmaZ08kj12j3J1Hc6qy c11l6NmajjXiaUbwZNay57Lp7Rg08r7y7iuh9+X8x4n/cmNrIPp1uFZtB0jVeFYuwDuw /5FIYSvzwmVsg3hkJOX2jXbCZo3h1JmCk5N959E3Mf3DBQfxZVUevXxMSfnk22njeCuK ALfTM/QnSgEJPHl1QXlTMHzSWk0FeO+ByUpUziZT2SdbaTaI/g+geEMNV4uDsvlyw1Sg wQ3SItkMNMnpkuQ3F3mKUzDZquJSvRzsh1uELghAKMgmT43K6wGzOwXd860v/vq8H0xP PX2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=a1dknQ78; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v4 09/69] target/arm: Convert Halfword multiply and multiply accumulate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 218 +++++++++++++++++++++++------------------ target/arm/a32.decode | 20 ++++ target/arm/t32.decode | 29 ++++++ 3 files changed, 170 insertions(+), 97 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index ddb2c764a1..5306e93470 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8170,6 +8170,117 @@ DO_QADDSUB(QDSUB, false, true) #undef DO_QADDSUB +/* + * Halfword multiply and multiply accumulate + */ + +static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, + int add_long, bool nt, bool mt) +{ + TCGv_i32 t0, t1; + TCGv_i64 t64; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_5TE) { + return false; + } + + t0 = load_reg(s, a->rn); + t1 = load_reg(s, a->rm); + gen_mulxy(t0, t1, nt, mt); + tcg_temp_free_i32(t1); + + switch (add_long) { + case 0: + store_reg(s, a->rd, t0); + break; + case 1: + t1 = load_reg(s, a->ra); + gen_helper_add_setq(t0, cpu_env, t0, t1); + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + break; + case 2: + t64 = tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(t64, t0); + tcg_temp_free_i32(t0); + gen_addq(s, t64, a->ra, a->rd); + gen_storeq_reg(s, a->ra, a->rd, t64); + tcg_temp_free_i64(t64); + break; + default: + g_assert_not_reached(); + } + return true; +} + +#define DO_SMLAX(NAME, add, nt, mt) \ +static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \ +{ \ + return op_smlaxxx(s, a, add, nt, mt); \ +} + +DO_SMLAX(SMULBB, 0, 0, 0) +DO_SMLAX(SMULBT, 0, 0, 1) +DO_SMLAX(SMULTB, 0, 1, 0) +DO_SMLAX(SMULTT, 0, 1, 1) + +DO_SMLAX(SMLABB, 1, 0, 0) +DO_SMLAX(SMLABT, 1, 0, 1) +DO_SMLAX(SMLATB, 1, 1, 0) +DO_SMLAX(SMLATT, 1, 1, 1) + +DO_SMLAX(SMLALBB, 2, 0, 0) +DO_SMLAX(SMLALBT, 2, 0, 1) +DO_SMLAX(SMLALTB, 2, 1, 0) +DO_SMLAX(SMLALTT, 2, 1, 1) + +#undef DO_SMLAX + +static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt) +{ + TCGv_i32 t0, t1; + TCGv_i64 t64; + + if (!ENABLE_ARCH_5TE) { + return false; + } + + t0 = load_reg(s, a->rn); + t1 = load_reg(s, a->rm); + if (mt) { + tcg_gen_sari_i32(t1, t1, 16); + } else { + gen_sxth(t1); + } + t64 = gen_muls_i64_i32(t0, t1); + tcg_gen_shri_i64(t64, t64, 16); + t1 = tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(t1, t64); + tcg_temp_free_i64(t64); + if (add) { + t0 = load_reg(s, a->ra); + gen_helper_add_setq(t1, cpu_env, t1, t0); + tcg_temp_free_i32(t0); + } + store_reg(s, a->rd, t1); + return true; +} + +#define DO_SMLAWX(NAME, add, mt) \ +static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \ +{ \ + return op_smlawx(s, a, add, mt); \ +} + +DO_SMLAWX(SMULWB, 0, 0) +DO_SMLAWX(SMULWT, 0, 1) +DO_SMLAWX(SMLAWB, 1, 0) +DO_SMLAWX(SMLAWT, 1, 1) + +#undef DO_SMLAWX + /* * Legacy decoder. */ @@ -8636,56 +8747,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } break; } - case 0x8: /* signed multiply */ + case 0x8: case 0xa: case 0xc: case 0xe: - ARCH(5TE); - rs = (insn >> 8) & 0xf; - rn = (insn >> 12) & 0xf; - rd = (insn >> 16) & 0xf; - if (op1 == 1) { - /* (32 * 16) >> 16 */ - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rs); - if (sh & 4) - tcg_gen_sari_i32(tmp2, tmp2, 16); - else - gen_sxth(tmp2); - tmp64 = gen_muls_i64_i32(tmp, tmp2); - tcg_gen_shri_i64(tmp64, tmp64, 16); - tmp = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tmp64); - tcg_temp_free_i64(tmp64); - if ((sh & 2) == 0) { - tmp2 = load_reg(s, rn); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rd, tmp); - } else { - /* 16 * 16 */ - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rs); - gen_mulxy(tmp, tmp2, sh & 2, sh & 4); - tcg_temp_free_i32(tmp2); - if (op1 == 2) { - tmp64 = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_temp_free_i32(tmp); - gen_addq(s, tmp64, rn, rd); - gen_storeq_reg(s, rn, rd, tmp64); - tcg_temp_free_i64(tmp64); - } else { - if (op1 == 0) { - tmp2 = load_reg(s, rn); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rd, tmp); - } - } - break; + /* Halfword multiply and multiply accumulate. */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; default: goto illegal_op; } @@ -10143,13 +10211,14 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) break; case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */ switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32, in decodetree */ + case 0: /* 32 x 32 -> 32 */ + case 1: /* 16 x 16 -> 32 */ + case 3: /* 32 * 16 -> 32msb */ + /* in decodetree */ goto illegal_op; case 7: /* Unsigned sum of absolute differences. */ break; - case 1: /* 16 x 16 -> 32 */ case 2: /* Dual multiply add. */ - case 3: /* 32 * 16 -> 32msb */ case 4: /* Dual multiply subtract. */ case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { @@ -10161,15 +10230,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tmp = load_reg(s, rn); tmp2 = load_reg(s, rm); switch ((insn >> 20) & 7) { - case 1: /* 16 x 16 -> 32 */ - gen_mulxy(tmp, tmp2, op & 2, op & 1); - tcg_temp_free_i32(tmp2); - if (rs != 15) { - tmp2 = load_reg(s, rs); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; case 2: /* Dual multiply add. */ case 4: /* Dual multiply subtract. */ if (op) @@ -10193,23 +10253,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(tmp2); } break; - case 3: /* 32 * 16 -> 32msb */ - if (op) - tcg_gen_sari_i32(tmp2, tmp2, 16); - else - gen_sxth(tmp2); - tmp64 = gen_muls_i64_i32(tmp, tmp2); - tcg_gen_shri_i64(tmp64, tmp64, 16); - tmp = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tmp64); - tcg_temp_free_i64(tmp64); - if (rs != 15) - { - tmp2 = load_reg(s, rs); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2); if (rs != 15) { @@ -10290,29 +10333,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) gen_storeq_reg(s, rs, rd, tmp64); tcg_temp_free_i64(tmp64); } else { - if ((op & 0x20) || !(op & 8)) { - /* Signed/unsigned 64-bit multiply, in decodetree */ - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - /* smlalxy */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - gen_mulxy(tmp, tmp2, op & 2, op & 1); + /* Signed/unsigned 64-bit multiply, in decodetree */ tcg_temp_free_i32(tmp2); - tmp64 = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); tcg_temp_free_i32(tmp); - if (op & 0x40) { - /* 64-bit accumulate. */ - gen_addq(s, tmp64, rs, rd); - } - gen_storeq_reg(s, rs, rd, tmp64); - tcg_temp_free_i64(tmp64); + goto illegal_op; } break; } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 7791be5590..19d12e726b 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -114,6 +114,7 @@ MVN_rxi .... 001 1111 . 0000 .... ............ @s_rxi_rot @s_rdamn ---- .... ... s:1 rd:4 ra:4 rm:4 .... rn:4 &s_rrrr @s_rd0mn ---- .... ... s:1 rd:4 .... rm:4 .... rn:4 &s_rrrr ra=0 @rdamn ---- .... ... . rd:4 ra:4 rm:4 .... rn:4 &rrrr +@rd0mn ---- .... ... . rd:4 .... rm:4 .... rn:4 &rrrr ra=0 MUL .... 0000 000 . .... 0000 .... 1001 .... @s_rd0mn MLA .... 0000 001 . .... .... .... 1001 .... @s_rdamn @@ -132,3 +133,22 @@ QADD .... 0001 0000 .... .... 0000 0101 .... @rndm QSUB .... 0001 0010 .... .... 0000 0101 .... @rndm QDADD .... 0001 0100 .... .... 0000 0101 .... @rndm QDSUB .... 0001 0110 .... .... 0000 0101 .... @rndm + +# Halfword multiply and multiply accumulate + +SMLABB .... 0001 0000 .... .... .... 1000 .... @rdamn +SMLABT .... 0001 0000 .... .... .... 1100 .... @rdamn +SMLATB .... 0001 0000 .... .... .... 1010 .... @rdamn +SMLATT .... 0001 0000 .... .... .... 1110 .... @rdamn +SMLAWB .... 0001 0010 .... .... .... 1000 .... @rdamn +SMULWB .... 0001 0010 .... 0000 .... 1010 .... @rd0mn +SMLAWT .... 0001 0010 .... .... .... 1100 .... @rdamn +SMULWT .... 0001 0010 .... 0000 .... 1110 .... @rd0mn +SMLALBB .... 0001 0100 .... .... .... 1000 .... @rdamn +SMLALBT .... 0001 0100 .... .... .... 1100 .... @rdamn +SMLALTB .... 0001 0100 .... .... .... 1010 .... @rdamn +SMLALTT .... 0001 0100 .... .... .... 1110 .... @rdamn +SMULBB .... 0001 0110 .... 0000 .... 1000 .... @rd0mn +SMULBT .... 0001 0110 .... 0000 .... 1100 .... @rd0mn +SMULTB .... 0001 0110 .... 0000 .... 1010 .... @rd0mn +SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 7c6226e0af..122a0537ed 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -118,6 +118,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0 @s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra=0 s=0 @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr +@rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &rrrr ra=0 @rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr { @@ -130,6 +131,34 @@ UMULL 1111 1011 1010 .... .... .... 0000 .... @s0_rnadm SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm +{ + SMULWB 1111 1011 0011 .... 1111 .... 0000 .... @rn0dm + SMLAWB 1111 1011 0011 .... .... .... 0000 .... @rnadm +} +{ + SMULWT 1111 1011 0011 .... 1111 .... 0001 .... @rn0dm + SMLAWT 1111 1011 0011 .... .... .... 0001 .... @rnadm +} +{ + SMULBB 1111 1011 0001 .... 1111 .... 0000 .... @rn0dm + SMLABB 1111 1011 0001 .... .... .... 0000 .... @rnadm +} +{ + SMULBT 1111 1011 0001 .... 1111 .... 0001 .... @rn0dm + SMLABT 1111 1011 0001 .... .... .... 0001 .... @rnadm +} +{ + SMULTB 1111 1011 0001 .... 1111 .... 0010 .... @rn0dm + SMLATB 1111 1011 0001 .... .... .... 0010 .... @rnadm +} +{ + SMULTT 1111 1011 0001 .... 1111 .... 0011 .... @rn0dm + SMLATT 1111 1011 0001 .... .... .... 0011 .... @rnadm +} +SMLALBB 1111 1011 1100 .... .... .... 1000 .... @rnadm +SMLALBT 1111 1011 1100 .... .... .... 1001 .... @rnadm +SMLALTB 1111 1011 1100 .... .... .... 1010 .... @rnadm +SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm # Data-processing (two source registers) From patchwork Wed Sep 4 19:30:00 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:00 -0700 Message-Id: <20190904193059.26202-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v4 10/69] target/arm: Simplify op_smlaxxx for SMLAL* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since all of the inputs and outputs are i32, dispense with the intermediate promotion to i64 and use tcg_gen_add2_i32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 5306e93470..37aa873e25 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8177,8 +8177,7 @@ DO_QADDSUB(QDSUB, false, true) static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, int add_long, bool nt, bool mt) { - TCGv_i32 t0, t1; - TCGv_i64 t64; + TCGv_i32 t0, t1, tl, th; if (s->thumb ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) @@ -8202,12 +8201,14 @@ static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, store_reg(s, a->rd, t0); break; case 2: - t64 = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(t64, t0); + tl = load_reg(s, a->ra); + th = load_reg(s, a->rd); + t1 = tcg_const_i32(0); + tcg_gen_add2_i32(tl, th, tl, th, t0, t1); tcg_temp_free_i32(t0); - gen_addq(s, t64, a->ra, a->rd); - gen_storeq_reg(s, a->ra, a->rd, t64); - tcg_temp_free_i64(t64); + tcg_temp_free_i32(t1); + store_reg(s, a->ra, tl); + store_reg(s, a->rd, th); break; default: g_assert_not_reached(); From patchwork Wed Sep 4 19:30:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172974 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp361389ilq; Wed, 4 Sep 2019 12:44:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqz3zMzyXFtysZFp8JZmFNVTYfeCdm6Yvo78EtHWClWGRXUwz954Uu8e17fSPpTc1EU+0JFt X-Received: by 2002:ae9:eb09:: with SMTP id b9mr25290841qkg.84.1567626246813; Wed, 04 Sep 2019 12:44:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567626246; cv=none; d=google.com; s=arc-20160816; b=gWAKvuoq+DcTJipkMHcMg24+OvI8+tKfEl22HPU5gH7cLAMqSp7PIVph6rC7HnpL2m 3n9YzLvrCXhSZv0fQtn+YuaEgOhNSc/KqAzuECuDAAYNaLu7ozJSBTQ7lu0HfDP/hKLY WG6CQ6TZ+fcixesB4qQelbT+/PzfjtDvudmT4aUz/m4uUvLFyv2muKmkORuQYU/Kk2ja L3cFjgyjIhow0/urgA/w+er04VjuG4FpGOj4FvouwtCXnh9QzW3KpIpLOqVtT7qD4PVV ud2MQROaackQnR1UaJCGV+hRprvOQHN5fg2MkyiuXfygpImxCVRNnnzMD7S+RW4dHd5t jIjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=d8Wdw3hGEJ+w80H7Z6N3YxcS5gbQ3Bt1g5kmZafUCnU=; b=THKqHNLBsCd0jQhatK0ZzbHVNP0aNRbdKh1BRwwQtyFbGeP/886ZQNAVc4oQjIOqiX kF7BfULFf636TEzUxr9Ef8Hnz3Ayk+ovjLGibanRGwZJUAhich5AAZK/0UASo9PFcBoA AgHl69/XuEoA0/rh8E2hZWWf1MoQ+cwSjbmv+L1LSPe8FpWp4LYMuNroCJ0UziVOQUZc 48QXvnIztyxo2VGiH7SuJSmGfBjtTmBFZhsfbDTEkPNk5ZqMfcQtbZ5Y6bkl0MgpXm8/ DMzAJ0fZaqIHF0ASq7PvUs+Ytd8gkVAnGfBuKC5/buhw57ccd9eXo9oJaxTGBdr3fZUA SlwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XqaFgemV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:01 -0700 Message-Id: <20190904193059.26202-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v4 11/69] target/arm: Simplify op_smlawx for SMLAW* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" By shifting the 16-bit input left by 16, we can align the desired portion of the 48-bit product and use tcg_gen_muls2_i32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 37aa873e25..71cc96b70e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8242,7 +8242,6 @@ DO_SMLAX(SMLALTT, 2, 1, 1) static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt) { TCGv_i32 t0, t1; - TCGv_i64 t64; if (!ENABLE_ARCH_5TE) { return false; @@ -8250,16 +8249,17 @@ static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt) t0 = load_reg(s, a->rn); t1 = load_reg(s, a->rm); + /* + * Since the nominal result is product<47:16>, shift the 16-bit + * input up by 16 bits, so that the result is at product<63:32>. + */ if (mt) { - tcg_gen_sari_i32(t1, t1, 16); + tcg_gen_andi_i32(t1, t1, 0xffff0000); } else { - gen_sxth(t1); + tcg_gen_shli_i32(t1, t1, 16); } - t64 = gen_muls_i64_i32(t0, t1); - tcg_gen_shri_i64(t64, t64, 16); - t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, t64); - tcg_temp_free_i64(t64); + tcg_gen_muls2_i32(t0, t1, t0, t1); + tcg_temp_free_i32(t0); if (add) { t0 = load_reg(s, a->ra); gen_helper_add_setq(t1, cpu_env, t1, t0); From patchwork Wed Sep 4 19:30:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172978 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp364158ilq; Wed, 4 Sep 2019 12:47:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqzFzCgugdZbSLktkzEQEExRV1m0breQgBxUWDdNeN8Rw/NgQNTCw/CmHw0YqVmGr07HUyUx X-Received: by 2002:a17:906:b35a:: with SMTP id cd26mr33885967ejb.243.1567626435874; Wed, 04 Sep 2019 12:47:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567626435; cv=none; d=google.com; s=arc-20160816; b=VwO7fafolOq3U+fOzJLMMY3XWdcSsRawPVI66E5NM02suje/txa5o6z3nOfzq/DT6v V3zaKcXfqem/iS5roXF8x7DOQ+StiTG3UeJWvzWCH72mDG7sTb9ccB+ycZf+9PkcUTv3 fzTaMbEMEP63L6C7mAb8Pu233pdvnJO5BptU8buXxIPfnnCuqNsMLNR9DRPMjhia5qvs nOKZCsgFph2X35IKHhHL3LS6kTad4rXGH25ce8b5EHPF+KBraXVjGj21bE+74+gzlcvz ohjr3FFSzHMCa/Zv94c5FEPD3LAJNiT9e+TvBG8uHWRuDPkgH5ExPgM/f2AEK9PrH746 /S1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=qIboakrWv9IiGA+mdMxhBvLjlTlOJK5d1FVqxlQZi7U=; b=yZlFu/II5w8EhZTQ1VP5G7o2Q/9/x9e6WiDL1g7FGy3yaHgQhZtWi43OeK/eoSqXQO dvAN37ogAAJYoDTurB/Y15cHcG+yZIPwxi2t64SgPDiH6U4GTKhgm70fjri6Hid4nB+W HR+3r0YHnwqKIYmhnm7DtKRpevxi9FUY91xE5WwveIBhdrR4hJ/wIEvdrgEii4eqAl31 JzG3G8/oeQcmfwV3IdeQO19prIeLdbZKtoHKPmqZLLAz5QDrj2a7P8lWjrF0glwp2Z4O xI7v295Pt9eyW1k72KYmOtDAD1iKuLZA85wCTf7B0RwacEg63yMQpFb1QGlwkVWbREkk kC0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=tHoGUVce; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:02 -0700 Message-Id: <20190904193059.26202-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v4 12/69] target/arm: Convert MSR (immediate) and hints X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 60 +++++++++++++++++++++++++++++------------- target/arm/a32.decode | 25 ++++++++++++++++++ target/arm/t32.decode | 17 ++++++++++++ 3 files changed, 84 insertions(+), 18 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 71cc96b70e..58bfbb8ed9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8282,6 +8282,44 @@ DO_SMLAWX(SMLAWT, 1, 1) #undef DO_SMLAWX +/* + * MSR (immediate) and hints + */ + +static bool trans_YIELD(DisasContext *s, arg_YIELD *a) +{ + gen_nop_hint(s, 1); + return true; +} + +static bool trans_WFE(DisasContext *s, arg_WFE *a) +{ + gen_nop_hint(s, 2); + return true; +} + +static bool trans_WFI(DisasContext *s, arg_WFI *a) +{ + gen_nop_hint(s, 3); + return true; +} + +static bool trans_NOP(DisasContext *s, arg_NOP *a) +{ + return true; +} + +static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a) +{ + uint32_t val = ror32(a->imm, a->rot * 2); + uint32_t mask = msr_mask(s, a->mask, a->r); + + if (gen_set_psr_im(s, mask, a->r, val)) { + unallocated_encoding(s); + } + return true; +} + /* * Legacy decoder. */ @@ -8555,21 +8593,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } store_reg(s, rd, tmp); } else { - if (((insn >> 12) & 0xf) != 0xf) - goto illegal_op; - if (((insn >> 16) & 0xf) == 0) { - gen_nop_hint(s, insn & 0xff); - } else { - /* CPSR = immediate */ - val = insn & 0xff; - shift = ((insn >> 8) & 0xf) * 2; - val = ror32(val, shift); - i = ((insn & (1 << 22)) != 0); - if (gen_set_psr_im(s, msr_mask(s, (insn >> 16) & 0xf, i), - i, val)) { - goto illegal_op; - } - } + /* MSR (immediate) and hints */ + /* All done in decodetree. Illegal ops already signalled. */ + g_assert_not_reached(); } } else if ((insn & 0x0f900000) == 0x01000000 && (insn & 0x00000090) != 0x00000090) { @@ -10522,9 +10548,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; break; case 2: /* cps, nop-hint. */ - if (((insn >> 8) & 7) == 0) { - gen_nop_hint(s, insn & 0xff); - } + /* nop hints in decodetree */ /* Implemented as NOP in user mode. */ if (IS_USER(s)) break; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 19d12e726b..3d5c5408f9 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -22,6 +22,7 @@ # All insns that have 0xf in insn[31:28] are in a32-uncond.decode. # +&empty &s_rrr_shi s rd rn rm shim shty &s_rrr_shr s rn rd rm rs shty &s_rri_rot s rn rd imm rot @@ -152,3 +153,27 @@ SMULBB .... 0001 0110 .... 0000 .... 1000 .... @rd0mn SMULBT .... 0001 0110 .... 0000 .... 1100 .... @rd0mn SMULTB .... 0001 0110 .... 0000 .... 1010 .... @rd0mn SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn + +# MSR (immediate) and hints + +&msr_i r mask rot imm +@msr_i ---- .... .... mask:4 .... rot:4 imm:8 &msr_i + +{ + { + YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 + WFE ---- 0011 0010 0000 1111 ---- 0000 0010 + WFI ---- 0011 0010 0000 1111 ---- 0000 0011 + + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 + # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + + # The canonical nop ends in 00000000, but the whole of the + # rest of the space executes as nop if otherwise unsupported. + NOP ---- 0011 0010 0000 1111 ---- ---- ---- + } + # Note mask = 0 is covered by NOP + MSR_imm .... 0011 0010 .... 1111 .... .... .... @msr_i r=0 +} +MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=1 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 122a0537ed..ccb7cdd4ef 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -19,6 +19,7 @@ # This file is processed by scripts/decodetree.py # +&empty !extern &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot @@ -166,3 +167,19 @@ QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm + +# Branches and miscellaneous control + +{ + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 + + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + + # The canonical nop ends in 0000 0000, but the whole rest + # of the space is "reserved hint, behaves as nop". + NOP 1111 0011 1010 1111 1000 0000 ---- ---- +} From patchwork Wed Sep 4 19:30:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172973 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp360738ilq; Wed, 4 Sep 2019 12:43:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqyF8p+btjTlhAz4yT4gvRsc5Urn7TcEiDKsoWg/bstID71DCBKO5F41j5PgJYRfbEVPud/K X-Received: by 2002:a05:6214:1369:: with SMTP id c9mr18559637qvw.3.1567626199482; Wed, 04 Sep 2019 12:43:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567626199; cv=none; d=google.com; s=arc-20160816; b=fwjZ9n3clKS1nIukcJNAEfxd2Szmx/rxeix8qcfV8YO/AGAvE7zcR8DHRi4bHxP6Gc ve+kC3k/DdFDg7QqgGMXLpJ2mU78rOYJrrVF0RYOI+XGxdEEbO5VdKqaRhW9a3Uptvgw 1IiIipmkH21SPBFQ7CZydZXpTRQ1bEqnul9AfUUiCFvjWA1O+OOvyuNaW/LPyYbmonal f8td6aRbbTCfJLjrF0Ovxge6iGIbKTjKu6MuC8hyPG3Ne/O+QoRGfJobnPkHE1n7IN4O 9sRvenQvb2RpXtq2oEFTTaTuw/uBqBp83pptQa6rDKuKQaTajjrr1V/9W9RV7gyS96/P 0OTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=m4MAJXgoOrMBvW2yiXtAmVUpQTazbzn/T7aZQnWvwi0=; b=q6XfzsnhY0t/co6jk8xT236Z2jV/LzY/uFYOZpBV01zIV3GTx0mkfmD5jXVlbKkOZb g7uZ/kEaxMxE1w8aBPR47ZrenfgCxY2u/JTKy1ZqlrgSPnSEzcKWuVcWgiq6bLNOkXhN tbPsMd3dN6lgksJPzXLO0/vZEWi5T/lEGg8Vak1o+5WUmX5EVNeZd1/Xp/bfA9y+YLXe lLJYc7YQSi/24WuYtikCmGRmlgI3UgCdQWKaUHNTF5C+hgpd37xJT14sumOYzIYujCOQ kFPW9MRJ/ym8wUGozRYuHP2k71vac3oNbsdps6VfYopRwg799uFbPGxKbo2+s0E97nPU qzdQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eIPILYG8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:03 -0700 Message-Id: <20190904193059.26202-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v4 13/69] target/arm: Convert MRS/MSR (banked, register) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The m-profile and a-profile decodings overlap. Only return false for the case of wrong profile; handle UNDEFINED for permission failure directly. This ensures that we don't accidentally pass an insn that applies to the wrong profile. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 226 ++++++++++++++++++----------------------- target/arm/a32.decode | 14 +++ target/arm/t32.decode | 40 ++++++-- 3 files changed, 142 insertions(+), 138 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 58bfbb8ed9..02dd4a2ab8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8320,6 +8320,93 @@ static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a) return true; } +/* + * Miscellaneous instructions + */ + +static bool trans_MRS_bank(DisasContext *s, arg_MRS_bank *a) +{ + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_mrs_banked(s, a->r, a->sysm, a->rd); + return true; +} + +static bool trans_MSR_bank(DisasContext *s, arg_MSR_bank *a) +{ + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_msr_banked(s, a->r, a->sysm, a->rn); + return true; +} + +static bool trans_MRS_reg(DisasContext *s, arg_MRS_reg *a) +{ + TCGv_i32 tmp; + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (a->r) { + if (IS_USER(s)) { + unallocated_encoding(s); + return true; + } + tmp = load_cpu_field(spsr); + } else { + tmp = tcg_temp_new_i32(); + gen_helper_cpsr_read(tmp, cpu_env); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_MSR_reg(DisasContext *s, arg_MSR_reg *a) +{ + TCGv_i32 tmp; + uint32_t mask = msr_mask(s, a->mask, a->r); + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + tmp = load_reg(s, a->rn); + if (gen_set_psr(s, mask, a->r, tmp)) { + unallocated_encoding(s); + } + return true; +} + +static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a) +{ + TCGv_i32 tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + tmp = tcg_const_i32(a->sysm); + gen_helper_v7m_mrs(tmp, cpu_env, tmp); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) +{ + TCGv_i32 addr, reg; + + if (!arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + addr = tcg_const_i32((a->mask << 10) | a->sysm); + reg = load_reg(s, a->rn); + gen_helper_v7m_msr(cpu_env, addr, reg); + tcg_temp_free_i32(addr); + tcg_temp_free_i32(reg); + gen_lookup_tb(s); + return true; +} + /* * Legacy decoder. */ @@ -8604,46 +8691,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) sh = (insn >> 4) & 0xf; rm = insn & 0xf; switch (sh) { - case 0x0: /* MSR, MRS */ - if (insn & (1 << 9)) { - /* MSR (banked) and MRS (banked) */ - int sysm = extract32(insn, 16, 4) | - (extract32(insn, 8, 1) << 4); - int r = extract32(insn, 22, 1); - - if (op1 & 1) { - /* MSR (banked) */ - gen_msr_banked(s, r, sysm, rm); - } else { - /* MRS (banked) */ - int rd = extract32(insn, 12, 4); - - gen_mrs_banked(s, r, sysm, rd); - } - break; - } - - /* MSR, MRS (for PSRs) */ - if (op1 & 1) { - /* PSR = reg */ - tmp = load_reg(s, rm); - i = ((op1 & 2) != 0); - if (gen_set_psr(s, msr_mask(s, (insn >> 16) & 0xf, i), i, tmp)) - goto illegal_op; - } else { - /* reg = PSR */ - rd = (insn >> 12) & 0xf; - if (op1 & 2) { - if (IS_USER(s)) - goto illegal_op; - tmp = load_cpu_field(spsr); - } else { - tmp = tcg_temp_new_i32(); - gen_helper_cpsr_read(tmp, cpu_env); - } - store_reg(s, rd, tmp); - } - break; + case 0x0: + /* MSR/MRS (banked/register) */ + /* All done in decodetree. Illegal ops already signalled. */ + g_assert_not_reached(); case 0x1: if (op1 == 1) { /* branch/exchange thumb (bx). */ @@ -10513,40 +10564,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } else { op = (insn >> 20) & 7; switch (op) { - case 0: /* msr cpsr. */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - tmp = load_reg(s, rn); - /* the constant is the mask and SYSm fields */ - addr = tcg_const_i32(insn & 0xfff); - gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); - tcg_temp_free_i32(tmp); - gen_lookup_tb(s); - break; - } - /* fall through */ - case 1: /* msr spsr. */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - - if (extract32(insn, 5, 1)) { - /* MSR (banked) */ - int sysm = extract32(insn, 8, 4) | - (extract32(insn, 4, 1) << 4); - int r = op & 1; - - gen_msr_banked(s, r, sysm, rm); - break; - } - - /* MSR (for PSRs) */ - tmp = load_reg(s, rn); - if (gen_set_psr(s, - msr_mask(s, (insn >> 8) & 0xf, op == 1), - op == 1, tmp)) - goto illegal_op; - break; + case 0: /* msr cpsr, in decodetree */ + case 1: /* msr spsr, in decodetree */ + goto illegal_op; case 2: /* cps, nop-hint. */ /* nop hints in decodetree */ /* Implemented as NOP in user mode. */ @@ -10638,61 +10658,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } gen_exception_return(s, tmp); break; - case 6: /* MRS */ - if (extract32(insn, 5, 1) && - !arm_dc_feature(s, ARM_FEATURE_M)) { - /* MRS (banked) */ - int sysm = extract32(insn, 16, 4) | - (extract32(insn, 4, 1) << 4); - - gen_mrs_banked(s, 0, sysm, rd); - break; - } - - if (extract32(insn, 16, 4) != 0xf) { - goto illegal_op; - } - if (!arm_dc_feature(s, ARM_FEATURE_M) && - extract32(insn, 0, 8) != 0) { - goto illegal_op; - } - - /* mrs cpsr */ - tmp = tcg_temp_new_i32(); - if (arm_dc_feature(s, ARM_FEATURE_M)) { - addr = tcg_const_i32(insn & 0xff); - gen_helper_v7m_mrs(tmp, cpu_env, addr); - tcg_temp_free_i32(addr); - } else { - gen_helper_cpsr_read(tmp, cpu_env); - } - store_reg(s, rd, tmp); - break; - case 7: /* MRS */ - if (extract32(insn, 5, 1) && - !arm_dc_feature(s, ARM_FEATURE_M)) { - /* MRS (banked) */ - int sysm = extract32(insn, 16, 4) | - (extract32(insn, 4, 1) << 4); - - gen_mrs_banked(s, 1, sysm, rd); - break; - } - - /* mrs spsr. */ - /* Not accessible in user mode. */ - if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - - if (extract32(insn, 16, 4) != 0xf || - extract32(insn, 0, 8) != 0) { - goto illegal_op; - } - - tmp = load_cpu_field(spsr); - store_reg(s, rd, tmp); - break; + case 6: /* MRS, in decodetree */ + case 7: /* MSR, in decodetree */ + goto illegal_op; } } } else { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 3d5c5408f9..6ee12c1140 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -29,6 +29,10 @@ &s_rrrr s rd rn rm ra &rrrr rd rn rm ra &rrr rd rn rm +&msr_reg rn r mask +&mrs_reg rd r +&msr_bank rn r sysm +&mrs_bank rd r sysm # Data-processing (register) @@ -177,3 +181,13 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn MSR_imm .... 0011 0010 .... 1111 .... .... .... @msr_i r=0 } MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=1 + +# Miscellaneous instructions + +%sysm 8:1 16:4 + +MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %sysm +MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %sysm + +MRS_reg ---- 0001 0 r:1 00 1111 rd:4 0000 0000 0000 &mrs_reg +MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ccb7cdd4ef..98b682e7ec 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -26,6 +26,10 @@ &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra &rrr !extern rd rn rm +&msr_reg !extern rn r mask +&mrs_reg !extern rd r +&msr_bank !extern rn r sysm +&mrs_bank !extern rd r sysm # Data-processing (register) @@ -170,16 +174,34 @@ QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm # Branches and miscellaneous control +%msr_sysm 4:1 8:4 +%mrs_sysm 4:1 16:4 + { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + { + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 - # The canonical nop ends in 0000 0000, but the whole rest - # of the space is "reserved hint, behaves as nop". - NOP 1111 0011 1010 1111 1000 0000 ---- ---- + # The canonical nop ends in 0000 0000, but the whole rest + # of the space is "reserved hint, behaves as nop". + NOP 1111 0011 1010 1111 1000 0000 ---- ---- + } + # Note that the v7m insn overlaps both the normal and banked insn. + { + MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ + &mrs_bank sysm=%mrs_sysm + MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg + MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8 + } + { + MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \ + &msr_bank sysm=%msr_sysm + MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg + MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 + } } From patchwork Wed Sep 4 19:30:04 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:04 -0700 Message-Id: <20190904193059.26202-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v4 14/69] target/arm: Convert Cyclic Redundancy Check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 121 +++++++++++++++++++---------------------- target/arm/a32.decode | 9 +++ target/arm/t32.decode | 7 +++ 3 files changed, 72 insertions(+), 65 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 02dd4a2ab8..9d3f31f569 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8320,6 +8320,57 @@ static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a) return true; } +/* + * Cyclic Redundancy Check + */ + +static bool op_crc32(DisasContext *s, arg_rrr *a, bool c, MemOp sz) +{ + TCGv_i32 t1, t2, t3; + + if (!dc_isar_feature(aa32_crc32, s)) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + switch (sz) { + case MO_8: + gen_uxtb(t2); + break; + case MO_16: + gen_uxth(t2); + break; + case MO_32: + break; + default: + g_assert_not_reached(); + } + t3 = tcg_const_i32(1 << sz); + if (c) { + gen_helper_crc32c(t1, t1, t2, t3); + } else { + gen_helper_crc32(t1, t1, t2, t3); + } + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + store_reg(s, a->rd, t1); + return true; +} + +#define DO_CRC32(NAME, c, sz) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ + { return op_crc32(s, a, c, sz); } + +DO_CRC32(CRC32B, false, MO_8) +DO_CRC32(CRC32H, false, MO_16) +DO_CRC32(CRC32W, false, MO_32) +DO_CRC32(CRC32CB, true, MO_8) +DO_CRC32(CRC32CH, true, MO_16) +DO_CRC32(CRC32CW, true, MO_32) + +#undef DO_CRC32 + /* * Miscellaneous instructions */ @@ -8735,39 +8786,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) gen_bx(s, tmp); break; case 0x4: - { - /* crc32/crc32c */ - uint32_t c = extract32(insn, 8, 4); - - /* Check this CPU supports ARMv8 CRC instructions. - * op1 == 3 is UNPREDICTABLE but handle as UNDEFINED. - * Bits 8, 10 and 11 should be zero. - */ - if (!dc_isar_feature(aa32_crc32, s) || op1 == 0x3 || (c & 0xd) != 0) { - goto illegal_op; - } - - rn = extract32(insn, 16, 4); - rd = extract32(insn, 12, 4); - - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - if (op1 == 0) { - tcg_gen_andi_i32(tmp2, tmp2, 0xff); - } else if (op1 == 1) { - tcg_gen_andi_i32(tmp2, tmp2, 0xffff); - } - tmp3 = tcg_const_i32(1 << op1); - if (c & 0x2) { - gen_helper_crc32c(tmp, tmp, tmp2, tmp3); - } else { - gen_helper_crc32(tmp, tmp, tmp2, tmp3); - } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); - store_reg(s, rd, tmp); - break; - } + /* crc32 */ + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; case 0x5: /* Saturating addition and subtraction. */ /* All done in decodetree. Reach here for illegal ops. */ @@ -10216,16 +10237,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; } break; - case 0x20: /* crc32/crc32c */ + case 0x20: /* crc32/crc32c, in decodetree */ case 0x21: case 0x22: case 0x28: case 0x29: case 0x2a: - if (!dc_isar_feature(aa32_crc32, s)) { - goto illegal_op; - } - break; + goto illegal_op; default: goto illegal_op; } @@ -10254,33 +10272,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 0x18: /* clz */ tcg_gen_clzi_i32(tmp, tmp, 32); break; - case 0x20: - case 0x21: - case 0x22: - case 0x28: - case 0x29: - case 0x2a: - { - /* crc32/crc32c */ - uint32_t sz = op & 0x3; - uint32_t c = op & 0x8; - - tmp2 = load_reg(s, rm); - if (sz == 0) { - tcg_gen_andi_i32(tmp2, tmp2, 0xff); - } else if (sz == 1) { - tcg_gen_andi_i32(tmp2, tmp2, 0xffff); - } - tmp3 = tcg_const_i32(1 << sz); - if (c) { - gen_helper_crc32c(tmp, tmp, tmp2, tmp3); - } else { - gen_helper_crc32(tmp, tmp, tmp2, tmp3); - } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); - break; - } default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 6ee12c1140..a8ef435b15 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -182,6 +182,15 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn } MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=1 +# Cyclic Redundancy Check + +CRC32B .... 0001 0000 .... .... 0000 0100 .... @rndm +CRC32H .... 0001 0010 .... .... 0000 0100 .... @rndm +CRC32W .... 0001 0100 .... .... 0000 0100 .... @rndm +CRC32CB .... 0001 0000 .... .... 0010 0100 .... @rndm +CRC32CH .... 0001 0010 .... .... 0010 0100 .... @rndm +CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm + # Miscellaneous instructions %sysm 8:1 16:4 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 98b682e7ec..261db100ff 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -172,6 +172,13 @@ QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm +CRC32B 1111 1010 1100 .... 1111 .... 1000 .... @rndm +CRC32H 1111 1010 1100 .... 1111 .... 1001 .... @rndm +CRC32W 1111 1010 1100 .... 1111 .... 1010 .... @rndm +CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm +CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm +CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm + # Branches and miscellaneous control %msr_sysm 4:1 8:4 From patchwork Wed Sep 4 19:30:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172977 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp362498ilq; Wed, 4 Sep 2019 12:45:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqzWgvl6PjExQL/vdKuBSFj7Bx6cxSWrd/F9ErX80fq7KAyXhQV2QJUUOtoMcwVEtybyqkoA X-Received: by 2002:a50:884c:: with SMTP id c12mr31840643edc.134.1567626327779; Wed, 04 Sep 2019 12:45:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567626327; cv=none; d=google.com; s=arc-20160816; b=KSz/bKwiBkdHfFF3fEDPLYiRK/9o+msH0DTImogJCklSp9NTPcqDbsr3vlzO7MQtGn GoIOyKMIGnN5reI0IIabj/HloKjdMDpBJ4o4QGVfIott+fUK/7VaOuMbYr0ci2Qr/J9B ubD/VOl2cpdIKOKsoRRwJpM9CB/Ygsrywa76k9SSJoOhoZliN16F3ufewVZWNraLZOyv l0vSFQ8/HSRD/iAXZhxU1LRkMWvAMFfPzigXmQsGV9FeJSdrrBJy5T8T1/9/U8W1RvyW kDd/5+0wdGNd29d0JGZPL19svnEixElZLyw4yPackfRb2xYO/CY3D21YivgWZsvPXThi KHUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=DQ2Al2ZzVVcL195LoX3T2MlUUfcTCEsrN0xAjDQ6QOs=; b=YV1Ifo6bBTsf4dnAPeeyvfyNHA9ADT27btaVx4A+uhFXaKROZ8ucN+1T3vL7wT83fb nEg5QI6fi7WxAn2iuReXLKCKlY3xEUBpyAVPbncZUayUO9Kqc4SPWoinFOYJzNFK8OMG nRxO5/CuksiZXSmRVci5Sb+LrawYJaK3gsFJecMmnwMXNb9rBIOuNwc6pripsnEnlNKJ zbmN9QvcimECtg10NXfcGoThQeAOITvzHE65ByzPV76exQ9/Zzi3fmH7SK2m92QFXQef IXVysn+asmPn5uxqis68SPNCQYvjRdG68WFQtYklpvjmqW4pc6c3wdGlsio1u2n0ja7N hYZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rzQPC7qk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:05 -0700 Message-Id: <20190904193059.26202-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::530 Subject: [Qemu-devel] [PATCH v4 15/69] target/arm: Convert BX, BXJ, BLX (register) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 78 ++++++++++++++++++++---------------------- target/arm/a32.decode | 7 ++++ target/arm/t32.decode | 2 ++ 3 files changed, 47 insertions(+), 40 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 9d3f31f569..386a460bf5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8458,6 +8458,38 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) return true; } +static bool trans_BX(DisasContext *s, arg_BX *a) +{ + if (!ENABLE_ARCH_4T) { + return false; + } + gen_bx(s, load_reg(s, a->rm)); + return true; +} + +static bool trans_BXJ(DisasContext *s, arg_BXJ *a) +{ + if (!ENABLE_ARCH_5J || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + /* Trivial implementation equivalent to bx. */ + gen_bx(s, load_reg(s, a->rm)); + return true; +} + +static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_5) { + return false; + } + tmp = load_reg(s, a->rm); + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_bx(s, tmp); + return true; +} + /* * Legacy decoder. */ @@ -8747,12 +8779,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* All done in decodetree. Illegal ops already signalled. */ g_assert_not_reached(); case 0x1: - if (op1 == 1) { - /* branch/exchange thumb (bx). */ - ARCH(4T); - tmp = load_reg(s, rm); - gen_bx(s, tmp); - } else if (op1 == 3) { + if (op1 == 3) { /* clz */ ARCH(5); rd = (insn >> 12) & 0xf; @@ -8763,30 +8790,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) goto illegal_op; } break; - case 0x2: - if (op1 == 1) { - ARCH(5J); /* bxj */ - /* Trivial implementation equivalent to bx. */ - tmp = load_reg(s, rm); - gen_bx(s, tmp); - } else { - goto illegal_op; - } - break; - case 0x3: - if (op1 != 1) - goto illegal_op; - - ARCH(5); - /* branch link/exchange thumb (blx) */ - tmp = load_reg(s, rm); - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, s->base.pc_next); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - break; - case 0x4: - /* crc32 */ + case 0x2: /* bxj */ + case 0x3: /* blx */ + case 0x4: /* crc32 */ /* All done in decodetree. Illegal ops reach here. */ goto illegal_op; case 0x5: @@ -10620,16 +10626,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; } break; - case 4: /* bxj */ - /* Trivial implementation equivalent to bx. - * This instruction doesn't exist at all for M-profile. - */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - tmp = load_reg(s, rn); - gen_bx(s, tmp); - break; + case 4: /* bxj, in decodetree */ + goto illegal_op; case 5: /* Exception return. */ if (IS_USER(s)) { goto illegal_op; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index a8ef435b15..6cb9c16e2f 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -29,6 +29,7 @@ &s_rrrr s rd rn rm ra &rrrr rd rn rm ra &rrr rd rn rm +&r rm &msr_reg rn r mask &mrs_reg rd r &msr_bank rn r sysm @@ -195,8 +196,14 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm %sysm 8:1 16:4 +@rm ---- .... .... .... .... .... .... rm:4 &r + MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %sysm MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %sysm MRS_reg ---- 0001 0 r:1 00 1111 rd:4 0000 0000 0000 &mrs_reg MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg + +BX .... 0001 0010 1111 1111 1111 0001 .... @rm +BXJ .... 0001 0010 1111 1111 1111 0010 .... @rm +BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 261db100ff..337706ebbe 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -26,6 +26,7 @@ &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra &rrr !extern rd rn rm +&r !extern rm &msr_reg !extern rn r mask &mrs_reg !extern rd r &msr_bank !extern rn r sysm @@ -211,4 +212,5 @@ CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 } + BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r } From patchwork Wed Sep 4 19:30:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172982 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp367467ilq; Wed, 4 Sep 2019 12:50:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqx+b1t0Cx1j37a7P1rrN5R1Pcwoxe+vz8nKELoDWbldfDidF8PFi7cjrtFR8SNq314FcYAE X-Received: by 2002:a37:f518:: with SMTP id l24mr39547363qkk.54.1567626654683; Wed, 04 Sep 2019 12:50:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567626654; cv=none; d=google.com; s=arc-20160816; b=iku1x+eYv7IknE6Y21LQzqRgCy/HZqVDFFhOhGqxk0Cwu/+D60pckr9pkjUKVafzOJ n5hU4Gy04NN3r6EsreY2khZYJ0gFqHjBv/cCLF7uXPldGi1dEe+/zenJzO5y8CutzLrW bL9iosKriwWDPNE8XaS1eAUEXrjyBs8LmXmhd7unQJFF1+yOVjCs6mVPrbjTFOj4o4Eq E0cRJ5Skq38AoU81TJ6hdJ2mfak0bCjpRpCXFvo5K46UUTYTplGF4ApdwdxQNTjft9Ja L6ubabO0x4GRQoTSuC+W0Y4ABzy80tcPIn+rK8Fi4IcmwsH4a28nHGLBYe6dAd2m+C+x WcCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=gVoXo3oBV5rjG7odbH2AUIPExjRoZyxfBk+LHOtrM+4=; b=bgrx2BxubW/WwOgY0vAnbTrLKxizC0LW/j7y8D219FTGurZWe1FchppYFmIAywxWrq EABzaC6hyFLjBVEC8fyKFHAAAETYIaaZ0CDgZhQXfeuYPRWC5Pz1Wx/bERjTvZBU95sD RtzARMX2VNYgYbYMZNrP/4TlSzzZfqRvu6Uo+dxSnNh65tJ0zxgMAY/joFLckOL/mM0U BnVhBDtmw2ldhRNE3n33t4RDtoN6+5peg7QWvXVaY2D43um8Y5z1+Lor1YGprBITw8qm SLy1nrVw6zDI/SFPHLsxhoUGyuGi1Bt2TdCvvw92NKInqEYQZbTDrf+RTJSMfHvqM/0b rOvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Vwo8qtj1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:06 -0700 Message-Id: <20190904193059.26202-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v4 16/69] target/arm: Convert CLZ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Document our choice about the T32 CONSTRAINED UNPREDICTABLE behaviour. This matches the undocumented choice made by the legacy decoder. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 31 +++++++++++++++---------------- target/arm/a32.decode | 4 ++++ target/arm/t32.decode | 5 +++++ 3 files changed, 24 insertions(+), 16 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 386a460bf5..7de6949db3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8490,6 +8490,19 @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a) return true; } +static bool trans_CLZ(DisasContext *s, arg_CLZ *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_5) { + return false; + } + tmp = load_reg(s, a->rm); + tcg_gen_clzi_i32(tmp, tmp, 32); + store_reg(s, a->rd, tmp); + return true; +} + /* * Legacy decoder. */ @@ -8778,18 +8791,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* MSR/MRS (banked/register) */ /* All done in decodetree. Illegal ops already signalled. */ g_assert_not_reached(); - case 0x1: - if (op1 == 3) { - /* clz */ - ARCH(5); - rd = (insn >> 12) & 0xf; - tmp = load_reg(s, rm); - tcg_gen_clzi_i32(tmp, tmp, 32); - store_reg(s, rd, tmp); - } else { - goto illegal_op; - } - break; + case 0x1: /* bx, clz */ case 0x2: /* bxj */ case 0x3: /* blx */ case 0x4: /* crc32 */ @@ -10236,13 +10238,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 0x08: /* rev */ case 0x09: /* rev16 */ case 0x0b: /* revsh */ - case 0x18: /* clz */ break; case 0x10: /* sel */ if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { goto illegal_op; } break; + case 0x18: /* clz, in decodetree */ case 0x20: /* crc32/crc32c, in decodetree */ case 0x21: case 0x22: @@ -10275,9 +10277,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(tmp3); tcg_temp_free_i32(tmp2); break; - case 0x18: /* clz */ - tcg_gen_clzi_i32(tmp, tmp, 32); - break; default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 6cb9c16e2f..182f2b6725 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -29,6 +29,7 @@ &s_rrrr s rd rn rm ra &rrrr rd rn rm ra &rrr rd rn rm +&rr rd rm &r rm &msr_reg rn r mask &mrs_reg rd r @@ -197,6 +198,7 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm %sysm 8:1 16:4 @rm ---- .... .... .... .... .... .... rm:4 &r +@rdm ---- .... .... .... rd:4 .... .... rm:4 &rr MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %sysm MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %sysm @@ -207,3 +209,5 @@ MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg BX .... 0001 0010 1111 1111 1111 0001 .... @rm BXJ .... 0001 0010 1111 1111 1111 0010 .... @rm BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm + +CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 337706ebbe..67724efe4b 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -26,6 +26,7 @@ &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra &rrr !extern rd rn rm +&rr !extern rd rm &r !extern rm &msr_reg !extern rn r mask &mrs_reg !extern rd r @@ -126,6 +127,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr @rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &rrrr ra=0 @rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr +@rdm .... .... .... .... .... rd:4 .... rm:4 &rr { MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm @@ -180,6 +182,9 @@ CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm +# Note rn != rm is CONSTRAINED UNPREDICTABLE; we choose to ignore rn. +CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm + # Branches and miscellaneous control %msr_sysm 4:1 8:4 From patchwork Wed Sep 4 19:30:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172971 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp359603ilq; Wed, 4 Sep 2019 12:41:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqy5woKWuFwOteOPRvO6dIe5JtvBzUmFOtcd64FAaRXY0f+KIvXGDdBqpUYP1FkpadYf2aDk X-Received: by 2002:aa7:d755:: with SMTP id a21mr389014eds.18.1567626113052; Wed, 04 Sep 2019 12:41:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567626113; cv=none; d=google.com; s=arc-20160816; b=azUKJXPNCSZwSqAwpA6l+hllrewYbUkqSUl9iK7ETICGdXdritJ5TYXikVtP8dsBxH H612D5W/0Z0osP3P287j3de79basKfrdrOjTr8oC0hIbxVRjLVonr0fReAu2dWoB2Pai 72mczhsS8CY3Zwor9+ldEV/Q7WyIhXSeK29cpYtML62ex6nWwdbc+Xk8VKbSjmZzyhrM bhe9w3cuBCN4kAMYICMBq8YsTbqpui/PE21ACyUPVL+fXDsRErmpxENR59NhCKvaXDRG 58S5PO4yX8yWhirFklKdS1WakMBJDFHUcRv++pcorpxPvWr+G49VSQmrCDKITvQATvsv VRWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Br2b0vbKeN/2j/h9uyRFZAyuwQitptP6m+++156fwxo=; b=aDChMYb6zVqOUQjuSUgr7DE5i9vZDo9v3SScjYAAqKu2Qcg6GASSoOm8n+xM+RW2w/ x7ghZL5cp6sW72Qu2Qw5p+fWhb0elBnfRg/0t+4bd60qpg4OkRyhPUcoFOALDFNEMicO moZm3EREGs3xuCUU7Vwj8lq45wE595XdAIzMgrc3kohYbx7SfmJKapPOHEKV5jfOCGgK UC0zK3/bXf7zVC967jl+L1HAU2AjuGhfpCieNT/VZh3YR3CzdpiZUOb1A83o0SJiDa/D BdIM/7cS2VEEmZX48yDWkh0btGGU0OTBFoAJAyYZlgZ0CAit0n/lxi2WqIEzgaENLBbJ 1FLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dFs7DNhz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:07 -0700 Message-Id: <20190904193059.26202-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 17/69] target/arm: Convert ERET X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Pass the T5 encoding of SUBS PC, LR, #IMM through the normal SUBS path to make it clear exactly what's happening -- we hit ALUExceptionReturn along that path. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use unallocated_encoding for IS_USER check. --- target/arm/translate.c | 62 ++++++++++++++++-------------------------- target/arm/a32.decode | 2 ++ target/arm/t32.decode | 8 ++++++ 3 files changed, 33 insertions(+), 39 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 7de6949db3..9589e9bbb9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8503,6 +8503,27 @@ static bool trans_CLZ(DisasContext *s, arg_CLZ *a) return true; } +static bool trans_ERET(DisasContext *s, arg_ERET *a) +{ + TCGv_i32 tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) { + return false; + } + if (IS_USER(s)) { + unallocated_encoding(s); + return true; + } + if (s->current_el == 2) { + /* ERET from Hyp uses ELR_Hyp, not LR */ + tmp = load_cpu_field(elr_el[2]); + } else { + tmp = load_reg(s, 14); + } + gen_exception_return(s, tmp); + return true; +} + /* * Legacy decoder. */ @@ -8797,29 +8818,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) case 0x4: /* crc32 */ /* All done in decodetree. Illegal ops reach here. */ goto illegal_op; - case 0x5: - /* Saturating addition and subtraction. */ + case 0x5: /* Saturating addition and subtraction. */ + case 0x6: /* ERET */ /* All done in decodetree. Reach here for illegal ops. */ goto illegal_op; - case 0x6: /* ERET */ - if (op1 != 3) { - goto illegal_op; - } - if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) { - goto illegal_op; - } - if ((insn & 0x000fff0f) != 0x0000000e) { - /* UNPREDICTABLE; we choose to UNDEF */ - goto illegal_op; - } - - if (s->current_el == 2) { - tmp = load_cpu_field(elr_el[2]); - } else { - tmp = load_reg(s, 14); - } - gen_exception_return(s, tmp); - break; case 7: { int imm16 = extract32(insn, 0, 4) | (extract32(insn, 8, 12) << 4); @@ -10628,24 +10630,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 4: /* bxj, in decodetree */ goto illegal_op; case 5: /* Exception return. */ - if (IS_USER(s)) { - goto illegal_op; - } - if (rn != 14 || rd != 15) { - goto illegal_op; - } - if (s->current_el == 2) { - /* ERET from Hyp uses ELR_Hyp, not LR */ - if (insn & 0xff) { - goto illegal_op; - } - tmp = load_cpu_field(elr_el[2]); - } else { - tmp = load_reg(s, rn); - tcg_gen_subi_i32(tmp, tmp, insn & 0xff); - } - gen_exception_return(s, tmp); - break; case 6: /* MRS, in decodetree */ case 7: /* MSR, in decodetree */ goto illegal_op; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 182f2b6725..52a66dd1d5 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -211,3 +211,5 @@ BXJ .... 0001 0010 1111 1111 1111 0010 .... @rm BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm + +ERET ---- 0001 0110 0000 0000 0000 0110 1110 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 67724efe4b..6236d28b99 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -218,4 +218,12 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 } BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r + { + # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as for + # every other encoding of SUBS. With v7VE, IMM=0 is redefined as ERET. + # The distinction between the two only matters for Hyp mode. + ERET 1111 0011 1101 1110 1000 1111 0000 0000 + SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ + &s_rri_rot rot=0 s=1 rd=15 rn=14 + } } From patchwork Wed Sep 4 19:30:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172986 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp370130ilq; Wed, 4 Sep 2019 12:54:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqz26SPXIj9VI0ds5VbqLc3N+xNOooD0Uhd7CFKtGxpOsuBGx76+pkI9y4W+DVQvShUKGq07 X-Received: by 2002:a05:6402:13cb:: with SMTP id a11mr16144779edx.161.1567626851377; Wed, 04 Sep 2019 12:54:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567626851; cv=none; d=google.com; s=arc-20160816; b=XhgEa5HQtLC6jyNGo8nXBFck9Q650uX8hbEt19hBZLDEdQrO92o1Bn93rALRflj8uA aQSH42JIvLrhW66m3cQfUc6PqSNBhAFaGtEP7iMI23ILCTS1DUVZi9g3/jaqA0qD6NlA 5NSgAxrKvV/QcHoXXhT800ieIcMRW2fBbzzo9boXw+yScZ+Kq7y8Jk3Ryrs/PglvfKjm TV9EZEROFq+TMOT+JzrWDGlsloDr3Eg95Eg7JgblVdiCJ+Ddq7pPzmeytTQnJcS+VIsK zefrYFnTS65RJZsdI+Qv4VCJbsyFsfaUAdWa1XqOWJniLx3s+7x7xw4xNBnqTy6PDvwj ZIwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=kFutySvY3dUNUb39wtRAtuDmuWFVewtZdUowhmVNFME=; b=xSdnvlpMiC8chbc+Su9SJ20+wmWnByryEFmmyvUKStTJ1ExO0emrOdMd0I5afhrJ1d NYdO4s4bp0Nn5LVDLvYCfmvdVfCOW9igq1aWAKR6EGe0eFdCo0d7G3/nHCVYKfA4dbz+ pzQrhxtr3f2QL+FvT1y2zdOtMW9Ujqb8y6OZ7hHi2b3fjDoIL4fa6Mi7pAv+XgfqNcfT k6FwYexd+Xptyybo2TxtrN9hRtWbcW3HhCgoVBlCVjLV7iB4mAO7Epr7CRY6UoaceuGg J6RfFa2WrryCaJaQTrk5f1sPFgW6wa8KtTj4UEh//zpbj83l0bKcX3J9lxv2WKc6Rs1C D9Vw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=h0I4AGCh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:08 -0700 Message-Id: <20190904193059.26202-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v4 18/69] target/arm: Convert the rest of A32 Miscelaneous instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Call unallocated_encoding for IS_USER. --- target/arm/translate.c | 127 +++++++++++++++-------------------------- target/arm/a32.decode | 8 +++ target/arm/t32.decode | 5 ++ 3 files changed, 58 insertions(+), 82 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 9589e9bbb9..750331071b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8524,6 +8524,47 @@ static bool trans_ERET(DisasContext *s, arg_ERET *a) return true; } +static bool trans_HLT(DisasContext *s, arg_HLT *a) +{ + gen_hlt(s, a->imm); + return true; +} + +static bool trans_BKPT(DisasContext *s, arg_BKPT *a) +{ + if (!ENABLE_ARCH_5) { + return false; + } + gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); + return true; +} + +static bool trans_HVC(DisasContext *s, arg_HVC *a) +{ + if (!ENABLE_ARCH_7 || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (IS_USER(s)) { + unallocated_encoding(s); + } else { + gen_hvc(s, a->imm); + } + return true; +} + +static bool trans_SMC(DisasContext *s, arg_SMC *a) +{ + if (!ENABLE_ARCH_6K || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (IS_USER(s)) { + unallocated_encoding(s); + } else { + gen_smc(s); + } + return true; +} + /* * Legacy decoder. */ @@ -8804,68 +8845,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } else if ((insn & 0x0f900000) == 0x01000000 && (insn & 0x00000090) != 0x00000090) { /* miscellaneous instructions */ - op1 = (insn >> 21) & 3; - sh = (insn >> 4) & 0xf; - rm = insn & 0xf; - switch (sh) { - case 0x0: - /* MSR/MRS (banked/register) */ - /* All done in decodetree. Illegal ops already signalled. */ - g_assert_not_reached(); - case 0x1: /* bx, clz */ - case 0x2: /* bxj */ - case 0x3: /* blx */ - case 0x4: /* crc32 */ - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - case 0x5: /* Saturating addition and subtraction. */ - case 0x6: /* ERET */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - case 7: - { - int imm16 = extract32(insn, 0, 4) | (extract32(insn, 8, 12) << 4); - switch (op1) { - case 0: - /* HLT */ - gen_hlt(s, imm16); - break; - case 1: - /* bkpt */ - ARCH(5); - gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm16, false)); - break; - case 2: - /* Hypervisor call (v7) */ - ARCH(7); - if (IS_USER(s)) { - goto illegal_op; - } - gen_hvc(s, imm16); - break; - case 3: - /* Secure monitor call (v6+) */ - ARCH(6K); - if (IS_USER(s)) { - goto illegal_op; - } - gen_smc(s); - break; - default: - g_assert_not_reached(); - } - break; - } - case 0x8: - case 0xa: - case 0xc: - case 0xe: - /* Halfword multiply and multiply accumulate. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - default: - goto illegal_op; - } + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; } else if (((insn & 0x0e000000) == 0 && (insn & 0x00000090) != 0x90) || ((insn & 0x0e000000) == (1 << 25))) { @@ -10539,26 +10520,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; if (insn & (1 << 26)) { - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - if (!(insn & (1 << 20))) { - /* Hypervisor call (v7) */ - int imm16 = extract32(insn, 16, 4) << 12 - | extract32(insn, 0, 12); - ARCH(7); - if (IS_USER(s)) { - goto illegal_op; - } - gen_hvc(s, imm16); - } else { - /* Secure monitor call (v6+) */ - ARCH(6K); - if (IS_USER(s)) { - goto illegal_op; - } - gen_smc(s); - } + /* hvc, smc, in decodetree */ + goto illegal_op; } else { op = (insn >> 20) & 7; switch (op) { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 52a66dd1d5..c7f156be6d 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -31,6 +31,7 @@ &rrr rd rn rm &rr rd rm &r rm +&i imm &msr_reg rn r mask &mrs_reg rd r &msr_bank rn r sysm @@ -196,9 +197,11 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm # Miscellaneous instructions %sysm 8:1 16:4 +%imm16_8_0 8:12 0:4 @rm ---- .... .... .... .... .... .... rm:4 &r @rdm ---- .... .... .... rd:4 .... .... rm:4 &rr +@i16 ---- .... .... .... .... .... .... .... &i imm=%imm16_8_0 MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %sysm MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %sysm @@ -213,3 +216,8 @@ BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm ERET ---- 0001 0110 0000 0000 0000 0110 1110 + +HLT .... 0001 0000 .... .... .... 0111 .... @i16 +BKPT .... 0001 0010 .... .... .... 0111 .... @i16 +HVC .... 0001 0100 .... .... .... 0111 .... @i16 +SMC ---- 0001 0110 0000 0000 0000 0111 imm:4 &i diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 6236d28b99..5116c6165a 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -28,6 +28,7 @@ &rrr !extern rd rn rm &rr !extern rd rm &r !extern rm +&i !extern imm &msr_reg !extern rn r mask &mrs_reg !extern rd r &msr_bank !extern rn r sysm @@ -189,6 +190,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm %msr_sysm 4:1 8:4 %mrs_sysm 4:1 16:4 +%imm16_16_0 16:4 0:12 { { @@ -226,4 +228,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ &s_rri_rot rot=0 s=1 rd=15 rn=14 } + SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i + HVC 1111 0111 1110 .... 1000 .... .... .... \ + &i imm=%imm16_16_0 } From patchwork Wed Sep 4 19:30:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172989 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp372025ilq; Wed, 4 Sep 2019 12:56:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqyJCGZNuZqqGpwUyt+eDZsl06tNB3OdeobWd3oZ8M6XhqXn4aTeXG3NXbDCA+xPu9S5X6Yg X-Received: by 2002:a50:fb0c:: with SMTP id d12mr21040112edq.275.1567627000594; Wed, 04 Sep 2019 12:56:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567627000; cv=none; d=google.com; s=arc-20160816; b=zvhexxqiVfpZHmGKw5PXOMur39imQU+rbaUlBghuV3Ja6Odu+CSHMAvVDQ9gmIHtc7 C6p2BWyzaWDzAHOyu9fp8mocwm3DMcuwLJBA0pReFP4LFBKcrd+v7voC78ZT3ISgvXTD JFqXjKpG6287eNKCR5ivmq446gbpGdl5LyJ+DmHYrzHcox+ApDYL3KIPZpKmDPI8tzf1 pAnTeUJ/gfQO4ZCJ79HhDLpTellE8b9CF4LYFVtM24omMSay1taMlo+kHjG/VuJQSMVH r1bfM42l2WCd6xEXeZC2Et3f96rqWEDCFQx/GKJS1aox3UORcSlJsXhYeI3ub5oCqQ3U AOGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=VBWptZwV41wrybglM+V4M0H5NWdfiBjh3fvGH/I8Il8=; b=kju9x+hniwGkr8WNJG+Q8dv9yUOClBKnP3MtMENU2Rsp4kBCt+ltqkjaGyUUG/Jb7u iFNcy3aUCQnfRli7vJUqikN3RaXXk8SFIr8vQlHavuzFlrGz1iqsCi8FUTKErAvJR7wZ B8YzIbIaVp9lg+CZXWsDiIOVwngGvo80JGA+fYvr+QuxDMmFfCSqEdVnkAmN1RVqLzES 1VeezY6fw6XPA0snMBFpTLy/lhHLbapSs9d707yE9WXwlNE8WwX2MMRFwdF/AdbGU572 g5YqcUi19bSCrPzPt8r4IOx4k2t50Qq2f60V72fGoew7giqnZG0m1sdftEed71Slhf24 nn+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=lCJWSj6F; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 19/69] target/arm: Convert T32 ADDW/SUBW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 24 +++++++++++++----------- target/arm/a32.decode | 1 + target/arm/t32.decode | 19 +++++++++++++++++++ 3 files changed, 33 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 750331071b..7d12be4025 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7648,6 +7648,11 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond) * Constant expanders for the decoders. */ +static int negate(DisasContext *s, int x) +{ + return -x; +} + static int times_2(DisasContext *s, int x) { return x * 2; @@ -8004,6 +8009,12 @@ static bool trans_ORN_rri(DisasContext *s, arg_s_rri_rot *a) #undef DO_ANY2 #undef DO_CMP2 +static bool trans_ADR(DisasContext *s, arg_ri *a) +{ + store_reg_bx(s, a->rd, add_reg_for_lit(s, 15, a->imm)); + return true; +} + /* * Multiply and multiply accumulate */ @@ -10724,17 +10735,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } store_reg(s, rd, tmp); } else { - /* Add/sub 12-bit immediate. */ - if (insn & (1 << 23)) { - imm = -imm; - } - tmp = add_reg_for_lit(s, rn, imm); - if (rn == 13 && rd == 13) { - /* ADD SP, SP, imm or SUB SP, SP, imm */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } + /* Add/sub 12-bit immediate, in decodetree */ + goto illegal_op; } } } else { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index c7f156be6d..aac991664d 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -30,6 +30,7 @@ &rrrr rd rn rm ra &rrr rd rn rm &rr rd rm +&ri rd imm &r rm &i imm &msr_reg rn r mask diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 5116c6165a..be4e5f087c 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -27,6 +27,7 @@ &rrrr !extern rd rn rm ra &rrr !extern rd rn rm &rr !extern rd rm +&ri !extern rd imm &r !extern rm &i !extern imm &msr_reg !extern rn r mask @@ -121,6 +122,24 @@ SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot } RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot +# Data processing (plain binary immediate) + +%imm12_26_12_0 26:1 12:3 0:8 +%neg12_26_12_0 26:1 12:3 0:8 !function=negate +@s0_rri_12 .... ... .... . rn:4 . ... rd:4 ........ \ + &s_rri_rot imm=%imm12_26_12_0 rot=0 s=0 + +{ + ADR 1111 0.1 0000 0 1111 0 ... rd:4 ........ \ + &ri imm=%imm12_26_12_0 + ADD_rri 1111 0.1 0000 0 .... 0 ... .... ........ @s0_rri_12 +} +{ + ADR 1111 0.1 0101 0 1111 0 ... rd:4 ........ \ + &ri imm=%neg12_26_12_0 + SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12 +} + # Multiply and multiply accumulate @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0 From patchwork Wed Sep 4 19:30:10 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:10 -0700 Message-Id: <20190904193059.26202-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v4 20/69] target/arm: Convert load/store (register, immediate, literal) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use unallocated_encoding for RT odd --- target/arm/translate.c | 805 ++++++++++++++++++----------------------- target/arm/a32.decode | 120 ++++++ target/arm/t32.decode | 141 ++++++++ 3 files changed, 623 insertions(+), 443 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 7d12be4025..d383a16f4b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1265,62 +1265,6 @@ static inline void gen_hlt(DisasContext *s, int imm) unallocated_encoding(s); } -static inline void gen_add_data_offset(DisasContext *s, unsigned int insn, - TCGv_i32 var) -{ - int val, rm, shift, shiftop; - TCGv_i32 offset; - - if (!(insn & (1 << 25))) { - /* immediate */ - val = insn & 0xfff; - if (!(insn & (1 << 23))) - val = -val; - if (val != 0) - tcg_gen_addi_i32(var, var, val); - } else { - /* shift/register */ - rm = (insn) & 0xf; - shift = (insn >> 7) & 0x1f; - shiftop = (insn >> 5) & 3; - offset = load_reg(s, rm); - gen_arm_shift_im(offset, shiftop, shift, 0); - if (!(insn & (1 << 23))) - tcg_gen_sub_i32(var, var, offset); - else - tcg_gen_add_i32(var, var, offset); - tcg_temp_free_i32(offset); - } -} - -static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn, - int extra, TCGv_i32 var) -{ - int val, rm; - TCGv_i32 offset; - - if (insn & (1 << 22)) { - /* immediate */ - val = (insn & 0xf) | ((insn >> 4) & 0xf0); - if (!(insn & (1 << 23))) - val = -val; - val += extra; - if (val != 0) - tcg_gen_addi_i32(var, var, val); - } else { - /* register */ - if (extra) - tcg_gen_addi_i32(var, var, extra); - rm = (insn) & 0xf; - offset = load_reg(s, rm); - if (!(insn & (1 << 23))) - tcg_gen_sub_i32(var, var, offset); - else - tcg_gen_add_i32(var, var, offset); - tcg_temp_free_i32(offset); - } -} - static TCGv_ptr get_fpstatus_ptr(int neon) { TCGv_ptr statusptr = tcg_temp_new_ptr(); @@ -7658,6 +7602,11 @@ static int times_2(DisasContext *s, int x) return x * 2; } +static int times_4(DisasContext *s, int x) +{ + return x * 4; +} + /* Return only the rotation part of T32ExpandImm. */ static int t32_expandimm_rot(DisasContext *s, int x) { @@ -8576,6 +8525,353 @@ static bool trans_SMC(DisasContext *s, arg_SMC *a) return true; } +/* + * Load/store register index + */ + +static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w) +{ + ISSInfo ret; + + /* ISS not valid if writeback */ + if (p && !w) { + ret = rd; + } else { + ret = ISSInvalid; + } + return ret; +} + +static TCGv_i32 op_addr_rr_pre(DisasContext *s, arg_ldst_rr *a) +{ + TCGv_i32 addr = load_reg(s, a->rn); + + if (s->v8m_stackcheck && a->rn == 13 && a->w) { + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + if (a->p) { + TCGv_i32 ofs = load_reg(s, a->rm); + gen_arm_shift_im(ofs, a->shtype, a->shimm, 0); + if (a->u) { + tcg_gen_add_i32(addr, addr, ofs); + } else { + tcg_gen_sub_i32(addr, addr, ofs); + } + tcg_temp_free_i32(ofs); + } + return addr; +} + +static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a, + TCGv_i32 addr, int address_offset) +{ + if (!a->p) { + TCGv_i32 ofs = load_reg(s, a->rm); + gen_arm_shift_im(ofs, a->shtype, a->shimm, 0); + if (a->u) { + tcg_gen_add_i32(addr, addr, ofs); + } else { + tcg_gen_sub_i32(addr, addr, ofs); + } + tcg_temp_free_i32(ofs); + } else if (!a->w) { + tcg_temp_free_i32(addr); + return; + } + tcg_gen_addi_i32(addr, addr, address_offset); + store_reg(s, a->rn, addr); +} + +static bool op_load_rr(DisasContext *s, arg_ldst_rr *a, + MemOp mop, int mem_idx) +{ + ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w); + TCGv_i32 addr, tmp; + + addr = op_addr_rr_pre(s, a); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + + /* + * Perform base writeback before the loaded value to + * ensure correct behavior with overlapping index registers. + */ + op_addr_rr_post(s, a, addr, 0); + store_reg_from_load(s, a->rt, tmp); + return true; +} + +static bool op_store_rr(DisasContext *s, arg_ldst_rr *a, + MemOp mop, int mem_idx) +{ + ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite; + TCGv_i32 addr, tmp; + + addr = op_addr_rr_pre(s, a); + + tmp = load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + tcg_temp_free_i32(tmp); + + op_addr_rr_post(s, a, addr, 0); + return true; +} + +static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) +{ + int mem_idx = get_mem_index(s); + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_5TE) { + return false; + } + if (a->rt & 1) { + unallocated_encoding(s); + return true; + } + addr = op_addr_rr_pre(s, a); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, a->rt, tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, a->rt + 1, tmp); + + /* LDRD w/ base writeback is undefined if the registers overlap. */ + op_addr_rr_post(s, a, addr, -4); + return true; +} + +static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a) +{ + int mem_idx = get_mem_index(s); + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_5TE) { + return false; + } + if (a->rt & 1) { + unallocated_encoding(s); + return true; + } + addr = op_addr_rr_pre(s, a); + + tmp = load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp = load_reg(s, a->rt + 1); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + op_addr_rr_post(s, a, addr, -4); + return true; +} + +/* + * Load/store immediate index + */ + +static TCGv_i32 op_addr_ri_pre(DisasContext *s, arg_ldst_ri *a) +{ + int ofs = a->imm; + + if (!a->u) { + ofs = -ofs; + } + + if (s->v8m_stackcheck && a->rn == 13 && a->w) { + /* + * Stackcheck. Here we know 'addr' is the current SP; + * U is set if we're moving SP up, else down. It is + * UNKNOWN whether the limit check triggers when SP starts + * below the limit and ends up above it; we chose to do so. + */ + if (!a->u) { + TCGv_i32 newsp = tcg_temp_new_i32(); + tcg_gen_addi_i32(newsp, cpu_R[13], ofs); + gen_helper_v8m_stackcheck(cpu_env, newsp); + tcg_temp_free_i32(newsp); + } else { + gen_helper_v8m_stackcheck(cpu_env, cpu_R[13]); + } + } + + return add_reg_for_lit(s, a->rn, a->p ? ofs : 0); +} + +static void op_addr_ri_post(DisasContext *s, arg_ldst_ri *a, + TCGv_i32 addr, int address_offset) +{ + if (!a->p) { + if (a->u) { + address_offset += a->imm; + } else { + address_offset -= a->imm; + } + } else if (!a->w) { + tcg_temp_free_i32(addr); + return; + } + tcg_gen_addi_i32(addr, addr, address_offset); + store_reg(s, a->rn, addr); +} + +static bool op_load_ri(DisasContext *s, arg_ldst_ri *a, + MemOp mop, int mem_idx) +{ + ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w); + TCGv_i32 addr, tmp; + + addr = op_addr_ri_pre(s, a); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + + /* + * Perform base writeback before the loaded value to + * ensure correct behavior with overlapping index registers. + */ + op_addr_ri_post(s, a, addr, 0); + store_reg_from_load(s, a->rt, tmp); + return true; +} + +static bool op_store_ri(DisasContext *s, arg_ldst_ri *a, + MemOp mop, int mem_idx) +{ + ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite; + TCGv_i32 addr, tmp; + + addr = op_addr_ri_pre(s, a); + + tmp = load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + tcg_temp_free_i32(tmp); + + op_addr_ri_post(s, a, addr, 0); + return true; +} + +static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) +{ + int mem_idx = get_mem_index(s); + TCGv_i32 addr, tmp; + + addr = op_addr_ri_pre(s, a); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, a->rt, tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, rt2, tmp); + + /* LDRD w/ base writeback is undefined if the registers overlap. */ + op_addr_ri_post(s, a, addr, -4); + return true; +} + +static bool trans_LDRD_ri_a32(DisasContext *s, arg_ldst_ri *a) +{ + if (!ENABLE_ARCH_5TE || (a->rt & 1)) { + return false; + } + return op_ldrd_ri(s, a, a->rt + 1); +} + +static bool trans_LDRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a) +{ + arg_ldst_ri b = { + .u = a->u, .w = a->w, .p = a->p, + .rn = a->rn, .rt = a->rt, .imm = a->imm + }; + return op_ldrd_ri(s, &b, a->rt2); +} + +static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) +{ + int mem_idx = get_mem_index(s); + TCGv_i32 addr, tmp; + + addr = op_addr_ri_pre(s, a); + + tmp = load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp = load_reg(s, rt2); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + op_addr_ri_post(s, a, addr, -4); + return true; +} + +static bool trans_STRD_ri_a32(DisasContext *s, arg_ldst_ri *a) +{ + if (!ENABLE_ARCH_5TE || (a->rt & 1)) { + return false; + } + return op_strd_ri(s, a, a->rt + 1); +} + +static bool trans_STRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a) +{ + arg_ldst_ri b = { + .u = a->u, .w = a->w, .p = a->p, + .rn = a->rn, .rt = a->rt, .imm = a->imm + }; + return op_strd_ri(s, &b, a->rt2); +} + +#define DO_LDST(NAME, WHICH, MEMOP) \ +static bool trans_##NAME##_ri(DisasContext *s, arg_ldst_ri *a) \ +{ \ + return op_##WHICH##_ri(s, a, MEMOP, get_mem_index(s)); \ +} \ +static bool trans_##NAME##T_ri(DisasContext *s, arg_ldst_ri *a) \ +{ \ + return op_##WHICH##_ri(s, a, MEMOP, get_a32_user_mem_index(s)); \ +} \ +static bool trans_##NAME##_rr(DisasContext *s, arg_ldst_rr *a) \ +{ \ + return op_##WHICH##_rr(s, a, MEMOP, get_mem_index(s)); \ +} \ +static bool trans_##NAME##T_rr(DisasContext *s, arg_ldst_rr *a) \ +{ \ + return op_##WHICH##_rr(s, a, MEMOP, get_a32_user_mem_index(s)); \ +} + +DO_LDST(LDR, load, MO_UL) +DO_LDST(LDRB, load, MO_UB) +DO_LDST(LDRH, load, MO_UW) +DO_LDST(LDRSB, load, MO_SB) +DO_LDST(LDRSH, load, MO_SW) + +DO_LDST(STR, store, MO_UL) +DO_LDST(STRB, store, MO_UB) +DO_LDST(STRH, store, MO_UW) + +#undef DO_LDST + /* * Legacy decoder. */ @@ -9033,100 +9329,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } } } else { - int address_offset; - bool load = insn & (1 << 20); - bool wbit = insn & (1 << 21); - bool pbit = insn & (1 << 24); - bool doubleword = false; - ISSInfo issinfo; - - /* Misc load/store */ - rn = (insn >> 16) & 0xf; - rd = (insn >> 12) & 0xf; - - /* ISS not valid if writeback */ - issinfo = (pbit & !wbit) ? rd : ISSInvalid; - - if (!load && (sh & 2)) { - /* doubleword */ - ARCH(5TE); - if (rd & 1) { - /* UNPREDICTABLE; we choose to UNDEF */ - goto illegal_op; - } - load = (sh & 1) == 0; - doubleword = true; - } - - addr = load_reg(s, rn); - if (pbit) { - gen_add_datah_offset(s, insn, 0, addr); - } - address_offset = 0; - - if (doubleword) { - if (!load) { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp = load_reg(s, rd + 1); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } else { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - rd++; - } - address_offset = -4; - } else if (load) { - /* load */ - tmp = tcg_temp_new_i32(); - switch (sh) { - case 1: - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), - issinfo); - break; - case 2: - gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), - issinfo); - break; - default: - case 3: - gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), - issinfo); - break; - } - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), issinfo); - tcg_temp_free_i32(tmp); - } - /* Perform base writeback before the loaded value to - ensure correct behavior with overlapping index registers. - ldrd with base writeback is undefined if the - destination and index registers overlap. */ - if (!pbit) { - gen_add_datah_offset(s, insn, address_offset, addr); - store_reg(s, rn, addr); - } else if (wbit) { - if (address_offset) - tcg_gen_addi_i32(addr, addr, address_offset); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - if (load) { - /* Complete the load. */ - store_reg(s, rd, tmp); - } + /* Extra load/store (register) instructions */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } break; case 0x4: @@ -9443,58 +9648,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) break; } do_ldst: - /* Check for undefined extension instructions - * per the ARM Bible IE: - * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx - */ - sh = (0xf << 20) | (0xf << 4); - if (op1 == 0x7 && ((insn & sh) == sh)) - { - goto illegal_op; - } - /* load/store byte/word */ - rn = (insn >> 16) & 0xf; - rd = (insn >> 12) & 0xf; - tmp2 = load_reg(s, rn); - if ((insn & 0x01200000) == 0x00200000) { - /* ldrt/strt */ - i = get_a32_user_mem_index(s); - } else { - i = get_mem_index(s); - } - if (insn & (1 << 24)) - gen_add_data_offset(s, insn, tmp2); - if (insn & (1 << 20)) { - /* load */ - tmp = tcg_temp_new_i32(); - if (insn & (1 << 22)) { - gen_aa32_ld8u_iss(s, tmp, tmp2, i, rd); - } else { - gen_aa32_ld32u_iss(s, tmp, tmp2, i, rd); - } - } else { - /* store */ - tmp = load_reg(s, rd); - if (insn & (1 << 22)) { - gen_aa32_st8_iss(s, tmp, tmp2, i, rd); - } else { - gen_aa32_st32_iss(s, tmp, tmp2, i, rd); - } - tcg_temp_free_i32(tmp); - } - if (!(insn & (1 << 24))) { - gen_add_data_offset(s, insn, tmp2); - store_reg(s, rn, tmp2); - } else if (insn & (1 << 21)) { - store_reg(s, rn, tmp2); - } else { - tcg_temp_free_i32(tmp2); - } - if (insn & (1 << 20)) { - /* Complete the load. */ - store_reg_from_load(s, rd, tmp); - } - break; + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0x08: case 0x09: { @@ -9795,75 +9950,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) s->condexec_mask = 0; } } else if (insn & 0x01200000) { - /* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store dual (post-indexed) - * 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store dual (literal and immediate) - * 0b1111_1001_x11x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store dual (pre-indexed) - */ - bool wback = extract32(insn, 21, 1); - - if (rn == 15 && (insn & (1 << 21))) { - /* UNPREDICTABLE */ - goto illegal_op; - } - - addr = add_reg_for_lit(s, rn, 0); - offset = (insn & 0xff) * 4; - if ((insn & (1 << 23)) == 0) { - offset = -offset; - } - - if (s->v8m_stackcheck && rn == 13 && wback) { - /* - * Here 'addr' is the current SP; if offset is +ve we're - * moving SP up, else down. It is UNKNOWN whether the limit - * check triggers when SP starts below the limit and ends - * up above it; check whichever of the current and final - * SP is lower, so QEMU will trigger in that situation. - */ - if ((int32_t)offset < 0) { - TCGv_i32 newsp = tcg_temp_new_i32(); - - tcg_gen_addi_i32(newsp, addr, offset); - gen_helper_v8m_stackcheck(cpu_env, newsp); - tcg_temp_free_i32(newsp); - } else { - gen_helper_v8m_stackcheck(cpu_env, addr); - } - } - - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, offset); - offset = 0; - } - if (insn & (1 << 20)) { - /* ldrd */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rs, tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - } else { - /* strd */ - tmp = load_reg(s, rs); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp = load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - if (wback) { - /* Base writeback. */ - tcg_gen_addi_i32(addr, addr, offset - 4); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } + /* load/store dual, in decodetree */ + goto illegal_op; } else if ((insn & (1 << 23)) == 0) { /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx * - load/store exclusive word @@ -10746,184 +10834,15 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } } break; - case 12: /* Load/store single data item. */ - { - int postinc = 0; - int writeback = 0; - int memidx; - ISSInfo issinfo; - + case 12: if ((insn & 0x01100000) == 0x01000000) { if (disas_neon_ls_insn(s, insn)) { goto illegal_op; } break; } - op = ((insn >> 21) & 3) | ((insn >> 22) & 4); - if (rs == 15) { - if (!(insn & (1 << 20))) { - goto illegal_op; - } - if (op != 2) { - /* Byte or halfword load space with dest == r15 : memory hints. - * Catch them early so we don't emit pointless addressing code. - * This space is a mix of: - * PLD/PLDW/PLI, which we implement as NOPs (note that unlike - * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP - * cores) - * unallocated hints, which must be treated as NOPs - * UNPREDICTABLE space, which we NOP or UNDEF depending on - * which is easiest for the decoding logic - * Some space which must UNDEF - */ - int op1 = (insn >> 23) & 3; - int op2 = (insn >> 6) & 0x3f; - if (op & 2) { - goto illegal_op; - } - if (rn == 15) { - /* UNPREDICTABLE, unallocated hint or - * PLD/PLDW/PLI (literal) - */ - return; - } - if (op1 & 1) { - return; /* PLD/PLDW/PLI or unallocated hint */ - } - if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) { - return; /* PLD/PLDW/PLI or unallocated hint */ - } - /* UNDEF space, or an UNPREDICTABLE */ - goto illegal_op; - } - } - memidx = get_mem_index(s); - imm = insn & 0xfff; - if (insn & (1 << 23)) { - /* PC relative or Positive offset. */ - addr = add_reg_for_lit(s, rn, imm); - } else if (rn == 15) { - /* PC relative with negative offset. */ - addr = add_reg_for_lit(s, rn, -imm); - } else { - addr = load_reg(s, rn); - imm = insn & 0xff; - switch ((insn >> 8) & 0xf) { - case 0x0: /* Shifted Register. */ - shift = (insn >> 4) & 0xf; - if (shift > 3) { - tcg_temp_free_i32(addr); - goto illegal_op; - } - tmp = load_reg(s, rm); - tcg_gen_shli_i32(tmp, tmp, shift); - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - break; - case 0xc: /* Negative offset. */ - tcg_gen_addi_i32(addr, addr, -imm); - break; - case 0xe: /* User privilege. */ - tcg_gen_addi_i32(addr, addr, imm); - memidx = get_a32_user_mem_index(s); - break; - case 0x9: /* Post-decrement. */ - imm = -imm; - /* Fall through. */ - case 0xb: /* Post-increment. */ - postinc = 1; - writeback = 1; - break; - case 0xd: /* Pre-decrement. */ - imm = -imm; - /* Fall through. */ - case 0xf: /* Pre-increment. */ - writeback = 1; - break; - default: - tcg_temp_free_i32(addr); - goto illegal_op; - } - } - - issinfo = writeback ? ISSInvalid : rs; - - if (s->v8m_stackcheck && rn == 13 && writeback) { - /* - * Stackcheck. Here we know 'addr' is the current SP; - * if imm is +ve we're moving SP up, else down. It is - * UNKNOWN whether the limit check triggers when SP starts - * below the limit and ends up above it; we chose to do so. - */ - if ((int32_t)imm < 0) { - TCGv_i32 newsp = tcg_temp_new_i32(); - - tcg_gen_addi_i32(newsp, addr, imm); - gen_helper_v8m_stackcheck(cpu_env, newsp); - tcg_temp_free_i32(newsp); - } else { - gen_helper_v8m_stackcheck(cpu_env, addr); - } - } - - if (writeback && !postinc) { - tcg_gen_addi_i32(addr, addr, imm); - } - - if (insn & (1 << 20)) { - /* Load. */ - tmp = tcg_temp_new_i32(); - switch (op) { - case 0: - gen_aa32_ld8u_iss(s, tmp, addr, memidx, issinfo); - break; - case 4: - gen_aa32_ld8s_iss(s, tmp, addr, memidx, issinfo); - break; - case 1: - gen_aa32_ld16u_iss(s, tmp, addr, memidx, issinfo); - break; - case 5: - gen_aa32_ld16s_iss(s, tmp, addr, memidx, issinfo); - break; - case 2: - gen_aa32_ld32u_iss(s, tmp, addr, memidx, issinfo); - break; - default: - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(addr); - goto illegal_op; - } - store_reg_from_load(s, rs, tmp); - } else { - /* Store. */ - tmp = load_reg(s, rs); - switch (op) { - case 0: - gen_aa32_st8_iss(s, tmp, addr, memidx, issinfo); - break; - case 1: - gen_aa32_st16_iss(s, tmp, addr, memidx, issinfo); - break; - case 2: - gen_aa32_st32_iss(s, tmp, addr, memidx, issinfo); - break; - default: - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(addr); - goto illegal_op; - } - tcg_temp_free_i32(tmp); - } - if (postinc) - tcg_gen_addi_i32(addr, addr, imm); - if (writeback) { - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - } - break; + /* Load/store single data item, in decodetree */ + goto illegal_op; default: goto illegal_op; } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index aac991664d..f7742deaee 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -37,6 +37,8 @@ &mrs_reg rd r &msr_bank rn r sysm &mrs_bank rd r sysm +&ldst_rr p w u rn rt rm shimm shtype +&ldst_ri p w u rn rt imm # Data-processing (register) @@ -222,3 +224,121 @@ HLT .... 0001 0000 .... .... .... 0111 .... @i16 BKPT .... 0001 0010 .... .... .... 0111 .... @i16 HVC .... 0001 0100 .... .... .... 0111 .... @i16 SMC ---- 0001 0110 0000 0000 0000 0111 imm:4 &i + +# Load/Store Dual, Half, Signed Byte (register) + +@ldst_rr_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 .... .... rm:4 \ + &ldst_rr p=1 shimm=0 shtype=0 +@ldst_rr_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 .... .... rm:4 \ + &ldst_rr p=0 w=0 shimm=0 shtype=0 + +STRH_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_pw0 +STRH_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_p1w + +LDRD_rr .... 000. .0.0 .... .... 0000 1101 .... @ldst_rr_pw0 +LDRD_rr .... 000. .0.0 .... .... 0000 1101 .... @ldst_rr_p1w + +STRD_rr .... 000. .0.0 .... .... 0000 1111 .... @ldst_rr_pw0 +STRD_rr .... 000. .0.0 .... .... 0000 1111 .... @ldst_rr_p1w + +LDRH_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_pw0 +LDRH_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_p1w + +LDRSB_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_pw0 +LDRSB_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_p1w + +LDRSH_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_pw0 +LDRSH_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_p1w + +# Note the unpriv load/stores use the previously invalid P=0, W=1 encoding, +# and act as normal post-indexed (P=0, W=0). +@ldst_rr_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 .... .... rm:4 \ + &ldst_rr p=0 w=0 shimm=0 shtype=0 + +STRHT_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_p0w1 +LDRHT_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_p0w1 +LDRSBT_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_p0w1 +LDRSHT_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_p0w1 + +# Load/Store word and unsigned byte (register) + +@ldst_rs_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \ + &ldst_rr p=1 +@ldst_rs_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \ + &ldst_rr p=0 w=0 + +STR_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_pw0 +STR_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_p1w +STRB_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_pw0 +STRB_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_p1w + +LDR_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_pw0 +LDR_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_p1w +LDRB_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_pw0 +LDRB_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_p1w + +@ldst_rs_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \ + &ldst_rr p=0 w=0 + +STRT_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_p0w1 +STRBT_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_p0w1 +LDRT_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_p0w1 +LDRBT_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_p0w1 + +# Load/Store Dual, Half, Signed Byte (immediate) + +%imm8s_8_0 8:4 0:4 +@ldst_ri8_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 .... .... .... \ + &ldst_ri imm=%imm8s_8_0 p=1 +@ldst_ri8_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 .... .... .... \ + &ldst_ri imm=%imm8s_8_0 p=0 w=0 + +STRH_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_pw0 +STRH_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_p1w + +LDRD_ri_a32 .... 000. .1.0 .... .... .... 1101 .... @ldst_ri8_pw0 +LDRD_ri_a32 .... 000. .1.0 .... .... .... 1101 .... @ldst_ri8_p1w + +STRD_ri_a32 .... 000. .1.0 .... .... .... 1111 .... @ldst_ri8_pw0 +STRD_ri_a32 .... 000. .1.0 .... .... .... 1111 .... @ldst_ri8_p1w + +LDRH_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_pw0 +LDRH_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_p1w + +LDRSB_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_pw0 +LDRSB_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_p1w + +LDRSH_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_pw0 +LDRSH_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_p1w + +# Note the unpriv load/stores use the previously invalid P=0, W=1 encoding, +# and act as normal post-indexed (P=0, W=0). +@ldst_ri8_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 .... .... .... \ + &ldst_ri imm=%imm8s_8_0 p=0 w=0 + +STRHT_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_p0w1 +LDRHT_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_p0w1 +LDRSBT_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_p0w1 +LDRSHT_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_p0w1 + +# Load/Store word and unsigned byte (immediate) + +@ldst_ri12_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 imm:12 &ldst_ri p=1 +@ldst_ri12_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 imm:12 &ldst_ri p=0 w=0 + +STR_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p1w +STR_ri .... 010. .0.0 .... .... ............ @ldst_ri12_pw0 +STRB_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p1w +STRB_ri .... 010. .1.0 .... .... ............ @ldst_ri12_pw0 + +LDR_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p1w +LDR_ri .... 010. .0.1 .... .... ............ @ldst_ri12_pw0 +LDRB_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p1w +LDRB_ri .... 010. .1.1 .... .... ............ @ldst_ri12_pw0 + +@ldst_ri12_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 imm:12 &ldst_ri p=0 w=0 + +STRT_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p0w1 +STRBT_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p0w1 +LDRT_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p0w1 +LDRBT_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p0w1 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index be4e5f087c..a86597562b 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -34,6 +34,8 @@ &mrs_reg !extern rd r &msr_bank !extern rn r sysm &mrs_bank !extern rd r sysm +&ldst_rr !extern p w u rn rt rm shimm shtype +&ldst_ri !extern p w u rn rt imm # Data-processing (register) @@ -251,3 +253,142 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=%imm16_16_0 } + +# Load/store (register, immediate, literal) + +@ldst_rr .... .... .... rn:4 rt:4 ...... shimm:2 rm:4 \ + &ldst_rr p=1 w=0 u=1 shtype=0 +@ldst_ri_idx .... .... .... rn:4 rt:4 . p:1 u:1 . imm:8 \ + &ldst_ri w=1 +@ldst_ri_neg .... .... .... rn:4 rt:4 .... imm:8 \ + &ldst_ri p=1 w=0 u=0 +@ldst_ri_unp .... .... .... rn:4 rt:4 .... imm:8 \ + &ldst_ri p=1 w=0 u=1 +@ldst_ri_pos .... .... .... rn:4 rt:4 imm:12 \ + &ldst_ri p=1 w=0 u=1 +@ldst_ri_lit .... .... u:1 ... .... rt:4 imm:12 \ + &ldst_ri p=1 w=0 rn=15 + +STRB_rr 1111 1000 0000 .... .... 000000 .. .... @ldst_rr +STRB_ri 1111 1000 0000 .... .... 1..1 ........ @ldst_ri_idx +STRB_ri 1111 1000 0000 .... .... 1100 ........ @ldst_ri_neg +STRBT_ri 1111 1000 0000 .... .... 1110 ........ @ldst_ri_unp +STRB_ri 1111 1000 1000 .... .... ............ @ldst_ri_pos + +STRH_rr 1111 1000 0010 .... .... 000000 .. .... @ldst_rr +STRH_ri 1111 1000 0010 .... .... 1..1 ........ @ldst_ri_idx +STRH_ri 1111 1000 0010 .... .... 1100 ........ @ldst_ri_neg +STRHT_ri 1111 1000 0010 .... .... 1110 ........ @ldst_ri_unp +STRH_ri 1111 1000 1010 .... .... ............ @ldst_ri_pos + +STR_rr 1111 1000 0100 .... .... 000000 .. .... @ldst_rr +STR_ri 1111 1000 0100 .... .... 1..1 ........ @ldst_ri_idx +STR_ri 1111 1000 0100 .... .... 1100 ........ @ldst_ri_neg +STRT_ri 1111 1000 0100 .... .... 1110 ........ @ldst_ri_unp +STR_ri 1111 1000 1100 .... .... ............ @ldst_ri_pos + +# Note that Load, unsigned (literal) overlaps all other load encodings. +{ + { + NOP 1111 1000 -001 1111 1111 ------------ # PLD + LDRB_ri 1111 1000 .001 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1000 1001 ---- 1111 ------------ # PLD + LDRB_ri 1111 1000 1001 .... .... ............ @ldst_ri_pos + } + LDRB_ri 1111 1000 0001 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1000 0001 ---- 1111 1100 -------- # PLD + LDRB_ri 1111 1000 0001 .... .... 1100 ........ @ldst_ri_neg + } + LDRBT_ri 1111 1000 0001 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1000 0001 ---- 1111 000000 -- ---- # PLD + LDRB_rr 1111 1000 0001 .... .... 000000 .. .... @ldst_rr + } +} +{ + { + NOP 1111 1000 -011 1111 1111 ------------ # PLD + LDRH_ri 1111 1000 .011 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1000 1011 ---- 1111 ------------ # PLDW + LDRH_ri 1111 1000 1011 .... .... ............ @ldst_ri_pos + } + LDRH_ri 1111 1000 0011 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1000 0011 ---- 1111 1100 -------- # PLDW + LDRH_ri 1111 1000 0011 .... .... 1100 ........ @ldst_ri_neg + } + LDRHT_ri 1111 1000 0011 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1000 0011 ---- 1111 000000 -- ---- # PLDW + LDRH_rr 1111 1000 0011 .... .... 000000 .. .... @ldst_rr + } +} +{ + LDR_ri 1111 1000 .101 1111 .... ............ @ldst_ri_lit + LDR_ri 1111 1000 1101 .... .... ............ @ldst_ri_pos + LDR_ri 1111 1000 0101 .... .... 1..1 ........ @ldst_ri_idx + LDR_ri 1111 1000 0101 .... .... 1100 ........ @ldst_ri_neg + LDRT_ri 1111 1000 0101 .... .... 1110 ........ @ldst_ri_unp + LDR_rr 1111 1000 0101 .... .... 000000 .. .... @ldst_rr +} +# NOPs here are PLI. +{ + { + NOP 1111 1001 -001 1111 1111 ------------ + LDRSB_ri 1111 1001 .001 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1001 1001 ---- 1111 ------------ + LDRSB_ri 1111 1001 1001 .... .... ............ @ldst_ri_pos + } + LDRSB_ri 1111 1001 0001 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1001 0001 ---- 1111 1100 -------- + LDRSB_ri 1111 1001 0001 .... .... 1100 ........ @ldst_ri_neg + } + LDRSBT_ri 1111 1001 0001 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1001 0001 ---- 1111 000000 -- ---- + LDRSB_rr 1111 1001 0001 .... .... 000000 .. .... @ldst_rr + } +} +# NOPs here are unallocated memory hints, treated as NOP. +{ + { + NOP 1111 1001 -011 1111 1111 ------------ + LDRSH_ri 1111 1001 .011 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1001 1011 ---- 1111 ------------ + LDRSH_ri 1111 1001 1011 .... .... ............ @ldst_ri_pos + } + LDRSH_ri 1111 1001 0011 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1001 0011 ---- 1111 1100 -------- + LDRSH_ri 1111 1001 0011 .... .... 1100 ........ @ldst_ri_neg + } + LDRSHT_ri 1111 1001 0011 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1001 0011 ---- 1111 000000 -- ---- + LDRSH_rr 1111 1001 0011 .... .... 000000 .. .... @ldst_rr + } +} + +%imm8x4 0:8 !function=times_4 +&ldst_ri2 p w u rn rt rt2 imm +@ldstd_ri8 .... .... u:1 ... rn:4 rt:4 rt2:4 ........ \ + &ldst_ri2 imm=%imm8x4 + +STRD_ri_t32 1110 1000 .110 .... .... .... ........ @ldstd_ri8 w=1 p=0 +LDRD_ri_t32 1110 1000 .111 .... .... .... ........ @ldstd_ri8 w=1 p=0 + +STRD_ri_t32 1110 1001 .100 .... .... .... ........ @ldstd_ri8 w=0 p=1 +LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1 + +STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1 +LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1 From patchwork Wed Sep 4 19:30:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172975 Delivered-To: patch@linaro.org Received: by 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:11 -0700 Message-Id: <20190904193059.26202-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v4 21/69] target/arm: Convert Synchronization primitives X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Fix arch test for {ld,st}rex[bh] Use unallocated_encoding for odd reg checks --- target/arm/translate.c | 576 +++++++++++++++++++++++------------------ target/arm/a32.decode | 48 ++++ target/arm/t32.decode | 46 ++++ 3 files changed, 412 insertions(+), 258 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index d383a16f4b..ec80c9cbbc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8872,6 +8872,318 @@ DO_LDST(STRH, store, MO_UW) #undef DO_LDST +/* + * Synchronization primitives + */ + +static bool op_swp(DisasContext *s, arg_SWP *a, MemOp opc) +{ + TCGv_i32 addr, tmp; + TCGv taddr; + + opc |= s->be_data; + addr = load_reg(s, a->rn); + taddr = gen_aa32_addr(s, addr, opc); + tcg_temp_free_i32(addr); + + tmp = load_reg(s, a->rt2); + tcg_gen_atomic_xchg_i32(tmp, taddr, tmp, get_mem_index(s), opc); + tcg_temp_free(taddr); + + store_reg(s, a->rt, tmp); + return true; +} + +static bool trans_SWP(DisasContext *s, arg_SWP *a) +{ + return op_swp(s, a, MO_UL | MO_ALIGN); +} + +static bool trans_SWPB(DisasContext *s, arg_SWP *a) +{ + return op_swp(s, a, MO_UB); +} + +/* + * Load/Store Exclusive and Load-Acquire/Store-Release + */ + +static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel) +{ + TCGv_i32 addr; + + if (rel) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + + addr = tcg_temp_local_new_i32(); + load_reg_var(s, addr, a->rn); + tcg_gen_addi_i32(addr, addr, a->imm); + + gen_store_exclusive(s, a->rd, a->rt, a->rt2, addr, mop); + tcg_temp_free_i32(addr); + return true; +} + +static bool trans_STREX(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_strex(s, a, MO_32, false); +} + +static bool trans_STREXD_a32(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + if (a->rt & 1) { + unallocated_encoding(s); + return true; + } + a->rt2 = a->rt + 1; + return op_strex(s, a, MO_64, false); +} + +static bool trans_STREXD_t32(DisasContext *s, arg_STREX *a) +{ + return op_strex(s, a, MO_64, false); +} + +static bool trans_STREXB(DisasContext *s, arg_STREX *a) +{ + if (s->thumb ? !ENABLE_ARCH_7 : !ENABLE_ARCH_6K) { + return false; + } + return op_strex(s, a, MO_8, false); +} + +static bool trans_STREXH(DisasContext *s, arg_STREX *a) +{ + if (s->thumb ? !ENABLE_ARCH_7 : !ENABLE_ARCH_6K) { + return false; + } + return op_strex(s, a, MO_16, false); +} + +static bool trans_STLEX(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_32, true); +} + +static bool trans_STLEXD_a32(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + if (a->rt & 1) { + unallocated_encoding(s); + return true; + } + a->rt2 = a->rt + 1; + return op_strex(s, a, MO_64, true); +} + +static bool trans_STLEXD_t32(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_64, true); +} + +static bool trans_STLEXB(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_8, true); +} + +static bool trans_STLEXH(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_16, true); +} + +static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop) +{ + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_8) { + return false; + } + addr = load_reg(s, a->rn); + + tmp = load_reg(s, a->rt); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite); + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(addr); + return true; +} + +static bool trans_STL(DisasContext *s, arg_STL *a) +{ + return op_stl(s, a, MO_UL); +} + +static bool trans_STLB(DisasContext *s, arg_STL *a) +{ + return op_stl(s, a, MO_UB); +} + +static bool trans_STLH(DisasContext *s, arg_STL *a) +{ + return op_stl(s, a, MO_UW); +} + +static bool op_ldrex(DisasContext *s, arg_LDREX *a, MemOp mop, bool acq) +{ + TCGv_i32 addr; + + addr = tcg_temp_local_new_i32(); + load_reg_var(s, addr, a->rn); + tcg_gen_addi_i32(addr, addr, a->imm); + + gen_load_exclusive(s, a->rt, a->rt2, addr, mop); + tcg_temp_free_i32(addr); + + if (acq) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } + return true; +} + +static bool trans_LDREX(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_ldrex(s, a, MO_32, false); +} + +static bool trans_LDREXD_a32(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + if (a->rt & 1) { + unallocated_encoding(s); + return true; + } + a->rt2 = a->rt + 1; + return op_ldrex(s, a, MO_64, false); +} + +static bool trans_LDREXD_t32(DisasContext *s, arg_LDREX *a) +{ + return op_ldrex(s, a, MO_64, false); +} + +static bool trans_LDREXB(DisasContext *s, arg_LDREX *a) +{ + if (s->thumb ? !ENABLE_ARCH_7 : !ENABLE_ARCH_6K) { + return false; + } + return op_ldrex(s, a, MO_8, false); +} + +static bool trans_LDREXH(DisasContext *s, arg_LDREX *a) +{ + if (s->thumb ? !ENABLE_ARCH_7 : !ENABLE_ARCH_6K) { + return false; + } + return op_ldrex(s, a, MO_16, false); +} + +static bool trans_LDAEX(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_32, true); +} + +static bool trans_LDAEXD_a32(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + if (a->rt & 1) { + unallocated_encoding(s); + return true; + } + a->rt2 = a->rt + 1; + return op_ldrex(s, a, MO_64, true); +} + +static bool trans_LDAEXD_t32(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_64, true); +} + +static bool trans_LDAEXB(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_8, true); +} + +static bool trans_LDAEXH(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_16, true); +} + +static bool op_lda(DisasContext *s, arg_LDA *a, MemOp mop) +{ + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_8) { + return false; + } + addr = load_reg(s, a->rn); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel); + tcg_temp_free_i32(addr); + + store_reg(s, a->rt, tmp); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + return true; +} + +static bool trans_LDA(DisasContext *s, arg_LDA *a) +{ + return op_lda(s, a, MO_UL); +} + +static bool trans_LDAB(DisasContext *s, arg_LDA *a) +{ + return op_lda(s, a, MO_UB); +} + +static bool trans_LDAH(DisasContext *s, arg_LDA *a) +{ + return op_lda(s, a, MO_UW); +} + /* * Legacy decoder. */ @@ -9167,172 +9479,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) case 0x0: case 0x1: /* multiplies, extra load/stores */ - sh = (insn >> 5) & 3; - if (sh == 0) { - if (op1 == 0x0) { - /* Multiply and multiply accumulate. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } else { - rn = (insn >> 16) & 0xf; - rd = (insn >> 12) & 0xf; - if (insn & (1 << 23)) { - /* load/store exclusive */ - bool is_ld = extract32(insn, 20, 1); - bool is_lasr = !extract32(insn, 8, 1); - int op2 = (insn >> 8) & 3; - op1 = (insn >> 21) & 0x3; - - switch (op2) { - case 0: /* lda/stl */ - if (op1 == 1) { - goto illegal_op; - } - ARCH(8); - break; - case 1: /* reserved */ - goto illegal_op; - case 2: /* ldaex/stlex */ - ARCH(8); - break; - case 3: /* ldrex/strex */ - if (op1) { - ARCH(6K); - } else { - ARCH(6); - } - break; - } - - addr = tcg_temp_local_new_i32(); - load_reg_var(s, addr, rn); - - if (is_lasr && !is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - - if (op2 == 0) { - if (is_ld) { - tmp = tcg_temp_new_i32(); - switch (op1) { - case 0: /* lda */ - gen_aa32_ld32u_iss(s, tmp, addr, - get_mem_index(s), - rd | ISSIsAcqRel); - break; - case 2: /* ldab */ - gen_aa32_ld8u_iss(s, tmp, addr, - get_mem_index(s), - rd | ISSIsAcqRel); - break; - case 3: /* ldah */ - gen_aa32_ld16u_iss(s, tmp, addr, - get_mem_index(s), - rd | ISSIsAcqRel); - break; - default: - abort(); - } - store_reg(s, rd, tmp); - } else { - rm = insn & 0xf; - tmp = load_reg(s, rm); - switch (op1) { - case 0: /* stl */ - gen_aa32_st32_iss(s, tmp, addr, - get_mem_index(s), - rm | ISSIsAcqRel); - break; - case 2: /* stlb */ - gen_aa32_st8_iss(s, tmp, addr, - get_mem_index(s), - rm | ISSIsAcqRel); - break; - case 3: /* stlh */ - gen_aa32_st16_iss(s, tmp, addr, - get_mem_index(s), - rm | ISSIsAcqRel); - break; - default: - abort(); - } - tcg_temp_free_i32(tmp); - } - } else if (is_ld) { - switch (op1) { - case 0: /* ldrex */ - gen_load_exclusive(s, rd, 15, addr, 2); - break; - case 1: /* ldrexd */ - gen_load_exclusive(s, rd, rd + 1, addr, 3); - break; - case 2: /* ldrexb */ - gen_load_exclusive(s, rd, 15, addr, 0); - break; - case 3: /* ldrexh */ - gen_load_exclusive(s, rd, 15, addr, 1); - break; - default: - abort(); - } - } else { - rm = insn & 0xf; - switch (op1) { - case 0: /* strex */ - gen_store_exclusive(s, rd, rm, 15, addr, 2); - break; - case 1: /* strexd */ - gen_store_exclusive(s, rd, rm, rm + 1, addr, 3); - break; - case 2: /* strexb */ - gen_store_exclusive(s, rd, rm, 15, addr, 0); - break; - case 3: /* strexh */ - gen_store_exclusive(s, rd, rm, 15, addr, 1); - break; - default: - abort(); - } - } - tcg_temp_free_i32(addr); - - if (is_lasr && is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } - } else if ((insn & 0x00300f00) == 0) { - /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx - * - SWP, SWPB - */ - - TCGv taddr; - MemOp opc = s->be_data; - - rm = (insn) & 0xf; - - if (insn & (1 << 22)) { - opc |= MO_UB; - } else { - opc |= MO_UL | MO_ALIGN; - } - - addr = load_reg(s, rn); - taddr = gen_aa32_addr(s, addr, opc); - tcg_temp_free_i32(addr); - - tmp = load_reg(s, rm); - tcg_gen_atomic_xchg_i32(tmp, taddr, tmp, - get_mem_index(s), opc); - tcg_temp_free(taddr); - store_reg(s, rd, tmp); - } else { - goto illegal_op; - } - } - } else { - /* Extra load/store (register) instructions */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; break; case 0x4: case 0x5: @@ -9987,15 +10135,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } goto illegal_op; } - addr = tcg_temp_local_new_i32(); - load_reg_var(s, addr, rn); - tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2); - if (insn & (1 << 20)) { - gen_load_exclusive(s, rs, 15, addr, 2); - } else { - gen_store_exclusive(s, rd, rs, 15, addr, 2); - } - tcg_temp_free_i32(addr); + /* Load/store exclusive, in decodetree */ + goto illegal_op; } else if ((insn & (7 << 5)) == 0) { /* Table Branch. */ addr = load_reg(s, rn); @@ -10017,89 +10158,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_gen_addi_i32(tmp, tmp, read_pc(s)); store_reg(s, 15, tmp); } else { - bool is_lasr = false; - bool is_ld = extract32(insn, 20, 1); - int op2 = (insn >> 6) & 0x3; - op = (insn >> 4) & 0x3; - switch (op2) { - case 0: - goto illegal_op; - case 1: - /* Load/store exclusive byte/halfword/doubleword */ - if (op == 2) { - goto illegal_op; - } - ARCH(7); - break; - case 2: - /* Load-acquire/store-release */ - if (op == 3) { - goto illegal_op; - } - /* Fall through */ - case 3: - /* Load-acquire/store-release exclusive */ - ARCH(8); - is_lasr = true; - break; - } - - if (is_lasr && !is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - - addr = tcg_temp_local_new_i32(); - load_reg_var(s, addr, rn); - if (!(op2 & 1)) { - if (is_ld) { - tmp = tcg_temp_new_i32(); - switch (op) { - case 0: /* ldab */ - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), - rs | ISSIsAcqRel); - break; - case 1: /* ldah */ - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), - rs | ISSIsAcqRel); - break; - case 2: /* lda */ - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), - rs | ISSIsAcqRel); - break; - default: - abort(); - } - store_reg(s, rs, tmp); - } else { - tmp = load_reg(s, rs); - switch (op) { - case 0: /* stlb */ - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), - rs | ISSIsAcqRel); - break; - case 1: /* stlh */ - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), - rs | ISSIsAcqRel); - break; - case 2: /* stl */ - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), - rs | ISSIsAcqRel); - break; - default: - abort(); - } - tcg_temp_free_i32(tmp); - } - } else if (is_ld) { - gen_load_exclusive(s, rs, rd, addr, op); - } else { - gen_store_exclusive(s, rm, rs, rd, addr, op); - } - tcg_temp_free_i32(addr); - - if (is_lasr && is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } + /* Load/store exclusive, load-acq/store-rel, in decodetree */ + goto illegal_op; } } else { /* Load/store multiple, RFE, SRS. */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index f7742deaee..c76cbad569 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -39,6 +39,8 @@ &mrs_bank rd r sysm &ldst_rr p w u rn rt rm shimm shtype &ldst_ri p w u rn rt imm +&strex rn rd rt rt2 imm +&ldrex rn rt rt2 imm # Data-processing (register) @@ -342,3 +344,49 @@ STRT_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p0w1 STRBT_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p0w1 LDRT_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p0w1 LDRBT_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p0w1 + +# Synchronization primitives + +@swp ---- .... .... rn:4 rt:4 .... .... rt2:4 + +SWP .... 0001 0000 .... .... 0000 1001 .... @swp +SWPB .... 0001 0100 .... .... 0000 1001 .... @swp + +# Load/Store Exclusive and Load-Acquire/Store-Release +# +# Note rt2 for STREXD/LDREXD is set by the helper after checking rt is even. + +@strex ---- .... .... rn:4 rd:4 .... .... rt:4 \ + &strex imm=0 rt2=15 +@ldrex ---- .... .... rn:4 rt:4 .... .... .... \ + &ldrex imm=0 rt2=15 +@stl ---- .... .... rn:4 .... .... .... rt:4 \ + &ldrex imm=0 rt2=15 + +STREX .... 0001 1000 .... .... 1111 1001 .... @strex +STREXD_a32 .... 0001 1010 .... .... 1111 1001 .... @strex +STREXB .... 0001 1100 .... .... 1111 1001 .... @strex +STREXH .... 0001 1110 .... .... 1111 1001 .... @strex + +STLEX .... 0001 1000 .... .... 1110 1001 .... @strex +STLEXD_a32 .... 0001 1010 .... .... 1110 1001 .... @strex +STLEXB .... 0001 1100 .... .... 1110 1001 .... @strex +STLEXH .... 0001 1110 .... .... 1110 1001 .... @strex + +STL .... 0001 1000 .... 1111 1100 1001 .... @stl +STLB .... 0001 1100 .... 1111 1100 1001 .... @stl +STLH .... 0001 1110 .... 1111 1100 1001 .... @stl + +LDREX .... 0001 1001 .... .... 1111 1001 1111 @ldrex +LDREXD_a32 .... 0001 1011 .... .... 1111 1001 1111 @ldrex +LDREXB .... 0001 1101 .... .... 1111 1001 1111 @ldrex +LDREXH .... 0001 1111 .... .... 1111 1001 1111 @ldrex + +LDAEX .... 0001 1001 .... .... 1110 1001 1111 @ldrex +LDAEXD_a32 .... 0001 1011 .... .... 1110 1001 1111 @ldrex +LDAEXB .... 0001 1101 .... .... 1110 1001 1111 @ldrex +LDAEXH .... 0001 1111 .... .... 1110 1001 1111 @ldrex + +LDA .... 0001 1001 .... .... 1100 1001 1111 @ldrex +LDAB .... 0001 1101 .... .... 1100 1001 1111 @ldrex +LDAH .... 0001 1111 .... .... 1100 1001 1111 @ldrex diff --git a/target/arm/t32.decode b/target/arm/t32.decode index a86597562b..70cf8039d7 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -36,6 +36,8 @@ &mrs_bank !extern rd r sysm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm +&strex !extern rn rd rt rt2 imm +&ldrex !extern rn rt rt2 imm # Data-processing (register) @@ -392,3 +394,47 @@ LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1 LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1 + +# Load/Store Exclusive and Load-Acquire/Store-Release + +@strex_i .... .... .... rn:4 rt:4 rd:4 .... .... \ + &strex rt2=15 imm=%imm8x4 +@strex_0 .... .... .... rn:4 rt:4 .... .... rd:4 \ + &strex rt2=15 imm=0 +@strex_d .... .... .... rn:4 rt:4 rt2:4 .... rd:4 \ + &strex imm=0 + +@ldrex_i .... .... .... rn:4 rt:4 .... .... .... \ + &ldrex rt2=15 imm=%imm8x4 +@ldrex_0 .... .... .... rn:4 rt:4 .... .... .... \ + &ldrex rt2=15 imm=0 +@ldrex_d .... .... .... rn:4 rt:4 rt2:4 .... .... \ + &ldrex imm=0 + +STREX 1110 1000 0100 .... .... .... .... .... @strex_i +STREXB 1110 1000 1100 .... .... 1111 0100 .... @strex_0 +STREXH 1110 1000 1100 .... .... 1111 0101 .... @strex_0 +STREXD_t32 1110 1000 1100 .... .... .... 0111 .... @strex_d + +STLEX 1110 1000 1100 .... .... 1111 1110 .... @strex_0 +STLEXB 1110 1000 1100 .... .... 1111 1100 .... @strex_0 +STLEXH 1110 1000 1100 .... .... 1111 1101 .... @strex_0 +STLEXD_t32 1110 1000 1100 .... .... .... 1111 .... @strex_d + +STL 1110 1000 1100 .... .... 1111 1010 1111 @ldrex_0 +STLB 1110 1000 1100 .... .... 1111 1000 1111 @ldrex_0 +STLH 1110 1000 1100 .... .... 1111 1001 1111 @ldrex_0 + +LDREX 1110 1000 0101 .... .... 1111 .... .... @ldrex_i +LDREXB 1110 1000 1101 .... .... 1111 0100 1111 @ldrex_0 +LDREXH 1110 1000 1101 .... .... 1111 0101 1111 @ldrex_0 +LDREXD_t32 1110 1000 1101 .... .... .... 0111 1111 @ldrex_d + +LDAEX 1110 1000 1101 .... .... 1111 1110 1111 @ldrex_0 +LDAEXB 1110 1000 1101 .... .... 1111 1100 1111 @ldrex_0 +LDAEXH 1110 1000 1101 .... .... 1111 1101 1111 @ldrex_0 +LDAEXD_t32 1110 1000 1101 .... .... .... 1111 1111 @ldrex_d + +LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0 +LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0 +LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0 From patchwork Wed Sep 4 19:30:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172985 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp369581ilq; Wed, 4 Sep 2019 12:53:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqyR3wwenzl6Z3AFY566EG4KfvKTLN12jLTY5vHAm9Fb+w7LdKa3ei6ySaOjY5wrrDCT1G41 X-Received: by 2002:a37:6dc7:: with SMTP id i190mr42333961qkc.12.1567626812873; Wed, 04 Sep 2019 12:53:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567626812; cv=none; d=google.com; s=arc-20160816; b=zVZVX3WHZ2YZSX2TPFsUrZjym8OzwBoIbb1DW4FMO8wd1bfrZMSzlqpcmK2D0ES3Rj ry7xKBtXN9/WQTsbxu8ET6uVHESmuhjpUUldB2k9F0Exh6v9140Zn0ZTDqdIOumStgwR HI0rRIqBoUK4bDVyzBoG4W7T6bs5jChkSs3QIsHqK6PzNP3ip+7z+i6p6+aN4sYIV91Y ifsOWFwbBmeNi6UFM/s2UpHbHynFuttz//BOQLpZF8DBVqx1SqjqQXPnP7agaAdJhz6R szWJqHxsnWJBSo+eJbmK89Y/F3QjZhkXhRtu3s+qNNQSFsFS2DCJ/jCQlbaLO8fOt4hw ZFXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=w4KLvtnzbGeNcUZz918DD9xSWUWeMSJ2fRY4zLuIN7M=; b=pp1RhEqVApJIbPtZWGfoXSKx4CNtl+VEaNsWImiPh+ZUddpsajD4hsmIfIsqMDh/x+ R2Z6Byb2x7fVxgq+LObG7lQBcJXIMH+ujlxEVzDbISVxMetjRfII1OD0G4luue3yH4nZ b8BC+6GBYfX5xh9zjhYioNdAIVPOgFuAQWVa+oR1cVy1POrd+tmlXMuoFIj6y3k0QYFj p1ee9h9cBWcad0rFwL2EMoJUIccw7EsFfJ4Uqt4qD/9hfYPVIJAmtgkBEEsxogDCZ+bY 6p+lgPjVgcN6fDR3TXywZQagz56baEu895+9I5Y6mRVq8FS+y6VtlHbNVWw35DFGQ5pw I15g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Xo4CiaJ2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:12 -0700 Message-Id: <20190904193059.26202-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 22/69] target/arm: Diagnose UNPREDICTABLE ldrex/strex cases X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 40 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index ec80c9cbbc..9338873a4a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8912,6 +8912,18 @@ static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel) { TCGv_i32 addr; + /* We UNDEF for these UNPREDICTABLE cases. */ + if (a->rd == 15 || a->rn == 15 || a->rt == 15 + || a->rd == a->rn || a->rd == a->rt + || (s->thumb && (a->rd == 13 || a->rt == 13)) + || (mop == MO_64 + && (a->rt2 == 15 + || a->rd == a->rt2 || a->rt == a->rt2 + || (s->thumb && a->rt2 == 13)))) { + unallocated_encoding(s); + return true; + } + if (rel) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } @@ -8938,6 +8950,7 @@ static bool trans_STREXD_a32(DisasContext *s, arg_STREX *a) if (!ENABLE_ARCH_6K) { return false; } + /* We UNDEF for these UNPREDICTABLE cases. */ if (a->rt & 1) { unallocated_encoding(s); return true; @@ -8980,6 +8993,7 @@ static bool trans_STLEXD_a32(DisasContext *s, arg_STREX *a) if (!ENABLE_ARCH_8) { return false; } + /* We UNDEF for these UNPREDICTABLE cases. */ if (a->rt & 1) { unallocated_encoding(s); return true; @@ -9019,8 +9033,13 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop) if (!ENABLE_ARCH_8) { return false; } - addr = load_reg(s, a->rn); + /* We UNDEF for these UNPREDICTABLE cases. */ + if (a->rn == 15 || a->rt == 15) { + unallocated_encoding(s); + return true; + } + addr = load_reg(s, a->rn); tmp = load_reg(s, a->rt); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); @@ -9050,6 +9069,16 @@ static bool op_ldrex(DisasContext *s, arg_LDREX *a, MemOp mop, bool acq) { TCGv_i32 addr; + /* We UNDEF for these UNPREDICTABLE cases. */ + if (a->rn == 15 || a->rt == 15 + || (s->thumb && a->rt == 13) + || (mop == MO_64 + && (a->rt2 == 15 || a->rt == a->rt2 + || (s->thumb && a->rt2 == 13)))) { + unallocated_encoding(s); + return true; + } + addr = tcg_temp_local_new_i32(); load_reg_var(s, addr, a->rn); tcg_gen_addi_i32(addr, addr, a->imm); @@ -9076,6 +9105,7 @@ static bool trans_LDREXD_a32(DisasContext *s, arg_LDREX *a) if (!ENABLE_ARCH_6K) { return false; } + /* We UNDEF for these UNPREDICTABLE cases. */ if (a->rt & 1) { unallocated_encoding(s); return true; @@ -9118,6 +9148,7 @@ static bool trans_LDAEXD_a32(DisasContext *s, arg_LDREX *a) if (!ENABLE_ARCH_8) { return false; } + /* We UNDEF for these UNPREDICTABLE cases. */ if (a->rt & 1) { unallocated_encoding(s); return true; @@ -9157,8 +9188,13 @@ static bool op_lda(DisasContext *s, arg_LDA *a, MemOp mop) if (!ENABLE_ARCH_8) { return false; } - addr = load_reg(s, a->rn); + /* We UNDEF for these UNPREDICTABLE cases. */ + if (a->rn == 15 || a->rt == 15) { + unallocated_encoding(s); + return true; + } + addr = load_reg(s, a->rn); tmp = tcg_temp_new_i32(); gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel); From patchwork Wed Sep 4 19:30:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172979 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp365730ilq; Wed, 4 Sep 2019 12:49:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqxtTesiLppLYlkPYdbDuMIN9xHWfrKYlyuRVfOlBkNc5xX+QSCO0DU/dI2pcYT7AB3bH7bL X-Received: by 2002:a05:620a:103b:: with SMTP id a27mr1375107qkk.200.1567626540501; Wed, 04 Sep 2019 12:49:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567626540; cv=none; d=google.com; s=arc-20160816; b=R4ZqaLZ5Stc9gh919+u7oacRsYgEchdqSnkR6xJ0twyGtiKTx1D4qzeNSAYx+ABiDw T2cS34aSCSlNEfHVhhgOw/dPzBF3SUTzB34Fw1/RXIxLgC3sPxNOgoSKbeSh9+ZLRimQ +NucOz9jj7OZDTtmyp7hw4UuSJDgacTcP5vhAbwgoJhRWcANiJABhT1oqGrpW0buibgc wHfEnqHn9Gqg2P5VlateLowM0p6w+e7N2gLjmIe+3J3tH67exAwBRQRRYkOPeSrSQbDp ty76Pc+XQ8Tx9l4ab+IMLhV3qpCKLsW9Blxbtlzt8nHbQcty902v9zHV9ZPejP/kNej9 s2xw== ARC-Message-Signature: i=1; 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 23/69] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In op_bfx, note that tcg_gen_{,s}extract_i32 already checks for width == 32, so we don't need to special case that here. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use unallocated_encoding for out-of-range bitops. --- target/arm/translate.c | 201 +++++++++++++++++++++-------------------- target/arm/a32.decode | 20 ++++ target/arm/t32.decode | 19 ++++ 3 files changed, 144 insertions(+), 96 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 9338873a4a..1c50ea232a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9220,6 +9220,104 @@ static bool trans_LDAH(DisasContext *s, arg_LDA *a) return op_lda(s, a, MO_UW); } +/* + * Media instructions + */ + +static bool trans_USADA8(DisasContext *s, arg_USADA8 *a) +{ + TCGv_i32 t1, t2; + + if (!ENABLE_ARCH_6) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + gen_helper_usad8(t1, t1, t2); + tcg_temp_free_i32(t2); + if (a->ra != 15) { + t2 = load_reg(s, a->ra); + tcg_gen_add_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + } + store_reg(s, a->rd, t1); + return true; +} + +static bool op_bfx(DisasContext *s, arg_UBFX *a, bool u) +{ + TCGv_i32 tmp; + int width = a->widthm1 + 1; + int shift = a->lsb; + + if (!ENABLE_ARCH_6T2) { + return false; + } + if (shift + width > 32) { + /* UNPREDICTABLE; we choose to UNDEF */ + unallocated_encoding(s); + return true; + } + + tmp = load_reg(s, a->rn); + if (u) { + tcg_gen_extract_i32(tmp, tmp, shift, width); + } else { + tcg_gen_sextract_i32(tmp, tmp, shift, width); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_SBFX(DisasContext *s, arg_SBFX *a) +{ + return op_bfx(s, a, false); +} + +static bool trans_UBFX(DisasContext *s, arg_UBFX *a) +{ + return op_bfx(s, a, true); +} + +static bool trans_BFCI(DisasContext *s, arg_BFCI *a) +{ + TCGv_i32 tmp; + int msb = a->msb, lsb = a->lsb; + int width; + + if (!ENABLE_ARCH_6T2) { + return false; + } + if (msb < lsb) { + /* UNPREDICTABLE; we choose to UNDEF */ + unallocated_encoding(s); + return true; + } + + width = msb + 1 - lsb; + if (a->rn == 15) { + /* BFC */ + tmp = tcg_const_i32(0); + } else { + /* BFI */ + tmp = load_reg(s, a->rn); + } + if (width != 32) { + TCGv_i32 tmp2 = load_reg(s, a->rd); + tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width); + tcg_temp_free_i32(tmp2); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_UDF(DisasContext *s, arg_UDF *a) +{ + unallocated_encoding(s); + return true; +} + /* * Legacy decoder. */ @@ -9769,65 +9867,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } break; case 3: - op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7); - switch (op1) { - case 0: /* Unsigned sum of absolute differences. */ - ARCH(6); - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rs); - gen_helper_usad8(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rd != 15) { - tmp2 = load_reg(s, rd); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rn, tmp); - break; - case 0x20: case 0x24: case 0x28: case 0x2c: - /* Bitfield insert/clear. */ - ARCH(6T2); - shift = (insn >> 7) & 0x1f; - i = (insn >> 16) & 0x1f; - if (i < shift) { - /* UNPREDICTABLE; we choose to UNDEF */ - goto illegal_op; - } - i = i + 1 - shift; - if (rm == 15) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp = load_reg(s, rm); - } - if (i != 32) { - tmp2 = load_reg(s, rd); - tcg_gen_deposit_i32(tmp, tmp2, tmp, shift, i); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rd, tmp); - break; - case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */ - case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */ - ARCH(6T2); - tmp = load_reg(s, rm); - shift = (insn >> 7) & 0x1f; - i = ((insn >> 16) & 0x1f) + 1; - if (shift + i > 32) - goto illegal_op; - if (i < 32) { - if (op1 & 0x20) { - tcg_gen_extract_i32(tmp, tmp, shift, i); - } else { - tcg_gen_sextract_i32(tmp, tmp, shift, i); - } - } - store_reg(s, rd, tmp); - break; - default: - goto illegal_op; - } - break; + /* USAD, BFI, BFC, SBFX, UBFX */ + /* Done by decodetree */ + goto illegal_op; } break; } @@ -10466,10 +10508,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 0: /* 32 x 32 -> 32 */ case 1: /* 16 x 16 -> 32 */ case 3: /* 32 * 16 -> 32msb */ + case 7: /* Unsigned sum of absolute differences. */ /* in decodetree */ goto illegal_op; - case 7: /* Unsigned sum of absolute differences. */ - break; case 2: /* Dual multiply add. */ case 4: /* Dual multiply subtract. */ case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ @@ -10534,15 +10575,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } tcg_temp_free_i32(tmp2); break; - case 7: /* Unsigned sum of absolute differences. */ - gen_helper_usad8(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rs != 15) { - tmp2 = load_reg(s, rs); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; } store_reg(s, rd, tmp); break; @@ -10837,32 +10869,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tmp = load_reg(s, rn); } switch (op) { - case 2: /* Signed bitfield extract. */ - imm++; - if (shift + imm > 32) - goto illegal_op; - if (imm < 32) { - tcg_gen_sextract_i32(tmp, tmp, shift, imm); - } - break; - case 6: /* Unsigned bitfield extract. */ - imm++; - if (shift + imm > 32) - goto illegal_op; - if (imm < 32) { - tcg_gen_extract_i32(tmp, tmp, shift, imm); - } - break; - case 3: /* Bitfield insert/clear. */ - if (imm < shift) - goto illegal_op; - imm = imm + 1 - shift; - if (imm != 32) { - tmp2 = load_reg(s, rd); - tcg_gen_deposit_i32(tmp, tmp2, tmp, shift, imm); - tcg_temp_free_i32(tmp2); - } - break; + case 2: /* Signed bitfield extract, in decodetree */ + case 6: /* Unsigned bitfield extract, in decodetree */ + case 3: /* Bitfield insert/clear, in decodetree */ case 7: goto illegal_op; default: /* Saturate. */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index c76cbad569..285c08ca22 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -41,6 +41,8 @@ &ldst_ri p w u rn rt imm &strex rn rd rt rt2 imm &ldrex rn rt rt2 imm +&bfx rd rn lsb widthm1 +&bfi rd rn lsb msb # Data-processing (register) @@ -390,3 +392,21 @@ LDAEXH .... 0001 1111 .... .... 1110 1001 1111 @ldrex LDA .... 0001 1001 .... .... 1100 1001 1111 @ldrex LDAB .... 0001 1101 .... .... 1100 1001 1111 @ldrex LDAH .... 0001 1111 .... .... 1100 1001 1111 @ldrex + +# Media instructions + +# usad8 is usada8 w/ ra=15 +USADA8 ---- 0111 1000 rd:4 ra:4 rm:4 0001 rn:4 + +# ubfx and sbfx +@bfx ---- .... ... widthm1:5 rd:4 lsb:5 ... rn:4 &bfx + +SBFX .... 0111 101 ..... .... ..... 101 .... @bfx +UBFX .... 0111 111 ..... .... ..... 101 .... @bfx + +# bfc is bfi w/ rn=15 +BFCI ---- 0111 110 msb:5 rd:4 lsb:5 001 rn:4 &bfi + +# While we could get UDEF by not including this, add the pattern for +# documentation and to conflict with any other typos in this file. +UDF 1110 0111 1111 ---- ---- ---- 1111 ---- diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 70cf8039d7..682fc5c2c4 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -38,6 +38,8 @@ &ldst_ri !extern p w u rn rt imm &strex !extern rn rd rt rt2 imm &ldrex !extern rn rt rt2 imm +&bfx !extern rd rn lsb widthm1 +&bfi !extern rd rn lsb msb # Data-processing (register) @@ -144,6 +146,19 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12 } +# Saturate, bitfield + +@bfx .... .... ... . rn:4 . ... rd:4 .. . widthm1:5 \ + &bfx lsb=%imm5_12_6 +@bfi .... .... ... . rn:4 . ... rd:4 .. . msb:5 \ + &bfi lsb=%imm5_12_6 + +SBFX 1111 0011 010 0 .... 0 ... .... ..0..... @bfx +UBFX 1111 0011 110 0 .... 0 ... .... ..0..... @bfx + +# bfc is bfi w/ rn=15 +BFCI 1111 0011 011 0 .... 0 ... .... ..0..... @bfi + # Multiply and multiply accumulate @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0 @@ -192,6 +207,9 @@ SMLALBT 1111 1011 1100 .... .... .... 1001 .... @rnadm SMLALTB 1111 1011 1100 .... .... .... 1010 .... @rnadm SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm +# usad8 is usada8 w/ ra=15 +USADA8 1111 1011 0111 .... .... .... 0000 .... @rnadm + # Data-processing (two source registers) QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm @@ -254,6 +272,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=%imm16_16_0 + UDF 1111 0111 1111 ---- 1010 ---- ---- ---- } # Load/store (register, immediate, literal) From patchwork Wed Sep 4 19:30:14 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:14 -0700 Message-Id: <20190904193059.26202-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v4 24/69] target/arm: Convert Parallel addition and subtraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 229 ++++++++++++++++++++--------------------- target/arm/a32.decode | 44 ++++++++ target/arm/t32.decode | 44 ++++++++ 3 files changed, 200 insertions(+), 117 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 1c50ea232a..181d3d77f0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -648,99 +648,6 @@ static inline void gen_arm_shift_reg(TCGv_i32 var, int shiftop, tcg_temp_free_i32(shift); } -#define PAS_OP(pfx) \ - switch (op2) { \ - case 0: gen_pas_helper(glue(pfx,add16)); break; \ - case 1: gen_pas_helper(glue(pfx,addsubx)); break; \ - case 2: gen_pas_helper(glue(pfx,subaddx)); break; \ - case 3: gen_pas_helper(glue(pfx,sub16)); break; \ - case 4: gen_pas_helper(glue(pfx,add8)); break; \ - case 7: gen_pas_helper(glue(pfx,sub8)); break; \ - } -static void gen_arm_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b) -{ - TCGv_ptr tmp; - - switch (op1) { -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) - case 1: - tmp = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(s) - tcg_temp_free_ptr(tmp); - break; - case 5: - tmp = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(u) - tcg_temp_free_ptr(tmp); - break; -#undef gen_pas_helper -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) - case 2: - PAS_OP(q); - break; - case 3: - PAS_OP(sh); - break; - case 6: - PAS_OP(uq); - break; - case 7: - PAS_OP(uh); - break; -#undef gen_pas_helper - } -} -#undef PAS_OP - -/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */ -#define PAS_OP(pfx) \ - switch (op1) { \ - case 0: gen_pas_helper(glue(pfx,add8)); break; \ - case 1: gen_pas_helper(glue(pfx,add16)); break; \ - case 2: gen_pas_helper(glue(pfx,addsubx)); break; \ - case 4: gen_pas_helper(glue(pfx,sub8)); break; \ - case 5: gen_pas_helper(glue(pfx,sub16)); break; \ - case 6: gen_pas_helper(glue(pfx,subaddx)); break; \ - } -static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b) -{ - TCGv_ptr tmp; - - switch (op2) { -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) - case 0: - tmp = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(s) - tcg_temp_free_ptr(tmp); - break; - case 4: - tmp = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(u) - tcg_temp_free_ptr(tmp); - break; -#undef gen_pas_helper -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) - case 1: - PAS_OP(q); - break; - case 2: - PAS_OP(sh); - break; - case 5: - PAS_OP(uq); - break; - case 6: - PAS_OP(uh); - break; -#undef gen_pas_helper - } -} -#undef PAS_OP - /* * Generate a conditional based on ARM condition code cc. * This is common between ARM and Aarch64 targets. @@ -9318,6 +9225,114 @@ static bool trans_UDF(DisasContext *s, arg_UDF *a) return true; } +/* + * Parallel addition and subtraction + */ + +static bool op_par_addsub(DisasContext *s, arg_rrr *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 t0, t1; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t0 = load_reg(s, a->rn); + t1 = load_reg(s, a->rm); + + gen(t0, t0, t1); + + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +static bool op_par_addsub_ge(DisasContext *s, arg_rrr *a, + void (*gen)(TCGv_i32, TCGv_i32, + TCGv_i32, TCGv_ptr)) +{ + TCGv_i32 t0, t1; + TCGv_ptr ge; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t0 = load_reg(s, a->rn); + t1 = load_reg(s, a->rm); + + ge = tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ge, cpu_env, offsetof(CPUARMState, GE)); + gen(t0, t0, t1, ge); + + tcg_temp_free_ptr(ge); + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +#define DO_PAR_ADDSUB(NAME, helper) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_par_addsub(s, a, helper); \ +} + +#define DO_PAR_ADDSUB_GE(NAME, helper) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_par_addsub_ge(s, a, helper); \ +} + +DO_PAR_ADDSUB_GE(SADD16, gen_helper_sadd16) +DO_PAR_ADDSUB_GE(SASX, gen_helper_saddsubx) +DO_PAR_ADDSUB_GE(SSAX, gen_helper_ssubaddx) +DO_PAR_ADDSUB_GE(SSUB16, gen_helper_ssub16) +DO_PAR_ADDSUB_GE(SADD8, gen_helper_sadd8) +DO_PAR_ADDSUB_GE(SSUB8, gen_helper_ssub8) + +DO_PAR_ADDSUB_GE(UADD16, gen_helper_uadd16) +DO_PAR_ADDSUB_GE(UASX, gen_helper_uaddsubx) +DO_PAR_ADDSUB_GE(USAX, gen_helper_usubaddx) +DO_PAR_ADDSUB_GE(USUB16, gen_helper_usub16) +DO_PAR_ADDSUB_GE(UADD8, gen_helper_uadd8) +DO_PAR_ADDSUB_GE(USUB8, gen_helper_usub8) + +DO_PAR_ADDSUB(QADD16, gen_helper_qadd16) +DO_PAR_ADDSUB(QASX, gen_helper_qaddsubx) +DO_PAR_ADDSUB(QSAX, gen_helper_qsubaddx) +DO_PAR_ADDSUB(QSUB16, gen_helper_qsub16) +DO_PAR_ADDSUB(QADD8, gen_helper_qadd8) +DO_PAR_ADDSUB(QSUB8, gen_helper_qsub8) + +DO_PAR_ADDSUB(UQADD16, gen_helper_uqadd16) +DO_PAR_ADDSUB(UQASX, gen_helper_uqaddsubx) +DO_PAR_ADDSUB(UQSAX, gen_helper_uqsubaddx) +DO_PAR_ADDSUB(UQSUB16, gen_helper_uqsub16) +DO_PAR_ADDSUB(UQADD8, gen_helper_uqadd8) +DO_PAR_ADDSUB(UQSUB8, gen_helper_uqsub8) + +DO_PAR_ADDSUB(SHADD16, gen_helper_shadd16) +DO_PAR_ADDSUB(SHASX, gen_helper_shaddsubx) +DO_PAR_ADDSUB(SHSAX, gen_helper_shsubaddx) +DO_PAR_ADDSUB(SHSUB16, gen_helper_shsub16) +DO_PAR_ADDSUB(SHADD8, gen_helper_shadd8) +DO_PAR_ADDSUB(SHSUB8, gen_helper_shsub8) + +DO_PAR_ADDSUB(UHADD16, gen_helper_uhadd16) +DO_PAR_ADDSUB(UHASX, gen_helper_uhaddsubx) +DO_PAR_ADDSUB(UHSAX, gen_helper_uhsubaddx) +DO_PAR_ADDSUB(UHSUB16, gen_helper_uhsub16) +DO_PAR_ADDSUB(UHADD8, gen_helper_uhadd8) +DO_PAR_ADDSUB(UHSUB8, gen_helper_uhsub8) + +#undef DO_PAR_ADDSUB +#undef DO_PAR_ADDSUB_GE + /* * Legacy decoder. */ @@ -9630,16 +9645,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) rs = (insn >> 8) & 0xf; switch ((insn >> 23) & 3) { case 0: /* Parallel add/subtract. */ - op1 = (insn >> 20) & 7; - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - sh = (insn >> 5) & 7; - if ((op1 & 3) == 0 || sh == 5 || sh == 6) - goto illegal_op; - gen_arm_parallel_addsub(op1, sh, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + /* Done by decodetree */ + goto illegal_op; case 1: if ((insn & 0x00700020) == 0) { /* Halfword pack. */ @@ -10432,20 +10439,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } store_reg(s, rd, tmp); break; - case 2: /* SIMD add/subtract. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - op = (insn >> 20) & 7; - shift = (insn >> 4) & 7; - if ((op & 3) == 3 || (shift & 3) == 3) - goto illegal_op; - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - gen_thumb2_parallel_addsub(op, shift, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + case 2: /* SIMD add/subtract, in decodetree */ + goto illegal_op; case 3: /* Other data processing. */ op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7); if (op < 4) { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 285c08ca22..4dfd8133f7 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -410,3 +410,47 @@ BFCI ---- 0111 110 msb:5 rd:4 lsb:5 001 rn:4 &bfi # While we could get UDEF by not including this, add the pattern for # documentation and to conflict with any other typos in this file. UDF 1110 0111 1111 ---- ---- ---- 1111 ---- + +# Parallel addition and subtraction + +SADD16 .... 0110 0001 .... .... 1111 0001 .... @rndm +SASX .... 0110 0001 .... .... 1111 0011 .... @rndm +SSAX .... 0110 0001 .... .... 1111 0101 .... @rndm +SSUB16 .... 0110 0001 .... .... 1111 0111 .... @rndm +SADD8 .... 0110 0001 .... .... 1111 1001 .... @rndm +SSUB8 .... 0110 0001 .... .... 1111 1111 .... @rndm + +QADD16 .... 0110 0010 .... .... 1111 0001 .... @rndm +QASX .... 0110 0010 .... .... 1111 0011 .... @rndm +QSAX .... 0110 0010 .... .... 1111 0101 .... @rndm +QSUB16 .... 0110 0010 .... .... 1111 0111 .... @rndm +QADD8 .... 0110 0010 .... .... 1111 1001 .... @rndm +QSUB8 .... 0110 0010 .... .... 1111 1111 .... @rndm + +SHADD16 .... 0110 0011 .... .... 1111 0001 .... @rndm +SHASX .... 0110 0011 .... .... 1111 0011 .... @rndm +SHSAX .... 0110 0011 .... .... 1111 0101 .... @rndm +SHSUB16 .... 0110 0011 .... .... 1111 0111 .... @rndm +SHADD8 .... 0110 0011 .... .... 1111 1001 .... @rndm +SHSUB8 .... 0110 0011 .... .... 1111 1111 .... @rndm + +UADD16 .... 0110 0101 .... .... 1111 0001 .... @rndm +UASX .... 0110 0101 .... .... 1111 0011 .... @rndm +USAX .... 0110 0101 .... .... 1111 0101 .... @rndm +USUB16 .... 0110 0101 .... .... 1111 0111 .... @rndm +UADD8 .... 0110 0101 .... .... 1111 1001 .... @rndm +USUB8 .... 0110 0101 .... .... 1111 1111 .... @rndm + +UQADD16 .... 0110 0110 .... .... 1111 0001 .... @rndm +UQASX .... 0110 0110 .... .... 1111 0011 .... @rndm +UQSAX .... 0110 0110 .... .... 1111 0101 .... @rndm +UQSUB16 .... 0110 0110 .... .... 1111 0111 .... @rndm +UQADD8 .... 0110 0110 .... .... 1111 1001 .... @rndm +UQSUB8 .... 0110 0110 .... .... 1111 1111 .... @rndm + +UHADD16 .... 0110 0111 .... .... 1111 0001 .... @rndm +UHASX .... 0110 0111 .... .... 1111 0011 .... @rndm +UHSAX .... 0110 0111 .... .... 1111 0101 .... @rndm +UHSUB16 .... 0110 0111 .... .... 1111 0111 .... @rndm +UHADD8 .... 0110 0111 .... .... 1111 1001 .... @rndm +UHSUB8 .... 0110 0111 .... .... 1111 1111 .... @rndm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 682fc5c2c4..c899c56766 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -457,3 +457,47 @@ LDAEXD_t32 1110 1000 1101 .... .... .... 1111 1111 @ldrex_d LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0 LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0 LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0 + +# Parallel addition and subtraction + +SADD8 1111 1010 1000 .... 1111 .... 0000 .... @rndm +QADD8 1111 1010 1000 .... 1111 .... 0001 .... @rndm +SHADD8 1111 1010 1000 .... 1111 .... 0010 .... @rndm +UADD8 1111 1010 1000 .... 1111 .... 0100 .... @rndm +UQADD8 1111 1010 1000 .... 1111 .... 0101 .... @rndm +UHADD8 1111 1010 1000 .... 1111 .... 0110 .... @rndm + +SADD16 1111 1010 1001 .... 1111 .... 0000 .... @rndm +QADD16 1111 1010 1001 .... 1111 .... 0001 .... @rndm +SHADD16 1111 1010 1001 .... 1111 .... 0010 .... @rndm +UADD16 1111 1010 1001 .... 1111 .... 0100 .... @rndm +UQADD16 1111 1010 1001 .... 1111 .... 0101 .... @rndm +UHADD16 1111 1010 1001 .... 1111 .... 0110 .... @rndm + +SASX 1111 1010 1010 .... 1111 .... 0000 .... @rndm +QASX 1111 1010 1010 .... 1111 .... 0001 .... @rndm +SHASX 1111 1010 1010 .... 1111 .... 0010 .... @rndm +UASX 1111 1010 1010 .... 1111 .... 0100 .... @rndm +UQASX 1111 1010 1010 .... 1111 .... 0101 .... @rndm +UHASX 1111 1010 1010 .... 1111 .... 0110 .... @rndm + +SSUB8 1111 1010 1100 .... 1111 .... 0000 .... @rndm +QSUB8 1111 1010 1100 .... 1111 .... 0001 .... @rndm +SHSUB8 1111 1010 1100 .... 1111 .... 0010 .... @rndm +USUB8 1111 1010 1100 .... 1111 .... 0100 .... @rndm +UQSUB8 1111 1010 1100 .... 1111 .... 0101 .... @rndm +UHSUB8 1111 1010 1100 .... 1111 .... 0110 .... @rndm + +SSUB16 1111 1010 1101 .... 1111 .... 0000 .... @rndm +QSUB16 1111 1010 1101 .... 1111 .... 0001 .... @rndm +SHSUB16 1111 1010 1101 .... 1111 .... 0010 .... @rndm +USUB16 1111 1010 1101 .... 1111 .... 0100 .... @rndm +UQSUB16 1111 1010 1101 .... 1111 .... 0101 .... @rndm +UHSUB16 1111 1010 1101 .... 1111 .... 0110 .... @rndm + +SSAX 1111 1010 1110 .... 1111 .... 0000 .... @rndm +QSAX 1111 1010 1110 .... 1111 .... 0001 .... @rndm +SHSAX 1111 1010 1110 .... 1111 .... 0010 .... @rndm +USAX 1111 1010 1110 .... 1111 .... 0100 .... @rndm +UQSAX 1111 1010 1110 .... 1111 .... 0101 .... @rndm +UHSAX 1111 1010 1110 .... 1111 .... 0110 .... @rndm From patchwork Wed Sep 4 19:30:15 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:15 -0700 Message-Id: <20190904193059.26202-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v4 25/69] target/arm: Convert packing, unpacking, saturation, and reversal X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 541 ++++++++++++++++++----------------------- target/arm/a32.decode | 32 +++ target/arm/t32.decode | 37 ++- 3 files changed, 300 insertions(+), 310 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 181d3d77f0..a6de23c6d3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -355,7 +355,7 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) } /* Byteswap each halfword. */ -static void gen_rev16(TCGv_i32 var) +static void gen_rev16(TCGv_i32 dest, TCGv_i32 var) { TCGv_i32 tmp = tcg_temp_new_i32(); TCGv_i32 mask = tcg_const_i32(0x00ff00ff); @@ -363,17 +363,17 @@ static void gen_rev16(TCGv_i32 var) tcg_gen_and_i32(tmp, tmp, mask); tcg_gen_and_i32(var, var, mask); tcg_gen_shli_i32(var, var, 8); - tcg_gen_or_i32(var, var, tmp); + tcg_gen_or_i32(dest, var, tmp); tcg_temp_free_i32(mask); tcg_temp_free_i32(tmp); } /* Byteswap low halfword and sign extend. */ -static void gen_revsh(TCGv_i32 var) +static void gen_revsh(TCGv_i32 dest, TCGv_i32 var) { tcg_gen_ext16u_i32(var, var); tcg_gen_bswap16_i32(var, var); - tcg_gen_ext16s_i32(var, var); + tcg_gen_ext16s_i32(dest, var); } /* 32x32->64 multiply. Marks inputs as dead. */ @@ -426,7 +426,7 @@ static void gen_swap_half(TCGv_i32 var) t0 = (t0 + t1) ^ tmp; */ -static void gen_add16(TCGv_i32 t0, TCGv_i32 t1) +static void gen_add16(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) { TCGv_i32 tmp = tcg_temp_new_i32(); tcg_gen_xor_i32(tmp, t0, t1); @@ -434,9 +434,8 @@ static void gen_add16(TCGv_i32 t0, TCGv_i32 t1) tcg_gen_andi_i32(t0, t0, ~0x8000); tcg_gen_andi_i32(t1, t1, ~0x8000); tcg_gen_add_i32(t0, t0, t1); - tcg_gen_xor_i32(t0, t0, tmp); + tcg_gen_xor_i32(dest, t0, tmp); tcg_temp_free_i32(tmp); - tcg_temp_free_i32(t1); } /* Set N and Z flags from var. */ @@ -6356,7 +6355,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } break; case NEON_2RM_VREV16: - gen_rev16(tmp); + gen_rev16(tmp, tmp); break; case NEON_2RM_VCLS: switch (size) { @@ -9333,13 +9332,225 @@ DO_PAR_ADDSUB(UHSUB8, gen_helper_uhsub8) #undef DO_PAR_ADDSUB #undef DO_PAR_ADDSUB_GE +/* + * Packing, unpacking, saturation, and reversal + */ + +static bool trans_PKH(DisasContext *s, arg_PKH *a) +{ + TCGv_i32 tn, tm; + int shift = a->imm; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + tn = load_reg(s, a->rn); + tm = load_reg(s, a->rm); + if (a->tb) { + /* PKHTB */ + if (shift == 0) { + shift = 31; + } + tcg_gen_sari_i32(tm, tm, shift); + tcg_gen_deposit_i32(tn, tn, tm, 0, 16); + } else { + /* PKHBT */ + tcg_gen_shli_i32(tm, tm, shift); + tcg_gen_deposit_i32(tn, tm, tn, 0, 16); + } + tcg_temp_free_i32(tm); + store_reg(s, a->rd, tn); + return true; +} + +static bool op_sat(DisasContext *s, arg_sat *a, + void (*gen)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp, satimm; + int shift = a->imm; + + if (!ENABLE_ARCH_6) { + return false; + } + + tmp = load_reg(s, a->rn); + if (a->sh) { + tcg_gen_sari_i32(tmp, tmp, shift ? shift : 31); + } else { + tcg_gen_shli_i32(tmp, tmp, shift); + } + + satimm = tcg_const_i32(a->satimm); + gen(tmp, cpu_env, tmp, satimm); + tcg_temp_free_i32(satimm); + + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_SSAT(DisasContext *s, arg_sat *a) +{ + return op_sat(s, a, gen_helper_ssat); +} + +static bool trans_USAT(DisasContext *s, arg_sat *a) +{ + return op_sat(s, a, gen_helper_usat); +} + +static bool trans_SSAT16(DisasContext *s, arg_sat *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_sat(s, a, gen_helper_ssat16); +} + +static bool trans_USAT16(DisasContext *s, arg_sat *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_sat(s, a, gen_helper_usat16); +} + +static bool op_xta(DisasContext *s, arg_rrr_rot *a, + void (*gen_extract)(TCGv_i32, TCGv_i32), + void (*gen_add)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_6) { + return false; + } + + tmp = load_reg(s, a->rm); + /* + * TODO: In many cases we could do a shift instead of a rotate. + * Combined with a simple extend, that becomes an extract. + */ + tcg_gen_rotri_i32(tmp, tmp, a->rot * 8); + gen_extract(tmp, tmp); + + if (a->rn != 15) { + TCGv_i32 tmp2 = load_reg(s, a->rn); + gen_add(tmp, tmp, tmp2); + tcg_temp_free_i32(tmp2); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_SXTAB(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext8s_i32, tcg_gen_add_i32); +} + +static bool trans_SXTAH(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext16s_i32, tcg_gen_add_i32); +} + +static bool trans_SXTAB16(DisasContext *s, arg_rrr_rot *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_xta(s, a, gen_helper_sxtb16, gen_add16); +} + +static bool trans_UXTAB(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext8u_i32, tcg_gen_add_i32); +} + +static bool trans_UXTAH(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext16u_i32, tcg_gen_add_i32); +} + +static bool trans_UXTAB16(DisasContext *s, arg_rrr_rot *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_xta(s, a, gen_helper_uxtb16, gen_add16); +} + +static bool trans_SEL(DisasContext *s, arg_rrr *a) +{ + TCGv_i32 t1, t2, t3; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + t3 = tcg_temp_new_i32(); + tcg_gen_ld_i32(t3, cpu_env, offsetof(CPUARMState, GE)); + gen_helper_sel_flags(t1, t3, t1, t2); + tcg_temp_free_i32(t3); + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool op_rr(DisasContext *s, arg_rr *a, + void (*gen)(TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp; + + tmp = load_reg(s, a->rm); + gen(tmp, tmp); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_REV(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_rr(s, a, tcg_gen_bswap32_i32); +} + +static bool trans_REV16(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_rr(s, a, gen_rev16); +} + +static bool trans_REVSH(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_rr(s, a, gen_revsh); +} + +static bool trans_RBIT(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6T2) { + return false; + } + return op_rr(s, a, gen_helper_rbit); +} + /* * Legacy decoder. */ static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh; + unsigned int cond, val, op1, i, rm, rs, rn, rd; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 tmp3; @@ -9648,112 +9859,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* Done by decodetree */ goto illegal_op; case 1: - if ((insn & 0x00700020) == 0) { - /* Halfword pack. */ - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - shift = (insn >> 7) & 0x1f; - if (insn & (1 << 6)) { - /* pkhtb */ - if (shift == 0) { - shift = 31; - } - tcg_gen_sari_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16); - } else { - /* pkhbt */ - tcg_gen_shli_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x00200020) == 0x00200000) { - /* [us]sat */ - tmp = load_reg(s, rm); - shift = (insn >> 7) & 0x1f; - if (insn & (1 << 6)) { - if (shift == 0) - shift = 31; - tcg_gen_sari_i32(tmp, tmp, shift); - } else { - tcg_gen_shli_i32(tmp, tmp, shift); - } - sh = (insn >> 16) & 0x1f; - tmp2 = tcg_const_i32(sh); - if (insn & (1 << 22)) - gen_helper_usat(tmp, cpu_env, tmp, tmp2); - else - gen_helper_ssat(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x00300fe0) == 0x00200f20) { - /* [us]sat16 */ - tmp = load_reg(s, rm); - sh = (insn >> 16) & 0x1f; - tmp2 = tcg_const_i32(sh); - if (insn & (1 << 22)) - gen_helper_usat16(tmp, cpu_env, tmp, tmp2); - else - gen_helper_ssat16(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x00700fe0) == 0x00000fa0) { - /* Select bytes. */ - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - tmp3 = tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE)); - gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); - tcg_temp_free_i32(tmp3); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x000003e0) == 0x00000060) { - tmp = load_reg(s, rm); - shift = (insn >> 10) & 3; - /* ??? In many cases it's not necessary to do a - rotate, a shift is sufficient. */ - tcg_gen_rotri_i32(tmp, tmp, shift * 8); - op1 = (insn >> 20) & 7; - switch (op1) { - case 0: gen_sxtb16(tmp); break; - case 2: gen_sxtb(tmp); break; - case 3: gen_sxth(tmp); break; - case 4: gen_uxtb16(tmp); break; - case 6: gen_uxtb(tmp); break; - case 7: gen_uxth(tmp); break; - default: goto illegal_op; - } - if (rn != 15) { - tmp2 = load_reg(s, rn); - if ((op1 & 3) == 0) { - gen_add16(tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - } - store_reg(s, rd, tmp); - } else if ((insn & 0x003f0f60) == 0x003f0f20) { - /* rev */ - tmp = load_reg(s, rm); - if (insn & (1 << 22)) { - if (insn & (1 << 7)) { - gen_revsh(tmp); - } else { - ARCH(6T2); - gen_helper_rbit(tmp, tmp); - } - } else { - if (insn & (1 << 7)) - gen_rev16(tmp); - else - tcg_gen_bswap32_i32(tmp, tmp); - } - store_reg(s, rd, tmp); - } else { - goto illegal_op; - } - break; + /* Halfword pack, [US]SAT, [US]SAT16, SEL, REV et al */ + /* Done by decodetree */ + goto illegal_op; case 2: /* Multiplies (Type 3). */ switch ((insn >> 20) & 0x7) { case 5: @@ -10098,7 +10206,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t imm, shift, offset; + uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10353,151 +10461,18 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } break; case 5: - - op = (insn >> 21) & 0xf; - if (op == 6) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - /* Halfword pack. */ - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3); - if (insn & (1 << 5)) { - /* pkhtb */ - if (shift == 0) { - shift = 31; - } - tcg_gen_sari_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16); - } else { - /* pkhbt */ - tcg_gen_shli_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else { - /* Data processing register constant shift. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } - break; + /* All in decodetree */ + goto illegal_op; case 13: /* Misc data processing. */ op = ((insn >> 22) & 6) | ((insn >> 7) & 1); if (op < 4 && (insn & 0xf000) != 0xf000) goto illegal_op; switch (op) { case 0: /* Register controlled shift, in decodetree */ - goto illegal_op; - case 1: /* Sign/zero extend. */ - op = (insn >> 20) & 7; - switch (op) { - case 0: /* SXTAH, SXTH */ - case 1: /* UXTAH, UXTH */ - case 4: /* SXTAB, SXTB */ - case 5: /* UXTAB, UXTB */ - break; - case 2: /* SXTAB16, SXTB16 */ - case 3: /* UXTAB16, UXTB16 */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - break; - default: - goto illegal_op; - } - if (rn != 15) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - } - tmp = load_reg(s, rm); - shift = (insn >> 4) & 3; - /* ??? In many cases it's not necessary to do a - rotate, a shift is sufficient. */ - tcg_gen_rotri_i32(tmp, tmp, shift * 8); - op = (insn >> 20) & 7; - switch (op) { - case 0: gen_sxth(tmp); break; - case 1: gen_uxth(tmp); break; - case 2: gen_sxtb16(tmp); break; - case 3: gen_uxtb16(tmp); break; - case 4: gen_sxtb(tmp); break; - case 5: gen_uxtb(tmp); break; - default: - g_assert_not_reached(); - } - if (rn != 15) { - tmp2 = load_reg(s, rn); - if ((op >> 1) == 1) { - gen_add16(tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - } - store_reg(s, rd, tmp); - break; + case 1: /* Sign/zero extend, in decodetree */ case 2: /* SIMD add/subtract, in decodetree */ + case 3: /* Other data processing, in decodetree */ goto illegal_op; - case 3: /* Other data processing. */ - op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7); - if (op < 4) { - /* Saturating add/subtract. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } else { - switch (op) { - case 0x0a: /* rbit */ - case 0x08: /* rev */ - case 0x09: /* rev16 */ - case 0x0b: /* revsh */ - break; - case 0x10: /* sel */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - break; - case 0x18: /* clz, in decodetree */ - case 0x20: /* crc32/crc32c, in decodetree */ - case 0x21: - case 0x22: - case 0x28: - case 0x29: - case 0x2a: - goto illegal_op; - default: - goto illegal_op; - } - tmp = load_reg(s, rn); - switch (op) { - case 0x0a: /* rbit */ - gen_helper_rbit(tmp, tmp); - break; - case 0x08: /* rev */ - tcg_gen_bswap32_i32(tmp, tmp); - break; - case 0x09: /* rev16 */ - gen_rev16(tmp); - break; - case 0x0b: /* revsh */ - gen_revsh(tmp); - break; - case 0x10: /* sel */ - tmp2 = load_reg(s, rm); - tmp3 = tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE)); - gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); - tcg_temp_free_i32(tmp3); - tcg_temp_free_i32(tmp2); - break; - default: - g_assert_not_reached(); - } - } - store_reg(s, rd, tmp); - break; case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */ switch ((insn >> 20) & 7) { case 0: /* 32 x 32 -> 32 */ @@ -10851,60 +10826,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) * - Data-processing (plain binary immediate) */ if (insn & (1 << 24)) { - if (insn & (1 << 20)) - goto illegal_op; - /* Bitfield/Saturate. */ - op = (insn >> 21) & 7; - imm = insn & 0x1f; - shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); - if (rn == 15) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp = load_reg(s, rn); - } - switch (op) { - case 2: /* Signed bitfield extract, in decodetree */ - case 6: /* Unsigned bitfield extract, in decodetree */ - case 3: /* Bitfield insert/clear, in decodetree */ - case 7: - goto illegal_op; - default: /* Saturate. */ - if (op & 1) { - tcg_gen_sari_i32(tmp, tmp, shift); - } else { - tcg_gen_shli_i32(tmp, tmp, shift); - } - tmp2 = tcg_const_i32(imm); - if (op & 4) { - /* Unsigned. */ - if ((op & 1) && shift == 0) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - goto illegal_op; - } - gen_helper_usat16(tmp, cpu_env, tmp, tmp2); - } else { - gen_helper_usat(tmp, cpu_env, tmp, tmp2); - } - } else { - /* Signed. */ - if ((op & 1) && shift == 0) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - goto illegal_op; - } - gen_helper_ssat16(tmp, cpu_env, tmp, tmp2); - } else { - gen_helper_ssat(tmp, cpu_env, tmp, tmp2); - } - } - tcg_temp_free_i32(tmp2); - break; - } - store_reg(s, rd, tmp); + /* Bitfield/Saturate, in decodetree */ + goto illegal_op; } else { imm = ((insn & 0x04000000) >> 15) | ((insn & 0x7000) >> 4) | (insn & 0xff); @@ -11596,8 +11519,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) tmp = load_reg(s, rn); switch (op1) { case 0: tcg_gen_bswap32_i32(tmp, tmp); break; - case 1: gen_rev16(tmp); break; - case 3: gen_revsh(tmp); break; + case 1: gen_rev16(tmp, tmp); break; + case 3: gen_revsh(tmp, tmp); break; default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 4dfd8133f7..4990eb3839 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -28,6 +28,7 @@ &s_rri_rot s rn rd imm rot &s_rrrr s rd rn rm ra &rrrr rd rn rm ra +&rrr_rot rd rn rm rot &rrr rd rn rm &rr rd rm &ri rd imm @@ -43,6 +44,8 @@ &ldrex rn rt rt2 imm &bfx rd rn lsb widthm1 &bfi rd rn lsb msb +&sat rd rn satimm imm sh +&pkh rd rn rm imm tb # Data-processing (register) @@ -454,3 +457,32 @@ UHSAX .... 0110 0111 .... .... 1111 0101 .... @rndm UHSUB16 .... 0110 0111 .... .... 1111 0111 .... @rndm UHADD8 .... 0110 0111 .... .... 1111 1001 .... @rndm UHSUB8 .... 0110 0111 .... .... 1111 1111 .... @rndm + +# Packing, unpacking, saturation, and reversal + +PKH ---- 0110 1000 rn:4 rd:4 imm:5 tb:1 01 rm:4 &pkh + +@sat ---- .... ... satimm:5 rd:4 imm:5 sh:1 .. rn:4 &sat +@sat16 ---- .... .... satimm:4 rd:4 .... .... rn:4 \ + &sat imm=0 sh=0 + +SSAT .... 0110 101. .... .... .... ..01 .... @sat +USAT .... 0110 111. .... .... .... ..01 .... @sat + +SSAT16 .... 0110 1010 .... .... 1111 0011 .... @sat16 +USAT16 .... 0110 1110 .... .... 1111 0011 .... @sat16 + +@rrr_rot ---- .... .... rn:4 rd:4 rot:2 ...... rm:4 &rrr_rot + +SXTAB16 .... 0110 1000 .... .... ..00 0111 .... @rrr_rot +SXTAB .... 0110 1010 .... .... ..00 0111 .... @rrr_rot +SXTAH .... 0110 1011 .... .... ..00 0111 .... @rrr_rot +UXTAB16 .... 0110 1100 .... .... ..00 0111 .... @rrr_rot +UXTAB .... 0110 1110 .... .... ..00 0111 .... @rrr_rot +UXTAH .... 0110 1111 .... .... ..00 0111 .... @rrr_rot + +SEL .... 0110 1000 .... .... 1111 1011 .... @rndm +REV .... 0110 1011 1111 .... 1111 0011 .... @rdm +REV16 .... 0110 1011 1111 .... 1111 1011 .... @rdm +REVSH .... 0110 1111 1111 .... 1111 1011 .... @rdm +RBIT .... 0110 1111 1111 .... 1111 0011 .... @rdm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index c899c56766..71f6d728f2 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -25,6 +25,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra +&rrr_rot !extern rd rn rm rot &rrr !extern rd rn rm &rr !extern rd rm &ri !extern rd imm @@ -40,6 +41,8 @@ &ldrex !extern rn rt rt2 imm &bfx !extern rd rn lsb widthm1 &bfi !extern rd rn lsb msb +&sat !extern rd rn satimm imm sh +&pkh !extern rd rn rm imm tb # Data-processing (register) @@ -69,7 +72,8 @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi TEQ_xrri 1110101 0100 1 .... 0 ... 1111 .... .... @S_xrr_shi EOR_rrri 1110101 0100 . .... 0 ... .... .... .... @s_rrr_shi } -# PKHBT, PKHTB at opc1 = 0110 +PKH 1110101 0110 0 rn:4 0 ... rd:4 .. tb:1 0 rm:4 \ + &pkh imm=%imm5_12_6 { CMN_xrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi @@ -148,6 +152,20 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot # Saturate, bitfield +@sat .... .... .. sh:1 . rn:4 . ... rd:4 .. . satimm:5 \ + &sat imm=%imm5_12_6 +@sat16 .... .... .. . . rn:4 . ... rd:4 .. . satimm:5 \ + &sat sh=0 imm=0 + +{ + SSAT16 1111 0011 001 0 .... 0 000 .... 00 0 ..... @sat16 + SSAT 1111 0011 00. 0 .... 0 ... .... .. 0 ..... @sat +} +{ + USAT16 1111 0011 101 0 .... 0 000 .... 00 0 ..... @sat16 + USAT 1111 0011 10. 0 .... 0 ... .... .. 0 ..... @sat +} + @bfx .... .... ... . rn:4 . ... rd:4 .. . widthm1:5 \ &bfx lsb=%imm5_12_6 @bfi .... .... ... . rn:4 . ... rd:4 .. . msb:5 \ @@ -224,7 +242,13 @@ CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm +SEL 1111 1010 1010 .... 1111 .... 1000 .... @rndm + # Note rn != rm is CONSTRAINED UNPREDICTABLE; we choose to ignore rn. +REV 1111 1010 1001 ---- 1111 .... 1000 .... @rdm +REV16 1111 1010 1001 ---- 1111 .... 1001 .... @rdm +RBIT 1111 1010 1001 ---- 1111 .... 1010 .... @rdm +REVSH 1111 1010 1001 ---- 1111 .... 1011 .... @rdm CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm # Branches and miscellaneous control @@ -501,3 +525,14 @@ SHSAX 1111 1010 1110 .... 1111 .... 0010 .... @rndm USAX 1111 1010 1110 .... 1111 .... 0100 .... @rndm UQSAX 1111 1010 1110 .... 1111 .... 0101 .... @rndm UHSAX 1111 1010 1110 .... 1111 .... 0110 .... @rndm + +# Register extends + +@rrr_rot .... .... .... rn:4 .... rd:4 .. rot:2 rm:4 &rrr_rot + +SXTAH 1111 1010 0000 .... 1111 .... 10.. .... @rrr_rot +UXTAH 1111 1010 0001 .... 1111 .... 10.. .... @rrr_rot +SXTAB16 1111 1010 0010 .... 1111 .... 10.. .... @rrr_rot +UXTAB16 1111 1010 0011 .... 1111 .... 10.. .... @rrr_rot +SXTAB 1111 1010 0100 .... 1111 .... 10.. .... @rrr_rot +UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot From patchwork Wed Sep 4 19:30:16 2019 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::430 Subject: [Qemu-devel] [PATCH v4 26/69] target/arm: Convert Signed multiply, signed and unsigned divide X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 490 ++++++++++++++++++----------------------- target/arm/a32.decode | 22 ++ target/arm/t32.decode | 18 ++ 3 files changed, 258 insertions(+), 272 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index a6de23c6d3..5b9b303467 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9544,18 +9544,228 @@ static bool trans_RBIT(DisasContext *s, arg_rr *a) return op_rr(s, a, gen_helper_rbit); } +/* + * Signed multiply, signed and unsigned divide + */ + +static bool op_smlad(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub) +{ + TCGv_i32 t1, t2; + + if (!ENABLE_ARCH_6) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + if (m_swap) { + gen_swap_half(t2); + } + gen_smul_dual(t1, t2); + + if (sub) { + /* This subtraction cannot overflow. */ + tcg_gen_sub_i32(t1, t1, t2); + } else { + /* + * This addition cannot overflow 32 bits; however it may + * overflow considered as a signed operation, in which case + * we must set the Q flag. + */ + gen_helper_add_setq(t1, cpu_env, t1, t2); + } + tcg_temp_free_i32(t2); + + if (a->ra != 15) { + t2 = load_reg(s, a->ra); + gen_helper_add_setq(t1, cpu_env, t1, t2); + tcg_temp_free_i32(t2); + } + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_SMLAD(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, false, false); +} + +static bool trans_SMLADX(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, true, false); +} + +static bool trans_SMLSD(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, false, true); +} + +static bool trans_SMLSDX(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, true, true); +} + +static bool op_smlald(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub) +{ + TCGv_i32 t1, t2; + TCGv_i64 l1, l2; + + if (!ENABLE_ARCH_6) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + if (m_swap) { + gen_swap_half(t2); + } + gen_smul_dual(t1, t2); + + l1 = tcg_temp_new_i64(); + l2 = tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(l1, t1); + tcg_gen_ext_i32_i64(l2, t2); + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); + + if (sub) { + tcg_gen_sub_i64(l1, l1, l2); + } else { + tcg_gen_add_i64(l1, l1, l2); + } + tcg_temp_free_i64(l2); + + gen_addq(s, l1, a->ra, a->rd); + gen_storeq_reg(s, a->ra, a->rd, l1); + tcg_temp_free_i64(l1); + return true; +} + +static bool trans_SMLALD(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, false, false); +} + +static bool trans_SMLALDX(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, true, false); +} + +static bool trans_SMLSLD(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, false, true); +} + +static bool trans_SMLSLDX(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, true, true); +} + +static bool op_smmla(DisasContext *s, arg_rrrr *a, bool round, bool sub) +{ + TCGv_i32 t1, t2; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + tcg_gen_muls2_i32(t2, t1, t1, t2); + + if (a->ra != 15) { + TCGv_i32 t3 = load_reg(s, a->ra); + if (sub) { + /* + * For SMMLS, we need a 64-bit subtract. Borrow caused by + * a non-zero multiplicand lowpart, and the correct result + * lowpart for rounding. + */ + TCGv_i32 zero = tcg_const_i32(0); + tcg_gen_sub2_i32(t2, t1, zero, t3, t2, t1); + tcg_temp_free_i32(zero); + } else { + tcg_gen_add_i32(t1, t1, t3); + } + tcg_temp_free_i32(t3); + } + if (round) { + /* + * Adding 0x80000000 to the 64-bit quantity means that we have + * carry in to the high word when the low word has the msb set. + */ + tcg_gen_shri_i32(t2, t2, 31); + tcg_gen_add_i32(t1, t1, t2); + } + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_SMMLA(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, false, false); +} + +static bool trans_SMMLAR(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, true, false); +} + +static bool trans_SMMLS(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, false, true); +} + +static bool trans_SMMLSR(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, true, true); +} + +static bool op_div(DisasContext *s, arg_rrr *a, bool u) +{ + TCGv_i32 t1, t2; + + if (s->thumb + ? !dc_isar_feature(thumb_div, s) + : !dc_isar_feature(arm_div, s)) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + if (u) { + gen_helper_udiv(t1, t1, t2); + } else { + gen_helper_sdiv(t1, t1, t2); + } + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_SDIV(DisasContext *s, arg_rrr *a) +{ + return op_div(s, a, false); +} + +static bool trans_UDIV(DisasContext *s, arg_rrr *a) +{ + return op_div(s, a, true); +} + /* * Legacy decoder. */ static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, rm, rs, rn, rd; + unsigned int cond, val, op1, i, rn, rd; TCGv_i32 tmp; TCGv_i32 tmp2; - TCGv_i32 tmp3; TCGv_i32 addr; - TCGv_i64 tmp64; /* M variants do not implement ARM mode; this must raise the INVSTATE * UsageFault exception. @@ -9838,157 +10048,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) switch(op1) { case 0x0: case 0x1: - /* multiplies, extra load/stores */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - break; case 0x4: case 0x5: - goto do_ldst; case 0x6: case 0x7: - if (insn & (1 << 4)) { - ARCH(6); - /* Armv6 Media instructions. */ - rm = insn & 0xf; - rn = (insn >> 16) & 0xf; - rd = (insn >> 12) & 0xf; - rs = (insn >> 8) & 0xf; - switch ((insn >> 23) & 3) { - case 0: /* Parallel add/subtract. */ - /* Done by decodetree */ - goto illegal_op; - case 1: - /* Halfword pack, [US]SAT, [US]SAT16, SEL, REV et al */ - /* Done by decodetree */ - goto illegal_op; - case 2: /* Multiplies (Type 3). */ - switch ((insn >> 20) & 0x7) { - case 5: - if (((insn >> 6) ^ (insn >> 7)) & 1) { - /* op2 not 00x or 11x : UNDEF */ - goto illegal_op; - } - /* Signed multiply most significant [accumulate]. - (SMMUL, SMMLA, SMMLS) */ - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rs); - tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2); - - if (rd != 15) { - tmp3 = load_reg(s, rd); - if (insn & (1 << 6)) { - /* - * For SMMLS, we need a 64-bit subtract. - * Borrow caused by a non-zero multiplicand - * lowpart, and the correct result lowpart - * for rounding. - */ - TCGv_i32 zero = tcg_const_i32(0); - tcg_gen_sub2_i32(tmp2, tmp, zero, tmp3, - tmp2, tmp); - tcg_temp_free_i32(zero); - } else { - tcg_gen_add_i32(tmp, tmp, tmp3); - } - tcg_temp_free_i32(tmp3); - } - if (insn & (1 << 5)) { - /* - * Adding 0x80000000 to the 64-bit quantity - * means that we have carry in to the high - * word when the low word has the high bit set. - */ - tcg_gen_shri_i32(tmp2, tmp2, 31); - tcg_gen_add_i32(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rn, tmp); - break; - case 0: - case 4: - /* SMLAD, SMUAD, SMLSD, SMUSD, SMLALD, SMLSLD */ - if (insn & (1 << 7)) { - goto illegal_op; - } - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rs); - if (insn & (1 << 5)) - gen_swap_half(tmp2); - gen_smul_dual(tmp, tmp2); - if (insn & (1 << 22)) { - /* smlald, smlsld */ - TCGv_i64 tmp64_2; - - tmp64 = tcg_temp_new_i64(); - tmp64_2 = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_gen_ext_i32_i64(tmp64_2, tmp2); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - if (insn & (1 << 6)) { - tcg_gen_sub_i64(tmp64, tmp64, tmp64_2); - } else { - tcg_gen_add_i64(tmp64, tmp64, tmp64_2); - } - tcg_temp_free_i64(tmp64_2); - gen_addq(s, tmp64, rd, rn); - gen_storeq_reg(s, rd, rn, tmp64); - tcg_temp_free_i64(tmp64); - } else { - /* smuad, smusd, smlad, smlsd */ - if (insn & (1 << 6)) { - /* This subtraction cannot overflow. */ - tcg_gen_sub_i32(tmp, tmp, tmp2); - } else { - /* This addition cannot overflow 32 bits; - * however it may overflow considered as a - * signed operation, in which case we must set - * the Q flag. - */ - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - if (rd != 15) - { - tmp2 = load_reg(s, rd); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rn, tmp); - } - break; - case 1: - case 3: - /* SDIV, UDIV */ - if (!dc_isar_feature(arm_div, s)) { - goto illegal_op; - } - if (((insn >> 5) & 7) || (rd != 15)) { - goto illegal_op; - } - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rs); - if (insn & (1 << 21)) { - gen_helper_udiv(tmp, tmp, tmp2); - } else { - gen_helper_sdiv(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rn, tmp); - break; - default: - goto illegal_op; - } - break; - case 3: - /* USAD, BFI, BFC, SBFX, UBFX */ - /* Done by decodetree */ - goto illegal_op; - } - break; - } - do_ldst: /* All done in decodetree. Reach here for illegal ops. */ goto illegal_op; case 0x08: @@ -10210,9 +10273,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) uint32_t rd, rn, rm, rs; TCGv_i32 tmp; TCGv_i32 tmp2; - TCGv_i32 tmp3; TCGv_i32 addr; - TCGv_i64 tmp64; int op; /* @@ -10473,126 +10534,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 2: /* SIMD add/subtract, in decodetree */ case 3: /* Other data processing, in decodetree */ goto illegal_op; - case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */ - switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32 */ - case 1: /* 16 x 16 -> 32 */ - case 3: /* 32 * 16 -> 32msb */ - case 7: /* Unsigned sum of absolute differences. */ - /* in decodetree */ - goto illegal_op; - case 2: /* Dual multiply add. */ - case 4: /* Dual multiply subtract. */ - case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - break; - } - op = (insn >> 4) & 0xf; - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - switch ((insn >> 20) & 7) { - case 2: /* Dual multiply add. */ - case 4: /* Dual multiply subtract. */ - if (op) - gen_swap_half(tmp2); - gen_smul_dual(tmp, tmp2); - if (insn & (1 << 22)) { - /* This subtraction cannot overflow. */ - tcg_gen_sub_i32(tmp, tmp, tmp2); - } else { - /* This addition cannot overflow 32 bits; - * however it may overflow considered as a signed - * operation, in which case we must set the Q flag. - */ - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - if (rs != 15) - { - tmp2 = load_reg(s, rs); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; - case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ - tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2); - if (rs != 15) { - tmp3 = load_reg(s, rs); - if (insn & (1 << 20)) { - tcg_gen_add_i32(tmp, tmp, tmp3); - } else { - /* - * For SMMLS, we need a 64-bit subtract. - * Borrow caused by a non-zero multiplicand lowpart, - * and the correct result lowpart for rounding. - */ - TCGv_i32 zero = tcg_const_i32(0); - tcg_gen_sub2_i32(tmp2, tmp, zero, tmp3, tmp2, tmp); - tcg_temp_free_i32(zero); - } - tcg_temp_free_i32(tmp3); - } - if (insn & (1 << 4)) { - /* - * Adding 0x80000000 to the 64-bit quantity - * means that we have carry in to the high - * word when the low word has the high bit set. - */ - tcg_gen_shri_i32(tmp2, tmp2, 31); - tcg_gen_add_i32(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - break; - } - store_reg(s, rd, tmp); - break; - case 6: case 7: /* 64-bit multiply, Divide. */ - op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70); - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - if ((op & 0x50) == 0x10) { - /* sdiv, udiv */ - if (!dc_isar_feature(thumb_div, s)) { - goto illegal_op; - } - if (op & 0x20) - gen_helper_udiv(tmp, tmp, tmp2); - else - gen_helper_sdiv(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((op & 0xe) == 0xc) { - /* Dual multiply accumulate long. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - goto illegal_op; - } - if (op & 1) - gen_swap_half(tmp2); - gen_smul_dual(tmp, tmp2); - if (op & 0x10) { - tcg_gen_sub_i32(tmp, tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - /* BUGFIX */ - tmp64 = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_temp_free_i32(tmp); - gen_addq(s, tmp64, rs, rd); - gen_storeq_reg(s, rs, rd, tmp64); - tcg_temp_free_i64(tmp64); - } else { - /* Signed/unsigned 64-bit multiply, in decodetree */ - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - break; + case 4: case 5: + /* 32-bit multiply. Sum of absolute differences, in decodetree */ + goto illegal_op; + case 6: case 7: /* 64-bit multiply, Divide, in decodetree */ + goto illegal_op; } break; case 6: case 7: case 14: case 15: diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 4990eb3839..d7a333b90b 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -486,3 +486,25 @@ REV .... 0110 1011 1111 .... 1111 0011 .... @rdm REV16 .... 0110 1011 1111 .... 1111 1011 .... @rdm REVSH .... 0110 1111 1111 .... 1111 1011 .... @rdm RBIT .... 0110 1111 1111 .... 1111 0011 .... @rdm + +# Signed multiply, signed and unsigned divide + +@rdmn ---- .... .... rd:4 .... rm:4 .... rn:4 &rrr + +SMLAD .... 0111 0000 .... .... .... 0001 .... @rdamn +SMLADX .... 0111 0000 .... .... .... 0011 .... @rdamn +SMLSD .... 0111 0000 .... .... .... 0101 .... @rdamn +SMLSDX .... 0111 0000 .... .... .... 0111 .... @rdamn + +SDIV .... 0111 0001 .... 1111 .... 0001 .... @rdmn +UDIV .... 0111 0011 .... 1111 .... 0001 .... @rdmn + +SMLALD .... 0111 0100 .... .... .... 0001 .... @rdamn +SMLALDX .... 0111 0100 .... .... .... 0011 .... @rdamn +SMLSLD .... 0111 0100 .... .... .... 0101 .... @rdamn +SMLSLDX .... 0111 0100 .... .... .... 0111 .... @rdamn + +SMMLA .... 0111 0101 .... .... .... 0001 .... @rdamn +SMMLAR .... 0111 0101 .... .... .... 0011 .... @rdamn +SMMLS .... 0111 0101 .... .... .... 1101 .... @rdamn +SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 71f6d728f2..677acb698d 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -228,6 +228,24 @@ SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm # usad8 is usada8 w/ ra=15 USADA8 1111 1011 0111 .... .... .... 0000 .... @rnadm +SMLAD 1111 1011 0010 .... .... .... 0000 .... @rnadm +SMLADX 1111 1011 0010 .... .... .... 0001 .... @rnadm +SMLSD 1111 1011 0100 .... .... .... 0000 .... @rnadm +SMLSDX 1111 1011 0100 .... .... .... 0001 .... @rnadm + +SMLALD 1111 1011 1100 .... .... .... 1100 .... @rnadm +SMLALDX 1111 1011 1100 .... .... .... 1101 .... @rnadm +SMLSLD 1111 1011 1101 .... .... .... 1100 .... @rnadm +SMLSLDX 1111 1011 1101 .... .... .... 1101 .... @rnadm + +SMMLA 1111 1011 0101 .... .... .... 0000 .... @rnadm +SMMLAR 1111 1011 0101 .... .... .... 0001 .... @rnadm +SMMLS 1111 1011 0110 .... .... .... 0000 .... @rnadm +SMMLSR 1111 1011 0110 .... .... .... 0001 .... @rnadm + +SDIV 1111 1011 1001 .... 1111 .... 1111 .... @rndm +UDIV 1111 1011 1011 .... 1111 .... 1111 .... @rndm + # Data-processing (two source registers) QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm From patchwork Wed Sep 4 19:30:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172990 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp372536ilq; Wed, 4 Sep 2019 12:57:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqxkwUCZOQ7h7IREPV8a5paAjiHRQzKWBg9RRCgct80s28+hWCD4VF086N8Sf1WZxKSW6kte X-Received: by 2002:a37:6358:: with SMTP id x85mr30998805qkb.229.1567627046023; Wed, 04 Sep 2019 12:57:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567627046; cv=none; d=google.com; s=arc-20160816; b=odceCW/TSCAzRrKBHYXNHydK4HUDPTvF9aIhdY3iAjCcv87Ss+0wfXhiuwSqPsj1uU kDzrR+4OYmlOF9Qnlqjc4uaz+dcj1ijB3+4DsdJZCAfeLiR+nW8BjunOFMG5eB/e1r9o Vnn50UwaQ8/sw/FL4Gmn40H4z5mtplC3oVO5Tj2Xxi4o0pLFmLNN78+rNAHO+guiho5q Nscyd2ucA9LvmLGxEKKJr4sBDLfmSRptcLb9KzMcOCl+rEHhubLoQ8er9zeCkoMJwSJG I1rMrX9queZdJgCM3xwOGYrt3lFC3Ykvdvyitmd7h6eOZ54Y+ZbuZkuxidEOsFSpYmV4 rn3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=g/QDb2kvmqcOm71+AOuMbvaZW1g+/6rTDU0HkFA7so8=; b=o5Q3ak+Gl7A9RhSO9E3N3GAxhwTnMgGH099FlCbClorFw/gEs+l774MbrFkdAQEcwJ VkmiPu/g7k7yjZxwYsBFufd/vqlbSv+ymXLl2B7tlpa1Py9C7LNcHMxHKEa031hqwCaB gCjM0+82c3rrpKL2xrsETbnKHWVG3LihKF403k7s12qvwSJv+GZd74hKBOmDvEpj7BsF TW5jsUyo26PY4zt8OjA7JkCNRGGtkx46qsYRM4R245uSvEAYkUGWsLmXLkUQb/pNpn5m 8K6BxamHz10uCOleLVTpBAByZLo142fCBtefpKzhnOusH0vBu6jdc+7O2xNefDqg1lu1 7kGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EE+5fAWr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:17 -0700 Message-Id: <20190904193059.26202-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v4 27/69] target/arm: Convert MOVW, MOVT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 89 ++++++++++++++++-------------------------- target/arm/a32.decode | 6 +++ target/arm/t32.decode | 9 +++++ 3 files changed, 48 insertions(+), 56 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 5b9b303467..b7d26f7cc8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7870,6 +7870,34 @@ static bool trans_ADR(DisasContext *s, arg_ri *a) return true; } +static bool trans_MOVW(DisasContext *s, arg_MOVW *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_6T2) { + return false; + } + + tmp = tcg_const_i32(a->imm); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_MOVT(DisasContext *s, arg_MOVW *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_6T2) { + return false; + } + + tmp = load_reg(s, a->rd); + tcg_gen_ext16u_i32(tmp, tmp); + tcg_gen_ori_i32(tmp, tmp, a->imm << 16); + store_reg(s, a->rd, tmp); + return true; +} + /* * Multiply and multiply accumulate */ @@ -9762,7 +9790,7 @@ static bool trans_UDIV(DisasContext *s, arg_rrr *a) static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, rn, rd; + unsigned int cond, val, op1, i, rn; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -10011,26 +10039,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* fall back to legacy decoder */ if ((insn & 0x0f900000) == 0x03000000) { - if ((insn & (1 << 21)) == 0) { - ARCH(6T2); - rd = (insn >> 12) & 0xf; - val = ((insn >> 4) & 0xf000) | (insn & 0xfff); - if ((insn & (1 << 22)) == 0) { - /* MOVW */ - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, val); - } else { - /* MOVT */ - tmp = load_reg(s, rd); - tcg_gen_ext16u_i32(tmp, tmp); - tcg_gen_ori_i32(tmp, tmp, val << 16); - } - store_reg(s, rd, tmp); - } else { - /* MSR (immediate) and hints */ - /* All done in decodetree. Illegal ops already signalled. */ - g_assert_not_reached(); - } + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; } else if ((insn & 0x0f900000) == 0x01000000 && (insn & 0x00000090) != 0x00000090) { /* miscellaneous instructions */ @@ -10765,42 +10775,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) /* * 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx * - Data-processing (modified immediate, plain binary immediate) + * All in decodetree. */ - if (insn & (1 << 25)) { - /* - * 0b1111_0x1x_xxxx_0xxx_xxxx_xxxx - * - Data-processing (plain binary immediate) - */ - if (insn & (1 << 24)) { - /* Bitfield/Saturate, in decodetree */ - goto illegal_op; - } else { - imm = ((insn & 0x04000000) >> 15) - | ((insn & 0x7000) >> 4) | (insn & 0xff); - if (insn & (1 << 22)) { - /* 16-bit immediate. */ - imm |= (insn >> 4) & 0xf000; - if (insn & (1 << 23)) { - /* movt */ - tmp = load_reg(s, rd); - tcg_gen_ext16u_i32(tmp, tmp); - tcg_gen_ori_i32(tmp, tmp, imm << 16); - } else { - /* movw */ - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, imm); - } - store_reg(s, rd, tmp); - } else { - /* Add/sub 12-bit immediate, in decodetree */ - goto illegal_op; - } - } - } else { - /* Data-processing (modified immediate) */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } + goto illegal_op; } break; case 12: diff --git a/target/arm/a32.decode b/target/arm/a32.decode index d7a333b90b..341882e637 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -73,6 +73,12 @@ MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi +%imm16 16:4 0:12 +@mov16 ---- .... .... .... rd:4 ............ &ri imm=%imm16 + +MOVW .... 0011 0000 .... .... ............ @mov16 +MOVT .... 0011 0100 .... .... ............ @mov16 + # Data-processing (register-shifted register) @s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \ diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 677acb698d..f315fde0f4 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -150,6 +150,15 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12 } +# Move Wide + +%imm16_26_16_12_0 16:4 26:1 12:3 0:8 +@mov16 .... .... .... .... .... rd:4 .... .... \ + &ri imm=%imm16_26_16_12_0 + +MOVW 1111 0.10 0100 .... 0 ... .... ........ @mov16 +MOVT 1111 0.10 1100 .... 0 ... .... ........ @mov16 + # Saturate, bitfield @sat .... .... .. sh:1 . rn:4 . ... rd:4 .. . satimm:5 \ From patchwork Wed Sep 4 19:30:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172987 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp371993ilq; Wed, 4 Sep 2019 12:56:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqyJ82TCGtpY6RqL1FfQ46XYSW45GOuNjV3r/dUqiYrgCeNDt1INWx2lmjw/2VwUDsMCxVNm X-Received: by 2002:a50:f05a:: with SMTP id u26mr17314edl.116.1567626997579; Wed, 04 Sep 2019 12:56:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567626997; cv=none; d=google.com; s=arc-20160816; b=exFIJBrDKtUsJkmtWRCC3UrfDRlz9YlPoJLbpNUrut7zTpUvC1GGv9rQyfeH83NkO8 zAmRFldWiq1L0OaZqE3s3exRRsDuTMQ/czBusmidn3yrV+eztWLp1DgMJDHWUir7H1oP 8Bg+jXAktravjaCzNU52ZK0uuCk4zko0DUuPWDWzHNxKPhUDp29kquQXiyiHIYInlOoP eDus4vizc9Tj+yagCokYh8CNCv6mDMmsvWz7FsSwUYMu6HLZFsrXyJd48VJsj8EncOnV SxqGXZbV2oGt4fpEiBOmBKQ2qGgk7+QiCA/xo4FkTzjYFNXZdJZwhN9luJCdiDpIIyYY Rk3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=BBXbQPZIVt2C5TSZNQAU4v9y0CqssCskt3ZWxo2XK/s=; b=0OEwT66PX7rlvXNmGjeeVx0idScVWluAStqiS85FAjc3g02Fb8iEe3loRB3GZ0KvKr tFXbajtQWUR7Eu/zugQ7UX3/bSMiYRT5v0TEm/3HFZfFp95n3t11pfSq4OuympDyJG6J Toqd4/fmicZRHzu9hvor9KYjkk++WmZUlVmIOOWaBoI1PTmY7+Lz4RgluBKSeRxizQt1 35CxUjhi1y0Nw+OWPgXPrK/B7jNZCv2TfgJc/hkrs1HaMs4I1Gi5bonPaqlx5W1KAhmL daaTzuTBcTUrCXBOrQ1TLmnEzqIXAIGvyeLWY4wSzklOrSR+cNIhB6KZSL/bPIoUmqfl Oq2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LnxX8rTq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:18 -0700 Message-Id: <20190904193059.26202-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::432 Subject: [Qemu-devel] [PATCH v4 28/69] target/arm: Convert LDM, STM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This includes a minor bug fix to LDM (user), which requires bit 21 to be 0, which means no writeback. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 428 ++++++++++++++++++++++------------------- target/arm/a32.decode | 6 + target/arm/t32.decode | 10 + 3 files changed, 246 insertions(+), 198 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index b7d26f7cc8..1f3c7bbd54 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9784,6 +9784,232 @@ static bool trans_UDIV(DisasContext *s, arg_rrr *a) return op_div(s, a, true); } +/* + * Block data transfer + */ + +static TCGv_i32 op_addr_block_pre(DisasContext *s, arg_ldst_block *a, int n) +{ + TCGv_i32 addr = load_reg(s, a->rn); + + if (a->b) { + if (a->i) { + /* pre increment */ + tcg_gen_addi_i32(addr, addr, 4); + } else { + /* pre decrement */ + tcg_gen_addi_i32(addr, addr, -(n * 4)); + } + } else if (!a->i && n != 1) { + /* post decrement */ + tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); + } + + if (s->v8m_stackcheck && a->rn == 13 && a->w) { + /* + * If the writeback is incrementing SP rather than + * decrementing it, and the initial SP is below the + * stack limit but the final written-back SP would + * be above, then then we must not perform any memory + * accesses, but it is IMPDEF whether we generate + * an exception. We choose to do so in this case. + * At this point 'addr' is the lowest address, so + * either the original SP (if incrementing) or our + * final SP (if decrementing), so that's what we check. + */ + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + return addr; +} + +static void op_addr_block_post(DisasContext *s, arg_ldst_block *a, + TCGv_i32 addr, int n) +{ + if (a->w) { + /* write back */ + if (!a->b) { + if (a->i) { + /* post increment */ + tcg_gen_addi_i32(addr, addr, 4); + } else { + /* post decrement */ + tcg_gen_addi_i32(addr, addr, -(n * 4)); + } + } else if (!a->i && n != 1) { + /* pre decrement */ + tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); + } + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } +} + +static bool op_stm(DisasContext *s, arg_ldst_block *a) +{ + int i, j, n, list, mem_idx; + bool user = a->u; + TCGv_i32 addr, tmp, tmp2; + + if (user) { + /* STM (user) */ + if (IS_USER(s)) { + /* Only usable in supervisor mode. */ + unallocated_encoding(s); + return true; + } + } + + list = a->list; + n = ctpop16(list); + /* TODO: test invalid n == 0 case */ + + addr = op_addr_block_pre(s, a, n); + mem_idx = get_mem_index(s); + + for (i = j = 0; i < 16; i++) { + if (!(list & (1 << i))) { + continue; + } + + if (user && i != 15) { + tmp = tcg_temp_new_i32(); + tmp2 = tcg_const_i32(i); + gen_helper_get_user_reg(tmp, cpu_env, tmp2); + tcg_temp_free_i32(tmp2); + } else { + tmp = load_reg(s, i); + } + gen_aa32_st32(s, tmp, addr, mem_idx); + tcg_temp_free_i32(tmp); + + /* No need to add after the last transfer. */ + if (++j != n) { + tcg_gen_addi_i32(addr, addr, 4); + } + } + + op_addr_block_post(s, a, addr, n); + return true; +} + +static bool trans_STM(DisasContext *s, arg_ldst_block *a) +{ + return op_stm(s, a); +} + +static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a) +{ + /* Writeback register in register list is UNPREDICTABLE for T32. */ + if (a->w && (a->list & (1 << a->rn))) { + unallocated_encoding(s); + return true; + } + return op_stm(s, a); +} + +static bool do_ldm(DisasContext *s, arg_ldst_block *a) +{ + int i, j, n, list, mem_idx; + bool loaded_base; + bool user = a->u; + bool exc_return = false; + TCGv_i32 addr, tmp, tmp2, loaded_var; + + if (user) { + /* LDM (user), LDM (exception return) */ + if (IS_USER(s)) { + /* Only usable in supervisor mode. */ + unallocated_encoding(s); + return true; + } + if (extract32(a->list, 15, 1)) { + exc_return = true; + user = false; + } else { + /* LDM (user) does not allow writeback. */ + if (a->w) { + unallocated_encoding(s); + return true; + } + } + } + + list = a->list; + n = ctpop16(list); + /* TODO: test invalid n == 0 case */ + + addr = op_addr_block_pre(s, a, n); + mem_idx = get_mem_index(s); + loaded_base = false; + loaded_var = NULL; + + for (i = j = 0; i < 16; i++) { + if (!(list & (1 << i))) { + continue; + } + + tmp = tcg_temp_new_i32(); + gen_aa32_ld32u(s, tmp, addr, mem_idx); + if (user) { + tmp2 = tcg_const_i32(i); + gen_helper_set_user_reg(cpu_env, tmp2, tmp); + tcg_temp_free_i32(tmp2); + tcg_temp_free_i32(tmp); + } else if (i == a->rn) { + loaded_var = tmp; + loaded_base = true; + } else if (i == 15 && exc_return) { + store_pc_exc_ret(s, tmp); + } else { + store_reg_from_load(s, i, tmp); + } + + /* No need to add after the last transfer. */ + if (++j != n) { + tcg_gen_addi_i32(addr, addr, 4); + } + } + + op_addr_block_post(s, a, addr, n); + + if (loaded_base) { + store_reg(s, a->rn, loaded_var); + } + + if (exc_return) { + /* Restore CPSR from SPSR. */ + tmp = load_cpu_field(spsr); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_cpsr_write_eret(cpu_env, tmp); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } + tcg_temp_free_i32(tmp); + /* Must exit loop to check un-masked IRQs */ + s->base.is_jmp = DISAS_EXIT; + } + return true; +} + +static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a) +{ + return do_ldm(s, a); +} + +static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) +{ + /* Writeback register in register list is UNPREDICTABLE for T32. */ + if (a->w && (a->list & (1 << a->rn))) { + unallocated_encoding(s); + return true; + } + return do_ldm(s, a); +} + /* * Legacy decoder. */ @@ -10062,139 +10288,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) case 0x5: case 0x6: case 0x7: - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; case 0x08: case 0x09: - { - int j, n, loaded_base; - bool exc_return = false; - bool is_load = extract32(insn, 20, 1); - bool user = false; - TCGv_i32 loaded_var; - /* load/store multiple words */ - /* XXX: store correct base if write back */ - if (insn & (1 << 22)) { - /* LDM (user), LDM (exception return) and STM (user) */ - if (IS_USER(s)) - goto illegal_op; /* only usable in supervisor mode */ - - if (is_load && extract32(insn, 15, 1)) { - exc_return = true; - } else { - user = true; - } - } - rn = (insn >> 16) & 0xf; - addr = load_reg(s, rn); - - /* compute total size */ - loaded_base = 0; - loaded_var = NULL; - n = 0; - for (i = 0; i < 16; i++) { - if (insn & (1 << i)) - n++; - } - /* XXX: test invalid n == 0 case ? */ - if (insn & (1 << 23)) { - if (insn & (1 << 24)) { - /* pre increment */ - tcg_gen_addi_i32(addr, addr, 4); - } else { - /* post increment */ - } - } else { - if (insn & (1 << 24)) { - /* pre decrement */ - tcg_gen_addi_i32(addr, addr, -(n * 4)); - } else { - /* post decrement */ - if (n != 1) - tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); - } - } - j = 0; - for (i = 0; i < 16; i++) { - if (insn & (1 << i)) { - if (is_load) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (user) { - tmp2 = tcg_const_i32(i); - gen_helper_set_user_reg(cpu_env, tmp2, tmp); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - } else if (i == rn) { - loaded_var = tmp; - loaded_base = 1; - } else if (i == 15 && exc_return) { - store_pc_exc_ret(s, tmp); - } else { - store_reg_from_load(s, i, tmp); - } - } else { - /* store */ - if (i == 15) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, read_pc(s)); - } else if (user) { - tmp = tcg_temp_new_i32(); - tmp2 = tcg_const_i32(i); - gen_helper_get_user_reg(tmp, cpu_env, tmp2); - tcg_temp_free_i32(tmp2); - } else { - tmp = load_reg(s, i); - } - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - j++; - /* no need to add after the last transfer */ - if (j != n) - tcg_gen_addi_i32(addr, addr, 4); - } - } - if (insn & (1 << 21)) { - /* write back */ - if (insn & (1 << 23)) { - if (insn & (1 << 24)) { - /* pre increment */ - } else { - /* post increment */ - tcg_gen_addi_i32(addr, addr, 4); - } - } else { - if (insn & (1 << 24)) { - /* pre decrement */ - if (n != 1) - tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); - } else { - /* post decrement */ - tcg_gen_addi_i32(addr, addr, -(n * 4)); - } - } - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - if (loaded_base) { - store_reg(s, rn, loaded_var); - } - if (exc_return) { - /* Restore CPSR from SPSR. */ - tmp = load_cpu_field(spsr); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_cpsr_write_eret(cpu_env, tmp); - tcg_temp_free_i32(tmp); - /* Must exit loop to check un-masked IRQs */ - s->base.is_jmp = DISAS_EXIT; - } - } - break; + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0xa: case 0xb: { @@ -10461,73 +10558,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) insn & (1 << 21)); } } else { - int i, loaded_base = 0; - TCGv_i32 loaded_var; - bool wback = extract32(insn, 21, 1); - /* Load/store multiple. */ - addr = load_reg(s, rn); - offset = 0; - for (i = 0; i < 16; i++) { - if (insn & (1 << i)) - offset += 4; - } - - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, -offset); - } - - if (s->v8m_stackcheck && rn == 13 && wback) { - /* - * If the writeback is incrementing SP rather than - * decrementing it, and the initial SP is below the - * stack limit but the final written-back SP would - * be above, then then we must not perform any memory - * accesses, but it is IMPDEF whether we generate - * an exception. We choose to do so in this case. - * At this point 'addr' is the lowest address, so - * either the original SP (if incrementing) or our - * final SP (if decrementing), so that's what we check. - */ - gen_helper_v8m_stackcheck(cpu_env, addr); - } - - loaded_var = NULL; - for (i = 0; i < 16; i++) { - if ((insn & (1 << i)) == 0) - continue; - if (insn & (1 << 20)) { - /* Load. */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i == rn) { - loaded_var = tmp; - loaded_base = 1; - } else { - store_reg_from_load(s, i, tmp); - } - } else { - /* Store. */ - tmp = load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_gen_addi_i32(addr, addr, 4); - } - if (loaded_base) { - store_reg(s, rn, loaded_var); - } - if (wback) { - /* Base register writeback. */ - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, -offset); - } - /* Fault if writeback register is in register list. */ - if (insn & (1 << rn)) - goto illegal_op; - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } + /* Load/store multiple, in decodetree */ + goto illegal_op; } } break; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 341882e637..1267a689e2 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -40,6 +40,7 @@ &mrs_bank rd r sysm &ldst_rr p w u rn rt rm shimm shtype &ldst_ri p w u rn rt imm +&ldst_block rn i b u w list &strex rn rd rt rt2 imm &ldrex rn rt rt2 imm &bfx rd rn lsb widthm1 @@ -514,3 +515,8 @@ SMMLA .... 0111 0101 .... .... .... 0001 .... @rdamn SMMLAR .... 0111 0101 .... .... .... 0011 .... @rdamn SMMLS .... 0111 0101 .... .... .... 1101 .... @rdamn SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn + +# Block data transfer + +STM ---- 100 b:1 i:1 u:1 w:1 0 rn:4 list:16 &ldst_block +LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block diff --git a/target/arm/t32.decode b/target/arm/t32.decode index f315fde0f4..f1e2b934f8 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -37,6 +37,7 @@ &mrs_bank !extern rd r sysm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm +&ldst_block !extern rn i b u w list &strex !extern rn rd rt rt2 imm &ldrex !extern rn rt rt2 imm &bfx !extern rd rn lsb widthm1 @@ -563,3 +564,12 @@ SXTAB16 1111 1010 0010 .... 1111 .... 10.. .... @rrr_rot UXTAB16 1111 1010 0011 .... 1111 .... 10.. .... @rrr_rot SXTAB 1111 1010 0100 .... 1111 .... 10.. .... @rrr_rot UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot + +# Load/store multiple + +@ldstm .... .... .. w:1 . rn:4 list:16 &ldst_block u=0 + +STM_t32 1110 1000 10.0 .... ................ @ldstm i=1 b=0 +STM_t32 1110 1001 00.0 .... ................ @ldstm i=0 b=1 +LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0 +LDM_t32 1110 1001 00.1 .... ................ @ldstm i=0 b=1 From patchwork Wed Sep 4 19:30:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172993 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp376119ilq; Wed, 4 Sep 2019 13:01:14 -0700 (PDT) X-Google-Smtp-Source: APXvYqzFgCi5WXdvalSNr84mXmjJwuthJ0uXMGRZo8xxK6w+7L48OOPGj0ZjTeZ5NEreIB+6Dfz6 X-Received: by 2002:ae9:f70a:: with SMTP id s10mr10872152qkg.178.1567627274376; Wed, 04 Sep 2019 13:01:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567627274; cv=none; d=google.com; s=arc-20160816; b=Yt4khLmhl/W+D39y3/TooEuBoOoY/SbvLoiNsAPQEJx8q8eI0vG/jgXbQAi2CisOyJ jZj472W2O5azSIRzZ07mUXTk2JiwrtpDrQb81f1u/yrMNRwg7t7HZBmmGHAw0BOnolnL xb4hwrIniq6SrmfRrHVeAd6LiI7UGi6RpxJbGc/8jNOpPRNcB2yvDwE7nFqT3fUSP05z SOg/mN+cReuBuBygnyEW3qvjkRcHymYST1EpUxbqK427U8XWG3ByvG0fx8MZ/VAToavB T7+zwv7zfsTRj5lCb5Q0Xjbn1q8CECJYelaJEWjVRRa1WSPDUu74gmv2jFXZ5UR4NiPw OP9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=aH/3YEr2M2jm0vMpMPf4pJC6xbTf5AjfAwZZFhTAH2w=; b=IfJ2tCPoxrMYwJB/CVEPyfQ+110tBJNih1nwbuNwr8f2YHpDaylCESw4v104vkAAGn epbGLppCOb50cznGcYz31Qozj1jud1H/qwxQX8TBh+6nyjT1PInf9o1jriCA2on/t+4i SmVLnbiV8snett1EM37mXLGh97bpylmf9lQ3YPzzL63ysxDgdEf5f1inO+UdjiZZQJyI kitjLj5P+Qd8utbt/hHfg80tE0sSkxee04I/PTswlC0+BW/bnizb6vu8pa1gGwC/jM75 UZIPbxIzbull0CU296PkDh9O7rYR94ND4vPa9TdcZ5W9svNRVJLx6aCchRWpZPFjq56I 3KrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=e63ejY72; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:19 -0700 Message-Id: <20190904193059.26202-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 29/69] target/arm: Diagnose writeback register in list for LDM for v7 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Prior to v7, for the A32 encoding, this operation wrote an UNKNOWN value back to the base register. Starting in v7 this is UNPREDICTABLE. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 1f3c7bbd54..b67e7389d3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9997,6 +9997,15 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a) static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a) { + /* + * Writeback register in register list is UNPREDICTABLE + * for ArchVersion() >= 7. Prior to v7, A32 would write + * an UNKNOWN value to the base register. + */ + if (ENABLE_ARCH_7 && a->w && (a->list & (1 << a->rn))) { + unallocated_encoding(s); + return true; + } return do_ldm(s, a); } From patchwork Wed Sep 4 19:30:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172992 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp374324ilq; Wed, 4 Sep 2019 12:59:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqxHBxYklrwldc2VcMf74SCisg6dnFdEFDgTZMunAr1ieMKyqTLL1l3+9OMWFmAyx3uZ+W9t X-Received: by 2002:a05:620a:1487:: with SMTP id w7mr3774912qkj.95.1567627181626; Wed, 04 Sep 2019 12:59:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567627181; cv=none; d=google.com; s=arc-20160816; b=BTZf3706bCeR62GLKIi8W5jMNrEzUG2ZJquU0+Hu3r/AJNixxo4bsHxT8gPkHhkYt7 ftyTdB6tPpx0cI6UNfCtkUw46GwcVCvzQ6BElgx4gHJHHl4tPhsB9bOwiFA79DfWyuMu 5yz1RGGYCYMEKJewjC4E7xHX2k41xa1TNtl1lEIgfAzPKud3M3zQAwQphFB8cxZGS1zs Gr7a4+i47BwEctLigZ7aMRG0QoIbT9dKzBqat5ZMCkMkWkLnkfTC01ruEWIQAaRT/a5o d26R7p25ovU7v4pBuHLm4m1TUwcGqC2vczt+h7bLls76J8UQreNqxwWG4uVspSYjxXn5 MvAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=aOeT7JW4syMFoke9pOSfcUTMmUalFkDrt8zliWzFSBI=; b=WAzHe9NRfzJS7aLeeSf3BJbL8UkDCFEmfHFuTH6tSwKkvzuFdbImEv+FMPoYZwCuWa xTeqoXF2xWd7z2hV8SQBtJlBdypLGGGZde2jkpwUE6fYca5Nal/VBnSgODj7D06GE4uS Pxk977lDhkYhj88oJ9sqRAMZPNKMT7AIYUYsz8QpL3hkTKABJ69uFQYOkw3ZFD9eM/Rv aFUPmVCZZ3cjHNUnXneIRvn0nFf7By65W8ghc9v1XC0i+dL+yUgDaJ36WNsvXtOVu4Wg bIk5uKxHoe8xMfMsx/U3JrEYzaiAdj62BBv9xveF6cEghfeM2Rd8hngROqKNzKtzF/6z 2tAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PC6P+R2Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:20 -0700 Message-Id: <20190904193059.26202-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v4 30/69] target/arm: Diagnose too few registers in list for LDM/STM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This has been a TODO item for quite a while. The minimum bit count for A32 and T16 is 1, and for T32 is 2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index b67e7389d3..b623dbcd48 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9846,7 +9846,7 @@ static void op_addr_block_post(DisasContext *s, arg_ldst_block *a, } } -static bool op_stm(DisasContext *s, arg_ldst_block *a) +static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n) { int i, j, n, list, mem_idx; bool user = a->u; @@ -9863,7 +9863,10 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a) list = a->list; n = ctpop16(list); - /* TODO: test invalid n == 0 case */ + if (n < min_n) { + unallocated_encoding(s); + return true; + } addr = op_addr_block_pre(s, a, n); mem_idx = get_mem_index(s); @@ -9896,7 +9899,8 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a) static bool trans_STM(DisasContext *s, arg_ldst_block *a) { - return op_stm(s, a); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return op_stm(s, a, 1); } static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a) @@ -9906,10 +9910,11 @@ static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a) unallocated_encoding(s); return true; } - return op_stm(s, a); + /* BitCount(list) < 2 is UNPREDICTABLE */ + return op_stm(s, a, 2); } -static bool do_ldm(DisasContext *s, arg_ldst_block *a) +static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) { int i, j, n, list, mem_idx; bool loaded_base; @@ -9938,7 +9943,10 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a) list = a->list; n = ctpop16(list); - /* TODO: test invalid n == 0 case */ + if (n < min_n) { + unallocated_encoding(s); + return true; + } addr = op_addr_block_pre(s, a, n); mem_idx = get_mem_index(s); @@ -10006,7 +10014,8 @@ static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a) unallocated_encoding(s); return true; } - return do_ldm(s, a); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return do_ldm(s, a, 1); } static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) @@ -10016,7 +10025,8 @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) unallocated_encoding(s); return true; } - return do_ldm(s, a); + /* BitCount(list) < 2 is UNPREDICTABLE */ + return do_ldm(s, a, 2); } /* From patchwork Wed Sep 4 19:30:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172984 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp369566ilq; Wed, 4 Sep 2019 12:53:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqxNU/hQ3ctV+QgaOsnmO/h+IeuUtDV9VuRu4SsvEIzTMQyVnzTUjB8TgFph1CqDf5YfVSEx X-Received: by 2002:ac8:474d:: with SMTP id k13mr41296122qtp.266.1567626812360; Wed, 04 Sep 2019 12:53:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567626812; cv=none; d=google.com; s=arc-20160816; b=oadTgy2wA7ASTEnVwJKBoIIRwRmPkHTaGoRfWPNGufQJgFLOVoBRna4dG3Yev2ZNfd lzALHJOSvOqa038+NDkaZnFmiQscUX3iuxWYydM7qYrEElEDe8arj8hLIZP7EdT34CoD rz/vIQOJXogd8T60Q9eyqZi+zoETbJ/pPpsCd6bS/iPPuhmxS6zXvtkwtpf4p6RuvEgf bv/f1ILpyEaJlnmafFkK3H40i4yVxiqtL+QlYjMdy1XFS+JZrcoJHj6EAxFkTd8BoH01 iVbNNjfAALiKJE/I1eGpxt69Fnns/FsDnEmEEs2HBU9ugaNyFkzfJxgYYqvPZVLcGN9V zVCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=U7L/XkW0Sx1L9zkCTuOn1y4+61r+0iIpJsvReD5rmxY=; b=lrkgDWH6uUddaTh/WjT7uMigaMw83TeHoL7QYUoWlL0D0vhNFQM8TRjomVtcuZn8HN aE/u4py7vuMZLmJygSsb+1gbMnkuVfq5NsHCWnUGeyY3ZJfMjsa9T344gMbFKZQU8Din PCiGaxzqfC6Z3y20v6EIFgsHX3nQ4iTfKO0qqIAXKNnEtcrRb0030T9n/JVS58kk5J8w 7XbLSEdnTH/uinzavKmi0CHA6wW9KDAdk8IkbqHoWhqzGPkdi8UTf8Gb81hSGX4UDnDM ejPjB8qp1YSpdYp1bg+rtRDRfleGH9qgASQMHigfVue4FEqGatm+1LDEbvtEsSPqiRj5 wZhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RbPthGKh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:21 -0700 Message-Id: <20190904193059.26202-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v4 31/69] target/arm: Diagnose base == pc for LDM/STM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have been using store_reg and not store_reg_for_load when writing back a loaded value into the base register. At first glance this is incorrect when base == pc, however that case is UNPREDICTABLE. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index b623dbcd48..d0fc916ff9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9863,7 +9863,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n) list = a->list; n = ctpop16(list); - if (n < min_n) { + if (n < min_n || a->rn == 15) { unallocated_encoding(s); return true; } @@ -9943,7 +9943,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) list = a->list; n = ctpop16(list); - if (n < min_n) { + if (n < min_n || a->rn == 15) { unallocated_encoding(s); return true; } @@ -9983,6 +9983,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) op_addr_block_post(s, a, addr, n); if (loaded_base) { + /* Note that we reject base == pc above. */ store_reg(s, a->rn, loaded_var); } From patchwork Wed Sep 4 19:30:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172991 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp373338ilq; Wed, 4 Sep 2019 12:58:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqxFgonxhyTN46bhtsrOq/jR6DFUEiQwh1Y3U7yoPKddGRr6wNE8ODEV5K14PfZqHbyLnmrI X-Received: by 2002:a37:4b42:: with SMTP id y63mr42095853qka.450.1567627111546; Wed, 04 Sep 2019 12:58:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567627111; cv=none; d=google.com; s=arc-20160816; b=Fj03tKvanANOYWYRny9k20VNGSg6u9U8f/cMc0urJnx6Bna/pETQPu9Qs5AwCi2xB5 Rn3mijZYFddhFfLiSUvqSH1iYNCvzfpin2Mt58t7kmgq0p+xwWm0IMeCwZiI6pwu0XPT wqk3jaBC0zmvKLvY2/GunbCfKdCozumpb97ApaqZ6PEDPmiWVK5oIIcHP6QmjgiiDUDh wXA9NTnp6V5WBOYL0S90nR5AAxSfToHtIC0ECTmmDOVSpNMZoh7+qaAnrBIjsBBQ5gLl OZMJ6ONzRs4/TPHGTWKjFgjr/FjxjLgi43fQY0sd8yvKzusJx9g+1BcZJ0gihNdmQutr k52w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ctDcPeje2HRWgMe1VT5hCwuGlGkqYpgPECSd4XI9r2U=; b=LnvCgxEhq0j2rJdg0Zv9Hee9yH+J0fIBZ9TJMyt7RS+SpNSfsyA/coNX5nRqDbVkcY uh3fkdjjBDTe0pOln1wj4Xb8bw2jicMy/KS7fZ1EbKEFx3loUIcqXqh86wcT/XQI4gFL yNQemG5mjaJsHmfEjqIb4hGxtsEm226uPsaegR1khUK4ZUjrm0BaruYBLchze2Mw4Shv 5PoKeNUDal+RaoW+lzLo/1XJtRvxIYrho8sely7sr9h/n8TdZ+zVoswziL4Cx9bU94h7 hqCniduGZyuwLrcYLSy0H9HwXGBXN9FwgLCUemWNdVB2U4b8R+J5TCXVSFM8SerNKolY ZtkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hAdwaEa5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:22 -0700 Message-Id: <20190904193059.26202-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::531 Subject: [Qemu-devel] [PATCH v4 32/69] target/arm: Convert B, BL, BLX (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 133 +++++++++++++++-------------------- target/arm/a32-uncond.decode | 8 +++ target/arm/a32.decode | 8 +++ target/arm/t32.decode | 81 ++++++++++++--------- 4 files changed, 123 insertions(+), 107 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index d0fc916ff9..72e4708e61 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7545,6 +7545,14 @@ static int t32_expandimm_imm(DisasContext *s, int x) return imm; } +static int t32_branch24(DisasContext *s, int x) +{ + /* Convert J1:J2 at x[22:21] to I2:I1, which involves I=J^~S. */ + x ^= !(x < 0) * (3 << 21); + /* Append the final zero. */ + return x << 1; +} + /* * Include the generated decoders. */ @@ -10030,13 +10038,56 @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) return do_ldm(s, a, 2); } +/* + * Branch, branch with link + */ + +static bool trans_B(DisasContext *s, arg_i *a) +{ + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + +static bool trans_B_cond_thumb(DisasContext *s, arg_ci *a) +{ + /* This has cond from encoding, required to be outside IT block. */ + if (a->cond >= 0xe) { + return false; + } + if (s->condexec_mask) { + unallocated_encoding(s); + return true; + } + arm_skip_unless(s, a->cond); + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + +static bool trans_BL(DisasContext *s, arg_i *a) +{ + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + +static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) +{ + /* For A32, ARCH(5) is checked near the start of the uncond block. */ + if (s->thumb && (a->imm & 2)) { + return false; + } + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_bx_im(s, (read_pc(s) & ~3) + a->imm + !s->thumb); + return true; +} + /* * Legacy decoder. */ static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, rn; + unsigned int cond, op1, i, rn; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -10204,21 +10255,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } gen_rfe(s, tmp, tmp2); return; - } else if ((insn & 0x0e000000) == 0x0a000000) { - /* branch link and change to thumb (blx ) */ - int32_t offset; - - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, s->base.pc_next); - store_reg(s, 14, tmp); - /* Sign-extend the 24-bit offset */ - offset = (((int32_t)insn) << 8) >> 8; - val = read_pc(s); - /* offset * 4 + bit24 * 2 + (thumb bit) */ - val += (offset << 2) | ((insn >> 23) & 2) | 1; - /* protected by ARCH(5); above, near the start of uncond block */ - gen_bx_im(s, val); - return; } else if ((insn & 0x0e000f00) == 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10310,23 +10346,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) case 0x7: case 0x08: case 0x09: - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; case 0xa: case 0xb: - { - int32_t offset; - - /* branch (and link) */ - if (insn & (1 << 24)) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, s->base.pc_next); - store_reg(s, 14, tmp); - } - offset = sextract32(insn << 2, 0, 26); - gen_jmp(s, read_pc(s) + offset); - } - break; + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0xc: case 0xd: case 0xe: @@ -10693,32 +10716,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) if (insn & (1 << 15)) { /* Branches, misc control. */ if (insn & 0x5000) { - /* Unconditional branch. */ - /* signextend(hw1[10:0]) -> offset[:12]. */ - offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff; - /* hw1[10:0] -> offset[11:1]. */ - offset |= (insn & 0x7ff) << 1; - /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22] - offset[24:22] already have the same value because of the - sign extension above. */ - offset ^= ((~insn) & (1 << 13)) << 10; - offset ^= ((~insn) & (1 << 11)) << 11; - - if (insn & (1 << 14)) { - /* Branch and link. */ - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); - } - - offset += read_pc(s); - if (insn & (1 << 12)) { - /* b/bl */ - gen_jmp(s, offset); - } else { - /* blx */ - offset &= ~(uint32_t)2; - /* thumb2 bx, no need to check */ - gen_bx_im(s, offset); - } + /* Unconditional branch, in decodetree */ + goto illegal_op; } else if (((insn >> 23) & 7) == 7) { /* Misc control */ if (insn & (1 << 13)) @@ -10804,24 +10803,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } } } else { - /* Conditional branch. */ - op = (insn >> 22) & 0xf; - /* Generate a conditional jump to next instruction. */ - arm_skip_unless(s, op); - - /* offset[11:1] = insn[10:0] */ - offset = (insn & 0x7ff) << 1; - /* offset[17:12] = insn[21:16]. */ - offset |= (insn & 0x003f0000) >> 4; - /* offset[31:20] = insn[26]. */ - offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11; - /* offset[18] = insn[13]. */ - offset |= (insn & (1 << 13)) << 5; - /* offset[19] = insn[11]. */ - offset |= (insn & (1 << 11)) << 8; - - /* jump to the offset */ - gen_jmp(s, read_pc(s) + offset); + /* Conditional branch, in decodetree */ + goto illegal_op; } } else { /* diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 8dee26d3b6..573ac2cf8e 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -21,3 +21,11 @@ # All insns that have 0xf in insn[31:28] are decoded here. # All of those that have a COND field in insn[31:28] are in a32.decode # + +&i !extern imm + +# Branch with Link and Exchange + +%imm24h 0:s24 24:1 !function=times_2 + +BLX_i 1111 101 . ........................ &i imm=%imm24h diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 1267a689e2..62c6f8562e 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -520,3 +520,11 @@ SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn STM ---- 100 b:1 i:1 u:1 w:1 0 rn:4 list:16 &ldst_block LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block + +# Branch, branch with link + +%imm26 0:s24 !function=times_4 +@branch ---- .... ........................ &i imm=%imm26 + +B .... 1010 ........................ @branch +BL .... 1011 ........................ @branch diff --git a/target/arm/t32.decode b/target/arm/t32.decode index f1e2b934f8..ebc92f2c28 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -284,47 +284,55 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm %msr_sysm 4:1 8:4 %mrs_sysm 4:1 16:4 %imm16_16_0 16:4 0:12 +%imm21 26:s1 11:1 13:1 16:6 0:11 !function=times_2 +&ci cond imm { + # Group insn[25:23] = 111, which is cond=111x for the branch below, + # or unconditional, which would be illegal for the branch. { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + # Hints + { + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 - # The canonical nop ends in 0000 0000, but the whole rest - # of the space is "reserved hint, behaves as nop". - NOP 1111 0011 1010 1111 1000 0000 ---- ---- - } - # Note that the v7m insn overlaps both the normal and banked insn. - { - MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ + # The canonical nop ends in 0000 0000, but the whole rest + # of the space is "reserved hint, behaves as nop". + NOP 1111 0011 1010 1111 1000 0000 ---- ---- + } + # Note that the v7m insn overlaps both the normal and banked insn. + { + MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ &mrs_bank sysm=%mrs_sysm - MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg - MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8 - } - { - MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \ + MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg + MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8 + } + { + MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \ &msr_bank sysm=%msr_sysm - MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg - MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 - } - BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r - { - # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as for - # every other encoding of SUBS. With v7VE, IMM=0 is redefined as ERET. - # The distinction between the two only matters for Hyp mode. - ERET 1111 0011 1101 1110 1000 1111 0000 0000 - SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ + MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg + MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 + } + BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r + { + # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as for + # every other encoding of SUBS. With v7VE, IMM=0 is redefined as ERET. + # The distinction between the two only matters for Hyp mode. + ERET 1111 0011 1101 1110 1000 1111 0000 0000 + SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ &s_rri_rot rot=0 s=1 rd=15 rn=14 - } - SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i - HVC 1111 0111 1110 .... 1000 .... .... .... \ + } + SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i + HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=%imm16_16_0 - UDF 1111 0111 1111 ---- 1010 ---- ---- ---- + UDF 1111 0111 1111 ---- 1010 ---- ---- ---- + } + B_cond_thumb 1111 0. cond:4 ...... 10.0 ............ &ci imm=%imm21 } # Load/store (register, immediate, literal) @@ -573,3 +581,12 @@ STM_t32 1110 1000 10.0 .... ................ @ldstm i=1 b=0 STM_t32 1110 1001 00.0 .... ................ @ldstm i=0 b=1 LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0 LDM_t32 1110 1001 00.1 .... ................ @ldstm i=0 b=1 + +# Branches + +%imm24 26:s1 13:1 11:1 16:10 0:11 !function=t32_branch24 +@branch24 ................................ &i imm=%imm24 + +B 1111 0. .......... 10.1 ............ @branch24 +BL 1111 0. .......... 11.1 ............ @branch24 +BLX_i 1111 0. .......... 11.0 ............ @branch24 From patchwork Wed Sep 4 19:30:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173000 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp384013ilq; Wed, 4 Sep 2019 13:07:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqzYUxY97xWVOUixf36uLtv+4ayPZZ5QWFg9TYgLq9Qjg5HsBaWw6Fn8bfLsSgY0dnmBqz5s X-Received: by 2002:a17:906:edca:: with SMTP id sb10mr3191998ejb.1.1567627670645; Wed, 04 Sep 2019 13:07:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567627670; cv=none; d=google.com; s=arc-20160816; b=hm2LlJr/f63pV05fV3nV8nwUHPYi6xxadltqwirw/mlq0ajjGXwV1uqR59UsEfeueL GdKx5BcJqWxWAd9YfTn13dN7h8Ds/DxJpXKrLid8x5BtC87KqTq0ydkLgQ5iTCSlHn2t 3WRXRWjkjDhbY9Xxr0uDG3btMGnZnWsiqDTU+U2w9ncWC/oucAwZbfP3fKaoQ4ioji+o 5dP94Gw5mJ509xr5JTTGHYfoa9u8vJuTNYoGW4nKcVn/fote/W/q5hMNEMJTTuIq/hrP Fstg9LTcXLwIBSIP4XBPm4S5h9KkXk92e2Ml3pWXN1UzwTblvXvqYXi18GT+XKhIsu/d LTag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=jCLx5wbUWyoQFBTJtKxHJZzHzglyCub6PkVD7Xy998w=; b=l/1C33WFZvM4n5/qOEK5jGJHRcssQS8PCaE5i0SoYpR1/DChACFqRnVUnWAaYvhRDv wz3/vWxUfwowRUvEVomy4TKZY6lvxAX21y2eWSanCd+mT3U9ByYu6kPiV5JiBdmM2u0/ GhLc50wmXuUsWKdJ5E/hda+YYqI0teBUoWiyFqhhJJ+hxLcnsynz6S42NIrVmELb2kCO 76UnAnZ4R/aHM8+8fdFs9QNsSvLIeLgEiEACNj5xNYVdEROiJoeiFvDb7VBCEfypeqM+ YT2NSMpXs2ADVNZPHHf88NH+rAoZ6lf59hh6AhRDoXv8FrvrQnfyg8D28AXlrYeJ/sCa li8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XXT+tIT+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::534 Subject: [Qemu-devel] [PATCH v4 33/69] target/arm: Convert SVC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/translate.c | 19 +++++++++++++------ target/arm/a32.decode | 4 ++++ 2 files changed, 17 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 72e4708e61..208021181f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10081,6 +10081,18 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) return true; } +/* + * Supervisor call + */ + +static bool trans_SVC(DisasContext *s, arg_SVC *a) +{ + gen_set_pc_im(s, s->base.pc_next); + s->svc_imm = a->imm; + s->base.is_jmp = DISAS_SWI; + return true; +} + /* * Legacy decoder. */ @@ -10348,6 +10360,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) case 0x09: case 0xa: case 0xb: + case 0xf: /* All done in decodetree. Reach here for illegal ops. */ goto illegal_op; case 0xc: @@ -10363,12 +10376,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) goto illegal_op; } break; - case 0xf: - /* swi */ - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm = extract32(insn, 0, 24); - s->base.is_jmp = DISAS_SWI; - break; default: illegal_op: unallocated_encoding(s); diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 62c6f8562e..0bd952c069 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -528,3 +528,7 @@ LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block B .... 1010 ........................ @branch BL .... 1011 ........................ @branch + +# Supervisor call + +SVC ---- 1111 imm:24 &i From patchwork Wed Sep 4 19:30:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172988 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp372000ilq; Wed, 4 Sep 2019 12:56:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqzmNc0Lno3Rxmkj+xg2dsqkEKKY6fcguKWCcyHhAr7a1WYfWYzLhVGQBR83XGSwhL3rSk6K X-Received: by 2002:a17:906:f207:: with SMTP id gt7mr28297164ejb.126.1567626998211; Wed, 04 Sep 2019 12:56:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567626998; cv=none; d=google.com; s=arc-20160816; b=SM6G+TBSioGXgSDMkk9Bj/o9m/dRjPpvHH3d302fntU7wehEMMvy3trtxo6yolNFGS aZ7XRkhtYacyY0W7nfVGtFmv0ZqBcf/ofERt8Yau1NYKuEfhKzY5cWP33CqTsbSCghNS 5uh9nAzxZ5U9rQ6NtQ3iAM6PtKnAqDgn46oTCMEhA1h3VDKhncT8LkiX3hVaAXEJriFp XooTYL3xaQQyI8K35r7yYEu7cMWU9zoYWrh76malAJhgprkzEWG6jf6Z3Y4EJtsvHbXo RLdNISSWClxQaTnd7Rl3nUD2Vnto9Paxyuiwng1rPD8WRkfRiGAmdJVqpZOjVVZZ4fhA QELA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=YVJNMt9WNTMYk7iugljb14Z8xnu973MKG4jgT87zBAI=; b=Ly7AP373Dn6WJ9qCbza9dkIzoktSYd5EcudtU+kpagqMcOPv4Vbi3JtJQgjWB9w7jg LYZ5y2g9lYpVRYs6WDlXm/4AhR7XqeM7dZPySR6AYNqX0rTT1BOOqBf3Ndp5iQ0d3sx5 x0QTZMSubYumQUYNR/AW0SY+MyniOx98488JDV5Pr5tCx10+mojHYqCC9hjExQ/ckhxA S5kIuJvsR7NVk34p/BelXAXPXKRsKtbixPpBqoPTiK/sZJHij9bzVNo0RnWFzec/4P9n YorQZa2oN1pyUNc3yn5z5poo0nX6SA+n08f9GNwMA+U43TYS7c65I0AyOJpSRKnlDAbT 4ZrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zE+5ggMy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 34/69] target/arm: Convert RFE and SRS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Fix SRS decode; reject RFE and SRS for m-profile. v4: Fix checkpatch failure in trans_RFE. --- target/arm/translate.c | 144 +++++++++++++---------------------- target/arm/a32-uncond.decode | 8 ++ target/arm/t32.decode | 12 +++ 3 files changed, 75 insertions(+), 89 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 208021181f..ca4873e514 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10093,16 +10093,65 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) return true; } +/* + * Unconditional system instructions + */ + +static bool trans_RFE(DisasContext *s, arg_RFE *a) +{ + static const int8_t pre_offset[4] = { + /* DA */ -4, /* IA */ 0, /* DB */ -8, /* IB */ 4 + }; + static const int8_t post_offset[4] = { + /* DA */ -8, /* IA */ 4, /* DB */ -4, /* IB */ 0 + }; + TCGv_i32 addr, t1, t2; + + if (!ENABLE_ARCH_6 || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (IS_USER(s)) { + unallocated_encoding(s); + return true; + } + + addr = load_reg(s, a->rn); + tcg_gen_addi_i32(addr, addr, pre_offset[a->pu]); + + /* Load PC into tmp and CPSR into tmp2. */ + t1 = tcg_temp_new_i32(); + gen_aa32_ld32u(s, t1, addr, get_mem_index(s)); + tcg_gen_addi_i32(addr, addr, 4); + t2 = tcg_temp_new_i32(); + gen_aa32_ld32u(s, t2, addr, get_mem_index(s)); + + if (a->w) { + /* Base writeback. */ + tcg_gen_addi_i32(addr, addr, post_offset[a->pu]); + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } + gen_rfe(s, t1, t2); + return true; +} + +static bool trans_SRS(DisasContext *s, arg_SRS *a) +{ + if (!ENABLE_ARCH_6 || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_srs(s, a->mode, a->pu, a->w); + return true; +} + /* * Legacy decoder. */ static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, op1, i, rn; - TCGv_i32 tmp; - TCGv_i32 tmp2; - TCGv_i32 addr; + unsigned int cond, op1; /* M variants do not implement ARM mode; this must raise the INVSTATE * UsageFault exception. @@ -10221,52 +10270,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) default: goto illegal_op; } - } else if ((insn & 0x0e5fffe0) == 0x084d0500) { - /* srs */ - ARCH(6); - gen_srs(s, (insn & 0x1f), (insn >> 23) & 3, insn & (1 << 21)); - return; - } else if ((insn & 0x0e50ffe0) == 0x08100a00) { - /* rfe */ - int32_t offset; - if (IS_USER(s)) - goto illegal_op; - ARCH(6); - rn = (insn >> 16) & 0xf; - addr = load_reg(s, rn); - i = (insn >> 23) & 3; - switch (i) { - case 0: offset = -4; break; /* DA */ - case 1: offset = 0; break; /* IA */ - case 2: offset = -8; break; /* DB */ - case 3: offset = 4; break; /* IB */ - default: abort(); - } - if (offset) - tcg_gen_addi_i32(addr, addr, offset); - /* Load PC into tmp and CPSR into tmp2. */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - tcg_gen_addi_i32(addr, addr, 4); - tmp2 = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s)); - if (insn & (1 << 21)) { - /* Base writeback. */ - switch (i) { - case 0: offset = -8; break; - case 1: offset = 4; break; - case 2: offset = -4; break; - case 3: offset = 0; break; - default: abort(); - } - if (offset) - tcg_gen_addi_i32(addr, addr, offset); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - gen_rfe(s, tmp, tmp2); - return; } else if ((insn & 0x0e000f00) == 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10429,7 +10432,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; - TCGv_i32 tmp2; TCGv_i32 addr; int op; @@ -10573,44 +10575,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; } } else { - /* Load/store multiple, RFE, SRS. */ - if (((insn >> 23) & 1) == ((insn >> 24) & 1)) { - /* RFE, SRS: not available in user mode or on M profile */ - if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - if (insn & (1 << 20)) { - /* rfe */ - addr = load_reg(s, rn); - if ((insn & (1 << 24)) == 0) - tcg_gen_addi_i32(addr, addr, -8); - /* Load PC into tmp and CPSR into tmp2. */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - tcg_gen_addi_i32(addr, addr, 4); - tmp2 = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s)); - if (insn & (1 << 21)) { - /* Base writeback. */ - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, 4); - } else { - tcg_gen_addi_i32(addr, addr, -4); - } - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - gen_rfe(s, tmp, tmp2); - } else { - /* srs */ - gen_srs(s, (insn & 0x1f), (insn & (1 << 24)) ? 1 : 2, - insn & (1 << 21)); - } - } else { - /* Load/store multiple, in decodetree */ - goto illegal_op; - } + /* Load/store multiple, RFE, SRS, in decodetree */ + goto illegal_op; } break; case 5: diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 573ac2cf8e..64548a93e2 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -29,3 +29,11 @@ %imm24h 0:s24 24:1 !function=times_2 BLX_i 1111 101 . ........................ &i imm=%imm24h + +# System Instructions + +&rfe rn w pu +&srs mode w pu + +RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe +SRS 1111 100 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ebc92f2c28..c8a8aeceee 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -582,6 +582,18 @@ STM_t32 1110 1001 00.0 .... ................ @ldstm i=0 b=1 LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0 LDM_t32 1110 1001 00.1 .... ................ @ldstm i=0 b=1 +&rfe !extern rn w pu +@rfe .... .... .. w:1 . rn:4 ................ &rfe + +RFE 1110 1000 00.1 .... 1100000000000000 @rfe pu=2 +RFE 1110 1001 10.1 .... 1100000000000000 @rfe pu=1 + +&srs !extern mode w pu +@srs .... .... .. w:1 . .... ........... mode:5 &srs + +SRS 1110 1000 00.0 1101 1100 0000 000. .... @srs pu=2 +SRS 1110 1001 10.0 1101 1100 0000 000. .... @srs pu=1 + # Branches %imm24 26:s1 13:1 11:1 16:10 0:11 !function=t32_branch24 From patchwork Wed Sep 4 19:30:25 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:25 -0700 Message-Id: <20190904193059.26202-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42e Subject: [Qemu-devel] [PATCH v4 35/69] target/arm: Convert Clear-Exclusive, Barriers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v3: Check m-profile for all; fix missing isa check for ISB; fix thumb isa check for CLREX and DSB. --- target/arm/translate.c | 127 ++++++++++++++++------------------- target/arm/a32-uncond.decode | 10 +++ target/arm/t32.decode | 10 +++ 3 files changed, 78 insertions(+), 69 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index ca4873e514..364b51c2a6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10145,6 +10145,63 @@ static bool trans_SRS(DisasContext *s, arg_SRS *a) return true; } +/* + * Clear-Exclusive, Barriers + */ + +static bool trans_CLREX(DisasContext *s, arg_CLREX *a) +{ + if (s->thumb + ? !ENABLE_ARCH_7 && !arm_dc_feature(s, ARM_FEATURE_M) + : !ENABLE_ARCH_6K) { + return false; + } + gen_clrex(s); + return true; +} + +static bool trans_DSB(DisasContext *s, arg_DSB *a) +{ + if (!ENABLE_ARCH_7 && !arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + return true; +} + +static bool trans_DMB(DisasContext *s, arg_DMB *a) +{ + return trans_DSB(s, NULL); +} + +static bool trans_ISB(DisasContext *s, arg_ISB *a) +{ + if (!ENABLE_ARCH_7 && !arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + /* + * We need to break the TB after this insn to execute + * self-modifying code correctly and also to take + * any pending interrupts immediately. + */ + gen_goto_tb(s, 0, s->base.pc_next); + return true; +} + +static bool trans_SB(DisasContext *s, arg_SB *a) +{ + if (!dc_isar_feature(aa32_sb, s)) { + return false; + } + /* + * TODO: There is no speculation barrier opcode + * for TCG; MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, s->base.pc_next); + return true; +} + /* * Legacy decoder. */ @@ -10238,38 +10295,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) s->base.is_jmp = DISAS_UPDATE; } return; - } else if ((insn & 0x0fffff00) == 0x057ff000) { - switch ((insn >> 4) & 0xf) { - case 1: /* clrex */ - ARCH(6K); - gen_clrex(s); - return; - case 4: /* dsb */ - case 5: /* dmb */ - ARCH(7); - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - return; - case 6: /* isb */ - /* We need to break the TB after this insn to execute - * self-modifying code correctly and also to take - * any pending interrupts immediately. - */ - gen_goto_tb(s, 0, s->base.pc_next); - return; - case 7: /* sb */ - if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) { - goto illegal_op; - } - /* - * TODO: There is no speculation barrier opcode - * for TCG; MB and end the TB instead. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, s->base.pc_next); - return; - default: - goto illegal_op; - } } else if ((insn & 0x0e000f00) == 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10730,43 +10755,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) gen_set_psr_im(s, offset, 0, imm); } break; - case 3: /* Special control operations. */ - if (!arm_dc_feature(s, ARM_FEATURE_V7) && - !arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - op = (insn >> 4) & 0xf; - switch (op) { - case 2: /* clrex */ - gen_clrex(s); - break; - case 4: /* dsb */ - case 5: /* dmb */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - break; - case 6: /* isb */ - /* We need to break the TB after this insn - * to execute self-modifying code correctly - * and also to take any pending interrupts - * immediately. - */ - gen_goto_tb(s, 0, s->base.pc_next); - break; - case 7: /* sb */ - if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) { - goto illegal_op; - } - /* - * TODO: There is no speculation barrier opcode - * for TCG; MB and end the TB instead. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, s->base.pc_next); - break; - default: - goto illegal_op; - } - break; + case 3: /* Special control operations, in decodetree */ case 4: /* bxj, in decodetree */ goto illegal_op; case 5: /* Exception return. */ diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 64548a93e2..c7e9df8030 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -22,6 +22,7 @@ # All of those that have a COND field in insn[31:28] are in a32.decode # +&empty !extern &i !extern imm # Branch with Link and Exchange @@ -37,3 +38,12 @@ BLX_i 1111 101 . ........................ &i imm=%imm24h RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe SRS 1111 100 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs + +# Clear-Exclusive, Barriers + +# QEMU does not require the option field for the barriers. +CLREX 1111 0101 0111 1111 1111 0000 0001 1111 +DSB 1111 0101 0111 1111 1111 0000 0100 ---- +DMB 1111 0101 0111 1111 1111 0000 0101 ---- +ISB 1111 0101 0111 1111 1111 0000 0110 ---- +SB 1111 0101 0111 1111 1111 0000 0111 0000 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index c8a8aeceee..63bca82575 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -305,6 +305,16 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm # of the space is "reserved hint, behaves as nop". NOP 1111 0011 1010 1111 1000 0000 ---- ---- } + + # Miscellaneous control + { + CLREX 1111 0011 1011 1111 1000 1111 0010 1111 + DSB 1111 0011 1011 1111 1000 1111 0100 ---- + DMB 1111 0011 1011 1111 1000 1111 0101 ---- + ISB 1111 0011 1011 1111 1000 1111 0110 ---- + SB 1111 0011 1011 1111 1000 1111 0111 0000 + } + # Note that the v7m insn overlaps both the normal and banked insn. { MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ From patchwork Wed Sep 4 19:30:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172998 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp380724ilq; Wed, 4 Sep 2019 13:05:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqzdaeIdlhASVfZfR4BEHR5BT8bH8QW6UHSjuq+PUCmnUoqofjdXk7Gv80NWxfoGxaq5GO3z X-Received: by 2002:a05:6402:299:: with SMTP id l25mr8518edv.159.1567627500137; Wed, 04 Sep 2019 13:05:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567627500; cv=none; d=google.com; s=arc-20160816; b=ZQuF6+PUuB8asIdT01340zeNb+vLAtM0aRYLzeq6fSyQhxRIs6r2D+Vck48hDCGusZ 7+xyJ9rsTXd2WNXzN880+ViUr7+TFmbZtLrSmCld98yx5Gi/qiWZQecwdky9oEDMJ7Vq FlyCOLTvHw2Nn56GU7byBw0OZWkydDeDgZBQLj4lKt8RrAqp90U+vKxPpbWm+xft90TU N1pebF3r83Sx0/zCzTg5WU7cmQ2SZw2wSVIfWv767Sh0q7G3mfwVLDV+WaulRiGpCMwR q0288zyAimvEO+T1MqiQ0dN4xVxvXT6Mad5dt70fNbPcX5bV8jV0EMK+4Vk4bRgwAuVD ghRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=mFp920jQZpixU7k16+FPmF8mjjZjYKv6xPjZ8lwU3rc=; b=kFJNI3wf8KRJR1Yu4ChGfLTpLvA+h8HhGW81QhX2OtAeLRckTtY1dkT5KFMksmdOHA JIQuxf8W3ttteqaPIXvY9FPvcIpJ5xMp2iopVRJoB57kX+Z9Sx8WjObvxTJVnN8Mp98x DqNde0a2M7moAfFVHVVD6yw0t42zeLGe5GLPkv9QS/od6am2NWlWv5Z8h1Dn889anA3a htLdye74utMWnT1vfdfbumVFCl7/wUKE2Vrr9c8bPX1HiQ9g+QEe5wv3HzY4Geakja9l VE7hfU3+hnyiQJrgqm6MBYS7w6AV1EBwg3N2E4IPvC8N3Wx/Ba7LRoPLPkMQLFPlQrdV qjrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WkZkgncC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 36/69] target/arm: Convert CPS (privileged) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Reject for m-profile; add TODO for unpredictable arguments. Sort the T32 decode adjacent to the hint space. --- target/arm/translate.c | 91 ++++++++++++++++-------------------- target/arm/a32-uncond.decode | 3 ++ target/arm/t32.decode | 5 ++ 3 files changed, 48 insertions(+), 51 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 364b51c2a6..664ea281f8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10145,6 +10145,44 @@ static bool trans_SRS(DisasContext *s, arg_SRS *a) return true; } +static bool trans_CPS(DisasContext *s, arg_CPS *a) +{ + uint32_t mask, val; + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (IS_USER(s)) { + /* Implemented as NOP in user mode. */ + return true; + } + /* TODO: There are quite a lot of UNPREDICTABLE argument combinations. */ + + mask = val = 0; + if (a->imod & 2) { + if (a->A) { + mask |= CPSR_A; + } + if (a->I) { + mask |= CPSR_I; + } + if (a->F) { + mask |= CPSR_F; + } + if (a->imod & 1) { + val |= mask; + } + } + if (a->M) { + mask |= CPSR_M; + val |= a->mode; + } + if (mask) { + gen_set_psr_im(s, mask, 0, val); + } + return true; +} + /* * Clear-Exclusive, Barriers */ @@ -10321,31 +10359,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) ARCH(5TE); } else if ((insn & 0x0f000010) == 0x0e000010) { /* Additional coprocessor register transfer. */ - } else if ((insn & 0x0ff10020) == 0x01000000) { - uint32_t mask; - uint32_t val; - /* cps (privileged) */ - if (IS_USER(s)) - return; - mask = val = 0; - if (insn & (1 << 19)) { - if (insn & (1 << 8)) - mask |= CPSR_A; - if (insn & (1 << 7)) - mask |= CPSR_I; - if (insn & (1 << 6)) - mask |= CPSR_F; - if (insn & (1 << 18)) - val |= mask; - } - if (insn & (1 << 17)) { - mask |= CPSR_M; - val |= (insn & 0x1f); - } - if (mask) { - gen_set_psr_im(s, mask, 0, val); - } - return; } goto illegal_op; } @@ -10454,7 +10467,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; TCGv_i32 addr; @@ -10730,31 +10742,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 0: /* msr cpsr, in decodetree */ case 1: /* msr spsr, in decodetree */ goto illegal_op; - case 2: /* cps, nop-hint. */ - /* nop hints in decodetree */ - /* Implemented as NOP in user mode. */ - if (IS_USER(s)) - break; - offset = 0; - imm = 0; - if (insn & (1 << 10)) { - if (insn & (1 << 7)) - offset |= CPSR_A; - if (insn & (1 << 6)) - offset |= CPSR_I; - if (insn & (1 << 5)) - offset |= CPSR_F; - if (insn & (1 << 9)) - imm = CPSR_A | CPSR_I | CPSR_F; - } - if (insn & (1 << 8)) { - offset |= 0x1f; - imm |= (insn & 0x1f); - } - if (offset) { - gen_set_psr_im(s, offset, 0, imm); - } - break; + case 2: /* cps, nop-hint, in decodetree */ + goto illegal_op; case 3: /* Special control operations, in decodetree */ case 4: /* bxj, in decodetree */ goto illegal_op; diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index c7e9df8030..de611e8aff 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -35,9 +35,12 @@ BLX_i 1111 101 . ........................ &i imm=%imm24h &rfe rn w pu &srs mode w pu +&cps mode imod M A I F RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe SRS 1111 100 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs +CPS 1111 0001 0000 imod:2 M:1 0 0000 000 A:1 I:1 F:1 0 mode:5 \ + &cps # Clear-Exclusive, Barriers diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 63bca82575..11a9a2ef58 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -44,6 +44,7 @@ &bfi !extern rd rn lsb msb &sat !extern rd rn satimm imm sh &pkh !extern rd rn rm imm tb +&cps !extern mode imod M A I F # Data-processing (register) @@ -306,6 +307,10 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm NOP 1111 0011 1010 1111 1000 0000 ---- ---- } + # If imod == '00' && M == '0' then SEE "Hint instructions", above. + CPS 1111 0011 1010 1111 1000 0 imod:2 M:1 A:1 I:1 F:1 mode:5 \ + &cps + # Miscellaneous control { CLREX 1111 0011 1011 1111 1000 1111 0010 1111 From patchwork Wed Sep 4 19:30:27 2019 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 37/69] target/arm: Convert SETEND X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/translate.c | 22 +++++++++++++--------- target/arm/a32-uncond.decode | 4 ++++ 2 files changed, 17 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 664ea281f8..a599da96e1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10240,6 +10240,18 @@ static bool trans_SB(DisasContext *s, arg_SB *a) return true; } +static bool trans_SETEND(DisasContext *s, arg_SETEND *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + if (a->E != (s->be_data == MO_BE)) { + gen_helper_setend(cpu_env); + s->base.is_jmp = DISAS_UPDATE; + } + return true; +} + /* * Legacy decoder. */ @@ -10325,15 +10337,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) return; /* v7MP: Unallocated memory hint: must NOP */ } - if ((insn & 0x0ffffdff) == 0x01010000) { - ARCH(6); - /* setend */ - if (((insn >> 9) & 1) != !!(s->be_data == MO_BE)) { - gen_helper_setend(cpu_env); - s->base.is_jmp = DISAS_UPDATE; - } - return; - } else if ((insn & 0x0e000f00) == 0x0c000100) { + if ((insn & 0x0e000f00) == 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ if (extract32(s->c15_cpar, 1, 1)) { diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index de611e8aff..32253b4f9a 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -24,6 +24,7 @@ &empty !extern &i !extern imm +&setend E # Branch with Link and Exchange @@ -50,3 +51,6 @@ DSB 1111 0101 0111 1111 1111 0000 0100 ---- DMB 1111 0101 0111 1111 1111 0000 0101 ---- ISB 1111 0101 0111 1111 1111 0000 0110 ---- SB 1111 0101 0111 1111 1111 0000 0111 0000 + +# Set Endianness +SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend From patchwork Wed Sep 4 19:30:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172994 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp377472ilq; Wed, 4 Sep 2019 13:02:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqx8rnvqhEAXzD9qg8ul24w324Dc4Ne15t9uCff4JeNeDhUS+0uSFM+3k3c+EwCXXtjv0gRL X-Received: by 2002:a50:ad5a:: with SMTP id z26mr34140edc.180.1567627337380; Wed, 04 Sep 2019 13:02:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567627337; cv=none; d=google.com; s=arc-20160816; b=ljQkXIxCREL8AtyFoUUexyOOjnxDoQYvcP7iecHkWCFC6sC+2QwWCw2OVtlbdrwHDj ZyHlAhl4taISNqEHcmKKg1PIUDKqrvSQRRkc8I3N+cFyW2O0xtviRFwFEd3nP96sbE3L mTHwP3kUJ9nqthF7lLm/ZYMHMCokyEuHotgszGhqbmQOK5LYUT3MmmMr8rz3vjjSoe5i JnGo6wQfuC07zFclx15ak7OD1yE6RHn8pBp8BmXLXR+n1xue9es8wDZTUrjS+0zRjdSI mbxfOmhTsvJA3dnWQ197mBI1BbcaxcCskyYvD5hwtvlcuOO6Q+X5C513r7ZyXdPancMC TBOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=W/BZPRSZY6X94E8EzsWgQ6OBzD8ENERCVK/Str0XZk4=; b=cRAqZLxHvo0a/kuZQi3bQ7bsVaaBoZv89QLeAmbEL9TjEwCakuD1nZ0R2qB5vBGmpy 7a0HUPbe15xfCt+6I4SCewpStF2UxV8H6Vgzf5Q94R2subIMCUmZNKDWDXInw4qHzVwg vutxNLl2P1u8nudRl8YZmt2iP06rtH+80QjsdS6vmZtTql/d1rz3jBV7G9ZBVxUPlnV1 oUDjBO22whKPZbSqoeWSx19i0o1xvEeTeECrw6mkahpAwUSU2CVqDra5MWf1QjPkSFtU yVm8coIpTrSbZmXQBtH7xCPYe5AlfRizIp0vFAUgachMMPBJsjtke3y9vTzuDvEjN3j6 5qqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=lhH1jllA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v4 38/69] target/arm: Convert PLI, PLD, PLDW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/translate.c | 37 +++++++++++++++++++----------------- target/arm/a32-uncond.decode | 10 ++++++++++ 2 files changed, 30 insertions(+), 17 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index a599da96e1..3f02532d12 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10252,6 +10252,26 @@ static bool trans_SETEND(DisasContext *s, arg_SETEND *a) return true; } +/* + * Preload instructions + * All are nops, contingent on the appropriate arch level. + */ + +static bool trans_PLD(DisasContext *s, arg_PLD *a) +{ + return ENABLE_ARCH_5TE; +} + +static bool trans_PLDW(DisasContext *s, arg_PLD *a) +{ + return arm_dc_feature(s, ARM_FEATURE_V7MP); +} + +static bool trans_PLI(DisasContext *s, arg_PLD *a) +{ + return ENABLE_ARCH_7; +} + /* * Legacy decoder. */ @@ -10312,23 +10332,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } return; } - if (((insn & 0x0f30f000) == 0x0510f000) || - ((insn & 0x0f30f010) == 0x0710f000)) { - if ((insn & (1 << 22)) == 0) { - /* PLDW; v7MP */ - if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { - goto illegal_op; - } - } - /* Otherwise PLD; v5TE+ */ - ARCH(5TE); - return; - } - if (((insn & 0x0f70f000) == 0x0450f000) || - ((insn & 0x0f70f010) == 0x0650f000)) { - ARCH(7); - return; /* PLI; V7 */ - } if (((insn & 0x0f700000) == 0x04100000) || ((insn & 0x0f700010) == 0x06100000)) { if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 32253b4f9a..ddc5edfa5e 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -54,3 +54,13 @@ SB 1111 0101 0111 1111 1111 0000 0111 0000 # Set Endianness SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend + +# Preload instructions + +PLD 1111 0101 -101 ---- 1111 ---- ---- ---- # (imm, lit) 5te +PLDW 1111 0101 -001 ---- 1111 ---- ---- ---- # (imm, lit) 7mp +PLI 1111 0100 -101 ---- 1111 ---- ---- ---- # (imm, lit) 7 + +PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5te +PLDW 1111 0111 -001 ---- 1111 ----- -- 0 ---- # (register) 7mp +PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7 From patchwork Wed Sep 4 19:30:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173004 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp387675ilq; Wed, 4 Sep 2019 13:11:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqwHbYY6dojCgvreG/Z2x2J71/FEd/AQR8AuCM/Dmg5eV0M+506ThvRrF4tNpSsKVpH46+rY X-Received: by 2002:a37:9bd4:: with SMTP id d203mr19124377qke.257.1567627869100; Wed, 04 Sep 2019 13:11:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567627869; cv=none; d=google.com; s=arc-20160816; b=qXAHi3YnM9etReHdaL3iKD254DNwO1Bj0mBled59lYK0DhNu+ImXdiPGVHzwG3Xdci uNAmcQkBXuG1na023uw+n2lYkSZiCgH/Ucx8pemXK4t7P0F6nWzcIg9suFo6ZorCwHN0 BV7CDf7/+FoaINh6i5UVclssE/g1fhGd+MnyfuVUNw//wmnRLE1ZNA5NOkVKWwZXIRXa Zz3YvAFecNEikeQ214miQItJfZgT0cADPcW6QuBhX7ivs3JhOm/EQw55qvE4WYMpMwNk UgLBNyVhIER5X4gOiboUNidupgboU/935f8iAQThip5sh5C9NmFZ3gV2O9A6C0xXOAIO YNzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=O4gGKTm/ojsMEGeGW6yunfSWJTb8afl4fLManLOK4Wg=; b=t210VrDy/jDnQKWMwYicZUvvnMJAQldQbVhVWGQM1EreQadtD7GMRCS/SOlTf5LFvx FTVMvWN5kxMPhHMK7HghZqKobWKoyhYdMPPO+8FkHSvgKEyTOhdMC2tV+ixm2xIuOhVS 0ywQHP9VuldEY999bRaOKnIDl4+6nMNUc/eTolqq7xgb3Kl7wXR5HM0vhJqhFdBC+J8F RcWnDKniXXQ0SnocdZfb8hWv6ZGiViErkMa2vDVPtUQgqGobZ7wv8q115FCjDyd3QvRV zbfF66WcM7mhy0SkSqQlVhzfH72dxOQ4mKk4lsUlG4iXTHcEUwnnoVtRhxAewd1MmaRX r/dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LVsmspge; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:29 -0700 Message-Id: <20190904193059.26202-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v4 39/69] target/arm: Convert Unallocated memory hint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/translate.c | 8 -------- target/arm/a32-uncond.decode | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 3f02532d12..7023ee78f1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10332,14 +10332,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } return; } - if (((insn & 0x0f700000) == 0x04100000) || - ((insn & 0x0f700010) == 0x06100000)) { - if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { - goto illegal_op; - } - return; /* v7MP: Unallocated memory hint: must NOP */ - } - if ((insn & 0x0e000f00) == 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index ddc5edfa5e..60ccfc598d 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -64,3 +64,11 @@ PLI 1111 0100 -101 ---- 1111 ---- ---- ---- # (imm, lit) 7 PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5te PLDW 1111 0111 -001 ---- 1111 ----- -- 0 ---- # (register) 7mp PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7 + +# Unallocated memory hints +# +# Since these are v7MP nops, and PLDW is v7MP and implemented as nop, +# (ab)use the PLDW helper. + +PLDW 1111 0100 -001 ---- ---- ---- ---- ---- +PLDW 1111 0110 -001 ---- ---- ---- ---0 ---- From patchwork Wed Sep 4 19:30:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173003 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp387302ilq; Wed, 4 Sep 2019 13:10:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqweVlNI7+xOoJkQ+j2yeIMlTt2hxKW4qBLoM7qq82ZwZvyRcuqJ22t6ZQ+PY84wHnDlvnbU X-Received: by 2002:a37:a91:: with SMTP id 139mr18396362qkk.418.1567627852524; Wed, 04 Sep 2019 13:10:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567627852; cv=none; d=google.com; s=arc-20160816; b=NeWtKieVKVWcypaveT49pRS8vNUFyKM8kzf1pvCpvBTlVF/RDm6HhjnHhfQ2RGeFPZ nMxDKcWvZkxSorSeH6dEWZ9JB+OENmPhmyK4mJXObXRScX2rMjBs6dha4T0SYYN/KwGo lt07+HMBcXDYMXFmtOXhDJ0haezzvIcqnfeWamwPtX0wMSs2OnXOZSIPjQptEK/nf5R/ PUi3JnYb3AjOOfVQUxeOOdEBQai85EZFQrKzMBq9+pPk8thG+fsaL7cbUKKIiAFIej8s oPE5pE/sEXVxYUC0rDY2rfv5Jyp/5Lu/U0op0lQ86q6MJpa7xPaBe6FlRJ9+7/W5uhAX 6zlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=fNVbTJv60xmJj9T6kktIzTW/0WXFeS41CSEU1hxli/Q=; b=WOKyDFS9qUcls41SbH6W5hqMqARH5pMJXYcDrXhBqsuhUbnptyvS5NtsQXwMDxfgVe MCkcrUQM4J42E7xtpP+MjxhWNqSn+YNGDxkN+dGbb1j7ppPiKtElsW5UvExeUWFUSUkv bhynConVIUJdM5Pyx+sy7rrYiMc9hY1GCEFi6CJwsUxifdZmPFXx6tQglV3Tau/GjXjl bHbphWprmKP7HCg2g78UZPXXe8dDtSvYlhAylH6Yvz60h7fL+azUfmDxeexlbab+RpVp 5PPNjD2BFY7TBERhM54Mq7kjmSDJYHXcDKavsRj12nHLFUry2M4WnCPS2TnMjpelrMov F7yQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=R0l99mDm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:30 -0700 Message-Id: <20190904193059.26202-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42e Subject: [Qemu-devel] [PATCH v4 40/69] target/arm: Convert Table Branch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 57 +++++++++++++++++++++++++----------------- target/arm/t32.decode | 8 +++++- 2 files changed, 41 insertions(+), 24 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 7023ee78f1..96149eabf4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10081,6 +10081,37 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) return true; } +static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) +{ + TCGv_i32 addr, tmp; + + tmp = load_reg(s, a->rm); + if (half) { + tcg_gen_add_i32(tmp, tmp, tmp); + } + addr = load_reg(s, a->rn); + tcg_gen_add_i32(addr, addr, tmp); + + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), + half ? MO_UW | s->be_data : MO_UB); + tcg_temp_free_i32(addr); + + tcg_gen_add_i32(tmp, tmp, tmp); + tcg_gen_addi_i32(tmp, tmp, read_pc(s)); + store_reg(s, 15, tmp); + return true; +} + +static bool trans_TBB(DisasContext *s, arg_tbranch *a) +{ + return op_tbranch(s, a, false); +} + +static bool trans_TBH(DisasContext *s, arg_tbranch *a) +{ + return op_tbranch(s, a, true); +} + /* * Supervisor call */ @@ -10466,9 +10497,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t rd, rn, rm, rs; - TCGv_i32 tmp; - TCGv_i32 addr; + uint32_t rd, rn, rs; int op; /* @@ -10514,7 +10543,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) rn = (insn >> 16) & 0xf; rs = (insn >> 12) & 0xf; rd = (insn >> 8) & 0xf; - rm = insn & 0xf; switch ((insn >> 25) & 0xf) { case 0: case 1: case 2: case 3: /* 16-bit instructions. Should never happen. */ @@ -10587,25 +10615,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) /* Load/store exclusive, in decodetree */ goto illegal_op; } else if ((insn & (7 << 5)) == 0) { - /* Table Branch. */ - addr = load_reg(s, rn); - tmp = load_reg(s, rm); - tcg_gen_add_i32(addr, addr, tmp); - if (insn & (1 << 4)) { - /* tbh */ - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - tmp = tcg_temp_new_i32(); - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); - } else { /* tbb */ - tcg_temp_free_i32(tmp); - tmp = tcg_temp_new_i32(); - gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); - } - tcg_temp_free_i32(addr); - tcg_gen_shli_i32(tmp, tmp, 1); - tcg_gen_addi_i32(tmp, tmp, read_pc(s)); - store_reg(s, 15, tmp); + /* Table Branch, in decodetree */ + goto illegal_op; } else { /* Load/store exclusive, load-acq/store-rel, in decodetree */ goto illegal_op; diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 11a9a2ef58..d05673ff3e 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -489,7 +489,7 @@ LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1 LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1 -# Load/Store Exclusive and Load-Acquire/Store-Release +# Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch @strex_i .... .... .... rn:4 rt:4 rd:4 .... .... \ &strex rt2=15 imm=%imm8x4 @@ -533,6 +533,12 @@ LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0 LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0 LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0 +&tbranch rn rm +@tbranch .... .... .... rn:4 .... .... .... rm:4 &tbranch + +TBB 1110 1000 1101 .... 1111 0000 0000 .... @tbranch +TBH 1110 1000 1101 .... 1111 0000 0001 .... @tbranch + # Parallel addition and subtraction SADD8 1111 1010 1000 .... 1111 .... 0000 .... @rndm From patchwork Wed Sep 4 19:30:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173008 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp393448ilq; Wed, 4 Sep 2019 13:16:43 -0700 (PDT) X-Google-Smtp-Source: APXvYqxUafZU45bV6ninnNxgeMvfaMCzBh0dw6tV0AQb388RwerYY15BcYOAyrE4MVpsT71xw9Gx X-Received: by 2002:a17:906:a416:: with SMTP id l22mr29911998ejz.302.1567628202972; Wed, 04 Sep 2019 13:16:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567628202; cv=none; d=google.com; s=arc-20160816; b=ZNIqGBP48WMON/dZYkvO3nbR+2lgWg7X8eGafM6ldYrcnE2Z0cqy5a+OWlugdXXcUe raJf5yewdADRsmW97aeUyaVRWe/xuxJySqEGzN3CRTnrtFR8vGM8GZ1EAHQTrgKuv3Vv 9wpIFSSy+K2KA63k5Zry7ihdEVZFJj/BC5E7CloNNpqzq0wbw8iH/0m1eWmPHJIi2Svo +JmtUnQB7CwNpscrQy2UDspYVKkccOPk1ysGZ2yjRdmidViDxpEZ8oe4UwvD9NZbe4Rj KVg3lQZVa8h0uellltPXmL9tpnhcHSneu6Zvru/0a031GbID43rpOJeB9MnfzfZo6ESG YOfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=bRqYq2TLJ+WIjlJfH/2hIAtxOVh3ChiZfI3nAvVSmQE=; b=HK47fb0vv7retiI0U+iRC02d6pqsv6zZMMrIfsW+/GmaUJap8iKO3YUFW5qtwu6r8N e1G56qhmZj7PgcXsw3BcvqTIQyUTQ/2pEout6te7E82Om3vIHjKreI6V1y3IU+AtJfCy gEIWXlL4JJD1zgxdZgkD/v5spUveKm7502uWqSKZtmEid7VwhfhFN7viOidpGcsAALng bnboVLp6H/P1yqH9Xan8cKYPhNE233KKfFJk13OoQkGOE3NGVLGMVB2vOwC3nOdSZNTI XbwXEgPbBPFvDApceGyatHdWQM4ujZ42qMqb4XVyorvv25m8SDIVBIS1YyxFGuGIX0He TaSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="iRb1/wXK"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:31 -0700 Message-Id: <20190904193059.26202-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 41/69] target/arm: Convert SG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 51 ++++++++++++++++++++++++------------------ target/arm/t32.decode | 5 ++++- 2 files changed, 33 insertions(+), 23 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 96149eabf4..af7eddca48 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8467,6 +8467,34 @@ static bool trans_SMC(DisasContext *s, arg_SMC *a) return true; } +static bool trans_SG(DisasContext *s, arg_SG *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + /* + * SG (v8M only) + * The bulk of the behaviour for this instruction is implemented + * in v7m_handle_execute_nsc(), which deals with the insn when + * it is executed by a CPU in non-secure state from memory + * which is Secure & NonSecure-Callable. + * Here we only need to handle the remaining cases: + * * in NS memory (including the "security extension not + * implemented" case) : NOP + * * in S memory but CPU already secure (clear IT bits) + * We know that the attribute for the memory this insn is + * in must match the current CPU state, because otherwise + * get_phys_addr_pmsav8 would have generated an exception. + */ + if (s->v8m_secure) { + /* Like the IT insn, we don't need to generate any code */ + s->condexec_cond = 0; + s->condexec_mask = 0; + } + return true; +} + /* * Load/store register index */ @@ -10553,28 +10581,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) * - load/store doubleword, load/store exclusive, ldacq/strel, * table branch, TT. */ - if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_M) && - arm_dc_feature(s, ARM_FEATURE_V8)) { - /* 0b1110_1001_0111_1111_1110_1001_0111_111 - * - SG (v8M only) - * The bulk of the behaviour for this instruction is implemented - * in v7m_handle_execute_nsc(), which deals with the insn when - * it is executed by a CPU in non-secure state from memory - * which is Secure & NonSecure-Callable. - * Here we only need to handle the remaining cases: - * * in NS memory (including the "security extension not - * implemented" case) : NOP - * * in S memory but CPU already secure (clear IT bits) - * We know that the attribute for the memory this insn is - * in must match the current CPU state, because otherwise - * get_phys_addr_pmsav8 would have generated an exception. - */ - if (s->v8m_secure) { - /* Like the IT insn, we don't need to generate any code */ - s->condexec_cond = 0; - s->condexec_mask = 0; - } - } else if (insn & 0x01200000) { + if (insn & 0x01200000) { /* load/store dual, in decodetree */ goto illegal_op; } else if ((insn & (1 << 23)) == 0) { diff --git a/target/arm/t32.decode b/target/arm/t32.decode index d05673ff3e..c956ddb254 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -487,7 +487,10 @@ STRD_ri_t32 1110 1001 .100 .... .... .... ........ @ldstd_ri8 w=0 p=1 LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1 -LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1 +{ + SG 1110 1001 0111 1111 1110 1001 01111111 + LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1 +} # Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch From patchwork Wed Sep 4 19:30:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173011 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp396393ilq; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:32 -0700 Message-Id: <20190904193059.26202-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v4 42/69] target/arm: Convert TT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use unallocated_encoding. --- target/arm/translate.c | 90 ++++++++++++++---------------------------- target/arm/t32.decode | 5 ++- 2 files changed, 34 insertions(+), 61 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index af7eddca48..46c27ea6a8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8495,6 +8495,33 @@ static bool trans_SG(DisasContext *s, arg_SG *a) return true; } +static bool trans_TT(DisasContext *s, arg_TT *a) +{ + TCGv_i32 addr, tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + if (a->rd == 13 || a->rd == 15 || a->rn == 15) { + /* We UNDEF for these UNPREDICTABLE cases */ + unallocated_encoding(s); + return true; + } + if (a->A && !s->v8m_secure) { + /* This case is UNDEFINED. */ + unallocated_encoding(s); + return true; + } + + addr = load_reg(s, a->rn); + tmp = tcg_const_i32((a->A << 1) | a->T); + gen_helper_v7m_tt(tmp, cpu_env, addr, tmp); + tcg_temp_free_i32(addr); + store_reg(s, a->rd, tmp); + return true; +} + /* * Load/store register index */ @@ -10525,7 +10552,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t rd, rn, rs; + uint32_t rn; int op; /* @@ -10569,70 +10596,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) /* fall back to legacy decoder */ rn = (insn >> 16) & 0xf; - rs = (insn >> 12) & 0xf; - rd = (insn >> 8) & 0xf; switch ((insn >> 25) & 0xf) { case 0: case 1: case 2: case 3: /* 16-bit instructions. Should never happen. */ abort(); case 4: - if (insn & (1 << 22)) { - /* 0b1110_100x_x1xx_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store doubleword, load/store exclusive, ldacq/strel, - * table branch, TT. - */ - if (insn & 0x01200000) { - /* load/store dual, in decodetree */ - goto illegal_op; - } else if ((insn & (1 << 23)) == 0) { - /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store exclusive word - * - TT (v8M only) - */ - if (rs == 15) { - if (!(insn & (1 << 20)) && - arm_dc_feature(s, ARM_FEATURE_M) && - arm_dc_feature(s, ARM_FEATURE_V8)) { - /* 0b1110_1000_0100_xxxx_1111_xxxx_xxxx_xxxx - * - TT (v8M only) - */ - bool alt = insn & (1 << 7); - TCGv_i32 addr, op, ttresp; - - if ((insn & 0x3f) || rd == 13 || rd == 15 || rn == 15) { - /* we UNDEF for these UNPREDICTABLE cases */ - goto illegal_op; - } - - if (alt && !s->v8m_secure) { - goto illegal_op; - } - - addr = load_reg(s, rn); - op = tcg_const_i32(extract32(insn, 6, 2)); - ttresp = tcg_temp_new_i32(); - gen_helper_v7m_tt(ttresp, cpu_env, addr, op); - tcg_temp_free_i32(addr); - tcg_temp_free_i32(op); - store_reg(s, rd, ttresp); - break; - } - goto illegal_op; - } - /* Load/store exclusive, in decodetree */ - goto illegal_op; - } else if ((insn & (7 << 5)) == 0) { - /* Table Branch, in decodetree */ - goto illegal_op; - } else { - /* Load/store exclusive, load-acq/store-rel, in decodetree */ - goto illegal_op; - } - } else { - /* Load/store multiple, RFE, SRS, in decodetree */ - goto illegal_op; - } - break; + /* All in decodetree */ + goto illegal_op; case 5: /* All in decodetree */ goto illegal_op; diff --git a/target/arm/t32.decode b/target/arm/t32.decode index c956ddb254..c63082fc9c 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -508,7 +508,10 @@ STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1 @ldrex_d .... .... .... rn:4 rt:4 rt2:4 .... .... \ &ldrex imm=0 -STREX 1110 1000 0100 .... .... .... .... .... @strex_i +{ + TT 1110 1000 0100 rn:4 1111 rd:4 A:1 T:1 000000 + STREX 1110 1000 0100 .... .... .... .... .... @strex_i +} STREXB 1110 1000 1100 .... .... 1111 0100 .... @strex_0 STREXH 1110 1000 1100 .... .... 1111 0101 .... @strex_0 STREXD_t32 1110 1000 1100 .... .... .... 0111 .... @strex_d From patchwork Wed Sep 4 19:30:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173014 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp399245ilq; Wed, 4 Sep 2019 13:23:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqxDnA1t/w3sZTyKhABnZ4Qx6UVEDPBQiJuleuuFr4GJCQR9GNYunvtpL9D48AStbWq8xkJh X-Received: by 2002:a37:de10:: with SMTP id h16mr22396043qkj.338.1567628585071; Wed, 04 Sep 2019 13:23:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567628585; cv=none; d=google.com; s=arc-20160816; b=lnDCBnKPgk3gZ1Y/bry+llLGFGR5slw1Qmj+A2UB0f5YkiMdIEPloZldxO4vGu5CbO 9ZBPD5F7Ot06XcMARoHCLuXJIas9xB6Ojk8lAPQsA6sfmoPswjlY5eqbr+nCkVVidVNg KEA2N5ei7rmWLCDptwjPZxIWquJ02hFXgVyQZfjfZUeJNDs/D2dQtHrJnX99qQ8Dua/F CwQIb3IKThmuEA51UVdof6IVb46O5Cd1b91uo+lxKjjXxor/pQCuLzB92MxLafu/xk6o TXuKKlQ7sfhXV+dl0RK3hjMJfeueB4ynMEDT35JglcM6moF8mT7MRQ2kvO4TBNdlz1SI x4UA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=3YTIbEYYLxo/KQorAmZTbgiM25Lefa2PHYOLeWCcYi0=; b=e/aqHpDO5H+PYAHr/+o/TTcb6rzBIMfT3TUSi3uR8QqCSX/KbdyXzlMOp06N2GP0Ob +J3aI1CU0p7ECfhJmxYeRrOPXfvi9c5li6T7j+t1mxo43DpX0GoZhWHvFAAB/1n9lp+W 8CYFaUEboD4Nk3Zliojf2mRMGf7PT6JoUoGXJzMzQCBTra4Y/SYvIl9PHsAsAqNU2NXM geJDe6+6cKja1BkNfelI7wit58mLxg+4A3tIxNGObx/NeyljKoaVYYRJi+ktbM0iRQCl 6zK7ctdbaS11pCbrFGAm3QVa6UM7EmueispRcWhmMG/kO8Nygc0pfUFsbM8jh4ww5ndE EKSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=sWmnukhB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:33 -0700 Message-Id: <20190904193059.26202-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v4 43/69] target/arm: Simplify disas_thumb2_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Fold away all of the cases that now just goto illegal_op, because all of their internal bits are now in decodetree. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 79 ++---------------------------------------- 1 file changed, 3 insertions(+), 76 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 46c27ea6a8..f68e09ff1f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10552,9 +10552,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t rn; - int op; - /* * ARMv6-M supports a limited subset of Thumb2 instructions. * Other Thumb1 architectures allow only 32-bit @@ -10595,34 +10592,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } /* fall back to legacy decoder */ - rn = (insn >> 16) & 0xf; switch ((insn >> 25) & 0xf) { case 0: case 1: case 2: case 3: /* 16-bit instructions. Should never happen. */ abort(); - case 4: - /* All in decodetree */ - goto illegal_op; - case 5: - /* All in decodetree */ - goto illegal_op; - case 13: /* Misc data processing. */ - op = ((insn >> 22) & 6) | ((insn >> 7) & 1); - if (op < 4 && (insn & 0xf000) != 0xf000) - goto illegal_op; - switch (op) { - case 0: /* Register controlled shift, in decodetree */ - case 1: /* Sign/zero extend, in decodetree */ - case 2: /* SIMD add/subtract, in decodetree */ - case 3: /* Other data processing, in decodetree */ - goto illegal_op; - case 4: case 5: - /* 32-bit multiply. Sum of absolute differences, in decodetree */ - goto illegal_op; - case 6: case 7: /* 64-bit multiply, Divide, in decodetree */ - goto illegal_op; - } - break; case 6: case 7: case 14: case 15: /* Coprocessor. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { @@ -10651,6 +10624,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } if (arm_dc_feature(s, ARM_FEATURE_VFP)) { + uint32_t rn = (insn >> 16) & 0xf; TCGv_i32 fptr = load_reg(s, rn); if (extract32(insn, 20, 1)) { @@ -10709,50 +10683,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } } break; - case 8: case 9: case 10: case 11: - if (insn & (1 << 15)) { - /* Branches, misc control. */ - if (insn & 0x5000) { - /* Unconditional branch, in decodetree */ - goto illegal_op; - } else if (((insn >> 23) & 7) == 7) { - /* Misc control */ - if (insn & (1 << 13)) - goto illegal_op; - - if (insn & (1 << 26)) { - /* hvc, smc, in decodetree */ - goto illegal_op; - } else { - op = (insn >> 20) & 7; - switch (op) { - case 0: /* msr cpsr, in decodetree */ - case 1: /* msr spsr, in decodetree */ - goto illegal_op; - case 2: /* cps, nop-hint, in decodetree */ - goto illegal_op; - case 3: /* Special control operations, in decodetree */ - case 4: /* bxj, in decodetree */ - goto illegal_op; - case 5: /* Exception return. */ - case 6: /* MRS, in decodetree */ - case 7: /* MSR, in decodetree */ - goto illegal_op; - } - } - } else { - /* Conditional branch, in decodetree */ - goto illegal_op; - } - } else { - /* - * 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx - * - Data-processing (modified immediate, plain binary immediate) - * All in decodetree. - */ - goto illegal_op; - } - break; case 12: if ((insn & 0x01100000) == 0x01000000) { if (disas_neon_ls_insn(s, insn)) { @@ -10760,14 +10690,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } break; } - /* Load/store single data item, in decodetree */ goto illegal_op; default: - goto illegal_op; + illegal_op: + unallocated_encoding(s); } - return; -illegal_op: - unallocated_encoding(s); } static void disas_thumb_insn(DisasContext *s, uint32_t insn) From patchwork Wed Sep 4 19:30:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173019 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp404286ilq; Wed, 4 Sep 2019 13:28:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqxFyvsx+lquoyFTyHPE5f8C8ONUgRQfighA7oenjJ4LbAx1CaHPXPVsjLCD2amYj1u3sWD2 X-Received: by 2002:a50:fd95:: with SMTP id o21mr176361edt.6.1567628925766; Wed, 04 Sep 2019 13:28:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567628925; cv=none; d=google.com; s=arc-20160816; b=zdp8tUrKmWBp/m7vUfveqt043+CMSUveDgwPduN5SntvSUsXfyIyjZ0MFWM1LVmQG/ o0P6/PhNlI372RMAWhS2A+DtPZXwCaqqj45/EGVg6C/6xidQxKDcMxYR2VqDJq8spYGo CvQw3UpMcz+l8jR+Py9M4bPkzQQK5+VEat3/q/0HtDCQQGI9PJamKqDb+5EsqBcijqPC UkyhkInztOQ2/SbABR23CjFU7uS+sIkZHNIjEbGpZOadJh9ADfXT9I/0SQIuRZWhGKg/ YztgwcOTtOnkUL23RcBk2273cWcX87x1Sn2d10bz+8BwNC2MXVWvjra3R1xXUg7vo+AX A9DQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=VzsNEJ79vBBXHa6di56eotbjbD089opoeS7FPmrAgFs=; b=DiIdS+yuRr4gNRh8NUNuh/o11WwQHbdaSGxkLu8ESWslSDzc702qjj/Fs1rXjK9pJt YiSUgf6X2I4OjTcsUdaOQcVNx5RGz3z98DaTIrRZZYqs0q6Hmt4pHKcmZ1suxmAIAlOh KhgObhtFWTVmvChQ86To+vIq425JRcB4gegaMqkf6n3SaVpeahkgIdgmy2zcStN43TqJ GH535hBndzQNz9pi1bqzMEcRDMm00ESOmOC2eYlucJuawkfUVejjDxqA9+yzqOv5Z7Ql qJCzvqpufJoO+9AJnLil/J3OJkLeQxUs4D2QwVfuGbcHcEJtWHq1PDoJOuegESLasziO 7bbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hYOf+kyO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:34 -0700 Message-Id: <20190904193059.26202-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v4 44/69] target/arm: Simplify disas_arm_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Fold away all of the cases that now just goto illegal_op, because all of their internal bits are now in decodetree. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 69 ++++++++++-------------------------------- 1 file changed, 16 insertions(+), 53 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index f68e09ff1f..7f2a46100e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10364,7 +10364,7 @@ static bool trans_PLI(DisasContext *s, arg_PLD *a) static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, op1; + unsigned int cond = insn >> 28; /* M variants do not implement ARM mode; this must raise the INVSTATE * UsageFault exception. @@ -10374,7 +10374,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) default_exception_el(s)); return; } - cond = insn >> 28; if (cond == 0xf) { /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we @@ -10439,11 +10438,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) goto illegal_op; } return; - } else if ((insn & 0x0fe00000) == 0x0c400000) { - /* Coprocessor double register transfer. */ - ARCH(5TE); - } else if ((insn & 0x0f000010) == 0x0e000010) { - /* Additional coprocessor register transfer. */ } goto illegal_op; } @@ -10458,55 +10452,24 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } /* fall back to legacy decoder */ - if ((insn & 0x0f900000) == 0x03000000) { - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - } else if ((insn & 0x0f900000) == 0x01000000 - && (insn & 0x00000090) != 0x00000090) { - /* miscellaneous instructions */ - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - } else if (((insn & 0x0e000000) == 0 && - (insn & 0x00000090) != 0x90) || - ((insn & 0x0e000000) == (1 << 25))) { - /* Data-processing (reg, reg-shift-reg, imm). */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } else { - /* other instructions */ - op1 = (insn >> 24) & 0xf; - switch(op1) { - case 0x0: - case 0x1: - case 0x4: - case 0x5: - case 0x6: - case 0x7: - case 0x08: - case 0x09: - case 0xa: - case 0xb: - case 0xf: - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - case 0xc: - case 0xd: - case 0xe: - if (((insn >> 8) & 0xe) == 10) { - /* VFP. */ - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } - } else if (disas_coproc_insn(s, insn)) { - /* Coprocessor. */ + switch ((insn >> 24) & 0xf) { + case 0xc: + case 0xd: + case 0xe: + if (((insn >> 8) & 0xe) == 10) { + /* VFP. */ + if (disas_vfp_insn(s, insn)) { goto illegal_op; } - break; - default: - illegal_op: - unallocated_encoding(s); - break; + } else if (disas_coproc_insn(s, insn)) { + /* Coprocessor. */ + goto illegal_op; } + break; + default: + illegal_op: + unallocated_encoding(s); + break; } } From patchwork Wed Sep 4 19:30:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173006 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp391406ilq; Wed, 4 Sep 2019 13:14:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqzV/uXEkbnUSiXfnCda2ntJBbHNkxrfL4IV3PBm4eWgZ6BGG00WoAmlCUd2ZhG4VZtIcPsW X-Received: by 2002:a17:906:1f9a:: with SMTP id t26mr31651251ejr.252.1567628082675; Wed, 04 Sep 2019 13:14:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567628082; cv=none; d=google.com; s=arc-20160816; b=dnmmZVo2on6i30M0uKuVmJaFOrAB+ehD2MJn8K4gsZrqaOc/xBj3pow/R41mGpIsfQ 4M681YSGNzTyq/IZgUCCC7IqdaKovsiT+8FVcwx8umpnS4qDVM4SXzQtFpPsy5yTmSQr tq0DAg7FbTsgDdcmkfp939W5RFflXHMqwN4GlFfy4IMXTPhKgwpADo9FcgOFWOwLJFyQ 0dIsDOCjfB59bLBOOx/AidJJReiFO1nPcPx3BbieZj4MG7fwpxdEaDEoCOQL2iOutRRZ JW9WIpyPnQ9/Gps3WqdA/8VAK8T9AxO2ehth+U6tw20cp5ie28k3HC0zE50/hpMsc5mu dJXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=0Xeagu+uHVK2sO684+uTrIYgzxrvd15EJGaykrkk5Oc=; b=CX0TMlYLVPUZ9lprU9bpashQ14YQNwEnvHbe5LDywNxWELyFMhFM0F83AOaaPuPlLW 9JcTbpVpQE4UxXpky6JSY1xuvsjKw7CWrKwHLkvqvOh5BT4iXLj75IUiZOL2jWNHdCFA 4RbjFlHBhFhbH3uIDUzzN/Q0nyrdT1/Ch1G7odysr8dyUTAIxrAmPfOGKlnlTU10l+So tm/MQh05RtOGt38J2UaQ+A20cFA8qJnS6ffDJq7V5o3Wukl0Gm6c25jhp+dzIlYerZwZ 1eCg9sYiZlsQKSeHU9y7jEONaRHQ9PXxWHy6yhspW0z9rp6JOkJdjLfj8TFkjT89ws6L a1yw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BS78uIzA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:35 -0700 Message-Id: <20190904193059.26202-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::429 Subject: [Qemu-devel] [PATCH v4 45/69] target/arm: Add skeleton for T16 decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/translate.c | 6 ++++++ target/arm/Makefile.objs | 6 ++++++ target/arm/t16.decode | 20 ++++++++++++++++++++ 3 files changed, 32 insertions(+) create mode 100644 target/arm/t16.decode -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 7f2a46100e..7e530f1fdc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7560,6 +7560,7 @@ static int t32_branch24(DisasContext *s, int x) #include "decode-a32.inc.c" #include "decode-a32-uncond.inc.c" #include "decode-t32.inc.c" +#include "decode-t16.inc.c" /* Helpers to swap operands for reverse-subtract. */ static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) @@ -10669,6 +10670,11 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) TCGv_i32 tmp2; TCGv_i32 addr; + if (disas_t16(s, insn)) { + return; + } + /* fall back to legacy decoder */ + switch (insn >> 12) { case 0: case 1: diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 7806b4dac0..cf26c16f5f 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -43,12 +43,18 @@ target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE) $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\ "GEN", $(TARGET_DIR)$@) +target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) -w 16 --static-decode disas_t16 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + target/arm/translate-sve.o: target/arm/decode-sve.inc.c target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c target/arm/translate.o: target/arm/decode-a32.inc.c target/arm/translate.o: target/arm/decode-a32-uncond.inc.c target/arm/translate.o: target/arm/decode-t32.inc.c +target/arm/translate.o: target/arm/decode-t16.inc.c obj-y += tlb_helper.o debug_helper.o obj-y += translate.o op_helper.o diff --git a/target/arm/t16.decode b/target/arm/t16.decode new file mode 100644 index 0000000000..e954f61fe4 --- /dev/null +++ b/target/arm/t16.decode @@ -0,0 +1,20 @@ +# Thumb1 instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# From patchwork Wed Sep 4 19:30:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173001 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp384931ilq; Wed, 4 Sep 2019 13:08:43 -0700 (PDT) X-Google-Smtp-Source: APXvYqyzUYGZNdPyTjAb/UsUbzwaR2OftcDXXlyyBEOslTh4Ue+5vkUooUgxFLP9bGEcIbBrNkNn X-Received: by 2002:ac8:7242:: with SMTP id l2mr42385093qtp.4.1567627723426; Wed, 04 Sep 2019 13:08:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567627723; cv=none; d=google.com; s=arc-20160816; b=wWKDYtn6I32fsEAWZbjWLXc/J8kH0oS2Pvq+RUPwirwezUmDUmQSvJJxo063Voj6Iw QIcp/NeUZk3lKY31adg8HxI11JCKIodNygF4kh4+nD2eUv4RaqTDM3qeRzz5bLcpUewm 2JuIko9PSWGN2uXf4Yvmuo18zNvFZz+fTFVkEvc3i5VTiCyl6N+lFS1zeuCoQkQMd9JX srexAV3CaXEDz/kS+NpBECTJWcThqMcpf+ljIbb0qTHxYXNl5yHQWJ72d6N925j7dj89 pNXvIvbvsq13DiCOesc2CXbRLNHNPWaZLvu0P+fhTvyErEnmMgTwU3+2JQXdRrOituxL 5yww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=egisVGOg4CJ3QPg/JSR7AUyfTVGzQfFPHW96Z7DyXjs=; b=e/fCvxq0cqtAGAIYRUZperax8WbCTAkmtMFxpb7T1y6BTN0PooF25FWKgBAsD9Cyyl p9c+A5Ik2T+DM6WTlT0QaRVVAPtHZBkjX9t1T0RhuGTYE1acYKXsLncrwuzA3NEC9R6j gHYQ8sEjGX0KkXWILE7FlCGqN0uZONWNcDiwRLL4NGaxko5M19qr5wsbl2cAy+cabwSt TMl1UhRIWs21HUs+H3C/QKjzuqhFwVxaSlqBNjusZuaGePXO97CyMsu1dt9nRGoGqQ+V MPSHWU0svfl0b1fcWD3pLEVULOeXOEx9RPRtpoCgadQUvRDm57/c8CQFrGI3c51JtHQC KE0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=z2bWqD+U; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:36 -0700 Message-Id: <20190904193059.26202-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v4 46/69] target/arm: Convert T16 data-processing (two low regs) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 152 ++--------------------------------------- target/arm/t16.decode | 36 ++++++++++ 2 files changed, 43 insertions(+), 145 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 7e530f1fdc..b77922f808 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -445,13 +445,6 @@ static inline void gen_logic_CC(TCGv_i32 var) tcg_gen_mov_i32(cpu_ZF, var); } -/* T0 += T1 + CF. */ -static void gen_adc(TCGv_i32 t0, TCGv_i32 t1) -{ - tcg_gen_add_i32(t0, t0, t1); - tcg_gen_add_i32(t0, t0, cpu_CF); -} - /* dest = T0 + T1 + CF. */ static void gen_add_carry(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) { @@ -7553,6 +7546,11 @@ static int t32_branch24(DisasContext *s, int x) return x << 1; } +static int t16_setflags(DisasContext *s) +{ + return s->condexec_mask == 0; +} + /* * Include the generated decoders. */ @@ -10861,145 +10859,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) /* * 0b0100_00xx_xxxx_xxxx - * - Data-processing (two low registers) + * - Data-processing (two low registers), in decodetree */ - rd = insn & 7; - rm = (insn >> 3) & 7; - op = (insn >> 6) & 0xf; - if (op == 2 || op == 3 || op == 4 || op == 7) { - /* the shift/rotate ops want the operands backwards */ - val = rm; - rm = rd; - rd = val; - val = 1; - } else { - val = 0; - } - - if (op == 9) { /* neg */ - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else if (op != 0xf) { /* mvn doesn't read its first operand */ - tmp = load_reg(s, rd); - } else { - tmp = NULL; - } - - tmp2 = load_reg(s, rm); - switch (op) { - case 0x0: /* and */ - tcg_gen_and_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0x1: /* eor */ - tcg_gen_xor_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0x2: /* lsl */ - if (s->condexec_mask) { - gen_shl(tmp2, tmp2, tmp); - } else { - gen_helper_shl_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x3: /* lsr */ - if (s->condexec_mask) { - gen_shr(tmp2, tmp2, tmp); - } else { - gen_helper_shr_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x4: /* asr */ - if (s->condexec_mask) { - gen_sar(tmp2, tmp2, tmp); - } else { - gen_helper_sar_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x5: /* adc */ - if (s->condexec_mask) { - gen_adc(tmp, tmp2); - } else { - gen_adc_CC(tmp, tmp, tmp2); - } - break; - case 0x6: /* sbc */ - if (s->condexec_mask) { - gen_sub_carry(tmp, tmp, tmp2); - } else { - gen_sbc_CC(tmp, tmp, tmp2); - } - break; - case 0x7: /* ror */ - if (s->condexec_mask) { - tcg_gen_andi_i32(tmp, tmp, 0x1f); - tcg_gen_rotr_i32(tmp2, tmp2, tmp); - } else { - gen_helper_ror_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x8: /* tst */ - tcg_gen_and_i32(tmp, tmp, tmp2); - gen_logic_CC(tmp); - rd = 16; - break; - case 0x9: /* neg */ - if (s->condexec_mask) - tcg_gen_neg_i32(tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - break; - case 0xa: /* cmp */ - gen_sub_CC(tmp, tmp, tmp2); - rd = 16; - break; - case 0xb: /* cmn */ - gen_add_CC(tmp, tmp, tmp2); - rd = 16; - break; - case 0xc: /* orr */ - tcg_gen_or_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0xd: /* mul */ - tcg_gen_mul_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0xe: /* bic */ - tcg_gen_andc_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0xf: /* mvn */ - tcg_gen_not_i32(tmp2, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp2); - val = 1; - rm = rd; - break; - } - if (rd != 16) { - if (val) { - store_reg(s, rm, tmp2); - if (op != 0xf) - tcg_temp_free_i32(tmp); - } else { - store_reg(s, rd, tmp); - tcg_temp_free_i32(tmp2); - } - } else { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - } - break; + goto illegal_op; case 5: /* load/store register offset. */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index e954f61fe4..44e7250c55 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -18,3 +18,39 @@ # # This file is processed by scripts/decodetree.py # + +&s_rrr_shi !extern s rd rn rm shim shty +&s_rrr_shr !extern s rn rd rm rs shty +&s_rri_rot !extern s rn rd imm rot +&s_rrrr !extern s rd rn rm ra + +# Set S if the instruction is outside of an IT block. +%s !function=t16_setflags + +# Data-processing (two low registers) + +%reg_0 0:3 + +@lll_noshr ...... .... rm:3 rd:3 \ + &s_rrr_shi %s rn=%reg_0 shim=0 shty=0 +@xll_noshr ...... .... rm:3 rn:3 \ + &s_rrr_shi s=1 rd=0 shim=0 shty=0 +@lxl_shr ...... .... rs:3 rd:3 \ + &s_rrr_shr %s rm=%reg_0 rn=0 + +AND_rrri 010000 0000 ... ... @lll_noshr +EOR_rrri 010000 0001 ... ... @lll_noshr +MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL +MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR +MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR +ADC_rrri 010000 0101 ... ... @lll_noshr +SBC_rrri 010000 0110 ... ... @lll_noshr +MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR +TST_xrri 010000 1000 ... ... @xll_noshr +RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=0 rot=0 +CMP_xrri 010000 1010 ... ... @xll_noshr +CMN_xrri 010000 1011 ... ... @xll_noshr +ORR_rrri 010000 1100 ... ... @lll_noshr +MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0 +BIC_rrri 010000 1110 ... ... @lll_noshr +MVN_rxri 010000 1111 ... ... @lll_noshr From patchwork Wed Sep 4 19:30:37 2019 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v4 47/69] target/arm: Convert T16 load/store (register offset) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 51 ++---------------------------------------- target/arm/t16.decode | 15 +++++++++++++ 2 files changed, 17 insertions(+), 49 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index b77922f808..789abe9b87 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10864,55 +10864,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) goto illegal_op; case 5: - /* load/store register offset. */ - rd = insn & 7; - rn = (insn >> 3) & 7; - rm = (insn >> 6) & 7; - op = (insn >> 9) & 7; - addr = load_reg(s, rn); - tmp = load_reg(s, rm); - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - - if (op < 3) { /* store */ - tmp = load_reg(s, rd); - } else { - tmp = tcg_temp_new_i32(); - } - - switch (op) { - case 0: /* str */ - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 1: /* strh */ - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 2: /* strb */ - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 3: /* ldrsb */ - gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 4: /* ldr */ - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 5: /* ldrh */ - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 6: /* ldrb */ - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 7: /* ldrsh */ - gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - } - if (op >= 3) { /* load */ - store_reg(s, rd, tmp); - } else { - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; + /* load/store register offset, in decodetree */ + goto illegal_op; case 6: /* load/store word immediate offset */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 44e7250c55..83fe4363c7 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&ldst_rr !extern p w u rn rt rm shimm shtype # Set S if the instruction is outside of an IT block. %s !function=t16_setflags @@ -54,3 +55,17 @@ ORR_rrri 010000 1100 ... ... @lll_noshr MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0 BIC_rrri 010000 1110 ... ... @lll_noshr MVN_rxri 010000 1111 ... ... @lll_noshr + +# Load/store (register offset) + +@ldst_rr ....... rm:3 rn:3 rt:3 \ + &ldst_rr p=1 w=0 u=1 shimm=0 shtype=0 + +STR_rr 0101 000 ... ... ... @ldst_rr +STRH_rr 0101 001 ... ... ... @ldst_rr +STRB_rr 0101 010 ... ... ... @ldst_rr +LDRSB_rr 0101 011 ... ... ... @ldst_rr +LDR_rr 0101 100 ... ... ... @ldst_rr +LDRH_rr 0101 101 ... ... ... @ldst_rr +LDRB_rr 0101 110 ... ... ... @ldst_rr +LDRSH_rr 0101 111 ... ... ... @ldst_rr From patchwork Wed Sep 4 19:30:38 2019 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 48/69] target/arm: Convert T16 load/store (immediate offset) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 94 +++--------------------------------------- target/arm/t16.decode | 33 +++++++++++++++ 2 files changed, 38 insertions(+), 89 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 789abe9b87..4ae73d1c92 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10863,97 +10863,13 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) */ goto illegal_op; - case 5: - /* load/store register offset, in decodetree */ + case 5: /* load/store register offset, in decodetree */ + case 6: /* load/store word immediate offset, in decodetree */ + case 7: /* load/store byte immediate offset, in decodetree */ + case 8: /* load/store halfword immediate offset, in decodetree */ + case 9: /* load/store from stack, in decodetree */ goto illegal_op; - case 6: - /* load/store word immediate offset */ - rd = insn & 7; - rn = (insn >> 3) & 7; - addr = load_reg(s, rn); - val = (insn >> 4) & 0x7c; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 7: - /* load/store byte immediate offset */ - rd = insn & 7; - rn = (insn >> 3) & 7; - addr = load_reg(s, rn); - val = (insn >> 6) & 0x1f; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 8: - /* load/store halfword immediate offset */ - rd = insn & 7; - rn = (insn >> 3) & 7; - addr = load_reg(s, rn); - val = (insn >> 5) & 0x3e; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 9: - /* load/store from stack */ - rd = (insn >> 8) & 7; - addr = load_reg(s, 13); - val = (insn & 0xff) * 4; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - case 10: /* * 0b1010_xxxx_xxxx_xxxx diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 83fe4363c7..1cf79789ac 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &ldst_rr !extern p w u rn rt rm shimm shtype +&ldst_ri !extern p w u rn rt imm # Set S if the instruction is outside of an IT block. %s !function=t16_setflags @@ -69,3 +70,35 @@ LDR_rr 0101 100 ... ... ... @ldst_rr LDRH_rr 0101 101 ... ... ... @ldst_rr LDRB_rr 0101 110 ... ... ... @ldst_rr LDRSH_rr 0101 111 ... ... ... @ldst_rr + +# Load/store word/byte (immediate offset) + +%imm5_6x4 6:5 !function=times_4 + +@ldst_ri_1 ..... imm:5 rn:3 rt:3 \ + &ldst_ri p=1 w=0 u=1 +@ldst_ri_4 ..... ..... rn:3 rt:3 \ + &ldst_ri p=1 w=0 u=1 imm=%imm5_6x4 + +STR_ri 01100 ..... ... ... @ldst_ri_4 +LDR_ri 01101 ..... ... ... @ldst_ri_4 +STRB_ri 01110 ..... ... ... @ldst_ri_1 +LDRB_ri 01111 ..... ... ... @ldst_ri_1 + +# Load/store halfword (immediate offset) + +%imm5_6x2 6:5 !function=times_2 +@ldst_ri_2 ..... ..... rn:3 rt:3 \ + &ldst_ri p=1 w=0 u=1 imm=%imm5_6x2 + +STRH_ri 10000 ..... ... ... @ldst_ri_2 +LDRH_ri 10001 ..... ... ... @ldst_ri_2 + +# Load/store (SP-relative) + +%imm8_0x4 0:8 !function=times_4 +@ldst_spec_i ..... rt:3 ........ \ + &ldst_ri p=1 w=0 u=1 imm=%imm8_0x4 + +STR_ri 10010 ... ........ @ldst_spec_i rn=13 +LDR_ri 10011 ... ........ @ldst_spec_i rn=13 From patchwork Wed Sep 4 19:30:39 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:39 -0700 Message-Id: <20190904193059.26202-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62d Subject: [Qemu-devel] [PATCH v4 49/69] target/arm: Convert T16 add pc/sp (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 12 +----------- target/arm/t16.decode | 7 +++++++ 2 files changed, 8 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 4ae73d1c92..d8a4c7bf99 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10868,19 +10868,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) case 7: /* load/store byte immediate offset, in decodetree */ case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ + case 10: /* add PC/SP (immediate), in decodetree */ goto illegal_op; - case 10: - /* - * 0b1010_xxxx_xxxx_xxxx - * - Add PC/SP (immediate) - */ - rd = (insn >> 8) & 7; - val = (insn & 0xff) * 4; - tmp = add_reg_for_lit(s, insn & (1 << 11) ? 13 : 15, val); - store_reg(s, rd, tmp); - break; - case 11: /* misc */ op = (insn >> 8) & 0xf; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 1cf79789ac..71b3e8f02e 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&ri !extern rd imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm @@ -102,3 +103,9 @@ LDRH_ri 10001 ..... ... ... @ldst_ri_2 STR_ri 10010 ... ........ @ldst_spec_i rn=13 LDR_ri 10011 ... ........ @ldst_spec_i rn=13 + +# Add PC/SP (immediate) + +ADR 10100 rd:3 ........ imm=%imm8_0x4 +ADD_rri 10101 rd:3 ........ \ + &s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP From patchwork Wed Sep 4 19:30:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173030 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp416726ilq; Wed, 4 Sep 2019 13:41:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqwRfNcDASMJHsxLkEyoq/51vvTrCnll4jK85Rig6E93K6GrLPilXkr8vqDCwaCitcdClz7O X-Received: by 2002:a37:410:: with SMTP id 16mr39013863qke.52.1567629687408; Wed, 04 Sep 2019 13:41:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567629687; cv=none; d=google.com; s=arc-20160816; b=ZW+DpccsxFJhdytJ4vFWtx4Xm6+ZJ/Jet2SvAX/YYXmozDcbv/eZRcq8gLTCNbFqID HpI3ZMHQ2jctD1wSukBQlwDbwHoqO9SJL+9EnkfaIL1Lo1iOPrmKP6Mp+El0WjTOCo4W eRY+dmMGl+jtUGesvUT/mKjaTOEUBwpVJmQHb8RrrrJloCtXlDd2m3qlElcwh8xK7QwL AyrziJJ1tmAb1UlpLMc4wGDWd7eOHSDFmviXHlnqHk8BNRKIA/cB8IpHaNXhQMHXtZqg 3E/Rkaer4zZNCQOA+x0T3wVZkrto7opjlP6MWbtpijAfXUS2+NUb8J2O5MGJzRP9OW2R OX/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=w0yZvSWJxMpGMZQus1AoRlEpuCLgbCFvsCSBHnvLgJY=; b=Bd5l6EhgpqFTaf8b4m7JyFFXML269nBeyWMGS1wpF7IvjDqPxfcJJtl22XLpjYWPSg I76gBbtFafNv5lzZliMyMpF9ED56xjEf6Me9BINzIUtNoQ69WiFy+G+g7oCpAbYQ0XQj Jcdp2eaIJPZglPm5D5mJ5sCWWmskidzyqaWpAP53rHDRE9s03XoCjfRgxaWD5xpNmu1u wNjpd64SHklXovuWuw/mMUk0skxOeyJI/1GrFecm9kGkOb/9pS95vk2W22Xpn83N0OW6 AsTEa3mbzKqBMsMCCjDMpiBb2le0snzl7jDMoAh1r47HDkNertQm6X4BW2s3u9QN9dRN c+GQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=oAWMyx+O; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:40 -0700 Message-Id: <20190904193059.26202-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 50/69] target/arm: Convert T16 load/store multiple X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 48 ++++++++---------------------------------- target/arm/t16.decode | 8 +++++++ 2 files changed, 17 insertions(+), 39 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index d8a4c7bf99..f9d4b619fa 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10092,6 +10092,14 @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) return do_ldm(s, a, 2); } +static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a) +{ + /* Writeback is conditional on the base register not being loaded. */ + a->w = !(a->list & (1 << a->rn)); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return do_ldm(s, a, 1); +} + /* * Branch, branch with link */ @@ -10869,6 +10877,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ case 10: /* add PC/SP (immediate), in decodetree */ + case 12: /* load/store multiple, in decodetree */ goto illegal_op; case 11: @@ -11092,45 +11101,6 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) } break; - case 12: - { - /* load/store multiple */ - TCGv_i32 loaded_var = NULL; - rn = (insn >> 8) & 0x7; - addr = load_reg(s, rn); - for (i = 0; i < 8; i++) { - if (insn & (1 << i)) { - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i == rn) { - loaded_var = tmp; - } else { - store_reg(s, i, tmp); - } - } else { - /* store */ - tmp = load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - /* advance to the next address */ - tcg_gen_addi_i32(addr, addr, 4); - } - } - if ((insn & (1 << rn)) == 0) { - /* base reg not in list: base register writeback */ - store_reg(s, rn, addr); - } else { - /* base reg in list: if load, complete it now */ - if (insn & (1 << 11)) { - store_reg(s, rn, loaded_var); - } - tcg_temp_free_i32(addr); - } - break; - } case 13: /* conditional branch or swi */ cond = (insn >> 8) & 0xf; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 71b3e8f02e..a7a437f930 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -26,6 +26,7 @@ &ri !extern rd imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm +&ldst_block !extern rn i b u w list # Set S if the instruction is outside of an IT block. %s !function=t16_setflags @@ -109,3 +110,10 @@ LDR_ri 10011 ... ........ @ldst_spec_i rn=13 ADR 10100 rd:3 ........ imm=%imm8_0x4 ADD_rri 10101 rd:3 ........ \ &s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP + +# Load/store multiple + +@ldstm ..... rn:3 list:8 &ldst_block i=1 b=0 u=0 w=1 + +STM 11000 ... ........ @ldstm +LDM_t16 11001 ... ........ @ldstm From patchwork Wed Sep 4 19:30:41 2019 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 51/69] target/arm: Convert T16 add/sub (3 low, 2 low and imm) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 ++------------------------ target/arm/t16.decode | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 24 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index f9d4b619fa..45d617a2d3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10691,31 +10691,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) * 0b0001_1xxx_xxxx_xxxx * - Add, subtract (three low registers) * - Add, subtract (two low registers and immediate) + * In decodetree. */ - rn = (insn >> 3) & 7; - tmp = load_reg(s, rn); - if (insn & (1 << 10)) { - /* immediate */ - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, (insn >> 6) & 7); - } else { - /* reg */ - rm = (insn >> 6) & 7; - tmp2 = load_reg(s, rm); - } - if (insn & (1 << 9)) { - if (s->condexec_mask) - tcg_gen_sub_i32(tmp, tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - } else { - if (s->condexec_mask) - tcg_gen_add_i32(tmp, tmp, tmp2); - else - gen_add_CC(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); + goto illegal_op; } else { /* shift immediate */ rm = (insn >> 3) & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index a7a437f930..2b5f368d31 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -117,3 +117,19 @@ ADD_rri 10101 rd:3 ........ \ STM 11000 ... ........ @ldstm LDM_t16 11001 ... ........ @ldstm + +# Add/subtract (three low registers) + +@addsub_3 ....... rm:3 rn:3 rd:3 \ + &s_rrr_shi %s shim=0 shty=0 + +ADD_rrri 0001100 ... ... ... @addsub_3 +SUB_rrri 0001101 ... ... ... @addsub_3 + +# Add/subtract (two low registers and immediate) + +@addsub_2i ....... imm:3 rn:3 rd:3 \ + &s_rri_rot %s rot=0 + +ADD_rri 0001 110 ... ... ... @addsub_2i +SUB_rri 0001 111 ... ... ... @addsub_2i From patchwork Wed Sep 4 19:30:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173017 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp401581ilq; Wed, 4 Sep 2019 13:25:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqyoxfHtz74NdanoTpsQQFtMi+SXy/WI8RsisB7jeIQC8Ud3tR7x3GsLFYWKZkKXWJkdr8mD X-Received: by 2002:a50:c052:: with SMTP id u18mr156838edd.88.1567628747170; Wed, 04 Sep 2019 13:25:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567628747; cv=none; d=google.com; s=arc-20160816; b=tRsqjuOA/nfIG6Z/sNpPS7N2E6WWUgouw/PIhGX1RfKOX5ex+4o9skcNAxUJBSp4Vq LV+Z2Sz8WKIWCk4AZkoYXDWBfeEHLYPuCiujA0ek7+k85h8gKnmz5V276exoWQ56Vy6O b2ezgwoL2pf1dygMeDk/y5aP6VBSM+2BMAZVNvuJcvK3Gs+msQj6KShS3LFSTE660y6W fbAJMfgt1MrzIBvUPSD8KPEjJ0u6oZ07wvPEN+EVGqQ+mOBEPk7yCDIs0NhIk3RY+eEp MFxbhaLg6Ks4i+b0uNv8iwBEax+xJT/Y85EDTU2MzIVHsPq+/VKzTKjXOX3Ttx7E3Hmc uBJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=GTpzfRqA1Z7CTTR4kjGQDvZeJQsqYpR7KKBaZOTKQX8=; b=XquxFQ94VnUiUz05J9IipGjncuQQXVCcjiLmZP6MsJjbjr4V1kCsq8VjSitKPysIX2 EPjlUHJwy//s4BMdjYKoUW02cXL6Pw6AZwo+tIbE2Pd7Bq4Fufxk86kTFr04+xjRWwT0 vZlRfusPXOiDVD9dbzFH8pJOP0h0tbA/zNTvhFV9RqEoMHh4ANE2SHaTcM2rA7w8HZ3Y 0Nj9mCCnNMVE1blrILHPnB3tl3qmEJQJYqO5Sv8nyYkJZgVrDc1Eh6937ZxplKLYPdrD /pgbTPUOpZTZ8+I/kQrCgyjQie87+OkQuWdezIRuVC6tuLR7K2jNeWnIAr/I6yLuy2+j Iuyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=xBr3jDB+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 52/69] target/arm: Convert T16 one low register and immediate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 44 ++---------------------------------------- target/arm/t16.decode | 11 +++++++++++ 2 files changed, 13 insertions(+), 42 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 45d617a2d3..405176527c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10705,48 +10705,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) store_reg(s, rd, tmp); } break; - case 2: case 3: - /* - * 0b001x_xxxx_xxxx_xxxx - * - Add, subtract, compare, move (one low register and immediate) - */ - op = (insn >> 11) & 3; - rd = (insn >> 8) & 0x7; - if (op == 0) { /* mov */ - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, insn & 0xff); - if (!s->condexec_mask) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - } else { - tmp = load_reg(s, rd); - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, insn & 0xff); - switch (op) { - case 1: /* cmp */ - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - break; - case 2: /* add */ - if (s->condexec_mask) - tcg_gen_add_i32(tmp, tmp, tmp2); - else - gen_add_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; - case 3: /* sub */ - if (s->condexec_mask) - tcg_gen_sub_i32(tmp, tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; - } - } - break; + case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ + goto illegal_op; case 4: if (insn & (1 << 11)) { rd = (insn >> 8) & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 2b5f368d31..0654275e68 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -133,3 +133,14 @@ SUB_rrri 0001101 ... ... ... @addsub_3 ADD_rri 0001 110 ... ... ... @addsub_2i SUB_rri 0001 111 ... ... ... @addsub_2i + +# Add, subtract, compare, move (one low register and immediate) + +%reg_8 8:3 +@arith_1i ..... rd:3 imm:8 \ + &s_rri_rot rot=0 rn=%reg_8 + +MOV_rxi 00100 ... ........ @arith_1i %s +CMP_xri 00101 ... ........ @arith_1i s=1 +ADD_rri 00110 ... ........ @arith_1i %s +SUB_rri 00111 ... ........ @arith_1i %s From patchwork Wed Sep 4 19:30:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173010 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp395475ilq; Wed, 4 Sep 2019 13:18:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqyMFZ6K1Fusp0fYKrYGYW2YDQv/7+rcePdfdyCjZgrvkByrgcyDa4NyZwbLB7lbWEt9+XtX X-Received: by 2002:a05:6402:160d:: with SMTP id f13mr70966edv.227.1567628327149; Wed, 04 Sep 2019 13:18:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567628327; cv=none; d=google.com; s=arc-20160816; b=Wb4Ur2guljHKo1yB0XvXZH9V40VgwWCxyhyekQ5SD8fBoXOfn79QfegN+zkhdrz7Fp fwDR0eAEZ2FcGGBrDx8U2zkXujZkqkGZMLjcgpw0CHCidfvu9y5oPI1SIqUaH2wp1p4S 9Zh6sqZOP55yeriRGBrhJyLFWX8MuOy7F3u/3XIpjx/qjMphc18NJmxarEoR8HBlbp5m hcJdMg5btsx0IaE46vQ366Bof86Tt8w0Q1OVMjvYyuyVCQunjJ4kYmCotJfDB3UvZrLp /J7/N0RLKu+IupnIWSG8dhRtILnUA6fcH5RObqSe1EaPLQioa2/yhqbjH4ljx/u8yZ/3 UBJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=kYh+jTzMtTJhUz3xyrw306VQI42LXaHYhBmdbXyrNe4=; b=pwmHQumUxzIx6ZrbkFIMb7qAzUXcSFzyr4g7RQ+EbNP/DNHpsQnxDbSUdi/1uIoTci Pb++ti4+5iHnUV0HLgJsJwFQ8VVZnNfDJlS1w2RLIe+DxXifH+nhSLFJmziYArhP9nhs tmTBL6hgUQya6ZqOSSfU/y3E07mKs+cwQCBt5q5ZymqgOCpBpTycTnhRY4y/sm6YkpMp szyYis5D32Xoq1BiQnsZlEI2BHzBi8o4X0VQi2Gwu3Y6en+Kn1E5sJb1yk2FUlaiOMAj t5ttkigoGX0Mea7LRmBA2QKRH8xAqPdrr+eLa0qj+JCstDsyNP5nhVVginJ0Od+s9vWw WkEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=j8z0f6M1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:43 -0700 Message-Id: <20190904193059.26202-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v4 53/69] target/arm: Convert T16 branch and exchange X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 70 +++++++++++++++++------------------------- target/arm/t16.decode | 10 ++++++ 2 files changed, 39 insertions(+), 41 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 405176527c..e6ef935247 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8364,7 +8364,7 @@ static bool trans_BX(DisasContext *s, arg_BX *a) if (!ENABLE_ARCH_4T) { return false; } - gen_bx(s, load_reg(s, a->rm)); + gen_bx_excret(s, load_reg(s, a->rm)); return true; } @@ -8391,6 +8391,32 @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a) return true; } +/* + * BXNS/BLXNS: only exist for v8M with the security extensions, + * and always UNDEF if NonSecure. We don't implement these in + * the user-only mode either (in theory you can use them from + * Secure User mode but they are too tied in to system emulation). + */ +static bool trans_BXNS(DisasContext *s, arg_BXNS *a) +{ + if (!s->v8m_secure || IS_USER_ONLY) { + unallocated_encoding(s); + } else { + gen_bxns(s, a->rm); + } + return true; +} + +static bool trans_BLXNS(DisasContext *s, arg_BLXNS *a) +{ + if (!s->v8m_secure || IS_USER_ONLY) { + unallocated_encoding(s); + } else { + gen_blxns(s, a->rm); + } + return true; +} + static bool trans_CLZ(DisasContext *s, arg_CLZ *a) { TCGv_i32 tmp; @@ -10756,49 +10782,11 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) } break; case 3: - { /* 0b0100_0111_xxxx_xxxx * - branch [and link] exchange thumb register + * In decodetree */ - bool link = insn & (1 << 7); - - if (insn & 3) { - goto undef; - } - if (link) { - ARCH(5); - } - if ((insn & 4)) { - /* BXNS/BLXNS: only exists for v8M with the - * security extensions, and always UNDEF if NonSecure. - * We don't implement these in the user-only mode - * either (in theory you can use them from Secure User - * mode but they are too tied in to system emulation.) - */ - if (!s->v8m_secure || IS_USER_ONLY) { - goto undef; - } - if (link) { - gen_blxns(s, rm); - } else { - gen_bxns(s, rm); - } - break; - } - /* BLX/BX */ - tmp = load_reg(s, rm); - if (link) { - val = (uint32_t)s->base.pc_next | 1; - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, val); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - } else { - /* Only BX works as exception-return, not BLX */ - gen_bx_excret(s, tmp); - } - break; - } + goto illegal_op; } break; } diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 0654275e68..edddbfb9b8 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &ri !extern rd imm +&r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list @@ -144,3 +145,12 @@ MOV_rxi 00100 ... ........ @arith_1i %s CMP_xri 00101 ... ........ @arith_1i s=1 ADD_rri 00110 ... ........ @arith_1i %s SUB_rri 00111 ... ........ @arith_1i %s + +# Branch and exchange + +@branchr .... .... . rm:4 ... &r + +BX 0100 0111 0 .... 000 @branchr +BLX_r 0100 0111 1 .... 000 @branchr +BXNS 0100 0111 0 .... 100 @branchr +BLXNS 0100 0111 1 .... 100 @branchr From patchwork Wed Sep 4 19:30:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173015 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp399301ilq; Wed, 4 Sep 2019 13:23:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqxBbqQIW9f9gVg/Hxg4ZGjzMJnteTNzZA8E4dmJMMAZMX50rtqWCz6I2EdmXHEu1GHRbYbl X-Received: by 2002:ac8:2707:: with SMTP id g7mr32429709qtg.294.1567628589509; Wed, 04 Sep 2019 13:23:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567628589; cv=none; d=google.com; s=arc-20160816; b=Gb/+3eHNUovZSFpLRRyLX8Ih8XoqH8myZHowhDiob2wYKDzLh6hFAz+1qZdqlU9gLZ aCFQVLBjTgbfnWmtEg+0Mgc8Meq2hE176Kp6iuDorxUuYPW5aeif/nUd9VxXSlBw5NRv ahmmRQbOQt/yN9hq4BghI1HemHG8oeNtlDfmL2vcNVAshj0WivcTACvS1P9IjfwNt0D4 Wy9HejUhwiLIyh1mbSce9y69uhuLmpBQ9kf3A+hj/+LvnAClE7bqbjoaB9K2gsWLJO6b o+SLO8429QQw93YHCn5Q1oM6kEn2xwponZfWnxmrRs/jf3jivxi7y09je+FdZ0l5octf c1cQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=2ZLJXIt+PxkZztXfn8SSMwPCXqB6/2ClBwSngJqOcn0=; b=u1mZiLAnxSv5+0biBSJfZOnziPw/vx/N08b92wk2aTiIN9CsTjEFFLfwU7JYRlNOg8 RVJDm1pbYi8kaRAC4e5i6EMCe53RxP1mE37m6EgPlV3S3BOrQQ4u6fhW9rNLlyLjvfC6 tNspSUx6G+VwXR/HkYcGajIt9no63Fo+qxAjSpMJkScnQO17PTqfEfocHR6OCLVV0E6B 2p+AcM927qGu+VPSDWj/EDmBCrBaJF9gn/YMqEhpE1apvhbb7IYwZUkXHemcLefOLETO IMOD+AQuqc4Z0xxOW26+hiA4nFS90cQTovbbOEWlEQxFpZ+COF1sEVrhIwfCEQis5phE 62bQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NaaG8ZLN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:44 -0700 Message-Id: <20190904193059.26202-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 54/69] target/arm: Convert T16 add, compare, move (two high registers) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 49 ++---------------------------------------- target/arm/t16.decode | 10 +++++++++ 2 files changed, 12 insertions(+), 47 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index e6ef935247..73c8863134 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10745,55 +10745,10 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) store_reg(s, rd, tmp); break; } - if (insn & (1 << 10)) { - /* 0b0100_01xx_xxxx_xxxx - * - data processing extended, branch and exchange - */ - rd = (insn & 7) | ((insn >> 4) & 8); - rm = (insn >> 3) & 0xf; - op = (insn >> 8) & 3; - switch (op) { - case 0: /* add */ - tmp = load_reg(s, rd); - tmp2 = load_reg(s, rm); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rd == 13) { - /* ADD SP, SP, reg */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } - break; - case 1: /* cmp */ - tmp = load_reg(s, rd); - tmp2 = load_reg(s, rm); - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - break; - case 2: /* mov/cpy */ - tmp = load_reg(s, rm); - if (rd == 13) { - /* MOV SP, reg */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } - break; - case 3: - /* 0b0100_0111_xxxx_xxxx - * - branch [and link] exchange thumb register - * In decodetree - */ - goto illegal_op; - } - break; - } /* - * 0b0100_00xx_xxxx_xxxx - * - Data-processing (two low registers), in decodetree + * - Data-processing (two low registers), in decodetree + * - data processing extended, branch and exchange, in decodetree */ goto illegal_op; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index edddbfb9b8..5a570484e3 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -146,6 +146,16 @@ CMP_xri 00101 ... ........ @arith_1i s=1 ADD_rri 00110 ... ........ @arith_1i %s SUB_rri 00111 ... ........ @arith_1i %s +# Add, compare, move (two high registers) + +%reg_0_7 7:1 0:3 +@addsub_2h .... .... . rm:4 ... \ + &s_rrr_shi rd=%reg_0_7 rn=%reg_0_7 shim=0 shty=0 + +ADD_rrri 0100 0100 . .... ... @addsub_2h s=0 +CMP_xrri 0100 0101 . .... ... @addsub_2h s=1 +MOV_rxri 0100 0110 . .... ... @addsub_2h s=0 + # Branch and exchange @branchr .... .... . rm:4 ... &r From patchwork Wed Sep 4 19:30:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173034 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp420598ilq; Wed, 4 Sep 2019 13:46:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqy8tZHl3Yqm6rhwpNO8IUZuAjlXHeoNOjUmQi0lBgOro11KdOvEAJdhtrdQnOPV5v+0fRa7 X-Received: by 2002:a37:a44f:: with SMTP id n76mr30540392qke.414.1567629960887; Wed, 04 Sep 2019 13:46:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567629960; cv=none; d=google.com; s=arc-20160816; b=M7y10HVVtIUdwfyyZAJuZJpb6W0K11CU+O/8gNxb4P5NIZdVe3qFbBuXkYaxd4DICH T78fRlg+jj+zv9SBHWSjY00jhoD+DPnueofN35nN7xfW6xy9aC0Ma/TVBZ7JkEwOYUtu 2gvIP5f9PWY2FZjUyvHfqSjt0GCmc5kXDdKGZizKa9JyCQTyt9RKx0J5+V/B2E8HkmNI G9cdKcZmAOs6ylYjgWhPfxXYk6D28KquG9Yac3zvDrMwfsmJqPEhoq+otx8ToFlkSuow 6jBL0HGh3AdzeeSpMmOl8XqCTLwnhG5UW/B+E2Oi9LgVQ9fhQqxfUsAae02T4GQqHz+n S2ug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=RL68ZjIe5eYQCwpJOU1fJcxAoSZgrEZ6K/Zv64QpDaE=; b=mrJl2xW36BrkmW8Hw/R5vADpMGp73WdZg/FqK9krgNAjKGg0CsQuqJjaRz79l4MZNC isPWxjFQYwGWoGL3MWa9nErWHfGFhZMGj4PBP656di7PBeeHyyCE8WgM/eRwoEqBfkmD c5/vd9FrZiJKjjsIfgZ6x3FfMujYGggsKAccgW7Sxd05OG7ahMnUl9/Z114b1spWYEQO lk7qeqsjC5oqmd9duZW3EkHqlPc8/G6H6UYXCzK+/11WpB5tHLlWXJ6cFKOQ08TldZJ1 ARoBZ6AYfdYbnJtU8PeUgqnCRmfiWnTLaOL4/zS0xSb0tnktCxPUpTvu5z8pZG0zU/Nh qmhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=lTWfIa2p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v4 55/69] target/arm: Convert T16 adjust sp (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 15 ++------------- target/arm/t16.decode | 9 +++++++++ 2 files changed, 11 insertions(+), 13 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 73c8863134..8399a2c1f6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10765,19 +10765,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) /* misc */ op = (insn >> 8) & 0xf; switch (op) { - case 0: - /* - * 0b1011_0000_xxxx_xxxx - * - ADD (SP plus immediate) - * - SUB (SP minus immediate) - */ - tmp = load_reg(s, 13); - val = (insn & 0x7f) * 4; - if (insn & (1 << 7)) - val = -(int32_t)val; - tcg_gen_addi_i32(tmp, tmp, val); - store_sp_checked(s, tmp); - break; + case 0: /* add/sub (sp, immediate), in decodetree */ + goto illegal_op; case 2: /* sign/zero extend. */ ARCH(6); diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 5a570484e3..b425b86795 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -156,6 +156,15 @@ ADD_rrri 0100 0100 . .... ... @addsub_2h s=0 CMP_xrri 0100 0101 . .... ... @addsub_2h s=1 MOV_rxri 0100 0110 . .... ... @addsub_2h s=0 +# Adjust SP (immediate) + +%imm7_0x4 0:7 !function=times_4 +@addsub_sp_i .... .... . ....... \ + &s_rri_rot s=0 rd=13 rn=13 rot=0 imm=%imm7_0x4 + +ADD_rri 1011 0000 0 ....... @addsub_sp_i +SUB_rri 1011 0000 1 ....... @addsub_sp_i + # Branch and exchange @branchr .... .... . rm:4 ... &r From patchwork Wed Sep 4 19:30:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173007 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp392893ilq; Wed, 4 Sep 2019 13:16:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqz6v6CLWXzxhA+IuBoP4XXtJiqBgQnwiFx4JBHT0c9l9I+05MJMZwyUxRRit+euthvt9bHN X-Received: by 2002:aa7:c649:: with SMTP id z9mr77512edr.97.1567628169262; Wed, 04 Sep 2019 13:16:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567628169; cv=none; d=google.com; s=arc-20160816; b=Pgv1qktnd8mosqQKbjBFyFjLV4ina8zR9JDpvuRtBAeecVY80uNF4nKgbqesPXk+er BNGRa8pCpcTXfR9MLTtK0TumONhN1FYoiTsqL9u+QIAle1Rw3sET6glfVy+tT15qTHJD BrjTzdLmytPMkFALs668UTdDerjTF0CTNwICoD4Li91FyOX1Kk569+sclJVEcc1fBURP qTSPuygT64DWJgFY7w8zBhHYDWI+UPB8chCepw6AMTpLJuxBsUbriLKWFnBHQm2rBqBZ DUUkV8XpjWYh9IVDrbwcrQYQkck+8oyyof9j6t41oN87ot33KBHrIKA3xQZrNNXDHFMg SUEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=hhcY0Qa7fXCZ0Y1BiAhkkX6indoh0p/z8TLYSSed1LE=; b=zfsLgOP4FGoCUTaVYcNwjTTTNMEmpSc7blAtwQXi+QZSGYZMF2z9mvLK2vL1e//uYC SU38MZOPdsBvPg5M56UmBVhjKfXXGpEoIYHppSTI6zQcdAn2QEagoxD8j/APbr3Hzd3G Eil9k1dmSOj//PdmXok0bIdaQqHRyqEvGVkDziQfrY9Sz5ja8FU/xVlhokePhuUHNjnd 1sHD0SVhGYru0xKMvuQh+mXksXRA09tmEMefgyKT6FzOAHSj8uDR3v7URH1jIsoL2NZW xhs01gVh2GwAQ2F4bz2j8F6StmzQjE878ksIb5llo3AGJxi2W3Wi9K9EEQDcG8/g1Pmk OpLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IqIdEnms; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v4 56/69] target/arm: Convert T16, extract X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 14 +------------- target/arm/t16.decode | 10 ++++++++++ 2 files changed, 11 insertions(+), 13 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 8399a2c1f6..09c05de320 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10766,21 +10766,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) op = (insn >> 8) & 0xf; switch (op) { case 0: /* add/sub (sp, immediate), in decodetree */ + case 2: /* sign/zero extend, in decodetree */ goto illegal_op; - case 2: /* sign/zero extend. */ - ARCH(6); - rd = insn & 7; - rm = (insn >> 3) & 7; - tmp = load_reg(s, rm); - switch ((insn >> 6) & 3) { - case 0: gen_sxth(tmp); break; - case 1: gen_sxtb(tmp); break; - case 2: gen_uxth(tmp); break; - case 3: gen_uxtb(tmp); break; - } - store_reg(s, rd, tmp); - break; case 4: case 5: case 0xc: case 0xd: /* * 0b1011_x10x_xxxx_xxxx diff --git a/target/arm/t16.decode b/target/arm/t16.decode index b425b86795..b5b5086e8a 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&rrr_rot !extern rd rn rm rot &ri !extern rd imm &r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype @@ -173,3 +174,12 @@ BX 0100 0111 0 .... 000 @branchr BLX_r 0100 0111 1 .... 000 @branchr BXNS 0100 0111 0 .... 100 @branchr BLXNS 0100 0111 1 .... 100 @branchr + +# Extend + +@extend .... .... .. rm:3 rd:3 &rrr_rot rn=15 rot=0 + +SXTAH 1011 0010 00 ... ... @extend +SXTAB 1011 0010 01 ... ... @extend +UXTAH 1011 0010 10 ... ... @extend +UXTAB 1011 0010 11 ... ... @extend From patchwork Wed Sep 4 19:30:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173013 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp397266ilq; Wed, 4 Sep 2019 13:20:48 -0700 (PDT) X-Google-Smtp-Source: APXvYqxEzGtNi4iD9LLAmL51mSffxR47PejoDAQFrKdQ/fqs17Tw+E91rdLbsgq7uA9wotOnOWwj X-Received: by 2002:a17:906:a954:: with SMTP id hh20mr35133183ejb.196.1567628448895; Wed, 04 Sep 2019 13:20:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567628448; cv=none; d=google.com; s=arc-20160816; b=YRB/IYPiDHWmcwUhfCh5Bczu20WRnEA3IR6WbpyA2p0p3Zfa03sXGIgb1pmTgdh+hy Hc4CVQFztKVo6RnqEmR0kSx4ofXnVsAWmyCzu86w03b1egI1JZZUDNhJfznJLsnvnQg1 6tg0r7MGSeGE7a5R1Bsan00Jc2YEHwIWw116qbmQ/7qY7s3Gg18AYYluohT9Hl6tTeN+ TCjIIr3l5BikqClV/GeL9HwqKE2igWl6oKPjCpTY0DuoCnfQTg6Uqfjqf6GrUIur+NdX Rt7cfK9XiZcPdo0bl9YRl9JRktuoI4+IOcYWcHhsKv4oRYCLrSVvHiHbhtlMsrwcgYjN 95+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=fMRa2kGO1W6JycMdagL8+nOz15aN9a5pAkRiDJ3RJXk=; b=xRiod12wOc/3OC017SmPBVd2Fu5GFhF8SXfQHVlVF90KK2UGicZBx9A196aauzZICd B7iJ9u/ZS5qBknjm9u3+hLoFH9SOGEm2t92Qio3HwnbjASGILXWvLJalG5I2PYkJ29ca iLj8EaugKoGJ1otAPQ9bMev1BE2UxmtXCHivXqqWnv41CQWQuZpyzEmW9G95MOQKcc/x gSP/Oz9+JWHo13hBidQSSHoeQeWdBTeh4OZQlyXPbVN7221eD74FrzEDs2Sdd+kTDpk6 3UXHgxIPI8wwTJQousjL8xHcPnf3pJyRxx8lAgUpbHwyMROU79i34ZmLXrHAh7Np9I9t snPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=t9LNCLqq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:47 -0700 Message-Id: <20190904193059.26202-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v4 57/69] target/arm: Convert T16, Change processor state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a check for ARMv6 in trans_CPS. We had this correct in the T16 path, but had previously forgotten the check on the A32 and T32 paths. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Fix cps architecture checks. Rename s/v6m/v7m/g --- target/arm/translate.c | 84 +++++++++++++++++++----------------------- target/arm/t16.decode | 12 ++++++ 2 files changed, 50 insertions(+), 46 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 09c05de320..ce394ddb00 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7496,6 +7496,11 @@ static int negate(DisasContext *s, int x) return -x; } +static int plus_2(DisasContext *s, int x) +{ + return x + 2; +} + static int times_2(DisasContext *s, int x) { return x * 2; @@ -10268,7 +10273,7 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a) { uint32_t mask, val; - if (arm_dc_feature(s, ARM_FEATURE_M)) { + if (!ENABLE_ARCH_6 || arm_dc_feature(s, ARM_FEATURE_M)) { return false; } if (IS_USER(s)) { @@ -10302,6 +10307,36 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a) return true; } +static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a) +{ + TCGv_i32 tmp, addr; + + if (!arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (IS_USER(s)) { + /* Implemented as NOP in user mode. */ + return true; + } + + tmp = tcg_const_i32(a->im); + /* FAULTMASK */ + if (a->F) { + addr = tcg_const_i32(19); + gen_helper_v7m_msr(cpu_env, addr, tmp); + tcg_temp_free_i32(addr); + } + /* PRIMASK */ + if (a->I) { + addr = tcg_const_i32(16); + gen_helper_v7m_msr(cpu_env, addr, tmp); + tcg_temp_free_i32(addr); + } + tcg_temp_free_i32(tmp); + gen_lookup_tb(s); + return true; +} + /* * Clear-Exclusive, Barriers */ @@ -10908,51 +10943,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) break; } - case 6: - switch ((insn >> 5) & 7) { - case 2: - /* setend */ - ARCH(6); - if (((insn >> 3) & 1) != !!(s->be_data == MO_BE)) { - gen_helper_setend(cpu_env); - s->base.is_jmp = DISAS_UPDATE; - } - break; - case 3: - /* cps */ - ARCH(6); - if (IS_USER(s)) { - break; - } - if (arm_dc_feature(s, ARM_FEATURE_M)) { - tmp = tcg_const_i32((insn & (1 << 4)) != 0); - /* FAULTMASK */ - if (insn & 1) { - addr = tcg_const_i32(19); - gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); - } - /* PRIMASK */ - if (insn & 2) { - addr = tcg_const_i32(16); - gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); - } - tcg_temp_free_i32(tmp); - gen_lookup_tb(s); - } else { - if (insn & (1 << 4)) { - shift = CPSR_A | CPSR_I | CPSR_F; - } else { - shift = 0; - } - gen_set_psr_im(s, ((insn & 7) << 6), 0, shift); - } - break; - default: - goto undef; - } - break; + case 6: /* setend, cps; in decodetree */ + goto illegal_op; default: goto undef; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index b5b5086e8a..032902a1f4 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -29,6 +29,8 @@ &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list +&setend !extern E +&cps !extern mode imod M A I F # Set S if the instruction is outside of an IT block. %s !function=t16_setflags @@ -183,3 +185,13 @@ SXTAH 1011 0010 00 ... ... @extend SXTAB 1011 0010 01 ... ... @extend UXTAH 1011 0010 10 ... ... @extend UXTAB 1011 0010 11 ... ... @extend + +# Change processor state + +%imod 4:1 !function=plus_2 + +SETEND 1011 0110 010 1 E:1 000 &setend +{ + CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=0 M=0 %imod + CPS_v7m 1011 0110 011 im:1 00 I:1 F:1 +} From patchwork Wed Sep 4 19:30:48 2019 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::62d Subject: [Qemu-devel] [PATCH v4 58/69] target/arm: Convert T16, Reverse bytes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 18 +++--------------- target/arm/t16.decode | 9 +++++++++ 2 files changed, 12 insertions(+), 15 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index ce394ddb00..b70491d39e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10730,7 +10730,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rn, rd, shift, cond; + uint32_t val, op, rm, rd, shift, cond; int32_t offset; int i; TCGv_i32 tmp; @@ -10927,20 +10927,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) break; } - /* Otherwise this is rev */ - ARCH(6); - rn = (insn >> 3) & 0x7; - rd = insn & 0x7; - tmp = load_reg(s, rn); - switch (op1) { - case 0: tcg_gen_bswap32_i32(tmp, tmp); break; - case 1: gen_rev16(tmp, tmp); break; - case 3: gen_revsh(tmp, tmp); break; - default: - g_assert_not_reached(); - } - store_reg(s, rd, tmp); - break; + /* Otherwise this is rev, in decodetree */ + goto illegal_op; } case 6: /* setend, cps; in decodetree */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 032902a1f4..19a442b894 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrr_rot !extern rd rn rm rot +&rr !extern rd rm &ri !extern rd imm &r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype @@ -195,3 +196,11 @@ SETEND 1011 0110 010 1 E:1 000 &setend CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=0 M=0 %imod CPS_v7m 1011 0110 011 im:1 00 I:1 F:1 } + +# Reverse bytes + +@rdm .... .... .. rm:3 rd:3 &rr + +REV 1011 1010 00 ... ... @rdm +REV16 1011 1010 01 ... ... @rdm +REVSH 1011 1010 11 ... ... @rdm From patchwork Wed Sep 4 19:30:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173005 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp389683ilq; Wed, 4 Sep 2019 13:12:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqxjLv7IGw9zD93qHC4Tb+LANGJ6e1D5eqd6oiYxqFsh8pQeeJgpm8QjLYq6vLJDoKxAsnvb X-Received: by 2002:a05:620a:1f8:: with SMTP id x24mr1661381qkn.413.1567627977293; Wed, 04 Sep 2019 13:12:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567627977; cv=none; d=google.com; s=arc-20160816; b=oUD1xoACbdc/rPReWHBvImrv20mJ5Jfx67WpWZu0zwm4JGF/Cnv2Fa7QsSIlkUoM+T MRCjQFx6UOsi1YQfuQfpT2XtHJ3UcGLEnUVpsCHeVCuFpmgNBd0P/LalIUMyUlc393d8 /lwH+DwcvCVJV8JnWtYgM3P/K17mJMZI5c4rVT1Aq/T63Ou5GuhVHfwY8pKcLFWD5oY7 5fOGNHLEsZFLgqNyX9IJBH6Xacel1+ax/ChCmsJ9/Akk1NMhP5SjZdE8j26jsBKIKQJL AB1R7MgdqGPDix5BzzV3mc3JRniIF1G94IN+rQKXUjnnEZg3mgpiq2ASGlaTeWDHu7+n nqpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=NK+hQjn74sTmmQoYkWqtZ1EbyzqY+R+jJ+p0UyW4OS0=; b=0kaG3niXMXNiJWEdjKLH52bi4DAfbXVvxPlrCyDfDiEukiupMPndh0L3wrUAqszRQE x5DUcqQPIWd73KO11Q6+RELMJ2gu8QblYLSSXzk69kjKwrEQu9xA+lMf5E6EGUS5C5eY fsnh3Wie+Vav8raQlC/eIoeZ0OEToxl3MuAqfzJr+SsXc4bu1S/Lgcy+GYsxHfFNKnzi Jg+H8BpVbwKPNxIkllXiyXGOVCNksUdU0M7l5iafn8mEYFaY0habWNJ042P7u/wY8rzP xKgl41Z3UV04OWB84uekgZN4dk5wOnYNLEn4Xp018vwVh35ZH5lP97F5XnE9Umjn500u kelw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fIYOgT14; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 59/69] target/arm: Convert T16, nop hints X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 3 +-- target/arm/t16.decode | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/translate.c b/target/arm/translate.c index b70491d39e..69092c12c3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10891,8 +10891,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) case 15: /* IT, nop-hint. */ if ((insn & 0xf) == 0) { - gen_nop_hint(s, (insn >> 4) & 0xf); - break; + goto illegal_op; /* nop hint, in decodetree */ } /* * IT (If-Then) diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 19a442b894..5829b9a58c 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -19,6 +19,7 @@ # This file is processed by scripts/decodetree.py # +&empty !extern &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot @@ -204,3 +205,19 @@ SETEND 1011 0110 010 1 E:1 000 &setend REV 1011 1010 00 ... ... @rdm REV16 1011 1010 01 ... ... @rdm REVSH 1011 1010 11 ... ... @rdm + +# Hints + +{ + YIELD 1011 1111 0001 0000 + WFE 1011 1111 0010 0000 + WFI 1011 1111 0011 0000 + + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1011 1111 0100 0000 + # SEVL 1011 1111 0101 0000 + + # The canonical nop has the second nibble as 0000, but the whole of the + # rest of the space is a reserved hint, behaves as nop. + NOP 1011 1111 ---- 0000 +} From patchwork Wed Sep 4 19:30:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173012 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp396833ilq; Wed, 4 Sep 2019 13:20:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqzCcC4KwuQP5Sy9llvM1ZSXghfVsYJMpbTTkyFTaMV8zJSmm6vbvUGrd+rVtFnN4NcxUizJ X-Received: by 2002:a17:906:2619:: with SMTP id h25mr9159680ejc.283.1567628415998; Wed, 04 Sep 2019 13:20:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567628415; cv=none; d=google.com; s=arc-20160816; b=E3exvDjLcAixoyH0t41cCPgRRjN+nqHlTmaFcDfk5i+zABY59RCc7h9hs25k6B7Ay/ /30zO01z4AoIV16jCzKVrGsnLvhwqZGbOy8iLLWTHz3/iS6CMjp231b6MdZjEzygrTap aqqBoxBEcdaWZDgSg9ftCfB6qJMIcJ7Ce5895Yq9RokA6JLOyOUk1N06TTN0lyqmOK82 eXD5MF0H4plMQlRDool181Du211lgiknpABN4F43CV2sBKOvLksjj4NfAXj3ENSWXe4a T53GBezmhxMqy/vyy+DsZ8VoTBFwAV5uq6XUZEO1UIdf2jHsk28339GnIJuUtJifNwGA nXTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=QO3IBs61SUEB1dyssLo6yzRJXGICvl8lJuuHe5SABa4=; b=xXJUImDyEbmq1khDk6C7GQfOe0vOrpWCuFt5J4ZUodcgLFUJDchDMW37L9/AKFqtFY vekZfml1wrwnlfEC47/3a+VbMZpxC3YY+k5XqNVNnEzvpX1mmYxZc7hAxSC1JAbU3veP 0MYTuznCtPKoIXQqy4edjIU2hXhXG37jrzC/PSY8JFLqS6x2tYTythnEmUWZtBUElbGA ew243gvnR8ZRvJEaNjJspnM9ae8ds/1x1KiSewlaU66qv6PpX+qx6jcFP3XloVhJnaVs mUbjdYn05Wa0Jfga+dhHABOOM6NrE1ndx5TNHlosovjdaibW4p/cgpwuBADx9x05LteQ /Kbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nKLxRsbD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:50 -0700 Message-Id: <20190904193059.26202-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v4 60/69] target/arm: Split gen_nop_hint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that all callers pass a constant value, split the switch statement into the individual trans_* functions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 67 +++++++++++++++--------------------------- 1 file changed, 24 insertions(+), 43 deletions(-) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/translate.c b/target/arm/translate.c index 69092c12c3..d076c962ea 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3061,46 +3061,6 @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc) gen_rfe(s, pc, load_cpu_field(spsr)); } -/* - * For WFI we will halt the vCPU until an IRQ. For WFE and YIELD we - * only call the helper when running single threaded TCG code to ensure - * the next round-robin scheduled vCPU gets a crack. In MTTCG mode we - * just skip this instruction. Currently the SEV/SEVL instructions - * which are *one* of many ways to wake the CPU from WFE are not - * implemented so we can't sleep like WFI does. - */ -static void gen_nop_hint(DisasContext *s, int val) -{ - switch (val) { - /* When running in MTTCG we don't generate jumps to the yield and - * WFE helpers as it won't affect the scheduling of other vCPUs. - * If we wanted to more completely model WFE/SEV so we don't busy - * spin unnecessarily we would need to do something more involved. - */ - case 1: /* yield */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_set_pc_im(s, s->base.pc_next); - s->base.is_jmp = DISAS_YIELD; - } - break; - case 3: /* wfi */ - gen_set_pc_im(s, s->base.pc_next); - s->base.is_jmp = DISAS_WFI; - break; - case 2: /* wfe */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_set_pc_im(s, s->base.pc_next); - s->base.is_jmp = DISAS_WFE; - } - break; - case 4: /* sev */ - case 5: /* sevl */ - /* TODO: Implement SEV, SEVL and WFE. May help SMP performance. */ - default: /* nop */ - break; - } -} - #define CPU_V001 cpu_V0, cpu_V0, cpu_V1 static inline void gen_neon_add(int size, TCGv_i32 t0, TCGv_i32 t1) @@ -8194,19 +8154,40 @@ DO_SMLAWX(SMLAWT, 1, 1) static bool trans_YIELD(DisasContext *s, arg_YIELD *a) { - gen_nop_hint(s, 1); + /* + * When running single-threaded TCG code, use the helper to ensure that + * the next round-robin scheduled vCPU gets a crack. When running in + * MTTCG we don't generate jumps to the helper as it won't affect the + * scheduling of other vCPUs. + */ + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_set_pc_im(s, s->base.pc_next); + s->base.is_jmp = DISAS_YIELD; + } return true; } static bool trans_WFE(DisasContext *s, arg_WFE *a) { - gen_nop_hint(s, 2); + /* + * When running single-threaded TCG code, use the helper to ensure that + * the next round-robin scheduled vCPU gets a crack. In MTTCG mode we + * just skip this instruction. Currently the SEV/SEVL instructions, + * which are *one* of many ways to wake the CPU from WFE, are not + * implemented so we can't sleep like WFI does. + */ + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_set_pc_im(s, s->base.pc_next); + s->base.is_jmp = DISAS_WFE; + } return true; } static bool trans_WFI(DisasContext *s, arg_WFI *a) { - gen_nop_hint(s, 3); + /* For WFI, halt the vCPU until an IRQ. */ + gen_set_pc_im(s, s->base.pc_next); + s->base.is_jmp = DISAS_WFI; return true; } From patchwork Wed Sep 4 19:30:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173021 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp405166ilq; Wed, 4 Sep 2019 13:29:43 -0700 (PDT) X-Google-Smtp-Source: APXvYqwwR5HOvde8DClZPfRGvxEtBc+1cEheEcRsFuJUrJ24FPxO/lnuJCX4jiBwhIAdxVRGlC55 X-Received: by 2002:ae9:e842:: with SMTP id a63mr26972608qkg.447.1567628983022; Wed, 04 Sep 2019 13:29:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567628983; cv=none; d=google.com; s=arc-20160816; b=O+K8NxrgMDVwSdf5sZ3Ceo36veGi/x2Txw/tMLrboG4elIsR3oNHSM4dxLhlIfqG6h gBeoimK0BTIAuuYXYZePq8+3ctAVWQA0ZLDIeMOxIc5BgsNn42X3gbB5LSFih1/PK05J IIZ0Bk1jlj/NDwvyJ0WDecG8bm90FT2U33kMtg/0WEL3sTypE2hkRXBH/oT3SMcsOt3v a1FcfENbYNs4bbl8aBo+aH1oKqmJH/2LuBkmVXBcTS6Z9DfG/bsWxRJxqhppsMIbxsNI Tnyg7aaMdhCN+4BoGsH969nHJhUZ1TtuB9D0Gclm6rb6vWcJK53B+7XSwX0fwRStZrJ2 ZRgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=dXwskgwxwGoHO9g80cjucHpMD4vJQ5Oi2of0il2UAv8=; b=lkkiBwqz9PByL22WYpXbYrpSDOkFHT/wqN2nW4yflQyDkKmUupKj2XqQqRtHzEdGlb Q8dtqSe7kIhIcXU33TMNYb6M6oq23fmrQVg562kiikXvm7QsquLqBmPiNpCbpzF9Lbh3 ZRFu3rl6rK+pNUoU6Zvh1Y8MvB9wQ/5uj6m8/RNAV/wo3HVK2kUiwXXOKQQm0s+0YvlP NKQZDpAambt721TyzEkO2yWSRHvtwjfCMJKZ0df8iYjY2iJNMN5ENzEDBufXOldrHuE6 h2yQj8yQJflTH/0DOP3LD/Qx6tCne6SR2Ub12gEzTQDZ7y8tIR4TPQlotAFWRlceaBeD uNwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=awDsgTvB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::629 Subject: [Qemu-devel] [PATCH v4 61/69] target/arm: Convert T16, push and pop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 83 ++++++------------------------------------ target/arm/t16.decode | 10 +++++ 2 files changed, 22 insertions(+), 71 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index d076c962ea..ed52018c17 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7516,6 +7516,16 @@ static int t16_setflags(DisasContext *s) return s->condexec_mask == 0; } +static int t16_push_list(DisasContext *s, int x) +{ + return (x & 0xff) | (x & 0x100) << (14 - 8); +} + +static int t16_pop_list(DisasContext *s, int x) +{ + return (x & 0xff) | (x & 0x100) << (15 - 8); +} + /* * Include the generated decoders. */ @@ -10713,7 +10723,6 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) { uint32_t val, op, rm, rd, shift, cond; int32_t offset; - int i; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -10786,76 +10795,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) goto illegal_op; case 4: case 5: case 0xc: case 0xd: - /* - * 0b1011_x10x_xxxx_xxxx - * - push/pop - */ - addr = load_reg(s, 13); - if (insn & (1 << 8)) - offset = 4; - else - offset = 0; - for (i = 0; i < 8; i++) { - if (insn & (1 << i)) - offset += 4; - } - if ((insn & (1 << 11)) == 0) { - tcg_gen_addi_i32(addr, addr, -offset); - } - - if (s->v8m_stackcheck) { - /* - * Here 'addr' is the lower of "old SP" and "new SP"; - * if this is a pop that starts below the limit and ends - * above it, it is UNKNOWN whether the limit check triggers; - * we choose to trigger. - */ - gen_helper_v8m_stackcheck(cpu_env, addr); - } - - for (i = 0; i < 8; i++) { - if (insn & (1 << i)) { - if (insn & (1 << 11)) { - /* pop */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, i, tmp); - } else { - /* push */ - tmp = load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - /* advance to the next address. */ - tcg_gen_addi_i32(addr, addr, 4); - } - } - tmp = NULL; - if (insn & (1 << 8)) { - if (insn & (1 << 11)) { - /* pop pc */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - /* don't set the pc until the rest of the instruction - has completed */ - } else { - /* push lr */ - tmp = load_reg(s, 14); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_gen_addi_i32(addr, addr, 4); - } - if ((insn & (1 << 11)) == 0) { - tcg_gen_addi_i32(addr, addr, -offset); - } - /* write back the new stack pointer */ - store_reg(s, 13, addr); - /* set the new PC value */ - if ((insn & 0x0900) == 0x0900) { - store_reg_from_load(s, 15, tmp); - } - break; + /* push/pop, in decodetree */ + goto illegal_op; case 1: case 3: case 9: case 11: /* czb */ rm = insn & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 5829b9a58c..55fadce223 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -221,3 +221,13 @@ REVSH 1011 1010 11 ... ... @rdm # rest of the space is a reserved hint, behaves as nop. NOP 1011 1111 ---- 0000 } + +# Push and Pop + +%push_list 0:9 !function=t16_push_list +%pop_list 0:9 !function=t16_pop_list + +STM 1011 010 ......... \ + &ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list +LDM_t16 1011 110 ......... \ + &ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list From patchwork Wed Sep 4 19:30:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173024 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp410728ilq; Wed, 4 Sep 2019 13:35:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqzeV/6yU6rEejnqthR3qGVgGoFwqZwG31hE2+521CreBJKZtmWyJnNTOv3+R5Yc7YB15oK4 X-Received: by 2002:ac8:44c7:: with SMTP id b7mr25400366qto.170.1567629306661; Wed, 04 Sep 2019 13:35:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567629306; cv=none; d=google.com; s=arc-20160816; b=GhQBDSfTggW9HFzLTrDKleEGZyeUxMum35Z73fKANoh1l4QjTTDAyylR2AnFkWiu8p d4ZyIBJiammFfsxYkKf2m2NrMjEATQPQ6+miAG5JlMbUrxD1bsSyvtiWmCXqc0O+u/aK UwgCxLiLi4pY7oZZpt65QsEA1SaD2pczApezz5XHc7ZI1kjVJOP4gDFJee9q9aHmk4lE 8FV0j0I1/GLyJXVU/0/EthULik+mjw9VSh0cBtCU10bB3isnTaFihNUxNSktDldhaag+ EnxKrJv3yfPLhX91bdhcihkDXfgrGxSE6pcUF3FQLefCAwgToZP88xuZRvPLmlPdvEaM j/+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=852c/awIgTh3C7GCCijbpsvu4SQYTMvdpB+Gb73lAXI=; b=Ycb5WiexXwb42ZmIhHHWeAQgK6K0QYQPjYhQriM2WY8E6/mGQzTUKAtc31rOo71tw9 z2dRQ7o/g7HMv1jAuENFjDn73Qcj/TCzu2WgOns5WBlTtXM0LyW0fRhSc1/QJR6My2dm 6nnj+nXVN5YthnsN032Mfe8Fizr8EnaXJsE2McYHYhu11m6EStCTTrFs7xv7kRKZqGyx DKYHitTQTjpe/xAI29ZOFddzIKCGikAdDo/P989Eh+/+y0Ds0uZfA/c6F+ePh55ORd2Q fh79KA1kybw0q+1m7MQe/QzSE6ZybCw4bm8QXSCCrQnJGVVGrYUogDo+RdNuXeO5fqJE evyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PleWZl9q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:52 -0700 Message-Id: <20190904193059.26202-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v4 62/69] target/arm: Convert T16, Conditional branches, Supervisor call X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 +++----------------------- target/arm/t16.decode | 12 ++++++++++++ 2 files changed, 15 insertions(+), 23 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index ed52018c17..a4844992d5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10721,7 +10721,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rd, shift, cond; + uint32_t val, op, rm, rd, shift; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10860,28 +10860,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) } break; - case 13: - /* conditional branch or swi */ - cond = (insn >> 8) & 0xf; - if (cond == 0xe) - goto undef; - - if (cond == 0xf) { - /* swi */ - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm = extract32(insn, 0, 8); - s->base.is_jmp = DISAS_SWI; - break; - } - /* generate a conditional jump to next instruction */ - arm_skip_unless(s, cond); - - /* jump to the offset */ - val = read_pc(s); - offset = ((int32_t)insn << 24) >> 24; - val += offset << 1; - gen_jmp(s, val); - break; + case 13: /* conditional branch or swi, in decodetree */ + goto illegal_op; case 14: if (insn & (1 << 11)) { diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 55fadce223..cbc64f4e48 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -28,11 +28,13 @@ &rr !extern rd rm &ri !extern rd imm &r !extern rm +&i !extern imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list &setend !extern E &cps !extern mode imod M A I F +&ci !extern cond imm # Set S if the instruction is outside of an IT block. %s !function=t16_setflags @@ -231,3 +233,13 @@ STM 1011 010 ......... \ &ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list LDM_t16 1011 110 ......... \ &ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list + +# Conditional branches, Supervisor call + +%imm8_0x2 0:s8 !function=times_2 + +{ + UDF 1101 1110 ---- ---- + SVC 1101 1111 imm:8 &i + B_cond_thumb 1101 cond:4 ........ &ci imm=%imm8_0x2 +} From patchwork Wed Sep 4 19:30:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173016 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp400539ilq; Wed, 4 Sep 2019 13:24:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqyMrg9X1Sjyszs0oN6YK+yb+kGTuvOMW1LKu+lO6OpSTr3bHdpl0zbCs9Kl4m6g/VjVZUG2 X-Received: by 2002:a50:a6c8:: with SMTP id f8mr164522edc.60.1567628676666; Wed, 04 Sep 2019 13:24:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567628676; cv=none; d=google.com; s=arc-20160816; b=ye9F1xP8wGPtWHgHrabsQrSF+P8CHzi/y2j1JUT9kwBHZZC4RuwdrDSORzSJI9/kpf ObkXcqDpyWZE/2zcSfD1Njpw8DgHd+QpCyK5cxYIC014HH0157LJXC+dL/KwIBA1nRR+ JoarfA+bbGmZ7IxX72kfbqFPT9yUKLu44DNb6DGAJBAnXvw+NC53KINGi4mFaChNXEe3 ihltjKVzDNb3vygtjb9kwSiA5WNCGNswtEdJ14pJYJMVP96S6qy3fjB/oOC+kdVy1XB1 f928nDiKuvXVcGYK/mHPXfAVa9cTM0CddwM++8fKma+BLIVtTYrxBTwW849ae3sM4lTY X7JA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=U5HqQQCoMgATbAeqUvsvbzJcESqlSaZ4tMjdZ5JSZUU=; b=iXG2lSc1auCnP+IWbKIEPdk7Zr4sb/8aDfereM/j5pEtZ63wcW9h3wOBVz7t7ALoWY Rf5x2Wbam0AkwhhFToto7p+pp5bP0Pa+dhlamyYJMlH5Jxki0I6HMa/XBYtfPbQaB3XI AE4AK/G4R/ZfcNpBom7ji+H0J8tBWEpHIYA9cA+7zBHbPE4dfwGuCklZKMrc+2vF+vDV IaIH/CGpCsOQApIVicsaLdifA9BqLG3gVEpFnDwliVV+D+fG2bUEyLY0koAOVt/pMb6/ giGs0tjsavbooOb0Ig5sms11zRWaQwGqz05zaGp8RZLSrYBVnX+b+J7ckB/lioPfqc7X HYUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rg66FiXw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:53 -0700 Message-Id: <20190904193059.26202-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::536 Subject: [Qemu-devel] [PATCH v4 63/69] target/arm: Convert T16, Miscellaneous 16-bit instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Split firstcond & mask within trans_IT. --- target/arm/translate.c | 111 +++++++++++++---------------------------- target/arm/t16.decode | 29 +++++++---- 2 files changed, 54 insertions(+), 86 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index a4844992d5..48ed6f6b5d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10196,6 +10196,18 @@ static bool trans_TBH(DisasContext *s, arg_tbranch *a) return op_tbranch(s, a, true); } +static bool trans_CBZ(DisasContext *s, arg_CBZ *a) +{ + TCGv_i32 tmp = load_reg(s, a->rn); + + arm_gen_condlabel(s); + tcg_gen_brcondi_i32(a->nz ? TCG_COND_EQ : TCG_COND_NE, + tmp, 0, s->condlabel); + tcg_temp_free_i32(tmp); + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + /* * Supervisor call */ @@ -10417,6 +10429,27 @@ static bool trans_PLI(DisasContext *s, arg_PLD *a) return ENABLE_ARCH_7; } +/* + * If-then + */ + +static bool trans_IT(DisasContext *s, arg_IT *a) +{ + int cond_mask = a->cond_mask; + + /* + * No actual code generated for this insn, just setup state. + * + * Combinations of firstcond and mask which set up an 0b1111 + * condition are UNPREDICTABLE; we take the CONSTRAINED + * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110, + * i.e. both meaning "execute always". + */ + s->condexec_cond = (cond_mask >> 4) & 0xe; + s->condexec_mask = cond_mask & 0x1f; + return true; +} + /* * Legacy decoder. */ @@ -10783,83 +10816,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ case 10: /* add PC/SP (immediate), in decodetree */ + case 11: /* misc, in decodetree */ case 12: /* load/store multiple, in decodetree */ - goto illegal_op; - - case 11: - /* misc */ - op = (insn >> 8) & 0xf; - switch (op) { - case 0: /* add/sub (sp, immediate), in decodetree */ - case 2: /* sign/zero extend, in decodetree */ - goto illegal_op; - - case 4: case 5: case 0xc: case 0xd: - /* push/pop, in decodetree */ - goto illegal_op; - - case 1: case 3: case 9: case 11: /* czb */ - rm = insn & 7; - tmp = load_reg(s, rm); - arm_gen_condlabel(s); - if (insn & (1 << 11)) - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel); - else - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel); - tcg_temp_free_i32(tmp); - offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3; - gen_jmp(s, read_pc(s) + offset); - break; - - case 15: /* IT, nop-hint. */ - if ((insn & 0xf) == 0) { - goto illegal_op; /* nop hint, in decodetree */ - } - /* - * IT (If-Then) - * - * Combinations of firstcond and mask which set up an 0b1111 - * condition are UNPREDICTABLE; we take the CONSTRAINED - * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110, - * i.e. both meaning "execute always". - */ - s->condexec_cond = (insn >> 4) & 0xe; - s->condexec_mask = insn & 0x1f; - /* No actual code generated for this insn, just setup state. */ - break; - - case 0xe: /* bkpt */ - { - int imm8 = extract32(insn, 0, 8); - ARCH(5); - gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true)); - break; - } - - case 0xa: /* rev, and hlt */ - { - int op1 = extract32(insn, 6, 2); - - if (op1 == 2) { - /* HLT */ - int imm6 = extract32(insn, 0, 6); - - gen_hlt(s, imm6); - break; - } - - /* Otherwise this is rev, in decodetree */ - goto illegal_op; - } - - case 6: /* setend, cps; in decodetree */ - goto illegal_op; - - default: - goto undef; - } - break; - case 13: /* conditional branch or swi, in decodetree */ goto illegal_op; @@ -10915,7 +10873,6 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) } return; illegal_op: -undef: unallocated_encoding(s); } diff --git a/target/arm/t16.decode b/target/arm/t16.decode index cbc64f4e48..f128110dee 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -211,19 +211,30 @@ REVSH 1011 1010 11 ... ... @rdm # Hints { - YIELD 1011 1111 0001 0000 - WFE 1011 1111 0010 0000 - WFI 1011 1111 0011 0000 + { + YIELD 1011 1111 0001 0000 + WFE 1011 1111 0010 0000 + WFI 1011 1111 0011 0000 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1011 1111 0100 0000 - # SEVL 1011 1111 0101 0000 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1011 1111 0100 0000 + # SEVL 1011 1111 0101 0000 - # The canonical nop has the second nibble as 0000, but the whole of the - # rest of the space is a reserved hint, behaves as nop. - NOP 1011 1111 ---- 0000 + # The canonical nop has the second nibble as 0000, but the whole of the + # rest of the space is a reserved hint, behaves as nop. + NOP 1011 1111 ---- 0000 + } + IT 1011 1111 cond_mask:8 } +# Miscellaneous 16-bit instructions + +%imm6_9_3 9:1 3:5 !function=times_2 + +HLT 1011 1010 10 imm:6 &i +BKPT 1011 1110 imm:8 &i +CBZ 1011 nz:1 0.1 ..... rn:3 imm=%imm6_9_3 + # Push and Pop %push_list 0:9 !function=t16_push_list From patchwork Wed Sep 4 19:30:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173018 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp402254ilq; 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 64/69] target/arm: Convert T16, shift immediate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 ++------------------------ target/arm/t16.decode | 8 ++++++++ 2 files changed, 10 insertions(+), 24 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 48ed6f6b5d..d409afd55f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10754,7 +10754,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rd, shift; + uint32_t val, rd; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10766,29 +10766,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) /* fall back to legacy decoder */ switch (insn >> 12) { - case 0: case 1: - - rd = insn & 7; - op = (insn >> 11) & 3; - if (op == 3) { - /* - * 0b0001_1xxx_xxxx_xxxx - * - Add, subtract (three low registers) - * - Add, subtract (two low registers and immediate) - * In decodetree. - */ - goto illegal_op; - } else { - /* shift immediate */ - rm = (insn >> 3) & 7; - shift = (insn >> 6) & 0x1f; - tmp = load_reg(s, rm); - gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0); - if (!s->condexec_mask) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - } - break; + case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */ case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ goto illegal_op; case 4: diff --git a/target/arm/t16.decode b/target/arm/t16.decode index f128110dee..79a1d66d6c 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -126,6 +126,14 @@ ADD_rri 10101 rd:3 ........ \ STM 11000 ... ........ @ldstm LDM_t16 11001 ... ........ @ldstm +# Shift (immediate) + +@shift_i ..... shim:5 rm:3 rd:3 &s_rrr_shi %s rn=%reg_0 + +MOV_rxri 000 00 ..... ... ... @shift_i shty=0 # LSL +MOV_rxri 000 01 ..... ... ... @shift_i shty=1 # LSR +MOV_rxri 000 10 ..... ... ... @shift_i shty=2 # ASR + # Add/subtract (three low registers) @addsub_3 ....... rm:3 rn:3 rd:3 \ From patchwork Wed Sep 4 19:30:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173038 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp425484ilq; Wed, 4 Sep 2019 13:52:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqzZbh1d6a3T2RTTwxUC6uJkEHKCQ280gew4Q2RKEdf235oJLx7yt0TJrUAiWnSR6alSzBWw X-Received: by 2002:aa7:c6ca:: with SMTP id b10mr201259eds.233.1567630329897; Wed, 04 Sep 2019 13:52:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567630329; cv=none; d=google.com; s=arc-20160816; b=spAnDp0CcdQAayWEXRoJTuCu7IZ5G6jdSVqp95Z/EsqDJuJzCUXRrU3ct6lLcThMzA mMSj2M1AblagMEZEo1/8cCFIwO6zSGk42IOaDAviWaR6lE6YOxF9jdgoisL9WmBkXONj tdhxEeUcMB/WuPaxZ6fbUcK6N8mvGX8PuqW7AxjYZXHVXmfKMz4F+eno9y1sI2dQqReJ h/WM5Ly0rRVp7MxEJIoKEU86R+cD8nfn+DdsR7HlhYBmoZld6uKMVL6VMhIUK3uounq5 2m76Mn6WYZBe9iKP6J4ylIpZ+EY51d6Bv7XukxBF5px6plmpx+A+dAX2+c2GnoLt25IB a65g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=VYZV/zdp2JerFG4ZPo6G3uzAjb1Br+I2f89wbKWVC8A=; b=L1n/JNu2LvjZ9xB3NJgCGxLNTdJaDTOhDcA+KmrapBMMyGLu5DVz/O01nqlUKLxHik j8xfQ9R4znu0ObexdOowBM/eTTbLT7rcEjpn3mGbxaGuPFVYOJDaGq37dCTnQuieVddp Am/JDYlmFA6zxyb6gDj6oGHO+cQLAOgD8jdqBYEXPR1NI7P4Yt5NHe1Y654oT1lD9wGq JnJSByiYecqQXy1yya4UEEMo86m58Si1IX31BzMvIGk8aVGsw/NhgvSPv7jOLJE8Ftpo maSpqC42RxhuQqmW8m91fXJdLQ64Y5WgaUOor1A0d8x8sLwU2cTYiuzYenLCLU92NAOH s6iA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="V/9uNM7q"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:55 -0700 Message-Id: <20190904193059.26202-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 65/69] target/arm: Convert T16, load (literal) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 42 ++---------------------------------------- target/arm/t16.decode | 4 ++++ 2 files changed, 6 insertions(+), 40 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index d409afd55f..4f4c77fc89 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -982,14 +982,6 @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ TCGv_i32 a32, int index) \ { \ gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \ -} \ -static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s, \ - TCGv_i32 val, \ - TCGv_i32 a32, int index, \ - ISSInfo issinfo) \ -{ \ - gen_aa32_ld##SUFF(s, val, a32, index); \ - disas_set_da_iss(s, OPC, issinfo); \ } #define DO_GEN_ST(SUFF, OPC) \ @@ -997,14 +989,6 @@ static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ TCGv_i32 a32, int index) \ { \ gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \ -} \ -static inline void gen_aa32_st##SUFF##_iss(DisasContext *s, \ - TCGv_i32 val, \ - TCGv_i32 a32, int index, \ - ISSInfo issinfo) \ -{ \ - gen_aa32_st##SUFF(s, val, a32, index); \ - disas_set_da_iss(s, OPC, issinfo | ISSIsWrite); \ } static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val) @@ -1053,9 +1037,7 @@ static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data); } -DO_GEN_LD(8s, MO_SB) DO_GEN_LD(8u, MO_UB) -DO_GEN_LD(16s, MO_SW) DO_GEN_LD(16u, MO_UW) DO_GEN_LD(32u, MO_UL) DO_GEN_ST(8, MO_UB) @@ -10754,11 +10736,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, rd; + uint32_t val; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; - TCGv_i32 addr; if (disas_t16(s, insn)) { return; @@ -10768,26 +10749,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) switch (insn >> 12) { case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */ case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ - goto illegal_op; - case 4: - if (insn & (1 << 11)) { - rd = (insn >> 8) & 7; - /* load pc-relative. Bit 1 of PC is ignored. */ - addr = add_reg_for_lit(s, 15, (insn & 0xff) * 4); - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), - rd | ISSIs16Bit); - tcg_temp_free_i32(addr); - store_reg(s, rd, tmp); - break; - } - - /* - * - Data-processing (two low registers), in decodetree - * - data processing extended, branch and exchange, in decodetree - */ - goto illegal_op; - + case 4: /* ldr lit, data proc (2reg), data proc ext, bx; in decodetree */ case 5: /* load/store register offset, in decodetree */ case 6: /* load/store word immediate offset, in decodetree */ case 7: /* load/store byte immediate offset, in decodetree */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 79a1d66d6c..0b4da411e0 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -113,6 +113,10 @@ LDRH_ri 10001 ..... ... ... @ldst_ri_2 STR_ri 10010 ... ........ @ldst_spec_i rn=13 LDR_ri 10011 ... ........ @ldst_spec_i rn=13 +# Load (PC-relative) + +LDR_ri 01001 ... ........ @ldst_spec_i rn=15 + # Add PC/SP (immediate) ADR 10100 rd:3 ........ imm=%imm8_0x4 From patchwork Wed Sep 4 19:30:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173026 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp412704ilq; Wed, 4 Sep 2019 13:37:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqzXALmg3iviSZ/t/YgR+Px6OCvK0Xn38g53XGf9FbrRfy+vW+g4I0pCJbkaMjnMtUN+vZqy X-Received: by 2002:a05:6402:160d:: with SMTP id f13mr144663edv.227.1567629428567; Wed, 04 Sep 2019 13:37:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567629428; cv=none; d=google.com; s=arc-20160816; b=SRYcw7y9sFcjlmIV7zuLJIhMI+SjXNEBhcdy8wvEOEyipw2nqZkUXR+EC/ln9ZEmP/ m78MLuzad0/wST2Y6ExSNnkUHzyJt2N67Iou+CQeUksbraa6E+UmHc50DJG7IcSa7XcF thAeb6znXk+ZswMWysWSVhFy8fBjWbD16EG0xzhgXU/rOVG5Mh8ojeI7KXSvjRed7vH3 DjkJ2NVANtRmcf0+CWgCVGOR8MiIJQbUzQTvw+wZpS+1Q9TVYD05ACpvXlc+avcpFCtM cyF6xubE7CWXM7Ai7XMjPGN6V/nclixkGQNZtcX7v5yUPv+6ip0uJ/wfdw0e3C30sgI2 rLgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ubjb98obYB0wcr0PkhZrvGjTKBKP700KuYx4LrhjRCk=; b=Jg7A7ia/BAEMtesrjKNCWrmWGuVNNysF1HHok4rAwP9zefftMFb+W/0+5W9dfUrZmG V7nY3/YkoocLl0DLxQ7OxFF/3OGItcoRwiYi5TLNQBxYFjdwUfMIk3vOxM+KYKbsC9tA Jjzu8jd8hiN2nFG1ZQYzNpAdrv5yXKg+zK46y7FNCDPCeeO+PcTRu/REzhjDKhmeAes6 3vyH6Xdx/QQcL+WWI3QvEUKjLC19GOAqGc5eArqHScmXruNcjDnQwBNRJCAPIyLy/MVG Fi5NlMzSlwQ0JzBBd2HW0+xteRN5A9GqjqL7dRc8pFdLfvdTgq9a8OBO/Ye+OplW9DYC EdJg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fnGC5dr5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:56 -0700 Message-Id: <20190904193059.26202-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::435 Subject: [Qemu-devel] [PATCH v4 66/69] target/arm: Convert T16, Unconditional branch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 9 ++------- target/arm/t16.decode | 6 ++++++ 2 files changed, 8 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 4f4c77fc89..3238ccbf1e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10736,7 +10736,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10780,12 +10779,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) gen_bx(s, tmp); break; } - /* unconditional branch */ - val = read_pc(s); - offset = ((int32_t)insn << 21) >> 21; - val += offset << 1; - gen_jmp(s, val); - break; + /* unconditional branch, in decodetree */ + goto illegal_op; case 15: /* thumb_insn_is_16bit() ensures we can't get here for diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 0b4da411e0..a4c89dba61 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -266,3 +266,9 @@ LDM_t16 1011 110 ......... \ SVC 1101 1111 imm:8 &i B_cond_thumb 1101 cond:4 ........ &ci imm=%imm8_0x2 } + +# Unconditional Branch + +%imm11_0x2 0:s11 !function=times_2 + +B 11100 ........... &i imm=%imm11_0x2 From patchwork Wed Sep 4 19:30:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173020 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp404923ilq; Wed, 4 Sep 2019 13:29:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqz/n3AodR0Escot2DIcEVpw2rI7/aajdebLWXHzqSdiVYTV4EkYtI/IHfNParTqIcM3xcGW X-Received: by 2002:a37:4a8d:: with SMTP id x135mr40381765qka.472.1567628967875; Wed, 04 Sep 2019 13:29:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567628967; cv=none; d=google.com; s=arc-20160816; b=PrBzaPw/NQbCD1GBfhlbXTgYuTE4App24/L7ynBCjIgI5rTCJ5mZA72694Hq9W6kAg HMCEI2FxklxrpeS7swaQ2DV0NAihHAL2emApk/YVXNCCI0uLhSDmORSPamYmvuiRtxUc pVYgCpxu5dKrVW9BWZkFKrCJV16FW6AKOOP8Eq8JevYZmHrUhGVa/MqLsbep/18bnmTh 4e3VKMYBVjKEDEW2S23IuT81Cnxl5c2M/Rjw3B7d8CLc8j1GA1DICjSCU6xXK3urjcCQ Xrc2LrhvWmPFWNf+IVsVrC1pXrPGsOVNiqx9n0kT15FBfUHnum4ung7zv9flRn1KSnzQ cg8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=HzFCgBINrkpo6Knja84cWCi2ubxaaPHPuYIHOK9s5JA=; b=ozba0dIHXoT2HMNmGP4pOVuQE/2nrAuc4O/WMIbdKu/SiAD5utmuFzTI41njJlzxnk DIlsXA0HN+AFK0cWgBcnQc2zcbldvP7OXjfz2RxwDU4VUOcCAFng32KNz7ahbYhNNYmz Iccel7UHGcxbtHJeAJuGX01QTxuGzHRdhepjF+b2qQtDKv77Wt3BxWcHXTuKkzXvmIdp O6ETHgWIFA9TolNEFNHkFlVJbordM4ZiffPxZ7knOSrnMsaswodIvJaGGVYpZjCsxu4c /cIaTHsn5ZvsCf77DeFh5OCyO0DdCj9iM7IvnwNsNXDCg/959VVWXLUu/0kcdNB1Pm7a 5iYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hUyxOfky; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:57 -0700 Message-Id: <20190904193059.26202-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42d Subject: [Qemu-devel] [PATCH v4 67/69] target/arm: Convert T16, long branches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 85 ++++++++++++++++++------------------------ target/arm/t16.decode | 7 ++++ 2 files changed, 43 insertions(+), 49 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 3238ccbf1e..a99a5c2eef 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10147,6 +10147,40 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) return true; } +static bool trans_BL_BLX_prefix(DisasContext *s, arg_BL_BLX_prefix *a) +{ + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); + tcg_gen_movi_i32(cpu_R[14], read_pc(s) + (a->imm << 12)); + return true; +} + +static bool trans_BL_suffix(DisasContext *s, arg_BL_suffix *a) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); + tcg_gen_addi_i32(tmp, cpu_R[14], (a->imm << 1) | 1); + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); + gen_bx(s, tmp); + return true; +} + +static bool trans_BLX_suffix(DisasContext *s, arg_BLX_suffix *a) +{ + TCGv_i32 tmp; + + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); + if (!ENABLE_ARCH_5) { + return false; + } + tmp = tcg_temp_new_i32(); + tcg_gen_addi_i32(tmp, cpu_R[14], a->imm << 1); + tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); + gen_bx(s, tmp); + return true; +} + static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) { TCGv_i32 addr, tmp; @@ -10736,10 +10770,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - int32_t offset; - TCGv_i32 tmp; - TCGv_i32 tmp2; - if (disas_t16(s, insn)) { return; } @@ -10758,53 +10788,10 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) case 11: /* misc, in decodetree */ case 12: /* load/store multiple, in decodetree */ case 13: /* conditional branch or swi, in decodetree */ - goto illegal_op; - case 14: - if (insn & (1 << 11)) { - /* thumb_insn_is_16bit() ensures we can't get here for - * a Thumb2 CPU, so this must be a thumb1 split BL/BLX: - * 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF) - */ - assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); - ARCH(5); - offset = ((insn & 0x7ff) << 1); - tmp = load_reg(s, 14); - tcg_gen_addi_i32(tmp, tmp, offset); - tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); - - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, s->base.pc_next | 1); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - break; - } - /* unconditional branch, in decodetree */ - goto illegal_op; - case 15: - /* thumb_insn_is_16bit() ensures we can't get here for - * a Thumb2 CPU, so this must be a thumb1 split BL/BLX. - */ - assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); - - if (insn & (1 << 11)) { - /* 0b1111_1xxx_xxxx_xxxx : BL suffix */ - offset = ((insn & 0x7ff) << 1) | 1; - tmp = load_reg(s, 14); - tcg_gen_addi_i32(tmp, tmp, offset); - - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, s->base.pc_next | 1); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - } else { - /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */ - uint32_t uoffset = ((int32_t)insn << 21) >> 9; - - tcg_gen_movi_i32(cpu_R[14], read_pc(s) + uoffset); - } - break; + /* branches, in decodetree */ + goto illegal_op; } return; illegal_op: diff --git a/target/arm/t16.decode b/target/arm/t16.decode index a4c89dba61..43b9a267a1 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -272,3 +272,10 @@ LDM_t16 1011 110 ......... \ %imm11_0x2 0:s11 !function=times_2 B 11100 ........... &i imm=%imm11_0x2 + +# thumb_insn_is_16bit() ensures we won't be decoding these as +# T16 instructions for a Thumb2 CPU, so these patterns must be +# a Thumb1 split BL/BLX. +BLX_suffix 11101 imm:11 &i +BL_BLX_prefix 11110 imm:s11 &i +BL_suffix 11111 imm:11 &i From patchwork Wed Sep 4 19:30:58 2019 Content-Type: text/plain; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:58 -0700 Message-Id: <20190904193059.26202-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v4 68/69] target/arm: Clean up disas_thumb_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that everything is converted, remove the rest of the legacy decode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 27 ++------------------------- 1 file changed, 2 insertions(+), 25 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index a99a5c2eef..2412dde631 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10770,32 +10770,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - if (disas_t16(s, insn)) { - return; + if (!disas_t16(s, insn)) { + unallocated_encoding(s); } - /* fall back to legacy decoder */ - - switch (insn >> 12) { - case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */ - case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ - case 4: /* ldr lit, data proc (2reg), data proc ext, bx; in decodetree */ - case 5: /* load/store register offset, in decodetree */ - case 6: /* load/store word immediate offset, in decodetree */ - case 7: /* load/store byte immediate offset, in decodetree */ - case 8: /* load/store halfword immediate offset, in decodetree */ - case 9: /* load/store from stack, in decodetree */ - case 10: /* add PC/SP (immediate), in decodetree */ - case 11: /* misc, in decodetree */ - case 12: /* load/store multiple, in decodetree */ - case 13: /* conditional branch or swi, in decodetree */ - case 14: - case 15: - /* branches, in decodetree */ - goto illegal_op; - } - return; -illegal_op: - unallocated_encoding(s); } static bool insn_crosses_page(CPUARMState *env, DisasContext *s) From patchwork Wed Sep 4 19:30:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 173022 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp405332ilq; Wed, 4 Sep 2019 13:29:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqwVvSXBHyPk9rskqUB13LBo7oocDOjOFzKLGcjK5zvvgMi71H4DhDhA8XttCl62wg3nof/6 X-Received: by 2002:a17:906:a40b:: with SMTP id l11mr30166952ejz.307.1567628993043; Wed, 04 Sep 2019 13:29:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567628993; cv=none; d=google.com; s=arc-20160816; b=GWN4LHw2p5C4RgHp9OuA/ryCwIb/6zDu4UuzWPfA9QadryxYO9gXPo6XVYXetCMgnT Jj44iQZXH3rcVEljG76gunJyzf75O56jFzO/CnBWxdRgV9mHdK2oItgPgfpsDgc881L0 JYJNXLN6aBe7QJhDv2tUzaaoM+88q3nM0dSFgdvDTc+Bsk8guuTWqQdzGOHtKSsFfDMK TnkGrE/GlsK/x7DNWoWQsiYtUuWXQhblPj5p1/GcYHXxzIwU/EblBI64CthHE4D/h39t vJ0QOtiec3lgnj0lWYv+77SSe9d5wQ7y6u4PaYO2Zl07YEwlYF1Q7bgbu00L8D/VO53q 4BoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=/PXkXzASKMcUQDbV6Hl9B5xocqfOCXTaxlqtgyWXLXY=; b=htIunpg/qC+E1YUxDGnVKbQ3aljRxnpdTiZbE/hfuThyvXXpMqWpEo/Xjob825g8B0 ZXZrX94gcMI/PLhPe37+L1F9gGGmNKPhe5dn1o3ErhWQ+UCZ4QL983pMOQ4XMtQJd1qE F+HlVqlOD0PQ5svj69dWpjTharptqQFfnSItdRlaOLERKG/TQXFKBC6biTFWx1X8irnv cBQlAQ+HP4zlrBe013qXzyaWfeBaoDzwcFZTk+uUFBmxbrgGbd7byKZYOVZndQ+oCGoK L37eeyvUY9V9zRBbcGrj0b6KiUJkVNcCzQOnm96u/E828p4P0n4aKLFyAVl8P6CkKqwo 2PyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=oABczCk+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:59 -0700 Message-Id: <20190904193059.26202-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v4 69/69] target/arm: Inline gen_bx_im into callers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There are only two remaining uses of gen_bx_im. In each case, we know the destination mode -- not changing in the case of gen_jmp or changing in the case of trans_BLX_i. Use this to simplify the surrounding code. For trans_BLX_i, use gen_jmp for the actual branch. For gen_jmp, use gen_set_pc_im to set up the single-step. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 +++++++------------------- 1 file changed, 7 insertions(+), 19 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 2412dde631..34bb280e3d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -765,21 +765,6 @@ static inline void gen_set_pc_im(DisasContext *s, target_ulong val) tcg_gen_movi_i32(cpu_R[15], val); } -/* Set PC and Thumb state from an immediate address. */ -static inline void gen_bx_im(DisasContext *s, uint32_t addr) -{ - TCGv_i32 tmp; - - s->base.is_jmp = DISAS_JUMP; - if (s->thumb != (addr & 1)) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, addr & 1); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, thumb)); - tcg_temp_free_i32(tmp); - } - tcg_gen_movi_i32(cpu_R[15], addr & ~1); -} - /* Set PC and Thumb state from var. var is marked as dead. */ static inline void gen_bx(DisasContext *s, TCGv_i32 var) { @@ -2725,9 +2710,8 @@ static inline void gen_jmp (DisasContext *s, uint32_t dest) { if (unlikely(is_singlestepping(s))) { /* An indirect jump so that we still trigger the debug exception. */ - if (s->thumb) - dest |= 1; - gen_bx_im(s, dest); + gen_set_pc_im(s, dest); + s->base.is_jmp = DISAS_JUMP; } else { gen_goto_tb(s, 0, dest); } @@ -10138,12 +10122,16 @@ static bool trans_BL(DisasContext *s, arg_i *a) static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) { + TCGv_i32 tmp; + /* For A32, ARCH(5) is checked near the start of the uncond block. */ if (s->thumb && (a->imm & 2)) { return false; } tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); - gen_bx_im(s, (read_pc(s) & ~3) + a->imm + !s->thumb); + tmp = tcg_const_i32(!s->thumb); + store_cpu_field(tmp, thumb); + gen_jmp(s, (read_pc(s) & ~3) + a->imm); return true; }