From patchwork Wed Sep 4 20:46:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 173094 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp471229ilq; Wed, 4 Sep 2019 14:42:10 -0700 (PDT) X-Google-Smtp-Source: APXvYqyl5XA+ITb+cXU9Nmg5JUzds5RC1sQG1ddC6zewEZjL8vPwTr1pFT09ATQpyFiYlrVDiDzF X-Received: by 2002:a17:906:5606:: with SMTP id f6mr179865ejq.110.1567633330671; Wed, 04 Sep 2019 14:42:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567633330; cv=none; d=google.com; s=arc-20160816; b=VKXnlcJ75bpnh02ozJRQ2++qdRnvgL23FSJ319ZDdZFwUr7kg+Yt7FGSrwaxU7BDfV wy6wSDHq1+fmn3o+SYYk8w3CSA5Jl6atb35nGLxmqsTycN7d2BNEbqQbm0LWh60W/dK/ 7Y9zIwlQGkhne6PAx/4+I78Rqdo3gHiAz68LJvTTYwV6sHCbh2W1z9tqRuENPSCvDM2y nA+BWKBAFDXXrl67XSP4wbyYYgwqoMwL9YSts9nlDuVraEWKpeIlzHXTrkmeJ32L5hW3 zz2XuwmTFyUhf+6WLFkOTZpUlvbyijS7I6Heicg8dERbOJ1WBjjJrLHnt/185ukE6Go+ GYVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=HQtnWNrP8D72LbEgXfy17eyXRyD3NwnFC8A9XXKTA4A=; b=LGTPHSeFl3ioNvoX33r4H/J4vHtVWXbCy5ISEv1nuZ5aCriy81OsuFyGMpSF05d3cO 9vP6Y9qqSbBl0OvI6B+1WDoD2nN0/dVmsNy9q6ZQDqeWjxxVftYzr15MRDHk2TL+dLio J/RVAKrmkHBH5WRcLyF2x12UXhdxKD9do91MEMUumJzpoCM95lsi4UJ/s5pqDfhr0Vzv f6yWJ5TUAex0zHWxTL0q89zAdicuhoIUcawkHkNaRlE1kSr14z6Vbu6sk0LeXCY+EVKO Cwi4p/jJIxXti27tkHDDK5Toy4P5OEHCji6VZ8+1ul6BdK7ATFg6MLPUy9glIgP/RNi0 zygg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k17si159889ejd.222.2019.09.04.14.42.10 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 04 Sep 2019 14:42:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:40414 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5d2W-0008S5-Ua for patch@linaro.org; Wed, 04 Sep 2019 17:42:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53295) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5cBZ-00089y-HB for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:47:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5cBU-0000iH-W6 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:47:23 -0400 Received: from 1.mo177.mail-out.ovh.net ([178.33.107.143]:56754) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i5cBU-0000hf-IK for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:47:20 -0400 Received: from player691.ha.ovh.net (unknown [10.109.159.136]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id 0EA751097C2 for ; Wed, 4 Sep 2019 22:47:18 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player691.ha.ovh.net (Postfix) with ESMTPSA id 405CB98B27AC; Wed, 4 Sep 2019 20:47:12 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: Peter Maydell Date: Wed, 4 Sep 2019 22:46:45 +0200 Message-Id: <20190904204659.13878-2-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190904204659.13878-1-clg@kaod.org> References: <20190904204659.13878-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2510193846439807761 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrudejhedgudehudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.33.107.143 Subject: [Qemu-devel] [RFC PATCH 01/15] hw: aspeed_scu: Add AST2600 support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , =?utf-8?q?C=C3=A9dric_Le_Goater?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Joel Stanley Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley AST2600 has extra registers. Increase the number of regs of the model and introduce a new field in the class to customize the MemoryRegion operations depending on the SoC model. Signed-off-by: Joel Stanley [clg: - improved commit log ] - reworked mode integration into new objet class ] Signed-off-by: Cédric Le Goater --- include/hw/misc/aspeed_scu.h | 7 +- hw/misc/aspeed_scu.c | 184 ++++++++++++++++++++++++++++++++++- 2 files changed, 185 insertions(+), 6 deletions(-) -- 2.21.0 diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index 239e94fe2c47..1d7f7ffc1598 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -17,8 +17,10 @@ #define ASPEED_SCU(obj) OBJECT_CHECK(AspeedSCUState, (obj), TYPE_ASPEED_SCU) #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400" #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500" +#define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600" #define ASPEED_SCU_NR_REGS (0x1A8 >> 2) +#define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2) typedef struct AspeedSCUState { /*< private >*/ @@ -27,7 +29,7 @@ typedef struct AspeedSCUState { /*< public >*/ MemoryRegion iomem; - uint32_t regs[ASPEED_SCU_NR_REGS]; + uint32_t regs[ASPEED_AST2600_SCU_NR_REGS]; uint32_t silicon_rev; uint32_t hw_strap1; uint32_t hw_strap2; @@ -38,6 +40,7 @@ typedef struct AspeedSCUState { #define AST2400_A1_SILICON_REV 0x02010303U #define AST2500_A0_SILICON_REV 0x04000303U #define AST2500_A1_SILICON_REV 0x04010303U +#define AST2600_A0_SILICON_REV 0x05000303U #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) @@ -54,6 +57,8 @@ typedef struct AspeedSCUClass { const uint32_t *resets; uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg); uint32_t apb_divider; + uint32_t nr_regs; + const MemoryRegionOps *ops; } AspeedSCUClass; #define ASPEED_SCU_PROT_KEY 0x1688A8A8 diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 620b25c20476..4190adab8220 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -88,6 +88,33 @@ #define BMC_REV TO_REG(0x19C) #define BMC_DEV_ID TO_REG(0x1A4) +#define AST2600_PROT_KEY TO_REG(0x00) +#define AST2600_SILICON_REV TO_REG(0x04) +#define AST2600_SILICON_REV2 TO_REG(0x14) +#define AST2600_SYS_RST_CTRL TO_REG(0x40) +#define AST2600_SYS_RST_CTRL_CLR TO_REG(0x44) +#define AST2600_SYS_RST_CTRL2 TO_REG(0x50) +#define AST2600_SYS_RST_CTRL2_CLR TO_REG(0x54) +#define AST2600_CLK_STOP_CTRL TO_REG(0x80) +#define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84) +#define AST2600_CLK_STOP_CTRL2 TO_REG(0x90) +#define AST2600_CLK_STOP_CTR2L_CLR TO_REG(0x94) +#define AST2600_MPLL_EXT TO_REG(0x224) +#define AST2600_EPLL_EXT TO_REG(0x244) +#define AST2600_CLK_SEL TO_REG(0x300) +#define AST2600_CLK_SEL2 TO_REG(0x304) +#define AST2600_CLK_SEL3 TO_REG(0x310) +#define AST2600_HW_STRAP1 TO_REG(0x500) +#define AST2600_HW_STRAP1_CLR TO_REG(0x504) +#define AST2600_HW_STRAP1_PROT TO_REG(0x508) +#define AST2600_HW_STRAP2 TO_REG(0x510) +#define AST2600_HW_STRAP2_CLR TO_REG(0x514) +#define AST2600_HW_STRAP2_PROT TO_REG(0x518) +#define AST2600_RNG_CTRL TO_REG(0x524) +#define AST2600_RNG_DATA TO_REG(0x540) + +#define AST2600_CLK TO_REG(0x40) + #define SCU_IO_REGION_SIZE 0x1000 static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = { @@ -178,7 +205,7 @@ static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size) AspeedSCUState *s = ASPEED_SCU(opaque); int reg = TO_REG(offset); - if (reg >= ARRAY_SIZE(s->regs)) { + if (reg >= ASPEED_SCU_NR_REGS) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", __func__, offset); @@ -208,7 +235,7 @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data, AspeedSCUState *s = ASPEED_SCU(opaque); int reg = TO_REG(offset); - if (reg >= ARRAY_SIZE(s->regs)) { + if (reg >= ASPEED_SCU_NR_REGS) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", __func__, offset); @@ -346,7 +373,7 @@ static void aspeed_scu_reset(DeviceState *dev) AspeedSCUState *s = ASPEED_SCU(dev); AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); - memcpy(s->regs, asc->resets, sizeof(s->regs)); + memcpy(s->regs, asc->resets, asc->nr_regs * 4); s->regs[SILICON_REV] = s->silicon_rev; s->regs[HW_STRAP1] = s->hw_strap1; s->regs[HW_STRAP2] = s->hw_strap2; @@ -358,6 +385,7 @@ static uint32_t aspeed_silicon_revs[] = { AST2400_A1_SILICON_REV, AST2500_A0_SILICON_REV, AST2500_A1_SILICON_REV, + AST2600_A0_SILICON_REV, }; bool is_supported_silicon_rev(uint32_t silicon_rev) @@ -377,6 +405,7 @@ static void aspeed_scu_realize(DeviceState *dev, Error **errp) { SysBusDevice *sbd = SYS_BUS_DEVICE(dev); AspeedSCUState *s = ASPEED_SCU(dev); + AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); if (!is_supported_silicon_rev(s->silicon_rev)) { error_setg(errp, "Unknown silicon revision: 0x%" PRIx32, @@ -384,7 +413,7 @@ static void aspeed_scu_realize(DeviceState *dev, Error **errp) return; } - memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_scu_ops, s, + memory_region_init_io(&s->iomem, OBJECT(s), asc->ops, s, TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE); sysbus_init_mmio(sbd, &s->iomem); @@ -395,7 +424,7 @@ static const VMStateDescription vmstate_aspeed_scu = { .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { - VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_SCU_NR_REGS), + VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_AST2600_SCU_NR_REGS), VMSTATE_END_OF_LIST() } }; @@ -436,6 +465,8 @@ static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data) asc->resets = ast2400_a0_resets; asc->calc_hpll = aspeed_2400_scu_calc_hpll; asc->apb_divider = 2; + asc->nr_regs = ASPEED_SCU_NR_REGS; + asc->ops = &aspeed_scu_ops; } static const TypeInfo aspeed_2400_scu_info = { @@ -454,6 +485,8 @@ static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data) asc->resets = ast2500_a1_resets; asc->calc_hpll = aspeed_2500_scu_calc_hpll; asc->apb_divider = 4; + asc->nr_regs = ASPEED_SCU_NR_REGS; + asc->ops = &aspeed_scu_ops; } static const TypeInfo aspeed_2500_scu_info = { @@ -463,11 +496,152 @@ static const TypeInfo aspeed_2500_scu_info = { .class_init = aspeed_2500_scu_class_init, }; +static uint64_t aspeed_ast2600_scu_read(void *opaque, hwaddr offset, + unsigned size) +{ + AspeedSCUState *s = ASPEED_SCU(opaque); + int reg = TO_REG(offset); + + if (reg >= ASPEED_AST2600_SCU_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + return 0; + } + + switch (reg) { + case AST2600_EPLL_EXT: + case AST2600_MPLL_EXT: + /* PLLs are always "locked" */ + return s->regs[reg] | BIT(31); + case AST2600_RNG_DATA: + /* + * On hardware, RNG_DATA works regardless of the state of the + * enable bit in RNG_CTRL + * + * TODO: Check this is true for ast2600 + */ + s->regs[AST2600_RNG_DATA] = aspeed_scu_get_random(); + break; + } + + return s->regs[reg]; +} + +static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, uint64_t data, + unsigned size) +{ + AspeedSCUState *s = ASPEED_SCU(opaque); + int reg = TO_REG(offset); + + if (reg >= ASPEED_AST2600_SCU_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + return; + } + + if (reg > PROT_KEY && !s->regs[PROT_KEY]) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); + } + + trace_aspeed_scu_write(offset, size, data); + + switch (reg) { + case AST2600_PROT_KEY: + s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0; + return; + case AST2600_HW_STRAP1: + case AST2600_HW_STRAP2: + if (s->regs[reg + 2]) { + return; + } + /* fall through */ + case AST2600_SYS_RST_CTRL: + case AST2600_SYS_RST_CTRL2: + /* W1S (Write 1 to set) registers */ + s->regs[reg] |= data; + return; + case AST2600_SYS_RST_CTRL_CLR: + case AST2600_SYS_RST_CTRL2_CLR: + case AST2600_HW_STRAP1_CLR: + case AST2600_HW_STRAP2_CLR: + /* W1C (Write 1 to clear) registers */ + s->regs[reg] &= ~data; + return; + + case AST2600_RNG_DATA: + case AST2600_SILICON_REV: + case AST2600_SILICON_REV2: + /* Add read only registers here */ + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + return; + } + + s->regs[reg] = data; +} + +static const MemoryRegionOps aspeed_ast2600_scu_ops = { + .read = aspeed_ast2600_scu_read, + .write = aspeed_ast2600_scu_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid.min_access_size = 4, + .valid.max_access_size = 4, + .valid.unaligned = false, +}; + +static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = { + [AST2600_SILICON_REV] = AST2600_SILICON_REV, + [AST2600_SILICON_REV2] = AST2600_SILICON_REV, + [AST2600_SYS_RST_CTRL] = 0xF7CFFEDC | 0x100, + [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC, + [AST2600_CLK_STOP_CTRL] = 0xEFF43E8B, + [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, +}; + +static void aspeed_ast2600_scu_reset(DeviceState *dev) +{ + AspeedSCUState *s = ASPEED_SCU(dev); + AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); + + memcpy(s->regs, asc->resets, asc->nr_regs * 4); + + s->regs[AST2600_SILICON_REV] = s->silicon_rev; + s->regs[AST2600_SILICON_REV2] = s->silicon_rev; + s->regs[AST2600_HW_STRAP1] = s->hw_strap1; + s->regs[AST2600_HW_STRAP2] = s->hw_strap2; + s->regs[PROT_KEY] = s->hw_prot_key; +} + +static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); + + dc->desc = "ASPEED 2600 System Control Unit"; + dc->reset = aspeed_ast2600_scu_reset; + asc->resets = ast2600_a0_resets; + asc->calc_hpll = aspeed_2500_scu_calc_hpll; + asc->apb_divider = 4; + asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS; + asc->ops = &aspeed_ast2600_scu_ops; +} + +static const TypeInfo aspeed_2600_scu_info = { + .name = TYPE_ASPEED_2600_SCU, + .parent = TYPE_ASPEED_SCU, + .instance_size = sizeof(AspeedSCUState), + .class_init = aspeed_2600_scu_class_init, +}; + static void aspeed_scu_register_types(void) { type_register_static(&aspeed_scu_info); type_register_static(&aspeed_2400_scu_info); type_register_static(&aspeed_2500_scu_info); + type_register_static(&aspeed_2600_scu_info); } type_init(aspeed_scu_register_types); From patchwork Wed Sep 4 20:46:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 173086 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp463354ilq; Wed, 4 Sep 2019 14:33:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqww7mqkeWD30vecB/6j8mgdIUdLpnk48ApglspxwoiIr/qTIDniVrKkAg3jEGsT9BHJKR3p X-Received: by 2002:aa7:c74e:: with SMTP id c14mr363567eds.223.1567632780529; Wed, 04 Sep 2019 14:33:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567632780; cv=none; d=google.com; s=arc-20160816; b=QOvWvb9GL6GQYAvwWRQtsK6+bNOpnZkPHd8BIgOO8bXKlHAatgftj9IiK2mgaZyRXW BOrakmgUL8EACSM6w669dJi16qYzye2iEROSRVFSU+XPs5TbtOVXkHv/9X4KakkvQEmH Xl3pB0Q3g4SIx+aWJS8pdLkzMgDcJ2vKe0/JLiQFg1TrAyndFyDdfNkf84T/vl5V0AuS fXRSdWNwQRsd4C3j4tu3aIzhs2xdtaw6us2d59+eInMfUHukHDY8nmiA1BF6/d98OELy ZdZDzWq5FfhHzNDvQlV5dCNMG6a2PFPi4pNV6kLGaP8FR2qGsayuZrKA2pFNE+Y6BZZC rWvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=GkaTcs7nUmjex66xrLMJyNBTMurOuARGf2oeyyl5K88=; b=Co91+CN2D0m1LfTtG2A/6BvCNoIHvH2lq+RC//saHWzi6VhZZiAu1Z+CRZbhfr+efJ tU8cCZzWLAAoyGXroMNW2/B6ja3AH9gxDEGPs69rSPVi/6j5tiN2q3L6T3vCyxcM2MDu m+A+8CX47hBv23bMTbCaRTlVO1rB5/MwPKfsBn8pz0GeaC78Klp5PVnXQvfktOq0JLUi xpVekUYE/s9rzeJplXXKyzknWpCWPoq9HZujTNcoATiXUGrKpZSNl6ZO4KWBjxUNECv6 QAyWx6ncE/Jmes6xbOlYtwGEDxWjHvDny8GEejhEt5sYsThxFmoq98s4FDRRN4J+7cvP Pi2Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e48si8142eda.130.2019.09.04.14.33.00 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 04 Sep 2019 14:33:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:40242 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5cte-000673-Or for patch@linaro.org; Wed, 04 Sep 2019 17:32:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53479) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5cCB-0000VW-8y for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:48:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5cC9-0001bx-JU for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:48:03 -0400 Received: from 5.mo7.mail-out.ovh.net ([178.32.120.239]:49610) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i5cC9-0001ak-D9 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:48:01 -0400 Received: from player691.ha.ovh.net (unknown [10.108.35.185]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 5471012E8EF for ; Wed, 4 Sep 2019 22:47:59 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player691.ha.ovh.net (Postfix) with ESMTPSA id 351E698B285F; Wed, 4 Sep 2019 20:47:52 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: Peter Maydell Date: Wed, 4 Sep 2019 22:46:51 +0200 Message-Id: <20190904204659.13878-8-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190904204659.13878-1-clg@kaod.org> References: <20190904204659.13878-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2521734316675468049 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrudejhedgudehudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.32.120.239 Subject: [Qemu-devel] [RFC PATCH 07/15] aspeed/sdmc: Add AST2600 support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , =?utf-8?q?C=C3=A9dric_Le_Goater?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Joel Stanley Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley The AST2600 SDMC controller is slightly different from its predecessor (DRAM training). Max memory is now 2G on the AST2600. Signed-off-by: Joel Stanley [clg: - improved commit log ] - reworked mode integration into new objet class ] Signed-off-by: Cédric Le Goater --- include/hw/misc/aspeed_sdmc.h | 1 + hw/misc/aspeed_scu.c | 2 + hw/misc/aspeed_sdmc.c | 82 +++++++++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) -- 2.21.0 diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h index 81156320c497..5dbde59fe777 100644 --- a/include/hw/misc/aspeed_sdmc.h +++ b/include/hw/misc/aspeed_sdmc.h @@ -15,6 +15,7 @@ #define ASPEED_SDMC(obj) OBJECT_CHECK(AspeedSDMCState, (obj), TYPE_ASPEED_SDMC) #define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400" #define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500" +#define TYPE_ASPEED_2600_SDMC TYPE_ASPEED_SDMC "-ast2600" #define ASPEED_SDMC_NR_REGS (0x174 >> 2) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 4190adab8220..df76bd58a1bb 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -99,6 +99,7 @@ #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84) #define AST2600_CLK_STOP_CTRL2 TO_REG(0x90) #define AST2600_CLK_STOP_CTR2L_CLR TO_REG(0x94) +#define AST2600_SDRAM_HANDSHAKE TO_REG(0x100) #define AST2600_MPLL_EXT TO_REG(0x224) #define AST2600_EPLL_EXT TO_REG(0x244) #define AST2600_CLK_SEL TO_REG(0x300) @@ -599,6 +600,7 @@ static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = { [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC, [AST2600_CLK_STOP_CTRL] = 0xEFF43E8B, [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, + [AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */ }; static void aspeed_ast2600_scu_reset(DeviceState *dev) diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index 60c99e773488..f3a63a2e01db 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -28,6 +28,7 @@ /* Control/Status Register #1 (ast2500) */ #define R_STATUS1 (0x60 / 4) #define PHY_BUSY_STATE BIT(0) +#define PHY_PLL_LOCK_STATUS BIT(4) #define R_ECC_TEST_CTRL (0x70 / 4) #define ECC_TEST_FINISHED BIT(12) @@ -85,6 +86,11 @@ #define ASPEED_SDMC_AST2500_512MB 0x2 #define ASPEED_SDMC_AST2500_1024MB 0x3 +#define ASPEED_SDMC_AST2600_256MB 0x0 +#define ASPEED_SDMC_AST2600_512MB 0x1 +#define ASPEED_SDMC_AST2600_1024MB 0x2 +#define ASPEED_SDMC_AST2600_2048MB 0x3 + #define ASPEED_SDMC_AST2500_READONLY_MASK \ (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \ ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \ @@ -186,6 +192,28 @@ static int ast2500_rambits(AspeedSDMCState *s) return ASPEED_SDMC_AST2500_512MB; } +static int ast2600_rambits(AspeedSDMCState *s) +{ + switch (s->ram_size >> 20) { + case 256: + return ASPEED_SDMC_AST2600_256MB; + case 512: + return ASPEED_SDMC_AST2600_512MB; + case 1024: + return ASPEED_SDMC_AST2600_1024MB; + case 2048: + return ASPEED_SDMC_AST2600_2048MB; + default: + break; + } + + /* use a common default */ + warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 512M", + s->ram_size); + s->ram_size = 512 << 20; + return ASPEED_SDMC_AST2600_512MB; +} + static void aspeed_sdmc_reset(DeviceState *dev) { AspeedSDMCState *s = ASPEED_SDMC(dev); @@ -340,11 +368,65 @@ static const TypeInfo aspeed_2500_sdmc_info = { .class_init = aspeed_2500_sdmc_class_init, }; +static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data) +{ + uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(3) | + ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | + ASPEED_SDMC_DRAM_SIZE(ast2600_rambits(s)); + + /* Make sure readonly bits are kept (use ast2500 mask) */ + data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; + + return data | fixed_conf; +} + +static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg, + uint32_t data) +{ + switch (reg) { + case R_CONF: + data = aspeed_2600_sdmc_compute_conf(s, data); + break; + case R_STATUS1: + /* Will never return 'busy'. 'lock status' is always set */ + data &= ~PHY_BUSY_STATE; + data |= PHY_PLL_LOCK_STATUS; + break; + case R_ECC_TEST_CTRL: + /* Always done, always happy */ + data |= ECC_TEST_FINISHED; + data &= ~ECC_TEST_FAIL; + break; + default: + break; + } + + s->regs[reg] = data; +} + +static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); + + dc->desc = "ASPEED 2600 SDRAM Memory Controller"; + asc->max_ram_size = 2048 << 20; + asc->compute_conf = aspeed_2600_sdmc_compute_conf; + asc->write = aspeed_2600_sdmc_write; +} + +static const TypeInfo aspeed_2600_sdmc_info = { + .name = TYPE_ASPEED_2600_SDMC, + .parent = TYPE_ASPEED_SDMC, + .class_init = aspeed_2600_sdmc_class_init, +}; + static void aspeed_sdmc_register_types(void) { type_register_static(&aspeed_sdmc_info); type_register_static(&aspeed_2400_sdmc_info); type_register_static(&aspeed_2500_sdmc_info); + type_register_static(&aspeed_2600_sdmc_info); } type_init(aspeed_sdmc_register_types); From patchwork Wed Sep 4 20:46:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 173098 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp479038ilq; Wed, 4 Sep 2019 14:51:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqywUC8KapZG8OzlsJK30uyDPAP5n0OkB4CI93mhrhxpEhZqK8xkpXgDaku+JBJua12J7pEr X-Received: by 2002:ac8:7601:: with SMTP id t1mr283310qtq.342.1567633906967; Wed, 04 Sep 2019 14:51:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567633906; cv=none; d=google.com; s=arc-20160816; b=rzvAKBwUP7KC09brWT2nJk10NgAy2WFLSAqTeiHqU85kU8L1IHy9VY6aPwqaLMTLJM rT7OTJgXDc8rXV4ofXWT+BdyhwKocXwe0C+XIMMVbTyaQMsza9Nm3oyGFj+SgXnv07NF zS3GQos9jeXwwFnszb917P1YmmI4PilS6xTv9q/Z/m0GcFLNaVGUH6G9Lvi5eExZxIgk LfD/mmBWFRCFRV3I4tFLJ/ZY7L+ku9qKYVSJj4/9RU7aioiBMO0IMmZfCNC9sJBr2m6P EkVEVsuxmtRnmhCjsN8a2sACq4VJtI/2Oc9ktHogX9ca7V+6oJQ3Dmm/avO3UNFs+qn0 lHyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=dBASQ8pq6Y0dk1ibQvTzKgWM71NWA3vrPlV4KeVAP0E=; b=bOmB6+T6mwNVgiddNd8PV9o7x3O10O3P+54B0zgyFS8v7h/2o5nsQ9ViY3NHeJENjd b0yO4Zj8IDQ8sBmr1ceRN183gLHW+hNmeKIOgS/HcDyNob8LF4VPKW0kTUOh7gascaUV oCCNNj8kqvTVnKzMT2y+fnjUbtCFa8KkCaXmB2tGeTdACAal9qHow7pkeMOF888efrs/ jYz/u/KciniIZ75SStxizuJjPDikEFzaK4dHwJXenn1580ucbVCRL21A/2fE6bin9u6q R3KuUIAkaW+gafi4tyZ/z7jjjI9o+dZRDOawRNhbiH7ofEnKie3VaJbY72GBMgPq3UjJ SXvA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a21si9710168qtc.357.2019.09.04.14.51.46 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 04 Sep 2019 14:51:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:40538 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5dBq-0001jc-7g for patch@linaro.org; Wed, 04 Sep 2019 17:51:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53565) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5cCO-0000kB-3x for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:48:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5cCM-0001j8-S9 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:48:15 -0400 Received: from 2.mo2.mail-out.ovh.net ([188.165.53.149]:33973) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i5cCM-0001iQ-M2 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:48:14 -0400 Received: from player691.ha.ovh.net (unknown [10.109.159.224]) by mo2.mail-out.ovh.net (Postfix) with ESMTP id 53A671AB3A5 for ; Wed, 4 Sep 2019 22:48:13 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player691.ha.ovh.net (Postfix) with ESMTPSA id A2E0998B289E; Wed, 4 Sep 2019 20:48:06 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: Peter Maydell Date: Wed, 4 Sep 2019 22:46:53 +0200 Message-Id: <20190904204659.13878-10-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190904204659.13878-1-clg@kaod.org> References: <20190904204659.13878-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2525674966197504785 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrudejhedgudehudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 188.165.53.149 Subject: [Qemu-devel] [RFC PATCH 09/15] hw: wdt_aspeed: Add AST2600 support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , =?utf-8?q?C=C3=A9dric_Le_Goater?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Joel Stanley Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley The AST2600 has four watchdogs, and they each have a 0x40 of registers. When running as part of an ast2600 system we must check a different offset for the system reset control register in the SCU. Signed-off-by: Joel Stanley [clg: - reworked mode integration into new objet class ] Signed-off-by: Cédric Le Goater --- include/hw/arm/aspeed_soc.h | 2 +- include/hw/watchdog/wdt_aspeed.h | 1 + hw/watchdog/wdt_aspeed.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 31 insertions(+), 1 deletion(-) -- 2.21.0 diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index ba5bbb53e1a1..b427f2668a8a 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -27,7 +27,7 @@ #include "hw/sd/aspeed_sdhci.h" #define ASPEED_SPIS_NUM 2 -#define ASPEED_WDTS_NUM 3 +#define ASPEED_WDTS_NUM 4 #define ASPEED_CPUS_NUM 2 #define ASPEED_MACS_NUM 2 diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h index 796342764e2e..dfedd7662dd1 100644 --- a/include/hw/watchdog/wdt_aspeed.h +++ b/include/hw/watchdog/wdt_aspeed.h @@ -18,6 +18,7 @@ OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT) #define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400" #define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500" +#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600" #define ASPEED_WDT_REGS_MAX (0x20 / 4) diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c index 9e241b7c8da4..6870dcf0c107 100644 --- a/hw/watchdog/wdt_aspeed.c +++ b/hw/watchdog/wdt_aspeed.c @@ -40,12 +40,14 @@ #define WDT_DRIVE_TYPE_MASK (0xFF << 24) #define WDT_PUSH_PULL_MAGIC (0xA8 << 24) #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) +#define WDT_RESET_MASK1 (0x1c / 4) #define WDT_TIMEOUT_STATUS (0x10 / 4) #define WDT_TIMEOUT_CLEAR (0x14 / 4) #define WDT_RESTART_MAGIC 0x4755 +#define AST2600_SCU_RESET_CONTROL1 (0x40 / 4) #define SCU_RESET_CONTROL1 (0x04 / 4) #define SCU_RESET_SDRAM BIT(0) @@ -74,6 +76,8 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) return s->regs[WDT_CTRL]; case WDT_RESET_WIDTH: return s->regs[WDT_RESET_WIDTH]; + case WDT_RESET_MASK1: + return s->regs[WDT_RESET_MASK1]; case WDT_TIMEOUT_STATUS: case WDT_TIMEOUT_CLEAR: qemu_log_mask(LOG_UNIMP, @@ -146,6 +150,11 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, s->regs[WDT_RESET_WIDTH] |= data & awc->ext_pulse_width_mask; break; + case WDT_RESET_MASK1: + /* TODO: implement */ + s->regs[WDT_RESET_MASK1] = data; + break; + case WDT_TIMEOUT_STATUS: case WDT_TIMEOUT_CLEAR: qemu_log_mask(LOG_UNIMP, @@ -316,12 +325,32 @@ static const TypeInfo aspeed_2500_wdt_info = { .class_init = aspeed_2500_wdt_class_init, }; +static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); + + dc->desc = "ASPEED 2600 Watchdog Controller"; + awc->offset = 0x40; + awc->ext_pulse_width_mask = 0xfffff; /* TODO */ + awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1; + awc->reset_pulse = aspeed_2500_wdt_reset_pulse; +} + +static const TypeInfo aspeed_2600_wdt_info = { + .name = TYPE_ASPEED_2600_WDT, + .parent = TYPE_ASPEED_WDT, + .instance_size = sizeof(AspeedWDTState), + .class_init = aspeed_2600_wdt_class_init, +}; + static void wdt_aspeed_register_types(void) { watchdog_add_model(&model); type_register_static(&aspeed_wdt_info); type_register_static(&aspeed_2400_wdt_info); type_register_static(&aspeed_2500_wdt_info); + type_register_static(&aspeed_2600_wdt_info); } type_init(wdt_aspeed_register_types) From patchwork Wed Sep 4 20:46:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 173097 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp478924ilq; Wed, 4 Sep 2019 14:51:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqxmsD1GRbk9OKJMkQavOS47eoRdL++5w3cHkCEgFPM/RtLzHiyNUmJbDn+3fd5dot8t8Dq6 X-Received: by 2002:a37:9b89:: with SMTP id d131mr8682353qke.176.1567633900714; Wed, 04 Sep 2019 14:51:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567633900; cv=none; d=google.com; s=arc-20160816; b=EObJVY8i2EWpXYd+znkE/JKsNeSCVvwWCdsEQGpfU98kqT6daV5+QFahaZaBv7yxM+ 5Tu/JYAdrz0uKKO4ytMUtcimNaCu1t//NbG2vyRULkn1pD+W//FVdSlLbd0LkhNtuzjC k9S2bOI9d1Y08FDhZ7qhzOPubH/ctU5ADRpnrmB6pmsX/FSVaF5kWgTVn88gxBzhHm5C W0P3RI28jAeazVYUhyJBrUSI/+Hhvebu+vkZ/4+eR3rIUFAUdQSjQaRhz6Dkcg8EVsTA 9L6/uG070+KaaDpAIVG7fP5lYx8MX/HqFWLJgbPPytStR0AaEhlblkXng7PA7S+xd28z Pseg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=80DGmK8yJaQDQ6SpsfBax7lLCFFcXGwSSG2hC3ZeePY=; b=AFEga9baW+QIGnqM6/PqJ19B2ZhI1DyEIXSFKimCULJtHye+Sg4g7/IUM4K4+nMO+f 22L/pWva/DWY4KvfohdL2q5/7Jrya9IaTxMgze4fVsQ7h0KwQNoLEqyO1BVDqmAC5Qvv ncpWzMcFj3e9BPRIbJTeXBskq9/kMCa1yZFtq//zlcLtpoDzQHAw9kg5toyI8ZIqeEi0 nNzs4S/4IJt9gFHi9ln8tTLDaaB4ZAjmGealEMjfOo0wyfVajH3JQFRufavWaVmamP6z vlCZ+eaFSdnBgmvkVKxUaL+nGdAalncr4RxmBOubvnNjb3TDXLcdrxXTbSNTBUZnZZyx Qjlg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q39si16726436qtk.133.2019.09.04.14.51.40 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 04 Sep 2019 14:51:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:40534 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5dBj-0001dF-Ru for patch@linaro.org; Wed, 04 Sep 2019 17:51:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53833) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5cCu-0001Dm-Bh for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:48:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5cCt-00023E-27 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:48:48 -0400 Received: from 7.mo7.mail-out.ovh.net ([46.105.43.131]:45247) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i5cCr-00020n-UH for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:48:46 -0400 Received: from player691.ha.ovh.net (unknown [10.108.54.36]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 0F36D130B4B for ; Wed, 4 Sep 2019 22:48:42 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player691.ha.ovh.net (Postfix) with ESMTPSA id D498398B2998; Wed, 4 Sep 2019 20:48:34 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: Peter Maydell Date: Wed, 4 Sep 2019 22:46:57 +0200 Message-Id: <20190904204659.13878-14-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190904204659.13878-1-clg@kaod.org> References: <20190904204659.13878-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2533556269348457233 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrudejhedgudehudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.43.131 Subject: [Qemu-devel] [RFC PATCH 13/15] aspeed: Parameterise number of MACs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , =?utf-8?q?C=C3=A9dric_Le_Goater?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Joel Stanley Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley To support the ast2600's four MACs allow SoCs to specify the number they have, and create that many. Signed-off-by: Joel Stanley Signed-off-by: Cédric Le Goater --- include/hw/arm/aspeed_soc.h | 5 ++++- hw/arm/aspeed_soc.c | 7 ++++++- 2 files changed, 10 insertions(+), 2 deletions(-) -- 2.21.0 diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 74db48374531..30b67a09f13c 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -30,7 +30,7 @@ #define ASPEED_SPIS_NUM 2 #define ASPEED_WDTS_NUM 4 #define ASPEED_CPUS_NUM 2 -#define ASPEED_MACS_NUM 2 +#define ASPEED_MACS_NUM 4 typedef struct AspeedSoCState { /*< private >*/ @@ -67,6 +67,7 @@ typedef struct AspeedSoCInfo { uint64_t sram_size; int spis_num; int wdts_num; + int macs_num; const int *irqmap; const hwaddr *memmap; uint32_t num_cpus; @@ -117,6 +118,8 @@ enum { ASPEED_I2C, ASPEED_ETH1, ASPEED_ETH2, + ASPEED_ETH3, + ASPEED_ETH4, ASPEED_SDRAM, ASPEED_XDMA, }; diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 80d7f206004c..8069de8d5a36 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -90,7 +90,9 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { [ASPEED_SPI1] = 0x1E630000, [ASPEED_SPI2] = 0x1E641000, [ASPEED_ETH1] = 0x1E660000, + [ASPEED_ETH3] = 0x1E670000, [ASPEED_ETH2] = 0x1E680000, + [ASPEED_ETH4] = 0x1E690000, [ASPEED_VIC] = 0x1E6C0000, [ASPEED_SDMC] = 0x1E6E0000, [ASPEED_SCU] = 0x1E6E2000, @@ -190,6 +192,7 @@ static const AspeedSoCInfo aspeed_socs[] = { .sram_size = 0x8000, .spis_num = 1, .wdts_num = 2, + .macs_num = 2, .irqmap = aspeed_soc_ast2400_irqmap, .memmap = aspeed_soc_ast2400_memmap, .num_cpus = 1, @@ -200,6 +203,7 @@ static const AspeedSoCInfo aspeed_socs[] = { .sram_size = 0x9000, .spis_num = 2, .wdts_num = 3, + .macs_num = 2, .irqmap = aspeed_soc_ast2500_irqmap, .memmap = aspeed_soc_ast2500_memmap, .num_cpus = 1, @@ -210,6 +214,7 @@ static const AspeedSoCInfo aspeed_socs[] = { .sram_size = 0x10000, .spis_num = 2, .wdts_num = 4, + .macs_num = 4, .irqmap = aspeed_soc_ast2600_irqmap, .memmap = aspeed_soc_ast2600_memmap, .num_cpus = 2, @@ -305,7 +310,7 @@ static void aspeed_soc_init(Object *obj) OBJECT(&s->scu), &error_abort); } - for (i = 0; i < ASPEED_MACS_NUM; i++) { + for (i = 0; i < sc->info->macs_num; i++) { sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]), sizeof(s->ftgmac100[i]), TYPE_FTGMAC100); } From patchwork Wed Sep 4 20:46:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 173089 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp466313ilq; Wed, 4 Sep 2019 14:36:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqwjrUOBRMqpjpTLy/+zW6vWQgW60dGbC6rztaH8NVmNK+uK0SpgTf4AkPT42fyCgHqaLbOy X-Received: by 2002:a5d:6785:: with SMTP id v5mr40301706wru.9.1567632983212; Wed, 04 Sep 2019 14:36:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567632983; cv=none; d=google.com; s=arc-20160816; b=HiggiikC8SXQB8VZm7zyLrx6XtxgV+O5UBD2vGeLEMfGPUb8iW8PfT9jLPo9nn3Qke MOp6MbB9sKTka8UFiX8Wa+R64Y+fyZWFHD9FH3wSBiJgaFjfKTHMsD9U7wXwEtv7VurD eEgaL6bIlWMij5JAtxZBLW0H8WdsNuUaqMFyZ3Nc0oLWIfjjPv/xB3A13mzfj9mrewIT eLwRrdchR2BcBSkgMqnSxuih8H+fb7aynQ7nZqc+QlzRas0zrr0v+DzS2uyKjcl8WChQ YiSBvz+oEV1+ylI/ApDe1GNvz4U2DrNMquZmnm6vyl0UEvEBkuSs0O6ok/ujoS64l6xy CNDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=AQ2W/wn5zzSquA+AEb7r6H1Zqtx7Tq0Ndz2XW/gYuWc=; b=D/FHksegwo7MbVXH7JodE37jPm2AB7l2ELwvhMgx+qsYeM/8LdnRJiqegVDjjK/qr3 ymVnGDbG8ZFt7ad6WkQTxUNCevnEPQxxhyN2tTzr5JNYdl9aH5hoPEdVUNjpA0P4Exw2 fzqbwKLpF2cMBcQKFO9qmayoMsUbIKtlkm0KEC5HLMQKR9Lqqq934F702D5jmhRVc8Xe gqE2NFyZdFpo5788mTAJ+yOhpkFD7Y0ntouiTf+bfastCvxRMLgm4vKgO+P16uI6e7mY 2xnqKFllrpa0JW3aHucJAWWLeQ3kF5yPxazFYIJOpft196xka5qHgEfqSffbm/KguI4Y XdTw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e3si60354wra.323.2019.09.04.14.36.23 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 04 Sep 2019 14:36:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:40292 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5cwv-0001PZ-I0 for patch@linaro.org; Wed, 04 Sep 2019 17:36:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53986) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5cD4-0001MB-NH for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:48:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5cD3-0002AY-DZ for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:48:58 -0400 Received: from 1.mo173.mail-out.ovh.net ([178.33.111.180]:60614) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i5cD3-00029t-7q for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:48:57 -0400 Received: from player691.ha.ovh.net (unknown [10.109.146.53]) by mo173.mail-out.ovh.net (Postfix) with ESMTP id 5E4B4117E70 for ; Wed, 4 Sep 2019 22:48:56 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player691.ha.ovh.net (Postfix) with ESMTPSA id CCAF698B2A19; Wed, 4 Sep 2019 20:48:49 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: Peter Maydell Date: Wed, 4 Sep 2019 22:46:59 +0200 Message-Id: <20190904204659.13878-16-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190904204659.13878-1-clg@kaod.org> References: <20190904204659.13878-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2537778391939910417 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrudejhedgudehudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 178.33.111.180 Subject: [Qemu-devel] [RFC PATCH 15/15] aspeed/soc: Add ASPEED Video stub X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , =?utf-8?q?C=C3=A9dric_Le_Goater?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Joel Stanley Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley Signed-off-by: Joel Stanley Signed-off-by: Cédric Le Goater --- include/hw/arm/aspeed_soc.h | 1 + hw/arm/aspeed_soc.c | 5 +++++ 2 files changed, 6 insertions(+) -- 2.21.0 diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 9e06a6ad4fbd..ef5b93e5e9cf 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -99,6 +99,7 @@ enum { ASPEED_SDMC, ASPEED_SCU, ASPEED_ADC, + ASPEED_VIDEO, ASPEED_SRAM, ASPEED_SDHCI, ASPEED_GPIO, diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index c3f99849b7f0..b9da49e16f2d 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -102,6 +102,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { [ASPEED_SCU] = 0x1E6E2000, [ASPEED_XDMA] = 0x1E6E7000, [ASPEED_ADC] = 0x1E6E9000, + [ASPEED_VIDEO] = 0x1E700000, [ASPEED_SDHCI] = 0x1E740000, [ASPEED_GPIO] = 0x1E780000, [ASPEED_GPIO_1_8V] = 0x1E780800, @@ -371,6 +372,10 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_IOMEM], ASPEED_SOC_IOMEM_SIZE); + /* Video engine stub */ + create_unimplemented_device("aspeed.video", sc->info->memmap[ASPEED_VIDEO], + 0x1000); + if (s->num_cpus > sc->info->num_cpus) { warn_report("%s: invalid number of CPUs %d, using default %d", sc->info->name, s->num_cpus, sc->info->num_cpus);