From patchwork Wed Jan 3 13:35:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 759675 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10BF519BD8 for ; Wed, 3 Jan 2024 13:37:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="IgvJB4hV" Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-a28a6cef709so44793566b.1 for ; Wed, 03 Jan 2024 05:37:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704289021; x=1704893821; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=XfDCSXNar/0OypW7xIXC/SzvfN+SSQCc1nv247H/a24=; b=IgvJB4hVyHg3hf8XIM99RSVYOwlXZfk5qn3T/BwJuk6CeCupv890n2qKQn4ELULmcs nUGNfHEEVDRGQWpF6ysdnJCSkwmjlfQFaGyeilcqpeMf7b9a1vg8i4viJ2/R6D2Gk4KN NpM45rkW8lDXSJ+93um1cwn57l+1AYZQ+/I/UEIVdray/VdE9Mo8GPNafgPGKKLYGmtE U01MjvQLuRmIFKIdn3gQLIllgkg3GSQLpN+dJz/Lw0FIKI/6S1qFQhpo4f+NkYYI0vMV T4ACS9eEUQ/u7masbITeJDRJgWkekwCLrUAOLcF3yrxm58OOqKJk05vm4gr1XxFhbMqZ W3kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704289021; x=1704893821; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XfDCSXNar/0OypW7xIXC/SzvfN+SSQCc1nv247H/a24=; b=gbgiqqQuCMLvJjBYFKzOowgDk13Rwt7r3S/SnurHhXh3iK6ZCCThfnssErsg75so0c QJfI2cGMj5DaywXUTDF+BvSlkP1Q/J2SvlwUFTfp1durs0qdhubdf7R7Hb9Xc7spl3CG lRUKyV5auQcP/gh96R6vY9Hgw9o29A8/7qMzlYffq1+isacbQS9zVazOtkr3zc1Gl+Tn vANUHHYHq6PLFC423bnDQZ1W9q8pSmkiFcvTUMH13WZzbTUaUPAkbbrtZ66lmrn3Se+D eP71b34PbLiqR9J5mUaw7376RQ/BfslmSWvSD/NPNKtEM8gcV29RJvLJtAIJYGb5c0cl +YQQ== X-Gm-Message-State: AOJu0Ywft1wP52ccne616rTALqofLLDOjYD+b4MaS9ki8puCDqav4Rq2 FsTGhU6Rlr1Ce+PPVlHfpzrfCiofYJoU3A== X-Google-Smtp-Source: AGHT+IHxiQuhkrSM0RX0P1zd4jMRtmlubvUGFuRkRDsJfTas5+F1IbZfHovp7xAyXzNb65nINVnfhw== X-Received: by 2002:a17:906:8910:b0:a27:5343:d3e8 with SMTP id fr16-20020a170906891000b00a275343d3e8mr4661410ejc.97.1704289021333; Wed, 03 Jan 2024 05:37:01 -0800 (PST) Received: from [10.167.154.1] (178235179036.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.36]) by smtp.gmail.com with ESMTPSA id cl2-20020a170906c4c200b00a275637e699sm6474351ejb.166.2024.01.03.05.37.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:37:01 -0800 (PST) From: Konrad Dybcio Date: Wed, 03 Jan 2024 14:35:59 +0100 Subject: [PATCH v5 01/12] clk: qcom: branch: Add a helper for setting the enable bit Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v5-1-99942e6bf1ba@linaro.org> References: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Johan Hovold , Bryan O'Donoghue X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704289018; l=1413; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Bhpm8sfSCBACZPHOO1eUmAv4id2tp/m4vWhfhP3T9EI=; b=hEZH4a69zyBqaQHiB5GodkQDXw08IHWnibGhlyALGGLFuAseNs0NvKha96pN6FJfWQb2xmkJL 70H7xhOF6ikC2pE3knApl7HawF5a8QnHmPCx9eCtcxaXKpH2FNOuCJM X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= We hardcode some clocks to be always-on, as they're essential to the functioning of the SoC / some peripherals. Add a helper to do so to make the writes less magic. Reviewed-by: Johan Hovold Reviewed-by: Bryan O'Donoghue Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/clk-branch.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 8ffed603c050..0514bc43100b 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -64,6 +64,7 @@ struct clk_mem_branch { #define CBCR_FORCE_MEM_PERIPH_OFF BIT(12) #define CBCR_WAKEUP GENMASK(11, 8) #define CBCR_SLEEP GENMASK(7, 4) +#define CBCR_CLOCK_ENABLE BIT(0) static inline void qcom_branch_set_force_mem_core(struct regmap *regmap, struct clk_branch clk, bool on) @@ -98,6 +99,12 @@ static inline void qcom_branch_set_sleep(struct regmap *regmap, struct clk_branc FIELD_PREP(CBCR_SLEEP, val)); } +static inline void qcom_branch_set_clk_en(struct regmap *regmap, u32 cbcr) +{ + regmap_update_bits(regmap, cbcr, CBCR_CLOCK_ENABLE, + CBCR_CLOCK_ENABLE); +} + extern const struct clk_ops clk_branch_ops; extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch_simple_ops; From patchwork Wed Jan 3 13:36:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 759674 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E498519BDE for ; Wed, 3 Jan 2024 13:37:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="bvOqS2M6" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-a28aa47bd15so43378666b.2 for ; Wed, 03 Jan 2024 05:37:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704289023; x=1704893823; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hA5+S1rM4gMiohG5+nQpYSDFJAJ1brF/eqxgbJITzcQ=; b=bvOqS2M6WtKotZI0oj0QFLRbVO0CA4iyqfli/a17sXUY5Qe8sg5o0PkwmZITs8Byky 2so6iQoSqH9/uXh3bc9raTGMSn7IHn9vctlSxBPulSjmHrQ4QpgzfXAAnbU1zKAdotx/ GMiMZ/lJH3+BdutRXoI7gk6SWJpOeh84U7o/D2ZvbOfz9C+dsgNyAFyyxeEDft0RP9GK N4X7QQjfSxrbZSUwQnHMf9FTFNcESqH28EyG6l30+6qgDBuj2hbjq/qFaxU9oFPVT4It 0yiw290VI3sL8SCNB1NTq9PwVjB2JwBVVAENYA9/3FOI9vl1eFhCI+w2Li5tpON5owZM Wk6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704289023; x=1704893823; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hA5+S1rM4gMiohG5+nQpYSDFJAJ1brF/eqxgbJITzcQ=; b=isxDK/Gy/rd/3R79grpyooUIf2zZIJzRnsQW6A/jluEaPqMzL14PvaK4lR3kfRC4GK VHFDAO7CAWW/JGqQRJQeHP9sBEiGujYarFzRaRlOF1vBY6oKQb/XOwDS5M5flAjE+6yv YeHFst5E5SVl1jrHSexWSChIf/aWkAAai64ULIaTZLDDaGh3atAMnftSi1+qIMk6FSje IiOXB+OLBpOF6FP5Hg2Y4UUCogHL/tV9sKJLsOrrkr0vvXJLWbyCbF0dVlJVu0lnHcIp 0sWwn1sZh61SLitTkJqlMSka8tV2+7z71GZaxgFd7vWeltlXUbA3DrSysyYrsjY3+HAj TINQ== X-Gm-Message-State: AOJu0Yzw1qDFW4PojvvvrUp3uwONkZfb9zDc3bt9GtevXfzzg++UUhEG dWjH7vhbdUdi8BuW3JDxcO7VOBRo1xta/A== X-Google-Smtp-Source: AGHT+IGfTzV5j76ij+IQTmNI7BCKAmopC3dBkkb170KMH8Y+Z6mQb1mK4R3d+pF+4KZjYaUGg9HzeQ== X-Received: by 2002:a17:906:7f99:b0:a28:b085:bea with SMTP id f25-20020a1709067f9900b00a28b0850beamr169560ejr.53.1704289022992; Wed, 03 Jan 2024 05:37:02 -0800 (PST) Received: from [10.167.154.1] (178235179036.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.36]) by smtp.gmail.com with ESMTPSA id cl2-20020a170906c4c200b00a275637e699sm6474351ejb.166.2024.01.03.05.37.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:37:02 -0800 (PST) From: Konrad Dybcio Date: Wed, 03 Jan 2024 14:36:00 +0100 Subject: [PATCH v5 02/12] clk: qcom: Use qcom_branch_set_clk_en() Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v5-2-99942e6bf1ba@linaro.org> References: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Bryan O'Donoghue X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704289018; l=41621; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=o5DvaqMapSYx4rP5dmjD93mtcBuwMok2ueBvVpKJ0BM=; b=0CHygtcttCcm1jhJXkDPNCKXngm1aIPTpf0St4ixHvlSQV4vuvsle3+mW7SCd9512TVZadZ+W y7rsVUJmFkBAJ+vWAtIe0kSZFFkZ76pYWBJgXBq6De+7J9qDexZrszy X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Instead of magically poking at the bit0 of branch clocks' CBCR, use the newly introduced helper. Reviewed-by: Bryan O'Donoghue Signed-off-by: Konrad Dybcio Reviewed-by: Johan Hovold --- drivers/clk/qcom/camcc-sc8280xp.c | 6 ++---- drivers/clk/qcom/camcc-sm8550.c | 10 +++------- drivers/clk/qcom/dispcc-qcm2290.c | 4 ++-- drivers/clk/qcom/dispcc-sc7280.c | 7 ++----- drivers/clk/qcom/dispcc-sc8280xp.c | 4 ++-- drivers/clk/qcom/dispcc-sm6115.c | 4 ++-- drivers/clk/qcom/dispcc-sm8250.c | 4 ++-- drivers/clk/qcom/dispcc-sm8450.c | 7 ++----- drivers/clk/qcom/dispcc-sm8550.c | 7 ++----- drivers/clk/qcom/dispcc-sm8650.c | 4 ++-- drivers/clk/qcom/gcc-sa8775p.c | 25 ++++++++++--------------- drivers/clk/qcom/gcc-sc7180.c | 22 +++++++++------------- drivers/clk/qcom/gcc-sc7280.c | 20 ++++++++------------ drivers/clk/qcom/gcc-sc8180x.c | 28 +++++++++++----------------- drivers/clk/qcom/gcc-sc8280xp.c | 25 ++++++++++--------------- drivers/clk/qcom/gcc-sdx55.c | 12 ++++-------- drivers/clk/qcom/gcc-sdx65.c | 13 +++++-------- drivers/clk/qcom/gcc-sdx75.c | 10 +++------- drivers/clk/qcom/gcc-sm4450.c | 28 +++++++++------------------- drivers/clk/qcom/gcc-sm6375.c | 11 ++++------- drivers/clk/qcom/gcc-sm7150.c | 23 +++++++++-------------- drivers/clk/qcom/gcc-sm8250.c | 19 +++++++------------ drivers/clk/qcom/gcc-sm8350.c | 20 ++++++++------------ drivers/clk/qcom/gcc-sm8450.c | 21 ++++++++------------- drivers/clk/qcom/gcc-sm8550.c | 21 ++++++++------------- drivers/clk/qcom/gcc-sm8650.c | 16 ++++++++-------- drivers/clk/qcom/gcc-x1e80100.c | 16 ++++++++-------- drivers/clk/qcom/gpucc-sc7280.c | 9 +++------ drivers/clk/qcom/gpucc-sc8280xp.c | 9 +++------ drivers/clk/qcom/gpucc-sm8550.c | 10 +++------- drivers/clk/qcom/lpasscorecc-sc7180.c | 7 ++----- drivers/clk/qcom/videocc-sm8250.c | 6 +++--- drivers/clk/qcom/videocc-sm8350.c | 10 +++------- drivers/clk/qcom/videocc-sm8450.c | 13 ++++--------- drivers/clk/qcom/videocc-sm8550.c | 13 ++++--------- 35 files changed, 175 insertions(+), 289 deletions(-) diff --git a/drivers/clk/qcom/camcc-sc8280xp.c b/drivers/clk/qcom/camcc-sc8280xp.c index 3dcd79b01515..84f9caf3ddbf 100644 --- a/drivers/clk/qcom/camcc-sc8280xp.c +++ b/drivers/clk/qcom/camcc-sc8280xp.c @@ -3010,10 +3010,8 @@ static int camcc_sc8280xp_probe(struct platform_device *pdev) clk_lucid_pll_configure(&camcc_pll6, regmap, &camcc_pll6_config); clk_lucid_pll_configure(&camcc_pll7, regmap, &camcc_pll7_config); - /* - * Keep camcc_gdsc_clk always enabled: - */ - regmap_update_bits(regmap, 0xc1e4, BIT(0), 1); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0xc1e4); /* CAMCC_GDSC_CLK */ ret = qcom_cc_really_probe(pdev, &camcc_sc8280xp_desc, regmap); if (ret) diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c index dd51ba4ea757..1ef59a96f664 100644 --- a/drivers/clk/qcom/camcc-sm8550.c +++ b/drivers/clk/qcom/camcc-sm8550.c @@ -3536,13 +3536,9 @@ static int cam_cc_sm8550_probe(struct platform_device *pdev) clk_lucid_ole_pll_configure(&cam_cc_pll11, regmap, &cam_cc_pll11_config); clk_lucid_ole_pll_configure(&cam_cc_pll12, regmap, &cam_cc_pll12_config); - /* - * Keep clocks always enabled: - * cam_cc_gdsc_clk - * cam_cc_sleep_clk - */ - regmap_update_bits(regmap, 0x1419c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x142cc, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x1419c); /* CAM_CC_GDSC_CLK */ + qcom_branch_set_clk_en(regmap, 0x142cc); /* CAM_CC_SLEEP_CLK */ ret = qcom_cc_really_probe(pdev, &cam_cc_sm8550_desc, regmap); diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c index 9206f0eed446..200f81ac4827 100644 --- a/drivers/clk/qcom/dispcc-qcm2290.c +++ b/drivers/clk/qcom/dispcc-qcm2290.c @@ -519,8 +519,8 @@ static int disp_cc_qcm2290_probe(struct platform_device *pdev) clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); - /* Keep DISP_CC_XO_CLK always-ON */ - regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &disp_cc_qcm2290_desc, regmap); if (ret) { diff --git a/drivers/clk/qcom/dispcc-sc7280.c b/drivers/clk/qcom/dispcc-sc7280.c index ad596d567f6a..3ba07f08cbdd 100644 --- a/drivers/clk/qcom/dispcc-sc7280.c +++ b/drivers/clk/qcom/dispcc-sc7280.c @@ -878,11 +878,8 @@ static int disp_cc_sc7280_probe(struct platform_device *pdev) clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); - /* - * Keep the clocks always-ON - * DISP_CC_XO_CLK - */ - regmap_update_bits(regmap, 0x5008, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x5008); /* DISP_CC_XO_CLK */ return qcom_cc_really_probe(pdev, &disp_cc_sc7280_desc, regmap); } diff --git a/drivers/clk/qcom/dispcc-sc8280xp.c b/drivers/clk/qcom/dispcc-sc8280xp.c index 30f636b9f0ec..bd1ffb143e0c 100644 --- a/drivers/clk/qcom/dispcc-sc8280xp.c +++ b/drivers/clk/qcom/dispcc-sc8280xp.c @@ -3178,8 +3178,8 @@ static int disp_cc_sc8280xp_probe(struct platform_device *pdev) goto out_pm_runtime_put; } - /* DISP_CC_XO_CLK always-on */ - regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */ out_pm_runtime_put: pm_runtime_put_sync(&pdev->dev); diff --git a/drivers/clk/qcom/dispcc-sm6115.c b/drivers/clk/qcom/dispcc-sm6115.c index 1fab43f08e73..bd07f26af35a 100644 --- a/drivers/clk/qcom/dispcc-sm6115.c +++ b/drivers/clk/qcom/dispcc-sm6115.c @@ -583,8 +583,8 @@ static int disp_cc_sm6115_probe(struct platform_device *pdev) clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); - /* Keep DISP_CC_XO_CLK always-ON */ - regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &disp_cc_sm6115_desc, regmap); if (ret) { diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index e17bb8b543b5..ccf696c74dc3 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -1365,8 +1365,8 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) /* Enable clock gating for MDP clocks */ regmap_update_bits(regmap, 0x8000, 0x10, 0x10); - /* DISP_CC_XO_CLK always-on */ - regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap); diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c index 2c4aecd75186..b358751aba4b 100644 --- a/drivers/clk/qcom/dispcc-sm8450.c +++ b/drivers/clk/qcom/dispcc-sm8450.c @@ -1787,11 +1787,8 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev) /* Enable clock gating for MDP clocks */ regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); - /* - * Keep clocks always enabled: - * disp_cc_xo_clk - */ - regmap_update_bits(regmap, 0xe05c, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &disp_cc_sm8450_desc, regmap); if (ret) diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c index f96d8b81fd9a..3d86b20e2062 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -1780,11 +1780,8 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev) /* Enable clock gating for MDP clocks */ regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); - /* - * Keep clocks always enabled: - * disp_cc_xo_clk - */ - regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &disp_cc_sm8550_desc, regmap); if (ret) diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c index f3b1d9d16bae..795ac4d93658 100644 --- a/drivers/clk/qcom/dispcc-sm8650.c +++ b/drivers/clk/qcom/dispcc-sm8650.c @@ -1777,8 +1777,8 @@ static int disp_cc_sm8650_probe(struct platform_device *pdev) /* Enable clock gating for MDP clocks */ regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); - /* Keep clocks always enabled */ - regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0)); /* disp_cc_xo_clk */ + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &disp_cc_sm8650_desc, regmap); if (ret) diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c index 8171d23c96e6..9dbb68f60d86 100644 --- a/drivers/clk/qcom/gcc-sa8775p.c +++ b/drivers/clk/qcom/gcc-sa8775p.c @@ -4742,21 +4742,16 @@ static int gcc_sa8775p_probe(struct platform_device *pdev) if (ret) return ret; - /* - * Keep the clocks always-ON - * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP1_AHB_CLK, - * GCC_DISP1_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, - * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK. - */ - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x32020, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xc7004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xc7018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x33004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x33018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x7d004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x32020); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0xc7004); /* GCC_DISP1_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0xc7018); /* GCC_DISP1_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x33004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x33018); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x7d004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */ return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap); } diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c index a3406aadbd17..6a5f785c0ced 100644 --- a/drivers/clk/qcom/gcc-sc7180.c +++ b/drivers/clk/qcom/gcc-sc7180.c @@ -2443,19 +2443,15 @@ static int gcc_sc7180_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); regmap_update_bits(regmap, 0x71028, 0x3, 0x3); - /* - * Keep the clocks always-ON - * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, - * GCC_DISP_AHB_CLK, GCC_GPU_CFG_AHB_CLK - */ - regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b02c); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b028); /* GCC_VIDEO_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b030); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index 2b661df5de26..f45a8318900c 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -3453,18 +3453,14 @@ static int gcc_sc7280_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - /* - * Keep the clocks always-ON - * GCC_CAMERA_AHB_CLK/XO_CLK, GCC_DISP_AHB_CLK/XO_CLK - * GCC_VIDEO_AHB_CLK/XO_CLK, GCC_GPU_CFG_AHB_CLK - */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x2701C, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x26004);/* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x26028);/* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x27004);/* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x2701c);/* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x28004);/* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x28014);/* GCC_VIDEO_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004);/* GCC_GPU_CFG_AHB_CLK */ regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13)); ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c index ae2147381559..c8dfe76f5582 100644 --- a/drivers/clk/qcom/gcc-sc8180x.c +++ b/drivers/clk/qcom/gcc-sc8180x.c @@ -4579,23 +4579,17 @@ static int gcc_sc8180x_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - /* - * Enable the following always-on clocks: - * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK, - * GCC_VIDEO_XO_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_XO_CLK, - * GCC_CPUSS_GNOC_CLK, GCC_CPUSS_DVM_BUS_CLK, GCC_NPU_CFG_AHB_CLK and - * GCC_GPU_CFG_AHB_CLK - */ - regmap_update_bits(regmap, 0xb004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb00c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb040, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb044, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb048, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x48190, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x4d004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0xb004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0xb008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0xb00c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0xb040); /* GCC_VIDEO_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0xb044); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0xb048); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ + qcom_branch_set_clk_en(regmap, 0x48190); /* GCC_CPUSS_DVM_BUS_CLK */ + qcom_branch_set_clk_en(regmap, 0x4d004); /* GCC_NPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c index bfb77931e868..816a06bfedb2 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -7543,21 +7543,16 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev) goto err_put_rpm; } - /* - * Keep the clocks always-ON - * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, - * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, - * GCC_VIDEO_XO_CLK, GCC_DISP1_AHB_CLK, GCC_DISP1_XO_CLK - */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x26020, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xbb004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xbb028, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x26020); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x27028); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x28004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x28028); /* GCC_VIDEO_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0xbb004); /* GCC_DISP1_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0xbb028); /* GCC_DISP1_XO_CLK */ ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); if (ret) diff --git a/drivers/clk/qcom/gcc-sdx55.c b/drivers/clk/qcom/gcc-sdx55.c index d5e17122698c..26279b8d321a 100644 --- a/drivers/clk/qcom/gcc-sdx55.c +++ b/drivers/clk/qcom/gcc-sdx55.c @@ -1611,14 +1611,10 @@ static int gcc_sdx55_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - /* - * Keep the clocks always-ON as they are critical to the functioning - * of the system: - * GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK - */ - regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); - regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x6d008); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */ + regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */ return qcom_cc_really_probe(pdev, &gcc_sdx55_desc, regmap); } diff --git a/drivers/clk/qcom/gcc-sdx65.c b/drivers/clk/qcom/gcc-sdx65.c index ffddbed5a6db..8fde6463574b 100644 --- a/drivers/clk/qcom/gcc-sdx65.c +++ b/drivers/clk/qcom/gcc-sdx65.c @@ -1574,14 +1574,11 @@ static int gcc_sdx65_probe(struct platform_device *pdev) regmap = qcom_cc_map(pdev, &gcc_sdx65_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); - /* - * Keep the clocks always-ON as they are critical to the functioning - * of the system: - * GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK - */ - regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); - regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); + + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x6d008); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */ + regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */ return qcom_cc_really_probe(pdev, &gcc_sdx65_desc, regmap); } diff --git a/drivers/clk/qcom/gcc-sdx75.c b/drivers/clk/qcom/gcc-sdx75.c index 573af17bd24c..c51338f08ef1 100644 --- a/drivers/clk/qcom/gcc-sdx75.c +++ b/drivers/clk/qcom/gcc-sdx75.c @@ -2936,13 +2936,9 @@ static int gcc_sdx75_probe(struct platform_device *pdev) if (ret) return ret; - /* - * Keep clocks always enabled: - * gcc_ahb_pcie_link_clk - * gcc_xo_pcie_link_clk - */ - regmap_update_bits(regmap, 0x3e004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x3e008, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x3e004); /* GCC_AHB_PCIE_LINK_CLK */ + qcom_branch_set_clk_en(regmap, 0x3e008); /* GCC_XO_PCIE_LINK_CLK */ return qcom_cc_really_probe(pdev, &gcc_sdx75_desc, regmap); } diff --git a/drivers/clk/qcom/gcc-sm4450.c b/drivers/clk/qcom/gcc-sm4450.c index 31abe2775fc8..1226d39e6442 100644 --- a/drivers/clk/qcom/gcc-sm4450.c +++ b/drivers/clk/qcom/gcc-sm4450.c @@ -2849,25 +2849,15 @@ static int gcc_sm4450_probe(struct platform_device *pdev) qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); - /* - * Keep clocks always enabled: - * gcc_camera_ahb_clk - * gcc_camera_sleep_clk - * gcc_camera_xo_clk - * gcc_disp_ahb_clk - * gcc_disp_xo_clk - * gcc_gpu_cfg_ahb_clk - * gcc_video_ahb_clk - * gcc_video_xo_clk - */ - regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x36018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x3601c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x37014, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x42018, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x36018); /* GCC_CAMERA_SLEEP_CLK */ + qcom_branch_set_clk_en(regmap, 0x3601c); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x37014); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x81004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x42018); /* GCC_VIDEO_XO_CLK */ regmap_update_bits(regmap, 0x4201c, BIT(21), BIT(21)); diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c index 3dd15d765b22..84639d5b89bf 100644 --- a/drivers/clk/qcom/gcc-sm6375.c +++ b/drivers/clk/qcom/gcc-sm6375.c @@ -3882,13 +3882,10 @@ static int gcc_sm6375_probe(struct platform_device *pdev) if (ret) return ret; - /* - * Keep the following clocks always on: - * GCC_CAMERA_XO_CLK, GCC_CPUSS_GNOC_CLK, GCC_DISP_XO_CLK - */ - regmap_update_bits(regmap, 0x17028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x2b004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x1702c, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x2b004); /* GCC_CPUSS_GNOC_CLK */ + qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */ clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config); clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config); diff --git a/drivers/clk/qcom/gcc-sm7150.c b/drivers/clk/qcom/gcc-sm7150.c index d9983bb27475..47c25b3d95ad 100644 --- a/drivers/clk/qcom/gcc-sm7150.c +++ b/drivers/clk/qcom/gcc-sm7150.c @@ -3002,20 +3002,15 @@ static int gcc_sm7150_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); regmap_update_bits(regmap, 0x71028, 0x3, 0x3); - /* - * Keep the critical clocks always-ON - * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, - * GCC_DISP_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_VIDEO_XO_CLK, - * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK - */ - regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b02c); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b028); /* GCC_VIDEO_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b030); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ ret = qcom_cc_register_rcg_dfs(regmap, gcc_sm7150_dfs_desc, ARRAY_SIZE(gcc_sm7150_dfs_desc)); diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c index c6c5261264f1..9990931aa172 100644 --- a/drivers/clk/qcom/gcc-sm8250.c +++ b/drivers/clk/qcom/gcc-sm8250.c @@ -3643,18 +3643,13 @@ static int gcc_sm8250_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); regmap_update_bits(regmap, 0x71028, 0x3, 0x3); - /* - * Keep the clocks always-ON - * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK, - * GCC_CPUSS_DVM_BUS_CLK, GCC_GPU_CFG_AHB_CLK, - * GCC_SYS_NOC_CPUSS_AHB_CLK - */ - regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x4818c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x52000, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x4818c); /* GCC_CPUSS_DVM_BUS_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x52000); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c index 1385a98eb3bb..e83a9facc19b 100644 --- a/drivers/clk/qcom/gcc-sm8350.c +++ b/drivers/clk/qcom/gcc-sm8350.c @@ -3806,18 +3806,14 @@ static int gcc_sm8350_probe(struct platform_device *pdev) return PTR_ERR(regmap); } - /* - * Keep the critical clock always-On - * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, - * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK - */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x26018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x2701c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28020, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x26018); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x2701c); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x28004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x28020); /* GCC_VIDEO_XO_CLK */ ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); if (ret) diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index 563542982551..43e9c32921f3 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -3280,19 +3280,14 @@ static int gcc_sm8450_probe(struct platform_device *pdev) /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14)); - /* - * Keep the critical clock always-On - * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, - * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, - * gcc_video_xo_clk - */ - regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x36020, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x3701c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x42028, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x36020); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x3701c); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x81004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x42028); /* GCC_VIDEO_XO_CLK */ return qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap); } diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index b883dffe5f7a..60895648f281 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -3352,19 +3352,14 @@ static int gcc_sm8550_probe(struct platform_device *pdev) /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14)); - /* - * Keep the critical clock always-On - * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, - * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, - * gcc_video_xo_clk - */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ regmap_write(regmap, 0x52024, 0x0); diff --git a/drivers/clk/qcom/gcc-sm8650.c b/drivers/clk/qcom/gcc-sm8650.c index 9174dd82308c..c4a6540b1522 100644 --- a/drivers/clk/qcom/gcc-sm8650.c +++ b/drivers/clk/qcom/gcc-sm8650.c @@ -3808,14 +3808,14 @@ static int gcc_sm8650_probe(struct platform_device *pdev) if (ret) return ret; - /* Keep the critical clock always-On */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_clk */ - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); /* gcc_camera_xo_clk */ - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); /* gcc_disp_ahb_clk */ - regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); /* gcc_disp_xo_clk */ - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); /* gcc_gpu_cfg_ahb_clk */ - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); /* gcc_video_ahb_clk */ - regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); /* gcc_video_xo_clk */ + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c index d7182d6e9783..1404017be918 100644 --- a/drivers/clk/qcom/gcc-x1e80100.c +++ b/drivers/clk/qcom/gcc-x1e80100.c @@ -6769,14 +6769,14 @@ static int gcc_x1e80100_probe(struct platform_device *pdev) if (ret) return ret; - /* Keep the critical clock always-On */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_clk */ - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); /* gcc_camera_xo_clk */ - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); /* gcc_disp_ahb_clk */ - regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); /* gcc_disp_xo_clk */ - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); /* gcc_video_ahb_clk */ - regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); /* gcc_video_xo_clk */ - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); /* gcc_gpu_cfg_ahb_clk */ + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ regmap_write(regmap, 0x52224, 0x0); diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c index 1490cd45a654..293b57080685 100644 --- a/drivers/clk/qcom/gpucc-sc7280.c +++ b/drivers/clk/qcom/gpucc-sc7280.c @@ -457,12 +457,9 @@ static int gpu_cc_sc7280_probe(struct platform_device *pdev) clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); - /* - * Keep the clocks always-ON - * GPU_CC_CB_CLK, GPUCC_CX_GMU_CLK - */ - regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x1098, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x1170); /* GPU_CC_CB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1098); /* GPUCC_CX_GMU_CLK */ regmap_update_bits(regmap, 0x1098, BIT(13), BIT(13)); return qcom_cc_really_probe(pdev, &gpu_cc_sc7280_desc, regmap); diff --git a/drivers/clk/qcom/gpucc-sc8280xp.c b/drivers/clk/qcom/gpucc-sc8280xp.c index 8e147ee294ee..a8ea2143057d 100644 --- a/drivers/clk/qcom/gpucc-sc8280xp.c +++ b/drivers/clk/qcom/gpucc-sc8280xp.c @@ -444,12 +444,9 @@ static int gpu_cc_sc8280xp_probe(struct platform_device *pdev) clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); - /* - * Keep the clocks always-ON - * GPU_CC_CB_CLK, GPU_CC_CXO_CLK - */ - regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x109c, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x1170); /* GPU_CC_CB_CLK */ + qcom_branch_set_clk_en(regmap, 0x109c); /* GPU_CC_CXO_CLK */ ret = qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap); pm_runtime_put(&pdev->dev); diff --git a/drivers/clk/qcom/gpucc-sm8550.c b/drivers/clk/qcom/gpucc-sm8550.c index 2fa8673424d7..783d14ef9a0c 100644 --- a/drivers/clk/qcom/gpucc-sm8550.c +++ b/drivers/clk/qcom/gpucc-sm8550.c @@ -575,13 +575,9 @@ static int gpu_cc_sm8550_probe(struct platform_device *pdev) clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); - /* - * Keep clocks always enabled: - * gpu_cc_cxo_aon_clk - * gpu_cc_demet_clk - */ - regmap_update_bits(regmap, 0x9004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x900c, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */ + qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */ return qcom_cc_really_probe(pdev, &gpu_cc_sm8550_desc, regmap); } diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c b/drivers/clk/qcom/lpasscorecc-sc7180.c index 9051fd567112..fd9cd2e3f956 100644 --- a/drivers/clk/qcom/lpasscorecc-sc7180.c +++ b/drivers/clk/qcom/lpasscorecc-sc7180.c @@ -401,11 +401,8 @@ static int lpass_core_cc_sc7180_probe(struct platform_device *pdev) goto exit; } - /* - * Keep the CLK always-ON - * LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK - */ - regmap_update_bits(regmap, 0x24000, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x24000); /* LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK */ /* PLL settings */ regmap_write(regmap, 0x1008, 0x20); diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c index ad46c4014a40..6fd8666813a8 100644 --- a/drivers/clk/qcom/videocc-sm8250.c +++ b/drivers/clk/qcom/videocc-sm8250.c @@ -383,9 +383,9 @@ static int video_cc_sm8250_probe(struct platform_device *pdev) clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config); - /* Keep VIDEO_CC_AHB_CLK and VIDEO_CC_XO_CLK ALWAYS-ON */ - regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0xe58); /* VIDEO_CC_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0xeec); /* VIDEO_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap); diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-sm8350.c index 7246f3c99492..002e4c0666fa 100644 --- a/drivers/clk/qcom/videocc-sm8350.c +++ b/drivers/clk/qcom/videocc-sm8350.c @@ -558,13 +558,9 @@ static int video_cc_sm8350_probe(struct platform_device *pdev) clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config); - /* - * Keep clocks always enabled: - * video_cc_ahb_clk - * video_cc_xo_clk - */ - regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); - regmap_update_bits(regmap, video_cc_xo_clk_cbcr, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0xe58); /* VIDEO_CC_AHB_CLK */ + qcom_branch_set_clk_en(regmap, video_cc_xo_clk_cbcr); /* VIDEO_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap); pm_runtime_put(&pdev->dev); diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c index 16a61146e619..045eee07ea5f 100644 --- a/drivers/clk/qcom/videocc-sm8450.c +++ b/drivers/clk/qcom/videocc-sm8450.c @@ -423,15 +423,10 @@ static int video_cc_sm8450_probe(struct platform_device *pdev) clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); - /* - * Keep clocks always enabled: - * video_cc_ahb_clk - * video_cc_sleep_clk - * video_cc_xo_clk - */ - regmap_update_bits(regmap, 0x80e4, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x8130, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x8114, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x80e4); /* VIDEO_CC_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x8130); /* VIDEO_CC_SLEEP_CLK */ + qcom_branch_set_clk_en(regmap, 0x8114); /* VIDEO_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &video_cc_sm8450_desc, regmap); diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c index f3c9dfaee968..fa81e48f83e7 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -428,15 +428,10 @@ static int video_cc_sm8550_probe(struct platform_device *pdev) clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); - /* - * Keep clocks always enabled: - * video_cc_ahb_clk - * video_cc_sleep_clk - * video_cc_xo_clk - */ - regmap_update_bits(regmap, 0x80f4, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x8140, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x8124, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x80f4); /* VIDEO_CC_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x8140); /* VIDEO_CC_SLEEP_CLK */ + qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap); From patchwork Wed Jan 3 13:36:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 759916 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 352121A5A4 for ; Wed, 3 Jan 2024 13:37:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="AjThiLTV" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-a275b3a1167so587057366b.3 for ; Wed, 03 Jan 2024 05:37:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704289024; x=1704893824; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=6Cgup25mFBqNvuEmoK7puNS/TKkyMwPWWdoAoEKxYzo=; b=AjThiLTVWHNLbp2CAFBKbigl8QNqkavcMnuXXZTrLgCL0qDHeh9UQtx8bz/kBVMTQO 4Vphj6G0ddMryVpr3hqXiZnEIaisyNy3dQOu2rmfNNcpotvL89dn6K3bggoBT65c0EqV f9mWnZCsZiDJKh0Hse6zcLihwlVg6Qygm6hvKp4EA8NEVHu2wfdKiAbeqLPXl70ilOH3 qPhZZbLa3pw255YGjZapZ+dZRfnRBANbFz9SDt4I3k7ICpg3TsM8rCJBXj9BDKWHXXBe mFSK6+Tr404IcT/Vg+40uhXqBGpY3GEbFLf3lmR1/DXniaqJv2oqjqrgR/Al8kqwnEiK XaJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704289024; x=1704893824; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6Cgup25mFBqNvuEmoK7puNS/TKkyMwPWWdoAoEKxYzo=; b=J5+a/KE/dZfAvEjbrP42uw1UC6dz5cMQbJA2JOPdYE8VdR0jiOYatiqCnHU5/4qhNL 84gNLvcilhEYsFl/QN8iRXssaBIvQ71XktAq4M6lGpRNm3fYD/r28RSrY6ZDlgOtjmqM Hn7pOv14K5+Xrq8Rv8DpTmn1fncMXXFX0id+8POEkgoOxuO6JHBxlg7z7yLG0YY7vCPo 1ASFaA4odbaWRoMcZknu9drUoJ8LpWEvNTkpzratJREPDHUVojHXg+wR3O2Ce3A+7qi+ 6B5ITFBwxQTxnickkZ/dK3g+cfv9Uy6MG5sdYaY1D/i200OiaXNhNCRUZ5DFPot5wxXU N1Gw== X-Gm-Message-State: AOJu0Yw426igvn7n9KiVutU+BuR5dTJ6gj1A9nR5qNG/9tFvN9nHMQ+J 0n6a+avOrizhsrvf9Cshd1LwPairKjG8Cg== X-Google-Smtp-Source: AGHT+IEbR2tyIwQC3zP+G6fGrzknH/hAJWI8LwNxraVJWFP4Ry4ozbxFPXmme1HJ2bhCAkieOEYICg== X-Received: by 2002:a17:906:f84d:b0:a28:b183:a637 with SMTP id ks13-20020a170906f84d00b00a28b183a637mr140943ejb.40.1704289024523; Wed, 03 Jan 2024 05:37:04 -0800 (PST) Received: from [10.167.154.1] (178235179036.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.36]) by smtp.gmail.com with ESMTPSA id cl2-20020a170906c4c200b00a275637e699sm6474351ejb.166.2024.01.03.05.37.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:37:04 -0800 (PST) From: Konrad Dybcio Date: Wed, 03 Jan 2024 14:36:01 +0100 Subject: [PATCH v5 03/12] clk: qcom: gcc-sm6375: Unregister critical clocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v5-3-99942e6bf1ba@linaro.org> References: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704289018; l=6876; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=QwZrer5hUrufa1cwj4h/mbEbY79jEsGECy877LaHpmw=; b=D95hVpbcxSRFv1dTl4UGZfPZaL65U/LzTU8npnpJhInPhhYfw9F6nS0ZIzMYMMh+F6MKU2INC n0DXjK+nCGxBj4MU2GV1fypWXhkF1Y/5JxAfC1w7o0FktJuBgqzgEi/ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm6375.c | 94 +++---------------------------------------- 1 file changed, 5 insertions(+), 89 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c index 84639d5b89bf..a20fc07c5af3 100644 --- a/drivers/clk/qcom/gcc-sm6375.c +++ b/drivers/clk/qcom/gcc-sm6375.c @@ -1743,22 +1743,6 @@ static struct clk_branch gcc_cam_throttle_rt_clk = { }, }; -static struct clk_branch gcc_camera_ahb_clk = { - .halt_reg = 0x17008, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0x17008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x17008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_camss_axi_clk = { .halt_reg = 0x58044, .halt_check = BRANCH_HALT, @@ -2309,22 +2293,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { }, }; -static struct clk_branch gcc_disp_ahb_clk = { - .halt_reg = 0x1700c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x1700c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x1700c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_regmap_div gcc_disp_gpll0_clk_src = { .reg = 0x17058, .shift = 0, @@ -2455,22 +2423,6 @@ static struct clk_branch gcc_gp3_clk = { }, }; -static struct clk_branch gcc_gpu_cfg_ahb_clk = { - .halt_reg = 0x36004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x36004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x36004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_cfg_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gpu_gpll0_clk_src = { .halt_check = BRANCH_HALT_DELAY, .clkr = { @@ -3094,26 +3046,6 @@ static struct clk_branch gcc_sdcc2_apps_clk = { }, }; -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { - .halt_reg = 0x2b06c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x2b06c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x79004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sys_noc_cpuss_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { .halt_reg = 0x45098, .halt_check = BRANCH_HALT, @@ -3433,22 +3365,6 @@ static struct clk_branch gcc_venus_ctl_axi_clk = { }, }; -static struct clk_branch gcc_video_ahb_clk = { - .halt_reg = 0x17004, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0x17004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x17004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_video_axi0_clk = { .halt_reg = 0x1701c, .halt_check = BRANCH_HALT_VOTED, @@ -3615,7 +3531,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, - [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, @@ -3671,7 +3586,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr, - [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, @@ -3683,7 +3597,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, @@ -3739,7 +3652,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, @@ -3766,7 +3678,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, - [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, @@ -3886,6 +3797,11 @@ static int gcc_sm6375_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */ qcom_branch_set_clk_en(regmap, 0x2b004); /* GCC_CPUSS_GNOC_CLK */ qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x17008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1700c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x79004); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x17004); /* GCC_VIDEO_AHB_CLK */ clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config); clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config); From patchwork Wed Jan 3 13:36:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 759915 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7ED5A1A5BB for ; Wed, 3 Jan 2024 13:37:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="PeVT9nCL" Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-555aa7fd668so4892690a12.0 for ; Wed, 03 Jan 2024 05:37:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704289026; x=1704893826; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Yq1JGC68uTd3cPMS7VFU/4ZnPLni1wHoKXEP4mEYH+A=; b=PeVT9nCLH1khJbkYP+c+CYw5YfvNtBu0iEfoEnuXCAoVKrscSHWbPXStIoOF8rWrUJ VIOct8cMRpgFcA8yiS4oK5Cqbl0kkHk4utulCgEoUH2FjQloW4vUfIE47/IR+ph3RTtK 1it3nEkt4PVHgkZ56wvaJJes7rNaV7Xd7tAU1G3GPT/vHqv1R8NBTZMGfZcJWsE8xK5h YybT5lFNQPI6YYSGlGEIGFZv4ahUAHoTqhAzNHNPZJmI7sCMHctRxm4+6ouPUPJJAGfm JcxLxFZrogOatrWZQckQtwuTLRVGqEyhS8Fl9LtEcUdCpaM68ar7v3wkBGP3cgrFzJg4 56Bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704289026; x=1704893826; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Yq1JGC68uTd3cPMS7VFU/4ZnPLni1wHoKXEP4mEYH+A=; b=VztoIA13ACh241WNDzx1Sb5MXqELef9vK8BifY7HLEIlntNeqw3Y76qekLxaiTuk9c qLtDuVyXo+cLSn4HTeKxg6dMmQQtwSkmePwEq6RmSgD1a4lQDds9ZwQ6WNAltwoJazxh DOhkUXqNrowV7djLw0Ip0/h5QrC/O40foTNXZGAfndzyOiRyyUPZjaaZb2NK3UNvpa2z Jkmmg9UOiLDZk2KiXtZqEnGOKGg35tOm25LAxLyvhahAv1kL7UIhyc1Ipg9glru96EfF tRii8so8LKjMEAF3x5ysyeRoStYknpBnxs98cKqQYtnaLYHpsFdo18O1ijfYGxomKIPp /BTA== X-Gm-Message-State: AOJu0YzQG8+X2GFnm7wkvNQlEqnKNwlJkewk7ueKpd6sPONLSNLluq2a O9kbK1PNfovLrzpLJJSklMybuOmnvWqSFg== X-Google-Smtp-Source: AGHT+IGZY+EXGbVD9tTFe7R1bRK9SLf68p64TnkgQFK8XUyK3z3eTgulvxsqwSqXe/3lBezuM2n3pQ== X-Received: by 2002:a17:906:6952:b0:a28:a01:ee92 with SMTP id c18-20020a170906695200b00a280a01ee92mr2120619ejs.36.1704289025971; Wed, 03 Jan 2024 05:37:05 -0800 (PST) Received: from [10.167.154.1] (178235179036.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.36]) by smtp.gmail.com with ESMTPSA id cl2-20020a170906c4c200b00a275637e699sm6474351ejb.166.2024.01.03.05.37.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:37:05 -0800 (PST) From: Konrad Dybcio Date: Wed, 03 Jan 2024 14:36:02 +0100 Subject: [PATCH v5 04/12] clk: qcom: gpucc-sm6375: Unregister critical clocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v5-4-99942e6bf1ba@linaro.org> References: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Bryan O'Donoghue X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704289018; l=3066; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=GHhudpM9IAN/Lc38xFu1FTckBvfyQEfeLWFuAx9ceqc=; b=h//62tjk6Hx8GrQUJmei/DxNFmIbbfRVZKURbysVBxVyeHMJyfQFBjgjrNv2jR4Zg0Ug2KwY/ eZnlvruiNbTD7Ra4hNdqgmrp+1yALlDuFEdWW+HcvIfV7iTYhMJW6F6 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Reviewed-by: Bryan O'Donoghue Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm6375.c | 34 ++++------------------------------ 1 file changed, 4 insertions(+), 30 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm6375.c index da24276a018e..07ebe5e139d5 100644 --- a/drivers/clk/qcom/gpucc-sm6375.c +++ b/drivers/clk/qcom/gpucc-sm6375.c @@ -183,20 +183,6 @@ static struct clk_rcg2 gpucc_gx_gfx3d_clk_src = { }, }; -static struct clk_branch gpucc_ahb_clk = { - .halt_reg = 0x1078, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x1078, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpucc_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpucc_cx_gfx3d_clk = { .halt_reg = 0x10a4, .halt_check = BRANCH_HALT_DELAY, @@ -294,20 +280,6 @@ static struct clk_branch gpucc_cxo_clk = { }, }; -static struct clk_branch gpucc_gx_cxo_clk = { - .halt_reg = 0x1060, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x1060, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpucc_gx_cxo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpucc_gx_gfx3d_clk = { .halt_reg = 0x1054, .halt_check = BRANCH_HALT_DELAY, @@ -381,7 +353,6 @@ static struct gdsc gpu_gx_gdsc = { }; static struct clk_regmap *gpucc_sm6375_clocks[] = { - [GPU_CC_AHB_CLK] = &gpucc_ahb_clk.clkr, [GPU_CC_CX_GFX3D_CLK] = &gpucc_cx_gfx3d_clk.clkr, [GPU_CC_CX_GFX3D_SLV_CLK] = &gpucc_cx_gfx3d_slv_clk.clkr, [GPU_CC_CX_GMU_CLK] = &gpucc_cx_gmu_clk.clkr, @@ -389,7 +360,6 @@ static struct clk_regmap *gpucc_sm6375_clocks[] = { [GPU_CC_CXO_AON_CLK] = &gpucc_cxo_aon_clk.clkr, [GPU_CC_CXO_CLK] = &gpucc_cxo_clk.clkr, [GPU_CC_GMU_CLK_SRC] = &gpucc_gmu_clk_src.clkr, - [GPU_CC_GX_CXO_CLK] = &gpucc_gx_cxo_clk.clkr, [GPU_CC_GX_GFX3D_CLK] = &gpucc_gx_gfx3d_clk.clkr, [GPU_CC_GX_GFX3D_CLK_SRC] = &gpucc_gx_gfx3d_clk_src.clkr, [GPU_CC_GX_GMU_CLK] = &gpucc_gx_gmu_clk.clkr, @@ -455,6 +425,10 @@ static int gpucc_sm6375_probe(struct platform_device *pdev) clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config); clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x1078); /* GPUCC_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1060); /* GPUCC_GX_CXO_CLK */ + ret = qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap); pm_runtime_put(&pdev->dev); From patchwork Wed Jan 3 13:36:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 759673 Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44A251A731 for ; Wed, 3 Jan 2024 13:37:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="DT5Upm+q" Received: by mail-ed1-f46.google.com with SMTP id 4fb4d7f45d1cf-555144cd330so8118572a12.2 for ; Wed, 03 Jan 2024 05:37:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704289027; x=1704893827; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3nZ/FgD+oGFs2Rc41jcok1cEWb2G/4+bAmbkMjU4FYc=; b=DT5Upm+q4fb03UtIN+T+SNVxdcnHJ+P0EXasNj7CBo7FelwyrH+V8Cpkzkf5GzdJnQ oBq7f+GDrjU/srQul+OUiR0SQ9dM0AhZiMIe2TPkyLtwFDt6cOTixAv1se8/MiXJPE1G xWwY/6QTE3R7bC52vhrjuqZl3LKCo+yOXMjMyumXvluRI1kMiBvz5b0vRFp+h6uXMahA ok/n14nf09KqqvEFrlt7O1H0JDmAkuuUafcIXLpwPZdNzavUYjOOKzsVEuChKrYcE4wY KcloXulLtvHhsgbLdNtkQifaPMYgo7Vpze+0tKKm0W+KjKve2jnfoHBoqQaaCHWt4/ET ittQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704289027; x=1704893827; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3nZ/FgD+oGFs2Rc41jcok1cEWb2G/4+bAmbkMjU4FYc=; b=WyX7yufgETV1DoXRt97AgFD8cRTUDhKgUBdq6/Hg1ao8rtRuO//kbeGgFilGsLPbJa XQPunuBOd107MADtlg/RhR4T8/C1FCNqgte3zZIU3v23esg/mVULMoMfTHUsQDT/0qvp NBEkNPycmn0wmMi6AqNOhy8WWVJYW76UUDb7Msp98CIGEGm5HNr0vSwTn9zCjbjCz9pT 7EEvQw2Z4Kibz1qpgwGfJPNf8ZvBtvGhEhhOUJmEeIM19l53voyGBzh3CQuk0BysqAmT w4cQmWyxw2yEjt/SoW11Kl8rw072oermJfx/XTH7+qjctv1Z6PTk8JK9z9J+RQcIr58w kbKg== X-Gm-Message-State: AOJu0Yz+/mh9nd0We4ijMGOV0s++Ycra1q7YtT59un7A7osW7lZT0JjY cPWr+CNZ2ZJUxkS3Hgk6txSWMp1JnYnJ2A== X-Google-Smtp-Source: AGHT+IFCmlo3/fRMDs6alAryIWIgMCXX96y6EO1Hhto50Cylu50WTQZpRA7qOqWfLtuBhGEEI91lYg== X-Received: by 2002:a17:906:749c:b0:a28:b830:fadb with SMTP id e28-20020a170906749c00b00a28b830fadbmr40327ejl.138.1704289027594; Wed, 03 Jan 2024 05:37:07 -0800 (PST) Received: from [10.167.154.1] (178235179036.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.36]) by smtp.gmail.com with ESMTPSA id cl2-20020a170906c4c200b00a275637e699sm6474351ejb.166.2024.01.03.05.37.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:37:07 -0800 (PST) From: Konrad Dybcio Date: Wed, 03 Jan 2024 14:36:03 +0100 Subject: [PATCH v5 05/12] clk: qcom: gpucc-sm6115: Unregister critical clocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v5-5-99942e6bf1ba@linaro.org> References: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704289018; l=2984; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=RdTke+2ukdWoXFZFASghqIHvc/0hMwv913x8iK/xxg0=; b=dXVz4LRN6Bw17VJpQ9OlKaq0pWQc2XGhDtXwPAqkQPsof0NdqZqmUkkKuu6wZ32HE09YtQGTq PKOxeZiDiGaAYdZBERGVoImw4O1fUZ/+I4n8mu+HP6dx1R1WxVNBDOb X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm6115.c | 34 ++++------------------------------ 1 file changed, 4 insertions(+), 30 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm6115.c index fb71c21c9a89..2c2c184747b1 100644 --- a/drivers/clk/qcom/gpucc-sm6115.c +++ b/drivers/clk/qcom/gpucc-sm6115.c @@ -234,20 +234,6 @@ static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { }, }; -static struct clk_branch gpu_cc_ahb_clk = { - .halt_reg = 0x1078, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x1078, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpu_cc_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpu_cc_crc_ahb_clk = { .halt_reg = 0x107c, .halt_check = BRANCH_HALT_DELAY, @@ -336,20 +322,6 @@ static struct clk_branch gpu_cc_cxo_clk = { }, }; -static struct clk_branch gpu_cc_gx_cxo_clk = { - .halt_reg = 0x1060, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x1060, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpu_cc_gx_cxo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpu_cc_gx_gfx3d_clk = { .halt_reg = 0x1054, .halt_check = BRANCH_HALT_SKIP, @@ -418,7 +390,6 @@ static struct gdsc gpu_gx_gdsc = { }; static struct clk_regmap *gpu_cc_sm6115_clocks[] = { - [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, @@ -426,7 +397,6 @@ static struct clk_regmap *gpu_cc_sm6115_clocks[] = { [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, - [GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr, [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, @@ -488,6 +458,10 @@ static int gpu_cc_sm6115_probe(struct platform_device *pdev) qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true); qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x1078); /* GPU_CC_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1060); /* GPU_CC_GX_CXO_CLK */ + return qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap); } From patchwork Wed Jan 3 13:36:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 759914 Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E6A81B296 for ; Wed, 3 Jan 2024 13:37:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="MDQLzVAv" Received: by mail-ed1-f44.google.com with SMTP id 4fb4d7f45d1cf-556c3f0d6c5so836131a12.2 for ; Wed, 03 Jan 2024 05:37:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704289029; x=1704893829; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=04GA/gYikhVm70mp04BE89vJbyB+HCgNcamoEcplm6o=; b=MDQLzVAvbHFQdNCFz1L7tuuslY0vfAbjeAqMx1ux/E07ieqegX3aX/KiyXEbSdiVc4 1n37A9ielzv2JaxluXcR+QVovJTkQsIceQoSPuEi8CeyfQGRZQmY0rNcuOY61GHbCxnO cl+we3mbQ9I0RFfiONWDDouqyV135Fj1AmSbfBtpDmKJXrcy/LLdB3RjP+xqypjWMvUA vJ5GQX0ziMcXZloc6PJsKc/B5EmOyUa+PSWHP244++7EQbPzfQapMCwub4dA72QR8Hps XsAE7gVs7T5VKCGhb+Xl8aG+mj/7EQlhQ//6kW9sFfyfQkGE7rcYWwOng11pGCLhw8bq FkqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704289029; x=1704893829; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=04GA/gYikhVm70mp04BE89vJbyB+HCgNcamoEcplm6o=; b=QP55CoA3OE3h1eWE6Gtk2XWfGMF2pEAdy8UyU8nTk1JsOaCFZPGe5IJDHK4zZYCP6k C3BdatnDGKLaBlYtVcmbarTU4Tey3vXOKqRzyV1NwZLc4kj6eq63S/d5nexD3cHkEEX+ b46BWwKzvUvAC6jE9K7IowzTRSxep/5YcezqG+xLFi2aOQYmtddA/sFqNKGNHijSb+n+ jrvO6y6Y6CVtIdkxNqipF07uaoYFtgRahcGtzlJz+szdhsKjWl3FzO9ktv6UrwysdT3f J7aIWGOvBGYR3t/8fIMhdzJfG/OTBhoocD/bFYywsN2XYjWaZ39FIZh9v5QhKnJVtw7o 0nag== X-Gm-Message-State: AOJu0YzJ0lk3kZ9FzN5yczIxjWjO+FoqzPf+t98egIScwR6yCg4clTXy /X9DXrUys69eEq9lpoQrvUQslBUPLlK18g== X-Google-Smtp-Source: AGHT+IFV0w31rqoLt9vSqzh0T6ScG8iYjN75jF53jvf4lVP/qavgZouRKDWwmFjf6Ct7fztt3EZKvQ== X-Received: by 2002:a17:906:ca92:b0:a27:cfe3:f8a2 with SMTP id js18-20020a170906ca9200b00a27cfe3f8a2mr1397262ejb.10.1704289029005; Wed, 03 Jan 2024 05:37:09 -0800 (PST) Received: from [10.167.154.1] (178235179036.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.36]) by smtp.gmail.com with ESMTPSA id cl2-20020a170906c4c200b00a275637e699sm6474351ejb.166.2024.01.03.05.37.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:37:08 -0800 (PST) From: Konrad Dybcio Date: Wed, 03 Jan 2024 14:36:04 +0100 Subject: [PATCH v5 06/12] clk: qcom: gpucc-sm6115: Add runtime PM Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v5-6-99942e6bf1ba@linaro.org> References: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704289018; l=1935; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=alZr67bLnwqb3yV+3Ojldc2X/6n9g3vN6yGz8GMYLR4=; b=VY7iX087OYTjgUsb+T75Ntm60WeEZ1+WIw8ho4GUgfty/ZLYMyBtOaINhNMPFhEuD4ZGYVP3a TVoTNQ7Z4GyBx10tIKAJXiQHwDRSDs6YBPV/Y6x3T7mc2nRrjlDVpFR X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The GPU_CC block on SM6115 is powered by the VDD_CX rail. We only need to cast an enable vote for it if the GPU blocks are in use. Enable runtime PM to keep the power flowing only when necessary. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm6115.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm6115.c index 2c2c184747b1..15cf5d63c9ad 100644 --- a/drivers/clk/qcom/gpucc-sm6115.c +++ b/drivers/clk/qcom/gpucc-sm6115.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -443,10 +444,21 @@ MODULE_DEVICE_TABLE(of, gpu_cc_sm6115_match_table); static int gpu_cc_sm6115_probe(struct platform_device *pdev) { struct regmap *regmap; + int ret; + + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; regmap = qcom_cc_map(pdev, &gpu_cc_sm6115_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } clk_alpha_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_alpha_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); @@ -462,7 +474,10 @@ static int gpu_cc_sm6115_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x1078); /* GPU_CC_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0x1060); /* GPU_CC_GX_CXO_CLK */ - return qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap); + ret = qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap); + pm_runtime_put(&pdev->dev); + + return ret; } static struct platform_driver gpu_cc_sm6115_driver = { From patchwork Wed Jan 3 13:36:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 759672 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20AF81BDDC for ; Wed, 3 Jan 2024 13:37:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="koVpEgDH" Received: by mail-ej1-f49.google.com with SMTP id a640c23a62f3a-a1915034144so1186340966b.0 for ; Wed, 03 Jan 2024 05:37:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704289030; x=1704893830; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=e1jopfAGdfe1hjjbTajwNyBuWaTVCIyoa2pimuhzPf8=; b=koVpEgDHe4C/mmRlIcUGJ7A0FTJZXBih24BKoAYkykFWmk6PsgGDWRNeD6GT5NNZcK s5kkS1N4Mj17yiKnrhIHFxy4dQgz6dMyVl5gjv95PF78W2nKcNiUzvZBRbAJwYJswkI+ z3t6PO2NvJr/pUaU21p4AykGu+uXzHXlb9BZAsYE85u8lbOYTXJ90NHZXPCrrUAiLDvj RsotXHA7YGMqyII0DZE3GpNeaob17UVLBkTBT07b4DHkDdhgVpnc6TxOWayWROa3W576 kgWsdsMhBehR10WsIqOVxfhIjvPv+lIi8uI7EZbL+39190KvzPNgo3nXtegMBnqXUoKD EXTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704289030; x=1704893830; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e1jopfAGdfe1hjjbTajwNyBuWaTVCIyoa2pimuhzPf8=; b=mCrePrD6vCfo5j46ZH9wrx3S9xrx03rInmo6i4VZf+/kAzVCb0YuUokLII8jRr95+X VPSm/pHdahO66cgVUDb4cu9OgD1neNHzqocZatGYYbsRdwMHQAuCP3ITr63xR/t0XIw/ sddJtWYVxiGX4Sg6AuKwnHFZx2Pbcg2CwrP6zc3qeJEjH11Wu84lRPJeCiFuPUwK6Nb0 cR9ZirhUsSIp+ei2HJ/CcxGNyMvrfgBCxsV1XSK3y4vEkQXRIVD33LUqscnQeBr4Nzhh akf53DKUBO+Nfc4kcVJ4YyPOM6OQ6r0QrLqnBktlzlAb64JfhTJmwBNs7Pk9nnKXN4cJ flEg== X-Gm-Message-State: AOJu0YyrLua9Z9Ca9pq8i78ZHZCVP3bpB5CTujdElQ42AaA9B8uB5X6j s8hLx1tTZcebO3j8TmKlSSENYiCG+pCQig== X-Google-Smtp-Source: AGHT+IG/DINJE/6VlhUirr/8wk5v44a5KZyToxGrHwomTnCJISJ3ekOBWYvbswqutU47rdgH/ryZvQ== X-Received: by 2002:a17:906:a186:b0:a26:9113:4c52 with SMTP id s6-20020a170906a18600b00a2691134c52mr9028745ejy.32.1704289030558; Wed, 03 Jan 2024 05:37:10 -0800 (PST) Received: from [10.167.154.1] (178235179036.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.36]) by smtp.gmail.com with ESMTPSA id cl2-20020a170906c4c200b00a275637e699sm6474351ejb.166.2024.01.03.05.37.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:37:10 -0800 (PST) From: Konrad Dybcio Date: Wed, 03 Jan 2024 14:36:05 +0100 Subject: [PATCH v5 07/12] clk: qcom: gcc-sm6115: Unregister critical clocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v5-7-99942e6bf1ba@linaro.org> References: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704289018; l=7187; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=BGPRFI1v4i7Cy9f0RwThogxUuQIjnVpQUX8HZwceY5k=; b=zVQDXcGfZIkLYk/d+FKxQmKW0pJ1KteAKEy84N3bGlp7ZW61LS7zGhMhZdxep/wMroMl4PcZY rwI8AdLcQm9B7GCr2BrpAgxLGKYeHxQkSAm7k8K+DgdCMB4eTiVdpoW X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm6115.c | 124 +++--------------------------------------- 1 file changed, 9 insertions(+), 115 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c index 13e521cd4259..2880d48c9bc0 100644 --- a/drivers/clk/qcom/gcc-sm6115.c +++ b/drivers/clk/qcom/gcc-sm6115.c @@ -1586,36 +1586,6 @@ static struct clk_branch gcc_cam_throttle_rt_clk = { }, }; -static struct clk_branch gcc_camera_ahb_clk = { - .halt_reg = 0x17008, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0x17008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x17008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_xo_clk = { - .halt_reg = 0x17028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x17028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_camss_axi_clk = { .halt_reg = 0x58044, .halt_check = BRANCH_HALT, @@ -2124,38 +2094,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { }, }; -static struct clk_branch gcc_cpuss_gnoc_clk = { - .halt_reg = 0x2b004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x2b004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x79004, - .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_gnoc_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_ahb_clk = { - .halt_reg = 0x1700c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x1700c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x1700c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_regmap_div gcc_disp_gpll0_clk_src = { .reg = 0x17058, .shift = 0, @@ -2215,20 +2153,6 @@ static struct clk_branch gcc_disp_throttle_core_clk = { }, }; -static struct clk_branch gcc_disp_xo_clk = { - .halt_reg = 0x1702c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1702c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gp1_clk = { .halt_reg = 0x4d000, .halt_check = BRANCH_HALT, @@ -2283,22 +2207,6 @@ static struct clk_branch gcc_gp3_clk = { }, }; -static struct clk_branch gcc_gpu_cfg_ahb_clk = { - .halt_reg = 0x36004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x36004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x36004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_cfg_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gpu_gpll0_clk_src = { .halt_check = BRANCH_HALT_DELAY, .clkr = { @@ -2771,22 +2679,6 @@ static struct clk_branch gcc_sdcc2_apps_clk = { }, }; -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { - .halt_reg = 0x2b06c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x2b06c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x79004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sys_noc_cpuss_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { .halt_reg = 0x45098, .halt_check = BRANCH_HALT, @@ -3272,8 +3164,6 @@ static struct clk_regmap *gcc_sm6115_clocks[] = { [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, - [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, - [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr, @@ -3322,20 +3212,16 @@ static struct clk_regmap *gcc_sm6115_clocks[] = { [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, - [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, - [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, - [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, @@ -3376,7 +3262,6 @@ static struct clk_regmap *gcc_sm6115_clocks[] = { [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, @@ -3513,6 +3398,15 @@ static int gcc_sm6115_probe(struct platform_device *pdev) clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config); clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x17008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x2b004); /* GCC_CPUSS_GNOC_CLK */ + qcom_branch_set_clk_en(regmap, 0x1700c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x2b06c); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap); } From patchwork Wed Jan 3 13:36:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 759913 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBA841B286 for ; Wed, 3 Jan 2024 13:37:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zb3jTgtH" Received: by mail-ej1-f52.google.com with SMTP id a640c23a62f3a-a2345aaeb05so1084531566b.0 for ; Wed, 03 Jan 2024 05:37:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704289032; x=1704893832; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=CB6wboZIYsl99NW7ZpENCmNA/cZy6QRen2wbuMMkSvc=; b=zb3jTgtHT7NEq5DsqnBjIzlESY2ELoWRl6I+m014Hodly7YrbsVH3ErEaO74XBBLJv R4Yw2K2WEE2usPyWjbVI/U/CZYdr1zmUeq7oINS18VGVuZ/ec/8IlV0pL/ojbf6a2zhe aQjbnb2LpYA38m+4dYwtiEQ0w1R7SD9b/9Ko33qxxe5nnqe1P4P8nGCcskli5Pi/EaoZ Gt5xR35Gv9p1c9SG/IL+GJm5VI76qQ/AFWYGHVjDG8TXmEbXbBz9dsDhlgyu02/tJ3+1 VN5a9sOiHTfz/SDsX0kfARqk65bRaY7JaaDoMQQky4JlOSw43R+DY0TXrFPXQk58VgWh ZopQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704289032; x=1704893832; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CB6wboZIYsl99NW7ZpENCmNA/cZy6QRen2wbuMMkSvc=; b=WERcDNSClcbeha3RA6gndK4vO1sCNsmyDpxkE+xK7kKGxe8czgtaw2fQo5Y9Hmxksm dD3nn14iE+A+5iFEJz3+P+RbTAsnR88rX72NZANGYmc7ACo5kZNKurvF4/b9y4GiCzSW jjQtJxZpXABw7SMrv16U4LCMdMgQSJJnZMFv/grOVPkhPyV36vg3EGPr1oJNDizsLXWk CUsYDViM9dM5ld8XCuwm42pj1Hk6vDvPN7+2NxXvPrQYwLbFqu8aDLCv+jntat0DfduG vHjYGGnuOxThOmPyoRKj2n+tfjizLO5I2q+7yAdo8EEjtb7KD2EQ1Ed4bZqzTCa2u9qr JK/A== X-Gm-Message-State: AOJu0YwpI1ccgQj6ai7pRFpuTfMNVGAfcrKKn1OlzZs2B7/WFrGilVie fjhCnAWIevuOEb9YirJ5+UQFXE35TaQVYw== X-Google-Smtp-Source: AGHT+IEpLtJxLQmL62jOOYBMHmkT/h4ijT4DDG14vEFVqHUHgp6jNzlQgJ3l5yU7DJ1pJEZjpyGrrA== X-Received: by 2002:a17:906:59b:b0:9cc:450c:b0d5 with SMTP id 27-20020a170906059b00b009cc450cb0d5mr8142503ejn.4.1704289032149; Wed, 03 Jan 2024 05:37:12 -0800 (PST) Received: from [10.167.154.1] (178235179036.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.36]) by smtp.gmail.com with ESMTPSA id cl2-20020a170906c4c200b00a275637e699sm6474351ejb.166.2024.01.03.05.37.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:37:11 -0800 (PST) From: Konrad Dybcio Date: Wed, 03 Jan 2024 14:36:06 +0100 Subject: [PATCH v5 08/12] clk: qcom: gcc-qcm2290: Unregister critical clocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v5-8-99942e6bf1ba@linaro.org> References: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704289018; l=6713; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=StIiRcseer0t+d6QEt9QWDW2dseAKGGF158KsOvOerA=; b=IWucqp1N/H1Oog9EmPW/QTilhhHFeSTCyZm5hk1Tm9H36sdaqvByR8sHM+34bLsGXosteOWLS hLZCVTaWrkECsmnMRdl7X+e85e9dm7gagqC1Zim24GHkNT0qy9yigS+ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-qcm2290.c | 106 ++++------------------------------------- 1 file changed, 8 insertions(+), 98 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcm2290.c b/drivers/clk/qcom/gcc-qcm2290.c index 48995e50c6bd..ab281f0d5114 100644 --- a/drivers/clk/qcom/gcc-qcm2290.c +++ b/drivers/clk/qcom/gcc-qcm2290.c @@ -1397,36 +1397,6 @@ static struct clk_branch gcc_cam_throttle_rt_clk = { }, }; -static struct clk_branch gcc_camera_ahb_clk = { - .halt_reg = 0x17008, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0x17008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x17008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_xo_clk = { - .halt_reg = 0x17028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x17028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_camss_axi_clk = { .halt_reg = 0x58044, .halt_check = BRANCH_HALT, @@ -1825,22 +1795,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { }, }; -static struct clk_branch gcc_disp_ahb_clk = { - .halt_reg = 0x1700c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x1700c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x1700c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_regmap_div gcc_disp_gpll0_clk_src = { .reg = 0x17058, .shift = 0, @@ -1899,20 +1853,6 @@ static struct clk_branch gcc_disp_throttle_core_clk = { }, }; -static struct clk_branch gcc_disp_xo_clk = { - .halt_reg = 0x1702c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1702c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gp1_clk = { .halt_reg = 0x4d000, .halt_check = BRANCH_HALT, @@ -1964,22 +1904,6 @@ static struct clk_branch gcc_gp3_clk = { }, }; -static struct clk_branch gcc_gpu_cfg_ahb_clk = { - .halt_reg = 0x36004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x36004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x36004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_cfg_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gpu_gpll0_clk_src = { .halt_check = BRANCH_HALT_DELAY, .clkr = { @@ -2439,22 +2363,6 @@ static struct clk_branch gcc_sdcc2_apps_clk = { }, }; -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { - .halt_reg = 0x2b06c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x2b06c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x79004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sys_noc_cpuss_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { .halt_reg = 0x1a080, .halt_check = BRANCH_HALT, @@ -2774,8 +2682,6 @@ static struct clk_regmap *gcc_qcm2290_clocks[] = { [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, - [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, - [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr, @@ -2816,19 +2722,16 @@ static struct clk_regmap *gcc_qcm2290_clocks[] = { [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, - [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, - [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, @@ -2869,7 +2772,6 @@ static struct clk_regmap *gcc_qcm2290_clocks[] = { [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, @@ -2994,6 +2896,14 @@ static int gcc_qcm2290_probe(struct platform_device *pdev) clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x17008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x1700c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x2b06c); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + return qcom_cc_really_probe(pdev, &gcc_qcm2290_desc, regmap); } From patchwork Wed Jan 3 13:36:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 759912 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6BD51C6B9 for ; Wed, 3 Jan 2024 13:37:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="QGcMzbmU" Received: by mail-ej1-f52.google.com with SMTP id a640c23a62f3a-a235eb41251so1177969166b.3 for ; Wed, 03 Jan 2024 05:37:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704289033; x=1704893833; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+ls2aUMbVxdc/7lozE+p30ZeM7lcweE8oneLXZx5wYg=; b=QGcMzbmUacsSd58oRUd4e21k/4GGq4MGKovvAHEw+pT6UmmgXuzd9Qpr2A74YoCfxE MB4pEQY22AYJzi0xHPqlgmJrZvBMG0d97fhlgjnOD0dLK5fVYNlZ3gjvQClKbslmJBB/ QlIuogEl0vzAgMXW9sY7mGmXK0rzi0xpcM+0De4M0JbIMQ3jHCHzIRcVZXhP1sIarbo4 RArVFBEQOPfbAZ8QbjD9exYj62Off0dIWbvIXXYexa+IIrIIi2MPHVGyXgrCI96H0iG8 neQKKzsBbhPM1SpLGTKxrd92Xon0HUdfqZ+J2gKVeF67XObkTJHNDRgvl29cXNtY+Tuq pbNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704289033; x=1704893833; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+ls2aUMbVxdc/7lozE+p30ZeM7lcweE8oneLXZx5wYg=; b=fijjrEHryeApiOuLj138uKKJsd+bu0U3bLvyQoacETgvaz67P0kGpzbNnrOXYbukTF SpilW7Ox+A0A6y17qsE6YgEU+Gd0VWc8DTEBL1Njdw5aGQQDKe2vY7YuGpp5+xtLgL/K 3/YAFL/QbNFXaoOB7bivUGFf7kpV9p1o1n/po2pIJfRsZuPKvLV88YJdQ5IOQFBpiWO4 FnB/zcNmkK0cOlz+y2VyjY9/nzfczdHPmfWoUvh1ujVKCZgMmSmNB+ILHYOnMYZP4+eE PYkMBfTjw0+27Rjukk0QYB6DdbfI5ttpyZJcZ7Qhy4bPf9tHOIqEVekq0O4kg4mYbmRu iAEw== X-Gm-Message-State: AOJu0Yy2zCAfW7pFmFcr3x4U1/VBiYoB55i8q42fb8WeRAQJQa0onM9t 0gKFo6QT9dtbTE0MA2gCD37lIkuPf+fk7w== X-Google-Smtp-Source: AGHT+IGpnAm1YkMHGNwPzJ3DRXklifvsksvW4hhRlQoW6RG52YHgNlPC2VFhLZd8F74ypE9UZEQs7Q== X-Received: by 2002:a17:906:73d9:b0:a28:6e42:6798 with SMTP id n25-20020a17090673d900b00a286e426798mr597344ejl.61.1704289033363; Wed, 03 Jan 2024 05:37:13 -0800 (PST) Received: from [10.167.154.1] (178235179036.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.36]) by smtp.gmail.com with ESMTPSA id cl2-20020a170906c4c200b00a275637e699sm6474351ejb.166.2024.01.03.05.37.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:37:13 -0800 (PST) From: Konrad Dybcio Date: Wed, 03 Jan 2024 14:36:07 +0100 Subject: [PATCH v5 09/12] arm64: dts: qcom: sm6375: Add VDD_CX to GCC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v5-9-99942e6bf1ba@linaro.org> References: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704289018; l=718; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Gc/yH23ZENvzGFFViZ7/qVCV3FeiRMp+LehbPO3k6Xw=; b=Qe9/JEGcMm7CuZ8EE8ZjuJT/aV+Qlb+RHQliiaxESf2QmZB6YF37XfLxBq9aEGe+/FuC7R6I8 iJrXxfeKBTCA5pb2Gm8v0iEeVa9zxxRgRuxcAGZKOoPdvEBQQsHgnuy X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The GCC block is mainly powered by VDD_CX. Describe that. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 7ac8bf26dda3..f578d110f36b 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -954,6 +954,7 @@ gcc: clock-controller@1400000 { clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&sleep_clk>; + power-domains = <&rpmpd SM6375_VDDCX>; #power-domain-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; From patchwork Wed Jan 3 13:36:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 759671 Received: from mail-ed1-f42.google.com (mail-ed1-f42.google.com [209.85.208.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CA951C69F for ; Wed, 3 Jan 2024 13:37:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="jNkVVTy1" Received: by mail-ed1-f42.google.com with SMTP id 4fb4d7f45d1cf-5569472f775so1856108a12.2 for ; Wed, 03 Jan 2024 05:37:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704289034; x=1704893834; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=EIS8BVV6xMe2SYH6GmTY+cChP0QmWaX59VMotnHi2Jo=; b=jNkVVTy1pUwC5PLcjMZiLZUHNzvQywrH7bnD9/M8amUDELvjcMRgU/K7WTw+SoI/PD aMnrLWaJeUa3GLaYHZ+djilhpfU9L7UZ9gEE426bcU7AbXfVqxIBQoeuHJ1FJkJBtWVK euRE5xhhvW+lqetv/+7H/5ku8Gh4F+7u8AD51QdbLVofpCB+GmwDce0j/weymYsfolqO YrL1aSfQn5BjgPkcq8Wj0gQu1VHaYTvD81zH21XsM/0I4F69okJGHmgihvlIjx9Rfjrf zx5VfW9VhXZ7iGFLm5L0WuAV3aiVddnDfuYScVr6dKH99ir8EA6rHuFU+NBAj14ZHfZT uDaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704289034; x=1704893834; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EIS8BVV6xMe2SYH6GmTY+cChP0QmWaX59VMotnHi2Jo=; b=jn/KpUZhptNfRFlDmObsw2Gu7FuPy53b/j2eItgSK/hkzSgan3L20I9mABRKE4X2VH KGZVhWJRe+QHDXRTyupVMcit9qTEpcKlFJqFjEP7avZh1Q/wVlU1T7jsM2TFXkeBby08 NaigqlA+CX9zvEs1g71PParSJHqSPIKWF5iNl3vbmhLB86exW+NitN3ylSQspjjMlElK e2IBjXD3TCM1Lcmrj3/q17qJEaxepJjo0901GQ0Scy6V/laA6r/RVHi2F05cGU5DDzTc /gXrA0SuBqjhlkwCSxy3WY/KEe8F47SBLc0b9kRnl9putXglsO4nI2rAUUNuK69BSdKp A5VQ== X-Gm-Message-State: AOJu0Yy8JguaGb7z+j7/jHhhfQ6tWzrkLAYfgupoFdmQdO2yiGgSJVFE kca9AwCwKJBIYltwaPcs30KORwCXrafynQ== X-Google-Smtp-Source: AGHT+IFDazcmCrVYp6lQ2rvk/GUbOsFxa3D/rgZo7aLaPmsY9V0zaFzS2s/uI6Ck/R39fHgXfhyl3w== X-Received: by 2002:a17:906:7387:b0:a28:27cd:c1d5 with SMTP id f7-20020a170906738700b00a2827cdc1d5mr1690688ejl.105.1704289034705; Wed, 03 Jan 2024 05:37:14 -0800 (PST) Received: from [10.167.154.1] (178235179036.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.36]) by smtp.gmail.com with ESMTPSA id cl2-20020a170906c4c200b00a275637e699sm6474351ejb.166.2024.01.03.05.37.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:37:14 -0800 (PST) From: Konrad Dybcio Date: Wed, 03 Jan 2024 14:36:08 +0100 Subject: [PATCH v5 10/12] arm64: dts: qcom: qcm2290: Add VDD_CX to GCC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v5-10-99942e6bf1ba@linaro.org> References: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704289018; l=764; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=HEE3DdJ4zQzS/Foajh/2RBi9l8ssp2UwDgoH6XqPOSE=; b=zKPKX5XuwjH/UsyKzKynP4dN/j/mBdLyAXFRp+ZALR0r+r5bhyiMry3AvpjFCM/4utcE9udMs xxbMuFAyatRDG2UYQpDbnRkxBxE8ZqW5sazcwqE5tI4vhVtrUN38nkk X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The GCC block is mainly powered by VDD_CX. Describe that. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 0911fb08ed63..51b05019ee25 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -647,6 +647,7 @@ gcc: clock-controller@1400000 { reg = <0x0 0x01400000 0x0 0x1f0000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; clock-names = "bi_tcxo", "sleep_clk"; + power-domains = <&rpmpd QCM2290_VDDCX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From patchwork Wed Jan 3 13:36:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 759670 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DACDD1CA90 for ; Wed, 3 Jan 2024 13:37:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="TFm3rVEH" Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-556c3f0d6c5so836253a12.2 for ; Wed, 03 Jan 2024 05:37:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704289036; x=1704893836; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Tm7vsf6UZKbMh6cnZmrwv/W/K4dUYmjWU07UgTkkSLk=; b=TFm3rVEH6elCQhdWkUehstSb2c9bZlUrnsJ4Ocg7W+o1QhpGL20qkAqAQV584dpwoB WA7RobEUGATsd3LP8cJoYk2+Gt6YvnCOO8R3NrdyJMaLcXQGw7bX7txAioKcJJ8YJGNM ClzlpJPSpRf/ZGae+m2dd7wxnJanOYhpAULRB8Nud/jCICV26Alkvxk8HKRr0ZfyaSHS 39ynjfEPe/N8BMjxQ+hs0Rsy+O4G+158sjMlDSeBgvPNtmuxVH2Y4EMufmR7k2PBcodQ xtdNo6AvqDW2IRWpj8EAXH3RW8uo1jYGf2Za3Z+h+66P2YC6VL8puTVnKrXZP+pBKX3z CMVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704289036; x=1704893836; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tm7vsf6UZKbMh6cnZmrwv/W/K4dUYmjWU07UgTkkSLk=; b=gJ4M0MHpFI1aj9Y/b7+GX0hDlo8X43DruXhJtlzBr5NyyZB+Pfe3cPHz0env3sUXM6 ApWXsbq5Be8JM1SlEn6h2FidX9+qgib6xvWhQL4XMw3QeWF0DZfaoVDlthzGY8/h9I5N SkC47vSti0bvC+xv8CyB6mADhzgZUqo7NhFhbPMFdulHFHHB3SDEAt5vh+7VD4g7P5d0 lW9TDUHBJOahK2wfOImd3hfaIbI1ShsJhTYr8/WG2agHIllKoIqt587fmj3/HKYcBb5F uzMpAjPIEliaCwpEPLzggl7VC0ceTO2uPZk1ueIqQBBFWhKOyzhicuuS99A2pkE9RO3x uvgw== X-Gm-Message-State: AOJu0YxK9S6B3dVPcpRQDS4qd8NBwxkSqK7EGBHu0+37pBd2Scdv9Xj0 hYItSPZCijVjxt4ENEu/0F7nRJDVPacQtg== X-Google-Smtp-Source: AGHT+IGvVYI4IeESAJWHTgmEd9qDmMC6i5QwnW7ftiUW6nuXzWeikhEhvNDPxQxxzuG4vsPRteLNPw== X-Received: by 2002:a17:906:bc58:b0:a28:a552:92e2 with SMTP id s24-20020a170906bc5800b00a28a55292e2mr240000ejv.43.1704289036270; Wed, 03 Jan 2024 05:37:16 -0800 (PST) Received: from [10.167.154.1] (178235179036.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.36]) by smtp.gmail.com with ESMTPSA id cl2-20020a170906c4c200b00a275637e699sm6474351ejb.166.2024.01.03.05.37.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:37:16 -0800 (PST) From: Konrad Dybcio Date: Wed, 03 Jan 2024 14:36:09 +0100 Subject: [PATCH v5 11/12] arm64: dts: qcom: sm6115: Add VDD_CX to GCC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v5-11-99942e6bf1ba@linaro.org> References: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704289018; l=758; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=L7WLthXykOxwSCjhfTNvX8JtR2g4GIz2oFPri6fp1uU=; b=4cv1/NHGVZ3hzhfLG3uMDFV74Ryx7DGRCmW/dgacvSjY+egEtyvdqP2T0EX9S1w/GJ+BKFrop ChwsYyJteiPCwLAcu1TicJmyGGi3eqV/Jjek3Tt9m8Z+pw2OvHtzuSs X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The GCC block is mainly powered by VDD_CX. Describe that. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 160e098f1075..30b140e1cec0 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -807,6 +807,7 @@ gcc: clock-controller@1400000 { reg = <0x0 0x01400000 0x0 0x1f0000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; clock-names = "bi_tcxo", "sleep_clk"; + power-domains = <&rpmpd SM6115_VDDCX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From patchwork Wed Jan 3 13:36:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 759911 Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8007E1CF83 for ; Wed, 3 Jan 2024 13:37:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="h1ixBfMk" Received: by mail-ed1-f48.google.com with SMTP id 4fb4d7f45d1cf-55539cac143so7208822a12.0 for ; Wed, 03 Jan 2024 05:37:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704289038; x=1704893838; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=RUTCpmfzsSKDHjYlRAYYiQ/aykX/VSlVLVDx9q/aHss=; b=h1ixBfMknoaC4l+AUBd8AJxLIjHhdyqHNtr3TRY2V1hHkTm9QeSDGOvrG1GzBlZq+Q NVCTPRvFcjckYbw7Y6qRd5AoJ4ONtTKVESzq/rubsJ+DENS23TMIeAr1KGrbpqCe3Yw0 v3sW3Z/obnwJ2/V+id+HCUx1KE9Z08MaYUzqTfLd6zhT5GjX7m4NQfn3DE/ZOzhK35ei smQdQui0GNmWoXV4sodszlxVuV4gNDVT4wV6TVGPOaABi2MEYB7P68xFTYdd7u/U8NRv l4VngCj4nKauf9etSdvfoWYSBL6LGYEU1bF43kR/SmQ31yXvIM0q+5JAyUJ0BfVJsHvb eQFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704289038; x=1704893838; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RUTCpmfzsSKDHjYlRAYYiQ/aykX/VSlVLVDx9q/aHss=; b=TptA2n/s63PTnDum/SKV80dXgK1kLL8NiqqgiE7B/ELBmOcI+IdXosmzSTAFp8f703 L2XH5eYDM7yHOduz8LGuNSwahwS5JADplC33JvUaIxpZCiHtvRAVTj7YZBmge3FFZT14 CuTsK4vLRlmzk7H1RKs9d3qG8MOT/ehrfptFudebeKWRAlx3KeIGpV9Lt8JIiSq74bQ4 eI8eZHs0k4y0Y3bwFhqFelCD+6QSn/2rSSwxazxRErhJaOxUqGJaz5FQ2sTYOjce5vTB ivhO0H4yi1vGcBp/RiARLn2VHjCdmNiuekVuZ5Pv2zwL80Y3+ag47QlzAg1zbeOwNett 6f7Q== X-Gm-Message-State: AOJu0YxvYhMMTX9Jkh6tSTe1VGUoAPJUflqPwiivCuffZwOCf9sXTxXj UmUP10RQv/ek2t36h01NU+N2W+EPwf36mQ== X-Google-Smtp-Source: AGHT+IGb2r7J18V8yKKCdqerodJ+VgX/4qpTBHIyyTYZHgIVHNAnqdK32Kg08Qc9J+Leig1llChqKA== X-Received: by 2002:a17:906:1cca:b0:a26:9776:5ed8 with SMTP id i10-20020a1709061cca00b00a2697765ed8mr8882690ejh.91.1704289037859; Wed, 03 Jan 2024 05:37:17 -0800 (PST) Received: from [10.167.154.1] (178235179036.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.36]) by smtp.gmail.com with ESMTPSA id cl2-20020a170906c4c200b00a275637e699sm6474351ejb.166.2024.01.03.05.37.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:37:17 -0800 (PST) From: Konrad Dybcio Date: Wed, 03 Jan 2024 14:36:10 +0100 Subject: [PATCH v5 12/12] arm64: dts: qcom: sm6115: Add VDD_CX to GPU_CC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v5-12-99942e6bf1ba@linaro.org> References: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v5-0-99942e6bf1ba@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704289018; l=911; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=WDI26IliceRlW0YgN7X8GrPWGyVd7988pOYar0kAAss=; b=01bznyiO7SHJ7u1n+mr2x5/l72XfL8vU3ZTAqXysZ9MQBbaRmXXk4/moJBIOB2Jy+kHXEQjaM l7nr6hxPSFuDoC/YFopLpiuMznUulnRmARQvej1R6ze5B6MQZen2SfK X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The GPU_CC block is powered by VDD_CX. Link the power domain and provide a reasonable minimum vote (lowest available on the platform) to ensure the registers within are accessible. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 30b140e1cec0..ec9a74acc69c 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1723,6 +1723,8 @@ gpucc: clock-controller@5990000 { clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains = <&rpmpd SM6115_VDDCX>; + required-opps = <&rpmpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>;