From patchwork Sat Jan 6 22:39:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 760922 Received: from mail-io1-f45.google.com (mail-io1-f45.google.com [209.85.166.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A294101DB; Sat, 6 Jan 2024 22:40:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="b4uLV6oU" Received: by mail-io1-f45.google.com with SMTP id ca18e2360f4ac-7ba8e33dd0cso40709239f.0; Sat, 06 Jan 2024 14:40:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704580804; x=1705185604; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=c8cx4G027Gz6iFuAIfhaAQlzyB7pPX4ipODK9kWLrHg=; b=b4uLV6oUIW5+bjhHmJXZMwI1o19KJ0VO/PC+GzwryYc0hcBeL4pPRjGFB+lPXA8qGj pAGcXXkRWvR1XhTtCFT033Xu5mo24w571QorytCXimSv6+QqAopjZ6ldIJbpNGg2P6FO rhltdVCBdRL9mHDRf0nH/LUlZ7/gBpKz3BM0z4Bdglfhf0MB8BHJnKK55kQDH7t6uAB8 bYtHURLnU5xTl6SFQua2XH6/D0AvQGjmbpUz+LQE3ZpuoWgoSzz1h+LxThw96Tyl5zcF /KYoch82dDPaZ0xmQ6k8IvLFh5lzGUueUkhqJQQH6P6TarK28ZTzdvhHxAEYVAUu0UFQ T8GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704580804; x=1705185604; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=c8cx4G027Gz6iFuAIfhaAQlzyB7pPX4ipODK9kWLrHg=; b=ZvfBVQUVCmETVQtnzX+ELFDZ875QQjqoIQ7OL4RPVa6jFkYD9Ccel9gRltaaEJn0ZF rGl7WVzXSyPvYjtxETReffdLR2YznKgPNY4Upa94Wzl2LJ2NWvYbs3/lwe8OViZdqvkF 6Wep6YI7BN9b0tuBTLwxKiyITZIriyJU1fe8WmtYUjFJRRhzJGHorfFp6gXeh6juXVw7 MVcGSbivOfjZfHuCRCu5NDA9kcZS8+f+0MfodWtV6KjlPTX2EWgN50GKZJt8wsoU5E6+ hVD8iVPl1SI7S0zyv3JxkNOwZyhJgKlg2JkwLPI+8mxQQeQd+7lEb1do7dVNpSoQYvn4 /vcg== X-Gm-Message-State: AOJu0YyGgBj9UIJwC+lW40yHywuqeuQribgl2eZDCIq/ojs5q030lGrB FgtprvFO0GMBepOYmuG3eP+u2KWQ8nRyHw== X-Google-Smtp-Source: AGHT+IF4ssqcTFHr3Jn08b3Gd7DuE+48XGfS+pjvMKa/I6ROTT1Ogk6JfMsJzI/AFBbKn9NBmODzPw== X-Received: by 2002:a05:6e02:16c7:b0:35f:f707:46ed with SMTP id 7-20020a056e0216c700b0035ff70746edmr2343459ilx.5.1704580804057; Sat, 06 Jan 2024 14:40:04 -0800 (PST) Received: from aford-System-Version.lan ([2601:447:d002:5be:af2f:17f0:33a3:d6fe]) by smtp.gmail.com with ESMTPSA id l13-20020a056e021c0d00b0035ffe828182sm735346ilh.37.2024.01.06.14.40.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Jan 2024 14:40:03 -0800 (PST) From: Adam Ford To: linux-pm@vger.kernel.org Cc: Adam Ford , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Ulf Hansson , Lucas Stach , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] dt-bindings: soc: imx: add fdcc clock to i.MX8MP hdmi blk ctrl Date: Sat, 6 Jan 2024 16:39:48 -0600 Message-ID: <20240106223951.387067-1-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Per guidance from the NXP downstream kernel, if the clock is disabled before HDMI/LCDIF probe, LCDIF will not get pixel clock from HDMI PHY and throw an error. Fix this by adding the fdcc clock to the hdmi_blk_ctrl. Signed-off-by: Adam Ford diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml index 1be4ce2a45e8..741b5d8da4bb 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml @@ -42,8 +42,8 @@ properties: - const: hdmi-tx-phy clocks: - minItems: 4 - maxItems: 4 + minItems: 5 + maxItems: 5 clock-names: items: @@ -51,6 +51,7 @@ properties: - const: axi - const: ref_266m - const: ref_24m + - const: fdcc interconnects: maxItems: 3 @@ -82,8 +83,9 @@ examples: clocks = <&clk IMX8MP_CLK_HDMI_APB>, <&clk IMX8MP_CLK_HDMI_ROOT>, <&clk IMX8MP_CLK_HDMI_REF_266M>, - <&clk IMX8MP_CLK_HDMI_24M>; - clock-names = "apb", "axi", "ref_266m", "ref_24m"; + <&clk IMX8MP_CLK_HDMI_24M>, + <&clk IMX8MP_CLK_HDMI_FDCC_TST>; + clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc"; power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmi_phy>; From patchwork Sat Jan 6 22:39:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 760463 Received: from mail-io1-f51.google.com (mail-io1-f51.google.com [209.85.166.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D5B4101E3; Sat, 6 Jan 2024 22:40:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="cgOP3q4p" Received: by mail-io1-f51.google.com with SMTP id ca18e2360f4ac-7ba8e33dd0cso40710339f.0; Sat, 06 Jan 2024 14:40:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704580806; x=1705185606; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pjMgdeRpctwTJ7F3CFnuysHXKhIpRAp8TwJ6AUfLDG4=; b=cgOP3q4p95nx0zj5ZtKQ7kGZqSW23grCuabNMXaiXOFQjzzU97RI4y7zXClkW24kxF j/wCoxYxZZDlCVK8gmrcFWY3iKbzDNP9Gn9WH0BirU/abG/oR8HtClJPWd+Vih7vPbiU Uo331tSs0C+GBZLwznUXtljFebb19eShSXKTCecvy04nffMHpGsO4UQifsVhGP6yyo5z Hj+QL3xf1I6G2szt7gtzudmGutsdVRT2P7dBP/J87Gwe29VweLfhsyI98yO3scYSuyVL +sUSWHPduky0htJjKZQ6kmfsZFDLadcVwNIk7fzJiyDHzdeSRhWEExiFDb06J8fpf9ST dRRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704580806; x=1705185606; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pjMgdeRpctwTJ7F3CFnuysHXKhIpRAp8TwJ6AUfLDG4=; b=hcdEi6Jnx1OHohYuypPDEGkunnDzyM5SwqtaIZK7dCq9bLT3G32evzxZ2k6qO6ok3C uhB5drSr2ZJkb4pvzWUsELXX4jzL9APf7ygebDMjxwCPqj7K5HvWvUoqMUIC5rHlDyWu fonxW+OmW03duUA8UbKnkxpG9RUzSOklp9Ul3+Q3YIjuiS/pUd1HX7twY1W/DrrVqXOl IXZZlsUVY60Gjh8jaVOXXnMDwYqVUkhP0FslGLpPkkrgJR3Xr9sD9n0k6Ye6Xdj0LtrP ux++jLcDTZvo6+4oWhfxFJBG8vdVOHjk45cAjCwQJpf+x5sxNLK4k1eb4LFfYMa++gGf XinQ== X-Gm-Message-State: AOJu0YzKMeGme657fGtRZLwmhQGD4fLr/HtRbl+u1pU5ATvgX+KDql4/ Dzys4DDv+o9EMAODBPQHnS3Z8J5S+2oyeA== X-Google-Smtp-Source: AGHT+IH6sL6lYSC6STeoHI+PeiaWMCl/uvrhXHbpVW3sbXBLqzbyLho0XvENXWhiIPVRFPYJCUkyuA== X-Received: by 2002:a05:6e02:2402:b0:360:8928:2170 with SMTP id bs2-20020a056e02240200b0036089282170mr507707ilb.26.1704580805888; Sat, 06 Jan 2024 14:40:05 -0800 (PST) Received: from aford-System-Version.lan ([2601:447:d002:5be:af2f:17f0:33a3:d6fe]) by smtp.gmail.com with ESMTPSA id l13-20020a056e021c0d00b0035ffe828182sm735346ilh.37.2024.01.06.14.40.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Jan 2024 14:40:05 -0800 (PST) From: Adam Ford To: linux-pm@vger.kernel.org Cc: Adam Ford , Sandor Yu , Jacky Bai , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Ulf Hansson , Lucas Stach , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] pmdomain: imx8mp-blk-ctrl: imx8mp_blk: Add fdcc clock to hdmimix domain Date: Sat, 6 Jan 2024 16:39:49 -0600 Message-ID: <20240106223951.387067-2-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240106223951.387067-1-aford173@gmail.com> References: <20240106223951.387067-1-aford173@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 According to i.MX8MP RM and HDMI ADD, the fdcc clock is part of hdmi rx verification IP that should not enable for HDMI TX. But actually if the clock is disabled before HDMI/LCDIF probe, LCDIF will not get pixel clock from HDMI PHY and print the error logs: [CRTC:39:crtc-2] vblank wait timed out WARNING: CPU: 2 PID: 9 at drivers/gpu/drm/drm_atomic_helper.c:1634 drm_atomic_helper_wait_for_vblanks.part.0+0x23c/0x260 Add fdcc clock to LCDIF and HDMI TX power domains to fix the issue. Signed-off-by: Sandor Yu Reviewed-by: Jacky Bai Signed-off-by: Adam Ford --- The original work was from Sandor on the NXP Down-stream kernel diff --git a/drivers/pmdomain/imx/imx8mp-blk-ctrl.c b/drivers/pmdomain/imx/imx8mp-blk-ctrl.c index e3203eb6a022..a56f7f92d091 100644 --- a/drivers/pmdomain/imx/imx8mp-blk-ctrl.c +++ b/drivers/pmdomain/imx/imx8mp-blk-ctrl.c @@ -55,7 +55,7 @@ struct imx8mp_blk_ctrl_domain_data { const char *gpc_name; }; -#define DOMAIN_MAX_CLKS 2 +#define DOMAIN_MAX_CLKS 3 #define DOMAIN_MAX_PATHS 3 struct imx8mp_blk_ctrl_domain { @@ -457,8 +457,8 @@ static const struct imx8mp_blk_ctrl_domain_data imx8mp_hdmi_domain_data[] = { }, [IMX8MP_HDMIBLK_PD_LCDIF] = { .name = "hdmiblk-lcdif", - .clk_names = (const char *[]){ "axi", "apb" }, - .num_clks = 2, + .clk_names = (const char *[]){ "axi", "apb", "fdcc" }, + .num_clks = 3, .gpc_name = "lcdif", .path_names = (const char *[]){"lcdif-hdmi"}, .num_paths = 1, @@ -483,8 +483,8 @@ static const struct imx8mp_blk_ctrl_domain_data imx8mp_hdmi_domain_data[] = { }, [IMX8MP_HDMIBLK_PD_HDMI_TX] = { .name = "hdmiblk-hdmi-tx", - .clk_names = (const char *[]){ "apb", "ref_266m" }, - .num_clks = 2, + .clk_names = (const char *[]){ "apb", "ref_266m", "fdcc" }, + .num_clks = 3, .gpc_name = "hdmi-tx", }, [IMX8MP_HDMIBLK_PD_HDMI_TX_PHY] = { From patchwork Sat Jan 6 22:39:50 2024 Content-Type: text/plain; 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Sat, 06 Jan 2024 14:40:07 -0800 (PST) Received: from aford-System-Version.lan ([2601:447:d002:5be:af2f:17f0:33a3:d6fe]) by smtp.gmail.com with ESMTPSA id l13-20020a056e021c0d00b0035ffe828182sm735346ilh.37.2024.01.06.14.40.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Jan 2024 14:40:06 -0800 (PST) From: Adam Ford To: linux-pm@vger.kernel.org Cc: Lucas Stach , Adam Ford , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Ulf Hansson , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] arm64: dts: imx8mp: add HDMI power-domains Date: Sat, 6 Jan 2024 16:39:50 -0600 Message-ID: <20240106223951.387067-3-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240106223951.387067-1-aford173@gmail.com> References: <20240106223951.387067-1-aford173@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lucas Stach This adds the PGC and HDMI blk-ctrl nodes providing power control for HDMI subsystem peripherals. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford --- V2: Added the fdcc to hdmi_blk_ctrl per NXP's downstream kernel guidance I (Adam) tried to help move this along, so I took Lucas' patch and attempted to apply fixes based on feedback. I don't have all the history, so apologies for that. diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 76c73daf546b..d695c80e710c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -836,6 +836,23 @@ pgc_mediamix: power-domain@10 { <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; }; + pgc_hdmimix: power-domains@14 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_133M>; + assigned-clock-rates = <500000000>, <133000000>; + }; + + pgc_hdmi_phy: power-domains@15 { + #power-domain-cells = <0>; + reg = ; + }; + pgc_mipi_phy2: power-domain@16 { #power-domain-cells = <0>; reg = ; @@ -1361,6 +1378,25 @@ eqos: ethernet@30bf0000 { intf_mode = <&gpr 0x4>; status = "disabled"; }; + + hdmi_blk_ctrl: blk-ctrl@32fc0000 { + compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; + reg = <0x32fc0000 0x23c>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_HDMI_24M>, + <&clk IMX8MP_CLK_HDMI_FDCC_TST>; + clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc"; + power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmi_phy>; + power-domain-names = "bus", "irqsteer", "lcdif", + "pai", "pvi", "trng", + "hdmi-tx", "hdmi-tx-phy"; + #power-domain-cells = <1>; + }; }; aips5: bus@30c00000 {