From patchwork Tue Jan 16 01:08:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 763092 Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0A6B41C85 for ; Tue, 16 Jan 2024 01:08:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="UOptdqcQ" Received: by mail-lf1-f52.google.com with SMTP id 2adb3069b0e04-50e7b51b0ceso9363888e87.1 for ; Mon, 15 Jan 2024 17:08:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705367319; x=1705972119; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2GejD4zZZsGDMHwYRtgsSZy6lum8oExkOS46Y7L43Kw=; b=UOptdqcQT5WJDc6CE2x/MuBStJwy2Xyodd2Fv7UWOiBU9F7DPP006ebmYPZ350a9ZM 7Fzuf9Ub7QPk/vFO5mKBk4eeGTWPlb0UteD46wr4APz6rHDklNrY671XYN8mEbDUhTD1 AfvY/BaZVSPOljTn23nM/DhZmsK1RRsKFdCOlYmRsFaTVGcCDDZnGe2thbLAXYFohSAw 0ILx034PxDKNo5wShb2HOub+/4NWiSr1XLYAoKMELr9C+BftcXl+6EEWkUzHKQ5ojD+X oF47EpkN90AL10//JXnt2WR4COqoEYEgcrRCwHxSQbMu7XJmGluhhDjZDnVfxyX+yqrk 5e5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705367319; x=1705972119; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2GejD4zZZsGDMHwYRtgsSZy6lum8oExkOS46Y7L43Kw=; b=eHBFAgRiABzJi++kEQEfAHkhWRoXTS6O1tPZJXUy0wDqi8Onaq/VFkAl+eKda9XyvR TVtwlycB7Ys1AJIOogCli5TbL/H/hz+DoCPzm3fonHeUv3O4flM2qubYR72TJ/KMq4qI Vj0NejCpgwr+0LpuOIIsVaS03XcVw9fFb0BlGJDMC9diRM4cwP6nE9tkwx2DqdfnQpED m2XsM8NSb7M0rNtCScmkJ7YB28CMFq8eLkYURLW4zIphLBz5aImVnVH26ghsA9vApeDX YGiqHvdlmvzzMCyGqmZhAWlDd/WcUj0RKgM0R0kLpBeuo9eyUD8t0E2+p/ZCtJ59YLbJ exLg== X-Gm-Message-State: AOJu0YzDJif6GuChaSOb3BGwePbZjqbf0nwtYDax21bi6Ft1eL3cm6Ko TiHguWXessKoKL4wEsvy94kKm1jXK1oBWA== X-Google-Smtp-Source: AGHT+IF4uY2IXXqcFlQk0kE43Q3PU+KiNoFsBavpJ8CtG05uDWkQ8ylL0yG7cG2uDfhV/l7L8wGeRw== X-Received: by 2002:a05:6512:39d3:b0:50e:70b9:8600 with SMTP id k19-20020a05651239d300b0050e70b98600mr4138890lfu.0.1705367318393; Mon, 15 Jan 2024 17:08:38 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id t3-20020a056512208300b0050eb2325472sm1615507lfr.37.2024.01.15.17.08.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jan 2024 17:08:38 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 16 Jan 2024 03:08:27 +0200 Subject: [PATCH 1/6] dt-bindings: mfd: qcom,tcsr: Add compatibles for QCM2290 and SM6115 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240116-usbc-phy-vls-clamp-v1-1-73b2da7691c5@linaro.org> References: <20240116-usbc-phy-vls-clamp-v1-0-73b2da7691c5@linaro.org> In-Reply-To: <20240116-usbc-phy-vls-clamp-v1-0-73b2da7691c5@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Jeffrey Hugo Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org, Dmitry Baryshkov X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1054; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Y+5fCr59sQqkRvEhrPMHqTIkuV7VTqZkyNtAF9yAvO0=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlpdcTmV3QAehqNHLkPutAKWHGSN2ww4nuk/KvH 8y0ySv2OpqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZaXXEwAKCRCLPIo+Aiko 1e94B/9wqdYVWm8HYtf/Ue6b5mdGcQIQWHHHZMY1fnsWqMaPORGTKLpgJGwJ/EtES8+Q+49LwfV Me31jibYz9GVkaujuwN4H4y3EnYd3CWlIj6U44rJ1oiGBSGrsfYaece9x3H2l6PP5pMxpsRbq3W zAQ/Zq6h1d/R7BqeTT2B2uhfueY5EHjYmKmayDNi/M295/3b3O/caKdO953L6tGjfcFGfng2cdY KT11GycxK9SeZURuTyJzZgZiAxLQPcNFH/+qchs8dIEbDsNtqJmZEjL52sRcxKnY8uoyE7EXxkr CkeEpR5hLY1OSqfPZwSzv2dTNq+X6/EfwWy7pnQOS/3pWOup X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Add qcom,qcm2290-tcsr and qcom,sm6115-tcsr, compatibles for TCSR blocks on the corresponding platforms. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml index 798705ab6a46..b97d77015335 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -19,6 +19,7 @@ properties: - enum: - qcom,msm8976-tcsr - qcom,msm8998-tcsr + - qcom,qcm2290-tcsr - qcom,qcs404-tcsr - qcom,sc7180-tcsr - qcom,sc7280-tcsr @@ -28,6 +29,7 @@ properties: - qcom,sdx55-tcsr - qcom,sdx65-tcsr - qcom,sm4450-tcsr + - qcom,sm6115-tcsr - qcom,sm8150-tcsr - qcom,sm8250-tcsr - qcom,sm8350-tcsr From patchwork Tue Jan 16 01:08:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 763348 Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D075341C8A for ; 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Mon, 15 Jan 2024 17:08:39 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id t3-20020a056512208300b0050eb2325472sm1615507lfr.37.2024.01.15.17.08.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jan 2024 17:08:38 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 16 Jan 2024 03:08:28 +0200 Subject: [PATCH 2/6] dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: add TCSR registers Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240116-usbc-phy-vls-clamp-v1-2-73b2da7691c5@linaro.org> References: <20240116-usbc-phy-vls-clamp-v1-0-73b2da7691c5@linaro.org> In-Reply-To: <20240116-usbc-phy-vls-clamp-v1-0-73b2da7691c5@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Jeffrey Hugo Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org, Dmitry Baryshkov X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1603; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=aBcQF7l7ykn1twMJr9c0QhEVt66OcJk/Ki8m8VZZ5gA=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlpdcUwW7a37xFdBCpgcJhqWckj1rXkxGi7snJH SLCros33d+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZaXXFAAKCRCLPIo+Aiko 1a1LB/0R8F87C2htTQS4hraLPGVNqIStbZfamJwSeJQO2gOpDAdXtp9pZdR7iwfDEqosWps99jA LpaUXEyagmbPmyqgJUkUBoDBaZ/GD6C/fuC7UhRPINF6DsCDt68VIQBeA77Gkv/U9/mhhb/MNll JA0i+lZwYuFXf6CIN6HgRmrhbunt3ZJyLxcC19CUg81yvQzJ7SYOrEATxliPYbeMq8ETLFQu6ZB vvWXJ+Vmn3WpcjbzsHplCeB2sIsOYvVlaA+hilh9O3ssflu7UPqySGu29Wmyasj3rzAf7wqujQd 0ofGcqFLJiQ+g+fpugm4ANRZKMW9iwuWmWg/QZPfMyEwRMiF X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The QMP USB PHYs on msm8998, qcm2290 and some other platforms don't have the PCS_MISC_CLAMP_ENABLE register. Instead they need to toggle the register in the TCSR space. Declare the registers accessible through the TCSR space. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml index da5d4cbca24c..140843347d1e 100644 --- a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml @@ -55,6 +55,14 @@ properties: Flag the PHY as possible handler of USB Type-C orientation switching type: boolean + qcom,tcsr-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to TCSR hardware block + - description: offset of the VLS CLAMP register + description: Clamp register present in the TCSR + ports: $ref: /schemas/graph.yaml#/properties/ports properties: @@ -78,6 +86,7 @@ required: - "#clock-cells" - clock-output-names - "#phy-cells" + - qcom,tcsr-reg allOf: - if: @@ -148,6 +157,8 @@ examples: orientation-switch; + qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>; + ports { #address-cells = <1>; #size-cells = <0>; From patchwork Tue Jan 16 01:08:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 763347 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D09A41C94 for ; Tue, 16 Jan 2024 01:08:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Vzqpqr3E" Received: by mail-lf1-f47.google.com with SMTP id 2adb3069b0e04-50e67e37661so12814278e87.0 for ; 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a=openpgp-sha256; l=5055; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=XQ5Pv7+enL8CAcnblULFpJMoVjMYx0Ov7jzzVvGDtFw=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlpdcUGwNBPnlX0CcdJ9wAyEjTedGPvRMPpezqV KveL8p7W3eJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZaXXFAAKCRCLPIo+Aiko 1f6eB/4tLjA4jNoELTTVUVfj7LoUH4GVYHmuiq1uVXGznyXax4TS9ZuxNQK6rcHQnRfV8jdq7fm 3NFs26on14zIR0gWIFuqKiuBZ81mI0B+VNzXyKmOpKxYfo0ctY2Qy3dheLrSYB8xX9WJynLMzpO Eesq73QMO9pePPTr8mUFV7raPRuVudW/jmZfEVVag25lf5w4BmnfBkj0PtwzMtDN2ilh4b1Qvd2 3kPT4ds+U3c987kDhz2yYeUOSQdUbwN8wOK5A17C6onM4bhMNkf0j/17ODI6NOlXrC5ZVmx0VHF zXd/d4F/NmBAZegDevoCnXbDtERoqDZbEefBjiNrjSCQdZVU X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The QMP USB PHYs on msm8998, qcm2290 and some other platforms don't have the PCS_MISC_CLAMP_ENABLE register. Instead they need to toggle the register in the TCSR space. Make the new phy-qcom-qmp-usbc driver correctly handle the clamp register. Fixes: a51969fafc82 ("phy: qcom-qmp: Add QMP V3 USB3 PHY support for msm8998") Fixes: 8abe5e778b2c ("phy: qcom-qmp: Add QCM2290 USB3 PHY support") Cc: Jeffrey Hugo Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 48 ++++++++++++++++++++++++-------- 1 file changed, 37 insertions(+), 11 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c index 214cf4203de4..3a4b4849db0f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -10,11 +10,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -56,9 +58,6 @@ /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ #define IRQ_CLEAR BIT(0) -/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ -#define CLAMP_EN BIT(0) /* enables i/o clamp_n */ - #define PHY_INIT_COMPLETE_TIMEOUT 10000 struct qmp_phy_init_tbl { @@ -94,7 +93,6 @@ enum qphy_reg_layout { QPHY_PCS_AUTONOMOUS_MODE_CTRL, QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, QPHY_PCS_POWER_DOWN_CONTROL, - QPHY_PCS_MISC_CLAMP_ENABLE, /* Keep last to ensure regs_layout arrays are properly initialized */ QPHY_LAYOUT_SIZE }; @@ -106,7 +104,6 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, - [QPHY_PCS_MISC_CLAMP_ENABLE] = QPHY_V3_PCS_MISC_CLAMP_ENABLE, }; static const unsigned int qmp_v3_usb3phy_regs_layout_qcm2290[QPHY_LAYOUT_SIZE] = { @@ -369,6 +366,9 @@ struct qmp_usbc { void __iomem *tx2; void __iomem *rx2; + struct regmap *tcsr_map; + u32 vls_clamp_reg; + struct clk *pipe_clk; struct clk_bulk_data *clks; int num_clks; @@ -691,7 +691,6 @@ static void qmp_usbc_enable_autonomous_mode(struct qmp_usbc *qmp) { const struct qmp_phy_cfg *cfg = qmp->cfg; void __iomem *pcs = qmp->pcs; - void __iomem *pcs_misc = qmp->pcs_misc; u32 intr_mask; if (qmp->mode == PHY_MODE_USB_HOST_SS || @@ -712,19 +711,18 @@ static void qmp_usbc_enable_autonomous_mode(struct qmp_usbc *qmp) qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); /* Enable i/o clamp_n for autonomous mode */ - if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE]) - qphy_clrbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN); + if (qmp->tcsr_map && qmp->vls_clamp_reg) + regmap_write(qmp->tcsr_map, qmp->vls_clamp_reg, 1); } static void qmp_usbc_disable_autonomous_mode(struct qmp_usbc *qmp) { const struct qmp_phy_cfg *cfg = qmp->cfg; void __iomem *pcs = qmp->pcs; - void __iomem *pcs_misc = qmp->pcs_misc; /* Disable i/o clamp_n on resume for normal mode */ - if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE]) - qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN); + if (qmp->tcsr_map && qmp->vls_clamp_reg) + regmap_write(qmp->tcsr_map, qmp->vls_clamp_reg, 0); qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); @@ -1063,6 +1061,30 @@ static int qmp_usbc_parse_dt(struct qmp_usbc *qmp) return 0; } +static int qmp_usbc_parse_vls_clamp(struct qmp_usbc *qmp) +{ + struct of_phandle_args tcsr_args; + struct device *dev = qmp->dev; + int ret; + + /* for backwards compatibility ignore if there is no property */ + ret = of_parse_phandle_with_fixed_args(dev->of_node, "qcom,tcsr-reg", 1, 0, + &tcsr_args); + if (ret == -ENOENT) + return 0; + else if (ret < 0) + return dev_err_probe(dev, ret, "Failed to parse qcom,tcsr-reg\n"); + + qmp->tcsr_map = syscon_node_to_regmap(tcsr_args.np); + of_node_put(tcsr_args.np); + if (IS_ERR(qmp->tcsr_map)) + return PTR_ERR(qmp->tcsr_map); + + qmp->vls_clamp_reg = tcsr_args.args[0]; + + return 0; +} + static int qmp_usbc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1093,6 +1115,10 @@ static int qmp_usbc_probe(struct platform_device *pdev) if (ret) return ret; + ret = qmp_usbc_parse_vls_clamp(qmp); + if (ret) + return ret; + /* Check for legacy binding with child node. */ np = of_get_child_by_name(dev->of_node, "phy"); if (np) { From patchwork Tue Jan 16 01:08:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 763091 Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6659D41C99 for ; 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Mon, 15 Jan 2024 17:08:40 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 16 Jan 2024 03:08:30 +0200 Subject: [PATCH 4/6] arm64: dts: qcom: msm8998: declare VLS CLAMP register for USB3 PHY Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240116-usbc-phy-vls-clamp-v1-4-73b2da7691c5@linaro.org> References: <20240116-usbc-phy-vls-clamp-v1-0-73b2da7691c5@linaro.org> In-Reply-To: <20240116-usbc-phy-vls-clamp-v1-0-73b2da7691c5@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Jeffrey Hugo Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org, Dmitry Baryshkov X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=891; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=f12NIWxuaNF6335LMHvzmeal7J/0jE48+iZdMsjs8pU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlpdcUA8BUvO4Wnz7aji2y1YM/6hAjte1eVG47Z JNASjDNHYmJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZaXXFAAKCRCLPIo+Aiko 1UvWCACP1E1eQ+zq2gm6nte6GNYwnjgkNsu3bQqf3JTyTM+qr7Bxxx/fWTfWf1oYITy+IpqIJeM rGF6hjNDw32Q9hACywkkN428oWtcmFPt696i1pj8VUELOeIUi5SxZvsowN7+ArPhUDjtBNJRoMC s2dGoqYra9M8xRvQ7Z4FMum/LXjBPzU5Bxnig5PU82hY2xy6Fs3BUDQwXqQRo6Y8sBRZDJzMvor rcsKgTZqW4WfyNNoQ0qmxC1sA7IYp5QfxDVWmaZOOpHVDdrGr7bAnRONU9gA8ANy+uhWMdJBiKg daVJ4Rul3PnAGpufyUxD3pbO3lV/G+mZ0sjdag3YOCy5GEV6 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The USB3 PHY on the MSM8998 platform doesn't have built-in PCS_MISC_CLAMP_ENABLE register. Instead clamping is handled separately via the register in the TCSR space. Declare corresponding register. Fixes: 026dad8f5873 ("arm64: dts: qcom: msm8998: Add USB-related nodes") Cc: Jeffrey Hugo Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 2793cc22d381..e21e5693ba1e 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2174,6 +2174,8 @@ usb3phy: phy@c010000 { reset-names = "phy", "phy_phy"; + qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>; + status = "disabled"; }; From patchwork Tue Jan 16 01:08:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 763346 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B62C643AAB for ; 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Mon, 15 Jan 2024 17:08:40 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id t3-20020a056512208300b0050eb2325472sm1615507lfr.37.2024.01.15.17.08.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jan 2024 17:08:40 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 16 Jan 2024 03:08:31 +0200 Subject: [PATCH 5/6] arm64: dts: qcom: qcm2290: declare VLS CLAMP register for USB3 PHY Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240116-usbc-phy-vls-clamp-v1-5-73b2da7691c5@linaro.org> References: <20240116-usbc-phy-vls-clamp-v1-0-73b2da7691c5@linaro.org> In-Reply-To: <20240116-usbc-phy-vls-clamp-v1-0-73b2da7691c5@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Jeffrey Hugo Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org, Dmitry Baryshkov X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1149; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=5s+C8l9HjeR5C9PMCkzn2M15yrFw6QVI1uh1HoQRbAw=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlpdcUB5Y++cfi+p9OvDh9xSmKvHvrn1QVKX8p7 Oh2qsjYNoSJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZaXXFAAKCRCLPIo+Aiko 1cPCB/4nTVJB8iCrE0+m/U4GPT2jleb1BIy0WpsHcERz38NcTplPem5Xekmt8JzdIbRytU2hLq4 NY0qaS4PBhsBUo2hMLH4LCfc4o1QIKMSB01pLj3B7wl0H4wnlx46MX8NZ3MY46kxhIBLNa1NOjL g6QAhwM2aToZWXcOgvIB4OJgfMrxc6BUhMv1gYMmwj/UkattbENA/hjTDSNQb1rwrpUVgkbOlpM 5nMruXaSA0z592WhsqGrlMWsBmnRN7sj2I9ArQT48kWeUGq+a0Ywt/wXrwRUtZCaV+H4nG6Va2M eNtEWrnBU+bGM/OkCp3aaW0iV33PLptzgBAhhmQzjmQ9OGLs X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The USB3 PHY on the QCM2290 platform doesn't have built-in PCS_MISC_CLAMP_ENABLE register. Instead clamping is handled separately via the register in the TCSR space. Declare corresponding register. Fixes: 0c55f6229bc3 ("arm64: dts: qcom: qcm2290: Add USB3 PHY") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 0911fb08ed63..68b52e8faba5 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -442,6 +442,11 @@ tcsr_mutex: hwlock@340000 { #hwlock-cells = <1>; }; + tcsr_regs_1: syscon@360000 { + compatible = "qcom,qcm2290-tcsr", "syscon"; + reg = <0x0 0x00360000 0x0 0x20000>; + }; + tlmm: pinctrl@500000 { compatible = "qcom,qcm2290-tlmm"; reg = <0x0 0x00500000 0x0 0x300000>; @@ -690,6 +695,8 @@ usb_qmpphy: phy@1615000 { #phy-cells = <0>; + qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>; + status = "disabled"; }; From patchwork Tue Jan 16 01:08:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 763090 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5064041C8F for ; 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Mon, 15 Jan 2024 17:08:41 -0800 (PST) From: Dmitry Baryshkov Date: Tue, 16 Jan 2024 03:08:32 +0200 Subject: [PATCH 6/6] arm64: dts: qcom: sm6115: declare VLS CLAMP register for USB3 PHY Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240116-usbc-phy-vls-clamp-v1-6-73b2da7691c5@linaro.org> References: <20240116-usbc-phy-vls-clamp-v1-0-73b2da7691c5@linaro.org> In-Reply-To: <20240116-usbc-phy-vls-clamp-v1-0-73b2da7691c5@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Jeffrey Hugo Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org, Dmitry Baryshkov X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1151; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=AdXDhIsnd+iXSWZKTFcLsyqUk+oKkuaRSto6EvCY8cg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBlpdcUlM9KRQMg6qbyevu03KD/zZr72wNib4qD1 uB4dUptrKeJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZaXXFAAKCRCLPIo+Aiko 1R/XB/9FpNoeUmcKdOQ6BmmvI4G2XZzEF+ILr7Y0cQdQPcopIXTcMcJUqYEM6eAhwIQLOhsxE0o ZmyurDD5Mvv6hMZqdudsoMoVgOz3YhVTiUyMg5wEAMdSYgtwigWEsA9C4JasUen3m4zfclT+WeL 2Ed2c5799TBbn56oGjrXcolU0RUOd9fIl9EibLT7ZK1Lj8U58reZ4urgkjxzpkT5wzIWWU4s7+K A0FDXtbK+To573tmlnFj/5aLxphxn1Di8D0rT453WxunZF/eTp5lpQQs5shEZOX9IY+HnFjnGAz 6Zf9pwsf9cU1C7rzCh/rmEnCRNQ/8s3DKWindT753QqFnAJr X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The USB3 PHY on the SM6115 platform doesn't have built-in PCS_MISC_CLAMP_ENABLE register. Instead clamping is handled separately via the register in the TCSR space. Declare corresponding register. Fixes: 9dd5f6dba729 ("arm64: dts: qcom: sm6115: Add USB SS qmp phy node") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 160e098f1075..8cee943fb24e 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -614,6 +614,11 @@ tcsr_mutex: hwlock@340000 { #hwlock-cells = <1>; }; + tcsr_regs_1: syscon@360000 { + compatible = "qcom,sm6115-tcsr", "syscon"; + reg = <0x0 0x00360000 0x0 0x20000>; + }; + tlmm: pinctrl@500000 { compatible = "qcom,sm6115-tlmm"; reg = <0x0 0x00500000 0x0 0x400000>, @@ -879,6 +884,8 @@ usb_qmpphy: phy@1615000 { #phy-cells = <0>; + qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>; + status = "disabled"; };