From patchwork Tue Jan 23 18:46:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 765463 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2CBA823B3; Tue, 23 Jan 2024 18:47:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706035633; cv=none; b=MmcKwXMaoU9nDNFHGfz4W2Wd7a6atkcjWMQ6TAEJDfKwoLdhnlrQtgFXrr82vsx2Ky3lGueuW3oP9b1mQjXHNVVG9te1ZgJi5RpDwAcCf+AU8rmDaDYtgxyr61fIsI2ix7NNFt85uBAq+ybipAYNxjyJxyEgf1AenyPfK+bS+uc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706035633; c=relaxed/simple; bh=p96N34DQIp9iFKK4bMHk+DDoqnyUXSCL+rvjuPLimgY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MVodrtd+OtoY3+9AOsJ93yI/YppDkIAuwqeMZvTC9vZaIExJsREWnPoEx/PRn4zd/4bivLHIVjHDznpN/3jxnCVvFHfmizSFs9XS11dUAEa/1cjCw0xRufDiBfNZ7k374JgYrTZawoxRJqyfqPS9SULP8U/w8MrBItKM1EUFLgg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=LKBshbAo; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="LKBshbAo" Received: by mail.gandi.net (Postfix) with ESMTPSA id 9120EC000B; Tue, 23 Jan 2024 18:47:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706035623; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Hzzlts4PGXFUuRWYcplGsnHuTe6WB3sA9fR+Y6Zs2Sk=; b=LKBshbAo11cOuZuIPLSZE4b0MvEIZl73uJXWr1LvAfV6Zt89UdGgHgceqBeSEf2VNPsH17 hufmYUC7IQoR5a8cXnT+t5AxQEMybWOnR6QG2Q5OdhZUZDCjoP4KjXc5UEOj8i5VSZyst1 kdKS5JK08Oq0Lz/NclDCsAUYphlvn0SAkS4PzmPSQlHHlR9j9I7zoWr4rWrIuwpZx7DXmD tEFd9HAifMtXFUK30eVFahx0hZwKI4UiRM4pUQPhuTV6KvPo/N3zHBeG6lO+VpgdVjeeW+ jrW6R7u0bbsC6UAmLB4oQWTj2v6v+s/lMP5g35vYevGBS2brx+ylgRkOPBpqaw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Tue, 23 Jan 2024 19:46:47 +0100 Subject: [PATCH v3 02/17] clk: fixed-factor: add fwname-based constructor functions Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240123-mbly-clk-v3-2-392b010b8281@bootlin.com> References: <20240123-mbly-clk-v3-0-392b010b8281@bootlin.com> In-Reply-To: <20240123-mbly-clk-v3-0-392b010b8281@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com Add four functions to register clk_hw based on the fw_name field in clk_parent_data, ie the value in the DT property `clock-names`. There are variants for devm or not and passing an accuracy or not passing one: - clk_hw_register_fixed_factor_fwname - clk_hw_register_fixed_factor_with_accuracy_fwname - devm_clk_hw_register_fixed_factor_fwname - devm_clk_hw_register_fixed_factor_with_accuracy_fwname The `struct clk_parent_data` init is extracted from __clk_hw_register_fixed_factor to each calling function. It is required to allow each function to pass whatever field they want, not only index. Signed-off-by: Théo Lebrun --- drivers/clk/clk-fixed-factor.c | 85 +++++++++++++++++++++++++++++++++++------- include/linux/clk-provider.h | 14 +++++++ 2 files changed, 85 insertions(+), 14 deletions(-) diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index bc2644a9bd7d..fe0500a1af3e 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -91,13 +91,12 @@ static void devm_clk_hw_register_fixed_factor_release(struct device *dev, void * static struct clk_hw * __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, const char *name, const char *parent_name, - const struct clk_hw *parent_hw, int index, + const struct clk_hw *parent_hw, const struct clk_parent_data *pdata, unsigned long flags, unsigned int mult, unsigned int div, unsigned long acc, unsigned int fixflags, bool devm) { struct clk_fixed_factor *fix; struct clk_init_data init = { }; - struct clk_parent_data pdata = { .index = index }; struct clk_hw *hw; int ret; @@ -128,7 +127,7 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, else if (parent_hw) init.parent_hws = &parent_hw; else - init.parent_data = &pdata; + init.parent_data = pdata; init.num_parents = 1; hw = &fix->hw; @@ -165,7 +164,9 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, const char *name, unsigned int index, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, index, + const struct clk_parent_data pdata = { .index = index }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, &pdata, flags, mult, div, 0, 0, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_index); @@ -187,8 +188,10 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev, const char *name, const struct clk_hw *parent_hw, unsigned long flags, unsigned int mult, unsigned int div) { + const struct clk_parent_data pdata = { .index = -1 }; + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw, - -1, flags, mult, div, 0, 0, true); + &pdata, flags, mult, div, 0, 0, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_parent_hw); @@ -196,9 +199,10 @@ struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev, const char *name, const struct clk_hw *parent_hw, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, - parent_hw, -1, flags, mult, div, - 0, 0, false); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw, + &pdata, flags, mult, div, 0, 0, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_parent_hw); @@ -206,11 +210,37 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1, - flags, mult, div, 0, 0, false); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, + &pdata, flags, mult, div, 0, 0, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor); +struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, 0, 0, false); +} +EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_fwname); + +struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div, + unsigned long acc) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, acc, + CLK_FIXED_FACTOR_FIXED_ACCURACY, false); +} +EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_with_accuracy_fwname); + struct clk *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) @@ -253,16 +283,43 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1, - flags, mult, div, 0, 0, true); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, + &pdata, flags, mult, div, 0, 0, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor); +struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, 0, 0, true); +} +EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_fwname); + +struct clk_hw *devm_clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div, + unsigned long acc) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, acc, + CLK_FIXED_FACTOR_FIXED_ACCURACY, true); +} +EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_with_accuracy_fwname); + #ifdef CONFIG_OF static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) { struct clk_hw *hw; const char *clk_name = node->name; + const struct clk_parent_data pdata = { .index = 0 }; u32 div, mult; int ret; @@ -280,8 +337,8 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) of_property_read_string(node, "clock-output-names", &clk_name); - hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, 0, - 0, mult, div, 0, 0, false); + hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, + &pdata, 0, mult, div, 0, 0, false); if (IS_ERR(hw)) { /* * Clear OF_POPULATED flag so that clock registration can be diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 7ddc952c8c67..4a537260f655 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1116,10 +1116,24 @@ void clk_unregister_fixed_factor(struct clk *clk); struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div, + unsigned long acc); void clk_hw_unregister_fixed_factor(struct clk_hw *hw); struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *devm_clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div, + unsigned long acc); struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, const char *name, unsigned int index, unsigned long flags, unsigned int mult, unsigned int div); From patchwork Tue Jan 23 18:46:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 765461 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5FDE85C69; Tue, 23 Jan 2024 18:47:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706035635; cv=none; b=swhaufhGkIwm8zKwWoSVXzUsp4FuUUOnve7tXokUxddOYUkHX1CaiA1hNfdOCP5upFMxypZkQoAm6C9ag5OfvZIMVDMh99aRebwDZQV0lAAOSjLzTq4ySC2khq9CEeeBBaJiHJOBsnZpRcxsIgz67Fuiei6wvG3Nxmb49ziHDEQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706035635; c=relaxed/simple; bh=7a7PULsrWAbyk9o4WQFw6EoMLo4uq3Z4GNa/bdfQE3w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Msr5ChaqMbavffqPw6llGwS+H1Sqll14wyVzY5D/V65ftjk4ncJYnHhHfLru5n9gEu9zW/xi6StR9Z3vgXt4vm5w3PT9lFKxqCxzqBQU8+SOj0WBEu4QXhTNqyrVoNaHLDRuF2JyWeq8yjmyo6QoyUEZ2VNCAAjCceeLG6J7hls= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=mhugsTg1; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="mhugsTg1" Received: by mail.gandi.net (Postfix) with ESMTPSA id 1D388C0003; Tue, 23 Jan 2024 18:47:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706035624; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ALLeDsdcOzz1oO5db0iKwfD4lCc6kwOs8jwpRo0rnSg=; b=mhugsTg1cC2oVa+DAg4hs8kC/QXRlGyvpQY1PDaxVlpwfmjXlaQGXHEp69SymbFAbSjnQp hYk6a2BkwNKx5VSt5ZdoFdd84W1DzVndG1bLcI7N305fuFDFrMvxgmeMYje9QL3MG3ZHrh QaFTiUrqCA0NDFjNYc4G57ttbQ9uAHrEjsc4OF1ImJHYJ/+7ff823KW/0v6XjWGBMt41ZI XhA5IyvLAwxf8eGojwAZ29fkzBKGYQuuZnNbqv6+o5SHc0p8t5uW3MoOmCW0XyrfedQBys wA14QYS0TeDfEdJDNwNzFFzFhaPw8LWe9FlYs4UPwk//zigCvYauTkiPpO2CeA== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Tue, 23 Jan 2024 19:46:49 +0100 Subject: [PATCH v3 04/17] dt-bindings: soc: mobileye: add EyeQ5 OLB system controller Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240123-mbly-clk-v3-4-392b010b8281@bootlin.com> References: <20240123-mbly-clk-v3-0-392b010b8281@bootlin.com> In-Reply-To: <20240123-mbly-clk-v3-0-392b010b8281@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com Add documentation to describe the "Other Logic Block" syscon. Signed-off-by: Théo Lebrun --- .../bindings/soc/mobileye/mobileye,eyeq5-olb.yaml | 77 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 78 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml new file mode 100644 index 000000000000..031ef6a532c1 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq5-olb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 SoC system controller + +maintainers: + - Grégory Clement + - Théo Lebrun + - Vladimir Kondratiev + +description: + OLB ("Other Logic Block") is a hardware block grouping smaller blocks. Clocks, + resets, pinctrl are being handled from here. + +properties: + compatible: + items: + - const: mobileye,eyeq5-olb + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + clock-controller: + $ref: /schemas/clock/mobileye,eyeq5-clk.yaml# + type: object + + reset-controller: + $ref: /schemas/reset/mobileye,eyeq5-reset.yaml# + type: object + + pinctrl-a: + $ref: /schemas/pinctrl/mobileye,eyeq5-pinctrl.yaml# + type: object + + pinctrl-b: + $ref: /schemas/pinctrl/mobileye,eyeq5-pinctrl.yaml# + type: object + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + system-controller@e00000 { + compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd"; + reg = <0xe00000 0x400>; + + clock-controller { + compatible = "mobileye,eyeq5-clk"; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "ref"; + }; + + reset-controller { + compatible = "mobileye,eyeq5-reset"; + #reset-cells = <2>; + }; + + pinctrl-a { + compatible = "mobileye,eyeq5-a-pinctrl"; + #pinctrl-cells = <1>; + }; + + pinctrl-b { + compatible = "mobileye,eyeq5-b-pinctrl"; + #pinctrl-cells = <1>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index cb431c79c7b8..fe1270e8c983 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14786,6 +14786,7 @@ M: Théo Lebrun L: linux-mips@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/mips/mobileye.yaml +F: Documentation/devicetree/bindings/soc/mobileye/ F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig F: arch/mips/mobileye/board-epm5.its.S From patchwork Tue Jan 23 18:46:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 765462 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2CF5823B6; Tue, 23 Jan 2024 18:47:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706035634; cv=none; b=sBZTqcP5B2HuF/BnZFAVANXVEhXvr6zFr0zJ0kB48ZLAQtmiaAYNQwIGhUIFdooq+uGFTXqnjxmpjfu6gsLCfenOCyI80RjX9TeqZr7hdI3nTOIbycyhR+491Z3Pwr3nnQWr1KCHUzuE5t8TV+59YxRIRIsGQoUTsZVamvaKW7E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706035634; c=relaxed/simple; bh=lrlfW6P8+nnr7Vb4eIZh44sDhNKfAZ2uiq0VLEkYi6c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LR+7Tb6nGuzrIRli0i808PNZxuYgimWXFtUTxhmfLqBtkA1PvDVXCa6tORM0l4QlFYlzx4onpRsYfH3eA1j0bd1kdCo3s5zmc+kwFR/8YE8/4FZa62D23nOPAEYmjF/5lxdyrtvRJrsSc0J0LTCwdoc4z15P+RzxVElXGfD8oFY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=EAdVLGtQ; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="EAdVLGtQ" Received: by mail.gandi.net (Postfix) with ESMTPSA id 37EFAC000D; Tue, 23 Jan 2024 18:47:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706035629; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=j6vdXTz6q1AE5aHZA1n5hZRYgrR1vbjLA1zvfxUbjoA=; b=EAdVLGtQj0F9hFuiz1QiLaFXudfKra+CgoktuU1lEDJ8khw32qoFDK93J7cZr6SlWgtNX5 IqV71vYYNDBvIVL278R/gLjXHy0MH6NtGGwXMP+SZePyvdOTubSUve9ETZlWYBsISuD0D+ wZCI4k7PRGjuKO5Fenyq952NYqsawZ+3D65Oh4n82CnxD+Invy5SFWJCjvt3DrMnP4gw0U mh3MzLw3epLdkQKvu71IsMDAQVc1mOcMki4Je69fbxlRBC7TLMQCxQjNTJ3Wcr8eWh2YBJ RPAoWSVMiLMbzfapMlHx0tglSTCiFLV7T7Ug7yHcgmwGp9C20vPDW620LO1wIQ== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Tue, 23 Jan 2024 19:46:54 +0100 Subject: [PATCH v3 09/17] reset: eyeq5: add platform driver Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240123-mbly-clk-v3-9-392b010b8281@bootlin.com> References: <20240123-mbly-clk-v3-0-392b010b8281@bootlin.com> In-Reply-To: <20240123-mbly-clk-v3-0-392b010b8281@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com Add the Mobileye EyeQ5 reset controller driver. It belongs to a syscon region called OLB. It might grow to add later support of other platforms from Mobileye. Signed-off-by: Théo Lebrun --- MAINTAINERS | 1 + drivers/reset/Kconfig | 12 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-eyeq5.c | 383 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 397 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3ea96ab7d2b8..dd3b5834386f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14794,6 +14794,7 @@ F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig F: arch/mips/mobileye/board-epm5.its.S F: drivers/clk/clk-eyeq5.c +F: drivers/reset/reset-eyeq5.c F: include/dt-bindings/clock/mobileye,eyeq5-clk.h F: include/dt-bindings/soc/mobileye,eyeq5.h diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index ccd59ddd7610..80bfde54c076 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -66,6 +66,18 @@ config RESET_BRCMSTB_RESCAL This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on BCM7216. +config RESET_EYEQ5 + bool "Mobileye EyeQ5 reset controller" + depends on MFD_SYSCON + depends on MACH_EYEQ5 || COMPILE_TEST + default MACH_EYEQ5 + help + This enables the Mobileye EyeQ5 reset controller. + + It has three domains, with a varying number of resets in each of them. + Registers are located in a shared register region called OLB accessed + through a syscon & regmap. + config RESET_HSDK bool "Synopsys HSDK Reset Driver" depends on HAS_IOMEM diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 8270da8a4baa..4fabe0070390 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o +obj-$(CONFIG_RESET_EYEQ5) += reset-eyeq5.o obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o diff --git a/drivers/reset/reset-eyeq5.c b/drivers/reset/reset-eyeq5.c new file mode 100644 index 000000000000..2217e42e140b --- /dev/null +++ b/drivers/reset/reset-eyeq5.c @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Reset driver for the Mobileye EyeQ5 platform. + * + * The registers are located in a syscon region called OLB. We handle three + * reset domains. Domains 0 and 2 look similar in that they both use one bit + * per reset line. Domain 1 has a register per reset. + * + * We busy-wait after updating a reset in domains 0 or 1. The reason is hardware + * logic built-in self-test (LBIST) that might be enabled. + * + * We use eq5r_ as prefix, as-in "EyeQ5 Reset", but way shorter. + * + * Known resets in domain 0: + * 3. CAN0 + * 4. CAN1 + * 5. CAN2 + * 6. SPI0 + * 7. SPI1 + * 8. SPI2 + * 9. SPI3 + * 10. UART0 + * 11. UART1 + * 12. UART2 + * 13. I2C0 + * 14. I2C1 + * 15. I2C2 + * 16. I2C3 + * 17. I2C4 + * 18. TIMER0 + * 19. TIMER1 + * 20. TIMER2 + * 21. TIMER3 + * 22. TIMER4 + * 23. WD0 + * 24. EXT0 + * 25. EXT1 + * 26. GPIO + * 27. WD1 + * + * Known resets in domain 1: + * 0. VMP0 (Vector Microcode Processors) + * 1. VMP1 + * 2. VMP2 + * 3. VMP3 + * 4. PMA0 (Programmable Macro Array) + * 5. PMA1 + * 6. PMAC0 + * 7. PMAC1 + * 8. MPC0 (Multi-threaded Processing Clusters) + * 9. MPC1 + * + * Known resets in domain 2: + * 0. PCIE0_CORE + * 1. PCIE0_APB + * 2. PCIE0_LINK_AXI + * 3. PCIE0_LINK_MGMT + * 4. PCIE0_LINK_HOT + * 5. PCIE0_LINK_PIPE + * 6. PCIE1_CORE + * 7. PCIE1_APB + * 8. PCIE1_LINK_AXI + * 9. PCIE1_LINK_MGMT + * 10. PCIE1_LINK_HOT + * 11. PCIE1_LINK_PIPE + * 12. MULTIPHY + * 13. MULTIPHY_APB + * 15. PCIE0_LINK_MGMT + * 16. PCIE1_LINK_MGMT + * 17. PCIE0_LINK_PM + * 18. PCIE1_LINK_PM + * + * Copyright (C) 2024 Mobileye Vision Technologies Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Offsets into the OLB region as well as masks for domain 1 registers. */ +#define EQ5R_OLB_SARCR0 (0x004) +#define EQ5R_OLB_SARCR1 (0x008) +#define EQ5R_OLB_PCIE_GP (0x120) +#define EQ5R_OLB_ACRP_REG(n) (0x200 + 4 * (n)) // n=0..12 +#define EQ5R_OLB_ACRP_PD_REQ BIT(0) +#define EQ5R_OLB_ACRP_ST_POWER_DOWN BIT(27) +#define EQ5R_OLB_ACRP_ST_ACTIVE BIT(29) + +/* Vendor-provided values. D1 has a long timeout because of LBIST. */ +#define D0_TIMEOUT_POLL 10 +#define D1_TIMEOUT_POLL 40000 + +/* + * Masks for valid reset lines in each domain. This array is also used to get + * the domain and reset counts. + */ +static const u32 eq5r_valid_masks[] = { 0x0FFFFFF8, 0x00001FFF, 0x0007BFFF }; + +#define EQ5R_DOMAIN_COUNT ARRAY_SIZE(eq5r_valid_masks) + +struct eq5r_private { + struct mutex mutexes[EQ5R_DOMAIN_COUNT]; /* We serialize all reset operations. */ + struct regmap *olb; /* Writes go to a syscon regmap. */ + struct reset_controller_dev rcdev; +}; + +static int _eq5r_busy_wait(struct eq5r_private *priv, struct device *dev, + u32 domain, u32 offset, bool assert) +{ + unsigned int val, mask; + int i; + + lockdep_assert_held(&priv->mutexes[domain]); + + switch (domain) { + case 0: + for (i = 0; i < D0_TIMEOUT_POLL; i++) { + regmap_read(priv->olb, EQ5R_OLB_SARCR1, &val); + val = !(val & BIT(offset)); + if (val == assert) + return 0; + __udelay(1); + } + break; + case 1: + mask = assert ? EQ5R_OLB_ACRP_ST_POWER_DOWN : EQ5R_OLB_ACRP_ST_ACTIVE; + for (i = 0; i < D1_TIMEOUT_POLL; i++) { + regmap_read(priv->olb, EQ5R_OLB_ACRP_REG(offset), &val); + if (val & mask) + return 0; + __udelay(1); + } + break; + case 2: + return 0; /* No busy waiting for domain 2. */ + default: + WARN_ON(1); + return -EINVAL; + } + + dev_dbg(dev, "%u-%u: timeout\n", domain, offset); + return -ETIMEDOUT; +} + +static void _eq5r_assert(struct eq5r_private *priv, u32 domain, u32 offset) +{ + lockdep_assert_held(&priv->mutexes[domain]); + + switch (domain) { + case 0: + regmap_clear_bits(priv->olb, EQ5R_OLB_SARCR0, BIT(offset)); + break; + case 1: + regmap_set_bits(priv->olb, EQ5R_OLB_ACRP_REG(offset), + EQ5R_OLB_ACRP_PD_REQ); + break; + case 2: + regmap_clear_bits(priv->olb, EQ5R_OLB_PCIE_GP, BIT(offset)); + break; + default: + WARN_ON(1); + } +} + +static int eq5r_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct eq5r_private *priv = dev_get_drvdata(rcdev->dev); + u32 offset = id & GENMASK(7, 0); + u32 domain = id >> 8; + int ret; + + if (WARN_ON(domain >= EQ5R_DOMAIN_COUNT)) + return -EINVAL; + + dev_dbg(rcdev->dev, "%u-%u: assert request\n", domain, offset); + + mutex_lock(&priv->mutexes[domain]); + _eq5r_assert(priv, domain, offset); + ret = _eq5r_busy_wait(priv, rcdev->dev, domain, offset, true); + mutex_unlock(&priv->mutexes[domain]); + + return ret; +} + +static void _eq5r_deassert(struct eq5r_private *priv, u32 domain, u32 offset) +{ + lockdep_assert_held(&priv->mutexes[domain]); + + switch (domain) { + case 0: + regmap_set_bits(priv->olb, EQ5R_OLB_SARCR0, BIT(offset)); + break; + case 1: + regmap_clear_bits(priv->olb, EQ5R_OLB_ACRP_REG(offset), + EQ5R_OLB_ACRP_PD_REQ); + break; + case 2: + regmap_set_bits(priv->olb, EQ5R_OLB_PCIE_GP, BIT(offset)); + break; + default: + WARN_ON(1); + } +} + +static int eq5r_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct eq5r_private *priv = dev_get_drvdata(rcdev->dev); + u32 offset = id & GENMASK(7, 0); + u32 domain = id >> 8; + int ret; + + if (WARN_ON(domain >= EQ5R_DOMAIN_COUNT)) + return -EINVAL; + + dev_dbg(rcdev->dev, "%u-%u: deassert request\n", domain, offset); + + mutex_lock(&priv->mutexes[domain]); + _eq5r_deassert(priv, domain, offset); + ret = _eq5r_busy_wait(priv, rcdev->dev, domain, offset, false); + mutex_unlock(&priv->mutexes[domain]); + + return ret; +} + +static int eq5r_reset(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct device *dev = rcdev->dev; + struct eq5r_private *priv = dev_get_drvdata(dev); + u32 offset = id & GENMASK(7, 0); + u32 domain = id >> 8; + int ret; + + if (WARN_ON(domain >= EQ5R_DOMAIN_COUNT)) + return -EINVAL; + + dev_dbg(dev, "%u-%u: reset request\n", domain, offset); + + mutex_lock(&priv->mutexes[domain]); + + _eq5r_assert(priv, domain, offset); + ret = _eq5r_busy_wait(priv, dev, domain, offset, true); + if (ret) /* don't let an error disappear silently */ + dev_warn(dev, "%u-%u: reset assert failed: %d\n", + domain, offset, ret); + + _eq5r_deassert(priv, domain, offset); + ret = _eq5r_busy_wait(priv, dev, domain, offset, false); + + mutex_unlock(&priv->mutexes[domain]); + + return ret; +} + +static int eq5r_status(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct eq5r_private *priv = dev_get_drvdata(rcdev->dev); + u32 offset = id & GENMASK(7, 0); + u32 domain = id >> 8; + unsigned int val; + int ret; + + if (WARN_ON(domain >= EQ5R_DOMAIN_COUNT)) + return -EINVAL; + + dev_dbg(rcdev->dev, "%u-%u: status request\n", domain, offset); + + mutex_lock(&priv->mutexes[domain]); + + switch (domain) { + case 0: + regmap_read(priv->olb, EQ5R_OLB_SARCR1, &val); + ret = !(val & BIT(offset)); + break; + case 1: + regmap_read(priv->olb, EQ5R_OLB_ACRP_REG(offset), &val); + ret = !(val & EQ5R_OLB_ACRP_ST_ACTIVE); + break; + case 2: + regmap_read(priv->olb, EQ5R_OLB_PCIE_GP, &val); + ret = !(val & BIT(offset)); + break; + } + + mutex_unlock(&priv->mutexes[domain]); + + return ret; +} + +static const struct reset_control_ops eq5r_ops = { + .reset = eq5r_reset, + .assert = eq5r_assert, + .deassert = eq5r_deassert, + .status = eq5r_status, +}; + +static int eq5r_of_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + u32 domain, offset; + + if (WARN_ON(reset_spec->args_count != 2)) + return -EINVAL; + + domain = reset_spec->args[0]; + offset = reset_spec->args[1]; + + if (domain >= EQ5R_DOMAIN_COUNT || offset > 31 || + !(eq5r_valid_masks[domain] & BIT(offset))) { + dev_err(rcdev->dev, "%u-%u: invalid reset\n", domain, offset); + return -EINVAL; + } + + return (domain << 8) | offset; +} + +static int eq5r_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct device_node *parent_np = of_get_parent(np); + struct eq5r_private *priv; + int ret, i; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + dev_set_drvdata(dev, priv); + + priv->olb = ERR_PTR(-ENODEV); + if (parent_np) { + priv->olb = syscon_node_to_regmap(parent_np); + of_node_put(parent_np); + } + if (IS_ERR(priv->olb)) + return PTR_ERR(priv->olb); + + for (i = 0; i < EQ5R_DOMAIN_COUNT; i++) + mutex_init(&priv->mutexes[i]); + + priv->rcdev.ops = &eq5r_ops; + priv->rcdev.owner = THIS_MODULE; + priv->rcdev.dev = dev; + priv->rcdev.of_node = np; + priv->rcdev.of_reset_n_cells = 2; + priv->rcdev.of_xlate = eq5r_of_xlate; + + priv->rcdev.nr_resets = 0; + for (i = 0; i < EQ5R_DOMAIN_COUNT; i++) + priv->rcdev.nr_resets += __builtin_popcount(eq5r_valid_masks[i]); + + ret = reset_controller_register(&priv->rcdev); + if (ret) { + dev_err(dev, "Failed registering reset controller: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct of_device_id eq5r_match_table[] = { + { .compatible = "mobileye,eyeq5-reset" }, + {} +}; + +static struct platform_driver eq5r_driver = { + .probe = eq5r_probe, + .driver = { + .name = "eyeq5-reset", + .of_match_table = eq5r_match_table, + }, +}; + +static int __init eq5r_init(void) +{ + return platform_driver_register(&eq5r_driver); +} + +arch_initcall(eq5r_init); From patchwork Tue Jan 23 18:46:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 765460 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06E7C129A61; Tue, 23 Jan 2024 18:47:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706035636; cv=none; b=XCFhYjpPLhusoko+4J7WJpk6Htlp3zTNfSsIEmaWAFZQ0BjUpUxPIcCXSyJnVA2ndkYy/XhoDja7/MySBAYD3T68zIe43NU9iHl0+YhHFUbdVnRv2pwELi1vU8To3nMAh7m/nCKq/9s8rqQ+u9NgsJ9b055XFTgewzVn0Ch2HOs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706035636; c=relaxed/simple; bh=ourrz1ieqvpNYcthhHHVetAQ6WXHRFLcDA7Y7qV9bnQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JeJ6Icgk+/BMlOJPcJrRo0Hhy8JEoPolTQrEm1o+dkj31hDUncPD67g4ZkmkTkbILe/wfW5z446WsM8v1QmLJ6rMgJ4SmAff3zSz27GdB2beE186a4/1gJPC2Fk0N0xa34xFA0c4LvvSd9Z2HDyLv+hvmdMNWDgS+j9sXzFaKlg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=T8DecN12; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="T8DecN12" Received: by mail.gandi.net (Postfix) with ESMTPSA id EF3E3C0012; Tue, 23 Jan 2024 18:47:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706035630; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=y+ATZ34iEoyWc1+JbHiNiRhf/HnzqfKoQxwJINgzSnA=; b=T8DecN12aj9sX+3QFqPv1g2TiS7sETrtzjHE51aHuAbCrrQiZIHB8RF9pOEvZiqEwb2dEb VMFAjk+R2T8fyJpaEoeIqdjr6rR61K4+Rf/m0nosd8JuswfzxwW9p9d4UenFrV17Xzr1WF JxZ2a/pcGIU/fKXJ0CBXH+0Fmfl9f4OO1mQQ1eDlxO5DDiqBo4Rr+7msFvwkc291v6cRhl lxXD0ju4jjTS6xYuJXaclazkaJKp8g6C4jdJ93sgIL5dhDZyl6NcbHS5yYlwUq/ud2rQ+T e5RKtGDXsdkXwf6k5YEf21T7wP3Y6+FBV1x+jePUyFEITNP6boNc0GcaM4T7cw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Tue, 23 Jan 2024 19:46:56 +0100 Subject: [PATCH v3 11/17] MIPS: mobileye: eyeq5: rename olb@e00000 to system-controller@e00000 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240123-mbly-clk-v3-11-392b010b8281@bootlin.com> References: <20240123-mbly-clk-v3-0-392b010b8281@bootlin.com> In-Reply-To: <20240123-mbly-clk-v3-0-392b010b8281@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com Node names should be generic. OLB, meaning "Other Logic Block", is a name specific to this platform. Change the node name to the generic and often-used "system-controller". Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index fd34c49af510..81497febcdee 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -100,7 +100,7 @@ uart2: serial@a00000 { clock-names = "uartclk", "apb_pclk"; }; - olb: olb@e00000 { + olb: system-controller@e00000 { compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd"; reg = <0 0xe00000 0x0 0x400>; reg-io-width = <4>; From patchwork Tue Jan 23 18:46:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 765459 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FA21129A67; Tue, 23 Jan 2024 18:47:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706035637; cv=none; b=T9L3HfyP9tj+v7LYZL4XPdjfPShJM3dec6NqW9jrJcdWbDhRHmqdXbbKXr5bO0ylcmjt4zpWd2R/b7QLatsgMq3ins+YmswnPr23EaJLKeG7fCqsjHv2BtFnqBljOxXE46ZGAsya64CPxb1k36UAQpt71KA2RbQ+Wy3ORX5w3sc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706035637; c=relaxed/simple; bh=np58IRjhFW7bYBVy2w4MIPqolSpepjXpSTUgPuEZ5mQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XcOkVQbctfsTNNmubXqYSs1gJYXMSs6jlLDKRt1ygygQ5Xv6auMtOgvaq256366F8iE35qKTFAWwSWf1PPWcltL1XihnQ4mm1Urj2WtPzXRvu0g6vafEemgWDf7YWx6faNHQY2W8256qFF9eZlBmlNbde5IKWHBjs0DjKZOd/Xc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=OhbzoIm6; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="OhbzoIm6" Received: by mail.gandi.net (Postfix) with ESMTPSA id 9652FC0015; Tue, 23 Jan 2024 18:47:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706035632; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WfzZ6wXyhDIq1XXUnEVc8wcAAEq672fxqz6YivLJP0E=; b=OhbzoIm6pS68nh5NWAh+V/0Y/KQxevCd0Vpi8kWzb2V5jrNq4OEeiLHFmJqLf8dztgsne2 VvVipAEyJZvAjf0VM02DvmcSuWVS+jqguo5uwneqpneNQTf94WdWLCLf9vw1dUUOA7vFkP 63e9eNVbP1/puEMaJ35NP3dBMyI8t3WXGLoXnTBDbtsi9puBj1qBx0bbuqscFkvRL8LoI5 WgB17z3nptFYF+cFAyGay//6MBMPwCNZgMCZ/9L3q5BaoGi92Vprl64nYtuCs6PwaHpFLe UK5M7PJiA+uiYoYFGtJFZIY53rXJXMv/vc0ze0yMAGzPvT5KXtBqu+fJydg1iQ== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Tue, 23 Jan 2024 19:46:58 +0100 Subject: [PATCH v3 13/17] MIPS: mobileye: eyeq5: use OLB clocks controller Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240123-mbly-clk-v3-13-392b010b8281@bootlin.com> References: <20240123-mbly-clk-v3-0-392b010b8281@bootlin.com> In-Reply-To: <20240123-mbly-clk-v3-0-392b010b8281@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com We add the clock controller inside the OLB syscon region and removed previous fixed devicetree nodes representing PLLs exposed by the clock controller. Two quirks are present: - The OLB node is moved prior to UARTs, as platform device probe scheduling is dependent on devicetree ordering. - The core0-timer-clk fixed clock is created to feed the GIC timer. It requires a clock earlier than platform bus type initialisation (and therefore platform device init). Signed-off-by: Théo Lebrun --- .../{eyeq5-fixed-clocks.dtsi => eyeq5-clocks.dtsi} | 54 +++++++--------------- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 9 +++- 2 files changed, 24 insertions(+), 39 deletions(-) diff --git a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi similarity index 88% rename from arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi rename to arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi index 78f5533a95c6..aa6db704a786 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi @@ -3,42 +3,20 @@ * Copyright 2023 Mobileye Vision Technologies Ltd. */ +#include + / { /* Fixed clock */ - pll_cpu: pll-cpu { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1500000000>; - }; - - pll_vdi: pll-vdi { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1280000000>; - }; - - pll_per: pll-per { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <2000000000>; - }; - - pll_ddr0: pll-ddr0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1857210000>; - }; - - pll_ddr1: pll-ddr1 { + xtal: xtal { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <1857210000>; + clock-frequency = <30000000>; }; /* PLL_CPU derivatives */ occ_cpu: occ-cpu { compatible = "fixed-factor-clock"; - clocks = <&pll_cpu>; + clocks = <&clocks EQ5C_PLL_CPU>; #clock-cells = <0>; clock-div = <1>; clock-mult = <1>; @@ -101,7 +79,7 @@ mem_clk: mem-clk { }; occ_isram: occ-isram { compatible = "fixed-factor-clock"; - clocks = <&pll_cpu>; + clocks = <&clocks EQ5C_PLL_CPU>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; @@ -115,7 +93,7 @@ isram_clk: isram-clk { /* gate ClkRstGen_isram */ }; occ_dbu: occ-dbu { compatible = "fixed-factor-clock"; - clocks = <&pll_cpu>; + clocks = <&clocks EQ5C_PLL_CPU>; #clock-cells = <0>; clock-div = <10>; clock-mult = <1>; @@ -130,7 +108,7 @@ si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */ /* PLL_VDI derivatives */ occ_vdi: occ-vdi { compatible = "fixed-factor-clock"; - clocks = <&pll_vdi>; + clocks = <&clocks EQ5C_PLL_VDI>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; @@ -144,7 +122,7 @@ vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */ }; occ_can_ser: occ-can-ser { compatible = "fixed-factor-clock"; - clocks = <&pll_vdi>; + clocks = <&clocks EQ5C_PLL_VDI>; #clock-cells = <0>; clock-div = <16>; clock-mult = <1>; @@ -158,7 +136,7 @@ can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */ }; i2c_ser_clk: i2c-ser-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_vdi>; + clocks = <&clocks EQ5C_PLL_VDI>; #clock-cells = <0>; clock-div = <20>; clock-mult = <1>; @@ -166,7 +144,7 @@ i2c_ser_clk: i2c-ser-clk { /* PLL_PER derivatives */ occ_periph: occ-periph { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <16>; clock-mult = <1>; @@ -225,7 +203,7 @@ gpio_clk: gpio-clk { }; emmc_sys_clk: emmc-sys-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <10>; clock-mult = <1>; @@ -233,7 +211,7 @@ emmc_sys_clk: emmc-sys-clk { }; ccf_ctrl_clk: ccf-ctrl-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; @@ -241,7 +219,7 @@ ccf_ctrl_clk: ccf-ctrl-clk { }; occ_mjpeg_core: occ-mjpeg-core { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; @@ -265,7 +243,7 @@ mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */ }; fcmu_a_clk: fcmu-a-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <20>; clock-mult = <1>; @@ -273,7 +251,7 @@ fcmu_a_clk: fcmu-a-clk { }; occ_pci_sys: occ-pci-sys { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 03e7e942ee22..935c095d1423 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -5,7 +5,7 @@ #include -#include "eyeq5-fixed-clocks.dtsi" +#include "eyeq5-clocks.dtsi" / { #address-cells = <2>; @@ -103,6 +103,13 @@ uart2: serial@a00000 { olb: system-controller@e00000 { compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd"; reg = <0 0xe00000 0x0 0x400>; + + clocks: clock-controller { + compatible = "mobileye,eyeq5-clk"; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "ref"; + }; }; gic: interrupt-controller@140000 { From patchwork Tue Jan 23 18:46:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 765458 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1831A129A97; Tue, 23 Jan 2024 18:47:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706035637; cv=none; b=PkGQM7hEceaJgnRyM7BWYLSRH1QUayeugQIpV4QmQ8cssh9aR/Ayor2a5WJccogSspTkUZuAYcODz+yIUa30x05EtTo6mKWUc47C5Kt88vL0gegl/lsR4KPIGbBoLplmbjikQkxeulV5BBWSgm0j2A6/kds9Dgom2C3m9yF8xHw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706035637; c=relaxed/simple; bh=BcYgSuGsmUgQc7+2j9PtwGdIZqvNCZsf9bcw5mP7bUc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IcbbJP25leLzaRECVe83VfNhE8A/HoyQCjEblNxkKF84f8FGTKewFgs3po4t2WZxHQ0OFatbDBJcOy2koEbqKVnX0XTuHzMGWdtYXqQ2Wz7k+KvPeG399T3AsTjklOjY2/Aph53dyDMUnlY4/ghLAd/WapITDS1RFJSlfypYqeE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=i9Q34Mml; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="i9Q34Mml" Received: by mail.gandi.net (Postfix) with ESMTPSA id 6ECAAC0016; Tue, 23 Jan 2024 18:47:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706035633; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qk8YOpcHtDGg66bCtfZqmVSEEO+Y3NAgtJEniv2d3iQ=; b=i9Q34MmlA7EiVXhBOYpjklbKnhDYR6ZjubDZjsRUHTOsDdOg9qJshHwbA4UA68mIrtjoub kNASSiZrw0yuoa0tH2eNf8Z/l91uru6JaiExiEQK6thB7/3UonJlQCWP0ZnS0hnuxZgFHg qm6EZpGohNm87JOAGOBmrNd7s/Ska68HQtVxYZ8oT2veefxcUt5Ylcyaw4KJ27jKIc7ZqV ibjQcF/klhM+7h5MnBgSvLCGg6LM5RZrUqGPTtp39Xxkjx8h1HeMjwtcFsJWNYfu/5uhUd eCuCaesZRYIboCx8QNUvq6Nv2eEoRtxyVKTO4ESxQNWRzwlDrVCPXVMUY8i5ZQ== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Tue, 23 Jan 2024 19:46:59 +0100 Subject: [PATCH v3 14/17] MIPS: mobileye: eyeq5: add OLB reset controller node Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240123-mbly-clk-v3-14-392b010b8281@bootlin.com> References: <20240123-mbly-clk-v3-0-392b010b8281@bootlin.com> In-Reply-To: <20240123-mbly-clk-v3-0-392b010b8281@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com Add the devicetree node for the reset controller on the Mobileye EyeQ5 platform. It appears as a subnode to the OLB syscon as its registers are located in this shared register region. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 935c095d1423..a246df6e3c85 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -110,6 +110,11 @@ clocks: clock-controller { clocks = <&xtal>; clock-names = "ref"; }; + + reset: reset-controller { + compatible = "mobileye,eyeq5-reset"; + #reset-cells = <2>; + }; }; gic: interrupt-controller@140000 { From patchwork Tue Jan 23 18:47:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 765457 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C255A12A15C; Tue, 23 Jan 2024 18:47:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706035638; cv=none; b=Y5Hb4C9dI2x4aW0M45YlV25FZG+8FMehPNLLIhcQoloDsXQ7X1f4HflRv+owIFISCxKmzrrUU/6z0S8UZ3BdNHSpX0p7JekXJkj3a/qtSR9L57xQImag2ymojCO4nh4xs5zUfuYjy92PJ4N0co792Yp+cNQdWgoI3fDQbXpCS1Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706035638; c=relaxed/simple; bh=CRl71IIRGChYj09LDs8MG3mlUeXntEyS2lM1Effj4pE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Q8Z3Vq1R2EuRYlN3wIeMRIXquiCAuJ2jIhJrlYtRZbbk4naG4LPkeo1Vt1j+ipGQMta9sBQ9Wv7n/O9oxvUlgBtBZOa7Xu8dY7NF63sCZIfLUu/Sk8vkV9E4HG+yyUjq/dc5velydey1XE5hekm/OLgmGb6U+HdUycHP4tEJbMY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=cEKsmENh; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="cEKsmENh" Received: by mail.gandi.net (Postfix) with ESMTPSA id 50091C000A; Tue, 23 Jan 2024 18:47:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706035634; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GdHSB87u5sD7QQGA0+EynSxKbm6bwp41S0X3AQVUPG8=; b=cEKsmENh7Gdycrf23pi7Tj0OuLskgCGYMllo546rTc/hjkELsx+yn2JF2EXtaAY1blnC9n Ezhlue8Z1PlRXBV7EqdI9uujXQ6o53eeBf8y28tkmFF9OORtg6udAb4a/sg0QO4uJVHFuy Ti/aHl6NFhduLRNR2nfB1+Qd+nD/Yp7bw2IHknufwWOT2d1a7ht3cTkhmp9YwbYZ1FJPXb 69uV0J6AuDp9yLxRpv9bEoXYbec9kBqacvelQSmWGNlYlSq29GTsMzyiCMFP6uM5PC5hZk GD5Laxwaue14ahU29uKCVqMDpFCB4PH2o7MOYLoyyU3RDi9lJiIvpqz408S/mg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Tue, 23 Jan 2024 19:47:00 +0100 Subject: [PATCH v3 15/17] MIPS: mobileye: eyeq5: add reset properties to uarts Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240123-mbly-clk-v3-15-392b010b8281@bootlin.com> References: <20240123-mbly-clk-v3-0-392b010b8281@bootlin.com> In-Reply-To: <20240123-mbly-clk-v3-0-392b010b8281@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com UART nodes have been added to the devicetree by the initial platform support patch series. Add reset properties now that the reset node is declared. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index a246df6e3c85..11cdbaed2b33 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -78,6 +78,7 @@ uart0: serial@800000 { interrupts = ; clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; + resets = <&reset 0 10>; }; uart1: serial@900000 { @@ -88,6 +89,7 @@ uart1: serial@900000 { interrupts = ; clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; + resets = <&reset 0 11>; }; uart2: serial@a00000 { @@ -98,6 +100,7 @@ uart2: serial@a00000 { interrupts = ; clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; + resets = <&reset 0 12>; }; olb: system-controller@e00000 { From patchwork Tue Jan 23 18:47:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 765456 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8359612AAF4; Tue, 23 Jan 2024 18:47:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706035640; cv=none; b=aHZbCbogJoAYbZyFzfii8qHIYKZ156Nmy8os5haXa0ZV0FFYhs7Vsi2A2FXrNct0V7RH9bo+DWuOaXGN5nAuWrK01oSdP7vEt6zLy/ePTI5kXzIz4J9B4oxTNMidoHrwcYZxh4cQw2fUk+fqIBnTZK2PBEd56g7ZdcVyNKPl2Mw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706035640; c=relaxed/simple; bh=yjp12oSxfxja7jh6fC7F+aeYuNS75B25MmED7rLtaBE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=o8n1dbuXyEYdhq1eVqWvTOjV3+xw4X3pAVV5Du8qi6HfZfmblwpXCFlK10V8EdvttMIq59aPGjPTSBpy0bMPIN9FK3oh3kmI3Dq+qmIWFW2QHiPyzJozvqvkjkzCENv6GeoRioKTw3MbtEva2XRu4YNu0JlUgtaXDZ4A5EkM4Js= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=mwtbmPbn; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="mwtbmPbn" Received: by mail.gandi.net (Postfix) with ESMTPSA id E52E0C000D; Tue, 23 Jan 2024 18:47:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706035635; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dCny+mSIAQq2p/t/iXy+uHmjfw0TgeBQHqm3tqR9vX8=; b=mwtbmPbnHEV8ihY4Nsm93+07vaoHgZHgbpN6eBU/T6yLf7ws9jHcuV5bPT5EZrJx9zyewO kjxpMtPpMUrcerqr+apQChN5GxKHgXdYuxeaUB0XTwBVyaIaACVsQqTBQwWVjIJnCGA41L WqfUI01cVLoiDIQidNCoPHGP5jj5uRgbqsWSJiCvY06l0XLBXXgFsJ/t/7OurUZuMojcxk Vc7Lwq4nbZdTfipYQE/b0R474+YZZdf8oM7WyjcXgnxpYJJ2yK88Uz+P7maZZ205bplll4 rV0YdAhnZx4F7LfW6gFqLOqVzbzTGAr6XjR3PMQVXC0cIKsaRn9ev6hpKch5oA== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Tue, 23 Jan 2024 19:47:02 +0100 Subject: [PATCH v3 17/17] MIPS: mobileye: eyeq5: add pinctrl properties to UART nodes Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240123-mbly-clk-v3-17-392b010b8281@bootlin.com> References: <20240123-mbly-clk-v3-0-392b010b8281@bootlin.com> In-Reply-To: <20240123-mbly-clk-v3-0-392b010b8281@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com UART nodes are present in the platform devicetree. Add pinctrl to them now that the pin controller is supported. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 05987c58ed73..bf06d7a801a2 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -79,6 +79,8 @@ uart0: serial@800000 { clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; resets = <&reset 0 10>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; }; uart1: serial@900000 { @@ -90,6 +92,8 @@ uart1: serial@900000 { clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; resets = <&reset 0 11>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; }; uart2: serial@a00000 { @@ -101,6 +105,8 @@ uart2: serial@a00000 { clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; resets = <&reset 0 12>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; }; olb: system-controller@e00000 {