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Tsirkin" , Igor Mammedov , Ani Sinha Subject: [PATCH v2 01/23] hw/acpi/cpu: Use CPUState typedef Date: Fri, 26 Jan 2024 23:03:43 +0100 Message-ID: <20240126220407.95022-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240126220407.95022-1-philmd@linaro.org> References: <20240126220407.95022-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=philmd@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org QEMU coding style recommend using structure typedefs: https://www.qemu.org/docs/master/devel/style.html#typedefs Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu --- include/hw/acpi/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h index bc901660fb..209e1773f8 100644 --- a/include/hw/acpi/cpu.h +++ b/include/hw/acpi/cpu.h @@ -19,7 +19,7 @@ #include "hw/hotplug.h" typedef struct AcpiCpuStatus { - struct CPUState *cpu; + CPUState *cpu; uint64_t arch_id; bool is_inserting; bool is_removing; From patchwork Fri Jan 26 22:03:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 766383 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp452440wrb; Fri, 26 Jan 2024 14:05:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IEsVeVsGgwKVXvnO+z9n/X0BnkhiGI+K4XUH/uBNys944N9g+Ar5wish9/ldYt512TUFdlo X-Received: by 2002:a05:622a:13ce:b0:42a:8634:6cb with SMTP id p14-20020a05622a13ce00b0042a863406cbmr800712qtk.53.1706306713007; Fri, 26 Jan 2024 14:05:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706306712; cv=none; d=google.com; s=arc-20160816; b=gBdQWmnAnEd+bic7gBQ59stUWOzr4fvZ5O4SIMEt5EEc+ZVqB8iLq90G2qgRMTNZMJ DmsoqM0Na6d32xSwCJW8ZqHH1Fd94x7rSy12uEgy799sYfPu6gj5H6gE1l1u11qDmSIW P9+YqgxHzgB150bxHI+Apf+YOu2FbZeq+E+eBM5Lq/k977vuTncDOh9fwxP6NBub2vXg G7Md1OemqUA0F9d2L0/IWnoiYTndGootuXtCuflYBl1qlCxL/0yGl9ulLSR7bb8+wMW7 TT6uqsiima1stlt4/Kldi9K0jnqVWkB5cpU6dvGN+2qHSmb7gNRjuJRBkPiphb6yTDgH FZqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=44vj1U77cG8ByngsPLkvtVP46j6F/SEPuSA1albtNLM=; fh=vjIQCdGIiQvlMQV4M7vu+NKSTn5p9Q4HADr8u1W/+iI=; b=QpfharxGnys9JNR4Cg/yOEHxoPG/WjTGbDBllP+JHWUmIpOp3Rb5ENScJUGqX1NbT2 JyD6GLkngiLcJa0nlY+F9IRLsLIoD5FdDepn+rfCdAoIFXk0tyobvP68LjXbH946kMtL sNFSMA6WNJpzOaEmnKeYGl6DRM435tWQhfu4WdJPJJ+HIEXtYeYpEF2FwGRqDKXakDsK moGLneCT4bd6rG5RXiGWNAhV2oaj7fSrQdU/dt37c0nzVKCwqBH6XRTT3k1Dsnt8ea/d cWWy2EcPxJncA5CzL+DDfjqu5c2uDXe4XZ36rlcF8IiSbS8fJqMd28qNLFGKGUJK85jA xlng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Qdg5POse; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- MAINTAINERS | 1 + scripts/coccinelle/cpu_env.cocci_template | 92 +++++++++++++++++++++++ 2 files changed, 93 insertions(+) create mode 100644 scripts/coccinelle/cpu_env.cocci_template diff --git a/MAINTAINERS b/MAINTAINERS index dfaca8323e..1d57130ff8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -157,6 +157,7 @@ F: accel/tcg/ F: accel/stubs/tcg-stub.c F: util/cacheinfo.c F: util/cacheflush.c +F: scripts/coccinelle/cpu_env.cocci_template F: scripts/decodetree.py F: docs/devel/decodetree.rst F: docs/devel/tcg* diff --git a/scripts/coccinelle/cpu_env.cocci_template b/scripts/coccinelle/cpu_env.cocci_template new file mode 100644 index 0000000000..462ed418bb --- /dev/null +++ b/scripts/coccinelle/cpu_env.cocci_template @@ -0,0 +1,92 @@ +/* + + Convert &ARCH_CPU(..)->env to use cpu_env(..). + + Rationale: ARCH_CPU() might be slow, being a QOM cast macro. + cpu_env() is its fast equivalent. + + SPDX-License-Identifier: GPL-2.0-or-later + SPDX-FileCopyrightText: Linaro Ltd 2024 + SPDX-FileContributor: Philippe Mathieu-Daudé + + Usage as of v8.2.0: + + $ for targetdir in target/*; do test -d $targetdir || continue; \ + export target=${targetdir:7}; \ + sed \ + -e "s/__CPUArchState__/$( \ + git grep -h --no-line-number '@env: #CPU.*State' \ + target/$target/cpu.h \ + | sed -n -e 's/.*\(CPU.*State\).\?/\1/p')/g" \ + -e "s/__ARCHCPU__/$( \ + git grep -h --no-line-number OBJECT_DECLARE_CPU_TYPE.*CPU \ + target/$target/cpu-qom.h \ + | sed -n -e 's/.*(\(.*\), .*, .*)/\1/p')/g" \ + -e "s/__ARCH_CPU__/$( \ + git grep -h --no-line-number OBJECT_DECLARE_CPU_TYPE.*CPU \ + target/$target/cpu-qom.h \ + | sed -n -e 's/.*(.*, .*, \(.*\))/\1/p')/g" \ + < scripts/coccinelle/cpu_env.cocci_template \ + > $TMPDIR/cpu_env_$target.cocci; \ + for dir in hw target/$target; do \ + spatch --macro-file scripts/cocci-macro-file.h \ + --sp-file $TMPDIR/cpu_env_$target.cocci \ + --keep-comments \ + --dir $dir \ + --in-place; \ + done; \ + done + +*/ + +/* Argument is CPUState* */ +@ CPUState_arg_used @ +CPUState *cs; +identifier cpu; +identifier env; +@@ +- __ARCHCPU__ *cpu = __ARCH_CPU__(cs); +- __CPUArchState__ *env = &cpu->env; ++ __CPUArchState__ *env = cpu_env(cs); + ... when != cpu + +/* + * Argument is not CPUState* but a related QOM object. + * CPU() is not a QOM macro but a cast (See commit 0d6d1ab499). + */ +@ depends on never CPUState_arg_used @ +identifier obj; +identifier cpu; +identifier env; +@@ +- __ARCHCPU__ *cpu = __ARCH_CPU__(obj); +- __CPUArchState__ *env = &cpu->env; ++ __CPUArchState__ *env = cpu_env(CPU(obj)); + ... when != cpu + +/* Both first_cpu/current_cpu are CPUState* */ +@@ +symbol first_cpu; +symbol current_cpu; +@@ +( +- CPU(first_cpu) ++ first_cpu +| +- CPU(current_cpu) ++ current_cpu +) + +/* When single use of 'env', call cpu_env() in place */ +@@ +type CPUArchState; +identifier env; +expression cs; +@@ + { +- CPUArchState *env = cpu_env(cs); + ... when != env +- env ++ cpu_env(cs) + ... when != env + } From patchwork Fri Jan 26 22:03:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 766387 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp452841wrb; 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Mechanical patch using the following Coccinelle spatch script: @@ type CPUArchState; identifier env; expression cs; @@ { - CPUArchState *env = cpu_env(cs); ... when != env - env + cpu_env(cs) ... when != env } Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/cpu-exec.c | 3 +-- linux-user/i386/cpu_loop.c | 4 ++-- target/hppa/mem_helper.c | 3 +-- target/hppa/translate.c | 3 +-- target/i386/nvmm/nvmm-all.c | 6 ++---- target/i386/whpx/whpx-all.c | 18 ++++++------------ target/loongarch/tcg/translate.c | 3 +-- target/rx/translate.c | 3 +-- target/sh4/op_helper.c | 4 +--- 9 files changed, 16 insertions(+), 31 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 67eda9865e..86206484f8 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -445,7 +445,6 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) static inline TranslationBlock * QEMU_DISABLE_CFI cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) { - CPUArchState *env = cpu_env(cpu); uintptr_t ret; TranslationBlock *last_tb; const void *tb_ptr = itb->tc.ptr; @@ -455,7 +454,7 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) } qemu_thread_jit_execute(); - ret = tcg_qemu_tb_exec(env, tb_ptr); + ret = tcg_qemu_tb_exec(cpu_env(cpu), tb_ptr); cpu->neg.can_do_io = true; qemu_plugin_disable_mem_helpers(cpu); /* diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index 42ecb4bf0a..92beb6830c 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -323,8 +323,8 @@ void cpu_loop(CPUX86State *env) static void target_cpu_free(void *obj) { - CPUArchState *env = cpu_env(obj); - target_munmap(env->gdt.base, sizeof(uint64_t) * TARGET_GDT_ENTRIES); + target_munmap(cpu_env(obj)->gdt.base, + sizeof(uint64_t) * TARGET_GDT_ENTRIES); g_free(obj); } diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 4fcc612754..bb85962d50 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -518,7 +518,6 @@ void HELPER(iitlbt_pa20)(CPUHPPAState *env, target_ulong r1, target_ulong r2) /* Purge (Insn/Data) TLB. */ static void ptlb_work(CPUState *cpu, run_on_cpu_data data) { - CPUHPPAState *env = cpu_env(cpu); vaddr start = data.target_ptr; vaddr end; @@ -532,7 +531,7 @@ static void ptlb_work(CPUState *cpu, run_on_cpu_data data) end = (vaddr)TARGET_PAGE_SIZE << (2 * end); end = start + end - 1; - hppa_flush_tlb_range(env, start, end); + hppa_flush_tlb_range(cpu_env(cpu), start, end); } /* This is local to the current cpu. */ diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3ef39b1bd7..5735335254 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3805,8 +3805,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) #ifndef CONFIG_USER_ONLY if (ctx->tb_flags & PSW_C) { - CPUHPPAState *env = cpu_env(ctx->cs); - int type = hppa_artype_for_page(env, ctx->base.pc_next); + int type = hppa_artype_for_page(cpu_env(ctx->cs), ctx->base.pc_next); /* If we could not find a TLB entry, then we need to generate an ITLB miss exception so the kernel will provide it. The resulting TLB fill operation will invalidate this TB and diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index cfdca91123..49a3a3b916 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -340,7 +340,6 @@ nvmm_get_registers(CPUState *cpu) static bool nvmm_can_take_int(CPUState *cpu) { - CPUX86State *env = cpu_env(cpu); AccelCPUState *qcpu = cpu->accel; struct nvmm_vcpu *vcpu = &qcpu->vcpu; struct nvmm_machine *mach = get_nvmm_mach(); @@ -349,7 +348,7 @@ nvmm_can_take_int(CPUState *cpu) return false; } - if (qcpu->int_shadow || !(env->eflags & IF_MASK)) { + if (qcpu->int_shadow || !(cpu_env(cpu)->eflags & IF_MASK)) { struct nvmm_x64_state *state = vcpu->state; /* Exit on interrupt window. */ @@ -645,13 +644,12 @@ static int nvmm_handle_halted(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - CPUX86State *env = cpu_env(cpu); int ret = 0; bql_lock(); if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && - (env->eflags & IF_MASK)) && + (cpu_env(cpu)->eflags & IF_MASK)) && !(cpu->interrupt_request & CPU_INTERRUPT_NMI)) { cpu->exception_index = EXCP_HLT; cpu->halted = true; diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index a7262654ac..31eec7048c 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -300,7 +300,6 @@ static SegmentCache whpx_seg_h2q(const WHV_X64_SEGMENT_REGISTER *hs) /* X64 Extended Control Registers */ static void whpx_set_xcrs(CPUState *cpu) { - CPUX86State *env = cpu_env(cpu); HRESULT hr; struct whpx_state *whpx = &whpx_global; WHV_REGISTER_VALUE xcr0; @@ -311,7 +310,7 @@ static void whpx_set_xcrs(CPUState *cpu) } /* Only xcr0 is supported by the hypervisor currently */ - xcr0.Reg64 = env->xcr0; + xcr0.Reg64 = cpu_env(cpu)->xcr0; hr = whp_dispatch.WHvSetVirtualProcessorRegisters( whpx->partition, cpu->cpu_index, &xcr0_name, 1, &xcr0); if (FAILED(hr)) { @@ -321,7 +320,6 @@ static void whpx_set_xcrs(CPUState *cpu) static int whpx_set_tsc(CPUState *cpu) { - CPUX86State *env = cpu_env(cpu); WHV_REGISTER_NAME tsc_reg = WHvX64RegisterTsc; WHV_REGISTER_VALUE tsc_val; HRESULT hr; @@ -345,7 +343,7 @@ static int whpx_set_tsc(CPUState *cpu) } } - tsc_val.Reg64 = env->tsc; + tsc_val.Reg64 = cpu_env(cpu)->tsc; hr = whp_dispatch.WHvSetVirtualProcessorRegisters( whpx->partition, cpu->cpu_index, &tsc_reg, 1, &tsc_val); if (FAILED(hr)) { @@ -556,7 +554,6 @@ static void whpx_set_registers(CPUState *cpu, int level) static int whpx_get_tsc(CPUState *cpu) { - CPUX86State *env = cpu_env(cpu); WHV_REGISTER_NAME tsc_reg = WHvX64RegisterTsc; WHV_REGISTER_VALUE tsc_val; HRESULT hr; @@ -569,14 +566,13 @@ static int whpx_get_tsc(CPUState *cpu) return -1; } - env->tsc = tsc_val.Reg64; + cpu_env(cpu)->tsc = tsc_val.Reg64; return 0; } /* X64 Extended Control Registers */ static void whpx_get_xcrs(CPUState *cpu) { - CPUX86State *env = cpu_env(cpu); HRESULT hr; struct whpx_state *whpx = &whpx_global; WHV_REGISTER_VALUE xcr0; @@ -594,7 +590,7 @@ static void whpx_get_xcrs(CPUState *cpu) return; } - env->xcr0 = xcr0.Reg64; + cpu_env(cpu)->xcr0 = xcr0.Reg64; } static void whpx_get_registers(CPUState *cpu) @@ -1400,8 +1396,7 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exit_context_valid) { if (cpu->vcpu_dirty) { /* The CPU registers have been modified by other parts of QEMU. */ - CPUArchState *env = cpu_env(cpu); - return env->eip; + return cpu_env(cpu)->eip; } else if (exit_context_valid) { /* * The CPU registers have not been modified by neither other parts @@ -1439,12 +1434,11 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exit_context_valid) static int whpx_handle_halt(CPUState *cpu) { - CPUX86State *env = cpu_env(cpu); int ret = 0; bql_lock(); if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && - (env->eflags & IF_MASK)) && + (cpu_env(cpu)->eflags & IF_MASK)) && !(cpu->interrupt_request & CPU_INTERRUPT_NMI)) { cpu->exception_index = EXCP_HLT; cpu->halted = true; diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c index 21f4db6fbd..7bb8cecab3 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -282,10 +282,9 @@ static uint64_t make_address_pc(DisasContext *ctx, uint64_t addr) static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { - CPULoongArchState *env = cpu_env(cs); DisasContext *ctx = container_of(dcbase, DisasContext, base); - ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next); + ctx->opcode = translator_ldl(cpu_env(cs), &ctx->base, ctx->base.pc_next); if (!decode(ctx, ctx->opcode)) { qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. " diff --git a/target/rx/translate.c b/target/rx/translate.c index c6ce717a95..1829a0b1cd 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2195,9 +2195,8 @@ static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { - CPURXState *env = cpu_env(cs); DisasContext *ctx = container_of(dcbase, DisasContext, base); - ctx->env = env; + ctx->env = cpu_env(cs); ctx->tb_flags = ctx->base.tb->flags; } diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 54d390fe1f..4559d0d376 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -29,9 +29,7 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - CPUSH4State *env = cpu_env(cs); - - env->tea = addr; + cpu_env(cs)->tea = addr; switch (access_type) { case MMU_INST_FETCH: case MMU_DATA_LOAD: From patchwork Fri Jan 26 22:03:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 766404 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp455130wrb; Fri, 26 Jan 2024 14:13:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IEfvIue+PI1fJB0MgTK5q5LuGA04UL8RPyAGuYbHIBA8HDiGp7iFLgd7fCtsdlCuW/iEozR X-Received: by 2002:a05:620a:29d1:b0:783:ce17:4c5d with SMTP id s17-20020a05620a29d100b00783ce174c5dmr526301qkp.104.1706307191789; Fri, 26 Jan 2024 14:13:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706307191; cv=none; d=google.com; s=arc-20160816; b=x/XwJuhwCthSOz0kTj2/Y0ceMIvt04JY4KEcacSQpGTD1Sgh1nC1yRBqXhkgS2Q7vV UMiDOaku9v2aL5XSitMWNbqpqPgCm0+ZAUN69foLTjJvPx620PsSqWJnjLljoP7y/5Dn KcV+Zb2+zj3dEdJ4bfqzJ7HsrJYS3EzONFNqFx6I/nKBmzJ3+ek4d1onHMTo2jdEBo6j J4YlDk9aseR2jZ7BUL9y/NeKdqtnB9OcNtmSuv9f6sCPaZ4BciJlYrkBgOtj3dCPaSot WnAgYc1VWRqvBL9gRarSNEO5ZSMRz4oiEu+SVWvH1T74I+0DqArDBhjAqNvtQYekXbLO maKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vZRGd7bldk8q+PytOQG4zQL+je/AXd973w95qInnP0Y=; fh=vjIQCdGIiQvlMQV4M7vu+NKSTn5p9Q4HADr8u1W/+iI=; b=A20d8IXjtOPRZZpjq3WnC5c/dqoTVorIDxURgRGKa8baUoY4A8Q89o/R6ou0JjTN0O dMtB1C3vGA8wf2Vp+xrd6x120UEosbUlv9j+ccmkxnha8m91vRhfOQL1UDWhgbUMK+nc zHPHgUSueg+GYkiOfek8+439qHfno23e46ETc3D4X/jvPtRIFinO6yIPHWZTkys5w2gW 4w2CU6A4j9ITCETftY6YH6pOMxK/GmMC4bPUt+iDXkoAs6TJkI1tqP/U9IgYunxxZOFB 6Q0yUVayxg/Hjz0TDfuwFLnIuMTbb8sWOQZ+rswMHXRyTucrxpP8ZmN/RYb7XBV8XZyY pM0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Uo8/h+hY"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/alpha/cpu.c | 31 +++++++------------------------ target/alpha/gdbstub.c | 6 ++---- target/alpha/helper.c | 12 ++++-------- target/alpha/mem_helper.c | 11 +++-------- 4 files changed, 16 insertions(+), 44 deletions(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index b8ed29e343..e21a8936c7 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -130,40 +130,27 @@ static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model) static void ev4_cpu_initfn(Object *obj) { - AlphaCPU *cpu = ALPHA_CPU(obj); - CPUAlphaState *env = &cpu->env; - - env->implver = IMPLVER_2106x; + cpu_env(CPU(obj))->implver = IMPLVER_2106x; } static void ev5_cpu_initfn(Object *obj) { - AlphaCPU *cpu = ALPHA_CPU(obj); - CPUAlphaState *env = &cpu->env; - - env->implver = IMPLVER_21164; + cpu_env(CPU(obj))->implver = IMPLVER_21164; } static void ev56_cpu_initfn(Object *obj) { - AlphaCPU *cpu = ALPHA_CPU(obj); - CPUAlphaState *env = &cpu->env; - - env->amask |= AMASK_BWX; + cpu_env(CPU(obj))->amask |= AMASK_BWX; } static void pca56_cpu_initfn(Object *obj) { - AlphaCPU *cpu = ALPHA_CPU(obj); - CPUAlphaState *env = &cpu->env; - - env->amask |= AMASK_MVI; + cpu_env(CPU(obj))->amask |= AMASK_MVI; } static void ev6_cpu_initfn(Object *obj) { - AlphaCPU *cpu = ALPHA_CPU(obj); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(CPU(obj)); env->implver = IMPLVER_21264; env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP; @@ -171,16 +158,12 @@ static void ev6_cpu_initfn(Object *obj) static void ev67_cpu_initfn(Object *obj) { - AlphaCPU *cpu = ALPHA_CPU(obj); - CPUAlphaState *env = &cpu->env; - - env->amask |= AMASK_CIX | AMASK_PREFETCH; + cpu_env(CPU(obj))->amask |= AMASK_CIX | AMASK_PREFETCH; } static void alpha_cpu_initfn(Object *obj) { - AlphaCPU *cpu = ALPHA_CPU(obj); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(CPU(obj)); env->lock_addr = -1; #if defined(CONFIG_USER_ONLY) diff --git a/target/alpha/gdbstub.c b/target/alpha/gdbstub.c index 0f8fa150f8..13694fd321 100644 --- a/target/alpha/gdbstub.c +++ b/target/alpha/gdbstub.c @@ -23,8 +23,7 @@ int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(cs); uint64_t val; CPU_DoubleU d; @@ -59,8 +58,7 @@ int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int alpha_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(cs); target_ulong tmp = ldtul_p(mem_buf); CPU_DoubleU d; diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 970c869771..eeed874e5a 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -298,8 +298,7 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(cs); target_ulong phys; int prot, fail; @@ -325,8 +324,7 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, void alpha_cpu_do_interrupt(CPUState *cs) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(cs); int i = cs->exception_index; if (qemu_loglevel_mask(CPU_LOG_INT)) { @@ -435,8 +433,7 @@ void alpha_cpu_do_interrupt(CPUState *cs) bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(cs); int idx = -1; /* We never take interrupts while in PALmode. */ @@ -487,8 +484,7 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags) "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", "t10", "t11", "ra", "t12", "at", "gp", "sp" }; - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(cs); int i; qemu_fprintf(f, "PC " TARGET_FMT_lx " PS %02x\n", diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index a39b52c5dd..872955f5e7 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -42,18 +42,14 @@ static void do_unaligned_access(CPUAlphaState *env, vaddr addr, uintptr_t retadd void alpha_cpu_record_sigbus(CPUState *cs, vaddr addr, MMUAccessType access_type, uintptr_t retaddr) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; - - do_unaligned_access(env, addr, retaddr); + do_unaligned_access(cpu_env(cs), addr, retaddr); } #else void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(cs); do_unaligned_access(env, addr, retaddr); cs->exception_index = EXCP_UNALIGN; @@ -67,8 +63,7 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(cs); env->trap_arg0 = addr; env->trap_arg1 = access_type == MMU_DATA_STORE ? 1 : 0; From patchwork Fri Jan 26 22:03:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 766393 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp453379wrb; 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_cpuif_common.c | 5 +---- target/arm/cpu.c | 19 +++++-------------- target/arm/debug_helper.c | 8 ++------ target/arm/gdbstub.c | 6 ++---- target/arm/gdbstub64.c | 6 ++---- target/arm/helper.c | 9 +++------ target/arm/hvf/hvf.c | 12 ++++-------- target/arm/kvm.c | 3 +-- target/arm/ptw.c | 3 +-- target/arm/tcg/cpu32.c | 3 +-- 10 files changed, 22 insertions(+), 52 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/intc/arm_gicv3_cpuif_common.c index ff1239f65d..bab3c3cdbd 100644 --- a/hw/intc/arm_gicv3_cpuif_common.c +++ b/hw/intc/arm_gicv3_cpuif_common.c @@ -15,8 +15,5 @@ void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) { - ARMCPU *arm_cpu = ARM_CPU(cpu); - CPUARMState *env = &arm_cpu->env; - - env->gicv3state = (void *)s; + cpu_env(cpu)->gicv3state = (void *)s; }; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 593695b424..3970223f33 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -51,8 +51,7 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); if (is_a64(env)) { env->pc = value; @@ -65,8 +64,7 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) static vaddr arm_cpu_get_pc(CPUState *cs) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); if (is_a64(env)) { return env->pc; @@ -994,19 +992,15 @@ static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) static bool arm_cpu_virtio_is_big_endian(CPUState *cs) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - cpu_synchronize_state(cs); - return arm_cpu_data_is_big_endian(env); + return arm_cpu_data_is_big_endian(cpu_env(cs)); } #endif static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) { - ARMCPU *ac = ARM_CPU(cpu); - CPUARMState *env = &ac->env; + CPUARMState *env = cpu_env(cpu); bool sctlr_b; if (is_a64(env)) { @@ -2428,10 +2422,7 @@ static Property arm_cpu_properties[] = { static const gchar *arm_gdb_arch_name(CPUState *cs) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - - if (arm_feature(env, ARM_FEATURE_IWMMXT)) { + if (arm_feature(cpu_env(cs), ARM_FEATURE_IWMMXT)) { return "iwmmxt"; } return "arm"; diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 7d856acddf..7bd5467414 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -468,8 +468,7 @@ void arm_debug_excp_handler(CPUState *cs) * Called by core code when a watchpoint or breakpoint fires; * need to check which one and raise the appropriate exception. */ - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); CPUWatchpoint *wp_hit = cs->watchpoint_hit; if (wp_hit) { @@ -757,9 +756,6 @@ void hw_breakpoint_update_all(ARMCPU *cpu) vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - /* * In BE32 system mode, target memory is stored byteswapped (on a * little-endian host system), and by the time we reach here (via an @@ -767,7 +763,7 @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) * to account for that, which means that watchpoints will not match. * Undo the adjustment here. */ - if (arm_sctlr_b(env)) { + if (arm_sctlr_b(cpu_env(cs))) { if (len == 1) { addr ^= 3; } else if (len == 2) { diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 28f546a5ff..dc6c29669c 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -40,8 +40,7 @@ typedef struct RegisterSysregXmlParam { int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); if (n < 16) { /* Core integer register. */ @@ -61,8 +60,7 @@ int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); uint32_t tmp; tmp = ldl_p(mem_buf); diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index d7b79a6589..b9f29b0a60 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -24,8 +24,7 @@ int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); if (n < 31) { /* Core integer register. */ @@ -45,8 +44,7 @@ int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); uint64_t tmp; tmp = ldq_p(mem_buf); diff --git a/target/arm/helper.c b/target/arm/helper.c index e068d35383..a504ed0612 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10900,8 +10900,7 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. */ uint32_t addr, mask; - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); switch (cs->exception_index) { case EXCP_UDEF: @@ -10979,8 +10978,7 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) static void arm_cpu_do_interrupt_aarch32(CPUState *cs) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); uint32_t addr; uint32_t mask; int new_mode; @@ -11479,8 +11477,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) #ifdef CONFIG_TCG static void tcg_handle_semihosting(CPUState *cs) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); if (is_a64(env)) { qemu_log_mask(CPU_LOG_INT, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index a537a5bc94..69211d0a60 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1004,8 +1004,7 @@ void hvf_kick_vcpu_thread(CPUState *cpu) static void hvf_raise_exception(CPUState *cpu, uint32_t excp, uint32_t syndrome) { - ARMCPU *arm_cpu = ARM_CPU(cpu); - CPUARMState *env = &arm_cpu->env; + CPUARMState *env = cpu_env(cpu); cpu->exception_index = excp; env->exception.target_el = 1; @@ -1483,8 +1482,7 @@ static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val) static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) { - ARMCPU *arm_cpu = ARM_CPU(cpu); - CPUARMState *env = &arm_cpu->env; + CPUARMState *env = cpu_env(cpu); trace_hvf_sysreg_write(reg, SYSREG_OP0(reg), @@ -2150,8 +2148,7 @@ static void hvf_put_gdbstub_debug_registers(CPUState *cpu) */ static void hvf_put_guest_debug_registers(CPUState *cpu) { - ARMCPU *arm_cpu = ARM_CPU(cpu); - CPUARMState *env = &arm_cpu->env; + CPUARMState *env = cpu_env(cpu); hv_return_t r = HV_SUCCESS; int i; @@ -2205,8 +2202,7 @@ static void hvf_arch_set_traps(void) void hvf_arch_update_guest_debug(CPUState *cpu) { - ARMCPU *arm_cpu = ARM_CPU(cpu); - CPUARMState *env = &arm_cpu->env; + CPUARMState *env = cpu_env(cpu); /* Check whether guest debugging is enabled */ cpu->accel->guest_debug_enabled = cpu->singlestep_enabled || diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 8f52b211f9..9e97c847b3 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1957,8 +1957,7 @@ int kvm_arch_destroy_vcpu(CPUState *cs) /* Callers must hold the iothread mutex lock */ static void kvm_inject_arm_sea(CPUState *c) { - ARMCPU *cpu = ARM_CPU(c); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(c); uint32_t esr; bool same_el; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5eb3577bcd..57a761ad68 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3528,8 +3528,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); ARMMMUIdx mmu_idx = arm_mmu_idx(env); ARMSecuritySpace ss = arm_security_space(env); S1Translate ptw = { diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index d9e0e2a4dd..c11c5c85c4 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -102,8 +102,7 @@ void aa32_max_features(ARMCPU *cpu) static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc = CPU_GET_CLASS(cs); - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; + CPUARMState *env = cpu_env(cs); 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/avr/cpu.c | 27 +++++++-------------------- target/avr/gdbstub.c | 6 ++---- target/avr/helper.c | 10 +++------- 3 files changed, 12 insertions(+), 31 deletions(-) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index f5cbdc4a8c..2ad24373a8 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -43,31 +43,22 @@ static vaddr avr_cpu_get_pc(CPUState *cs) static bool avr_cpu_has_work(CPUState *cs) { - AVRCPU *cpu = AVR_CPU(cs); - CPUAVRState *env = &cpu->env; - return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET)) - && cpu_interrupts_enabled(env); + && cpu_interrupts_enabled(cpu_env(cs)); } static void avr_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - AVRCPU *cpu = AVR_CPU(cs); - CPUAVRState *env = &cpu->env; - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); - env->pc_w = tb->pc / 2; /* internally PC points to words */ + cpu_env(cs)->pc_w = tb->pc / 2; /* internally PC points to words */ } static void avr_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - AVRCPU *cpu = AVR_CPU(cs); - CPUAVRState *env = &cpu->env; - - env->pc_w = data[0]; + cpu_env(cs)->pc_w = data[0]; } static void avr_cpu_reset_hold(Object *obj) @@ -165,8 +156,7 @@ static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - AVRCPU *cpu = AVR_CPU(cs); - CPUAVRState *env = &cpu->env; + CPUAVRState *env = cpu_env(cs); int i; qemu_fprintf(f, "\n"); @@ -276,8 +266,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) */ static void avr_avr5_initfn(Object *obj) { - AVRCPU *cpu = AVR_CPU(obj); - CPUAVRState *env = &cpu->env; + CPUAVRState *env = cpu_env(CPU(obj)); set_avr_feature(env, AVR_FEATURE_LPM); set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); @@ -305,8 +294,7 @@ static void avr_avr5_initfn(Object *obj) */ static void avr_avr51_initfn(Object *obj) { - AVRCPU *cpu = AVR_CPU(obj); - CPUAVRState *env = &cpu->env; + CPUAVRState *env = cpu_env(CPU(obj)); set_avr_feature(env, AVR_FEATURE_LPM); set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); @@ -335,8 +323,7 @@ static void avr_avr51_initfn(Object *obj) */ static void avr_avr6_initfn(Object *obj) { - AVRCPU *cpu = AVR_CPU(obj); - CPUAVRState *env = &cpu->env; + CPUAVRState *env = cpu_env(CPU(obj)); set_avr_feature(env, AVR_FEATURE_LPM); set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); diff --git a/target/avr/gdbstub.c b/target/avr/gdbstub.c index 150344d8b9..2eeee2bf4e 100644 --- a/target/avr/gdbstub.c +++ b/target/avr/gdbstub.c @@ -23,8 +23,7 @@ int avr_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - AVRCPU *cpu = AVR_CPU(cs); - CPUAVRState *env = &cpu->env; + CPUAVRState *env = cpu_env(cs); /* R */ if (n < 32) { @@ -53,8 +52,7 @@ int avr_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int avr_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - AVRCPU *cpu = AVR_CPU(cs); - CPUAVRState *env = &cpu->env; + CPUAVRState *env = cpu_env(cs); /* R */ if (n < 32) { diff --git a/target/avr/helper.c b/target/avr/helper.c index fdc9884ea0..eeca415c43 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -30,8 +30,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - AVRCPU *cpu = AVR_CPU(cs); - CPUAVRState *env = &cpu->env; + CPUAVRState *env = cpu_env(cs); /* * We cannot separate a skip from the next instruction, @@ -69,8 +68,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) void avr_cpu_do_interrupt(CPUState *cs) { - AVRCPU *cpu = AVR_CPU(cs); - CPUAVRState *env = &cpu->env; + CPUAVRState *env = cpu_env(cs); uint32_t ret = env->pc_w; int vector = 0; @@ -144,9 +142,7 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (probe) { page_size = 1; } else { - AVRCPU *cpu = AVR_CPU(cs); - CPUAVRState *env = &cpu->env; - env->fullacc = 1; + cpu_env(cs)->fullacc = 1; cpu_loop_exit_restore(cs, retaddr); } } From patchwork Fri Jan 26 22:03:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 766391 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp453334wrb; Fri, 26 Jan 2024 14:07:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IEnwToGLFhnzBfzCKHWH0Ia+VyN9xXVt/446/S00sSW1RPGDoOLEKfllP56LE/WPwMrJZwI X-Received: by 2002:a05:622a:2c5:b0:42a:88d1:1a59 with SMTP id a5-20020a05622a02c500b0042a88d11a59mr688463qtx.34.1706306850978; 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Iglesias" Subject: [PATCH v2 07/23] target/cris: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Fri, 26 Jan 2024 23:03:49 +0100 Message-ID: <20240126220407.95022-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240126220407.95022-1-philmd@linaro.org> References: <20240126220407.95022-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=philmd@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/cris/cpu.c | 5 +---- target/cris/gdbstub.c | 9 +++------ target/cris/helper.c | 12 ++++-------- target/cris/translate.c | 3 +-- 4 files changed, 9 insertions(+), 20 deletions(-) diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 9ba08e8b0c..8ec32fade8 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -142,10 +142,7 @@ static void cris_cpu_set_irq(void *opaque, int irq, int level) static void cris_disas_set_info(CPUState *cpu, disassemble_info *info) { - CRISCPU *cc = CRIS_CPU(cpu); - CPUCRISState *env = &cc->env; - - if (env->pregs[PR_VR] != 32) { + if (cpu_env(cpu)->pregs[PR_VR] != 32) { info->mach = bfd_mach_cris_v0_v10; info->print_insn = print_insn_crisv10; } else { diff --git a/target/cris/gdbstub.c b/target/cris/gdbstub.c index 25c0ca33a5..9e87069da8 100644 --- a/target/cris/gdbstub.c +++ b/target/cris/gdbstub.c @@ -23,8 +23,7 @@ int crisv10_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - CRISCPU *cpu = CRIS_CPU(cs); - CPUCRISState *env = &cpu->env; + CPUCRISState *env = cpu_env(cs); if (n < 15) { return gdb_get_reg32(mem_buf, env->regs[n]); @@ -55,8 +54,7 @@ int crisv10_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int cris_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - CRISCPU *cpu = CRIS_CPU(cs); - CPUCRISState *env = &cpu->env; + CPUCRISState *env = cpu_env(cs); uint8_t srs; srs = env->pregs[PR_SRS]; @@ -90,8 +88,7 @@ int cris_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int cris_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - CRISCPU *cpu = CRIS_CPU(cs); - CPUCRISState *env = &cpu->env; + CPUCRISState *env = cpu_env(cs); uint32_t tmp; if (n > 49) { diff --git a/target/cris/helper.c b/target/cris/helper.c index c0bf987e3e..1c3f86876f 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -53,8 +53,7 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - CRISCPU *cpu = CRIS_CPU(cs); - CPUCRISState *env = &cpu->env; + CPUCRISState *env = cpu_env(cs); struct cris_mmu_result res; int prot, miss; target_ulong phy; @@ -97,8 +96,7 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, void crisv10_cpu_do_interrupt(CPUState *cs) { - CRISCPU *cpu = CRIS_CPU(cs); - CPUCRISState *env = &cpu->env; + CPUCRISState *env = cpu_env(cs); int ex_vec = -1; D_LOG("exception index=%d interrupt_req=%d\n", @@ -159,8 +157,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) void cris_cpu_do_interrupt(CPUState *cs) { - CRISCPU *cpu = CRIS_CPU(cs); - CPUCRISState *env = &cpu->env; + CPUCRISState *env = cpu_env(cs); int ex_vec = -1; D_LOG("exception index=%d interrupt_req=%d\n", @@ -262,8 +259,7 @@ hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc = CPU_GET_CLASS(cs); - CRISCPU *cpu = CRIS_CPU(cs); - CPUCRISState *env = &cpu->env; + CPUCRISState *env = cpu_env(cs); bool ret = false; if (interrupt_request & CPU_INTERRUPT_HARD diff --git a/target/cris/translate.c b/target/cris/translate.c index b3974ba0bb..a935167f00 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3180,8 +3180,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - CRISCPU *cpu = CRIS_CPU(cs); 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/hppa/cpu.c | 8 ++------ target/hppa/int_helper.c | 8 ++------ target/hppa/mem_helper.c | 3 +-- 3 files changed, 5 insertions(+), 14 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 14e17fa9aa..3200de0998 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -106,11 +106,8 @@ void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - HPPACPU *cpu = HPPA_CPU(cs); - CPUHPPAState *env = &cpu->env; - cs->exception_index = EXCP_UNALIGN; - hppa_set_ior_and_isr(env, addr, MMU_IDX_MMU_DISABLED(mmu_idx)); + hppa_set_ior_and_isr(cpu_env(cs), addr, MMU_IDX_MMU_DISABLED(mmu_idx)); cpu_loop_exit_restore(cs, retaddr); } @@ -145,8 +142,7 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) static void hppa_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); - HPPACPU *cpu = HPPA_CPU(obj); - CPUHPPAState *env = &cpu->env; + CPUHPPAState *env = cpu_env(CPU(obj)); cs->exception_index = -1; cpu_hppa_loaded_fr0(env); diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index efe638b36e..d072ad2af7 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -99,8 +99,7 @@ void HELPER(write_eiem)(CPUHPPAState *env, target_ulong val) void hppa_cpu_do_interrupt(CPUState *cs) { - HPPACPU *cpu = HPPA_CPU(cs); - CPUHPPAState *env = &cpu->env; + CPUHPPAState *env = cpu_env(cs); int i = cs->exception_index; uint64_t old_psw; @@ -268,9 +267,6 @@ void hppa_cpu_do_interrupt(CPUState *cs) bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - HPPACPU *cpu = HPPA_CPU(cs); - CPUHPPAState *env = &cpu->env; - if (interrupt_request & CPU_INTERRUPT_NMI) { /* Raise TOC (NMI) interrupt */ cpu_reset_interrupt(cs, CPU_INTERRUPT_NMI); @@ -280,7 +276,7 @@ bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } /* If interrupts are requested and enabled, raise them. */ - if ((env->psw & PSW_I) && (interrupt_request & CPU_INTERRUPT_HARD)) { + if ((cpu_env(cs)->psw & PSW_I) && (interrupt_request & CPU_INTERRUPT_HARD)) { cs->exception_index = EXCP_EXT_INTERRUPT; hppa_cpu_do_interrupt(cs); return true; diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index bb85962d50..7e73b80788 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -357,8 +357,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, MMUAccessType type, int mmu_idx, bool probe, uintptr_t retaddr) { - HPPACPU *cpu = HPPA_CPU(cs); - CPUHPPAState *env = &cpu->env; + CPUHPPAState *env = cpu_env(cs); HPPATLBEntry *ent; int prot, excp, a_prot; hwaddr phys; From patchwork Fri Jan 26 22:03:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 766402 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp454858wrb; Fri, 26 Jan 2024 14:12:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IGAW1e1ifpV4L7d+W4n62ygtpySUEkO8qmVC1ChnsbUncP3odk23KTaFh2dxOQyBs4BZ0ce X-Received: by 2002:a05:6808:bc1:b0:3bd:bb13:4d1e with SMTP id o1-20020a0568080bc100b003bdbb134d1emr465264oik.101.1706307142828; Fri, 26 Jan 2024 14:12:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706307142; cv=none; d=google.com; s=arc-20160816; b=F3EQr76IbZkS6+Zc49OnDBwA8LjX0jVGmggK7O+o3Pbf8/nyGuO4L5uTWoBlnjYTGs +v8fba1qAa2z3x9lebzPtxTWy9FzwSMG50Dizb1sV2INujTMPsDqHE0pWfSIsGjIYaqr oInj1OiSeujU5K8vazbRv2SGPVdCsCv+iO5OWO9S8KQJq7Qxcr9yGeNeja/mbe4D6+RG imCmAqc433Ac5dv1mlaY6c5Jovt+6cDLkKGlM0AvH8CnYvaG5vLmiV0p86AO8pte5CBm hvjpm9iuPB2crNjX/bGYNjyTDwSRvg8lFPB/vEA7kGTPCySSvizGRPwdKK5Iz3eO/BEv nsUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3QQAYRUB98rUN30LN98QVH8jAOd3KtarXuPYMe2XkgM=; fh=p1XARvdnhCVn5KadEUXDOt8yvWK/iie0IWUXQLxA80k=; b=FUJ8uX78h3F8Meyq1PphAC1xujmQjkNyWygpt0hmfs+YQrdtod8w0Vh3T7qC4LquK0 rW+Wj+agBsCM3BvjXOT3Y07qraK6A35FcQyVLxiqh9S1vLOxJBKpoGWPkWrlU0xVuS7o XmIBQwa8jTfYNns1Hg5sLAqKVXTVPIvVnwQ1AV3xx+yV6llxqmsld5k/deIliUj5u710 7ScV1NEhJ9pCdSmUhpTox1UsuhiqC3ty4e4/RLqb8+QrhP/J/mwOIdZ3+PLjHxKNS/CA apnOfrKMptVOjagCIJpd4J9KvZAioGWXZ3JJMmX814v4bFxBMt7/pJoY/rV0mEyyLmPz NhQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=x9P2s2J3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 26 Jan 2024 14:05:04 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Thomas Huth , qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, Eduardo Habkost , kvm@vger.kernel.org, qemu-ppc@nongnu.org, Richard Henderson , Vladimir Sementsov-Ogievskiy , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Cameron Esfahani , Roman Bolshakov Subject: [PATCH v2 09/23] target/i386/hvf: Use CPUState typedef Date: Fri, 26 Jan 2024 23:03:51 +0100 Message-ID: <20240126220407.95022-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240126220407.95022-1-philmd@linaro.org> References: <20240126220407.95022-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=philmd@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org QEMU coding style recommend using structure typedefs: https://www.qemu.org/docs/master/devel/style.html#typedefs Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu --- target/i386/hvf/x86.h | 26 +++++++++++++------------- target/i386/hvf/x86_descr.h | 14 +++++++------- target/i386/hvf/x86_emu.h | 4 ++-- target/i386/hvf/x86_mmu.h | 6 +++--- target/i386/hvf/x86.c | 26 +++++++++++++------------- target/i386/hvf/x86_descr.c | 8 ++++---- target/i386/hvf/x86_mmu.c | 14 +++++++------- 7 files changed, 49 insertions(+), 49 deletions(-) diff --git a/target/i386/hvf/x86.h b/target/i386/hvf/x86.h index 947b98da41..3570f29aa9 100644 --- a/target/i386/hvf/x86.h +++ b/target/i386/hvf/x86.h @@ -248,30 +248,30 @@ typedef struct x68_segment_selector { #define BH(cpu) RH(cpu, R_EBX) /* deal with GDT/LDT descriptors in memory */ -bool x86_read_segment_descriptor(struct CPUState *cpu, +bool x86_read_segment_descriptor(CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel); -bool x86_write_segment_descriptor(struct CPUState *cpu, +bool x86_write_segment_descriptor(CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel); -bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc, +bool x86_read_call_gate(CPUState *cpu, struct x86_call_gate *idt_desc, int gate); /* helpers */ -bool x86_is_protected(struct CPUState *cpu); -bool x86_is_real(struct CPUState *cpu); -bool x86_is_v8086(struct CPUState *cpu); -bool x86_is_long_mode(struct CPUState *cpu); -bool x86_is_long64_mode(struct CPUState *cpu); -bool x86_is_paging_mode(struct CPUState *cpu); -bool x86_is_pae_enabled(struct CPUState *cpu); +bool x86_is_protected(CPUState *cpu); +bool x86_is_real(CPUState *cpu); +bool x86_is_v8086(CPUState *cpu); +bool x86_is_long_mode(CPUState *cpu); +bool x86_is_long64_mode(CPUState *cpu); +bool x86_is_paging_mode(CPUState *cpu); +bool x86_is_pae_enabled(CPUState *cpu); enum X86Seg; -target_ulong linear_addr(struct CPUState *cpu, target_ulong addr, enum X86Seg seg); -target_ulong linear_addr_size(struct CPUState *cpu, target_ulong addr, int size, +target_ulong linear_addr(CPUState *cpu, target_ulong addr, enum X86Seg seg); +target_ulong linear_addr_size(CPUState *cpu, target_ulong addr, int size, enum X86Seg seg); -target_ulong linear_rip(struct CPUState *cpu, target_ulong rip); +target_ulong linear_rip(CPUState *cpu, target_ulong rip); static inline uint64_t rdtscp(void) { diff --git a/target/i386/hvf/x86_descr.h b/target/i386/hvf/x86_descr.h index c356932fa4..9f06014b56 100644 --- a/target/i386/hvf/x86_descr.h +++ b/target/i386/hvf/x86_descr.h @@ -29,29 +29,29 @@ typedef struct vmx_segment { } vmx_segment; /* deal with vmstate descriptors */ -void vmx_read_segment_descriptor(struct CPUState *cpu, +void vmx_read_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, enum X86Seg seg); void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, enum X86Seg seg); -x68_segment_selector vmx_read_segment_selector(struct CPUState *cpu, +x68_segment_selector vmx_read_segment_selector(CPUState *cpu, enum X86Seg seg); -void vmx_write_segment_selector(struct CPUState *cpu, +void vmx_write_segment_selector(CPUState *cpu, x68_segment_selector selector, enum X86Seg seg); -uint64_t vmx_read_segment_base(struct CPUState *cpu, enum X86Seg seg); -void vmx_write_segment_base(struct CPUState *cpu, enum X86Seg seg, +uint64_t vmx_read_segment_base(CPUState *cpu, enum X86Seg seg); +void vmx_write_segment_base(CPUState *cpu, enum X86Seg seg, uint64_t base); -void x86_segment_descriptor_to_vmx(struct CPUState *cpu, +void x86_segment_descriptor_to_vmx(CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc); uint32_t vmx_read_segment_limit(CPUState *cpu, enum X86Seg seg); uint32_t vmx_read_segment_ar(CPUState *cpu, enum X86Seg seg); -void vmx_segment_to_x86_descriptor(struct CPUState *cpu, +void vmx_segment_to_x86_descriptor(CPUState *cpu, struct vmx_segment *vmx_desc, struct x86_segment_descriptor *desc); diff --git a/target/i386/hvf/x86_emu.h b/target/i386/hvf/x86_emu.h index 4b846ba80e..8bd97608c4 100644 --- a/target/i386/hvf/x86_emu.h +++ b/target/i386/hvf/x86_emu.h @@ -26,8 +26,8 @@ void init_emu(void); bool exec_instruction(CPUX86State *env, struct x86_decode *ins); -void load_regs(struct CPUState *cpu); -void store_regs(struct CPUState *cpu); +void load_regs(CPUState *cpu); +void store_regs(CPUState *cpu); void simulate_rdmsr(CPUX86State *env); void simulate_wrmsr(CPUX86State *env); diff --git a/target/i386/hvf/x86_mmu.h b/target/i386/hvf/x86_mmu.h index 9ae8a548de..9447ae072c 100644 --- a/target/i386/hvf/x86_mmu.h +++ b/target/i386/hvf/x86_mmu.h @@ -36,9 +36,9 @@ #define MMU_PAGE_US (1 << 2) #define MMU_PAGE_NX (1 << 3) -bool mmu_gva_to_gpa(struct CPUState *cpu, target_ulong gva, uint64_t *gpa); +bool mmu_gva_to_gpa(CPUState *cpu, target_ulong gva, uint64_t *gpa); -void vmx_write_mem(struct CPUState *cpu, target_ulong gva, void *data, int bytes); -void vmx_read_mem(struct CPUState *cpu, void *data, target_ulong gva, int bytes); +void vmx_write_mem(CPUState *cpu, target_ulong gva, void *data, int bytes); +void vmx_read_mem(CPUState *cpu, void *data, target_ulong gva, int bytes); #endif /* X86_MMU_H */ diff --git a/target/i386/hvf/x86.c b/target/i386/hvf/x86.c index 8ceea6398e..80e36136d0 100644 --- a/target/i386/hvf/x86.c +++ b/target/i386/hvf/x86.c @@ -46,7 +46,7 @@ return ar; }*/ -bool x86_read_segment_descriptor(struct CPUState *cpu, +bool x86_read_segment_descriptor(CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel) { @@ -76,7 +76,7 @@ bool x86_read_segment_descriptor(struct CPUState *cpu, return true; } -bool x86_write_segment_descriptor(struct CPUState *cpu, +bool x86_write_segment_descriptor(CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel) { @@ -99,7 +99,7 @@ bool x86_write_segment_descriptor(struct CPUState *cpu, return true; } -bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc, +bool x86_read_call_gate(CPUState *cpu, struct x86_call_gate *idt_desc, int gate) { target_ulong base = rvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_BASE); @@ -115,30 +115,30 @@ bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc, return true; } -bool x86_is_protected(struct CPUState *cpu) +bool x86_is_protected(CPUState *cpu) { uint64_t cr0 = rvmcs(cpu->accel->fd, VMCS_GUEST_CR0); return cr0 & CR0_PE_MASK; } -bool x86_is_real(struct CPUState *cpu) +bool x86_is_real(CPUState *cpu) { return !x86_is_protected(cpu); } -bool x86_is_v8086(struct CPUState *cpu) +bool x86_is_v8086(CPUState *cpu) { X86CPU *x86_cpu = X86_CPU(cpu); CPUX86State *env = &x86_cpu->env; return x86_is_protected(cpu) && (env->eflags & VM_MASK); } -bool x86_is_long_mode(struct CPUState *cpu) +bool x86_is_long_mode(CPUState *cpu) { return rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA; } -bool x86_is_long64_mode(struct CPUState *cpu) +bool x86_is_long64_mode(CPUState *cpu) { struct vmx_segment desc; vmx_read_segment_descriptor(cpu, &desc, R_CS); @@ -146,24 +146,24 @@ bool x86_is_long64_mode(struct CPUState *cpu) return x86_is_long_mode(cpu) && ((desc.ar >> 13) & 1); } -bool x86_is_paging_mode(struct CPUState *cpu) +bool x86_is_paging_mode(CPUState *cpu) { uint64_t cr0 = rvmcs(cpu->accel->fd, VMCS_GUEST_CR0); return cr0 & CR0_PG_MASK; } -bool x86_is_pae_enabled(struct CPUState *cpu) +bool x86_is_pae_enabled(CPUState *cpu) { uint64_t cr4 = rvmcs(cpu->accel->fd, VMCS_GUEST_CR4); return cr4 & CR4_PAE_MASK; } -target_ulong linear_addr(struct CPUState *cpu, target_ulong addr, X86Seg seg) +target_ulong linear_addr(CPUState *cpu, target_ulong addr, X86Seg seg) { return vmx_read_segment_base(cpu, seg) + addr; } -target_ulong linear_addr_size(struct CPUState *cpu, target_ulong addr, int size, +target_ulong linear_addr_size(CPUState *cpu, target_ulong addr, int size, X86Seg seg) { switch (size) { @@ -179,7 +179,7 @@ target_ulong linear_addr_size(struct CPUState *cpu, target_ulong addr, int size, return linear_addr(cpu, addr, seg); } -target_ulong linear_rip(struct CPUState *cpu, target_ulong rip) +target_ulong linear_rip(CPUState *cpu, target_ulong rip) { return linear_addr(cpu, rip, R_CS); } diff --git a/target/i386/hvf/x86_descr.c b/target/i386/hvf/x86_descr.c index c2d2e9ee84..5a9e8d307c 100644 --- a/target/i386/hvf/x86_descr.c +++ b/target/i386/hvf/x86_descr.c @@ -67,12 +67,12 @@ x68_segment_selector vmx_read_segment_selector(CPUState *cpu, X86Seg seg) return sel; } -void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector selector, X86Seg seg) +void vmx_write_segment_selector(CPUState *cpu, x68_segment_selector selector, X86Seg seg) { wvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector, selector.sel); } -void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment *desc, X86Seg seg) +void vmx_read_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, X86Seg seg) { desc->sel = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector); desc->base = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].base); @@ -90,7 +90,7 @@ void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, X86Se wvmcs(cpu->accel->fd, sf->ar_bytes, desc->ar); } -void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc) +void x86_segment_descriptor_to_vmx(CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc) { vmx_desc->sel = selector.sel; vmx_desc->base = x86_segment_base(desc); @@ -107,7 +107,7 @@ void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selector se desc->type; } -void vmx_segment_to_x86_descriptor(struct CPUState *cpu, struct vmx_segment *vmx_desc, struct x86_segment_descriptor *desc) +void vmx_segment_to_x86_descriptor(CPUState *cpu, struct vmx_segment *vmx_desc, struct x86_segment_descriptor *desc) { x86_set_segment_limit(desc, vmx_desc->limit); x86_set_segment_base(desc, vmx_desc->base); diff --git a/target/i386/hvf/x86_mmu.c b/target/i386/hvf/x86_mmu.c index 8cd08622a1..649074a7d2 100644 --- a/target/i386/hvf/x86_mmu.c +++ b/target/i386/hvf/x86_mmu.c @@ -49,7 +49,7 @@ struct gpt_translation { bool exec_access; }; -static int gpt_top_level(struct CPUState *cpu, bool pae) +static int gpt_top_level(CPUState *cpu, bool pae) { if (!pae) { return 2; @@ -73,7 +73,7 @@ static inline int pte_size(bool pae) } -static bool get_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, +static bool get_pt_entry(CPUState *cpu, struct gpt_translation *pt, int level, bool pae) { int index; @@ -95,7 +95,7 @@ static bool get_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, } /* test page table entry */ -static bool test_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, +static bool test_pt_entry(CPUState *cpu, struct gpt_translation *pt, int level, bool *is_large, bool pae) { uint64_t pte = pt->pte[level]; @@ -166,7 +166,7 @@ static inline uint64_t large_page_gpa(struct gpt_translation *pt, bool pae) -static bool walk_gpt(struct CPUState *cpu, target_ulong addr, int err_code, +static bool walk_gpt(CPUState *cpu, target_ulong addr, int err_code, struct gpt_translation *pt, bool pae) { int top_level, level; @@ -205,7 +205,7 @@ static bool walk_gpt(struct CPUState *cpu, target_ulong addr, int err_code, } -bool mmu_gva_to_gpa(struct CPUState *cpu, target_ulong gva, uint64_t *gpa) +bool mmu_gva_to_gpa(CPUState *cpu, target_ulong gva, uint64_t *gpa) { bool res; struct gpt_translation pt; @@ -225,7 +225,7 @@ bool mmu_gva_to_gpa(struct CPUState *cpu, target_ulong gva, uint64_t *gpa) return false; } -void vmx_write_mem(struct CPUState *cpu, target_ulong gva, void *data, int bytes) +void vmx_write_mem(CPUState *cpu, target_ulong gva, void *data, int bytes) { uint64_t gpa; @@ -246,7 +246,7 @@ void vmx_write_mem(struct CPUState *cpu, target_ulong gva, void *data, int bytes } } -void vmx_read_mem(struct CPUState *cpu, void *data, target_ulong gva, int bytes) +void vmx_read_mem(CPUState *cpu, void *data, target_ulong gva, int bytes) { uint64_t gpa; From patchwork Fri Jan 26 22:03:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 766394 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp453611wrb; Fri, 26 Jan 2024 14:08:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IHqzRKvVObbm1G8x8AmbhvMms0flQVxue+xKvYlxmPqQiWIn36i4T8itbj1BjauaJ0iO91X X-Received: by 2002:a05:622a:5c8:b0:429:f6bf:3b70 with SMTP id d8-20020a05622a05c800b00429f6bf3b70mr833577qtb.55.1706306909061; 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth --- target/m68k/cpu.c | 30 ++++++++++-------------------- target/m68k/gdbstub.c | 6 ++---- target/m68k/helper.c | 3 +-- target/m68k/m68k-semi.c | 6 ++---- target/m68k/op_helper.c | 11 +++-------- target/m68k/translate.c | 3 +-- 6 files changed, 19 insertions(+), 40 deletions(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 1421e77c2c..c122fd96fb 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -117,8 +117,7 @@ static ObjectClass *m68k_cpu_class_by_name(const char *cpu_model) static void m5206_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); m68k_set_feature(env, M68K_FEATURE_MOVEFROMSR_PRIV); @@ -127,8 +126,7 @@ static void m5206_cpu_initfn(Object *obj) /* Base feature set, including isns. for m68k family */ static void m68000_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68k_set_feature(env, M68K_FEATURE_M68K); m68k_set_feature(env, M68K_FEATURE_USP); @@ -141,8 +139,7 @@ static void m68000_cpu_initfn(Object *obj) */ static void m68010_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68000_cpu_initfn(obj); m68k_set_feature(env, M68K_FEATURE_M68010); @@ -161,8 +158,7 @@ static void m68010_cpu_initfn(Object *obj) */ static void m68020_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68010_cpu_initfn(obj); m68k_unset_feature(env, M68K_FEATURE_M68010); @@ -192,8 +188,7 @@ static void m68020_cpu_initfn(Object *obj) */ static void m68030_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68020_cpu_initfn(obj); m68k_unset_feature(env, M68K_FEATURE_M68020); @@ -219,8 +214,7 @@ static void m68030_cpu_initfn(Object *obj) */ static void m68040_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68030_cpu_initfn(obj); m68k_unset_feature(env, M68K_FEATURE_M68030); @@ -240,8 +234,7 @@ static void m68040_cpu_initfn(Object *obj) */ static void m68060_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68040_cpu_initfn(obj); m68k_unset_feature(env, M68K_FEATURE_M68040); @@ -254,8 +247,7 @@ static void m68060_cpu_initfn(Object *obj) static void m5208_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); m68k_set_feature(env, M68K_FEATURE_CF_ISA_APLUSC); @@ -267,8 +259,7 @@ static void m5208_cpu_initfn(Object *obj) static void cfv4e_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); m68k_set_feature(env, M68K_FEATURE_CF_ISA_B); @@ -281,8 +272,7 @@ static void cfv4e_cpu_initfn(Object *obj) static void any_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); m68k_set_feature(env, M68K_FEATURE_CF_ISA_B); diff --git a/target/m68k/gdbstub.c b/target/m68k/gdbstub.c index 1e5f033a12..15547e2313 100644 --- a/target/m68k/gdbstub.c +++ b/target/m68k/gdbstub.c @@ -23,8 +23,7 @@ int m68k_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(cs); if (n < 8) { /* D0-D7 */ @@ -50,8 +49,7 @@ int m68k_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int m68k_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(cs); uint32_t tmp; tmp = ldl_p(mem_buf); diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 14508dfa11..85f3cd1680 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -894,8 +894,7 @@ txfail: hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(cs); hwaddr phys_addr; int prot; int access_type; diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c index b4ffb70f8b..546cff2246 100644 --- a/target/m68k/m68k-semi.c +++ b/target/m68k/m68k-semi.c @@ -77,8 +77,7 @@ static int host_to_gdb_errno(int err) static void m68k_semi_u32_cb(CPUState *cs, uint64_t ret, int err) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(cs); target_ulong args = env->dregs[1]; if (put_user_u32(ret, args) || @@ -95,8 +94,7 @@ static void m68k_semi_u32_cb(CPUState *cs, uint64_t ret, int err) static void m68k_semi_u64_cb(CPUState *cs, uint64_t ret, int err) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(cs); target_ulong args = env->dregs[1]; if (put_user_u32(ret >> 32, args) || diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 1ce850bbc5..851cca640d 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -441,10 +441,7 @@ static void do_interrupt_all(CPUM68KState *env, int is_hw) void m68k_cpu_do_interrupt(CPUState *cs) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; - - do_interrupt_all(env, 0); + do_interrupt_all(cpu_env(cs), 0); } static inline void do_interrupt_m68k_hardirq(CPUM68KState *env) @@ -457,8 +454,7 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(cs); cpu_restore_state(cs, retaddr); @@ -511,8 +507,7 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(cs); if (interrupt_request & CPU_INTERRUPT_HARD && ((env->sr & SR_I) >> SR_I_SHIFT) < env->pending_level) { diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 4a0b0b2703..9688476a7b 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6108,8 +6108,7 @@ static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low) void m68k_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(cs); int i; uint16_t sr; for (i = 0; i < 8; i++) { From patchwork Fri Jan 26 22:03:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 766386 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp452836wrb; Fri, 26 Jan 2024 14:06:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IG5w3TUMM3ZQ70FlzN4uTKJUP3XqIAGWGqUiX7yzEjmmZvSIJi11AQdmueCBxDCsnMyTapO X-Received: by 2002:a05:620a:99a:b0:783:33d7:68ce with SMTP id x26-20020a05620a099a00b0078333d768cemr477147qkx.128.1706306772855; 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Iglesias" Subject: [PATCH v2 12/23] target/microblaze: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Fri, 26 Jan 2024 23:03:54 +0100 Message-ID: <20240126220407.95022-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240126220407.95022-1-philmd@linaro.org> References: <20240126220407.95022-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=philmd@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/microblaze/helper.c | 3 +-- target/microblaze/translate.c | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 98bdb82de8..bf955dd425 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -253,8 +253,7 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - CPUMBState *env = &cpu->env; + CPUMBState *env = cpu_env(cs); if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->msr & MSR_IE) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 49bfb4a0ea..1c6e4fcfe4 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1800,8 +1800,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - CPUMBState *env = &cpu->env; + CPUMBState *env = cpu_env(cs); uint32_t iflags; int i; From patchwork Fri Jan 26 22:03:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 766390 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp453274wrb; Fri, 26 Jan 2024 14:07:19 -0800 (PST) X-Google-Smtp-Source: AGHT+IGR0KOX3hgqjjIn4QeN9R2fRseeOiNBQKtRClLd4fXGWOK/aQxwbmprF0n6G5v/pmMpnDvP X-Received: by 2002:a05:620a:31a4:b0:783:cd67:a2f8 with SMTP id bi36-20020a05620a31a400b00783cd67a2f8mr569404qkb.22.1706306839026; Fri, 26 Jan 2024 14:07:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706306839; cv=none; d=google.com; s=arc-20160816; b=g6TmRlnwr5wURa3X+WDkpYwoYC7XJlog+5cbhvhEWAgUgIdE3F6ptfjwHR7jJ2aWZb DSl3RjappKR47l8Jfpfo/qHAzvJHMQdBHE/vXXu6LrWvOLdXC23SxJBEa0s9Qa3QA1pm dCo3yz2aA99rpFngs+yfKV63u+S/Ks5Mn/X88YRr+2b+rbhNW3moVa3MBrn3m35eU7g/ qElbNTucp7k6mwnAnzP3INIvV8F+KU05bUxGsUoaELPtcFXxR6U/1V+37WyKzzzU/Gi2 CPO8V9httrl7M73/Dhdml41Z13vxfnC2wZBs5GmkoA/vMpIBwdfNg5XEyDH7YPtxDWog m+Qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3J8OeebImZE8Elj1XiYwJgYjx4pjHQV9LzHXJrkifLg=; fh=sjjUIUAP8GU0sFT237usbTIjDQLfV5cBYW/XtzZnOp0=; b=C9pkIMjaOjL54xDXQ2NjTGM7cSERMYYWGegzevv1Z31/TWV0z+hWmZZ+8HylwndnTc jTTIXouCw67CniHK5OeoDYmt2xTkzoKiws89fVd0wy4ydl7vt3EGGNBsr+rHUQeK4cu9 TyQZotiDNODI6haVmm+7AMUdSxwysbidzkTkTsD+vUid60tsFvW0ZZWIerrUyCDmK7oo N73V3RCOZ8WCP8B4P8uoqLJ76KgFD5CEHpUEO7OCAZTH3APH635uF5kufDQX2XGOwXl/ Y1S4ZQQwzJ/tLdLm0cXhFt5jIZDVjW34PA+bY2VELbqv2SBlESrYdOEZGa7gJ7MCf56K RkLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oegaTsIe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 26 Jan 2024 14:05:29 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Thomas Huth , qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, Eduardo Habkost , kvm@vger.kernel.org, qemu-ppc@nongnu.org, Richard Henderson , Vladimir Sementsov-Ogievskiy , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH v2 13/23] target/mips: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Fri, 26 Jan 2024 23:03:55 +0100 Message-ID: <20240126220407.95022-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240126220407.95022-1-philmd@linaro.org> References: <20240126220407.95022-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=philmd@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/cpu.c | 11 +++------- target/mips/gdbstub.c | 6 ++---- target/mips/kvm.c | 27 +++++++++---------------- target/mips/sysemu/physaddr.c | 3 +-- target/mips/tcg/exception.c | 3 +-- target/mips/tcg/op_helper.c | 3 +-- target/mips/tcg/sysemu/special_helper.c | 3 +-- target/mips/tcg/sysemu/tlb_helper.c | 6 ++---- target/mips/tcg/translate.c | 3 +-- 9 files changed, 21 insertions(+), 44 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a0023edd43..d9c0c0dada 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -80,8 +80,7 @@ static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); int i; qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx @@ -137,8 +136,7 @@ static vaddr mips_cpu_get_pc(CPUState *cs) static bool mips_cpu_has_work(CPUState *cs) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); bool has_work = false; /* @@ -428,10 +426,7 @@ static void mips_cpu_reset_hold(Object *obj) static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) { - MIPSCPU *cpu = MIPS_CPU(s); - CPUMIPSState *env = &cpu->env; - - if (!(env->insn_flags & ISA_NANOMIPS32)) { + if (!(cpu_env(s)->insn_flags & ISA_NANOMIPS32)) { #if TARGET_BIG_ENDIAN info->print_insn = print_insn_big_mips; #else diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index 62d7b72407..169d47416a 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -25,8 +25,7 @@ int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); if (n < 32) { return gdb_get_regl(mem_buf, env->active_tc.gpr[n]); @@ -78,8 +77,7 @@ int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); target_ulong tmp; tmp = ldtul_p(mem_buf); diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 15d0cf9adb..6c52e59f55 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -63,8 +63,7 @@ int kvm_arch_irqchip_create(KVMState *s) int kvm_arch_init_vcpu(CPUState *cs) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); int ret = 0; qemu_add_vm_change_state_handler(kvm_mips_update_state, cs); @@ -460,8 +459,7 @@ static inline int kvm_mips_change_one_reg(CPUState *cs, uint64_t reg_id, */ static int kvm_mips_save_count(CPUState *cs) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); uint64_t count_ctl; int err, ret = 0; @@ -502,8 +500,7 @@ static int kvm_mips_save_count(CPUState *cs) */ static int kvm_mips_restore_count(CPUState *cs) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); uint64_t count_ctl; int err_dc, err, ret = 0; @@ -590,8 +587,7 @@ static void kvm_mips_update_state(void *opaque, bool running, RunState state) static int kvm_mips_put_fpu_registers(CPUState *cs, int level) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); int err, ret = 0; unsigned int i; @@ -670,8 +666,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int level) static int kvm_mips_get_fpu_registers(CPUState *cs) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); int err, ret = 0; unsigned int i; @@ -751,8 +746,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs) static int kvm_mips_put_cp0_registers(CPUState *cs, int level) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); int err, ret = 0; (void)level; @@ -974,8 +968,7 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level) static int kvm_mips_get_cp0_registers(CPUState *cs) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); int err, ret = 0; err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); @@ -1181,8 +1174,7 @@ static int kvm_mips_get_cp0_registers(CPUState *cs) int kvm_arch_put_registers(CPUState *cs, int level) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); struct kvm_regs regs; int ret; int i; @@ -1217,8 +1209,7 @@ int kvm_arch_put_registers(CPUState *cs, int level) int kvm_arch_get_registers(CPUState *cs) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); int ret = 0; struct kvm_regs regs; int i; diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c index 05990aa5bb..56380dfe6c 100644 --- a/target/mips/sysemu/physaddr.c +++ b/target/mips/sysemu/physaddr.c @@ -230,8 +230,7 @@ int get_physical_address(CPUMIPSState *env, hwaddr *physical, hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); hwaddr phys_addr; int prot; diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c index da49a93912..13275d1ded 100644 --- a/target/mips/tcg/exception.c +++ b/target/mips/tcg/exception.c @@ -79,8 +79,7 @@ void helper_wait(CPUMIPSState *env) void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); env->active_tc.PC = tb->pc; diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c index 98935b5e64..b57baa7ec1 100644 --- a/target/mips/tcg/op_helper.c +++ b/target/mips/tcg/op_helper.c @@ -279,8 +279,7 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); int error_code = 0; int excp; diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/sysemu/special_helper.c index 93276f789d..7934f2ea41 100644 --- a/target/mips/tcg/sysemu/special_helper.c +++ b/target/mips/tcg/sysemu/special_helper.c @@ -90,8 +90,7 @@ static void debug_post_eret(CPUMIPSState *env) bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && !(cs->tcg_cflags & CF_PCREL) && env->active_tc.PC != tb->pc) { diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index 4ede904800..6c48c4fa80 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -910,8 +910,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); hwaddr physical; int prot; int ret = TLBRET_BADADDR; @@ -1346,8 +1345,7 @@ void mips_cpu_do_interrupt(CPUState *cs) bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); if (cpu_mips_hw_interrupts_enabled(env) && cpu_mips_hw_interrupts_pending(env)) { diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 13e43fa3b6..e74b98de1c 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15628,8 +15628,7 @@ void mips_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); env->active_tc.PC = data[0]; env->hflags &= ~MIPS_HFLAG_BMASK; From patchwork Fri Jan 26 22:03:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 766397 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp453849wrb; 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/nios2/cpu.c | 15 +++------------ target/nios2/helper.c | 3 +-- target/nios2/nios2-semi.c | 6 ++---- 3 files changed, 6 insertions(+), 18 deletions(-) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index a27732bf2b..a2eaf35c1a 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -28,28 +28,19 @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value) { - Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; - - env->pc = value; + cpu_env(cs)->pc = value; } static vaddr nios2_cpu_get_pc(CPUState *cs) { - Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; - - return env->pc; + return cpu_env(cs)->pc; } static void nios2_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; - - env->pc = data[0]; + cpu_env(cs)->pc = data[0]; } static bool nios2_cpu_has_work(CPUState *cs) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index bb3b09e5a7..ac57121afc 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -287,8 +287,7 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; + CPUNios2State *env = cpu_env(cs); env->ctrl[CR_BADADDR] = addr; cs->exception_index = EXCP_UNALIGN; diff --git a/target/nios2/nios2-semi.c b/target/nios2/nios2-semi.c index 0b84fcb6b6..420702e293 100644 --- a/target/nios2/nios2-semi.c +++ b/target/nios2/nios2-semi.c @@ -75,8 +75,7 @@ static int host_to_gdb_errno(int err) static void nios2_semi_u32_cb(CPUState *cs, uint64_t ret, int err) { - Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; + CPUNios2State *env = cpu_env(cs); target_ulong args = env->regs[R_ARG1]; if (put_user_u32(ret, args) || @@ -93,8 +92,7 @@ static void nios2_semi_u32_cb(CPUState *cs, uint64_t ret, int err) static void nios2_semi_u64_cb(CPUState *cs, uint64_t ret, int err) { - Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; + CPUNios2State *env = cpu_env(cs); target_ulong args = env->regs[R_ARG1]; if (put_user_u32(ret >> 32, args) || From patchwork Fri Jan 26 22:03:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 766389 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp453183wrb; Fri, 26 Jan 2024 14:07:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IGnzipTPF9wzSY6x/vgZX/KUXyS+801ffKmPbfWDYHH42oKueXPjVn80UPSVsMURnD1AxcZ X-Received: by 2002:a05:6214:f28:b0:685:2e12:94cc with SMTP id iw8-20020a0562140f2800b006852e1294ccmr886032qvb.36.1706306823558; Fri, 26 Jan 2024 14:07:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706306823; cv=none; d=google.com; s=arc-20160816; b=A/OMWxoPlFN4cUF00acF4i/cVhKnP+9v0I7JY7j8KIkMBnFOGosDTXV5laicKLYNKy 42O3zb5kKw/Ivs3Ao0XO1FohHxiQcy4ZWBeXbelcYBfdF/kI03dF0tFFJ9a5sUhEKAuW KXw9MZig9j0NFl6BOuB63Qboi8lUtCCvnkZ6KIZZTTjdDz/CWC7dZltbmIqHLGr/fEFn k1/KJx5qW7OcuKXG89ObUcqogcgDHo2b57WNW6+QOQEirvoaZIHJg8Xmcr1PArhlCAzS RHa1aqBAgogcwqy532DmG9xZxmtuIKMveZ48P+m/RkXNUAqkic35eh6wTGHPn542elOh GNuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wkOEO96VeYz15t7MFpkcGQawVspurMDTqf/y8c7vhEo=; fh=/qojCzKzJzu17eSGMo9CTqxbtyYGaOrKOmbzUDrHuP4=; b=Bmvf/0o307R8BiYPGv7KMw8gGHDsNC90DSKV5M8UK3ezbVpXtNmTTx/op2+rusgD7Z Lw2NK9chrfXFSHHE7Gm0mO87VnQbhEcbGtCLq5nHB9thYbeBdrnwtTb6kaPp5ReiU3Vd xnuXMTN4XIZuyOUpNo5zdtJZt3erp7w3t6bj40EWiiNjHDZaHQgZuRIzWgz6C7u4yWwb CGlxj1HgEse6si5cfrXppySxrb4Ejcad9KqviXeAypTpu4nMo+g3g+AOdi9mpP7Ujz1Y h2mGQcwuHZRt7QGbwqiNL5IPGpqI+LFplYimz/EXrWJpfdX/Dp2QOd+ph6huhr3SSuk5 Coxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pTcaS6tJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/openrisc/gdbstub.c | 3 +-- target/openrisc/interrupt.c | 6 ++---- target/openrisc/translate.c | 3 +-- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c index d1074a0581..0cce8d4f92 100644 --- a/target/openrisc/gdbstub.c +++ b/target/openrisc/gdbstub.c @@ -23,8 +23,7 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - CPUOpenRISCState *env = &cpu->env; + CPUOpenRISCState *env = cpu_env(cs); if (n < 32) { return gdb_get_reg32(mem_buf, cpu_get_gpr(env, n)); diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index d4fdb8ce8e..b3b5b40577 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -29,8 +29,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) { - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - CPUOpenRISCState *env = &cpu->env; + CPUOpenRISCState *env = cpu_env(cs); int exception = cs->exception_index; env->epcr = env->pc; @@ -105,8 +104,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - CPUOpenRISCState *env = &cpu->env; + CPUOpenRISCState *env = cpu_env(cs); int idx = -1; if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) { diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index ecff4412b7..aff53c0065 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1668,8 +1668,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - CPUOpenRISCState *env = &cpu->env; + CPUOpenRISCState *env = cpu_env(cs); int i; qemu_fprintf(f, "PC=%08x\n", env->pc); From patchwork Fri Jan 26 22:03:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 766392 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp453343wrb; Fri, 26 Jan 2024 14:07:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IFeIoTxbu9CmROvW5/x0/dvG/F0f0VvrkktMpunWpRcfJQVNoiPoK2ddYM8KrrQzfqurhtX X-Received: by 2002:a05:6214:76c:b0:681:8f5d:1613 with SMTP id f12-20020a056214076c00b006818f5d1613mr497027qvz.128.1706306853813; Fri, 26 Jan 2024 14:07:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706306853; cv=none; d=google.com; s=arc-20160816; b=WVEUKgx9qDSDtY9O2o/VaQ86SHOjEFkCRWJGNY0YYaiPsfLmzLQZfYmBN6F5NIOraW Ah5FNY/os+EBTdM3cPkV6rd3uUOBVoKC3RJiC6lu4vr/+MMWfqz6CVInlCGZu+wOK864 uynJIGMixoiULEddLzQhltNdaNDEpfwa4YUwbcUZMMx0+0+4RhhcvsoN0U7sIPrctV12 hXaB6TlmkR7IvNgg8SKqUgYDP5VkanOL7t3eRNCz6+yNZf3SyNCUciFcKq3FjoVfxbNH 6GBI1RbakfR2uXrGS1rHNTOzzGeSuX/hXOlKUwv4OpZ7cx/BzcLfz6iG/WIJS0n4ihEo GBMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hrrpUHlY+apDJ+Bfl8GBcR4XdU7wA9f0hxfDSc9g5ew=; fh=0uTmhh8CZ0ElLKkgnDATgdub0eAKmdn9Je9K5Trh2n4=; b=YwIDJh3MiAJCEOM4lrvxU1T37DzXoMGIMzX3RzzKmoAguwUttMmQ9g2wSaWqif5p7B IwNOssou7o7Q8bJsd/BH3R/2QEk5yPuRuFUKgzkMkRwkkrw943KPZdNq5wSnK8AAKcuz 4fNiF/iFv4jwnt4yJhdOZEumfJfuhInlHHEY/YRjxdzuB3KFxfH6INwmRuLwcs5jPaMI 4RYJBwO81/3hRr26WRSrzQyUNFf66Wo+0TuUXmDqS468lxXK4MCDyY6SAXlRNVcnxKy+ CblIMGIgVMRYmVaflmcFzG8x83UnhlkuO0vhKfZQDOyFYTJrsplG7d22qEJxsVQ+hnG5 E2KA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LLURRiO+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 26 Jan 2024 14:05:47 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Thomas Huth , qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, Eduardo Habkost , kvm@vger.kernel.org, qemu-ppc@nongnu.org, Richard Henderson , Vladimir Sementsov-Ogievskiy , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?C?= =?utf-8?q?=C3=A9dric_Le_Goater?= , Nicholas Piggin , =?utf-8?b?RnLDqWTDqXJpYyBCYXJyYXQ=?= , Daniel Henrique Barboza , David Gibson , Harsh Prateek Bora Subject: [PATCH v2 16/23] target/ppc: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Fri, 26 Jan 2024 23:03:58 +0100 Message-ID: <20240126220407.95022-17-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240126220407.95022-1-philmd@linaro.org> References: <20240126220407.95022-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/ppc/mpc8544_guts.c | 3 +-- hw/ppc/pnv.c | 3 +-- hw/ppc/pnv_xscom.c | 5 +---- hw/ppc/ppce500_spin.c | 3 +-- hw/ppc/spapr.c | 3 +-- hw/ppc/spapr_caps.c | 6 ++---- target/ppc/cpu_init.c | 11 +++-------- target/ppc/excp_helper.c | 3 +-- target/ppc/gdbstub.c | 12 ++++-------- target/ppc/kvm.c | 6 ++---- target/ppc/ppc-qmp-cmds.c | 3 +-- target/ppc/user_only_helper.c | 3 +-- 12 files changed, 19 insertions(+), 42 deletions(-) diff --git a/hw/ppc/mpc8544_guts.c b/hw/ppc/mpc8544_guts.c index a26e83d048..e3540b0281 100644 --- a/hw/ppc/mpc8544_guts.c +++ b/hw/ppc/mpc8544_guts.c @@ -71,8 +71,7 @@ static uint64_t mpc8544_guts_read(void *opaque, hwaddr addr, unsigned size) { uint32_t value = 0; - PowerPCCPU *cpu = POWERPC_CPU(current_cpu); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(current_cpu); addr &= MPC8544_GUTS_MMIO_SIZE - 1; switch (addr) { diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0297871bdd..a202b377e1 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -2294,8 +2294,7 @@ static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); cpu_synchronize_state(cs); ppc_cpu_do_system_reset(cs); diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index 805b1d0c87..a17816d072 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -44,15 +44,12 @@ static void xscom_complete(CPUState *cs, uint64_t hmer_bits) * passed for the cpu, and no CPU completion is generated. */ if (cs) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; - /* * TODO: Need a CPU helper to set HMER, also handle generation * of HMIs */ cpu_synchronize_state(cs); - env->spr[SPR_HMER] |= hmer_bits; + cpu_env(cs)->spr[SPR_HMER] |= hmer_bits; } } diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index bbce63e8a4..dfbe759481 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -90,8 +90,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, static void spin_kick(CPUState *cs, run_on_cpu_data data) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); SpinInfo *curspin = data.host_ptr; hwaddr map_size = 64 * MiB; hwaddr map_start; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e8dabc8614..d7edfc2a1a 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3487,8 +3487,7 @@ static void spapr_machine_finalizefn(Object *obj) void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) { SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); cpu_synchronize_state(cs); /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index e889244e52..39edec0f84 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -194,8 +194,7 @@ static void cap_htm_apply(SpaprMachineState *spapr, uint8_t val, Error **errp) static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **errp) { ERRP_GUARD(); - PowerPCCPU *cpu = POWERPC_CPU(first_cpu); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(first_cpu); if (!val) { /* TODO: We don't support disabling vsx yet */ @@ -213,8 +212,7 @@ static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **errp) static void cap_dfp_apply(SpaprMachineState *spapr, uint8_t val, Error **errp) { ERRP_GUARD(); - PowerPCCPU *cpu = POWERPC_CPU(first_cpu); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(first_cpu); if (!val) { /* TODO: We don't support disabling dfp yet */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 344196a8ce..f39f426fa9 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7195,12 +7195,9 @@ static void ppc_cpu_reset_hold(Object *obj) static bool ppc_cpu_is_big_endian(CPUState *cs) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; - cpu_synchronize_state(cs); - return !FIELD_EX64(env->msr, MSR, LE); + return !FIELD_EX64(cpu_env(cs)->msr, MSR, LE); } static bool ppc_get_irq_stats(InterruptStatsProvider *obj, @@ -7287,8 +7284,7 @@ static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best) static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); if ((env->hflags >> MSR_LE) & 1) { info->endian = BFD_ENDIAN_LITTLE; @@ -7446,8 +7442,7 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) #define RGPL 4 #define RFPL 4 - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); int i; qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 2ec6429e36..fccfefa88e 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -2588,8 +2588,7 @@ void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector) bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); int interrupt; if ((interrupt_request & CPU_INTERRUPT_HARD) == 0) { diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index ec5731e5d6..fd986b1922 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -108,8 +108,7 @@ void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len) int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); uint8_t *mem_buf; int r = ppc_gdb_register_len(n); @@ -152,8 +151,7 @@ int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n) int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); uint8_t *mem_buf; int r = ppc_gdb_register_len_apple(n); @@ -206,8 +204,7 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n) int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); int r = ppc_gdb_register_len(n); if (!r) { @@ -253,8 +250,7 @@ int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) } int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); int r = ppc_gdb_register_len_apple(n); if (!r) { diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 26fa9d0575..7a0651b0af 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -546,8 +546,7 @@ static void kvm_sw_tlb_put(PowerPCCPU *cpu) static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); /* Init 'val' to avoid "uninitialised value" Valgrind warnings */ union { uint32_t u32; @@ -581,8 +580,7 @@ static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr) static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); union { uint32_t u32; uint64_t u64; diff --git a/target/ppc/ppc-qmp-cmds.c b/target/ppc/ppc-qmp-cmds.c index c0c137d9d7..9ac74f5c04 100644 --- a/target/ppc/ppc-qmp-cmds.c +++ b/target/ppc/ppc-qmp-cmds.c @@ -133,8 +133,7 @@ static int ppc_cpu_get_reg_num(const char *numstr, int maxnum, int *pregnum) int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval) { int i, regnum; - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); /* General purpose registers */ if ((qemu_tolower(name[0]) == 'r') && diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index 7ff76f7a06..a4d07a0d0d 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -27,8 +27,7 @@ void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address, MMUAccessType access_type, bool maperr, uintptr_t retaddr) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); int exception, error_code; /* From patchwork Fri Jan 26 22:03:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 766396 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp453778wrb; Fri, 26 Jan 2024 14:08:58 -0800 (PST) X-Google-Smtp-Source: AGHT+IFj4it+VPLwCot2k7O5XQt1/T2yrNk2YGIBbl7IBHcDEMW9i+5rgn3UCddhcSvVdrfLl0Pt X-Received: by 2002:a05:622a:f:b0:42a:2e93:b9fa with SMTP id x15-20020a05622a000f00b0042a2e93b9famr644322qtw.42.1706306938605; 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Fri, 26 Jan 2024 14:05:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Thomas Huth , qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, Eduardo Habkost , kvm@vger.kernel.org, qemu-ppc@nongnu.org, Richard Henderson , Vladimir Sementsov-Ogievskiy , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH v2 17/23] target/riscv: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Fri, 26 Jan 2024 23:03:59 +0100 Message-ID: <20240126220407.95022-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240126220407.95022-1-philmd@linaro.org> References: <20240126220407.95022-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/riscv/arch_dump.c | 6 ++---- target/riscv/cpu.c | 17 +++++------------ target/riscv/cpu_helper.c | 14 ++++---------- target/riscv/debug.c | 9 +++------ target/riscv/gdbstub.c | 6 ++---- target/riscv/kvm/kvm-cpu.c | 6 ++---- target/riscv/tcg/tcg-cpu.c | 9 +++------ target/riscv/translate.c | 3 +-- 8 files changed, 22 insertions(+), 48 deletions(-) diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c index 434c8a3dbb..994709647f 100644 --- a/target/riscv/arch_dump.c +++ b/target/riscv/arch_dump.c @@ -68,8 +68,7 @@ int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, DumpState *s) { struct riscv64_note note; - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(cs); int ret, i = 0; const char name[] = "CORE"; @@ -137,8 +136,7 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, DumpState *s) { struct riscv32_note note; - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(cs); int ret, i; const char name[] = "CORE"; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8cbfc7e781..fe21393655 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -419,8 +419,7 @@ static void riscv_any_cpu_init(Object *obj) static void riscv_max_cpu_init(Object *obj) { - RISCVCPU *cpu = RISCV_CPU(obj); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(CPU(obj)); RISCVMXL mlx = MXL_RV64; #ifdef TARGET_RISCV32 @@ -828,8 +827,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) static void riscv_cpu_set_pc(CPUState *cs, vaddr value) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(cs); if (env->xl == MXL_RV32) { env->pc = (int32_t)value; @@ -840,8 +838,7 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value) static vaddr riscv_cpu_get_pc(CPUState *cs) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(cs); /* Match cpu_get_tb_cpu_state. */ if (env->xl == MXL_RV32) { @@ -853,8 +850,7 @@ static vaddr riscv_cpu_get_pc(CPUState *cs) static bool riscv_cpu_has_work(CPUState *cs) { #ifndef CONFIG_USER_ONLY - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(cs); /* * Definition of the WFI instruction requires it to ignore the privilege * mode and delegation registers, but respect individual enables @@ -1642,10 +1638,7 @@ static void rva22s64_profile_cpu_init(Object *obj) static const gchar *riscv_gdb_arch_name(CPUState *cs) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - - switch (riscv_cpu_mxl(env)) { + switch (riscv_cpu_mxl(cpu_env(cs))) { case MXL_RV32: return "riscv:rv32"; case MXL_RV64: diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c7cc7eb423..9d4798b841 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -493,9 +493,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - int interruptno = riscv_cpu_local_irq_pending(env); + int interruptno = riscv_cpu_local_irq_pending(cpu_env(cs)); if (interruptno >= 0) { cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; riscv_cpu_do_interrupt(cs); @@ -1223,8 +1221,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(cs); if (access_type == MMU_DATA_STORE) { cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; @@ -1244,8 +1241,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(cs); switch (access_type) { case MMU_INST_FETCH: cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; @@ -1631,9 +1627,7 @@ static target_ulong riscv_transformed_insn(CPURISCVState *env, void riscv_cpu_do_interrupt(CPUState *cs) { #if !defined(CONFIG_USER_ONLY) - - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(cs); bool write_gva = false; uint64_t s; diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 4945d1a1f2..c8df9812be 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -757,8 +757,7 @@ target_ulong tinfo_csr_read(CPURISCVState *env) void riscv_cpu_debug_excp_handler(CPUState *cs) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(cs); if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { @@ -773,8 +772,7 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) bool riscv_cpu_debug_check_breakpoint(CPUState *cs) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(cs); CPUBreakpoint *bp; target_ulong ctrl; target_ulong pc; @@ -832,8 +830,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(cs); target_ulong ctrl; target_ulong addr; int trigger_type; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 58b3ace0fe..999d815b34 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -49,8 +49,7 @@ static const struct TypeSize vec_lanes[] = { int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(cs); target_ulong tmp; if (n < 32) { @@ -75,8 +74,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(cs); int length = 0; target_ulong tmp; diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 680a729cd8..cf0cae813b 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -171,8 +171,7 @@ static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, { KVMCPUConfig *misa_ext_cfg = opaque; target_ulong misa_bit = misa_ext_cfg->offset; - RISCVCPU *cpu = RISCV_CPU(obj); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(CPU(obj)); bool value = env->misa_ext_mask & misa_bit; visit_type_bool(v, name, &value, errp); @@ -184,8 +183,7 @@ static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, { KVMCPUConfig *misa_ext_cfg = opaque; target_ulong misa_bit = misa_ext_cfg->offset; - RISCVCPU *cpu = RISCV_CPU(obj); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(CPU(obj)); bool value, host_bit; if (!visit_type_bool(v, name, &value, errp)) { diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 994ca1cdf9..c7c4d9ac92 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -92,8 +92,7 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { if (!(tb_cflags(tb) & CF_PCREL)) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(cs); RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); @@ -110,8 +109,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(cs); RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); target_ulong pc; @@ -1030,8 +1028,7 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, { const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; target_ulong misa_bit = misa_ext_cfg->misa_bit; - RISCVCPU *cpu = RISCV_CPU(obj); - CPURISCVState *env = &cpu->env; + CPURISCVState *env = cpu_env(CPU(obj)); bool value; value = env->misa_ext & misa_bit; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 071fbad7ef..e94fb107e0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1265,8 +1265,7 @@ static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu, FILE *logfile) { #ifndef CONFIG_USER_ONLY - RISCVCPU *rvcpu = RISCV_CPU(cpu); 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[209.51.188.17]) by mx.google.com with ESMTPS id o22-20020a05620a111600b0078321c60d62si2158062qkk.762.2024.01.26.14.10.42 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jan 2024 14:10:42 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FaMf0o5E; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rTULQ-0003U0-U8; Fri, 26 Jan 2024 17:06:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rTUKw-0001xI-IW for qemu-devel@nongnu.org; Fri, 26 Jan 2024 17:06:10 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rTUKs-0004R5-B9 for qemu-devel@nongnu.org; Fri, 26 Jan 2024 17:06:08 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-40ee82d040dso9921965e9.3 for ; Fri, 26 Jan 2024 14:06:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706306761; x=1706911561; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1Fp9tWfUnWpTWSY0wSSNV5XB5wPrgNqsnYE0Bp5WmMs=; b=FaMf0o5ELztjZZjY0qxxwlGRIwT8Pe+zfZjIqDoPSDmX4nfIA6CQh2CxJO6btaabAi ygzNvz/1Ft7F0mTk4cTgQ+phOHFzlmKtSVCtFjOqSUbZotquJ7e75jwmO/Bt1Mm/qNy6 3fHRiMp0FAxIThUk3lphL1NiQRXfzOIol6FiaZqW3TG2kHbagkdgWmAQW+kJJRlLeK4p XtQ9G3iqORnzztKZtHuS9pU+dtvfVMGUIYRr1t4yLNgwtyXIUtus5ij1/YdiT66k1HeK Unv/H8gWiFtZdpCu7WmqnCsUcQZcRm454YXr52J7xJ2GyZQ41IM51E9RFxZ47rI5cmIa jV2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706306761; x=1706911561; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1Fp9tWfUnWpTWSY0wSSNV5XB5wPrgNqsnYE0Bp5WmMs=; b=G3SEx84ZgobYV5HcVIK9rUxhmFEua9Qkv3SjelDcgN/vCXSfI9dNHfS8bOLZva0qwY 8MMq9BLD8+1SMCbKwH6RHht2pFCx69lFouznmPOOeX3E0klFFKnexw2bH2Hd72aeTR8a U4XGUd6qd/08SxMsI4RBrz0h9ATKAZhE/kBelo4RP1gJb7rKc5Ty/SL1lFkBSwKiD56O zw2toZrn1yAH0PmT2OzAB/vgGClypycWXBqhZVkirwQ1/l3cYZV2pWvxIpUlLK3g4Y3z dU7CNzapwInug6tDZgUQ8J4ivrU1e/RvFu0E9J8qV+2uX6aAVMKd2PfAuUnKLJrgARbr QQkw== X-Gm-Message-State: AOJu0YxKiH824Aw9aIW+yY2gR0Ctes1nDrZS1A86OscZYEt0jxPoZhCO VGrMTC9H12gL80R+n6mszYGQQlwoGh/OXtAVl0Qdb6e8tNC1RLcS0vM2XMX8hLcbDhBUqQ72nhI S X-Received: by 2002:a05:600c:5187:b0:40e:d44a:ca9c with SMTP id fa7-20020a05600c518700b0040ed44aca9cmr330302wmb.48.1706306761345; Fri, 26 Jan 2024 14:06:01 -0800 (PST) Received: from m1x-phil.lan ([176.176.142.39]) by smtp.gmail.com with ESMTPSA id bi19-20020a05600c3d9300b0040ee51f1025sm1819887wmb.43.2024.01.26.14.05.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 26 Jan 2024 14:06:00 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Thomas Huth , qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, Eduardo Habkost , kvm@vger.kernel.org, qemu-ppc@nongnu.org, Richard Henderson , Vladimir Sementsov-Ogievskiy , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Yoshinori Sato Subject: [PATCH v2 18/23] target/rx: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Fri, 26 Jan 2024 23:04:00 +0100 Message-ID: <20240126220407.95022-19-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240126220407.95022-1-philmd@linaro.org> References: <20240126220407.95022-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/rx/gdbstub.c | 6 ++---- target/rx/helper.c | 6 ++---- target/rx/translate.c | 3 +-- 3 files changed, 5 insertions(+), 10 deletions(-) diff --git a/target/rx/gdbstub.c b/target/rx/gdbstub.c index d7e0e6689b..f222bf003b 100644 --- a/target/rx/gdbstub.c +++ b/target/rx/gdbstub.c @@ -21,8 +21,7 @@ int rx_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - RXCPU *cpu = RX_CPU(cs); - CPURXState *env = &cpu->env; + CPURXState *env = cpu_env(cs); switch (n) { case 0 ... 15: @@ -53,8 +52,7 @@ int rx_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int rx_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - RXCPU *cpu = RX_CPU(cs); - CPURXState *env = &cpu->env; + CPURXState *env = cpu_env(cs); uint32_t psw; switch (n) { case 0 ... 15: diff --git a/target/rx/helper.c b/target/rx/helper.c index dad5fb4976..80912e8dcb 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -45,8 +45,7 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte) #define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR) void rx_cpu_do_interrupt(CPUState *cs) { - RXCPU *cpu = RX_CPU(cs); - CPURXState *env = &cpu->env; + CPURXState *env = cpu_env(cs); int do_irq = cs->interrupt_request & INT_FLAGS; uint32_t save_psw; @@ -122,8 +121,7 @@ void rx_cpu_do_interrupt(CPUState *cs) bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - RXCPU *cpu = RX_CPU(cs); - CPURXState *env = &cpu->env; + CPURXState *env = cpu_env(cs); int accept = 0; /* hardware interrupt (Normal) */ if ((interrupt_request & CPU_INTERRUPT_HARD) && diff --git a/target/rx/translate.c b/target/rx/translate.c index 1829a0b1cd..26aaf7a6b5 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -131,8 +131,7 @@ static int bdsp_s(DisasContext *ctx, int d) void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - RXCPU *cpu = RX_CPU(cs); - CPURXState *env = &cpu->env; + CPURXState *env = cpu_env(cs); int i; uint32_t psw; From patchwork Fri Jan 26 22:04:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 766395 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp453635wrb; Fri, 26 Jan 2024 14:08:33 -0800 (PST) X-Google-Smtp-Source: AGHT+IGr/leIK3aC0Dn6hSglejlzMedzu0QOCsRVe0jsfrm+UE7f2YpTV5XD+d8jOUtTTGTJnQ+t X-Received: by 2002:a05:620a:618e:b0:783:9b1a:d4eb with SMTP id or14-20020a05620a618e00b007839b1ad4ebmr537071qkn.35.1706306913134; Fri, 26 Jan 2024 14:08:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706306913; cv=none; d=google.com; s=arc-20160816; b=TgmIOGc7PFbW9wHU/HdTjvfxsc9bZBsy4H/Ig0KXdbnV2o5xyH/EITB6JnkS7JtPzB BlM+67UYfGjBe982/+11oz7wD2MUEIO0aBt6/JihtxXNO+1KT6rU0utvYb9hgGFgKjdM R5cSRe5SEIZYaEpjE97yY1dwkRmRwC38GiYAN65uvn1dqehjJN4pvqGVIMDCNaTlkLVk cTr0enrBbVQ8ipPwFrSfT01trQbLXd8jPeO0s8O99EKNqMZVKHsbuUb5+mdtlTUdQi9l Hgb1XrJl2UpJRFSSjvG4197N/0UBNURqjRx/JAvoAsX5P8PweAMNfa3FyWfcMS+zSuNT UIuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zizmHElFAIvWicITNbOdvMqLrgaV6VK2Xkw5hMOGCk4=; fh=RNOgpSlp5ZOB9sTVZ6jYOqp9uF9PNrrPqTHe/Ih7Dxw=; b=vZ9J84meo3anR4Z+GOK7Llfb79NVcern+NR+5hRuI6J2mzfFXZwBM9+nuoVEe5r5vf cLa1ggZOIvAe4IZIIsBNE6indswsFajoVpbRlcRhJ6em6undlvZvH6PdQZR36On6TNyB P5X0eZh1T4+IFlsG3wnlVhhrs50wNsV69ApWQ9jZG/o3JzsHwadnvkWjZnQKA2hE1ALw MdsNLwGAFKXtqrEezMmoOnhKvl7Kuw73dsm5/nNlg8RyuAZeFFeu58RQ/QqXAASuJb0C Pv9yGH6Fo8enTtU3GCUsN1SZllaS/1YHi6EScvH9HeOgS2zD2c0mtVZu3GgIAlax8d6O AX9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nFQXn2wn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 26 Jan 2024 14:06:07 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Thomas Huth , qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, Eduardo Habkost , kvm@vger.kernel.org, qemu-ppc@nongnu.org, Richard Henderson , Vladimir Sementsov-Ogievskiy , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , David Hildenbrand , Ilya Leoshkevich , Halil Pasic , Christian Borntraeger Subject: [PATCH v2 19/23] target/s390x: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Fri, 26 Jan 2024 23:04:01 +0100 Message-ID: <20240126220407.95022-20-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240126220407.95022-1-philmd@linaro.org> References: <20240126220407.95022-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth --- target/s390x/cpu-dump.c | 3 +-- target/s390x/gdbstub.c | 6 ++---- target/s390x/helper.c | 3 +-- target/s390x/kvm/kvm.c | 6 ++---- target/s390x/tcg/excp_helper.c | 11 +++-------- target/s390x/tcg/translate.c | 3 +-- 6 files changed, 10 insertions(+), 22 deletions(-) diff --git a/target/s390x/cpu-dump.c b/target/s390x/cpu-dump.c index ffa9e94d84..69cc9f7746 100644 --- a/target/s390x/cpu-dump.c +++ b/target/s390x/cpu-dump.c @@ -27,8 +27,7 @@ void s390_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; + CPUS390XState *env = cpu_env(cs); int i; qemu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64, diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index 6fbfd41bc8..f02fa316e5 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -30,8 +30,7 @@ int s390_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; + CPUS390XState *env = cpu_env(cs); switch (n) { case S390_PSWM_REGNUM: @@ -46,8 +45,7 @@ int s390_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; + CPUS390XState *env = cpu_env(cs); target_ulong tmpl = ldtul_p(mem_buf); switch (n) { diff --git a/target/s390x/helper.c b/target/s390x/helper.c index d76c06381b..00d5d403f3 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -139,8 +139,7 @@ void do_restart_interrupt(CPUS390XState *env) void s390_cpu_recompute_watchpoints(CPUState *cs) { const int wp_flags = BP_CPU | BP_MEM_WRITE | BP_STOP_BEFORE_ACCESS; - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; + CPUS390XState *env = cpu_env(cs); /* We are called when the watchpoints have changed. First remove them all. */ diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 888d6c1a1c..4ce809c5d4 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -474,8 +474,7 @@ static int can_sync_regs(CPUState *cs, int regs) int kvm_arch_put_registers(CPUState *cs, int level) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; + CPUS390XState *env = cpu_env(cs); struct kvm_fpu fpu = {}; int r; int i; @@ -601,8 +600,7 @@ int kvm_arch_put_registers(CPUState *cs, int level) int kvm_arch_get_registers(CPUState *cs) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; + CPUS390XState *env = cpu_env(cs); struct kvm_fpu fpu; int i, r; diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index b875bf14e5..f1c33f7967 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -90,10 +90,7 @@ void HELPER(data_exception)(CPUS390XState *env, uint32_t dxc) static G_NORETURN void do_unaligned_access(CPUState *cs, uintptr_t retaddr) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; - - tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr); + tcg_s390_program_interrupt(cpu_env(cs), PGM_SPECIFICATION, retaddr); } #if defined(CONFIG_USER_ONLY) @@ -146,8 +143,7 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; + CPUS390XState *env = cpu_env(cs); target_ulong vaddr, raddr; uint64_t asc, tec; int prot, excp; @@ -600,8 +596,7 @@ bool s390_cpu_exec_interrupt(CPUState *cs, int interrupt_request) void s390x_cpu_debug_excp_handler(CPUState *cs) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; + CPUS390XState *env = cpu_env(cs); CPUWatchpoint *wp_hit = cs->watchpoint_hit; if (wp_hit && wp_hit->flags & BP_CPU) { diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 8df00b7df9..9995689bc8 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6558,8 +6558,7 @@ void s390x_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; + CPUS390XState *env = cpu_env(cs); int cc_op = data[1]; env->psw.addr = data[0]; From patchwork Fri Jan 26 22:04:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 766403 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp455005wrb; Fri, 26 Jan 2024 14:12:51 -0800 (PST) X-Google-Smtp-Source: AGHT+IGVvJ//LXDHLeZrV7BJblmkbt02dKsch1aMffOR7rbGEptrlNECt5qQTprtNTFLfOcVf3f7 X-Received: by 2002:a05:6808:1929:b0:3bd:d7d4:2e2c with SMTP id bf41-20020a056808192900b003bdd7d42e2cmr543641oib.35.1706307171457; Fri, 26 Jan 2024 14:12:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706307171; cv=none; d=google.com; s=arc-20160816; b=A7KMPgxygmg83E87L8C+KqA+rF8rRRMUQ4DBOD3WwscHGBEFB/oxp2NuXHcfAkhEgn hdbwVIrN623pjVn7pak6G7eY2AN9d818bGgjr2YseZVHNCQv96tcaiUeW0YOqvJukCcs Cc807E7rUCAmV9zb4XMd0rbezNbVpREet2eiM2wVZn8ApI/bcW/IZHaSPIhEuS93Zz7J bsLKbQHd9rqzm71qeO3wpef0uwhYnWBuN/i6VQ7qGHYKoJeN5F0w+4hUslKhMvSnv1Pe STwOC8iG7bRWzAyhX7YY+v9F0Bfbb8jAY8A+oONjeoeWjW8jRgjvd/pOjaHE20bOfOml GYLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YtuQrPEiaOdoOF8LUQEAgkD/kFrAu5dyJpYlVEeXrYA=; fh=Tzw7ry3evXwnVWACvzmwEOdsg3J6VzcKR4bd6HttjTI=; b=vyDXUDx+kRx7krH15pXUEKxZlttnwK2c7KVR6l69uFCF4qmg/V/6GmF3VZv3dfj2HY BZEHhRieei2Gt40iFlcvPvlvK0oZo39nDtLDYq74eJ8qvZPnnoz6gIw6ipdF9vw6ePw+ J5VorI0isscrAem7RdmxEH+hK8mvBrjNc1DeCsiFAdjGb5INApgT0xjv5+iV4JNlkBlb pWNR9jplZBfZ9Lzyns1jbtOuJaAslXi9LY3HMZ6NUuPrsmg+kd+I0gsVZ+lw8Of7A026 BO3Ue4x1j2ogYQYuurdZ9WUBUrRzfcTNZS2FVibj2ts0msxY3N8Uaw2CVzPDaEAGXlX3 JPow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IiJX0UpK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/sh4/cpu.c | 15 +++++---------- target/sh4/gdbstub.c | 6 ++---- target/sh4/helper.c | 11 +++-------- target/sh4/translate.c | 3 +-- 4 files changed, 11 insertions(+), 24 deletions(-) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 806a0ef875..786c77615e 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -71,8 +71,7 @@ static void superh_restore_state_to_opc(CPUState *cs, static bool superh_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb) { - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(cs); if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND)) && !(cs->tcg_cflags & CF_PCREL) && env->pc != tb->pc) { @@ -144,8 +143,7 @@ out: static void sh7750r_cpu_initfn(Object *obj) { - SuperHCPU *cpu = SUPERH_CPU(obj); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(CPU(obj)); env->id = SH_CPU_SH7750R; env->features = SH_FEATURE_BCR3_AND_BCR4; @@ -162,8 +160,7 @@ static void sh7750r_class_init(ObjectClass *oc, void *data) static void sh7751r_cpu_initfn(Object *obj) { - SuperHCPU *cpu = SUPERH_CPU(obj); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(CPU(obj)); env->id = SH_CPU_SH7751R; env->features = SH_FEATURE_BCR3_AND_BCR4; @@ -180,8 +177,7 @@ static void sh7751r_class_init(ObjectClass *oc, void *data) static void sh7785_cpu_initfn(Object *obj) { - SuperHCPU *cpu = SUPERH_CPU(obj); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(CPU(obj)); env->id = SH_CPU_SH7785; env->features = SH_FEATURE_SH4A; @@ -216,8 +212,7 @@ static void superh_cpu_realizefn(DeviceState *dev, Error **errp) static void superh_cpu_initfn(Object *obj) { - SuperHCPU *cpu = SUPERH_CPU(obj); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(CPU(obj)); env->movcal_backup_tail = &(env->movcal_backup); } diff --git a/target/sh4/gdbstub.c b/target/sh4/gdbstub.c index d8e199fc06..75926d4e04 100644 --- a/target/sh4/gdbstub.c +++ b/target/sh4/gdbstub.c @@ -26,8 +26,7 @@ int superh_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(cs); switch (n) { case 0 ... 7: @@ -76,8 +75,7 @@ int superh_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int superh_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(cs); switch (n) { case 0 ... 7: diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 5a6f653c12..28b81a5c54 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -55,8 +55,7 @@ int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr) void superh_cpu_do_interrupt(CPUState *cs) { - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(cs); int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD; int do_exp, irq_vector = cs->exception_index; @@ -782,11 +781,8 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; - /* Delay slots are indivisible, ignore interrupts */ - if (env->flags & TB_FLAG_DELAY_SLOT_MASK) { + if (cpu_env(cs)->flags & TB_FLAG_DELAY_SLOT_MASK) { return false; } else { superh_cpu_do_interrupt(cs); @@ -800,8 +796,7 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(cs); int ret; target_ulong physical; diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 81f825f125..4a933adad8 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -159,8 +159,7 @@ void sh4_translate_init(void) void superh_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(cs); int i; qemu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n", From patchwork Fri Jan 26 22:04:03 2024 Content-Type: text/plain; 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Bastian Koppelmann --- target/tricore/cpu.c | 20 ++++---------------- target/tricore/gdbstub.c | 6 ++---- target/tricore/helper.c | 3 +-- target/tricore/translate.c | 3 +-- 4 files changed, 8 insertions(+), 24 deletions(-) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 8acacdf0c0..7f0609090c 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -36,38 +36,26 @@ static const gchar *tricore_gdb_arch_name(CPUState *cs) static void tricore_cpu_set_pc(CPUState *cs, vaddr value) { - TriCoreCPU *cpu = TRICORE_CPU(cs); - CPUTriCoreState *env = &cpu->env; - - env->PC = value & ~(target_ulong)1; + cpu_env(cs)->PC = value & ~(target_ulong)1; } static vaddr tricore_cpu_get_pc(CPUState *cs) { - TriCoreCPU *cpu = TRICORE_CPU(cs); - CPUTriCoreState *env = &cpu->env; - - return env->PC; + return cpu_env(cs)->PC; } static void tricore_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - TriCoreCPU *cpu = TRICORE_CPU(cs); - CPUTriCoreState *env = &cpu->env; - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); - env->PC = tb->pc; + cpu_env(cs)->PC = tb->pc; } static void tricore_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - TriCoreCPU *cpu = TRICORE_CPU(cs); - CPUTriCoreState *env = &cpu->env; - - env->PC = data[0]; + cpu_env(cs)->PC = data[0]; } static void tricore_cpu_reset_hold(Object *obj) diff --git a/target/tricore/gdbstub.c b/target/tricore/gdbstub.c index e8f8e5e6ea..f9309c5e27 100644 --- a/target/tricore/gdbstub.c +++ b/target/tricore/gdbstub.c @@ -106,8 +106,7 @@ static void tricore_cpu_gdb_write_csfr(CPUTriCoreState *env, int n, int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - TriCoreCPU *cpu = TRICORE_CPU(cs); - CPUTriCoreState *env = &cpu->env; + CPUTriCoreState *env = cpu_env(cs); if (n < 16) { /* data registers */ return gdb_get_reg32(mem_buf, env->gpr_d[n]); @@ -121,8 +120,7 @@ int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - TriCoreCPU *cpu = TRICORE_CPU(cs); - CPUTriCoreState *env = &cpu->env; + CPUTriCoreState *env = cpu_env(cs); uint32_t tmp; tmp = ldl_p(mem_buf); diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 174f666e1e..d328414c99 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -67,8 +67,7 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType rw, int mmu_idx, bool probe, uintptr_t retaddr) { - TriCoreCPU *cpu = TRICORE_CPU(cs); - CPUTriCoreState *env = &cpu->env; + CPUTriCoreState *env = cpu_env(cs); hwaddr physical; int prot; int ret = 0; diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 66553d1be0..ad314bdf3c 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -95,8 +95,7 @@ enum { void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - TriCoreCPU *cpu = TRICORE_CPU(cs); - CPUTriCoreState *env = &cpu->env; + CPUTriCoreState *env = cpu_env(cs); uint32_t psw; int i; From patchwork Fri Jan 26 22:04:04 2024 Content-Type: text/plain; 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/xtensa/dbg_helper.c | 3 +-- target/xtensa/exc_helper.c | 3 +-- target/xtensa/gdbstub.c | 6 ++---- target/xtensa/helper.c | 9 +++------ target/xtensa/translate.c | 3 +-- 5 files changed, 8 insertions(+), 16 deletions(-) diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index 497dafca71..5546c82ecd 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -66,8 +66,7 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) bool xtensa_debug_check_breakpoint(CPUState *cs) { - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; + CPUXtensaState *env = cpu_env(cs); unsigned int i; if (xtensa_get_cintlevel(env) >= env->config->debug_level) { diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index 168419a505..0514c2c1f3 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -205,8 +205,7 @@ static void handle_interrupt(CPUXtensaState *env) /* Called from cpu_handle_interrupt with BQL held */ void xtensa_cpu_do_interrupt(CPUState *cs) { - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; + CPUXtensaState *env = cpu_env(cs); if (cs->exception_index == EXC_IRQ) { qemu_log_mask(CPU_LOG_INT, diff --git a/target/xtensa/gdbstub.c b/target/xtensa/gdbstub.c index 4b3bfb7e59..4748fb6532 100644 --- a/target/xtensa/gdbstub.c +++ b/target/xtensa/gdbstub.c @@ -65,8 +65,7 @@ void xtensa_count_regs(const XtensaConfig *config, int xtensa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; + CPUXtensaState *env = cpu_env(cs); const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; #ifdef CONFIG_USER_ONLY int num_regs = env->config->gdb_regmap.num_core_regs; @@ -120,8 +119,7 @@ int xtensa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; + CPUXtensaState *env = cpu_env(cs); uint32_t tmp; const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; #ifdef CONFIG_USER_ONLY diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index a9f8907083..ca214b948a 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -217,8 +217,7 @@ static uint32_t check_hw_breakpoints(CPUXtensaState *env) void xtensa_breakpoint_handler(CPUState *cs) { - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; + CPUXtensaState *env = cpu_env(cs); if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { @@ -266,8 +265,7 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; + CPUXtensaState *env = cpu_env(cs); uint32_t paddr; uint32_t page_size; unsigned access; @@ -297,8 +295,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr) { - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; + CPUXtensaState *env = cpu_env(cs); cpu_restore_state(cs, retaddr); HELPER(exception_cause_vaddr)(env, env->pc, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 87947236ca..426dcb6169 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1248,8 +1248,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; + CPUXtensaState *env = cpu_env(cs); xtensa_isa isa = env->config->isa; int i, j; From patchwork Fri Jan 26 22:04:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 766401 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp454653wrb; Fri, 26 Jan 2024 14:11:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IGpoHmDqmE/lUteP/w1hVMIOurjq9Vn/hJqpLZCQVTfL3VjQBJ8SabRXd2TWit7JicXEzZK X-Received: by 2002:a05:620a:27c5:b0:783:3891:f231 with SMTP id i5-20020a05620a27c500b007833891f231mr544673qkp.14.1706307100291; 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Fri, 26 Jan 2024 14:06:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Thomas Huth , qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, Eduardo Habkost , kvm@vger.kernel.org, qemu-ppc@nongnu.org, Richard Henderson , Vladimir Sementsov-Ogievskiy , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH v2 23/23] target/sparc: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Fri, 26 Jan 2024 23:04:05 +0100 Message-ID: <20240126220407.95022-24-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240126220407.95022-1-philmd@linaro.org> References: <20240126220407.95022-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Mark Cave-Ayland --- target/sparc/cpu.c | 14 ++++---------- target/sparc/gdbstub.c | 3 +-- target/sparc/int32_helper.c | 3 +-- target/sparc/int64_helper.c | 3 +-- target/sparc/ldst_helper.c | 6 ++---- target/sparc/mmu_helper.c | 15 +++++---------- target/sparc/translate.c | 3 +-- 7 files changed, 15 insertions(+), 32 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index befa7fc4eb..a53c200d8b 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -83,8 +83,7 @@ static void sparc_cpu_reset_hold(Object *obj) static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) { int pil = env->interrupt_index & 0xf; @@ -613,8 +612,7 @@ static void cpu_print_cc(FILE *f, uint32_t cc) static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); int i, x; qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, @@ -711,11 +709,8 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, static bool sparc_cpu_has_work(CPUState *cs) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - return (cs->interrupt_request & CPU_INTERRUPT_HARD) && - cpu_interrupts_enabled(env); + cpu_interrupts_enabled(cpu_env(cs)); } static char *sparc_cpu_type_name(const char *cpu_model) @@ -749,8 +744,7 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) CPUState *cs = CPU(dev); SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev); Error *local_err = NULL; - SPARCCPU *cpu = SPARC_CPU(dev); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); #if defined(CONFIG_USER_ONLY) /* We are emulating the kernel, which will trap and emulate float128. */ diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index a1c8fdc4d5..5257c49a0d 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -29,8 +29,7 @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); if (n < 8) { /* g0..g7 */ diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c index 058dd712b5..6b7d65b031 100644 --- a/target/sparc/int32_helper.c +++ b/target/sparc/int32_helper.c @@ -99,8 +99,7 @@ void cpu_check_irqs(CPUSPARCState *env) void sparc_cpu_do_interrupt(CPUState *cs) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); int cwp, intno = cs->exception_index; if (qemu_loglevel_mask(CPU_LOG_INT)) { diff --git a/target/sparc/int64_helper.c b/target/sparc/int64_helper.c index 27df9dba89..bd14c7a0db 100644 --- a/target/sparc/int64_helper.c +++ b/target/sparc/int64_helper.c @@ -130,8 +130,7 @@ void cpu_check_irqs(CPUSPARCState *env) void sparc_cpu_do_interrupt(CPUState *cs) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); int intno = cs->exception_index; trap_state *tsptr; diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 09066d5487..203441bfb2 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -421,8 +421,7 @@ static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, bool is_write, bool is_exec, int is_asi, unsigned size, uintptr_t retaddr) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); int fault_type; #ifdef DEBUG_UNASSIGNED @@ -483,8 +482,7 @@ static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, bool is_write, bool is_exec, int is_asi, unsigned size, uintptr_t retaddr) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); #ifdef DEBUG_UNASSIGNED printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 453498c670..a05ee22315 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -206,8 +206,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); CPUTLBEntryFull full = {}; target_ulong vaddr; int error_code = 0, access_index; @@ -391,8 +390,7 @@ void dump_mmu(CPUSPARCState *env) int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf, int len, bool is_write) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); target_ulong addr = address; int i; int len1; @@ -759,8 +757,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); CPUTLBEntryFull full = {}; int error_code = 0, access_index; @@ -898,8 +895,7 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); hwaddr phys_addr; int mmu_idx = cpu_mmu_index(env, false); @@ -916,8 +912,7 @@ G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, int mmu_idx, uintptr_t retaddr) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); #ifdef TARGET_SPARC64 env->dmmu.sfsr = build_sfsr(env, mmu_idx, access_type); diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 9387299559..412b7d1b66 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5406,8 +5406,7 @@ void sparc_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); target_ulong pc = data[0]; target_ulong npc = data[1];