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And the MUs in AONMIX has internal RAMs for SCMI shared buffer usage. Signed-off-by: Peng Fan --- .../devicetree/bindings/mailbox/fsl,mu.yaml | 58 +++++++++++++++++++++- 1 file changed, 57 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml index 12e7a7d536a3..33140f72da6d 100644 --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml @@ -29,8 +29,11 @@ properties: - const: fsl,imx8ulp-mu - const: fsl,imx8-mu-scu - const: fsl,imx8-mu-seco - - const: fsl,imx93-mu-s4 - const: fsl,imx8ulp-mu-s4 + - const: fsl,imx93-mu-s4 + - const: fsl,imx95-mu + - const: fsl,imx95-mu-ele + - const: fsl,imx95-mu-v2x - items: - const: fsl,imx93-mu - const: fsl,imx8ulp-mu @@ -95,6 +98,19 @@ properties: power-domains: maxItems: 1 + ranges: true + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +patternProperties: + "^sram@[a-f0-9]+": + $ref: /schemas/sram/sram.yaml# + unevaluatedProperties: false + required: - compatible - reg @@ -122,6 +138,15 @@ allOf: required: - interrupt-names + - if: + not: + properties: + compatible: + const: fsl,imx95-mu + then: + patternProperties: + "^sram@[a-f0-9]+": false + additionalProperties: false examples: @@ -134,3 +159,34 @@ examples: interrupts = ; #mbox-cells = <2>; }; + + - | + #include + + mu2: mailbox@445b0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445b0000 0x10000>; + ranges; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + #mbox-cells = <2>; + + sram@445b1000 { + compatible = "mmio-sram"; + reg = <0x445b1000 0x400>; + ranges = <0x0 0x445b1000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + scmi_buf0: scmi-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + scmi_buf1: scmi-sram-section@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + }; + }; From patchwork Fri Jan 26 06:29:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 766656 Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03on2088.outbound.protection.outlook.com [40.107.105.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC60E1B942; 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The patch only adds support the specific MU, such as ELE MU. For generic MU, not add support for number larger than 4. Reviewed-by: Sascha Hauer Signed-off-by: Peng Fan --- drivers/mailbox/imx-mailbox.c | 46 ++++++++++++++++++++++++++++++++----------- 1 file changed, 35 insertions(+), 11 deletions(-) diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c index dced4614065f..9e89f773d2f9 100644 --- a/drivers/mailbox/imx-mailbox.c +++ b/drivers/mailbox/imx-mailbox.c @@ -29,7 +29,9 @@ #define IMX_MU_S4_CHANS 2 #define IMX_MU_CHAN_NAME_SIZE 20 -#define IMX_MU_NUM_RR 4 +#define IMX_MU_V2_PAR_OFF 0x4 +#define IMX_MU_V2_TR_MASK GENMASK(7, 0) +#define IMX_MU_V2_RR_MASK GENMASK(15, 8) #define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000)) #define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000)) @@ -93,10 +95,11 @@ struct imx_mu_priv { struct clk *clk; int irq[IMX_MU_CHANS]; bool suspend; - - u32 xcr[IMX_MU_xCR_MAX]; - bool side_b; + + u32 xcr[IMX_MU_xCR_MAX]; + u32 num_tr; + u32 num_rr; }; enum imx_mu_type { @@ -264,18 +267,17 @@ static int imx_mu_generic_rxdb(struct imx_mu_priv *priv, static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data) { u32 *arg = data; + u32 num_tr = priv->num_tr; int i, ret; u32 xsr; - u32 size, max_size, num_tr; + u32 size, max_size; if (priv->dcfg->type & IMX_MU_V2_S4) { size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size; max_size = sizeof(struct imx_s4_rpc_msg_max); - num_tr = 8; } else { size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size; max_size = sizeof(struct imx_sc_rpc_msg_max); - num_tr = 4; } switch (cp->type) { @@ -324,6 +326,7 @@ static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv * int i, ret; u32 xsr; u32 size, max_size; + u32 num_rr = priv->num_rr; data = (u32 *)priv->msg; @@ -345,13 +348,13 @@ static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv * for (i = 1; i < size; i++) { ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr, - xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0, + xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % num_rr), 0, 5 * USEC_PER_SEC); if (ret) { dev_err(priv->dev, "timeout read idx %d\n", i); return ret; } - *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4); + *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % num_rr) * 4); } imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0); @@ -737,11 +740,30 @@ static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox, return imx_mu_xlate(mbox, sp); } +static void imx_mu_get_tr_rr(struct imx_mu_priv *priv) +{ + u32 val; + + if (priv->dcfg->type & IMX_MU_V2) { + val = imx_mu_read(priv, IMX_MU_V2_PAR_OFF); + priv->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val); + priv->num_rr = FIELD_GET(IMX_MU_V2_RR_MASK, val); + } else { + priv->num_tr = 4; + priv->num_rr = 4; + } +} + static int imx_mu_init_generic(struct imx_mu_priv *priv) { unsigned int i; unsigned int val; + if (priv->num_rr > 4 || priv->num_tr > 4) { + WARN_ONCE(true, "%s not support TR/RR larger than 4\n", __func__); + return -EOPNOTSUPP; + } + for (i = 0; i < IMX_MU_CHANS; i++) { struct imx_mu_con_priv *cp = &priv->con_priv[i]; @@ -768,8 +790,8 @@ static int imx_mu_init_generic(struct imx_mu_priv *priv) imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]); /* Clear any pending RSR */ - for (i = 0; i < IMX_MU_NUM_RR; i++) - imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4); + for (i = 0; i < priv->num_rr; i++) + imx_mu_read(priv, priv->dcfg->xRR + i * 4); return 0; } @@ -874,6 +896,8 @@ static int imx_mu_probe(struct platform_device *pdev) return ret; } + imx_mu_get_tr_rr(priv); + priv->side_b = of_property_read_bool(np, "fsl,mu-side-b"); ret = priv->dcfg->init(priv);