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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.30.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:30:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 01/33] include/hw/core: Add mmu_index to CPUClass Date: Tue, 30 Jan 2024 09:30:11 +1000 Message-Id: <20240129233043.34558-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org To be used after all targets have populated the hook. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 2c284d6397..4385ce54c9 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -103,6 +103,8 @@ struct SysemuCPUOps; * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. + * @mmu_index: Callback for choosing softmmu mmu index; + * may be used internally by memory_rw_debug without TCG. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @query_cpu_fast: @@ -150,6 +152,7 @@ struct CPUClass { void (*parse_features)(const char *typename, char *str, Error **errp); bool (*has_work)(CPUState *cpu); + int (*mmu_index)(CPUState *cpu, bool ifetch); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); From patchwork Mon Jan 29 23:30:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767459 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1125620wro; Mon, 29 Jan 2024 15:31:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IGZRNOf/WnfFjKF8amcU3ycXwvSrlaJ77ylqfxeMadBK3pEmQBvQZ8hsm79U42DXR/iCgcY X-Received: by 2002:ac8:7f82:0:b0:42a:32d0:49cc with SMTP id z2-20020ac87f82000000b0042a32d049ccmr10108363qtj.63.1706571115189; Mon, 29 Jan 2024 15:31:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571115; cv=none; d=google.com; s=arc-20160816; b=Cpy7MZwuP2M+5iOecTQecNFnYg28ZHfCCBK4sZdaefshn01QefZtnfp+D18rBitxAp MiVGMMgiFWEeFWC+z2pHLpjnvzv3pIYLSgA53vVYjhV7a/MqDDYLh5DyWXNo/OxLeuBb izlZ97uMQn+dAFJTZpU6p22OdDPcYTuWOkHJSXdQL73KVHHOiQ7kvLHyUuiZbRg+amiF eCUW99/RWQmFWFxBwO4N74olQoNkroY/BMUUi6LwbcR1++JU5UV5DILiySb5CR7fRtP2 +mkVfQM7BbTdQ6h7oKrEcto9UxppNmeCx2kAPNYepxUqe7zCb9bS1NLSBvGNKzl0jZYy mFTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GuLjJD6Uv7AUoT7v/CmrWdMUNxFVKqK7N1yrIDiYHSI=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=K3u4Bj5V3sghzhFRTtfhsCeFt5KJvS40pNJd4IH2AI48rL4bKxRkSoU4MBToy7kiRE LIGf0DBjxODex7oD9AjB0GiQGbHNdZ7sZ+eRb5yu+CMm0afDCCBCLquwLWZouIPV71Lv /O2t4Rbr7bH7wObINSMf5vuFqxOTnmEfgqnVmhX93fB6rxrcT6epI/vffbhSHxpy3kuk LIHBB2n6mZZFOA8A+gOS0zFbC5+oHALcu5kNDloE4iUTUL2fOfjf4AcCG4KlOJvrqSUt nZBlC7O41ymXTISS0h5lAJDPdyEtql/EC2l9MxDbC2kG2vqTiRfUwcQakBhcXEl1eX6p Ol9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Mjp+Errd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.30.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:30:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 02/33] target/alpha: Split out alpha_env_mmu_index Date: Tue, 30 Jan 2024 09:30:12 +1000 Message-Id: <20240129233043.34558-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 7 ++++++- target/alpha/translate.c | 2 +- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index ce806587ca..3beff2738a 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -389,7 +389,7 @@ enum { #define TB_FLAG_UNALIGN (1u << 1) -static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) +static inline int alpha_env_mmu_index(CPUAlphaState *env) { int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX; if (env->flags & ENV_FLAG_PAL_MODE) { @@ -398,6 +398,11 @@ static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) return ret; } +static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) +{ + return alpha_env_mmu_index(env); +} + enum { IR_V0 = 0, IR_T0 = 1, diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 134eb7225b..4b464f8651 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2875,7 +2875,7 @@ static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) int64_t bound; ctx->tbflags = ctx->base.tb->flags; - ctx->mem_idx = cpu_mmu_index(env, false); + ctx->mem_idx = alpha_env_mmu_index(env); ctx->implver = env->implver; ctx->amask = env->amask; From patchwork Mon Jan 29 23:30:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767469 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1126389wro; Mon, 29 Jan 2024 15:34:28 -0800 (PST) X-Google-Smtp-Source: AGHT+IGZBsKjsLTdwqpUEsTTbHe57Yud9TmrqzlqQOu0flz2HHVuqUwPQvzbM9v2pGjfiyI1B4ls X-Received: by 2002:a05:622a:109:b0:42a:b456:8696 with SMTP id u9-20020a05622a010900b0042ab4568696mr518929qtw.13.1706571268432; Mon, 29 Jan 2024 15:34:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571268; cv=none; d=google.com; s=arc-20160816; b=idcHNFcrdNNq58MBGY3rWYVBybbag267Ng4YJhftsReaQbBo2pasdGesXGfca3lMtQ TxWfBlHWSyLzcZvliipAdSttCBIfTIKK9PluPC7n4NhISbM90hhqAsuEAWgVMPqdHOdT TntbmCHmgOpJWSd16tWcPXRVMHxisgmBtlylsDxg8exfUJjRqcDVx3l+neKKH9wLcIS/ Ei/ANFvMoCQhrOYXl0HyQennocPgo12ErCnZHQqpvPY5mZhZMn4PrgKheJ5UirUvSXj3 HYnWiqJQlBxWZamwIxGxEiDDF37tilDJh7BB6S0yFQjGvwqq/WzAQHKxJpxE72WBaGTC aDRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rY4TKU6Y4tdsleFZysMCIHaTnyMqTWQ/l8+rNabU+ew=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=uCTsxD6ulNb0ozhsr/uA/fBmZ1hPzHLJxFg4Xds4FL5x0rfU5x4AyQKx+NggidVhSX jxMbEWOgp64zqGwVuZvS/mzkL9xl1gYN8XbCEhyq/HwuEU2pKyHHMDI90T+yHdEa1tKb 0dqAis5DvgBnB5g0LnzxRuNnMiDvPJYg3phyCwDIgBpc9rcjilLpNGjHWkXvlXLWhGUj dq1MXF8/MH1DuUesbYi24+zBSD2XAUeBODiTBJkFKvceizYnYuJaKROW1lBRKXRSOPHr 56j1aWF0oz20bqmhe/4ZJ30vkdchvfQLo/CaoZJtsnUaS+W4nqZ5479Wks69FwOJ5wN3 qB8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IwLV4zBz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.30.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:30:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 03/33] target/alpha: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:13 +1000 Message-Id: <20240129233043.34558-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/alpha/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index de705c3703..bf70173a25 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -64,6 +64,11 @@ static bool alpha_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_MCHK); } +static int alpha_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return alpha_env_mmu_index(cpu_env(cs)); +} + static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) { info->mach = bfd_mach_alpha_ev6; @@ -230,6 +235,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = alpha_cpu_class_by_name; cc->has_work = alpha_cpu_has_work; + cc->mmu_index = alpha_cpu_mmu_index; cc->dump_state = alpha_cpu_dump_state; cc->set_pc = alpha_cpu_set_pc; cc->get_pc = alpha_cpu_get_pc; From patchwork Mon Jan 29 23:30:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767463 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1125743wro; Mon, 29 Jan 2024 15:32:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IHFSEM8BGdjfuJ+dSzvbUCw/mFetaVNPnQNFHmHTTuplvpJxi2ItvTdq6wphK/PNyMZhfph X-Received: by 2002:ad4:5def:0:b0:68c:53e6:101c with SMTP id jn15-20020ad45def000000b0068c53e6101cmr2118272qvb.33.1706571140109; Mon, 29 Jan 2024 15:32:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571140; cv=none; d=google.com; s=arc-20160816; b=vo+5c0CGvz9BAumoPJO2Ro+AlrBcCkHWLur136LJ6VARBXm7ALnuR3B2rAnf/3wwFe LMQiaSYN5QWSG7pwjhfGmQcjMNn9ly+mqrplCx5BlMq/J+qFFgYd94amAyC1gcJXUpnV zDU1C0WJuCLHw3uH5z22Wh8mhfxLLZXQFYHIrhqOHxj41BUV/gDAXNrTFW65P7jMWJtT XyUeY6C82VSlVQ/ju6bYpr9OhplVqgfe5gnEGtt3bovvyuVe/Ix1phLqFPhfHx5ZWFgy bzVpAOQOUebH27vq18MUMxVHkFzDtn7fPkq8QgSqWCGgm02icFUMgrQyhQuuxwbJpBtf bnYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=lgGnmjgbm65ABwN9XCrwoifbds3p9aO0+EYuonhmffg=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=lgjuP5eynYU8wxBEBnR2gvWmIyGVZvzqiSlrMM+m8gkcmy2qY0C14LFDllQ//62O5O nWsH+p+xi9JHd/MjkYm9ZI3W+j5WJ8BecAHIuwN2HrGxVUz8RLR87MIvA8YRTF5A+FTd 5xtM8kDymJOWbQjkGterrATroRBOkWBliCP2jLtcCw4+30+OfSd3Il7WmcWtNAw1FZsF GWkRXevXpiv88aWkhshJezGX8HwYmTWhHPusmOBwZRe9t60uAlQy/gIswWPCnOLD4bpO 58KdH8jQmaHVx4Ope34CYieZCADmKRHIYY765JnFib6WhasgTQEGy73ZuLbZJeE+T1F7 GpNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uku3NPlS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.30.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:30:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 04/33] target/arm: Split out arm_env_mmu_index Date: Tue, 30 Jan 2024 09:30:14 +1000 Message-Id: <20240129233043.34558-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/arm/internals.h | 5 +++++ target/arm/helper.c | 2 +- target/arm/tcg/helper-a64.c | 4 ++-- target/arm/tcg/mte_helper.c | 18 +++++++++--------- target/arm/tcg/sve_helper.c | 8 ++++---- target/arm/tcg/tlb_helper.c | 2 +- 6 files changed, 22 insertions(+), 17 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 71d6c70bf3..fc337fe40e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -40,6 +40,11 @@ #define BANK_HYP 6 #define BANK_MON 7 +static inline int arm_env_mmu_index(CPUARMState *env) +{ + return EX_TBFLAG_ANY(env->hflags, MMUIDX); +} + static inline bool excp_is_internal(int excp) { /* Return true if this exception number represents a QEMU-internal diff --git a/target/arm/helper.c b/target/arm/helper.c index 945d8571a6..b0488caf40 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7841,7 +7841,7 @@ static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, uint64_t vaddr_in = (uint64_t) value; uint64_t vaddr = vaddr_in & ~(dline_size - 1); void *haddr; - int mem_idx = cpu_mmu_index(env, false); + int mem_idx = arm_env_mmu_index(env); /* This won't be crossing page boundaries */ haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC()); diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 198b975f20..ebaa7f00df 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -856,7 +856,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) tbii = EX_TBFLAG_A64(env->hflags, TBII); if ((tbii >> extract64(new_pc, 55, 1)) & 1) { /* TBI is enabled. */ - int core_mmu_idx = cpu_mmu_index(env, false); + int core_mmu_idx = arm_env_mmu_index(env); if (regime_has_2_ranges(core_to_aa64_mmu_idx(core_mmu_idx))) { new_pc = sextract64(new_pc, 0, 56); } else { @@ -925,7 +925,7 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) */ int blocklen = 4 << env_archcpu(env)->dcz_blocksize; uint64_t vaddr = vaddr_in & ~(blocklen - 1); - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = arm_env_mmu_index(env); void *mem; /* diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index ffb8ea1c34..d971b81370 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -291,7 +291,7 @@ static int load_tag1(uint64_t ptr, uint8_t *mem) uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt) { - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = arm_env_mmu_index(env); uint8_t *mem; int rtag = 0; @@ -311,7 +311,7 @@ static void check_tag_aligned(CPUARMState *env, uint64_t ptr, uintptr_t ra) { if (unlikely(!QEMU_IS_ALIGNED(ptr, TAG_GRANULE))) { arm_cpu_do_unaligned_access(env_cpu(env), ptr, MMU_DATA_STORE, - cpu_mmu_index(env, false), ra); + arm_env_mmu_index(env), ra); g_assert_not_reached(); } } @@ -344,7 +344,7 @@ typedef void stg_store1(uint64_t, uint8_t *, int); static inline void do_stg(CPUARMState *env, uint64_t ptr, uint64_t xt, uintptr_t ra, stg_store1 store1) { - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = arm_env_mmu_index(env); uint8_t *mem; check_tag_aligned(env, ptr, ra); @@ -371,7 +371,7 @@ void HELPER(stg_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt) void HELPER(stg_stub)(CPUARMState *env, uint64_t ptr) { - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = arm_env_mmu_index(env); uintptr_t ra = GETPC(); check_tag_aligned(env, ptr, ra); @@ -381,7 +381,7 @@ void HELPER(stg_stub)(CPUARMState *env, uint64_t ptr) static inline void do_st2g(CPUARMState *env, uint64_t ptr, uint64_t xt, uintptr_t ra, stg_store1 store1) { - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = arm_env_mmu_index(env); int tag = allocation_tag_from_addr(xt); uint8_t *mem1, *mem2; @@ -429,7 +429,7 @@ void HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt) void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr) { - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = arm_env_mmu_index(env); uintptr_t ra = GETPC(); int in_page = -(ptr | TARGET_PAGE_MASK); @@ -445,7 +445,7 @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr) uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) { - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = arm_env_mmu_index(env); uintptr_t ra = GETPC(); int gm_bs = env_archcpu(env)->gm_blocksize; int gm_bs_bytes = 4 << gm_bs; @@ -505,7 +505,7 @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) { - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = arm_env_mmu_index(env); uintptr_t ra = GETPC(); int gm_bs = env_archcpu(env)->gm_blocksize; int gm_bs_bytes = 4 << gm_bs; @@ -555,7 +555,7 @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val) { uintptr_t ra = GETPC(); - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = arm_env_mmu_index(env); int log2_dcz_bytes, log2_tag_bytes; intptr_t dcz_bytes, tag_bytes; uint8_t *mem; diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index f006d152cc..bce4295d28 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -5481,7 +5481,7 @@ bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, CPUARMState *env, target_ulong addr, MMUAccessType access_type, uintptr_t retaddr) { - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = arm_env_mmu_index(env); int mem_off = info->mem_off_first[0]; bool nofault = fault == FAULT_NO; bool have_work = true; @@ -6529,7 +6529,7 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, sve_ldst1_host_fn *host_fn, sve_ldst1_tlb_fn *tlb_fn) { - const int mmu_idx = cpu_mmu_index(env, false); + const int mmu_idx = arm_env_mmu_index(env); const intptr_t reg_max = simd_oprsz(desc); const int scale = simd_data(desc); ARMVectorReg scratch; @@ -6715,7 +6715,7 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, sve_ldst1_host_fn *host_fn, sve_ldst1_tlb_fn *tlb_fn) { - const int mmu_idx = cpu_mmu_index(env, false); + const int mmu_idx = arm_env_mmu_index(env); const intptr_t reg_max = simd_oprsz(desc); const int scale = simd_data(desc); const int esize = 1 << esz; @@ -6920,7 +6920,7 @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg, void *vm, sve_ldst1_host_fn *host_fn, sve_ldst1_tlb_fn *tlb_fn) { - const int mmu_idx = cpu_mmu_index(env, false); + const int mmu_idx = arm_env_mmu_index(env); const intptr_t reg_max = simd_oprsz(desc); const int scale = simd_data(desc); void *host[ARM_MAX_VQ * 4]; diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 5477c7fb7d..885bf4ec14 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -281,7 +281,7 @@ void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) { ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; int target_el = exception_target_el(env); - int mmu_idx = cpu_mmu_index(env, true); + int mmu_idx = arm_env_mmu_index(env); uint32_t fsc; env->exception.vaddress = pc; From patchwork Mon Jan 29 23:30:15 2024 Content-Type: text/plain; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.30.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:30:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 05/33] target/arm: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:15 +1000 Message-Id: <20240129233043.34558-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/arm/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6a96b245f2..1f9ea622bd 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -133,6 +133,11 @@ static bool arm_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_EXITTB); } +static int arm_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return arm_env_mmu_index(cpu_env(cs)); +} + void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque) { @@ -2497,6 +2502,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = arm_cpu_class_by_name; cc->has_work = arm_cpu_has_work; + cc->mmu_index = arm_cpu_mmu_index; cc->dump_state = arm_cpu_dump_state; cc->set_pc = arm_cpu_set_pc; cc->get_pc = arm_cpu_get_pc; From patchwork Mon Jan 29 23:30:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767480 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1127344wro; Mon, 29 Jan 2024 15:37:37 -0800 (PST) X-Google-Smtp-Source: AGHT+IEC8up870Giwy4DY0VCUjzReMBWxzEkXNcWlJewjd5uj7gSuDaXkJ6RyRKo71Sso5dovUXN X-Received: by 2002:a0c:f2cf:0:b0:68c:46ee:de71 with SMTP id c15-20020a0cf2cf000000b0068c46eede71mr107707qvm.1.1706571457613; Mon, 29 Jan 2024 15:37:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571457; cv=none; d=google.com; s=arc-20160816; b=T2vmWJhxAC9kizWcfWXsCephQFZBIJhDzhhe3mOeIEADrW6O/TDs/EebebpFzgSOHN YIIIGJCK2ZPEGdJ/FlJHNU57OxWrRj84gUzo0x1c6Xw+8sKAaW9dp9WDHlbYchjqRhN0 p3l0bRAgLOudrORhdE76KzzGffOko7zR2mZ0TKuGVldEYweWaIKZMYGvkWnzwRPL+JYz 3sdOM+/Y8wqxNYqyXTRwPY1Zq6oMs4b66G4kHFmjpDtoDJPShdvl8B3Wt07GdNY3ElIu J5yY/+nOswgZuaPSgX37OAWUk0CjfXezcHkPZ3OuavPoUxkOwQu31heBCKX4W8z7fEMM DoxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=P5Fsq2RX8/y2x9aiQTk6UToPX5ZjmTnnnnUS2+II2G4=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=XgLkIodcMDFa/nwnEf4YXAiSJPcTJ6EnA5TICz/0QLw8dI08Zziw8LinN3dupBWmaa +859ATs+dlwhyoe1hNaFh4+7uURNp6BLcA9HetkLsojNShkNDC/LkSx0B4UrOLCjFKnp qxdCYOec5iy5loGAcoRjh4vYwmrG4nfN9Y4yUkjnzenNPuMiw+avddUtJLIvVWENQBVB MOog/x+N2zN5c+UD9T2tfNnlFe++S8axh6AGlt5uFMb/HgaEN1kmS9BsCGf9KLv/U47y +O5B5eVb75bGWIxZE52qLT2ekh3Wigdky76n6jUQzw7f0qXRJAo7Nh3E/PaXLaDiZ5ln MH7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="SeNa/NMf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.30.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 06/33] target/avr: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:16 +1000 Message-Id: <20240129233043.34558-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/avr/cpu.h | 4 +--- target/avr/cpu.c | 6 ++++++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 7d5dd42575..4595c6bb18 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -184,9 +184,7 @@ static inline void set_avr_feature(CPUAVRState *env, int feature) env->features |= (1U << feature); } -#define cpu_mmu_index avr_cpu_mmu_index - -static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch) +static inline int cpu_mmu_index(CPUAVRState *env, bool ifetch) { return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 1c68748b24..a40f445af2 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -50,6 +50,11 @@ static bool avr_cpu_has_work(CPUState *cs) && cpu_interrupts_enabled(env); } +static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; +} + static void avr_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -236,6 +241,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = avr_cpu_class_by_name; cc->has_work = avr_cpu_has_work; + cc->mmu_index = avr_cpu_mmu_index; cc->dump_state = avr_cpu_dump_state; cc->set_pc = avr_cpu_set_pc; cc->get_pc = avr_cpu_get_pc; From patchwork Mon Jan 29 23:30:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767460 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1125623wro; Mon, 29 Jan 2024 15:31:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IFyAwxUgJO8LlpXHLtsUmfsJQnEJ2T8EFtrlnfailNYqXolsD+ho+y5RyjU2KYZQ7oHB9kj X-Received: by 2002:a05:6830:1607:b0:6dd:e3c3:65bf with SMTP id g7-20020a056830160700b006dde3c365bfmr7901486otr.63.1706571115490; Mon, 29 Jan 2024 15:31:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571115; cv=none; d=google.com; s=arc-20160816; b=H+WY9TuVQRmgicgFAxwbbMmRkHn1OdCsBiWWnbsqkoDDpT+D4kAYyCCEJeXiAWnyn/ 2VJ4sgeT0evg4NaWmVyJ/wNEA7e4a8DLFaiPqMld+uS/SMu+8UjIQVSncEYA6JX/gqmB K4J5RnEA+Du52Q+75KjE9ZoOpaOau+o/9nlo3mcv8EY5n0GsZYEa0YARCvSO8w+0f1xi tQC84R1fzsIClQy7g/1aClmO+h9NboMWpRJVzgEexB4VJ279qw98J+cbjjRnQF1SNVKp 2fkDDjRS0Zufx+JeHPm2AnyEZxjaTcPSPjRMDL8kF8FTUAJxhL+VBSBRQhXPXYYD17J9 pElw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3/S1vigBU1gXfX4oI3MWHNHDSQjD4iR9o36lTMrKyJs=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=UjMdn8njH7+RAXtS/zkLybkLetHZFxjqyck9q4QccXwzwQyAPkcNyZNSOQ38XhKAV1 ZIY9R8quzCMNjdUKeW4Kr84LF4E09Ij3Xeq1vACbO84l+rhltUmhvgX3Wb19nS29eTuv +9uKU6/8CawCTx1N8Epr3epjaIsDXFtP3Yy41zMjI4ddYfnJvzGQzj8VGem52QFck2Rh Y3v9ke2rBsHQDwpiIebWE2SoFZHjgMPXBD7gbIyewZxxamsL29qrW2iX6Epo+S6YIzI1 8xkrvuUQ0vj2KDE/AaTbSl1AtNFIH+ttqR5Yaps+kvMsBpcxj/9DUArzx+f5miQ9PzYl WI6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qi3Z7YOz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 07/33] target/cris: Cache mem_index in DisasContext Date: Tue, 30 Jan 2024 09:30:17 +1000 Message-Id: <20240129233043.34558-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Compute this value once for each translation. Signed-off-by: Richard Henderson --- target/cris/translate.c | 14 +++++--------- target/cris/translate_v10.c.inc | 6 ++---- 2 files changed, 7 insertions(+), 13 deletions(-) diff --git a/target/cris/translate.c b/target/cris/translate.c index ee1402a9a3..7acea29a01 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -94,6 +94,7 @@ typedef struct DisasContext { CRISCPU *cpu; target_ulong pc, ppc; + int mem_index; /* Decoder. */ unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc); @@ -1008,37 +1009,31 @@ static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type) static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr) { - int mem_index = cpu_mmu_index(&dc->cpu->env, false); - /* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */ if (dc->delayed_branch == 1) { cris_store_direct_jmp(dc); } - tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEUQ); + tcg_gen_qemu_ld_i64(dst, addr, dc->mem_index, MO_TEUQ); } static void gen_load(DisasContext *dc, TCGv dst, TCGv addr, unsigned int size, int sign) { - int mem_index = cpu_mmu_index(&dc->cpu->env, false); - /* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */ if (dc->delayed_branch == 1) { cris_store_direct_jmp(dc); } - tcg_gen_qemu_ld_tl(dst, addr, mem_index, + tcg_gen_qemu_ld_tl(dst, addr, dc->mem_index, MO_TE + ctz32(size) + (sign ? MO_SIGN : 0)); } static void gen_store (DisasContext *dc, TCGv addr, TCGv val, unsigned int size) { - int mem_index = cpu_mmu_index(&dc->cpu->env, false); - /* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */ if (dc->delayed_branch == 1) { @@ -1055,7 +1050,7 @@ static void gen_store (DisasContext *dc, TCGv addr, TCGv val, return; } - tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size)); + tcg_gen_qemu_st_tl(val, addr, dc->mem_index, MO_TE + ctz32(size)); if (dc->flags_x) { cris_evaluate_flags(dc); @@ -2971,6 +2966,7 @@ static void cris_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->cpu = env_archcpu(env); dc->ppc = pc_start; dc->pc = pc_start; + dc->mem_index = cpu_mmu_index(env, false); dc->flags_uptodate = 1; dc->flags_x = tb_flags & X_FLAG; dc->cc_x_uptodate = 0; diff --git a/target/cris/translate_v10.c.inc b/target/cris/translate_v10.c.inc index 6df599fdce..73fc27c15d 100644 --- a/target/cris/translate_v10.c.inc +++ b/target/cris/translate_v10.c.inc @@ -91,8 +91,6 @@ static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val, static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val, unsigned int size) { - int mem_index = cpu_mmu_index(&dc->cpu->env, false); - /* If we get a fault on a delayslot we must keep the jmp state in the cpu-state to be able to re-execute the jmp. */ if (dc->delayed_branch == 1) { @@ -101,11 +99,11 @@ static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val, /* Conditional writes. */ if (dc->flags_x) { - gen_store_v10_conditional(dc, addr, val, size, mem_index); + gen_store_v10_conditional(dc, addr, val, size, dc->mem_index); return; } - tcg_gen_qemu_st_tl(val, addr, mem_index, ctz32(size) | MO_TE); + tcg_gen_qemu_st_tl(val, addr, dc->mem_index, ctz32(size) | MO_TE); } From patchwork Mon Jan 29 23:30:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767466 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1126080wro; Mon, 29 Jan 2024 15:33:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IFZvO+cSirvR1idwOHD6Um50njEIDyhE8fPxZ4Yk0j4DKiiglTHaVqOuVxWFPijNV/WAlTI X-Received: by 2002:a05:622a:343:b0:42a:b1ed:65c4 with SMTP id r3-20020a05622a034300b0042ab1ed65c4mr1008087qtw.13.1706571204792; Mon, 29 Jan 2024 15:33:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571204; cv=none; d=google.com; s=arc-20160816; b=tIuK40uyl+AQwoxkDHLX/EDh6Ks3KwY/FYeqVwDWjQPnCP4kfrKeJ231hmf4hTAPN7 zmHn/30/Bboq11YhVPoDoyTC5klncYRCxjIrKkp+ORaB/9PTrnlhgbFfqLk7/Fhwc3wm RIDDPQ6Vh7JuCWQHzavjYcww1EEGlT0KNr5N9jdf6m50rZk29B8hvVdzyqdGl3B+RrZS Jggajp1yRVw+xwMV0bHbbnsW0mEgzQ7B1+lyj9TztaHBsAPm3GdvMt+plZSz7UU4m4iS dM30d0Hvav3YnTB0XA8+Se4FIvBpSEAAzJTvSBjXzIleuHStQ4vdSIN+FXujU8z7w53D yAoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2DGeNqrAocEQBW3s9u83YvGPr3pag37tdDcMnd/na+Q=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=VDQITiBZUeWQGIOm/PNozyvvb1TfqH68spDqGlVtXA97DwG5yGkIPwrzwd87tBkIf2 66X9ApgiVOaw4igXM08EQvYe0eEUJX4/UuOlr2TzpiBgdn2MIwxzW3b+wWEU+QaAuiLs bcMEN7FFKO7x2zSNDambas9Fv5FiRLnFic4OCHx7GOwBWF6KorMX0k03TsT3Dd6LOC6K qTl0u77GdFTAnW0at6FltPXIAHQCyC7D32i6YSuN1XDJ5L8ahz7CEDzdNNjvnIf1dzou zB7YzGU4emkGW0xj/MfdNN6thebR2GITcTWgxbCezYrE5kab6IJ/l7hoMNpQiKlgd+8O 3QDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UA6D7EO5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 08/33] target/cris: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:18 +1000 Message-Id: <20240129233043.34558-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/cris/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 6349148b65..163fb05d58 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -56,6 +56,11 @@ static bool cris_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } +static int cris_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return !!(cpu_env(cs)->pregs[PR_CCS] & U_FLAG); +} + static void cris_cpu_reset_hold(Object *obj) { CPUState *s = CPU(obj); @@ -274,6 +279,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = cris_cpu_class_by_name; cc->has_work = cris_cpu_has_work; + cc->mmu_index = cris_cpu_mmu_index; cc->dump_state = cris_cpu_dump_state; cc->set_pc = cris_cpu_set_pc; cc->get_pc = cris_cpu_get_pc; From patchwork Mon Jan 29 23:30:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767481 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1127345wro; Mon, 29 Jan 2024 15:37:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IG6cbb+hM6Qi26KIAhNmpTofZZUxbu/nXnJwaGjil+Zom49zPerttgznhLzmJY1xJXbeUMT X-Received: by 2002:a05:620a:1118:b0:783:e17c:2f74 with SMTP id o24-20020a05620a111800b00783e17c2f74mr114673qkk.46.1706571457875; Mon, 29 Jan 2024 15:37:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571457; cv=none; d=google.com; s=arc-20160816; b=N6EWU04aTGaf3acwvKFn3t03Nlh6i2bVaQKf1MtUXHwTpat4tj1e9vppUHQ3VzzHXl AoVwY1qBiDTrCd/7DS4wA4uNtNPkdeMk2y0TshtxwoJ0Z03qZr0hWHAuJSa8EpE01ATi IwU/By+IXDb7CS2jBzv+hqyh6HaNHWCzoTqfUsFJKN8XOe0y86BmDNxgAsmJAG0HSTUb O7Deuu6F5erJtW/HDeN/t+lXaqtKPXJO6oD5EMCWI22m2Pogv3YXr0vp6KSxsXI2ZhD6 Vkt1u9HdyYbwQOR4fEuT0yKeKCOYsJkZFFjqxoMyqSDRSMuj9mWIh6vtJ2cYqYFRmgd/ pmdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZpWWy5vO/pXMstRanLNjNwO63iDqbDF9cuw2FeN4mjg=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=BAYY/NwA0pzeTrL4TSKRTtxgEhUq/IklPUXjyuTUvXDt3DclcGMaoYHONUC70mQ9Ww 5V+K0IZOCZbuuIV6Z2a9fGBNsozasAuVKBEmKHGvIJR+26qHzkYyE65KcCc+KuPKANU0 KLWS9hcTNjvoJ7RZzyRmkueKr/xwbSXAfu3PwCW0xcUgvic/ob3u3stryZIzLcEx18ao j6VXq53LEjxJLpKtr1msKqBKYunU591rUC5avJKSk5aaFsLMuvye+IGqgco1fty4IUoa NQ9caoDDcTR+ymP7OZXB9HCBP/Fvxq5wn3J/vw4yOZcJDRBYtAJkW+KdcRh4LkKDAWuL Tusw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LbLWACt3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 09/33] target/hppa: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:19 +1000 Message-Id: <20240129233043.34558-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/cpu.h | 7 ++----- target/hppa/cpu.c | 12 ++++++++++++ 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 6a153405d2..04439f247d 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -281,16 +281,13 @@ static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE; } +int hppa_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return MMU_USER_IDX; #else - if (env->psw & (ifetch ? PSW_C : PSW_D)) { - return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P); - } - /* mmu disabled */ - return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; + return hppa_cpu_mmu_index(env_cpu(env), ifetch); #endif } diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 3c019855b4..fbb37e541e 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -94,6 +94,17 @@ static bool hppa_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } +int hppa_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUHPPAState *env = cpu_env(cs); + + if (env->psw & (ifetch ? PSW_C : PSW_D)) { + return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P); + } + /* mmu disabled */ + return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; +} + static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) { info->mach = bfd_mach_hppa20; @@ -194,6 +205,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = hppa_cpu_class_by_name; cc->has_work = hppa_cpu_has_work; + cc->mmu_index = hppa_cpu_mmu_index; cc->dump_state = hppa_cpu_dump_state; cc->set_pc = hppa_cpu_set_pc; cc->get_pc = hppa_cpu_get_pc; From patchwork Mon Jan 29 23:30:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767464 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1125978wro; Mon, 29 Jan 2024 15:33:05 -0800 (PST) X-Google-Smtp-Source: AGHT+IHRcTyd19jtp+Lq+WaR91iBp0JwKYThMfhCShAY/rtKL0JJBvw4eizJqFypRwRKm7UX2rtL X-Received: by 2002:a05:620a:cd1:b0:783:316b:890 with SMTP id b17-20020a05620a0cd100b00783316b0890mr7310734qkj.46.1706571185434; Mon, 29 Jan 2024 15:33:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571185; cv=none; d=google.com; s=arc-20160816; b=tiScCm7yXPIgvRTIp+xjr7DXzQb24xQ/eTijJEmC+FWk4SoD+luhd2HdHb/8nVP+Oa M+0RDaplT/hUGLThYRYBzK9OPGsjHpw7na6ggGp71gXFdlYieFlETFZp7bNUVptH22Az /GRpf25e/0XPbPC14mTrM4/hs/xWeqjWYtYZ9qT30WevnVbvW/S4sN7C/Fxp05WcVWIn JcsGnrKcbJJW69tFx8K4c9fslAcQlDJmtn805CTaP6OnPcjTvZYyiJ9RyM1UtENuhLE/ 78RW6TC6RlWLawxLJeRglKyEAxZecSE8ZYSPVI2zoXM/YtvpIVz7PCxq5/UiW6XqiKV3 W8tQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7WexDgLCM7IRsjNLi1wAJoGpQCSOk7DFJRsVIQhRYNU=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=KWA9sjX7LReqp/tTUkabGUzfxoJox3H/flHl1qpWZqoTvmCl3DZDQxUCv1cLNHu4Tc ncaGvckks0YL6gDEnduZlUqo+WSmYPA2e3Pqh5POspOX7Ae13wlh8GbRE5pOdTpN5udq IfDIasyetF4QL6foB8qbKRrvvcjEtYFPNIznm6NUFZSvBUJkR87TqT6ycfb0xmALbsA7 SxdvwrQam8xpniTeH0BgZoyN21pTyJG2vclRE5M+kv5ZtayoEPh9VcT3DxJqLHAe3eYy QBiWWHYaJXpwJGK/y3DZpV+WcQo5x7KHI4recwfRpY1CIJQ/nCxC7Bp0Usmt0WZp6JJ6 vsvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=V4X37Uqi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 10/33] target/i386: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:20 +1000 Message-Id: <20240129233043.34558-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/i386/cpu.h | 13 ++++++------- target/i386/cpu.c | 10 ++++++++++ 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7f0786e8b9..62bdb02378 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2296,13 +2296,6 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define MMU_NESTED_IDX 3 #define MMU_PHYS_IDX 4 -static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) -{ - return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : - (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) - ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; -} - static inline int cpu_mmu_index_kernel(CPUX86State *env) { return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : @@ -2322,6 +2315,12 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env) #include "hw/i386/apic.h" #endif +int x86_cpu_mmu_index(CPUState *cs, bool ifetch); +static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) +{ + return x86_cpu_mmu_index(env_cpu(env), ifetch); +} + static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 03822d9ba8..280bcb7d00 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7720,6 +7720,15 @@ static bool x86_cpu_has_work(CPUState *cs) return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; } +int x86_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUX86State *env = cpu_env(cs); + + return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : + (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) + ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; +} + static void x86_disas_set_info(CPUState *cs, disassemble_info *info) { X86CPU *cpu = X86_CPU(cs); @@ -7954,6 +7963,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) cc->class_by_name = x86_cpu_class_by_name; cc->parse_features = x86_cpu_parse_featurestr; cc->has_work = x86_cpu_has_work; + cc->mmu_index = x86_cpu_mmu_index; cc->dump_state = x86_cpu_dump_state; cc->set_pc = x86_cpu_set_pc; cc->get_pc = x86_cpu_get_pc; From patchwork Mon Jan 29 23:30:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767478 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1127052wro; Mon, 29 Jan 2024 15:36:41 -0800 (PST) X-Google-Smtp-Source: AGHT+IFDKR/gUSf+kaerErgvz5jp+ZT22ib0D08llcY2PdmeSePcrg2Bm1R5W+fZ7XZWu9zcBsLz X-Received: by 2002:a05:6808:ece:b0:3bd:f41f:f98c with SMTP id q14-20020a0568080ece00b003bdf41ff98cmr9471359oiv.29.1706571399246; Mon, 29 Jan 2024 15:36:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571399; cv=none; d=google.com; s=arc-20160816; b=BRGNtSzX9RKzOUXL1Ij6ru8r0L1jFLD4jexs3+I8Dl4PtwHl0kTFoCPB1ed5XGbUnC DBbbnCylui6TEYvL6qG15PXQGbyKQBaPdN+cjTBPp8Q/UKB+57oCc1CsfpUZdW2ivhY6 LxKTfZfLyLR4dpImazni0PKFo6/LB/K2s+8uG8rAsSmBtzcg9XEMu0cRKhh5w9TWGjBK /0g94IymPowCgRW8IYiX2C62jTuYpF+sgZW2RXnfG/hUK9V4TLFA7x8MFVaU/f3PNug+ nR8AfHiyOT1pDNaErejrZz1CfRcTIRf1XgrCJxEcfZKW4OHC7SyxRwQGTFNmg2+VoADy SqGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=O5n462vNeMjlBZwwraV55qst2NUkc1xnzZuaJY63KTM=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=q3MNQSVjFxF+hkK20PXYKdDTAEF5eXeVHTqah9Vyyj102aQYqkppWsxH+6jQWjhEwY +0f9gyyqvS+Nd/FuN7yRBEp5qr7BZcg8+eNHL3tKshbFqlLRPk8ljcnkRQaPT+/7dzUf DG2Yzg6CP4NLu4HlOIK4W9dfQQkw0tAqUuUnJ/WgyBhb/XGoeuUSbyXGOH11h+VXtMl6 9JBdAcsTR3W6hN5YKkBqbMA8N9zXjzDy2Y/ewkqAZU7Cr+xR2rUgBoFR2hOfj4HAWRc5 mBF+lFgc/CJ9WDo9NDO1dJ4i64HZf/Upm0Jt7jpzi8bfFn6avyhILdCBaemgsyY/dUbA rdDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RkQ5cQuy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 11/33] target/loongarch: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:21 +1000 Message-Id: <20240129233043.34558-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/loongarch/cpu.h | 6 ++---- target/loongarch/cpu.c | 11 +++++++++++ 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 0fa5e0ca93..5dfcfeb3a4 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -408,15 +408,13 @@ struct LoongArchCPUClass { #define MMU_IDX_USER MMU_PLV_USER #define MMU_IDX_DA 4 +int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return MMU_IDX_USER; #else - if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { - return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); - } - return MMU_IDX_DA; + return loongarch_cpu_mmu_index(env_cpu(env), ifetch); #endif } diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index fb8dde7def..cbecc63213 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -375,6 +375,16 @@ static bool loongarch_cpu_has_work(CPUState *cs) #endif } +int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPULoongArchState *env = cpu_env(cs); + + if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { + return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); + } + return MMU_IDX_DA; +} + static void loongarch_la464_initfn(Object *obj) { LoongArchCPU *cpu = LOONGARCH_CPU(obj); @@ -779,6 +789,7 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data) cc->class_by_name = loongarch_cpu_class_by_name; cc->has_work = loongarch_cpu_has_work; + cc->mmu_index = loongarch_cpu_mmu_index; cc->dump_state = loongarch_cpu_dump_state; cc->set_pc = loongarch_cpu_set_pc; cc->get_pc = loongarch_cpu_get_pc; From patchwork Mon Jan 29 23:30:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767462 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1125667wro; Mon, 29 Jan 2024 15:32:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IEk752f8eWkp8iB7dbi/gZrymCiBdh+4pG9XPp/AlBqAMmDlZEYV65Zsf/1Dw4kQXQ/bT84 X-Received: by 2002:a05:6102:3b87:b0:46b:3d9c:99cd with SMTP id z7-20020a0561023b8700b0046b3d9c99cdmr2473362vsu.15.1706571124620; Mon, 29 Jan 2024 15:32:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571124; cv=none; d=google.com; s=arc-20160816; b=zCr6sFjBoef7a8Otm13ZsvtC8COXkqjp5GxY6hHghGDuKNgfjDb4MpI1HbOTHKRsLF fnJT7tK/0EaqrXfhBbv8oX1N2/Tjtocl6AdvF6B3s5n0CTmwwsRmQWwYhh9Sd7J3kzFQ Qz7eB3Fi1YnpACVmZISLJ2OvkPb7tK3Mu3VQToXi0SeWkhlaMmqUJ2VKw1ubqMIIf5PU H2FGjJkKcgwphiukXjLS9/G9LpwzisGbiUH7thPiN6lWT+NNComR2Jw0e74orlV1VMFb Mf8QCYMW6Z9QMnS0uNhyAdNcbKmsltxl4jyazDWZpnR8uwvPXhY/fhWLLrzdpZJD8GiT rH+w== ARC-Message-Signature: i=1; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 12/33] target/loongarch: Rename MMU_IDX_* Date: Tue, 30 Jan 2024 09:30:22 +1000 Message-Id: <20240129233043.34558-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The expected form is MMU_FOO_IDX, not MMU_IDX_FOO. Rename to match generic code. Signed-off-by: Richard Henderson --- target/loongarch/cpu.h | 8 ++++---- target/loongarch/cpu.c | 2 +- target/loongarch/tcg/tlb_helper.c | 4 ++-- target/loongarch/tcg/translate.c | 2 +- target/loongarch/tcg/insn_trans/trans_privileged.c.inc | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 5dfcfeb3a4..47fd110e81 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -404,15 +404,15 @@ struct LoongArchCPUClass { */ #define MMU_PLV_KERNEL 0 #define MMU_PLV_USER 3 -#define MMU_IDX_KERNEL MMU_PLV_KERNEL -#define MMU_IDX_USER MMU_PLV_USER -#define MMU_IDX_DA 4 +#define MMU_KERNEL_IDX MMU_PLV_KERNEL +#define MMU_USER_IDX MMU_PLV_USER +#define MMU_DA_IDX 4 int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY - return MMU_IDX_USER; + return MMU_USER_IDX; #else return loongarch_cpu_mmu_index(env_cpu(env), ifetch); #endif diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index cbecc63213..139acfe373 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -382,7 +382,7 @@ int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); } - return MMU_IDX_DA; + return MMU_DA_IDX; } static void loongarch_la464_initfn(Object *obj) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index 449043c68b..65ffbef08e 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -188,8 +188,8 @@ static int get_physical_address(CPULoongArchState *env, hwaddr *physical, int *prot, target_ulong address, MMUAccessType access_type, int mmu_idx) { - int user_mode = mmu_idx == MMU_IDX_USER; - int kernel_mode = mmu_idx == MMU_IDX_KERNEL; + int user_mode = mmu_idx == MMU_USER_IDX; + int kernel_mode = mmu_idx == MMU_KERNEL_IDX; uint32_t plv, base_c, base_v; int64_t addr_high; uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA); diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c index 235515c629..58674cb268 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -125,7 +125,7 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase, if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) { ctx->mem_idx = ctx->plv; } else { - ctx->mem_idx = MMU_IDX_DA; + ctx->mem_idx = MMU_DA_IDX; } /* Bound the number of insns to execute to those left on the page. */ diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc index 01d457212b..7e4ec93edb 100644 --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc @@ -323,7 +323,7 @@ TRANS(iocsrwr_d, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_d) static void check_mmu_idx(DisasContext *ctx) { - if (ctx->mem_idx != MMU_IDX_DA) { + if (ctx->mem_idx != MMU_DA_IDX) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4); 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 13/33] target/m68k: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:23 +1000 Message-Id: <20240129233043.34558-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/m68k/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 44000f5869..8a8392e694 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -56,6 +56,11 @@ static bool m68k_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } +static int m68k_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return cpu_env(cs)->sr & SR_S ? MMU_KERNEL_IDX : MMU_USER_IDX; +} + static void m68k_set_feature(CPUM68KState *env, int feature) { env->features |= BIT_ULL(feature); @@ -551,6 +556,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) cc->class_by_name = m68k_cpu_class_by_name; cc->has_work = m68k_cpu_has_work; + cc->mmu_index = m68k_cpu_mmu_index; cc->dump_state = m68k_cpu_dump_state; cc->set_pc = m68k_cpu_set_pc; cc->get_pc = m68k_cpu_get_pc; From patchwork Mon Jan 29 23:30:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767490 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1127942wro; Mon, 29 Jan 2024 15:39:49 -0800 (PST) X-Google-Smtp-Source: AGHT+IGVH+XbnSjfUpL/tT83yPChupv7Rr0UofJr0xa7owaZq7gZHI/m95DKnVL4twBGmNlHq8Jm X-Received: by 2002:ac8:5f92:0:b0:42a:b169:4147 with SMTP id j18-20020ac85f92000000b0042ab1694147mr1025335qta.28.1706571589098; Mon, 29 Jan 2024 15:39:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571589; cv=none; d=google.com; s=arc-20160816; b=IsKBFjxBFqyR8aQbJj00C1EPZsrwSWAr4BYYkK3KhuhQCtgK12RC23JYGArsrQTYO3 PDRVLhpGcUdkWH9hTmr6s1TUnyjA4SILfLDYhD37eyMWHRuQ5x3y9xmIpzd/O4czJdsT kxf0nReVFXAD1HL9zMgaN8VfQkusIYfts+NSOONVC94dcbROd/1k0hVrd6PFkb9OVvUy tXSs9V2O8pzwElI2wwbGDOH2NHxF5MahgKYLMxI11lvCRPRn5l5UM2lDLuu00C4bW0OZ JuqvjdoI9AXRe98hRq7gzwbxrMsEBCKfK5HHWxY/u+6bOZ4MaEGqEewq9lHa9WenEPfs ewTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zRmglClgoVHSDx5STL3QfC7K3ahzi83m4KSgoX1Lwpc=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=tve4/wgjz1Gh01VBnd+awof4Cqf81nWxcvvmflEMQRl5P2ORpow/bVvv1Y9HnIhXMg yOB42L62rrxxG1Bjlh/tL0LQTr8EK+ypQ2lp/f7BGaaXTlaz5mriXPwY2zSP9X9x2QU1 frC6iE41WqaaGiAHfcarATSyD1W7MzCO92BUS3bBVdKOLbc8zh5tYsU+XvPinonR+BXl OrePW4sBSoufhAWYb4u/MXu2cqk1YbIPmFQP60KOAVN5upIKO6ftnlOcrYvcPriOkMeI xvXIKXaKv/bO+vyzD+vwxXwMP+hSHEH8T01qmr8+K6bDXtaGu30rRNFL0qlQjGP9U41J F0sw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B8gQYTaC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 14/33] target/microblaze: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:24 +1000 Message-Id: <20240129233043.34558-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 13 ++----------- target/microblaze/cpu.c | 18 +++++++++++++++++- 2 files changed, 19 insertions(+), 12 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b5374365f5..90ab796de9 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -434,19 +434,10 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, MemTxResult response, uintptr_t retaddr); #endif +int mb_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) { - MicroBlazeCPU *cpu = env_archcpu(env); - - /* Are we in nommu mode?. */ - if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { - return MMU_NOMMU_IDX; - } - - if (env->msr & MSR_UM) { - return MMU_USER_IDX; - } - return MMU_KERNEL_IDX; + return mb_cpu_mmu_index(env_cpu(env), ifetch); } #ifndef CONFIG_USER_ONLY diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 2318ad7013..6dad11905b 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -118,6 +118,22 @@ static bool mb_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } +int mb_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUMBState *env = cpu_env(cs); + MicroBlazeCPU *cpu = env_archcpu(env); + + /* Are we in nommu mode?. */ + if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { + return MMU_NOMMU_IDX; + } + + if (env->msr & MSR_UM) { + return MMU_USER_IDX; + } + return MMU_KERNEL_IDX; +} + #ifndef CONFIG_USER_ONLY static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level) { @@ -415,7 +431,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = mb_cpu_class_by_name; cc->has_work = mb_cpu_has_work; - + cc->mmu_index = mb_cpu_mmu_index; cc->dump_state = mb_cpu_dump_state; cc->set_pc = mb_cpu_set_pc; cc->get_pc = mb_cpu_get_pc; From patchwork Mon Jan 29 23:30:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767473 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1126666wro; Mon, 29 Jan 2024 15:35:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IGzUXOFbuCOioyUiZQbgc88bquSgQUnDJZD3EIRQU34cDtmqTHoccvs6SEp8y2ovODlF5N8 X-Received: by 2002:a25:c5c2:0:b0:dc2:65f4:1541 with SMTP id v185-20020a25c5c2000000b00dc265f41541mr3925707ybe.41.1706571324656; Mon, 29 Jan 2024 15:35:24 -0800 (PST) ARC-Seal: i=1; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 15/33] target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill Date: Tue, 30 Jan 2024 09:30:25 +1000 Message-Id: <20240129233043.34558-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rather than adjust env->hflags so that the value computed by cpu_mmu_index() changes, compute the mmu_idx that we want directly and pass it down. Introduce symbolic constants for MMU_{KERNEL,ERL}_IDX. Signed-off-by: Richard Henderson --- target/mips/cpu.h | 4 +++- target/mips/tcg/sysemu/tlb_helper.c | 32 ++++++++++++----------------- 2 files changed, 16 insertions(+), 20 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 1163a71f3c..3ba8dccd2d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1242,12 +1242,14 @@ uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); * MMU modes definitions. We carefully match the indices with our * hflags layout. */ +#define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 2 +#define MMU_ERL_IDX 3 static inline int hflags_mmu_index(uint32_t hflags) { if (hflags & MIPS_HFLAG_ERL) { - return 3; /* ERL */ + return MMU_ERL_IDX; } else { return hflags & MIPS_HFLAG_KSU; } diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index 4ede904800..b715449114 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -623,7 +623,7 @@ static uint64_t get_tlb_entry_layout(CPUMIPSState *env, uint64_t entry, static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, int directory_index, bool *huge_page, bool *hgpg_directory_hit, uint64_t *pw_entrylo0, uint64_t *pw_entrylo1, - unsigned directory_shift, unsigned leaf_shift) + unsigned directory_shift, unsigned leaf_shift, int ptw_mmu_idx) { int dph = (env->CP0_PWCtl >> CP0PC_DPH) & 0x1; int psn = (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F; @@ -638,8 +638,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, uint64_t w = 0; if (get_physical_address(env, &paddr, &prot, *vaddr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) != - TLBRET_MATCH) { + ptw_mmu_idx) != TLBRET_MATCH) { /* wrong base address */ return 0; } @@ -666,8 +665,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, *pw_entrylo0 = entry; } if (get_physical_address(env, &paddr, &prot, vaddr2, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) != - TLBRET_MATCH) { + ptw_mmu_idx) != TLBRET_MATCH) { return 0; } if (!get_pte(env, vaddr2, leafentry_size, &entry)) { @@ -690,7 +688,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, } static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, - int mmu_idx) + int ptw_mmu_idx) { int gdw = (env->CP0_PWSize >> CP0PS_GDW) & 0x3F; int udw = (env->CP0_PWSize >> CP0PS_UDW) & 0x3F; @@ -776,7 +774,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, vaddr |= goffset; switch (walk_directory(env, &vaddr, pf_gdw, &huge_page, &hgpg_gdhit, &pw_entrylo0, &pw_entrylo1, - directory_shift, leaf_shift)) + directory_shift, leaf_shift, ptw_mmu_idx)) { case 0: return false; @@ -793,7 +791,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, vaddr |= uoffset; switch (walk_directory(env, &vaddr, pf_udw, &huge_page, &hgpg_udhit, &pw_entrylo0, &pw_entrylo1, - directory_shift, leaf_shift)) + directory_shift, leaf_shift, ptw_mmu_idx)) { case 0: return false; @@ -810,7 +808,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, vaddr |= moffset; switch (walk_directory(env, &vaddr, pf_mdw, &huge_page, &hgpg_mdhit, &pw_entrylo0, &pw_entrylo1, - directory_shift, leaf_shift)) + directory_shift, leaf_shift, ptw_mmu_idx)) { case 0: return false; @@ -825,8 +823,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, /* Leaf Level Page Table - First half of PTE pair */ vaddr |= ptoffset0; if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) != - TLBRET_MATCH) { + ptw_mmu_idx) != TLBRET_MATCH) { return false; } if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { @@ -838,8 +835,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, /* Leaf Level Page Table - Second half of PTE pair */ vaddr |= ptoffset1; if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) != - TLBRET_MATCH) { + ptw_mmu_idx) != TLBRET_MATCH) { return false; } if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { @@ -944,12 +940,10 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, * Memory reads during hardware page table walking are performed * as if they were kernel-mode load instructions. */ - int mode = (env->hflags & MIPS_HFLAG_KSU); - bool ret_walker; - env->hflags &= ~MIPS_HFLAG_KSU; - ret_walker = page_table_walk_refill(env, address, mmu_idx); - env->hflags |= mode; - if (ret_walker) { + int ptw_mmu_idx = (env->hflags & MIPS_HFLAG_ERL ? + MMU_ERL_IDX : MMU_KERNEL_IDX); + + if (page_table_walk_refill(env, address, ptw_mmu_idx)) { ret = get_physical_address(env, &physical, &prot, address, access_type, mmu_idx); if (ret == TLBRET_MATCH) { From patchwork Mon Jan 29 23:30:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767470 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1126482wro; Mon, 29 Jan 2024 15:34:50 -0800 (PST) X-Google-Smtp-Source: AGHT+IFEM/iz+GHUE56mL92IwubT3NpQ/yY77YveBaZNl/lzIiXfGd2owKclKbVfqfGwPyo8gL8+ X-Received: by 2002:ac8:7f82:0:b0:42a:32d0:49cc with SMTP id z2-20020ac87f82000000b0042a32d049ccmr10114036qtj.63.1706571289960; Mon, 29 Jan 2024 15:34:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571289; cv=none; d=google.com; s=arc-20160816; b=in/QkLgq5qqJrK8SR5brysKa3Rt0QRufXtd+Sdw7CY/DxgrU0WgfiBtCYzBG45UJRC LowZMNheRqEf4wMPmincFXiLSQO+x+0jEFJmvUx7XiNTYSkgW8AYC0AdOkq+U4R4deT+ VzZGeIK8uRgdNNessK65/KBmz5u1OIYr+lz7m0yalbr4udmqYo61Z5VMCHq0RXy0mDD6 DJmHk4LKr4hT0JoBq/VNWrxRMm7fm+3TBBDhKg8+JOu6qyrQMdCtFRBuFPoapcp2OwQc KOq8L2zv/Ebfr1PTIJoEKSIWpPODIjLcCP+Nt53sLX/a4T7o5oEu5ZY86a0T9gcHt85o 0Rhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+TWhdTukAWg6C2H3nrXhuQpGBPdO1u3jsZKcAzF+cD4=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=nhDQuApO3u+6xF0aPORgt6VTeuphk614pxaTFslRZgCs/B2KIsc8ONiqwxKf5en0Rg LHS0J1vkEtCep0VW4T3bHAhJyM1nuLIDl2+d4aFgvQIcYS8RfrNgkZWYNnEKMs4SwwJ7 S4OkV7JmU/kRYkzwxzSB+xfOV5kudExhOvdaBOUwEvs6pzFFLjcLI0EjUB/efDK/8AAR PxB5Vg2NEtZ6uwi2mYICo3TkVfxydj8aK7+R+W8HDAVNqKmpHzLa4PLM3QUj2/evprr3 h+F01rjc4LcDdkMKGim80YCzpQnuoS2IypiHzMDjUrnbzp/PEi+/a6Kn+FHlpfE5Eh/s H13g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="QJ+O/poa"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 16/33] target/mips: Split out mips_env_mmu_index Date: Tue, 30 Jan 2024 09:30:26 +1000 Message-Id: <20240129233043.34558-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/mips/cpu.h | 7 ++++++- target/mips/sysemu/physaddr.c | 2 +- target/mips/tcg/msa_helper.c | 10 +++++----- target/mips/tcg/sysemu/cp0_helper.c | 2 +- target/mips/tcg/sysemu/special_helper.c | 2 +- target/mips/tcg/sysemu/tlb_helper.c | 2 +- 6 files changed, 15 insertions(+), 10 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3ba8dccd2d..4c15e76781 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1255,11 +1255,16 @@ static inline int hflags_mmu_index(uint32_t hflags) } } -static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) +static inline int mips_env_mmu_index(CPUMIPSState *env) { return hflags_mmu_index(env->hflags); } +static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) +{ + return mips_env_mmu_index(env); +} + #include "exec/cpu-all.h" /* Exceptions */ diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c index 05990aa5bb..13c8bc8f47 100644 --- a/target/mips/sysemu/physaddr.c +++ b/target/mips/sysemu/physaddr.c @@ -236,7 +236,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) int prot; if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) != 0) { + mips_env_mmu_index(env)) != 0) { return -1; } return phys_addr; diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 7a8dbada5d..d2181763e7 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8214,7 +8214,7 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd, #if !defined(CONFIG_USER_ONLY) #define MEMOP_IDX(DF) \ MemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \ - cpu_mmu_index(env, false)); + mips_env_mmu_index(env)); #else #define MEMOP_IDX(DF) #endif @@ -8323,7 +8323,7 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = mips_env_mmu_index(env); uintptr_t ra = GETPC(); ensure_writable_pages(env, addr, mmu_idx, ra); @@ -8337,7 +8337,7 @@ void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = mips_env_mmu_index(env); uintptr_t ra = GETPC(); uint64_t d0, d1; @@ -8358,7 +8358,7 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = mips_env_mmu_index(env); uintptr_t ra = GETPC(); uint64_t d0, d1; @@ -8379,7 +8379,7 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, target_ulong addr) { wr_t *pwd = &(env->active_fpu.fpr[wd].wr); - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = mips_env_mmu_index(env); uintptr_t ra = GETPC(); ensure_writable_pages(env, addr, mmu_idx, GETPC()); diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c index cc545aed9c..62f6fb4bf6 100644 --- a/target/mips/tcg/sysemu/cp0_helper.c +++ b/target/mips/tcg/sysemu/cp0_helper.c @@ -1202,7 +1202,7 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) old, old & env->CP0_Cause & CP0Ca_IP_mask, val, val & env->CP0_Cause & CP0Ca_IP_mask, env->CP0_Cause); - switch (cpu_mmu_index(env, false)) { + switch (mips_env_mmu_index(env)) { case 3: qemu_log(", ERL\n"); break; diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/sysemu/special_helper.c index 93276f789d..518d3fbc34 100644 --- a/target/mips/tcg/sysemu/special_helper.c +++ b/target/mips/tcg/sysemu/special_helper.c @@ -68,7 +68,7 @@ static void debug_post_eret(CPUMIPSState *env) if (env->hflags & MIPS_HFLAG_DM) { qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); } - switch (cpu_mmu_index(env, false)) { + switch (mips_env_mmu_index(env)) { case 3: qemu_log(", ERL\n"); break; diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index b715449114..cdae42ffdd 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -973,7 +973,7 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, /* data access */ ret = get_physical_address(env, &physical, &prot, address, access_type, - cpu_mmu_index(env, false)); + mips_env_mmu_index(env)); if (ret == TLBRET_MATCH) { return physical; } From patchwork Mon Jan 29 23:30:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767491 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1127961wro; Mon, 29 Jan 2024 15:39:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IFqk2PAXwZjPXVhL+6bs9xeaLgvw1Laq2wAQWlJ40ODY9RgDuQrFwMasNOhSfeN5Ve1OR+R X-Received: by 2002:a05:622a:449:b0:42a:6ce0:68c7 with SMTP id o9-20020a05622a044900b0042a6ce068c7mr8437680qtx.100.1706571592958; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 17/33] target/mips: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:27 +1000 Message-Id: <20240129233043.34558-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/mips/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index df544ab39b..d644adbc77 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -182,6 +182,11 @@ static bool mips_cpu_has_work(CPUState *cs) return has_work; } +static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) +{ + return mips_env_mmu_index(cpu_env(cs)); +} + #include "cpu-defs.c.inc" static void mips_cpu_reset_hold(Object *obj) @@ -579,6 +584,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) cc->class_by_name = mips_cpu_class_by_name; cc->has_work = mips_cpu_has_work; + cc->mmu_index = mips_cpu_mmu_index; cc->dump_state = mips_cpu_dump_state; cc->set_pc = mips_cpu_set_pc; cc->get_pc = mips_cpu_get_pc; From patchwork Mon Jan 29 23:30:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767487 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1127908wro; Mon, 29 Jan 2024 15:39:41 -0800 (PST) X-Google-Smtp-Source: AGHT+IGKiUQaWjtrX5/s3yrTDcZ4cH5ygUQRZ2Ainzpa5WBP2c2fpg+D6A0Qilfw4PCcanX2R7j9 X-Received: by 2002:a05:620a:4546:b0:783:f6a7:6d9c with SMTP id u6-20020a05620a454600b00783f6a76d9cmr3727672qkp.27.1706571581367; Mon, 29 Jan 2024 15:39:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571581; cv=none; d=google.com; s=arc-20160816; b=n15Iwt4v+CI2cW+IxiWxMAHAqkkVUD1+OZj68TcNCIT12rR+045z1LHNtE1v6Ch8mS 9IrRWL5q2UzKUMXMmcD7/v3LPeZ3Kj1hVRmdfQWqmIB5lVL2wijgNnXa5Tz+9NkcmxaY /pKWoZPXIV07y8HNjBvSR3RtkeqKR5Z21+xTHdKkr9jfDOdPbuLROQOVD+f2VGHG/fap /2DFNg+6v5QYQ/jqtI4v2EdZsrHBOXxFtPoWhOadhx6xXEEgNNsoZ52bYMqHDD3jxlTl h5N5m4dN3ruNMdbn7WEnG4qa+dO7GNQXyi7vVga8B4IISXnOD00o1dts9JAJHSToYKLa wbDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YucELH6fbErp+6umx07QFC7pYx6ueR6ifc1TTKY+quw=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=ChBsA99Q5U2bZ9WMqWmJCQpBIeb0vU7BF8g+ZwR7YCriEx+NqcfaP7+hP6JC7r1Doj S55P1a/0DtsFy4Eb2HnxePmTVCK4Kk4lr5uQBjanuoNctlBWNJM5m+sImKPmFedprSH0 6XHyeWwqbNZufDCFsmjJNIucTM51ybNvqm8dNa0bS3nGYzak/1vp/q1sw6PtrL3kCbRw 1CqghEzKbTRDUSQ3ieoDIcgS/xaDwkp7TtH/WsNYpkEbu1vSQ6aeyGnFi9HCDi4Ibp6P 6+UnIEvpj0xukyMhRJR0L9v2X5SNHhL8uwQczaZPNDEgtbOB0mHu3yXSAIiYehc+jqm8 SShA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Xd1j6lJm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 18/33] target/nios2: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:28 +1000 Message-Id: <20240129233043.34558-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 12 ++++++------ target/nios2/cpu.c | 7 +++++++ 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2d79b5b298..9965ff74c1 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -270,12 +270,6 @@ void do_nios2_semihosting(CPUNios2State *env); #define MMU_SUPERVISOR_IDX 0 #define MMU_USER_IDX 1 -static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) -{ - return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX : - MMU_SUPERVISOR_IDX; -} - #ifndef CONFIG_USER_ONLY hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, @@ -292,6 +286,12 @@ FIELD(TBFLAGS, CRS0, 0, 1) /* Set if CRS == 0. */ FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */ FIELD(TBFLAGS, R0_0, 2, 1) /* Set if R0 == 0. */ +int nios2_cpu_mmu_index(CPUState *cs, bool ifetch); +static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) +{ + return nios2_cpu_mmu_index(env_cpu(env), ifetch); +} + static inline void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 596c0c5617..e42885997e 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -57,6 +57,12 @@ static bool nios2_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } +int nios2_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return (cpu_env(cs)->ctrl[CR_STATUS] & CR_STATUS_U + ? MMU_USER_IDX : MMU_SUPERVISOR_IDX); +} + static void nios2_cpu_reset_hold(Object *obj) { CPUState *cs = CPU(obj); @@ -381,6 +387,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = nios2_cpu_class_by_name; cc->has_work = nios2_cpu_has_work; + cc->mmu_index = nios2_cpu_mmu_index; cc->dump_state = nios2_cpu_dump_state; cc->set_pc = nios2_cpu_set_pc; cc->get_pc = nios2_cpu_get_pc; From patchwork Mon Jan 29 23:30:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767465 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1126075wro; Mon, 29 Jan 2024 15:33:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IGgYVGs1/9BEqGxRUHG4AAPr2smlaWJpYEoU60mSaKrlRUuO5XIL4S3zZgQlSKb5BeR85K9 X-Received: by 2002:a05:6808:10d5:b0:3bd:f9b0:d4fa with SMTP id s21-20020a05680810d500b003bdf9b0d4famr6527124ois.28.1706571203956; Mon, 29 Jan 2024 15:33:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571203; cv=none; d=google.com; s=arc-20160816; b=hDxazQpdy/YiL0aBtpyYuvfOPPWsHdLvnlGs1QIguRlYet1w/ZJZ2nT33o2RBduQsZ z/2iEfsP8CS2Ka3R+MQgZIN2OSI5OKH4HmzOs/FwaO6V1vRPYQ79t9Jou9Dg2TXZBqwk sCxr3upXru+O7RhgRhrSAZT2BQU9YdhFOv+n3/VKMIvsJqCu6x9WOw71Iw4/0zc2tjA9 Kmk8eGrnnEUYv2H78dsc/Vlashv7kB9XUoE7X+xud70uek24Oa6EUVU07kT+DxAFbyxi f5dVP/MILhm+uAeYH9zjDeM8H4nVQa9nqrpqtIO4ICvy8o5jyAmBTnwSXOVKYZQq4D6R OsYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KeckyFuoEvdgwHDKZRRirlX+WDs+LbKrZFrG7XL0TJk=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=Fsu0M7UW8PnoDhC4c9BKdcsxIAk4H+jvGyR6ZCHzsTdKte+T8Q2L5JDSysTsplDn25 raH6LzMxRjJX/Vow2GyGV7ymND6d7hQQ7LHpK4tkorg3BP5Q4x2ZfiCXIIg0yk3bCQh6 byQ0jKoA2Q2CLdOGbvsDVe0DaFRSeMBp3caXg9qKiiJOruEsY8dMSow9soGLujtrNE7R rmwxc/2XnJO5q1CtVMGduySycBCakKUJX6JPDfn0hP4TRscnBQOtMGUv36lYFVjfkayc BYvvOUq1GODz/E0di0+lw9Xw6wjqExHYN8htgCvmMxNEVsPhZJUAW7MYPhe7TrTnVueL p1+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xnik9OU4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 19/33] target/openrisc: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:29 +1000 Message-Id: <20240129233043.34558-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 10 ++-------- target/openrisc/cpu.c | 13 +++++++++++++ 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index b454014ddd..7dbed8d8be 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -361,16 +361,10 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); } +int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) { - int ret = MMU_NOMMU_IDX; /* mmu is disabled */ - - if (env->sr & (ifetch ? SR_IME : SR_DME)) { - /* The mmu is enabled; test supervisor state. */ - ret = env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; - } - - return ret; + return openrisc_cpu_mmu_index(env_cpu(env), ifetch); } static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 477d49d4bc..8670152c84 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -68,6 +68,18 @@ static bool openrisc_cpu_has_work(CPUState *cs) CPU_INTERRUPT_TIMER); } +int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUOpenRISCState *env = cpu_env(cs); + + if (env->sr & (ifetch ? SR_IME : SR_DME)) { + /* The mmu is enabled; test supervisor state. */ + return env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; + } + + return MMU_NOMMU_IDX; /* mmu is disabled */ +} + static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) { info->print_insn = print_insn_or1k; @@ -239,6 +251,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = openrisc_cpu_class_by_name; cc->has_work = openrisc_cpu_has_work; + cc->mmu_index = openrisc_cpu_mmu_index; cc->dump_state = openrisc_cpu_dump_state; cc->set_pc = openrisc_cpu_set_pc; cc->get_pc = openrisc_cpu_get_pc; From patchwork Mon Jan 29 23:30:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767482 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1127338wro; Mon, 29 Jan 2024 15:37:37 -0800 (PST) X-Google-Smtp-Source: AGHT+IGVcuIHZ0xsVAPoHapyur1DxxN+yqZmWCjRYcO6+ID1PevKWYIxjQNeFFAembfuaO+BS/Ee X-Received: by 2002:a05:622a:150:b0:42a:84e0:baa8 with SMTP id v16-20020a05622a015000b0042a84e0baa8mr7459533qtw.6.1706571456907; Mon, 29 Jan 2024 15:37:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571456; cv=none; d=google.com; s=arc-20160816; b=UmafTVIfnTheQAdWp/bKIKDx2bbyuHOjlEU8E5GwZH5ey3fQzjsIOxeyAet1UEU6+p FIxJ2ZahoHx7KsUFL2zFC0kIcbWQcHWdhOAuFlGx4HKC8e3xAjtNxDl+6FbwkknxSeN+ u3mBHIACosj53VBH64OouJxPRM3WhE5F46D2YcTl3ztsq4B/AQjO2FASH6gBCRt5l849 BOvrfQguQhg1aJim71Y+8H+jAp26Q+imay+aU1+g0fkCPKZOt7weZdNTZOfZWrQuE/Kt akdtNQb+yoxA26Kc/dt7XThwUbWNqkblis06fI98hHx126dGC/Z7KGbqZtWfkHT29vMU uBJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rvOQFTMkY9QB65SS7g0QhXugn3UR4E0seouTHChD6V0=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=QKjQuiqDM0Q6wYzpri91PUvF6JfOT/E5ZgxVr1biR9UIvU9MniLfvyiQSHMOtslYNL 97A+qwD8E1xDPBVEbw6KXVQg/DX9HalkotUE/RVfagkNbkBGfhuXQF3tD6+PZIIjlVvq mHO14txy5pCcpt8DFWKY7xhh4PDpDN5eQb90HqD50vTw/XejXOPBJMlSCaNP9WFnlKD9 kQCY+lu45Bpm8UuH4h6v5ltkG1H3P1Dmjz+9AkfWTBTAhL7eelapnoG1XsGZr6uhJOhl DW/4jYfRBf+LXvM5ub0/Lnv9PccskslInFXRJLb5IYGI9Vd5XUQVaztTY3hLbpEOlSm/ 3l0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xcnb47P7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 20/33] target/ppc: Split out ppc_env_mmu_index Date: Tue, 30 Jan 2024 09:30:30 +1000 Message-Id: <20240129233043.34558-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 7 ++++++- target/ppc/cpu_init.c | 2 +- target/ppc/mem_helper.c | 10 +++++----- target/ppc/mmu_common.c | 4 ++-- 4 files changed, 14 insertions(+), 9 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f8101ffa29..5f4f52aec5 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1624,7 +1624,7 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val); /* MMU modes definitions */ #define MMU_USER_IDX 0 -static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) +static inline int ppc_env_mmu_index(CPUPPCState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return MMU_USER_IDX; @@ -1633,6 +1633,11 @@ static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) #endif } +static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) +{ + return ppc_env_mmu_index(env, ifetch); +} + /* Compatibility modes */ #if defined(TARGET_PPC64) bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 23eb5522b6..86c8031765 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7457,7 +7457,7 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " "%08x iidx %d didx %d\n", env->msr, env->spr[SPR_HID0], env->hflags, - cpu_mmu_index(env, true), cpu_mmu_index(env, false)); + ppc_env_mmu_index(env, true), ppc_env_mmu_index(env, false)); #if !defined(CONFIG_USER_ONLY) if (env->tb_env) { qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index c7535481d6..ea7e8443a8 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -83,7 +83,7 @@ static void *probe_contiguous(CPUPPCState *env, target_ulong addr, uint32_t nb, void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg) { uintptr_t raddr = GETPC(); - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = ppc_env_mmu_index(env, false); void *host = probe_contiguous(env, addr, (32 - reg) * 4, MMU_DATA_LOAD, mmu_idx, raddr); @@ -105,7 +105,7 @@ void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg) void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg) { uintptr_t raddr = GETPC(); - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = ppc_env_mmu_index(env, false); void *host = probe_contiguous(env, addr, (32 - reg) * 4, MMU_DATA_STORE, mmu_idx, raddr); @@ -135,7 +135,7 @@ static void do_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, return; } - mmu_idx = cpu_mmu_index(env, false); + mmu_idx = ppc_env_mmu_index(env, false); host = probe_contiguous(env, addr, nb, MMU_DATA_LOAD, mmu_idx, raddr); if (likely(host)) { @@ -224,7 +224,7 @@ void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb, return; } - mmu_idx = cpu_mmu_index(env, false); + mmu_idx = ppc_env_mmu_index(env, false); host = probe_contiguous(env, addr, nb, MMU_DATA_STORE, mmu_idx, raddr); if (likely(host)) { @@ -276,7 +276,7 @@ static void dcbz_common(CPUPPCState *env, target_ulong addr, target_ulong mask, dcbz_size = env->dcache_line_size; uint32_t i; void *haddr; - int mmu_idx = epid ? PPC_TLB_EPID_STORE : cpu_mmu_index(env, false); + int mmu_idx = epid ? PPC_TLB_EPID_STORE : ppc_env_mmu_index(env, false); #if defined(TARGET_PPC64) /* Check for dcbz vs dcbzl on 970 */ diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 6ca5d12207..751403f1c8 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -1561,9 +1561,9 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) * mapped by code TLBs, so we also try a MMU_INST_FETCH. */ if (ppc_xlate(cpu, addr, MMU_DATA_LOAD, &raddr, &s, &p, - cpu_mmu_index(&cpu->env, false), false) || + ppc_env_mmu_index(&cpu->env, false), false) || ppc_xlate(cpu, addr, MMU_INST_FETCH, &raddr, &s, &p, - cpu_mmu_index(&cpu->env, true), false)) { + ppc_env_mmu_index(&cpu->env, true), false)) { return raddr & TARGET_PAGE_MASK; } return -1; From patchwork Mon Jan 29 23:30:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767471 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1126537wro; Mon, 29 Jan 2024 15:35:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IHDEfwrI9Gj/6F2Bo3qdlTJMdiAKFb+KfDqnK/mOIrb4vO+sABfYSqPVka5iNb4FbKqc7rh X-Received: by 2002:a05:6214:f0e:b0:68c:5cc8:fbe7 with SMTP id gw14-20020a0562140f0e00b0068c5cc8fbe7mr873999qvb.55.1706571300364; Mon, 29 Jan 2024 15:35:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571300; cv=none; d=google.com; s=arc-20160816; b=rMloaMYu2ZhuOfwQ84CH0qC3LgDsGpPeizhKsIT6rsxfNp2reJipiz591QYI1/8Iyg vMbznbZEITAh8v5DRJB8wqsFDdDzpeMPHYHnZmSA33joKNTkK7II765P8VtN8DnhLS1T sddsLb/0Jdk5CMcBg1Vu6lJmUsmylvEpiP+xSK6yk20g76Cb57DEU6mzrqCKmf+gcxU7 oZ34edC6rdggkQELRbyAdyUPQMwwPJrM/hrz1ff1+JlH7dcTimFAzM4NJcCUmQl/LarK SZ3owtObge4dXNGimg2djQvqdnq5RG9bkAC8U0paGzdKA0A1hAVxeiisN0WITcxfMrXI Up6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=BdVwXO6aZnnqYTNIGGclZOCzzCuGYC0jnGIBlpxlAKQ=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=c8So6xGGj6tiVsunyatvl/Qi9kbE8mOyn2JZHf8kzldxMoFL2OTNhRA+slSA64x8sF cq1KYESBmFalFJ+Prmogro8bQ1znuWlhbAEZyMJ4erqLhvB6CrkS9ioUWanO38tlvT8b sAGfJM+q0h4YGMOvimzEcSzGKzXm+HM2bXi7eUeJIWDWmq5s4KeERBvRgb2CVWzrZllQ weD1OFH8J5g1KGs9V4HbZYVALQYMob7waTZ83KHf6z3PSPiZyYYO2euopJr43Uo8btZB C1pA6Cy4X1GhqGCULAolj9KplAkWJc9AuqYlBnjg7hlQDeZ1BS4fPp3EqfdYzHLXfV/X U5Jg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IjbDVnp+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 21/33] target/ppc: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:31 +1000 Message-Id: <20240129233043.34558-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/ppc/cpu_init.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 86c8031765..9931372a08 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7105,6 +7105,11 @@ static bool ppc_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } +static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return ppc_env_mmu_index(cpu_env(cs), ifetch); +} + static void ppc_cpu_reset_hold(Object *obj) { CPUState *s = CPU(obj); @@ -7372,6 +7377,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = ppc_cpu_class_by_name; cc->has_work = ppc_cpu_has_work; + cc->mmu_index = ppc_cpu_mmu_index; cc->dump_state = ppc_cpu_dump_state; cc->set_pc = ppc_cpu_set_pc; cc->get_pc = ppc_cpu_get_pc; From patchwork Mon Jan 29 23:30:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767468 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1126232wro; Mon, 29 Jan 2024 15:33:56 -0800 (PST) X-Google-Smtp-Source: AGHT+IFPf5BmJqtwnTewaOHF4TIidy0fRIbuK2bqsg/dF4ADNXjfOFSfPHkS6psxPbYOmEA4o4w9 X-Received: by 2002:a05:620a:1498:b0:783:dddf:2211 with SMTP id w24-20020a05620a149800b00783dddf2211mr5771611qkj.24.1706571235870; Mon, 29 Jan 2024 15:33:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571235; cv=none; d=google.com; s=arc-20160816; b=Ml48dYIOBYzh2rNAGhtldOfdtld7w/dR5JvL5/+dAcch4SkHRW7ugucq2k6Wd0Mxnv AWsxbgpKXA6rlqt0wPHQt61W4wK7XqxKV7QxpnohXwH4lZ9vvp6T1xt507BKeQeoVUX6 ZVzOXHm6gj20RscxO/ymUT3rgDJpzqMgT0bHPC6l8opFZ8Qk7vG4RX4phIPK3LClZM5Z EAd37yqTPGzf0EkvRFrf/yWLsZX5h4uzMmWAhDVgOPkD3hEPvM76/DQpcFDzK4eEgbQD 18JvSpUvx9BNWvapn9z0YX3K09Ip8DxjSvXePK2s1Q97wRBRsy6GE3Unfx1CLjtKKGik PpCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=w0VyFnxuloTGEbgz18a76FD3rClrdXq5QXu0ykcKSCs=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=yi/1qrRmk5MMpllhqpM9dxHRzgofBpbjbrTjLpBhdMsJBrl7SIXSwsYu0b1fLwItm9 4ZnlGr4kAxfrPGKNYbS9Kbbr9e9JHSIjy83ZIwd66NFd8xZZaGBe4VRhCuoVVlXSJoIH 8jg37xZvwpakItevs25mbmFgJ3zqylZgKquBi3PSAJNPFdY/Lb3iQ6XUdwMA89iIzS9m 6mbIJN8Ytvx/T85KIpIWoIUf0SpXWZUXmk5aVfvWANDdyTgeO6YtURy0n0/BHC4Nr1Wk tguF/O9bwsZy5PzUL+j2DqsHid6DzVdnjoeOUvHxnVS4wXfkIp1uHiuitHkU1FRBctmS /A/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dDu5Fzmg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 22/33] target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_index Date: Tue, 30 Jan 2024 09:30:32 +1000 Message-Id: <20240129233043.34558-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Free up the riscv_cpu_mmu_index name for other usage; emphasize that the argument is 'env'. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 4 ++-- target/riscv/cpu_helper.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5f3955c38d..9c825c7b51 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -498,7 +498,7 @@ target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); -int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); +int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); @@ -507,7 +507,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); -#define cpu_mmu_index riscv_cpu_mmu_index +#define cpu_mmu_index riscv_env_mmu_index #ifndef CONFIG_USER_ONLY void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c7cc7eb423..15f87ecdb0 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -33,7 +33,7 @@ #include "debug.h" #include "tcg/oversized-guest.h" -int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) +int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return 0; From patchwork Mon Jan 29 23:30:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767483 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1127355wro; Mon, 29 Jan 2024 15:37:39 -0800 (PST) X-Google-Smtp-Source: AGHT+IF1P5Iv6X73oRvPWDy7ubmEYE2KiL9MMGZRWjxu9tVn198M1ndLarkELNiguLMw9c6WOGOP X-Received: by 2002:a05:620a:127a:b0:783:f79f:6e5 with SMTP id b26-20020a05620a127a00b00783f79f06e5mr3424313qkl.70.1706571459562; Mon, 29 Jan 2024 15:37:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571459; cv=none; d=google.com; s=arc-20160816; b=ul9iUkSRlRUH633qDGXSWsoq3W1kKcwOWSkLJhq7cVNWa1YowI9kw8MqBeBLOUbCpq B7FYvhYF6mRb/l5ksPbAJnGPHTMEpVHd0UN7W4EH9iILUW1omrOLsbqARV4ryxLT9gaF MT1ntsXBZp7AC2qPY8mTjnmRnmnuNr2BoHuwLWc95Wo6CeNyuZKD9xv172Tt+UHM+IFe PyWnzaMog8jODDd/alnsJV0ydAUtSIN6NPJ9dzMcWXD4T9v0HX+o7+KGMC+g91mjQ/RT 8PGJDCUVekLj9NRDPWMsbjsJk73hMiuloN+NMwvE5U2keWQ7nZTKN7iK5bLh89Q7J9ee xMNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=T1A5JMP4c4pUqbkuAUmVb/gWlj2brd508NIa6msXbG4=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=0/nMIHtDzCNlouFYuWRyJhVWk/cd/SDBDzTuocwY6FJKh9Du6zfbr2fIK9gDNDMMfL hJscAIPNUxZidnbaK/9TuxyEG32NZfI+yOlhTEcL6qI49EiYttSWGRoV2RMsABCA0Ram Pcx+TvbXDAttj3hbQRQ8B2EHD9AjDGcDjrg7cNV8lDPXTxwNmhDH1bR7rtZeL58CPqVO ImomzXZ4KyMWHvhR3F71aVh/YKCTk4ZpMTQeFJKoEzR+K9eZNjrnG/0VQ2V5qxqV6LG9 E+g2eH0nMEo2EnBPiTo1uv94t0uUGaFGlMANG4OghBxoC9FMFebhKg4AumAO088Uw22/ +5zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MGzoZ4ep; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 23/33] target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index Date: Tue, 30 Jan 2024 09:30:33 +1000 Message-Id: <20240129233043.34558-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use the target-specific function name in preference to the generic name. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 4 ++-- target/riscv/op_helper.c | 4 ++-- target/riscv/vector_helper.c | 9 +++++---- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 15f87ecdb0..b6b23b7d03 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -106,7 +106,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, #else flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); - flags |= cpu_mmu_index(env, 0); + flags |= riscv_env_mmu_index(env, 0); fs = get_field(env->mstatus, MSTATUS_FS); vs = get_field(env->mstatus, MSTATUS_VS); @@ -1200,7 +1200,7 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) CPURISCVState *env = &cpu->env; hwaddr phys_addr; int prot; - int mmu_idx = cpu_mmu_index(&cpu->env, false); + int mmu_idx = riscv_env_mmu_index(&cpu->env, false); if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, true, env->virt_enabled, true)) { diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 5355225d56..f414aaebdb 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -157,7 +157,7 @@ void helper_cbo_zero(CPURISCVState *env, target_ulong address) { RISCVCPU *cpu = env_archcpu(env); uint16_t cbozlen = cpu->cfg.cboz_blocksize; - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = riscv_env_mmu_index(env, false); uintptr_t ra = GETPC(); void *mem; @@ -205,7 +205,7 @@ static void check_zicbom_access(CPURISCVState *env, uintptr_t ra) { RISCVCPU *cpu = env_archcpu(env); - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = riscv_env_mmu_index(env, false); uint16_t cbomlen = cpu->cfg.cbom_blocksize; void *phost; int ret; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index c1c3a4d1ea..fe0d5d053c 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -113,14 +113,15 @@ static void probe_pages(CPURISCVState *env, target_ulong addr, { target_ulong pagelen = -(addr | TARGET_PAGE_MASK); target_ulong curlen = MIN(pagelen, len); + int mmu_index = riscv_env_mmu_index(env, false); probe_access(env, adjust_addr(env, addr), curlen, access_type, - cpu_mmu_index(env, false), ra); + mmu_index, ra); if (len > curlen) { addr += curlen; curlen = len - curlen; probe_access(env, adjust_addr(env, addr), curlen, access_type, - cpu_mmu_index(env, false), ra); + mmu_index, ra); } } @@ -464,6 +465,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, uint32_t esz = 1 << log2_esz; uint32_t vma = vext_vma(desc); target_ulong addr, offset, remain; + int mmu_index = riscv_env_mmu_index(env, false); /* probe every access */ for (i = env->vstart; i < env->vl; i++) { @@ -478,8 +480,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, remain = nf << log2_esz; while (remain > 0) { offset = -(addr | TARGET_PAGE_MASK); - host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)); + host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_index); if (host) { #ifdef CONFIG_USER_ONLY if (!page_check_range(addr, offset, PAGE_READ)) { From patchwork Mon Jan 29 23:30:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767475 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1126735wro; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 24/33] target/riscv: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:34 +1000 Message-Id: <20240129233043.34558-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8cbfc7e781..be21fa09c6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -867,6 +867,11 @@ static bool riscv_cpu_has_work(CPUState *cs) #endif } +static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return riscv_env_mmu_index(cpu_env(cs), ifetch); +} + static void riscv_cpu_reset_hold(Object *obj) { #ifndef CONFIG_USER_ONLY @@ -1810,6 +1815,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) cc->class_by_name = riscv_cpu_class_by_name; cc->has_work = riscv_cpu_has_work; + cc->mmu_index = riscv_cpu_mmu_index; cc->dump_state = riscv_cpu_dump_state; cc->set_pc = riscv_cpu_set_pc; cc->get_pc = riscv_cpu_get_pc; From patchwork Mon Jan 29 23:30:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767488 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1127914wro; Mon, 29 Jan 2024 15:39:42 -0800 (PST) X-Google-Smtp-Source: AGHT+IFtWi1/Yla6GRQ1ecRt6oS03caPBKTeO9ibRowLTsm+9cpA9EU3mE1tIZuu+PWoQT6zRl9S X-Received: by 2002:a05:622a:94:b0:42a:a828:f276 with SMTP id o20-20020a05622a009400b0042aa828f276mr3068758qtw.29.1706571582618; Mon, 29 Jan 2024 15:39:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571582; cv=none; d=google.com; s=arc-20160816; b=eL1uCTtOZnZTnNLQqL6H0YWT14Yyp37IMSjXVhOJ/7REnxU3X7CGJL3t3jgHR2YJ3f SjxG5ePfR7ZX9l8EGTzAjsaxqkJAG/oeXngMiDiRvLMg4T1qOKXbB+pOOCCTZj7zSm38 3fgv/M+ecWEKmb1KZe7osq6WBnIO23qmgJWOxVYDnnNeu9IO1vQHuZJGJ6+vVwK4h4cY U+GJueIyb0vDeQ0/khU85MvHmCscwaAKP50XVCW8CFtWZHFIwZHYqhbfVBVEfz6amPKB m6YdOxmx+VGRKkbryj2UCDRnNQDFf5K/mRe0DG5rcl1RNDMwuyH1FHGsBzHp7p379h2u SqUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7ZadEiersJPkOM/pXyufttHg+GMQ5Zo4Kp1sJsHlj50=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=VBowvB0ZlWrzRWPMJqbhJMPaRseD+wHdLsl8cLHzltKEt5kHBUCqzfCE0bD0aokWy7 dAmVuUCIuS1SXpEboba2dcKS6rRN4o9kxYDqwxWFMGOqym6pi9TFvIVUy1Lvp71E+jAv U8mQJiE070XRzoqdnWEwBrt6Ucg93eR0cLvZoj3lJPL94Ge3A50cGn4ScvEZEhjnDTVc WRY+xtPWkw+qApB/OKxiqb3Y0vTT3IlmS+X3wkmgPbHvINa2qIAnxdGwUvXyKRqymFde DRpU9mLiNTvhyBDgGNA74kve4KRiPZs0YsaaCJpbEHvz/iFSo16wuQYLZVHs3HzDR4j4 Fxzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lqixDMYr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 25/33] target/rx: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:35 +1000 Message-Id: <20240129233043.34558-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/rx/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 353132dac2..5205167da1 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -64,6 +64,11 @@ static bool rx_cpu_has_work(CPUState *cs) (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); } +static int riscv_cpu_mmu_index(CPUState *cs, bool ifunc) +{ + return 0; +} + static void rx_cpu_reset_hold(Object *obj) { RXCPU *cpu = RX_CPU(obj); @@ -204,6 +209,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data) cc->class_by_name = rx_cpu_class_by_name; cc->has_work = rx_cpu_has_work; + cc->mmu_index = riscv_cpu_mmu_index; cc->dump_state = rx_cpu_dump_state; cc->set_pc = rx_cpu_set_pc; cc->get_pc = rx_cpu_get_pc; From patchwork Mon Jan 29 23:30:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767476 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1126938wro; Mon, 29 Jan 2024 15:36:19 -0800 (PST) X-Google-Smtp-Source: AGHT+IEt8PjXbrvGlCNLMAXTc9YL+ZmqGIebxk7dXB73eq7EsuwXwdifbiLzPrLVSlfxZauwDQhj X-Received: by 2002:a0c:dc06:0:b0:68c:3ee9:ed0a with SMTP id s6-20020a0cdc06000000b0068c3ee9ed0amr5006275qvk.12.1706571379655; Mon, 29 Jan 2024 15:36:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571379; cv=none; d=google.com; s=arc-20160816; b=yGzEukayYHTaW60ouud5VG+33/th8lBuq1QtbkFNtVhtX9XTFgX1LOhEDbvf55qx9M BbP5jUSGNc2eqH5A08P0U+8rDIxBHfOrF9bY+PYFvdWZjoU0oUwv/p9/Nkl8k8qe59ue ZLCa14MZdPbkqjz6wPGxdSQ/6QFSJE/AuOZRxMCRGLiSJ02T92+Xyyp7jf5ETigImLdY SmRCrC3hzqpDGdPBaFacutOI3Z41PUglcmxOiFATlA45WcFTbCzFIczb8lKQIgHmjEtU J5QzyWBa+glnoIEIhNY5k+mxLpqIZRIhAoF6kpHoYtr2iwH0x+jP4QAM2glTx4+YcpQM qXgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jR/oo/A0As45gwF9os4Db/TKdBueduPDROlzWdMxfpg=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=Jf+mMNPGoTyYt9nTCYghayjPiseWl/velcp03xFDOVTSXweBThR6YSyyzQb2UURUt+ xaNRpxALUl+28jk2xEUNcod36UiGMH0iEDZuKDRCEfvHhLws4UolmAP8tPOaQ7YNBgIA Ayc3l/toj7HMke9jbvPYNwRqyOSGMC5SaRg8VRpPPqZpIKrhxxP3LjZzm46LyGeDarPl wDhz1r2gI7qK2dOAm7g5gxabfF8uXYp+8VgjddII3E0FI6JB9irJWhv961msf9aXwrv+ OcwCO8u6JpharCv3NNX2fRAjyMV0/Tn19KmoQuFa5PQDerX2o9+lJDu9ny0ysWZlBhrF vL5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OuHfqSDQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 26/33] target/s390x: Split out s390x_env_mmu_index Date: Tue, 30 Jan 2024 09:30:36 +1000 Message-Id: <20240129233043.34558-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/s390x/cpu.h | 4 +++- target/s390x/tcg/mem_helper.c | 34 ++++++++++++++++++---------------- 2 files changed, 21 insertions(+), 17 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index fa3aac4f97..f0fed5d6ad 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -381,7 +381,7 @@ extern const VMStateDescription vmstate_s390_cpu; #define MMU_HOME_IDX 2 #define MMU_REAL_IDX 3 -static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) +static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return MMU_USER_IDX; @@ -412,6 +412,8 @@ static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) #endif } +#define cpu_mmu_index s390x_env_mmu_index + #ifdef CONFIG_TCG #include "tcg/tcg_s390x.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 84103251b9..557831def4 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -358,7 +358,7 @@ static int mmu_idx_from_as(uint8_t as) static uint32_t do_helper_nc(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src, uintptr_t ra) { - const int mmu_idx = cpu_mmu_index(env, false); + const int mmu_idx = s390x_env_mmu_index(env, false); S390Access srca1, srca2, desta; uint32_t i; uint8_t c = 0; @@ -392,7 +392,7 @@ uint32_t HELPER(nc)(CPUS390XState *env, uint32_t l, uint64_t dest, static uint32_t do_helper_xc(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src, uintptr_t ra) { - const int mmu_idx = cpu_mmu_index(env, false); + const int mmu_idx = s390x_env_mmu_index(env, false); S390Access srca1, srca2, desta; uint32_t i; uint8_t c = 0; @@ -433,7 +433,7 @@ uint32_t HELPER(xc)(CPUS390XState *env, uint32_t l, uint64_t dest, static uint32_t do_helper_oc(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src, uintptr_t ra) { - const int mmu_idx = cpu_mmu_index(env, false); + const int mmu_idx = s390x_env_mmu_index(env, false); S390Access srca1, srca2, desta; uint32_t i; uint8_t c = 0; @@ -467,7 +467,7 @@ uint32_t HELPER(oc)(CPUS390XState *env, uint32_t l, uint64_t dest, static uint32_t do_helper_mvc(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src, uintptr_t ra) { - const int mmu_idx = cpu_mmu_index(env, false); + const int mmu_idx = s390x_env_mmu_index(env, false); S390Access srca, desta; uint32_t i; @@ -508,7 +508,7 @@ void HELPER(mvc)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src) /* move right to left */ void HELPER(mvcrl)(CPUS390XState *env, uint64_t l, uint64_t dest, uint64_t src) { - const int mmu_idx = cpu_mmu_index(env, false); + const int mmu_idx = s390x_env_mmu_index(env, false); const uint64_t ra = GETPC(); S390Access srca, desta; int32_t i; @@ -529,7 +529,7 @@ void HELPER(mvcrl)(CPUS390XState *env, uint64_t l, uint64_t dest, uint64_t src) /* move inverse */ void HELPER(mvcin)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src) { - const int mmu_idx = cpu_mmu_index(env, false); + const int mmu_idx = s390x_env_mmu_index(env, false); S390Access srca, desta; uintptr_t ra = GETPC(); int i; @@ -550,7 +550,7 @@ void HELPER(mvcin)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src) /* move numerics */ void HELPER(mvn)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src) { - const int mmu_idx = cpu_mmu_index(env, false); + const int mmu_idx = s390x_env_mmu_index(env, false); S390Access srca1, srca2, desta; uintptr_t ra = GETPC(); int i; @@ -572,7 +572,7 @@ void HELPER(mvn)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src) /* move with offset */ void HELPER(mvo)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src) { - const int mmu_idx = cpu_mmu_index(env, false); + const int mmu_idx = s390x_env_mmu_index(env, false); /* MVO always processes one more byte than specified - maximum is 16 */ const int len_dest = (l >> 4) + 1; const int len_src = (l & 0xf) + 1; @@ -606,7 +606,7 @@ void HELPER(mvo)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src) /* move zones */ void HELPER(mvz)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src) { - const int mmu_idx = cpu_mmu_index(env, false); + const int mmu_idx = s390x_env_mmu_index(env, false); S390Access srca1, srca2, desta; uintptr_t ra = GETPC(); int i; @@ -669,7 +669,7 @@ uint32_t HELPER(clm)(CPUS390XState *env, uint32_t r1, uint32_t mask, if (!mask) { /* Recognize access exceptions for the first byte */ - probe_read(env, addr, 1, cpu_mmu_index(env, false), ra); + probe_read(env, addr, 1, s390x_env_mmu_index(env, false), ra); } while (mask) { @@ -893,7 +893,7 @@ uint32_t HELPER(mvpg)(CPUS390XState *env, uint64_t r0, uint32_t r1, uint32_t r2) { const uint64_t src = get_address(env, r2) & TARGET_PAGE_MASK; const uint64_t dst = get_address(env, r1) & TARGET_PAGE_MASK; - const int mmu_idx = cpu_mmu_index(env, false); + const int mmu_idx = s390x_env_mmu_index(env, false); const bool f = extract64(r0, 11, 1); const bool s = extract64(r0, 10, 1); const bool cco = extract64(r0, 8, 1); @@ -946,7 +946,7 @@ inject_exc: /* string copy */ uint32_t HELPER(mvst)(CPUS390XState *env, uint32_t r1, uint32_t r2) { - const int mmu_idx = cpu_mmu_index(env, false); + const int mmu_idx = s390x_env_mmu_index(env, false); const uint64_t d = get_address(env, r1); const uint64_t s = get_address(env, r2); const uint8_t c = env->regs[0]; @@ -1027,7 +1027,7 @@ static inline uint32_t do_mvcl(CPUS390XState *env, uint64_t *src, uint64_t *srclen, uint16_t pad, int wordsize, uintptr_t ra) { - const int mmu_idx = cpu_mmu_index(env, false); + const int mmu_idx = s390x_env_mmu_index(env, false); int len = MIN(*destlen, -(*dest | TARGET_PAGE_MASK)); S390Access srca, desta; int i, cc; @@ -1084,7 +1084,7 @@ static inline uint32_t do_mvcl(CPUS390XState *env, /* move long */ uint32_t HELPER(mvcl)(CPUS390XState *env, uint32_t r1, uint32_t r2) { - const int mmu_idx = cpu_mmu_index(env, false); + const int mmu_idx = s390x_env_mmu_index(env, false); uintptr_t ra = GETPC(); uint64_t destlen = env->regs[r1 + 1] & 0xffffff; uint64_t dest = get_address(env, r1); @@ -1742,7 +1742,7 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r1, uint32_t r2, static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2, bool parallel) { - uint32_t mem_idx = cpu_mmu_index(env, false); + uint32_t mem_idx = s390x_env_mmu_index(env, false); MemOpIdx oi16 = make_memop_idx(MO_TE | MO_128, mem_idx); MemOpIdx oi8 = make_memop_idx(MO_TE | MO_64, mem_idx); MemOpIdx oi4 = make_memop_idx(MO_TE | MO_32, mem_idx); @@ -2867,12 +2867,14 @@ uint32_t HELPER(cu42)(CPUS390XState *env, uint32_t r1, uint32_t r2, uint32_t m3) void probe_write_access(CPUS390XState *env, uint64_t addr, uint64_t len, uintptr_t ra) { + const int mmu_idx = s390x_env_mmu_index(env, false); + /* test the actual access, not just any access to the page due to LAP */ while (len) { const uint64_t pagelen = -(addr | TARGET_PAGE_MASK); const uint64_t curlen = MIN(pagelen, len); - probe_write(env, addr, curlen, cpu_mmu_index(env, false), ra); + probe_write(env, addr, curlen, mmu_idx, ra); addr = wrap_address(env, addr + curlen); len -= curlen; } From patchwork Mon Jan 29 23:30:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767472 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1126661wro; Mon, 29 Jan 2024 15:35:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IHZG4FALJWW1S6RTjy8pU0WrptV+rA0DSU7IGG2zhejz1gWTU2TvbVaEjVbxJX4+Sygq+js X-Received: by 2002:a25:c744:0:b0:dc2:2a7a:721f with SMTP id w65-20020a25c744000000b00dc22a7a721fmr3368123ybe.76.1706571324191; Mon, 29 Jan 2024 15:35:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571324; cv=none; d=google.com; s=arc-20160816; b=myd+NCYYexeZMjTE8kECpoub/v8mDAck8YgbCZfTAovMLiBk/Cwklu0o3gGw8J/B1b mk2aB5QKWyoho4UhbjvpxlLE0TRV+F0bsanpsQo3F9jeaNXN4j44Y/AzKWXwAV0N0rxJ f9TnFFH/Pv3Ime3KDpgbvjzQiYaewPipC1prbPXYLuSOz2mUT3QgSBfUI9dvfNlGbKyI wqPB9A4mFF97O36BMMEriVYzREzYLSw/8RRoSGqKR6UHzEv52nRbqJNtEXguN6Y3eFKg NdoD83RU1hnBte92iQacBT62McMKjTSIkQLmrqfXrUgda/H3T3m/C9SRJ4NSu5TbgARI cAVw== ARC-Message-Signature: i=1; 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 27/33] target/s390x: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:37 +1000 Message-Id: <20240129233043.34558-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/s390x/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7f123863dc..49a2341acc 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -142,6 +142,11 @@ static bool s390_cpu_has_work(CPUState *cs) return s390_cpu_has_int(cpu); } +static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return s390x_env_mmu_index(cpu_env(cs), ifetch); +} + static void s390_query_cpu_fast(CPUState *cpu, CpuInfoFast *value) { S390CPU *s390_cpu = S390_CPU(cpu); @@ -352,6 +357,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) scc->reset = s390_cpu_reset; cc->class_by_name = s390_cpu_class_by_name, cc->has_work = s390_cpu_has_work; + cc->mmu_index = s390x_cpu_mmu_index; cc->dump_state = s390_cpu_dump_state; cc->query_cpu_fast = s390_query_cpu_fast; cc->set_pc = s390_cpu_set_pc; From patchwork Mon Jan 29 23:30:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767486 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1127796wro; Mon, 29 Jan 2024 15:39:14 -0800 (PST) X-Google-Smtp-Source: AGHT+IGP6yMNTFfnl16wnhOAauCh4HkjxIC1gjulOi5WYjKIeTqPycVnG/O60gSO74+ty6HlWJbZ X-Received: by 2002:a05:6214:20ac:b0:68c:5cc4:a4e0 with SMTP id 12-20020a05621420ac00b0068c5cc4a4e0mr770388qvd.73.1706571554366; Mon, 29 Jan 2024 15:39:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571554; cv=none; d=google.com; s=arc-20160816; b=uFzLBJkPSe+Ix49kVLnsSrODSm39q9xq0PGQlCWPbzh4ZQmh47EoD4YIR0nEEE60+e x0Fp4fIAV7CbRQvVc2izpNTcn8nUtXVn6/rmWfugkUphpv9iAkp5VQE7e4He3gf3fsm0 MzlFbDg0NSHWjSoyhUlrJIOsMm1g3lvclEPq37wKhBi4AoLR6nh1c0Uljul5iBvFvvj8 Zrk/0r5foVLWYRd8l6hmK1ZzbTAcMFn+oRMlK6N2Y8SboaNyC6ltNuRcmk3fe+zmM42+ dz+rqb9JslzD6+B1SVUHaDo+GjktG6gkL60dj3C7f2R5Lpp0OKcMk+OQusDs6Kw0X/QK dxZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=pNNENKH/HQj+hw6JTH28lUCmFQmGh5or2lvTAvTEZkw=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=P34oSAm4+OjhL/2f6PKfASlFbP+dnCq3ildCwhP9LsUvWVZhN59j3mJcYyuMXbTnG4 mlLJwu8xbNJr61n096HgACrciW3NBk8S8q/+kzK+ZjmLUeYA8M7xGyjbbdd7TazHwdKJ Nvdy1UDnm1D1ssf+krzE829TwP68i0UZAb8ySxVftxrbUvIFc73Ku+90TeUm5UbYHwsU wwgqK3f5XGPsYK6pDEuYyweb7CGU6mR+9N8ONJJSmySTCo31YXAftbSSCijk4ig65YkN LME8CAMnllJaoycubAyjjI2dcPZrXOSoHpEVopPwggMGHy05+UttyPV2tEKDdDLmk9v6 4PMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T2Uavm53; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 28/33] target/sh4: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:38 +1000 Message-Id: <20240129233043.34558-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 16 ++++++---------- target/sh4/cpu.c | 16 ++++++++++++++++ 2 files changed, 22 insertions(+), 10 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 0e6fa65bae..9c5e2b349e 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -273,16 +273,6 @@ void cpu_load_tlb(CPUSH4State * env); /* MMU modes definitions */ #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch) -{ - /* The instruction in a RTE delay slot is fetched in privileged - mode, but executed in user mode. */ - if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) { - return 0; - } else { - return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0; - } -} #include "exec/cpu-all.h" @@ -380,6 +370,12 @@ static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr) env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); } +int sh4_cpu_mmu_index(CPUState *cs, bool ifetch); +static inline int cpu_mmu_index(CPUSH4State *env, bool ifetch) +{ + return sh4_cpu_mmu_index(env_cpu(env), ifetch); +} + static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 39772955b5..6fead5655f 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -89,6 +89,21 @@ static bool superh_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } +int sh4_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUSH4State *env = cpu_env(cs); + + /* + * The instruction in a RTE delay slot is fetched in privileged mode, + * but executed in user mode. + */ + if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) { + return 0; + } else { + return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0; + } +} + static void superh_cpu_reset_hold(Object *obj) { CPUState *s = CPU(obj); @@ -266,6 +281,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = superh_cpu_class_by_name; cc->has_work = superh_cpu_has_work; + cc->mmu_index = sh4_cpu_mmu_index; cc->dump_state = superh_cpu_dump_state; cc->set_pc = superh_cpu_set_pc; cc->get_pc = superh_cpu_get_pc; From patchwork Mon Jan 29 23:30:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767467 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1126081wro; Mon, 29 Jan 2024 15:33:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IH8gZLWlqxh53YJPYcx7RbB4fCgXUm/nPau0nN6tqZvDShq9JJ1+ao2UPpD4kUcgf2ifK9s X-Received: by 2002:a0c:df05:0:b0:68c:476a:a5a5 with SMTP id g5-20020a0cdf05000000b0068c476aa5a5mr92438qvl.12.1706571204957; Mon, 29 Jan 2024 15:33:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571204; cv=none; d=google.com; s=arc-20160816; b=FmejdR0eQhaZXBeutEalffZYZRjkJghMhUqsl5ad4Qylyc6rnDNl3PyOIdo+pRrAM6 BBtmFXxQKQV3Ga+W7zFRDLimJX6ALRMx/vuLmU6JR0uqMXCTYOcum1OcLbgyc5TbmtsJ VGIpcxPfV924wjB+Qsc/76CaU4p4mUABIsvWyyN47usOO+8YNI4A6dWDESYcqU/Zpc+H eg7KTkGlAKTlzSZDO2IF1hcNvC2azk4ZgxPEFDJjt0A7vPUOp7XKhqRJbQO7m00NJBpP TGUsQbeJaS6ZgOTzy6/5Ll7hISKolDUOhU/538lwpqW5qNkc1cBPbH13+mIup3sNU0WM 9UnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OUpbcCo1Gwdi5RtgiHT0o/+TLFpXSWoQp1ADmvaIAeE=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=zOuQejB4JhnMArZh2FYQWDGynU6GgBivCuIaUU7pKGlXuRPS/zRhdrfksR/2uCn4Ec mDGSWqwjMl3r4NL/u0DFeba/9Bda30jdfG07K3DimaG+nwio04P5RHT4PN802B5NDFL4 p6IEcID3eFwPlwTZgOnfD4DK2LcjPDIA2m6PIBo9oNNwIkKXvL/SY339eJoisRmnrAbf FEdw3bKMURKKb5MAEeSDAEfS8QlDb9MfZBT7m1h3j8Jl5RfQKfbsVV8NT7gUng+nLyAp Caq5TWnkHJJ2KnJUiGsSV6j64ln78YGEADF1W+lUyRvmLUptY7i/93G+N8tB40jTeVom +W9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eRr3aR97; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 29/33] target/sparc: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:39 +1000 Message-Id: <20240129233043.34558-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 34 ++++++---------------------------- target/sparc/cpu.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 28 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 12a11ecb26..92c58c92c1 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -708,34 +708,6 @@ static inline int cpu_supervisor_mode(CPUSPARCState *env1) } #endif -static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) -{ -#if defined(CONFIG_USER_ONLY) - return MMU_USER_IDX; -#elif !defined(TARGET_SPARC64) - if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ - return MMU_PHYS_IDX; - } else { - return env->psrs; - } -#else - /* IMMU or DMMU disabled. */ - if (ifetch - ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0 - : (env->lsu & DMMU_E) == 0) { - return MMU_PHYS_IDX; - } else if (cpu_hypervisor_mode(env)) { - return MMU_PHYS_IDX; - } else if (env->tl > 0) { - return MMU_NUCLEUS_IDX; - } else if (cpu_supervisor_mode(env)) { - return MMU_KERNEL_IDX; - } else { - return MMU_USER_IDX; - } -#endif -} - static inline int cpu_interrupts_enabled(CPUSPARCState *env1) { #if !defined (TARGET_SPARC64) @@ -777,6 +749,12 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_HYPER (1 << 7) #define TB_FLAG_ASI_SHIFT 24 +int sparc_cpu_mmu_index(CPUState *cs, bool ifetch); +static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) +{ + return sparc_cpu_mmu_index(env_cpu(env), ifetch); +} + static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags) { diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 7d0d629a3d..7a3b815737 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -718,6 +718,34 @@ static bool sparc_cpu_has_work(CPUState *cs) cpu_interrupts_enabled(env); } +int sparc_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUSPARCState *env = cpu_env(cs); + +#ifndef TARGET_SPARC64 + if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ + return MMU_PHYS_IDX; + } else { + return env->psrs; + } +#else + /* IMMU or DMMU disabled. */ + if (ifetch + ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0 + : (env->lsu & DMMU_E) == 0) { + return MMU_PHYS_IDX; + } else if (cpu_hypervisor_mode(env)) { + return MMU_PHYS_IDX; + } else if (env->tl > 0) { + return MMU_NUCLEUS_IDX; + } else if (cpu_supervisor_mode(env)) { + return MMU_KERNEL_IDX; + } else { + return MMU_USER_IDX; + } +#endif +} + static char *sparc_cpu_type_name(const char *cpu_model) { char *name = g_strdup_printf(SPARC_CPU_TYPE_NAME("%s"), cpu_model); @@ -906,6 +934,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = sparc_cpu_class_by_name; cc->parse_features = sparc_cpu_parse_features; cc->has_work = sparc_cpu_has_work; + cc->mmu_index = sparc_cpu_mmu_index; cc->dump_state = sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) cc->memory_rw_debug = sparc_cpu_memory_rw_debug; From patchwork Mon Jan 29 23:30:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767484 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1127394wro; Mon, 29 Jan 2024 15:37:45 -0800 (PST) X-Google-Smtp-Source: AGHT+IHax17qah7iHy27rybkGpNqf7/EV8IlLIhYqE5FPKU0lv7iXUoANeyLZwv9+ATXrFk8lsD9 X-Received: by 2002:a05:690c:c8a:b0:5fb:c044:f087 with SMTP id cm10-20020a05690c0c8a00b005fbc044f087mr4858790ywb.35.1706571464773; Mon, 29 Jan 2024 15:37:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571464; cv=none; d=google.com; s=arc-20160816; b=dHhvZTWO+O7b8s8ZFxxmDczCiML7rDsGORNiaTgEKVjNtMmrqfxc71fNKfkB9gur0B 1vmFh2uAMJUP0RYbphA1XYBFQwhvMJLZQiWxjNSf6q9qR38upfSKAtyQoS04qsxUmOtM 1i5epN4b+ycRccFhXIKc0tc14FOASklLTtME1HqhtwXjiffIG5PVn0evXSBgRlwvTk4+ SnoKZ50Sblr9q9aXISfvA/a2H1mZ9+D+EVN8G3zqm58RrxBpH7wA9NNr2SEkctnoO273 zuZdz+/A+OyPY997ulc4oDmVXmS2SmTHx+En41w/3bUkJmG6AVjwRmwz7rV9pWMGPNoT 9dAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Q1GkbX/2RhRtI6NxAEXwoMhTS8WkrOI/cziGDkYfcrg=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=nt5ZL4ZOIBx/uKT3JbCCxfI0LTc2qxXdgae760+THLot0/9riCYs9g/MSY5QA9wl9P g6BzEBj8LiKyKL966Raq0pgnYUI6AGyDfG1hy50zLMny2xl0bAcU0uktHV6pMU3okUCZ Ke2ZyfRG8jKXVFvl7mZwFL732ZLD7DmSaQeGG+Ex21yUGeLe2gstHy6g0F1sFbw/rYqw Bl9I1QspTPUQASJSPqoZaHYtud1HNbnJhvEg/IP2WzjddJxbux28UIvGy7O7brgd/DBx t9Gz4Iw6gc09PZCsm0OZ9nreYYysCQQYCNHbDGxbQwUOHBW4WMgPzGedermFyWig23OP x2OA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vZJ3YOQQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 30/33] target/tricore: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:40 +1000 Message-Id: <20240129233043.34558-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Bastian Koppelmann --- target/tricore/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index e6d91c74b5..74e8a22b86 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -89,6 +89,11 @@ static bool tricore_cpu_has_work(CPUState *cs) return true; } +static int tricore_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return 0; +} + static void tricore_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -194,6 +199,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data) &mcc->parent_phases); cc->class_by_name = tricore_cpu_class_by_name; cc->has_work = tricore_cpu_has_work; + cc->mmu_index = tricore_cpu_mmu_index; cc->gdb_read_register = tricore_cpu_gdb_read_register; cc->gdb_write_register = tricore_cpu_gdb_write_register; From patchwork Mon Jan 29 23:30:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767474 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1126709wro; Mon, 29 Jan 2024 15:35:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IHS8Idcd9l8WHrcsrSrlQlMZ8w3BizBLy7fC7bXSqSkRqhrJhpUsM5jfgsm0hNHdrH3Qoks X-Received: by 2002:a05:620a:2945:b0:784:4c6:6db1 with SMTP id n5-20020a05620a294500b0078404c66db1mr1579225qkp.21.1706571332384; Mon, 29 Jan 2024 15:35:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571332; cv=none; d=google.com; s=arc-20160816; b=tpP/E6e/0+5UIBbAFVZRGENvj4CMVK8AtWyBRN96Ps/uoqhXuL/ZoS+s6GbyQS4CFB 5/iFW4g0X6Jev9lS1fsYyAW0XJeCDfn+wsCLAQ00+TotvxTz/8rgwwEXSSV9SMpfm/Of 2d10YY8Fmr775QjKwvWFSoXU3YsPrjJDAgiJdvy94cgXi36UBH0lCTv7aruztxZgfXHi R4dnYBkK45v3DzGXhncH1Bq2Hr883OxUm7rtz0w/cm1kC5vnkbmIJkli3CvMkNBrPxeC uU2Lmb+7W6aRmrxtSIbjTOMlARHfKwa2mNu1nZn8wIo3UvZ7T9uCUX7QSOBdXa9Pctf1 yecA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=SgwxZ+7gYByz1ukIozRlYZNVczP1+9iCeAmnhFmDKhE=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=Igob1U/fIsHfJ+Bx9uzpI7xusdemXe59Zziw2xsoSuCFRFyGc/rM3lPPdgZtQdBkUG 4SAEzxx0VTdav6B0UDi373G94XNM4VKKfA1xe/ri2hdkK16SN0785VG7Wtr6Ab1ZQL+v AvqeNxy+X26nzqkC0lEXCFh+Z+pZrq6x0145nPNaUmTt+sIqODoXYIjTxMNdiXXE/6BO 8eEtLUYkMpSNiVyycLlWzy6OQC6Wn87FhAkux/58Tmlk9riWz9Q+WuAEZGvqGHHMeZMK 9h0+COHgLFQPRt/isXIWNr2xrBLIDxX3GkGxOLgzC3fUm8DVgchi5CdHi7A2FpXC/Wt7 OTtg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WhsdKq73; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:31:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 31/33] target/xtensa: Populate CPUClass.mmu_index Date: Tue, 30 Jan 2024 09:30:41 +1000 Message-Id: <20240129233043.34558-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/xtensa/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 62020b1f33..79f91819df 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -74,6 +74,11 @@ static bool xtensa_cpu_has_work(CPUState *cs) #endif } +static int xtensa_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return xtensa_get_cring(cpu_env(cs)); +} + #ifdef CONFIG_USER_ONLY static bool abi_call0; @@ -252,6 +257,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = xtensa_cpu_class_by_name; cc->has_work = xtensa_cpu_has_work; + cc->mmu_index = xtensa_cpu_mmu_index; cc->dump_state = xtensa_cpu_dump_state; cc->set_pc = xtensa_cpu_set_pc; cc->get_pc = xtensa_cpu_get_pc; From patchwork Mon Jan 29 23:30:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767485 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1127513wro; Mon, 29 Jan 2024 15:38:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IEYsF/XIluAy3sPiekXwTTo/DJOBVcIswXyQ+Dhh3YBdWIQkHVn8BVoht4MHMmZDg0Hl98u X-Received: by 2002:a05:6808:1411:b0:3bc:3cc4:e29e with SMTP id w17-20020a056808141100b003bc3cc4e29emr10557523oiv.42.1706571489506; Mon, 29 Jan 2024 15:38:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571489; cv=none; d=google.com; s=arc-20160816; b=PB83FGlsOSjyklS8Pd44K80cjdVw/Z5PJKg1pJDXuTU9ZVFv9Cc9fHfr6Ok2pHRFYq VxQqgNv8UOaFXVVrDULQaxGoU7g63JEDu2qfi5qWAlj1C2XyQ8Y/YoTfxH6Cuzb41JHK Yx1vzdAq/uEqoPo1ppGfFc9hWobiMCchil9coN64mH9+v8Pp1+t9MpkfFp7Y2baCh8mJ VDD4Mu27cC9HHNiFbnLjY0p8wKLWUkZFD7Ap6DipeIBn2mhMzeS8+WCUt/mWZC965iGP auYzrjFJuqmZlgiDfnwcTZV4E9jKU6TBMX3VTp5wFJdihwm1miSsHsng69KILkb655Yr +23g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=EOCVROUqo6BWAAqVMvgh7b7Oex6mEKUK85oHrQsmtgA=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=lPi/xrsnvwl73rL957eE5xCFfJlxRCnQo017stgLijySnQ2G6rVR7HKJTdx389qLXU tSjAWj/PGZJR7cX8lbj7KnLQy44TyynGa+bZTRYqu2OW6jmFvZKyNEtkyJWx+ZFQAHHx CYk8PhNcYtHTbKOneL+2jDcbzVi5et6CQ89c0QK07NI8eLJvHyX+35NtMaNZhQe/uRCs VipK3EftOMWJnl49kubj30Tb6pWI7meWra7geLkGK1Si98kSTe1wBnSXdusuH7R2XNEn NmwCKs7gmI+9hNJjkEOofu2RnCOMlI64ZaKiNAlePCZdIYTA1s4aORrBcGeMcugQZHoX AEcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RclNK3ur; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.31.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:32:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 32/33] include/exec: Implement cpu_mmu_index generically Date: Tue, 30 Jan 2024 09:30:42 +1000 Message-Id: <20240129233043.34558-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For user-only mode, use MMU_USER_IDX. For system mode, use CPUClass.mmu_index. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 4 ++++ include/exec/cpu-common.h | 19 +++++++++++++++++++ target/alpha/cpu.h | 5 ----- target/arm/cpu.h | 13 ------------- target/avr/cpu.h | 5 ----- target/cris/cpu.h | 4 ---- target/hexagon/cpu.h | 9 --------- target/hppa/cpu.h | 10 ---------- target/i386/cpu.h | 6 ------ target/loongarch/cpu.h | 10 ---------- target/m68k/cpu.h | 4 ---- target/microblaze/cpu.h | 6 ------ target/mips/cpu.h | 5 ----- target/nios2/cpu.h | 6 ------ target/openrisc/cpu.h | 6 ------ target/ppc/cpu.h | 5 ----- target/riscv/cpu.h | 2 -- target/rx/cpu.h | 5 ----- target/s390x/cpu.h | 2 -- target/sh4/cpu.h | 6 ------ target/sparc/cpu.h | 6 ------ target/tricore/cpu.h | 5 ----- target/xtensa/cpu.h | 5 ----- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- 31 files changed, 31 insertions(+), 133 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 8501a33dbf..80c0d0699b 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -311,6 +311,10 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2)) #define TLB_WATCHPOINT 0 +static inline int cpu_mmu_index(CPUArchState *env, bool ifetch) +{ + return MMU_USER_IDX; +} #else /* diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index dcbd5f5783..5a4a36a7d8 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -262,4 +262,23 @@ static inline CPUState *env_cpu(CPUArchState *env) return (void *)env - sizeof(CPUState); } +#ifndef CONFIG_USER_ONLY +/** + * cpu_mmu_index: + * @env: The cpu environment + * @ifetch: True for code access, false for data access. + * + * Return the core mmu index for the current translation regime. + * This function is used by generic TCG code paths. + * + * The user-only version of this function is inline in cpu-all.h, + * where it always returns MMU_USER_IDX. + */ +static inline int cpu_mmu_index(CPUArchState *env, bool ifetch) +{ + CPUState *cs = env_cpu(env); + return cs->cc->mmu_index(cs, ifetch); +} +#endif /* !CONFIG_USER_ONLY */ + #endif /* CPU_COMMON_H */ diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 3beff2738a..7188a409a0 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -398,11 +398,6 @@ static inline int alpha_env_mmu_index(CPUAlphaState *env) return ret; } -static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) -{ - return alpha_env_mmu_index(env); -} - enum { IR_V0 = 0, IR_T0 = 1, diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d3477b1601..63f31e0d98 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3240,19 +3240,6 @@ FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) -/** - * cpu_mmu_index: - * @env: The cpu environment - * @ifetch: True for code access, false for data access. - * - * Return the core mmu index for the current translation regime. - * This function is used by generic TCG code paths. - */ -static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) -{ - return EX_TBFLAG_ANY(env->hflags, MMUIDX); -} - /** * sve_vq * @env: the cpu context diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 4595c6bb18..d185d20dcb 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -184,11 +184,6 @@ static inline void set_avr_feature(CPUAVRState *env, int feature) env->features |= (1U << feature); } -static inline int cpu_mmu_index(CPUAVRState *env, bool ifetch) -{ - return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; -} - void avr_cpu_tcg_init(void); int cpu_avr_exec(CPUState *cpu); diff --git a/target/cris/cpu.h b/target/cris/cpu.h index d830dcac5b..3904e5448c 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -260,10 +260,6 @@ enum { /* MMU modes definitions */ #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) -{ - return !!(env->pregs[PR_CCS] & U_FLAG); -} /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 5c11ae3445..3eef58fe8f 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -146,15 +146,6 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, *flags = hex_flags; } -static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else -#error System mode not supported on Hexagon yet -#endif -} - typedef HexagonCPU ArchCPU; void hexagon_translate_init(void); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 04439f247d..7a181e8f33 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -281,16 +281,6 @@ static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE; } -int hppa_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else - return hppa_cpu_mmu_index(env_cpu(env), ifetch); -#endif -} - void hppa_translate_init(void); #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 62bdb02378..6a5b180ccb 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2315,12 +2315,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env) #include "hw/i386/apic.h" #endif -int x86_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) -{ - return x86_cpu_mmu_index(env_cpu(env), ifetch); -} - static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 47fd110e81..ec37579fd6 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -408,16 +408,6 @@ struct LoongArchCPUClass { #define MMU_USER_IDX MMU_PLV_USER #define MMU_DA_IDX 4 -int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else - return loongarch_cpu_mmu_index(env_cpu(env), ifetch); -#endif -} - static inline bool is_la64(CPULoongArchState *env) { return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index d13427b0fe..aca4aa610b 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -577,10 +577,6 @@ enum { /* MMU modes definitions */ #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) -{ - return (env->sr & SR_S) == 0 ? 1 : 0; -} bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 90ab796de9..446af5dd4c 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -434,12 +434,6 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, MemTxResult response, uintptr_t retaddr); #endif -int mb_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) -{ - return mb_cpu_mmu_index(env_cpu(env), ifetch); -} - #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_mb_cpu; #endif diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 4c15e76781..ef26fe03c7 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1260,11 +1260,6 @@ static inline int mips_env_mmu_index(CPUMIPSState *env) return hflags_mmu_index(env->hflags); } -static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) -{ - return mips_env_mmu_index(env); -} - #include "exec/cpu-all.h" /* Exceptions */ diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 9965ff74c1..4164a3432e 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -286,12 +286,6 @@ FIELD(TBFLAGS, CRS0, 0, 1) /* Set if CRS == 0. */ FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */ FIELD(TBFLAGS, R0_0, 2, 1) /* Set if R0 == 0. */ -int nios2_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) -{ - return nios2_cpu_mmu_index(env_cpu(env), ifetch); -} - static inline void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 7dbed8d8be..b1b7db5cbd 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -361,12 +361,6 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); } -int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) -{ - return openrisc_cpu_mmu_index(env_cpu(env), ifetch); -} - static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) { return (env->sr diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 5f4f52aec5..a44de22ca4 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1633,11 +1633,6 @@ static inline int ppc_env_mmu_index(CPUPPCState *env, bool ifetch) #endif } -static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) -{ - return ppc_env_mmu_index(env, ifetch); -} - /* Compatibility modes */ #if defined(TARGET_PPC64) bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9c825c7b51..f63ee9cc58 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -507,8 +507,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); -#define cpu_mmu_index riscv_env_mmu_index - #ifndef CONFIG_USER_ONLY void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 65f9cd2d0a..c53593d7aa 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -158,11 +158,6 @@ static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, *flags = FIELD_DP32(*flags, PSW, U, env->psw_u); } -static inline int cpu_mmu_index(CPURXState *env, bool ifetch) -{ - return 0; -} - static inline uint32_t rx_cpu_pack_psw(CPURXState *env) { uint32_t psw = 0; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index f0fed5d6ad..d37a49b4d9 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -412,8 +412,6 @@ static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch) #endif } -#define cpu_mmu_index s390x_env_mmu_index - #ifdef CONFIG_TCG #include "tcg/tcg_s390x.h" diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 9c5e2b349e..9211da6bde 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -370,12 +370,6 @@ static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr) env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); } -int sh4_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUSH4State *env, bool ifetch) -{ - return sh4_cpu_mmu_index(env_cpu(env), ifetch); -} - static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 92c58c92c1..51856152fa 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -749,12 +749,6 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_HYPER (1 << 7) #define TB_FLAG_ASI_SHIFT 24 -int sparc_cpu_mmu_index(CPUState *cs, bool ifetch); -static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) -{ - return sparc_cpu_mmu_index(env_cpu(env), ifetch); -} - static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags) { diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 2d4446cea5..220af69fc2 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -246,11 +246,6 @@ void fpu_set_state(CPUTriCoreState *env); #define MMU_USER_IDX 2 -static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) -{ - return 0; -} - #include "exec/cpu-all.h" FIELD(TB_FLAGS, PRIV, 0, 2) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 4b033ee924..6b8d0636d2 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -713,11 +713,6 @@ static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) /* MMU modes definitions */ #define MMU_USER_IDX 3 -static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) -{ - return xtensa_get_cring(env); -} - #define XTENSA_TBFLAG_RING_MASK 0x3 #define XTENSA_TBFLAG_EXCM 0x4 #define XTENSA_TBFLAG_LITBASE 0x8 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index fbb37e541e..5f87c1b12a 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -94,7 +94,7 @@ static bool hppa_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } -int hppa_cpu_mmu_index(CPUState *cs, bool ifetch) +static int hppa_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUHPPAState *env = cpu_env(cs); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 280bcb7d00..ef46755a50 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7720,7 +7720,7 @@ static bool x86_cpu_has_work(CPUState *cs) return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; } -int x86_cpu_mmu_index(CPUState *cs, bool ifetch) +static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUX86State *env = cpu_env(cs); diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 139acfe373..b08d0dc5de 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -375,7 +375,7 @@ static bool loongarch_cpu_has_work(CPUState *cs) #endif } -int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) +static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) { CPULoongArchState *env = cpu_env(cs); diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6dad11905b..2002231a6b 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -118,7 +118,7 @@ static bool mb_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } -int mb_cpu_mmu_index(CPUState *cs, bool ifetch) +static int mb_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUMBState *env = cpu_env(cs); MicroBlazeCPU *cpu = env_archcpu(env); diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index e42885997e..0760bf6b38 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -57,7 +57,7 @@ static bool nios2_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } -int nios2_cpu_mmu_index(CPUState *cs, bool ifetch) +static int nios2_cpu_mmu_index(CPUState *cs, bool ifetch) { return (cpu_env(cs)->ctrl[CR_STATUS] & CR_STATUS_U ? MMU_USER_IDX : MMU_SUPERVISOR_IDX); diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 8670152c84..a3cb80ca34 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -68,7 +68,7 @@ static bool openrisc_cpu_has_work(CPUState *cs) CPU_INTERRUPT_TIMER); } -int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) +static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUOpenRISCState *env = cpu_env(cs); diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 6fead5655f..2031168dc6 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -89,7 +89,7 @@ static bool superh_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } -int sh4_cpu_mmu_index(CPUState *cs, bool ifetch) +static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUSH4State *env = cpu_env(cs); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 7a3b815737..afa62723fe 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -718,7 +718,7 @@ static bool sparc_cpu_has_work(CPUState *cs) cpu_interrupts_enabled(env); } -int sparc_cpu_mmu_index(CPUState *cs, bool ifetch) +static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch) { CPUSPARCState *env = cpu_env(cs); From patchwork Mon Jan 29 23:30:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767489 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp1127926wro; Mon, 29 Jan 2024 15:39:45 -0800 (PST) X-Google-Smtp-Source: AGHT+IEP3ipAvD4tRuhYz42PZ+/+KKQg1qKTbogQQb3huKLnptQHRKktZs5VRjB2wH+oraOX0dMs X-Received: by 2002:a05:620a:ce2:b0:783:f72e:6a4b with SMTP id c2-20020a05620a0ce200b00783f72e6a4bmr3530216qkj.8.1706571585094; Mon, 29 Jan 2024 15:39:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706571585; cv=none; d=google.com; s=arc-20160816; b=Hib/88PMRWUZwEtEeISNc/dNjVKn7Xbz9wSPuNZ7uLutT+IXr4ysU+XkLYnZDG5+40 6RTgahj8BvyHw9u3qi8VJ0QYE8Ufc1PDeHuazymaAANQXH+z/1zMYWFwbYcUcdcUXGOn 0cTszaM4vfJLMnCey0NkqJ7UoBs8Gh740uISQdGkS6C2AjtxwUDN4L/oYlzeiL1ILGSC ppi0SSeoP3RU0UlKn/BJ+CKf3LzqGtX7i+ASZfZ3Hp+jmNrXFnegDYYPoIf8yY5KJNIS I4DoQNNLVN9mMfZOVT6NKxzV6ZXExl4hKh4XXLthuLUocO0fgh7V9bgElZg239zT1iQ2 Th3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=NRFiIFFXsXgZu5z5Pbd1LGjtyQm58p6bIAWrhZNFn9w=; fh=d3q967Ss27yOZEBNWb7WV1pwIIYORDjfLhLmomzC17w=; b=tOzQ4c7dc+6jYWQDCPHSsVtkUyR+nNQaXT0dQ44NKfIKhpL0d8b0vypJIzbHCQQo8B CyazbmBFyWAuQ7m+Vv3RNwEDwlsvBeA95Wv3GDTHf94vPG+rq26O47yzHdD5FV/zaNGd Bc/gu4asyPP4oivIjvV9RwxPbhMlCOU2PxtmYf1ajkDU3zF1xxHKPJzWeob6skIfflCt ZdPg3eZ6HSdtD75W8nt2ae2NABTnlKrmp7hAaB+Sbv1EmEyV4VSkRHoeGyBh92STzGRJ QECwwFt1IltTEpWM8eZ09FQgLpyXMAF71oQ+WNkTRXSeKMNyATXefv0xr7HlE8dpcAhj Wokw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OGTJxR6E; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id l6-20020a170902eb0600b001d8dbb867b1sm2710591plb.179.2024.01.29.15.32.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 15:32:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH 33/33] include/exec: Change cpu_mmu_index argument to CPUState Date: Tue, 30 Jan 2024 09:30:43 +1000 Message-Id: <20240129233043.34558-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129233043.34558-1-richard.henderson@linaro.org> References: <20240129233043.34558-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 2 +- include/exec/cpu-common.h | 3 +-- target/sparc/cpu.h | 2 +- accel/tcg/cputlb.c | 22 +++++++++------- semihosting/uaccess.c | 2 +- target/cris/translate.c | 2 +- target/hppa/mem_helper.c | 2 +- target/hppa/op_helper.c | 8 +++--- target/i386/tcg/translate.c | 2 +- target/loongarch/tcg/tlb_helper.c | 4 +-- target/m68k/op_helper.c | 2 +- target/microblaze/helper.c | 3 +-- target/microblaze/mmu.c | 2 +- target/microblaze/translate.c | 2 +- target/nios2/translate.c | 2 +- target/openrisc/translate.c | 2 +- target/sparc/ldst_helper.c | 2 +- target/sparc/mmu_helper.c | 2 +- target/tricore/helper.c | 2 +- target/tricore/translate.c | 2 +- target/xtensa/mmu_helper.c | 2 +- accel/tcg/ldst_common.c.inc | 42 ++++++++++++++++++++----------- 22 files changed, 65 insertions(+), 49 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 80c0d0699b..bc05dce7ab 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -311,7 +311,7 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2)) #define TLB_WATCHPOINT 0 -static inline int cpu_mmu_index(CPUArchState *env, bool ifetch) +static inline int cpu_mmu_index(CPUState *cs, bool ifetch) { return MMU_USER_IDX; } diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 5a4a36a7d8..532663e81d 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -274,9 +274,8 @@ static inline CPUState *env_cpu(CPUArchState *env) * The user-only version of this function is inline in cpu-all.h, * where it always returns MMU_USER_IDX. */ -static inline int cpu_mmu_index(CPUArchState *env, bool ifetch) +static inline int cpu_mmu_index(CPUState *cs, bool ifetch) { - CPUState *cs = env_cpu(env); return cs->cc->mmu_index(cs, ifetch); } #endif /* !CONFIG_USER_ONLY */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 51856152fa..1e076f6355 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -755,7 +755,7 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, uint32_t flags; *pc = env->pc; *cs_base = env->npc; - flags = cpu_mmu_index(env, false); + flags = cpu_mmu_index(env_cpu(env), false); #ifndef CONFIG_USER_ONLY if (cpu_supervisor_mode(env)) { flags |= TB_FLAG_SUPER; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 3facfcbb24..047cd2cc0a 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1601,7 +1601,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr, void *p; (void)probe_access_internal(env_cpu(env), addr, 1, MMU_INST_FETCH, - cpu_mmu_index(env, true), false, + cpu_mmu_index(env_cpu(env), true), false, &p, &full, 0, false); if (p == NULL) { return -1; @@ -2959,26 +2959,30 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, Int128 val, uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr) { - MemOpIdx oi = make_memop_idx(MO_UB, cpu_mmu_index(env, true)); - return do_ld1_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); + CPUState *cs = env_cpu(env); + MemOpIdx oi = make_memop_idx(MO_UB, cpu_mmu_index(cs, true)); + return do_ld1_mmu(cs, addr, oi, 0, MMU_INST_FETCH); } uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr) { - MemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(env, true)); - return do_ld2_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); + CPUState *cs = env_cpu(env); + MemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(cs, true)); + return do_ld2_mmu(cs, addr, oi, 0, MMU_INST_FETCH); } uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr) { - MemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(env, true)); - return do_ld4_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); + CPUState *cs = env_cpu(env); + MemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(cs, true)); + return do_ld4_mmu(cs, addr, oi, 0, MMU_INST_FETCH); } uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr) { - MemOpIdx oi = make_memop_idx(MO_TEUQ, cpu_mmu_index(env, true)); - return do_ld8_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); + CPUState *cs = env_cpu(env); + MemOpIdx oi = make_memop_idx(MO_TEUQ, cpu_mmu_index(cs, true)); + return do_ld8_mmu(cs, addr, oi, 0, MMU_INST_FETCH); } uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, diff --git a/semihosting/uaccess.c b/semihosting/uaccess.c index 5d889f9263..dc587d73bc 100644 --- a/semihosting/uaccess.c +++ b/semihosting/uaccess.c @@ -26,7 +26,7 @@ void *uaccess_lock_user(CPUArchState *env, target_ulong addr, ssize_t uaccess_strlen_user(CPUArchState *env, target_ulong addr) { - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = cpu_mmu_index(env_cpu(env), false); size_t len = 0; while (1) { diff --git a/target/cris/translate.c b/target/cris/translate.c index 7acea29a01..8f74b6c53f 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -2966,7 +2966,7 @@ static void cris_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->cpu = env_archcpu(env); dc->ppc = pc_start; dc->pc = pc_start; - dc->mem_index = cpu_mmu_index(env, false); + dc->mem_index = cpu_mmu_index(cs, false); dc->flags_uptodate = 1; dc->flags_x = tb_flags & X_FLAG; dc->cc_x_uptodate = 0; diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 4fcc612754..629a9d90ef 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -646,7 +646,7 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr) void HELPER(diag_btlb)(CPUHPPAState *env) { unsigned int phys_page, len, slot; - int mmu_idx = cpu_mmu_index(env, 0); + int mmu_idx = cpu_mmu_index(env_cpu(env), 0); uintptr_t ra = GETPC(); HPPATLBEntry *btlb; uint64_t virt_page; diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index ce15469465..b1f24a5aad 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -59,7 +59,7 @@ void HELPER(tcond)(CPUHPPAState *env, target_ulong cond) static void atomic_store_mask32(CPUHPPAState *env, target_ulong addr, uint32_t val, uint32_t mask, uintptr_t ra) { - int mmu_idx = cpu_mmu_index(env, 0); + int mmu_idx = cpu_mmu_index(env_cpu(env), 0); uint32_t old, new, cmp, *haddr; void *vaddr; @@ -86,7 +86,7 @@ static void atomic_store_mask64(CPUHPPAState *env, target_ulong addr, int size, uintptr_t ra) { #ifdef CONFIG_ATOMIC64 - int mmu_idx = cpu_mmu_index(env, 0); + int mmu_idx = cpu_mmu_index(env_cpu(env), 0); uint64_t old, new, cmp, *haddr; void *vaddr; @@ -235,7 +235,7 @@ static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ulong val, default: /* Nothing is stored, but protection is checked and the cacheline is marked dirty. */ - probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra); + probe_write(env, addr, 0, cpu_mmu_index(env_cpu(env), 0), ra); break; } } @@ -296,7 +296,7 @@ static void do_stdby_e(CPUHPPAState *env, target_ulong addr, uint64_t val, default: /* Nothing is stored, but protection is checked and the cacheline is marked dirty. */ - probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra); + probe_write(env, addr, 0, cpu_mmu_index(env_cpu(env), 0), ra); break; } } diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 2808903661..10cba16256 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -6955,7 +6955,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->cc_op_dirty = false; dc->popl_esp_hack = 0; /* select memory access functions */ - dc->mem_index = cpu_mmu_index(env, false); + dc->mem_index = cpu_mmu_index(cpu, false); dc->cpuid_features = env->features[FEAT_1_EDX]; dc->cpuid_ext_features = env->features[FEAT_1_ECX]; dc->cpuid_ext2_features = env->features[FEAT_8000_0001_EDX]; diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index 65ffbef08e..9e2a44c119 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -241,7 +241,7 @@ hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) int prot; if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) != 0) { + cpu_mmu_index(cs, false)) != 0) { return -1; } return phys_addr; @@ -320,7 +320,7 @@ static void invalidate_tlb_entry(CPULoongArchState *env, int index) uint8_t tlb_ps; LoongArchTLB *tlb = &env->tlb[index]; - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = cpu_mmu_index(env_cpu(env), false); uint8_t tlb_v0 = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V); uint8_t tlb_v1 = FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V); uint64_t tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN); diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 1ce850bbc5..47b4173bb9 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -811,7 +811,7 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2, uint32_t l1, l2; uintptr_t ra = GETPC(); #if defined(CONFIG_ATOMIC64) - int mmu_idx = cpu_mmu_index(env, 0); + int mmu_idx = cpu_mmu_index(env_cpu(env), 0); MemOpIdx oi = make_memop_idx(MO_BEUQ, mmu_idx); #endif diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 98bdb82de8..460eee0cf5 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -228,10 +228,9 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - CPUMBState *env = &cpu->env; target_ulong vaddr, paddr = 0; MicroBlazeMMULookup lu; - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = cpu_mmu_index(cs, false); unsigned int hit; /* Caller doesn't initialize */ diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 75651979a9..234006634e 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -305,7 +305,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) } hit = mmu_translate(cpu, &lu, v & TLB_EPN_MASK, - 0, cpu_mmu_index(env, false)); + 0, cpu_mmu_index(env_cpu(env), false)); if (hit) { env->mmu.regs[MMU_R_TLBX] = lu.idx; } else { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 2e628647d1..a465c2d245 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1607,7 +1607,7 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->ext_imm = dc->base.tb->cs_base; dc->r0 = NULL; dc->r0_set = false; - dc->mem_index = cpu_mmu_index(&cpu->env, false); + dc->mem_index = cpu_mmu_index(cs, false); dc->jmp_cond = dc->tb_flags & D_FLAG ? TCG_COND_ALWAYS : TCG_COND_NEVER; dc->jmp_dest = -1; diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 3078372b36..612556b297 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -948,7 +948,7 @@ static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) Nios2CPU *cpu = env_archcpu(env); int page_insns; - dc->mem_idx = cpu_mmu_index(env, false); + dc->mem_idx = cpu_mmu_index(cs, false); dc->cr_state = cpu->cr_state; dc->tb_flags = dc->base.tb->flags; dc->eic_present = cpu->eic_present; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index d4cbc5eaea..785bcb6552 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1528,7 +1528,7 @@ static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) CPUOpenRISCState *env = cpu_env(cs); int bound; - dc->mem_idx = cpu_mmu_index(env, false); + dc->mem_idx = cpu_mmu_index(cs, false); dc->tb_flags = dc->base.tb->flags; dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0; dc->cpucfgr = env->cpucfgr; diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 09066d5487..52aa6c631b 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -690,7 +690,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */ break; case ASI_KERNELTXT: /* Supervisor code access */ - oi = make_memop_idx(memop, cpu_mmu_index(env, true)); + oi = make_memop_idx(memop, cpu_mmu_index(env_cpu(env), true)); switch (size) { case 1: ret = cpu_ldb_code_mmu(env, addr, oi, GETPC()); diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 453498c670..5170a668bb 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -901,7 +901,7 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; hwaddr phys_addr; - int mmu_idx = cpu_mmu_index(env, false); + int mmu_idx = cpu_mmu_index(cs, false); if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) != 0) { if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) { diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 174f666e1e..649373a9cb 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -48,7 +48,7 @@ hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) TriCoreCPU *cpu = TRICORE_CPU(cs); hwaddr phys_addr; int prot; - int mmu_idx = cpu_mmu_index(&cpu->env, false); + int mmu_idx = cpu_mmu_index(cs, false); if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, MMU_DATA_LOAD, mmu_idx)) { diff --git a/target/tricore/translate.c b/target/tricore/translate.c index f1156c39e7..278c514ab0 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8355,7 +8355,7 @@ static void tricore_tr_init_disas_context(DisasContextBase *dcbase, { DisasContext *ctx = container_of(dcbase, DisasContext, base); CPUTriCoreState *env = cpu_env(cs); - ctx->mem_idx = cpu_mmu_index(env, false); + ctx->mem_idx = cpu_mmu_index(cs, false); uint32_t tb_flags = (uint32_t)ctx->base.tb->flags; ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 2fda4e887c..47063b0a57 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -66,7 +66,7 @@ void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr) * only the side-effects (ie any MMU or other exception) */ probe_access(env, vaddr, 1, MMU_INST_FETCH, - cpu_mmu_index(env, true), GETPC()); + cpu_mmu_index(env_cpu(env), true), GETPC()); } void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) diff --git a/accel/tcg/ldst_common.c.inc b/accel/tcg/ldst_common.c.inc index 44833513fb..c82048e377 100644 --- a/accel/tcg/ldst_common.c.inc +++ b/accel/tcg/ldst_common.c.inc @@ -354,7 +354,8 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_ldub_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index = cpu_mmu_index(env_cpu(env), false); + return cpu_ldub_mmuidx_ra(env, addr, mmu_index, ra); } int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) @@ -364,7 +365,8 @@ int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_lduw_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index = cpu_mmu_index(env_cpu(env), false); + return cpu_lduw_be_mmuidx_ra(env, addr, mmu_index, ra); } int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) @@ -374,17 +376,20 @@ int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_ldl_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index = cpu_mmu_index(env_cpu(env), false); + return cpu_ldl_be_mmuidx_ra(env, addr, mmu_index, ra); } uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_ldq_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index = cpu_mmu_index(env_cpu(env), false); + return cpu_ldq_be_mmuidx_ra(env, addr, mmu_index, ra); } uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_lduw_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index = cpu_mmu_index(env_cpu(env), false); + return cpu_lduw_le_mmuidx_ra(env, addr, mmu_index, ra); } int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) @@ -394,54 +399,63 @@ int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_ldl_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index = cpu_mmu_index(env_cpu(env), false); + return cpu_ldl_le_mmuidx_ra(env, addr, mmu_index, ra); } uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { - return cpu_ldq_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); + int mmu_index = cpu_mmu_index(env_cpu(env), false); + return cpu_ldq_le_mmuidx_ra(env, addr, mmu_index, ra); } void cpu_stb_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra) { - cpu_stb_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index = cpu_mmu_index(env_cpu(env), false); + cpu_stb_mmuidx_ra(env, addr, val, mmu_index, ra); } void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra) { - cpu_stw_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index = cpu_mmu_index(env_cpu(env), false); + cpu_stw_be_mmuidx_ra(env, addr, val, mmu_index, ra); } void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra) { - cpu_stl_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index = cpu_mmu_index(env_cpu(env), false); + cpu_stl_be_mmuidx_ra(env, addr, val, mmu_index, ra); } void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr addr, uint64_t val, uintptr_t ra) { - cpu_stq_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index = cpu_mmu_index(env_cpu(env), false); + cpu_stq_be_mmuidx_ra(env, addr, val, mmu_index, ra); } void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra) { - cpu_stw_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index = cpu_mmu_index(env_cpu(env), false); + cpu_stw_le_mmuidx_ra(env, addr, val, mmu_index, ra); } void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra) { - cpu_stl_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index = cpu_mmu_index(env_cpu(env), false); + cpu_stl_le_mmuidx_ra(env, addr, val, mmu_index, ra); } void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr addr, uint64_t val, uintptr_t ra) { - cpu_stq_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); + int mmu_index = cpu_mmu_index(env_cpu(env), false); + cpu_stq_le_mmuidx_ra(env, addr, val, mmu_index, ra); } /*--------------------------*/