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[34.141.189.94]) by smtp.gmail.com with ESMTPSA id q10-20020aa7cc0a000000b0055ef56f4575sm2281225edt.39.2024.01.30.01.38.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 01:38:27 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Andr=C3=A9?= =?utf-8?q?_Draszik?= Subject: [PATCH v2 1/6] clk: samsung: gs101: gpio_peric0_pclk needs to be kept on Date: Tue, 30 Jan 2024 09:36:40 +0000 Message-ID: <20240130093812.1746512-2-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240130093812.1746512-1-andre.draszik@linaro.org> References: <20240130093812.1746512-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This pclk clock is required any time we access the pinctrl registers of this block. Since pinctrl-samsung doesn't support a clock at the moment, we just keep the kernel from disabling it at boot, until we have an update for pinctrl-samsung to handle this required clock, at which point we'll be able to drop the flag again. Fixes: 893f133a040b ("clk: samsung: gs101: add support for cmu_peric0") Signed-off-by: André Draszik Reviewed-by: Sam Protsenko Reviewed-by: Tudor Ambarus Reviewed-by: Peter Griffin --- v2: collect Reviewed-by: tags --- drivers/clk/samsung/clk-gs101.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c index 4a0520e825b6..61bb0dcf84ee 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -2848,7 +2848,7 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK, "gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, - 21, 0, 0), + 21, CLK_IGNORE_UNUSED, 0), /* Disabling this clock makes the system hang. Mark the clock as critical. */ GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK, "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user", From patchwork Tue Jan 30 09:36:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Draszik?= X-Patchwork-Id: 768264 Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3F6E6089E for ; Tue, 30 Jan 2024 09:38:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706607514; cv=none; b=rJjcEDR40o+MQIDmduVx64Ru1b4AHIch5O8FuzuhiyydNiqXyr2R3m9p7otTZTfd1kj2KqwH4NeTNUxnNdVoawzWVWyBiQsGZNWRHRNZM7+EXJqHsk40/U7N/rYAt3QKmDp6z+eNwCiCq4nt4m7PkCPunXHar8snj+6g7PFv8nc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706607514; c=relaxed/simple; bh=KmlVQI5t6vRCllo/cOaAJqkCPGhX9wTEE9PDUFITUjE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=k+mjZqshowwSSrEfUXG5iRqFTvem57775fG/eBPv7HPToqtrBVJ8kudG3GBhGSQKLQTgaQ4Bv78uvUMsWHUVulhA86QE9EPyb0BwU7KTD8f40C93N9fzA4Z/ylyPVcS1FwFlNPdvZYkzv2+Xbq+DLQW2DL+lXbqSh5DCVjr8dLs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=yQCaAXXb; arc=none smtp.client-ip=209.85.208.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="yQCaAXXb" Received: by mail-ed1-f48.google.com with SMTP id 4fb4d7f45d1cf-55f2b0c5ae9so1364512a12.2 for ; Tue, 30 Jan 2024 01:38:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706607509; x=1707212309; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TAQSA+kK9jYgf9iRBFCJiMz1V0l84ZXoobUQ8ktAm0o=; b=yQCaAXXbt9/VBWNTUatbrRUbuxcKR3GlRGwqpgUcaro7C9RK5gO2EC+rtK10qrfVhY vD78PqQ9Qr5UI/IuM+4LgGTS0nQNlxhHF/9M4nBIOTju5ZkfFWnB3fyKYChK3fIESymk uLXevaiAMx06iE6RimyEgqnDX55Nvo/n/9DTOR1p37XOFd605q6O11Ettwe1Q2DFwTVM QLDFgJGIxqqeYTJRxl/FC57aVwun0rPS48NpjoV0IT9u//S7Xt6fQJVUm3kWgfdJdf57 3foYMkd3mitmRQbX60dcvQr+00tgMRgS8kDbFrQOz4P1U164Kqlrze3d6Nf2KM24esyF fz4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706607509; x=1707212309; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TAQSA+kK9jYgf9iRBFCJiMz1V0l84ZXoobUQ8ktAm0o=; b=ZbiI7STBIcDbZIckHB7t/6DNBA4K4DJWXlgqMk1iZ0E54cIPNLwjBk70G1Vb6e0lBj pZsi1KGcKXzkopFypUsGjC/95g0VB2Mp6RM+as/S8CkdePkhRnub9kBbUEaJZfUwMGaC XwvKi2cl1nRSyJtYitjuRKN8x6q6enItM4Vj/UXPCyJRPKrJGkZNsGkc7niUu46ZQHd9 7hyH+NeTMyNiCM6S5pVb+gGZ0fBJSc6JDPIFaD7Jh01GGS8WBo82UQSXyNicpAC8CZI5 UUEVGGiQUImrxk79zSzxxx39XK+lWaWi4RrtQomLMnTEjBCcpr5svFuXlO+SAR/lex4q XK3A== X-Gm-Message-State: AOJu0YwMp400ImzmEMY35mpS3QweEfhkO6CNq4OKhOtz5qCqNeUn3bGo JP3rU5DNKCTuPmY7c0AoN3ieJVhuxat5VuEYJ04e7oE+Qo7tGFbT7I4d4R6Rdjg= X-Google-Smtp-Source: AGHT+IF/m5mOArbCMzdGKzrOsjS0gVO6XRzIQWNVZ+HOi84zCHVgcM0i192IppW0vZqT+Xw+n90eTw== X-Received: by 2002:aa7:d7c4:0:b0:55f:aa:12a7 with SMTP id e4-20020aa7d7c4000000b0055f00aa12a7mr3320283eds.16.1706607508887; Tue, 30 Jan 2024 01:38:28 -0800 (PST) Received: from puffmais.c.googlers.com.com (94.189.141.34.bc.googleusercontent.com. [34.141.189.94]) by smtp.gmail.com with ESMTPSA id q10-20020aa7cc0a000000b0055ef56f4575sm2281225edt.39.2024.01.30.01.38.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 01:38:28 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Andr=C3=A9?= =?utf-8?q?_Draszik?= Subject: [PATCH v2 4/6] arm64: dts: exynos: gs101: use correct clocks for usi_uart Date: Tue, 30 Jan 2024 09:36:43 +0000 Message-ID: <20240130093812.1746512-5-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240130093812.1746512-1-andre.draszik@linaro.org> References: <20240130093812.1746512-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Wrong pclk clocks have been used in this usi_uart instance here. For USI and UART, we need the ipclk and pclk, where pclk is the bus clock. Without it, nothing can work. It is unclear what exactly is using USI0_UART_CLK, but it is not required for the IP to be operational at this stage, while pclk is. This also brings the DT in line with the clock names expected by the usi and uart drivers. Update the DTSI accordingly. Fixes: d97b6c902a40 ("arm64: dts: exynos: gs101: update USI UART to use peric0 clocks") Signed-off-by: André Draszik Reviewed-by: Sam Protsenko Reviewed-by: Tudor Ambarus Tested-by: Tudor Ambarus --- v2: * fix a typo in and add an empty line to the commit message * collect Reviewed-by: Tested-by: tags --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index e5b665be2d62..f93e937d2726 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -410,7 +410,7 @@ usi_uart: usi@10a000c0 { ranges; #address-cells = <1>; #size-cells = <1>; - clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x1020>; @@ -422,7 +422,7 @@ serial_0: serial@10a00000 { reg = <0x10a00000 0xc0>; interrupts = ; - clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; From patchwork Tue Jan 30 09:36:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Draszik?= X-Patchwork-Id: 768265 Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4AF2B60B97 for ; Tue, 30 Jan 2024 09:38:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706607513; 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[34.141.189.94]) by smtp.gmail.com with ESMTPSA id q10-20020aa7cc0a000000b0055ef56f4575sm2281225edt.39.2024.01.30.01.38.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 01:38:29 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Andr=C3=A9?= =?utf-8?q?_Draszik?= Subject: [PATCH v2 5/6] clk: samsung: gs101: don't mark non-essential clocks as critical Date: Tue, 30 Jan 2024 09:36:44 +0000 Message-ID: <20240130093812.1746512-6-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240130093812.1746512-1-andre.draszik@linaro.org> References: <20240130093812.1746512-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The peric0_top1_ipclk_0 and peric0_top1_pclk_0 are the clocks going to peric0/uart_usi, with pclk being the bus clock. Without pclk running, any bus access will hang. Unfortunately, in commit d97b6c902a40 ("arm64: dts: exynos: gs101: update USI UART to use peric0 clocks") the gs101 DT ended up specifying an incorrect pclk in the respective node and instead the two clocks here were marked as critical. We have fixed the gs101 DT and can therefore drop this incorrect work-around here, the uart driver will claim these clocks as needed. Note that this commit has the side-effect of causing earlycon to stop to work sometime into the boot for two reasons: * peric0_top1_ipclk_0 requires its parent gout_cmu_peric0_ip to be running, but because earlycon doesn't deal with clocks that parent will be disabled when none of the other drivers that actually deal with clocks correctly require it to be running and the real serial driver (which does deal with clocks) hasn't taken over yet * hand-over between earlycon and serial driver appears to be fragile and clocks get enabled and disabled a few times, which also causes register access to hang while earlycon is still active Nonetheless we shouldn't keep these clocks running unconditionally just for earlycon. Clocks should be disabled where possible. If earlycon is required in the future, e.g. for debug, this commit can simply be reverted (locally!). Fixes: 893f133a040b ("clk: samsung: gs101: add support for cmu_peric0") Signed-off-by: André Draszik Reviewed-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- v2: * collect Reviewed-by: tags --- drivers/clk/samsung/clk-gs101.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c index 61bb0dcf84ee..5c338ac9231c 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -2982,20 +2982,18 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, 21, 0, 0), - /* Disabling this clock makes the system hang. Mark the clock as critical. */ GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0, "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, 21, 0, 0), - /* Disabling this clock makes the system hang. Mark the clock as critical. */ GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2, "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2,