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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D8.mail.protection.outlook.com (10.167.241.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7249.19 via Frontend Transport; Fri, 2 Feb 2024 08:56:17 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Fri, 2 Feb 2024 02:56:13 -0600 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v2 1/6] ACPI: CPPC: enable AMD CPPC V2 support for family 17h processors Date: Fri, 2 Feb 2024 16:55:33 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D8:EE_|SA1PR12MB6996:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b127a1a-c4cb-4db1-4920-08dc23ccd179 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CAT:NONE; SFS:(13230031)(4636009)(39860400002)(136003)(396003)(376002)(346002)(230922051799003)(230273577357003)(230173577357003)(64100799003)(1800799012)(451199024)(186009)(82310400011)(40470700004)(46966006)(36840700001)(41300700001)(336012)(40480700001)(40460700003)(36756003)(47076005)(426003)(7696005)(26005)(36860700001)(478600001)(83380400001)(16526019)(82740400003)(6666004)(356005)(81166007)(70586007)(2616005)(110136005)(966005)(2906002)(316002)(6636002)(70206006)(4326008)(54906003)(5660300002)(44832011)(86362001)(8676002)(8936002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2024 08:56:17.3361 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b127a1a-c4cb-4db1-4920-08dc23ccd179 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6996 As there are some AMD processors which only support CPPC V2 firmware and BIOS implementation, the amd_pstate driver will be failed to load when system booting with below kernel warning message: [ 0.477523] amd_pstate: the _CPC object is not present in SBIOS or ACPI disabled To make the amd_pstate driver can be loaded on those TR40 processors, it needs to match x86_model from 0x30 to 0x7F for family 17H. With the change, the system can load amd_pstate driver as expected. Reviewed-by: Mario Limonciello Reported-by: Gino Badouri Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218171 Fixes: fbd74d1689 ("ACPI: CPPC: Fix enabling CPPC on AMD systems with shared memory") Signed-off-by: Perry Yuan --- arch/x86/kernel/acpi/cppc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c index 8d8752b44f11..ff8f25faca3d 100644 --- a/arch/x86/kernel/acpi/cppc.c +++ b/arch/x86/kernel/acpi/cppc.c @@ -20,7 +20,7 @@ bool cpc_supported_by_cpu(void) (boot_cpu_data.x86_model >= 0x20 && boot_cpu_data.x86_model <= 0x2f))) return true; else if (boot_cpu_data.x86 == 0x17 && - boot_cpu_data.x86_model >= 0x70 && boot_cpu_data.x86_model <= 0x7f) + boot_cpu_data.x86_model >= 0x30 && boot_cpu_data.x86_model <= 0x7f) return true; return boot_cpu_has(X86_FEATURE_CPPC); } From patchwork Fri Feb 2 08:55:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 769737 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2056.outbound.protection.outlook.com [40.107.94.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4ADB860ED0; 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Fri, 2 Feb 2024 02:56:16 -0600 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v2 2/6] cpufreq:amd-pstate: fix the nominal freq value set Date: Fri, 2 Feb 2024 16:55:34 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9DC:EE_|PH7PR12MB8777:EE_ X-MS-Office365-Filtering-Correlation-Id: 92186082-0e4e-45ea-f248-08dc23ccd312 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jdAvmcxVUIoJhWXDkIkE+z37kj7ra/fFEKX+b49uL9aEXHgU91T27Efs0pIMNOKdUVuvOHl5a7NREgef7651driBDi283WTWLGBQKih+MUr01sObXAR1KlOVcogSDaQ2AWPpp/IsL7t13rIRm19Z2nSsAucUyndh+7B/w0ik6BPsFNer0NS+XgDtH0RE0YPPABF30uqvVtMSBtFDmMvYV7p2BqbqaYU798mM4MJRBTeK8E9vmOAi/9g0plpedjDIfOxcj8h1lzzZc3Pp/GWWGqLpFk3xqR9I34TOTqndNbVoXGF1yvVzDCD+aa/fAj4ay9/DU1Kn4CTVwCpO6VS+BPlAl2t1h7b23fzHjgWpc+6OYX6CFSBm9nevtvgpukMfaBqtavWgh+JOG3X6u/ChG0hcOfAR7r0dJ/WkSSK/ai8jXGtzc9nRg4b0AzU18dthdOEP2j94qsePt0abS4bSef7Oj5J2Hg7dihknVtI/iULwaFQ5/LAedyCZVXLthwxUIPeMYPHYZDCwTyoJsJ55M7NQD3G2DY7BCqA30BtD7EUPqWyOPAHhf74PKy/v/vGCu6rA6Wq5ZvZgC6IkDZSATytephB6jrQcqKrvTg3faqNTpZdslutjI/QYhIS4GP9TSu5d6T28e5dw/PyKTAv6vtL6X7sQYc2BBKo0nT/wnh0RuNDO2+H+BaFv9uLKwoB4PvqNLtNOdLbKPvilsJBTSU+pOhTfyMq1vnLKEs34FymnCFqyghUBPYTP1/479Sj9tLa107p6mH5uYXUy2uQLtg== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Cc: stable@vger.kernel.org Fixes: ec437d71db7 ("cpufreq: amd-pstate: Introduce a new AMD P-State driver to support future processors") Reviewed-by: Mario Limonciello Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 08e112444c27..ac7faa98a450 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -640,8 +640,7 @@ static int amd_get_nominal_freq(struct amd_cpudata *cpudata) if (ret) return ret; - /* Switch to khz */ - return cppc_perf.nominal_freq * 1000; + return cppc_perf.nominal_freq; } static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) From patchwork Fri Feb 2 08:55:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 769401 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2042.outbound.protection.outlook.com [40.107.237.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF62E612ED; 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Fri, 2 Feb 2024 02:56:19 -0600 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v2 3/6] cpufreq:amd-pstate: initialize nominal_freq of each cpudata Date: Fri, 2 Feb 2024 16:55:35 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D8:EE_|DS7PR12MB6069:EE_ X-MS-Office365-Filtering-Correlation-Id: 23727953-b87a-4618-a81e-08dc23ccd543 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qiqWOAG/tFEezFLW33IPkeDGxQtnJHIbzzlxaC12271EKNyI6NKchy6pBiIXGlsfgb8GU0GDN/DhLO01pPKs5nXddVm3e+eBCLoNCfIs8FkQJunOKmB6A7o+dQWr3f5Cr4CiBG8N4TeOPOqtsDwtUoLGRnGgYQ3urQ1s8VfvBDcr1J6ndB0EVbCF+jz9LkqYF2zdqaMS9csnyciMQ073Cb4lWwqn6C26BkdbvsueLEu7jeMP6F4q2jKogWrav1PRtdMtn5JJMEMc1Z71Q2H46gNsYG5q6/IP443jL4aV65uCx3e4X0kA0ETrnnOxwsmQYtyQcQ0JoVHXwI0dUM7cM4dzXRPwTJ668X1UYbWVGvwzpF7g2TdLuEw669RF/EBLTdVTB/i3+LLnCWfdDdpKB/+MY48PXzvnF2xpd2XNCcylLvXT/k0LMnszDvyZBX58e2yRdSQG7fnzu/ZKz/GXbHh02r4s/hfUDTeW5XiYcPnvwIHE1VefmGtwvRwF7PXlI65wNADLBpviQx8MmccVgZDgFxL7ZhVkYmW4/wBo14CDMsjbemNBz0KyYp3fdRGwkGmWt0cM8Lll5Uqs3o7+FrSalOgj/TvaqStnh6L146Yebhqk24AyPp81rqmIUdpzQ8EyAjiBJUJxJW/O5mRLkhoutppoiwsWMfp0Jbg2hmpLxeiNej+EJXiHAclyBMkXB3hVrNkW/CpMrLNBqeK2PaRdXatgF0nDxEKGMwmVy+2dIgs+XpwwgbFQ7ElAeUvDbpLDmjboWwyyEeW7yhq36Q== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6069 Optimizes the process of retrieving the nominal frequency by utilizing 'cpudata->nominal_freq' instead of repeatedly accessing the cppc_acpi interface. To enhance efficiency and reduce the CPU load, shifted to using 'cpudata->nominal_freq'. It allows for the nominal frequency to be accessed directly from the cached data in 'cpudata' of each CPU. It will also slightly reduce the frequency change latency while using pstate driver passive mode. Reviewed-by: Mario Limonciello Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index ac7faa98a450..ea8681ea3bad 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -619,7 +619,7 @@ static int amd_get_max_freq(struct amd_cpudata *cpudata) if (ret) return ret; - nominal_freq = cppc_perf.nominal_freq; + nominal_freq = READ_ONCE(cpudata->nominal_freq); nominal_perf = READ_ONCE(cpudata->nominal_perf); max_perf = READ_ONCE(cpudata->highest_perf); @@ -654,7 +654,7 @@ static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) if (ret) return ret; - nominal_freq = cppc_perf.nominal_freq; + nominal_freq = READ_ONCE(cpudata->nominal_freq); nominal_perf = READ_ONCE(cpudata->nominal_perf); lowest_nonlinear_perf = cppc_perf.lowest_nonlinear_perf; @@ -848,13 +848,14 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) goto free_cpudata1; min_freq = amd_get_min_freq(cpudata); - max_freq = amd_get_max_freq(cpudata); nominal_freq = amd_get_nominal_freq(cpudata); + cpudata->nominal_freq = nominal_freq; + max_freq = amd_get_max_freq(cpudata); lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata); - if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) { - dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n", - min_freq, max_freq); + if (min_freq < 0 || max_freq < 0 || min_freq > max_freq || nominal_freq == 0) { + dev_err(dev, "min_freq(%d) or max_freq(%d) or nominal_freq(%d) is incorrect\n", + min_freq, max_freq, nominal_freq); ret = -EINVAL; goto free_cpudata1; } @@ -893,7 +894,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) cpudata->min_freq = min_freq; cpudata->max_limit_freq = max_freq; cpudata->min_limit_freq = min_freq; - cpudata->nominal_freq = nominal_freq; cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq; policy->driver_data = cpudata; @@ -1310,12 +1310,13 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) goto free_cpudata1; min_freq = amd_get_min_freq(cpudata); - max_freq = amd_get_max_freq(cpudata); nominal_freq = amd_get_nominal_freq(cpudata); + cpudata->nominal_freq = nominal_freq; + max_freq = amd_get_max_freq(cpudata); lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata); - if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) { - dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n", - min_freq, max_freq); + if (min_freq < 0 || max_freq < 0 || min_freq > max_freq || nominal_freq == 0) { + dev_err(dev, "min_freq(%d) or max_freq(%d) or nominal_freq(%d) is incorrect\n", + min_freq, max_freq, nominal_freq); ret = -EINVAL; goto free_cpudata1; } @@ -1328,7 +1329,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) /* Initial processor data capability frequencies */ cpudata->max_freq = max_freq; cpudata->min_freq = min_freq; - cpudata->nominal_freq = nominal_freq; cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq; policy->driver_data = cpudata; From patchwork Fri Feb 2 08:55:36 2024 Content-Type: text/plain; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D9.mail.protection.outlook.com (10.167.241.77) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7249.19 via Frontend Transport; Fri, 2 Feb 2024 08:56:46 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Fri, 2 Feb 2024 02:56:23 -0600 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v2 4/6] cpufreq:amd-pstate: get pstate transition delay and latency value from ACPI tables Date: Fri, 2 Feb 2024 16:55:36 +0800 Message-ID: <4e21b25ed21e3718cade07d3f72eef1a96cd7135.1706863981.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D9:EE_|LV2PR12MB5824:EE_ X-MS-Office365-Filtering-Correlation-Id: 0e8dbd5f-1bd6-4740-0877-08dc23cce309 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2024 08:56:46.8150 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0e8dbd5f-1bd6-4740-0877-08dc23cce309 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5824 make pstate driver initially retrieve the P-state transition delay and latency values from the BIOS ACPI tables which has more reasonable delay and latency values according to the platform design and requirements. Previously there values were hardcoded at specific value which may have conflicted with platform and it might not reflect the most accurate or optimized setting for the processor. [054h 0084 8] Preserve Mask : FFFFFFFF00000000 [05Ch 0092 8] Write Mask : 0000000000000001 [064h 0100 4] Command Latency : 00000FA0 [068h 0104 4] Maximum Access Rate : 0000EA60 [06Ch 0108 2] Minimum Turnaround Time : 0000 Reviewed-by: Mario Limonciello Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index ea8681ea3bad..77effc3caf6c 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -820,6 +820,36 @@ static void amd_pstate_update_limits(unsigned int cpu) mutex_unlock(&amd_pstate_driver_lock); } +/** + * Get pstate transition delay time from ACPI tables that firmware set + * instead of using hardcode value directly. + */ +static u32 amd_pstate_get_transition_delay_us(unsigned int cpu) +{ + u32 transition_delay_ns; + + transition_delay_ns = cppc_get_transition_latency(cpu); + if (transition_delay_ns == CPUFREQ_ETERNAL) + return AMD_PSTATE_TRANSITION_DELAY; + + return transition_delay_ns / NSEC_PER_USEC; +} + +/** + * Get pstate transition latency value from ACPI tables that firmware set + * instead of using hardcode value directly. + */ +static u32 amd_pstate_get_transition_latency(unsigned int cpu) +{ + u32 transition_latency; + + transition_latency = cppc_get_transition_latency(cpu); + if (transition_latency == CPUFREQ_ETERNAL) + return AMD_PSTATE_TRANSITION_LATENCY; + + return transition_latency; +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -860,8 +890,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) goto free_cpudata1; } - policy->cpuinfo.transition_latency = AMD_PSTATE_TRANSITION_LATENCY; - policy->transition_delay_us = AMD_PSTATE_TRANSITION_DELAY; + policy->cpuinfo.transition_latency = amd_pstate_get_transition_latency(policy->cpu); + policy->transition_delay_us = amd_pstate_get_transition_delay_us(policy->cpu); policy->min = min_freq; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2024 08:56:49.7865 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 84c63592-7b17-4050-71b8-08dc23cce4ce X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6289 to be more clear what is wrong with CPPC when pstate driver failed to load which has dependency on the CPPC capabilities. Add one more debug message to notify user if CPPC is not supported by the CPU, then it will be easy to find out what need to fix for pstate driver loading issue. [ 0.477523] amd_pstate: the _CPC object is not present in SBIOS or ACPI disabled Above message is not clear enough to verify whether CPPC is not supported. Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello --- drivers/acpi/cppc_acpi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index a50e70abdf19..e23a84f4a50a 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -679,8 +679,10 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr) if (!osc_sb_cppc2_support_acked) { pr_debug("CPPC v2 _OSC not acked\n"); - if (!cpc_supported_by_cpu()) + if (!cpc_supported_by_cpu()) { + pr_debug("CPPC is not supported by the CPU\n"); return -ENODEV; + } } /* Parse the ACPI _CPC table for this CPU. */ From patchwork Fri Feb 2 08:55:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 769735 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2084.outbound.protection.outlook.com [40.107.243.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1125657B1; 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Fri, 2 Feb 2024 02:56:49 -0600 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v2 6/6] cpufreq:amd-pstate: add quirk for the pstate CPPC capabilities missing Date: Fri, 2 Feb 2024 16:55:38 +0800 Message-ID: <8a55135d10cfc906616d3cd4530f9aac487c5034.1706863981.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D6:EE_|DS0PR12MB8788:EE_ X-MS-Office365-Filtering-Correlation-Id: eb53f080-838f-4a73-966b-08dc23cce6bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fQv1Jme2ylK3lkuX8U4V7fZgftaSSmoGQIpa1NVTCz8Ay1xq7aB6/31zuTY+tTdDfh7wtvu94ciRSLbsKUQrOL7gYm/evJNLQoOLeU1JT/fq36JlZpBE5/rPn+N0OFkHNt7bjq7naaQtJm6G7iekMpiA6FU5iM/frfwJnhEmKA0P4sCFsZcjUs/I4gdYUkYPLY2Nm/7SjG8zVLX3O3XzfcX9EQNdVJY2GIPA5xaUqmOH8qcSKVNrEJLVZd6XWSvOVFpHaFCkuuSJzsQf68+41PDfVPworCnGvmp7oClLkIzdMxUK9mCmhpkbJfkzhyqYtXwD5zY3pLuJl3WgC1FQdnvUapowl5kCTRFZxA7FFKx2jySDfO2vERZDMWrr46Auqhif5FM4V3A2seWyXxPE4Uu8O32niv4vdw+yg/25sASDOG6hLda0ccNVP4+pYU0G74BvTuz6Aq3QXvNqDrnO/PHF+/PoFFnAGIAMS92hBtKCLiwL2Rqeekk+YshYHkA1gczDMoWt+TqaMv74Wxee63DRhiiRcOSWA4vhSyVX82yqUAFEe5sJL0bXCPyXKUh6ybH0zbhEcsIkaJ2ZrDxmgm5ZVZnFjWNIJC2Fl389bAP9q2i0QzUIzmJlbPQ3Vz3qzMUoBuUVGf8NvqIhj+Z3PBH7sHBwqv6yf9SH/MTfYmxmLYN91ShlnXhQbrU8fpOCcX4WYSwnbtXgBvyhqcj9kYXcJmQlfVjLEWi8HhaJxSbJd+xD03mVBNXOq9vaNCh/bBoMvh1qJYRS90u2JVDp1A== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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If CPPC capabilities are not defined in the ACPI tables or wrongly defined by platform firmware, it needs to use quick to get those issues fixed with correct workaround values to make pstate driver can be loaded even though there are CPPC capabilities errors. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 49 ++++++++++++++++++++++++++++++++++-- include/linux/amd-pstate.h | 6 +++++ 2 files changed, 53 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 77effc3caf6c..4d426516abb9 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -67,6 +67,7 @@ static struct cpufreq_driver amd_pstate_epp_driver; static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; static bool amd_pstate_prefcore = true; +static struct quirk_entry *quirks; /* * AMD Energy Preference Performance (EPP) @@ -111,6 +112,33 @@ static unsigned int epp_values[] = { typedef int (*cppc_mode_transition_fn)(int); +static struct quirk_entry quirk_amd_7k62 = { + .nominal_freq = 2600, + .lowest_freq = 550, +}; + +static int __init dmi_matched(const struct dmi_system_id *dmi) +{ + quirks = dmi->driver_data; + pr_info("hardware type %s found\n", dmi->ident); + + return 1; +} + +static const struct dmi_system_id amd_pstate_quirks_table[] __initconst = { + { + .callback = dmi_matched, + .ident = "AMD EPYC 7K62", + .matches = { + DMI_MATCH(DMI_PRODUCT_VERSION, "C1"), + DMI_MATCH(DMI_PRODUCT_SERIAL, "FX19911000028"), + }, + .driver_data = &quirk_amd_7k62, + }, + {} +}; +MODULE_DEVICE_TABLE(dmi, amd_pstate_quirks_table); + static inline int get_mode_idx_from_str(const char *str, size_t size) { int i; @@ -600,13 +628,19 @@ static void amd_pstate_adjust_perf(unsigned int cpu, static int amd_get_min_freq(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; + u32 lowest_freq; int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); if (ret) return ret; + if (quirks && quirks->lowest_freq) + lowest_freq = quirks->lowest_freq; + else + lowest_freq = cppc_perf.lowest_freq; + /* Switch to khz */ - return cppc_perf.lowest_freq * 1000; + return lowest_freq * 1000; } static int amd_get_max_freq(struct amd_cpudata *cpudata) @@ -635,12 +669,18 @@ static int amd_get_max_freq(struct amd_cpudata *cpudata) static int amd_get_nominal_freq(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; + u32 nominal_freq; int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); if (ret) return ret; - return cppc_perf.nominal_freq; + if (quirks && quirks->nominal_freq) + nominal_freq = quirks->nominal_freq; + else + nominal_freq = cppc_perf.nominal_freq; + + return nominal_freq; } static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) @@ -1672,6 +1712,11 @@ static int __init amd_pstate_init(void) if (cpufreq_get_current_driver()) return -EEXIST; + quirks = NULL; + + /* check if this machine need CPPC quirks */ + dmi_check_system(amd_pstate_quirks_table); + switch (cppc_state) { case AMD_PSTATE_UNDEFINED: /* Disable on the following configs by default: diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index d21838835abd..7b2cbb892fd9 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -124,4 +124,10 @@ static const char * const amd_pstate_mode_string[] = { [AMD_PSTATE_GUIDED] = "guided", NULL, }; + +struct quirk_entry { + u32 nominal_freq; + u32 lowest_freq; +}; + #endif /* _LINUX_AMD_PSTATE_H */