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[209.51.188.17]) by mx.google.com with ESMTPS id kl21-20020a056214519500b0068fff085436si7566919qvb.340.2024.03.12.05.51.27 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:51:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=UPUIYInU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1VR-00054E-Mb; Tue, 12 Mar 2024 08:45:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VA-0004S8-EC for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:05 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1V3-0000Wh-Lq for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:04 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247495; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fVeQ/voPOLaHDifKQwHSPz/5PRJECd4+4KbN1orGcY0=; b=UPUIYInUbfngIOaMmOTRI3bplqmUkUUrLxWB01ehjG+/sChv1z+3nlyrn9sJxYZmY4jbEQ sTyeymrEI1b3B3+kur07WE16pWhziVsiS9eSw097fJJ8+0SqMqammm+A86tVTnBDpI4Su6 opPWEs51mwVzl9okwEWKgotfvaTHWC8= Received: from mimecast-mx02.redhat.com (mx-ext.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-512-uAfL0bO8OqiZ0GRkWU1U3g-1; Tue, 12 Mar 2024 08:44:50 -0400 X-MC-Unique: uAfL0bO8OqiZ0GRkWU1U3g-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 213011C41A19; Tue, 12 Mar 2024 12:44:50 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id 638C0492BC4; Tue, 12 Mar 2024 12:44:48 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Zhao Liu , Fabiano Rosas , Anthony PERARD Subject: [PULL 34/55] bulk: Access existing variables initialized to &S->F when available Date: Tue, 12 Mar 2024 13:43:18 +0100 Message-ID: <20240312124339.761630-35-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé When a variable is initialized to &struct->field, use it in place. Rationale: while this makes the code more concise, this also helps static analyzers. Mechanical change using the following Coccinelle spatch script: @@ type S, F; identifier s, m, v; @@ S *s; ... F *v = &s->m; <+... - &s->m + v ...+> Inspired-by: Zhao Liu Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20240129164514.73104-2-philmd@linaro.org> Acked-by: Fabiano Rosas Reviewed-by: Zhao Liu Reviewed-by: Anthony PERARD [thuth: Dropped hunks that need a rebase, and fixed sizeof() in pmu_realize()] Signed-off-by: Thomas Huth --- hw/display/ati.c | 2 +- hw/misc/macio/pmu.c | 3 +-- hw/misc/pvpanic-pci.c | 2 +- hw/pci-bridge/cxl_root_port.c | 2 +- hw/ppc/pnv.c | 20 ++++++++++---------- hw/virtio/vhost-user-scmi.c | 6 +++--- hw/virtio/virtio-pci.c | 2 +- hw/xen/xen_pt.c | 6 +++--- migration/multifd-zlib.c | 2 +- target/arm/cpu.c | 4 ++-- target/arm/kvm.c | 2 +- target/arm/machine.c | 6 +++--- target/i386/hvf/x86hvf.c | 2 +- target/m68k/helper.c | 2 +- target/ppc/kvm.c | 8 ++++---- 15 files changed, 34 insertions(+), 35 deletions(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index 569b8f6165..8d2501bd82 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -991,7 +991,7 @@ static void ati_vga_realize(PCIDevice *dev, Error **errp) } vga_init(vga, OBJECT(s), pci_address_space(dev), pci_address_space_io(dev), true); - vga->con = graphic_console_init(DEVICE(s), 0, s->vga.hw_ops, &s->vga); + vga->con = graphic_console_init(DEVICE(s), 0, s->vga.hw_ops, vga); if (s->cursor_guest_mode) { vga->cursor_invalidate = ati_cursor_invalidate; vga->cursor_draw_line = ati_cursor_draw_line; diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c index e9a90da88f..e40c51bf52 100644 --- a/hw/misc/macio/pmu.c +++ b/hw/misc/macio/pmu.c @@ -737,8 +737,7 @@ static void pmu_realize(DeviceState *dev, Error **errp) timer_mod(s->one_sec_timer, s->one_sec_target); if (s->has_adb) { - qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, - dev, "adb.0"); + qbus_init(adb_bus, sizeof(*adb_bus), TYPE_ADB_BUS, dev, "adb.0"); adb_register_autopoll_callback(adb_bus, pmu_adb_poll, s); } } diff --git a/hw/misc/pvpanic-pci.c b/hw/misc/pvpanic-pci.c index c01e4ce864..83be95d0d2 100644 --- a/hw/misc/pvpanic-pci.c +++ b/hw/misc/pvpanic-pci.c @@ -48,7 +48,7 @@ static void pvpanic_pci_realizefn(PCIDevice *dev, Error **errp) PVPanicPCIState *s = PVPANIC_PCI_DEVICE(dev); PVPanicState *ps = &s->pvpanic; - pvpanic_setup_io(&s->pvpanic, DEVICE(s), 2); + pvpanic_setup_io(ps, DEVICE(s), 2); pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &ps->mr); } diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 62f96994eb..8a30da602c 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -175,7 +175,7 @@ static void cxl_rp_realize(DeviceState *dev, Error **errp) cxl_cstate->dvsec_offset = CXL_ROOT_PORT_DVSEC_OFFSET; cxl_cstate->pdev = pci_dev; - build_dvsecs(&crp->cxl_cstate); + build_dvsecs(cxl_cstate); cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate, TYPE_CXL_ROOT_PORT); diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0b47b92baa..93d550988f 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1265,11 +1265,11 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) } /* Processor Service Interface (PSI) Host Bridge */ - object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), + object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), &error_fatal); - object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, + object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, OBJECT(chip8->xics), &error_abort); - if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { + if (!qdev_realize(DEVICE(psi8), NULL, errp)) { return; } pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, @@ -1300,7 +1300,7 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) } pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, - qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC)); + qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); /* OCC SRAM model */ memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), @@ -1553,12 +1553,12 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) &chip9->xive.xscom_regs); /* Processor Service Interface (PSI) Host Bridge */ - object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), + object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), &error_fatal); /* This is the only device with 4k ESB pages */ - object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K, + object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, &error_fatal); - if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { + if (!qdev_realize(DEVICE(psi9), NULL, errp)) { return; } pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, @@ -1594,7 +1594,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) } pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( - DEVICE(&chip9->psi), PSIHB9_IRQ_OCC)); + DEVICE(psi9), PSIHB9_IRQ_OCC)); /* OCC SRAM model */ memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), @@ -1609,7 +1609,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, &chip9->sbe.xscom_mbox_regs); qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( - DEVICE(&chip9->psi), PSIHB9_IRQ_PSU)); + DEVICE(psi9), PSIHB9_IRQ_PSU)); /* HOMER */ object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), @@ -1650,7 +1650,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) PNV9_XSCOM_I2CM_SIZE, &chip9->i2c[i].xscom_regs); qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, - qdev_get_gpio_in(DEVICE(&chip9->psi), + qdev_get_gpio_in(DEVICE(psi9), PSIHB9_IRQ_SBE_I2C)); } } diff --git a/hw/virtio/vhost-user-scmi.c b/hw/virtio/vhost-user-scmi.c index 918bb7dcf7..300847e672 100644 --- a/hw/virtio/vhost-user-scmi.c +++ b/hw/virtio/vhost-user-scmi.c @@ -56,9 +56,9 @@ static int vu_scmi_start(VirtIODevice *vdev) goto err_host_notifiers; } - vhost_ack_features(&scmi->vhost_dev, feature_bits, vdev->guest_features); + vhost_ack_features(vhost_dev, feature_bits, vdev->guest_features); - ret = vhost_dev_start(&scmi->vhost_dev, vdev, true); + ret = vhost_dev_start(vhost_dev, vdev, true); if (ret < 0) { error_report("Error starting vhost-user-scmi: %d", ret); goto err_guest_notifiers; @@ -71,7 +71,7 @@ static int vu_scmi_start(VirtIODevice *vdev) * enabling/disabling irqfd. */ for (i = 0; i < scmi->vhost_dev.nvqs; i++) { - vhost_virtqueue_mask(&scmi->vhost_dev, vdev, i, false); + vhost_virtqueue_mask(vhost_dev, vdev, i, false); } return 0; diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 1a7039fb0c..cb6940fc0e 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1929,7 +1929,7 @@ static void virtio_pci_device_plugged(DeviceState *d, Error **errp) bool modern_pio = proxy->flags & VIRTIO_PCI_FLAG_MODERN_PIO_NOTIFY; uint8_t *config; uint32_t size; - VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); + VirtIODevice *vdev = virtio_bus_get_device(bus); /* * Virtio capabilities present without diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c index a8edabdabc..3635d1b39f 100644 --- a/hw/xen/xen_pt.c +++ b/hw/xen/xen_pt.c @@ -711,7 +711,7 @@ static void xen_pt_destroy(PCIDevice *d) { uint8_t intx; int rc; - if (machine_irq && !xen_host_pci_device_closed(&s->real_device)) { + if (machine_irq && !xen_host_pci_device_closed(host_dev)) { intx = xen_pt_pci_intx(s); rc = xc_domain_unbind_pt_irq(xen_xc, xen_domid, machine_irq, PT_IRQ_TYPE_PCI, @@ -760,8 +760,8 @@ static void xen_pt_destroy(PCIDevice *d) { memory_listener_unregister(&s->io_listener); s->listener_set = false; } - if (!xen_host_pci_device_closed(&s->real_device)) { - xen_host_pci_device_put(&s->real_device); + if (!xen_host_pci_device_closed(host_dev)) { + xen_host_pci_device_put(host_dev); } } /* init */ diff --git a/migration/multifd-zlib.c b/migration/multifd-zlib.c index 6120faad65..9a3a7adb54 100644 --- a/migration/multifd-zlib.c +++ b/migration/multifd-zlib.c @@ -75,7 +75,7 @@ static int zlib_send_setup(MultiFDSendParams *p, Error **errp) err_free_zbuff: g_free(z->zbuff); err_deflate_end: - deflateEnd(&z->zs); + deflateEnd(zs); err_free_z: g_free(z); error_setg(errp, "multifd %u: %s", p->id, err_msg); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f3ed79cef2..02fc0adb65 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2095,7 +2095,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) * We rely on no XScale CPU having VFP so we can use the same bits in the * TB flags field for VECSTRIDE and XSCALE_CPAR. */ - assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || + assert(arm_feature(env, ARM_FEATURE_AARCH64) || !cpu_isar_feature(aa32_vfp_simd, cpu) || !arm_feature(env, ARM_FEATURE_XSCALE)); @@ -2145,7 +2145,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) } if (cpu->cfgend) { - if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { + if (arm_feature(env, ARM_FEATURE_V7)) { cpu->reset_sctlr |= SCTLR_EE; } else { cpu->reset_sctlr |= SCTLR_B; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 81813030a5..ab85d628a8 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1888,7 +1888,7 @@ int kvm_arch_init_vcpu(CPUState *cs) cpu->psci_version = QEMU_PSCI_VERSION_0_2; cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2; } - if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + if (!arm_feature(env, ARM_FEATURE_AARCH64)) { cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT; } if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) { diff --git a/target/arm/machine.c b/target/arm/machine.c index 9d7dbaea54..b2b39b2475 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -773,7 +773,7 @@ static int cpu_pre_load(void *opaque) env->irq_line_state = UINT32_MAX; if (!kvm_enabled()) { - pmu_op_start(&cpu->env); + pmu_op_start(env); } return 0; @@ -871,11 +871,11 @@ static int cpu_post_load(void *opaque, int version_id) } if (!kvm_enabled()) { - pmu_op_finish(&cpu->env); + pmu_op_finish(env); } if (tcg_enabled()) { - arm_rebuild_hflags(&cpu->env); + arm_rebuild_hflags(env); } return 0; diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index 3b1ef5f49a..be2c46246e 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -408,7 +408,7 @@ bool hvf_inject_interrupts(CPUState *cs) if (!(env->hflags & HF_INHIBIT_IRQ_MASK) && (cs->interrupt_request & CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK) && !(info & VMCS_INTR_VALID)) { - int line = cpu_get_pic_interrupt(&x86cpu->env); + int line = cpu_get_pic_interrupt(env); cs->interrupt_request &= ~CPU_INTERRUPT_HARD; if (line >= 0) { wvmcs(cs->accel->fd, VMCS_ENTRY_INTR_INFO, line | diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 1c33995e5d..44b245884e 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -984,7 +984,7 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, access_type |= ACCESS_SUPER; } - ret = get_physical_address(&cpu->env, &physical, &prot, + ret = get_physical_address(env, &physical, &prot, address, access_type, &page_size); if (likely(ret == 0)) { tlb_set_page(cs, address & TARGET_PAGE_MASK, diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index bcf30a5400..9f5a890655 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -635,8 +635,8 @@ static int kvm_put_fp(CPUState *cs) for (i = 0; i < 32; i++) { uint64_t vsr[2]; - uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); - uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); + uint64_t *fpr = cpu_fpr_ptr(env, i); + uint64_t *vsrl = cpu_vsrl_ptr(env, i); #if HOST_BIG_ENDIAN vsr[0] = float64_val(*fpr); @@ -704,8 +704,8 @@ static int kvm_get_fp(CPUState *cs) for (i = 0; i < 32; i++) { uint64_t vsr[2]; - uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); - uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); + uint64_t *fpr = cpu_fpr_ptr(env, i); + uint64_t *vsrl = cpu_vsrl_ptr(env, i); reg.addr = (uintptr_t) &vsr; reg.id = vsx ? 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[209.51.188.17]) by mx.google.com with ESMTPS id pt8-20020a056214048800b00690c5d87bd3si6487668qvb.524.2024.03.12.05.49.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:49:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=VwOH2fgN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1VV-0005Kp-Gp; Tue, 12 Mar 2024 08:45:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1V5-0004Nb-5f for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:01 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1V2-0000WV-D0 for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:44:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247493; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=l3iSAaDIIb1P5g2SBo9zDd7kQqe+DZKNANJ8NYQpZpE=; b=VwOH2fgNunfHWdNS4H+MbUgVUzgoFmors5xxIYhfxx3yqfIprL826AEo78CxFAyA/+smhB /iGfEW++P4AzrVLZSSXnUOxRVTCmJEf8XOGuooLUaoTwU8fQrxOZt0ATBoXM3v3c6PCZ8m HAner5cPOSC2U/fCexS/5dx8GCqoDgg= Received: from mimecast-mx02.redhat.com (mx-ext.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-651-zATo4KJCM0KKwVMsX1D2EQ-1; Tue, 12 Mar 2024 08:44:51 -0400 X-MC-Unique: zATo4KJCM0KKwVMsX1D2EQ-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 20EF91C41A0D; Tue, 12 Mar 2024 12:44:51 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id 635E2492BC4; Tue, 12 Mar 2024 12:44:50 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= Subject: [PULL 35/55] hw/core: Declare CPUArchId::cpu as CPUState instead of Object Date: Tue, 12 Mar 2024 13:43:19 +0100 Message-ID: <20240312124339.761630-36-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Do not accept any Object for CPUArchId::cpu field, restrict it to CPUState type. Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20240129164514.73104-3-philmd@linaro.org> Reviewed-by: Thomas Huth Signed-off-by: Thomas Huth --- include/hw/boards.h | 2 +- hw/core/machine.c | 4 ++-- hw/i386/x86.c | 2 +- hw/loongarch/virt.c | 2 +- hw/ppc/spapr.c | 5 ++--- hw/s390x/s390-virtio-ccw.c | 2 +- 6 files changed, 8 insertions(+), 9 deletions(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index bcfde8a84d..8b8f6d5c00 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -120,7 +120,7 @@ typedef struct CPUArchId { uint64_t arch_id; int64_t vcpus_count; CpuInstanceProperties props; - Object *cpu; + CPUState *cpu; const char *type; } CPUArchId; diff --git a/hw/core/machine.c b/hw/core/machine.c index 9ac5d5389a..024bf34f54 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -716,7 +716,7 @@ HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine) mc->possible_cpu_arch_ids(machine); for (i = 0; i < machine->possible_cpus->len; i++) { - Object *cpu; + CPUState *cpu; HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type); @@ -726,7 +726,7 @@ HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine) cpu = machine->possible_cpus->cpus[i].cpu; if (cpu) { - cpu_item->qom_path = object_get_canonical_path(cpu); + cpu_item->qom_path = object_get_canonical_path(OBJECT(cpu)); } QAPI_LIST_PREPEND(head, cpu_item); } diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 807e09bcdb..ffbda48917 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -225,7 +225,7 @@ void x86_cpu_plug(HotplugHandler *hotplug_dev, } found_cpu = x86_find_cpu_slot(MACHINE(x86ms), cpu->apic_id, NULL); - found_cpu->cpu = OBJECT(dev); + found_cpu->cpu = CPU(dev); out: error_propagate(errp, local_err); } diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 1e98d8bda5..efce112310 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -858,7 +858,7 @@ static void loongarch_init(MachineState *machine) for (i = 0; i < possible_cpus->len; i++) { cpu = cpu_create(machine->cpu_type); cpu->cpu_index = i; - machine->possible_cpus->cpus[i].cpu = OBJECT(cpu); + machine->possible_cpus->cpus[i].cpu = cpu; lacpu = LOONGARCH_CPU(cpu); lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id; } diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 55263f0815..f8980b62ec 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3979,7 +3979,6 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); CPUCore *cc = CPU_CORE(dev); - CPUState *cs; SpaprDrc *drc; CPUArchId *core_slot; int index; @@ -4013,7 +4012,7 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) } } - core_slot->cpu = OBJECT(dev); + core_slot->cpu = CPU(dev); /* * Set compatibility mode to match the boot CPU, which was either set @@ -4029,7 +4028,7 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) if (smc->pre_2_10_has_unused_icps) { for (i = 0; i < cc->nr_threads; i++) { - cs = CPU(core->threads[i]); + CPUState *cs = CPU(core->threads[i]); pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); } } diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 4b6aab8eef..b1dcb3857f 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -317,7 +317,7 @@ static void s390_cpu_plug(HotplugHandler *hotplug_dev, S390CPU *cpu = S390_CPU(dev); g_assert(!ms->possible_cpus->cpus[cpu->env.core_id].cpu); - ms->possible_cpus->cpus[cpu->env.core_id].cpu = OBJECT(dev); + ms->possible_cpus->cpus[cpu->env.core_id].cpu = CPU(dev); if (s390_has_topology()) { s390_topology_setup_cpu(ms, cpu, errp); From patchwork Tue Mar 12 12:43:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 779724 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2003485wrt; Tue, 12 Mar 2024 05:57:50 -0700 (PDT) X-Forwarded-Encrypted: i=2; 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[209.51.188.17]) by mx.google.com with ESMTPS id bj12-20020a05620a190c00b007882e4e7f46si7917879qkb.263.2024.03.12.05.57.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:57:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b="YiWB/H5j"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1Wj-0006wL-2Q; Tue, 12 Mar 2024 08:46:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VK-0004eO-7A for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:16 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1V4-0000Wo-VN for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:13 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247495; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=96tWQBOQ6hzkT9ZCC1lhsflVD2DlkF3bSvTLzkWacO0=; b=YiWB/H5jnkknN7ftTxIv6JoMF0n+kN7vEwesVm3d7eydUwPGugXL3rPlQFYawcQcqpZIcB pQa/k54ZXQm/lnxGtPPtsLjKdwnHOtI+rj38SU4tItHbywyDzYHO0K1VCHhYHAKmlD1qHI jwGde6kT+eDVXDPUaTc9Pg3C5/MJ8wo= Received: from mimecast-mx02.redhat.com (mx-ext.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-443-qXcBDlL0Mm-bfhiZkcv0Ww-1; Tue, 12 Mar 2024 08:44:52 -0400 X-MC-Unique: qXcBDlL0Mm-bfhiZkcv0Ww-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 57D643C0F187; Tue, 12 Mar 2024 12:44:52 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id 63650492BC4; Tue, 12 Mar 2024 12:44:51 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Richard Henderson Subject: [PULL 36/55] bulk: Call in place single use cpu_env() Date: Tue, 12 Mar 2024 13:43:20 +0100 Message-ID: <20240312124339.761630-37-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Avoid CPUArchState local variable when cpu_env() is used once. Mechanical patch using the following Coccinelle spatch script: @@ type CPUArchState; identifier env; expression cs; @@ { - CPUArchState *env = cpu_env(cs); ... when != env - env + cpu_env(cs) ... when != env } Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-ID: <20240129164514.73104-5-philmd@linaro.org> Signed-off-by: Thomas Huth --- accel/tcg/cpu-exec.c | 3 +-- linux-user/i386/cpu_loop.c | 4 ++-- target/hppa/mem_helper.c | 3 +-- target/hppa/translate.c | 3 +-- target/i386/nvmm/nvmm-all.c | 6 ++---- target/i386/whpx/whpx-all.c | 18 ++++++------------ target/loongarch/tcg/translate.c | 3 +-- target/rx/translate.c | 3 +-- target/sh4/op_helper.c | 4 +--- 9 files changed, 16 insertions(+), 31 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 52239a441f..5c70748060 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -436,7 +436,6 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) static inline TranslationBlock * QEMU_DISABLE_CFI cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) { - CPUArchState *env = cpu_env(cpu); uintptr_t ret; TranslationBlock *last_tb; const void *tb_ptr = itb->tc.ptr; @@ -446,7 +445,7 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) } qemu_thread_jit_execute(); - ret = tcg_qemu_tb_exec(env, tb_ptr); + ret = tcg_qemu_tb_exec(cpu_env(cpu), tb_ptr); cpu->neg.can_do_io = true; qemu_plugin_disable_mem_helpers(cpu); /* diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index 42ecb4bf0a..92beb6830c 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -323,8 +323,8 @@ void cpu_loop(CPUX86State *env) static void target_cpu_free(void *obj) { - CPUArchState *env = cpu_env(obj); - target_munmap(env->gdt.base, sizeof(uint64_t) * TARGET_GDT_ENTRIES); + target_munmap(cpu_env(obj)->gdt.base, + sizeof(uint64_t) * TARGET_GDT_ENTRIES); g_free(obj); } diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 3fc895c1c2..80f51e753f 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -538,7 +538,6 @@ void HELPER(iitlbt_pa20)(CPUHPPAState *env, target_ulong r1, target_ulong r2) /* Purge (Insn/Data) TLB. */ static void ptlb_work(CPUState *cpu, run_on_cpu_data data) { - CPUHPPAState *env = cpu_env(cpu); vaddr start = data.target_ptr; vaddr end; @@ -552,7 +551,7 @@ static void ptlb_work(CPUState *cpu, run_on_cpu_data data) end = (vaddr)TARGET_PAGE_SIZE << (2 * end); end = start + end - 1; - hppa_flush_tlb_range(env, start, end); + hppa_flush_tlb_range(cpu_env(cpu), start, end); } /* This is local to the current cpu. */ diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 01f3188656..eb2046c5ad 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3811,8 +3811,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) #ifndef CONFIG_USER_ONLY if (ctx->tb_flags & PSW_C) { - CPUHPPAState *env = cpu_env(ctx->cs); - int type = hppa_artype_for_page(env, ctx->base.pc_next); + int type = hppa_artype_for_page(cpu_env(ctx->cs), ctx->base.pc_next); /* If we could not find a TLB entry, then we need to generate an ITLB miss exception so the kernel will provide it. The resulting TLB fill operation will invalidate this TB and diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index cfdca91123..49a3a3b916 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -340,7 +340,6 @@ nvmm_get_registers(CPUState *cpu) static bool nvmm_can_take_int(CPUState *cpu) { - CPUX86State *env = cpu_env(cpu); AccelCPUState *qcpu = cpu->accel; struct nvmm_vcpu *vcpu = &qcpu->vcpu; struct nvmm_machine *mach = get_nvmm_mach(); @@ -349,7 +348,7 @@ nvmm_can_take_int(CPUState *cpu) return false; } - if (qcpu->int_shadow || !(env->eflags & IF_MASK)) { + if (qcpu->int_shadow || !(cpu_env(cpu)->eflags & IF_MASK)) { struct nvmm_x64_state *state = vcpu->state; /* Exit on interrupt window. */ @@ -645,13 +644,12 @@ static int nvmm_handle_halted(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - CPUX86State *env = cpu_env(cpu); int ret = 0; bql_lock(); if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && - (env->eflags & IF_MASK)) && + (cpu_env(cpu)->eflags & IF_MASK)) && !(cpu->interrupt_request & CPU_INTERRUPT_NMI)) { cpu->exception_index = EXCP_HLT; cpu->halted = true; diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index a7262654ac..31eec7048c 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -300,7 +300,6 @@ static SegmentCache whpx_seg_h2q(const WHV_X64_SEGMENT_REGISTER *hs) /* X64 Extended Control Registers */ static void whpx_set_xcrs(CPUState *cpu) { - CPUX86State *env = cpu_env(cpu); HRESULT hr; struct whpx_state *whpx = &whpx_global; WHV_REGISTER_VALUE xcr0; @@ -311,7 +310,7 @@ static void whpx_set_xcrs(CPUState *cpu) } /* Only xcr0 is supported by the hypervisor currently */ - xcr0.Reg64 = env->xcr0; + xcr0.Reg64 = cpu_env(cpu)->xcr0; hr = whp_dispatch.WHvSetVirtualProcessorRegisters( whpx->partition, cpu->cpu_index, &xcr0_name, 1, &xcr0); if (FAILED(hr)) { @@ -321,7 +320,6 @@ static void whpx_set_xcrs(CPUState *cpu) static int whpx_set_tsc(CPUState *cpu) { - CPUX86State *env = cpu_env(cpu); WHV_REGISTER_NAME tsc_reg = WHvX64RegisterTsc; WHV_REGISTER_VALUE tsc_val; HRESULT hr; @@ -345,7 +343,7 @@ static int whpx_set_tsc(CPUState *cpu) } } - tsc_val.Reg64 = env->tsc; + tsc_val.Reg64 = cpu_env(cpu)->tsc; hr = whp_dispatch.WHvSetVirtualProcessorRegisters( whpx->partition, cpu->cpu_index, &tsc_reg, 1, &tsc_val); if (FAILED(hr)) { @@ -556,7 +554,6 @@ static void whpx_set_registers(CPUState *cpu, int level) static int whpx_get_tsc(CPUState *cpu) { - CPUX86State *env = cpu_env(cpu); WHV_REGISTER_NAME tsc_reg = WHvX64RegisterTsc; WHV_REGISTER_VALUE tsc_val; HRESULT hr; @@ -569,14 +566,13 @@ static int whpx_get_tsc(CPUState *cpu) return -1; } - env->tsc = tsc_val.Reg64; + cpu_env(cpu)->tsc = tsc_val.Reg64; return 0; } /* X64 Extended Control Registers */ static void whpx_get_xcrs(CPUState *cpu) { - CPUX86State *env = cpu_env(cpu); HRESULT hr; struct whpx_state *whpx = &whpx_global; WHV_REGISTER_VALUE xcr0; @@ -594,7 +590,7 @@ static void whpx_get_xcrs(CPUState *cpu) return; } - env->xcr0 = xcr0.Reg64; + cpu_env(cpu)->xcr0 = xcr0.Reg64; } static void whpx_get_registers(CPUState *cpu) @@ -1400,8 +1396,7 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exit_context_valid) { if (cpu->vcpu_dirty) { /* The CPU registers have been modified by other parts of QEMU. */ - CPUArchState *env = cpu_env(cpu); - return env->eip; + return cpu_env(cpu)->eip; } else if (exit_context_valid) { /* * The CPU registers have not been modified by neither other parts @@ -1439,12 +1434,11 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exit_context_valid) static int whpx_handle_halt(CPUState *cpu) { - CPUX86State *env = cpu_env(cpu); int ret = 0; bql_lock(); if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && - (env->eflags & IF_MASK)) && + (cpu_env(cpu)->eflags & IF_MASK)) && !(cpu->interrupt_request & CPU_INTERRUPT_NMI)) { cpu->exception_index = EXCP_HLT; cpu->halted = true; diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c index 58674cb268..7567712655 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -282,10 +282,9 @@ static uint64_t make_address_pc(DisasContext *ctx, uint64_t addr) static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { - CPULoongArchState *env = cpu_env(cs); DisasContext *ctx = container_of(dcbase, DisasContext, base); - ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next); + ctx->opcode = translator_ldl(cpu_env(cs), &ctx->base, ctx->base.pc_next); if (!decode(ctx, ctx->opcode)) { qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. " diff --git a/target/rx/translate.c b/target/rx/translate.c index 2265bd14ac..f6bf68e00e 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2195,9 +2195,8 @@ static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { - CPURXState *env = cpu_env(cs); DisasContext *ctx = container_of(dcbase, DisasContext, base); - ctx->env = env; + ctx->env = cpu_env(cs); ctx->tb_flags = ctx->base.tb->flags; } diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 54d390fe1f..4559d0d376 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -29,9 +29,7 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - CPUSH4State *env = cpu_env(cs); - - env->tea = addr; + cpu_env(cs)->tea = addr; switch (access_type) { case MMU_INST_FETCH: case MMU_DATA_LOAD: From patchwork Tue Mar 12 12:43:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 779712 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2001477wrt; Tue, 12 Mar 2024 05:52:32 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXptRwcofSxnoAYSesyt9eIYHRWPvORccvLPqAX04dIS7DYJQjLduTRaPYAnX/sTeToXVEiQSg5rEWw3BB1GfN2 X-Google-Smtp-Source: AGHT+IFZPGnyDyRPHAxNKpTlkBUUOLkNn7Tny6HMPkP5ecx3ZLD7wBNCO0eV9cgo+KElO/RcJIbx X-Received: by 2002:a25:e0c5:0:b0:db5:50ea:d304 with SMTP id x188-20020a25e0c5000000b00db550ead304mr157459ybg.34.1710247951965; Tue, 12 Mar 2024 05:52:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1710247951; cv=none; d=google.com; s=arc-20160816; b=bzX8ISxbgTAGKS1KplCVe0l9OSSZMUS+l+vgHbSQMWdu9yT6/vyuiDBgoZ9pvjSFsN f5Zy9vRc+tzb3hs3rDSPA6ho+RdtbmyNNgdpuOyrPvnwqL/8oIAiSDyf1iJXOyk1CQ52 LjQFx0Izy8Im1oh2MkP0jaFJ9z+3UhrRZlXQCdylLyndH6+CtEvR4eiz3rkUo3UoM++q LNtZfrzJgZzqJE2B4lhl1lDS51POuic6UkK61dL3XftGd5BxWCy1GwudQBKsbBs9AdfH cW17koK5YtLFhuwr3XQui5bUqlqlYvA82fdWfVkaIRB/5JDYhEK2AHr7oRLK/qrn1mWR OEsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Tag4W2j1bocwj19HspBSk4KT111YUXnCwEQUEp1LouI=; fh=MVtmONGgcwaswePOsQaFbzD/JigNLxHXgB5l4X9593E=; b=VJXA/vY7SiSYo9O86VMFXWfYTVWbOrheueDAciHCG1HInKY1aiSogDKqrPNKCIQ121 Iog2I5U1iWoVns2fuRjpYdlemhiobvVcYhIhqEFJKfa/NHB9TbyPw3Yz7FRe36NPUKdy U3M7M3J+Rrzh7WilYcc+/ipOQsQvDDgCUuJZ73+nNtNhESfGi1i3Gyd/dhPKimfw9xsJ ALFD7qx7HKVJBVUEWiHPZhGHvQwGiW9wrPoHGMf9EOf7pj9VuQEo3D3E2MWmXAE9mMiT 05OXvxe5b9cO8VYtMzzQncCOeJZPIYoVRIR9NKH90CC8uub65+yl50CCJ43Nib7nMu/f pTYw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=Zd4nITfp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n22-20020ac85a16000000b0042ec4b1469dsi7668010qta.686.2024.03.12.05.52.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:52:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=Zd4nITfp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1XZ-00081X-2M; Tue, 12 Mar 2024 08:47:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VG-0004Xx-IU for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:12 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1V6-0000Xb-P1 for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:09 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247500; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Tag4W2j1bocwj19HspBSk4KT111YUXnCwEQUEp1LouI=; b=Zd4nITfp5Up6plcySVQQfx4wNhxSHp0qlZmA2gj1GNagnk+BpvIf7noBYt3WD3lJ1y5Y2m l2GUEkEL6CBPvPuT3oMKXj/zdC+CFaveypAfhGcX5LJym/UNH79W37XsGg2PzSB4wWc0Bg jo+EH1QwKgf+qTMBQ26mZs76hRsH948= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-31-v-PeDbHkMbiTPOhmLMoVug-1; Tue, 12 Mar 2024 08:44:53 -0400 X-MC-Unique: v-PeDbHkMbiTPOhmLMoVug-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 80D1E101D223; Tue, 12 Mar 2024 12:44:53 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9A38A492BC4; Tue, 12 Mar 2024 12:44:52 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Richard Henderson Subject: [PULL 37/55] target: Replace CPU_GET_CLASS(cpu -> obj) in cpu_reset_hold() handler Date: Tue, 12 Mar 2024 13:43:21 +0100 Message-ID: <20240312124339.761630-38-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Since CPU() macro is a simple cast, the following are equivalent: Object *obj; CPUState *cs = CPU(obj) In order to ease static analysis when running scripts/coccinelle/cpu_env.cocci from the previous commit, replace: - CPU_GET_CLASS(cpu); + CPU_GET_CLASS(obj); Most code use the 'cs' variable name for CPUState handle. Replace few 's' -> 'cs' to unify cpu_reset_hold() style. No logical change in this patch. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Richard Henderson Message-ID: <20240129164514.73104-7-philmd@linaro.org> Signed-off-by: Thomas Huth --- target/arm/cpu.c | 14 +++++++------- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hexagon/cpu.c | 2 +- target/i386/cpu.c | 14 +++++++------- target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 6 +++--- target/microblaze/cpu.c | 6 +++--- target/mips/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 8 ++++---- target/ppc/cpu_init.c | 12 ++++++------ target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/sh4/cpu.c | 6 +++--- target/sparc/cpu.c | 6 +++--- target/tricore/cpu.c | 6 +++--- target/xtensa/cpu.c | 8 ++++---- 18 files changed, 51 insertions(+), 51 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 02fc0adb65..ab8d007a86 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -214,9 +214,9 @@ static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) static void arm_cpu_reset_hold(Object *obj) { - CPUState *s = CPU(obj); - ARMCPU *cpu = ARM_CPU(s); - ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); + CPUState *cs = CPU(obj); + ARMCPU *cpu = ARM_CPU(cs); + ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); CPUARMState *env = &cpu->env; if (acc->parent_phases.hold) { @@ -233,7 +233,7 @@ static void arm_cpu_reset_hold(Object *obj) env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; - cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; + cpu->power_state = cs->start_powered_off ? PSCI_OFF : PSCI_ON; if (arm_feature(env, ARM_FEATURE_IWMMXT)) { env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; @@ -438,7 +438,7 @@ static void arm_cpu_reset_hold(Object *obj) /* Load the initial SP and PC from offset 0 and 4 in the vector table */ vecbase = env->v7m.vecbase[env->v7m.secure]; - rom = rom_ptr_for_as(s->as, vecbase, 8); + rom = rom_ptr_for_as(cs->as, vecbase, 8); if (rom) { /* Address zero is covered by ROM which hasn't yet been * copied into physical memory. @@ -451,8 +451,8 @@ static void arm_cpu_reset_hold(Object *obj) * it got copied into memory. In the latter case, rom_ptr * will return a NULL pointer and we should use ldl_phys instead. */ - initial_msp = ldl_phys(s->as, vecbase); - initial_pc = ldl_phys(s->as, vecbase + 4); + initial_msp = ldl_phys(cs->as, vecbase); + initial_pc = ldl_phys(cs->as, vecbase + 4); } qemu_log_mask(CPU_LOG_INT, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index a50170bc69..950f6cccf0 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -79,7 +79,7 @@ static void avr_cpu_reset_hold(Object *obj) { CPUState *cs = CPU(obj); AVRCPU *cpu = AVR_CPU(cs); - AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu); + AVRCPUClass *mcc = AVR_CPU_GET_CLASS(obj); CPUAVRState *env = &cpu->env; if (mcc->parent_phases.hold) { diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 163fb05d58..ab2f169f21 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -65,7 +65,7 @@ static void cris_cpu_reset_hold(Object *obj) { CPUState *s = CPU(obj); CRISCPU *cpu = CRIS_CPU(s); - CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); + CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj); CPUCRISState *env = &cpu->env; uint32_t vr; diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index a10d87b822..d41c6452a2 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -289,7 +289,7 @@ static void hexagon_cpu_reset_hold(Object *obj) { CPUState *cs = CPU(obj); HexagonCPU *cpu = HEXAGON_CPU(cs); - HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(cpu); + HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(obj); CPUHexagonState *env = &cpu->env; if (mcc->parent_phases.hold) { diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2666ef3808..9a210d8d92 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6695,9 +6695,9 @@ static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) static void x86_cpu_reset_hold(Object *obj) { - CPUState *s = CPU(obj); - X86CPU *cpu = X86_CPU(s); - X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); + CPUState *cs = CPU(obj); + X86CPU *cpu = X86_CPU(cs); + X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); CPUX86State *env = &cpu->env; target_ulong cr4; uint64_t xcr0; @@ -6785,8 +6785,8 @@ static void x86_cpu_reset_hold(Object *obj) memset(env->dr, 0, sizeof(env->dr)); env->dr[6] = DR6_FIXED_1; env->dr[7] = DR7_FIXED_1; - cpu_breakpoint_remove_all(s, BP_CPU); - cpu_watchpoint_remove_all(s, BP_CPU); + cpu_breakpoint_remove_all(cs, BP_CPU); + cpu_watchpoint_remove_all(cs, BP_CPU); cr4 = 0; xcr0 = XSTATE_FP_MASK; @@ -6837,9 +6837,9 @@ static void x86_cpu_reset_hold(Object *obj) env->triple_fault_pending = false; #if !defined(CONFIG_USER_ONLY) /* We hard-wire the BSP to the first CPU. */ - apic_designate_bsp(cpu->apic_state, s->cpu_index == 0); + apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); - s->halted = !cpu_is_bsp(cpu); + cs->halted = !cpu_is_bsp(cpu); if (kvm_enabled()) { kvm_arch_reset_vcpu(cpu); diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index bc2684179f..e935c79b68 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -510,7 +510,7 @@ static void loongarch_cpu_reset_hold(Object *obj) { CPUState *cs = CPU(obj); LoongArchCPU *cpu = LOONGARCH_CPU(cs); - LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu); + LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(obj); CPULoongArchState *env = &cpu->env; if (lacc->parent_phases.hold) { diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index cc6e4537be..9cc1de567f 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -73,9 +73,9 @@ static void m68k_unset_feature(CPUM68KState *env, int feature) static void m68k_cpu_reset_hold(Object *obj) { - CPUState *s = CPU(obj); - M68kCPU *cpu = M68K_CPU(s); - M68kCPUClass *mcc = M68K_CPU_GET_CLASS(cpu); + CPUState *cs = CPU(obj); + M68kCPU *cpu = M68K_CPU(cs); + M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj); CPUM68KState *env = &cpu->env; floatx80 nan = floatx80_default_nan(NULL); int i; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index e533e7a95e..96c2b71f7f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -183,9 +183,9 @@ static void microblaze_cpu_set_irq(void *opaque, int irq, int level) static void mb_cpu_reset_hold(Object *obj) { - CPUState *s = CPU(obj); - MicroBlazeCPU *cpu = MICROBLAZE_CPU(s); - MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu); + CPUState *cs = CPU(obj); + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(obj); CPUMBState *env = &cpu->env; if (mcc->parent_phases.hold) { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index d644adbc77..98ef073631 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -193,7 +193,7 @@ static void mips_cpu_reset_hold(Object *obj) { CPUState *cs = CPU(obj); MIPSCPU *cpu = MIPS_CPU(cs); - MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); + MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); CPUMIPSState *env = &cpu->env; if (mcc->parent_phases.hold) { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 0760bf6b38..b10693618b 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -67,7 +67,7 @@ static void nios2_cpu_reset_hold(Object *obj) { CPUState *cs = CPU(obj); Nios2CPU *cpu = NIOS2_CPU(cs); - Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(cpu); + Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(obj); CPUNios2State *env = &cpu->env; if (ncc->parent_phases.hold) { diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index a3cb80ca34..33c45dbf04 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -87,9 +87,9 @@ static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) static void openrisc_cpu_reset_hold(Object *obj) { - CPUState *s = CPU(obj); - OpenRISCCPU *cpu = OPENRISC_CPU(s); - OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); + CPUState *cs = CPU(obj); + OpenRISCCPU *cpu = OPENRISC_CPU(cs); + OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(obj); if (occ->parent_phases.hold) { occ->parent_phases.hold(obj); @@ -100,7 +100,7 @@ static void openrisc_cpu_reset_hold(Object *obj) cpu->env.pc = 0x100; cpu->env.sr = SR_FO | SR_SM; cpu->env.lock_addr = -1; - s->exception_index = -1; + cs->exception_index = -1; cpu_set_fpcsr(&cpu->env, 0); set_float_detect_tininess(float_tininess_before_rounding, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 1d3d1db7c3..6d9c5a6c9a 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7108,9 +7108,9 @@ static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch) static void ppc_cpu_reset_hold(Object *obj) { - CPUState *s = CPU(obj); - PowerPCCPU *cpu = POWERPC_CPU(s); - PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + CPUState *cs = CPU(obj); + PowerPCCPU *cpu = POWERPC_CPU(cs); + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(obj); CPUPPCState *env = &cpu->env; target_ulong msr; int i; @@ -7159,8 +7159,8 @@ static void ppc_cpu_reset_hold(Object *obj) env->nip = env->hreset_vector | env->excp_prefix; if (tcg_enabled()) { - cpu_breakpoint_remove_all(s, BP_CPU); - cpu_watchpoint_remove_all(s, BP_CPU); + cpu_breakpoint_remove_all(cs, BP_CPU); + cpu_watchpoint_remove_all(cs, BP_CPU); if (env->mmu_model != POWERPC_MMU_REAL) { ppc_tlb_invalidate_all(env); } @@ -7174,7 +7174,7 @@ static void ppc_cpu_reset_hold(Object *obj) env->reserve_addr = (target_ulong)-1ULL; /* Be sure no exception or interrupt is pending */ env->pending_interrupts = 0; - s->exception_index = POWERPC_EXCP_NONE; + cs->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; ppc_irq_reset(cpu); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5a48d30828..c160b9216b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -926,7 +926,7 @@ static void riscv_cpu_reset_hold(Object *obj) #endif CPUState *cs = CPU(obj); RISCVCPU *cpu = RISCV_CPU(cs); - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj); CPURISCVState *env = &cpu->env; if (mcc->parent_phases.hold) { diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 2f878d08d6..26ff822e71 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -72,7 +72,7 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifunc) static void rx_cpu_reset_hold(Object *obj) { RXCPU *cpu = RX_CPU(obj); - RXCPUClass *rcc = RX_CPU_GET_CLASS(cpu); + RXCPUClass *rcc = RX_CPU_GET_CLASS(obj); CPURXState *env = &cpu->env; uint32_t *resetvec; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 2031168dc6..eb7c551e9b 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -106,9 +106,9 @@ static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch) static void superh_cpu_reset_hold(Object *obj) { - CPUState *s = CPU(obj); - SuperHCPU *cpu = SUPERH_CPU(s); - SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); + CPUState *cs = CPU(obj); + SuperHCPU *cpu = SUPERH_CPU(cs); + SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(obj); CPUSH4State *env = &cpu->env; if (scc->parent_phases.hold) { diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 313ebc4c11..ce6aab6bcb 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -31,9 +31,9 @@ static void sparc_cpu_reset_hold(Object *obj) { - CPUState *s = CPU(obj); - SPARCCPU *cpu = SPARC_CPU(s); - SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu); + CPUState *cs = CPU(obj); + SPARCCPU *cpu = SPARC_CPU(cs); + SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj); CPUSPARCState *env = &cpu->env; if (scc->parent_phases.hold) { diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 74e8a22b86..682fc290ac 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -72,9 +72,9 @@ static void tricore_restore_state_to_opc(CPUState *cs, static void tricore_cpu_reset_hold(Object *obj) { - CPUState *s = CPU(obj); - TriCoreCPU *cpu = TRICORE_CPU(s); - TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(cpu); + CPUState *cs = CPU(obj); + TriCoreCPU *cpu = TRICORE_CPU(cs); + TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(obj); CPUTriCoreState *env = &cpu->env; if (tcc->parent_phases.hold) { diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 79f91819df..c1cedf3f35 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -95,9 +95,9 @@ bool xtensa_abi_call0(void) static void xtensa_cpu_reset_hold(Object *obj) { - CPUState *s = CPU(obj); - XtensaCPU *cpu = XTENSA_CPU(s); - XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); + CPUState *cs = CPU(obj); + XtensaCPU *cpu = XTENSA_CPU(cs); + XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); CPUXtensaState *env = &cpu->env; bool dfpu = xtensa_option_enabled(env->config, XTENSA_OPTION_DFP_COPROCESSOR); @@ -132,7 +132,7 @@ static void xtensa_cpu_reset_hold(Object *obj) #ifndef CONFIG_USER_ONLY reset_mmu(env); - s->halted = env->runstall; + cs->halted = env->runstall; #endif set_no_signaling_nans(!dfpu, &env->fp_status); set_use_first_nan(!dfpu, &env->fp_status); From patchwork Tue Mar 12 12:43:22 2024 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id z10-20020a05622a028a00b0042f11ba682dsi7734553qtw.496.2024.03.12.05.55.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:55:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=dDLBax1X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1WC-0006NS-H1; Tue, 12 Mar 2024 08:46:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1V8-0004P4-Dz for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:03 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1V4-0000XB-Uf for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:02 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247498; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eb58VdMkT72bE3NN+1BpFDoUUUPI1yhPfAiesZfAe2I=; b=dDLBax1XolEF01tWdd7zLhc6s27lQ7AFNGMndBi8z3oJt9q5r3oCH32hK6xPchGQGZ74VG x3uvB2jSdFhruUu7jPRAr0xN0skCeUwpxan+Co1w4frlILsEmxcTmn6jNT/SZJD1GC6eEc pOy3tAwXXeNNBWig/dObhGYCJmx3EM0= Received: from mimecast-mx02.redhat.com (mx-ext.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-684-i7uxCo4bPeWDHnC-d863sA-1; Tue, 12 Mar 2024 08:44:55 -0400 X-MC-Unique: i7uxCo4bPeWDHnC-d863sA-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id C4EED285F987; Tue, 12 Mar 2024 12:44:54 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id C9E28492BC4; Tue, 12 Mar 2024 12:44:53 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Richard Henderson Subject: [PULL 38/55] target/alpha: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Tue, 12 Mar 2024 13:43:22 +0100 Message-ID: <20240312124339.761630-39-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20240129164514.73104-8-philmd@linaro.org> Signed-off-by: Thomas Huth --- target/alpha/cpu.c | 31 +++++++------------------------ target/alpha/gdbstub.c | 6 ++---- target/alpha/helper.c | 15 +++++---------- target/alpha/mem_helper.c | 11 +++-------- target/alpha/translate.c | 4 ++-- 5 files changed, 19 insertions(+), 48 deletions(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index bf70173a25..05f9ee41e9 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -135,40 +135,27 @@ static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model) static void ev4_cpu_initfn(Object *obj) { - AlphaCPU *cpu = ALPHA_CPU(obj); - CPUAlphaState *env = &cpu->env; - - env->implver = IMPLVER_2106x; + cpu_env(CPU(obj))->implver = IMPLVER_2106x; } static void ev5_cpu_initfn(Object *obj) { - AlphaCPU *cpu = ALPHA_CPU(obj); - CPUAlphaState *env = &cpu->env; - - env->implver = IMPLVER_21164; + cpu_env(CPU(obj))->implver = IMPLVER_21164; } static void ev56_cpu_initfn(Object *obj) { - AlphaCPU *cpu = ALPHA_CPU(obj); - CPUAlphaState *env = &cpu->env; - - env->amask |= AMASK_BWX; + cpu_env(CPU(obj))->amask |= AMASK_BWX; } static void pca56_cpu_initfn(Object *obj) { - AlphaCPU *cpu = ALPHA_CPU(obj); - CPUAlphaState *env = &cpu->env; - - env->amask |= AMASK_MVI; + cpu_env(CPU(obj))->amask |= AMASK_MVI; } static void ev6_cpu_initfn(Object *obj) { - AlphaCPU *cpu = ALPHA_CPU(obj); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(CPU(obj)); env->implver = IMPLVER_21264; env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP; @@ -176,16 +163,12 @@ static void ev6_cpu_initfn(Object *obj) static void ev67_cpu_initfn(Object *obj) { - AlphaCPU *cpu = ALPHA_CPU(obj); - CPUAlphaState *env = &cpu->env; - - env->amask |= AMASK_CIX | AMASK_PREFETCH; + cpu_env(CPU(obj))->amask |= AMASK_CIX | AMASK_PREFETCH; } static void alpha_cpu_initfn(Object *obj) { - AlphaCPU *cpu = ALPHA_CPU(obj); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(CPU(obj)); env->lock_addr = -1; #if defined(CONFIG_USER_ONLY) diff --git a/target/alpha/gdbstub.c b/target/alpha/gdbstub.c index 0f8fa150f8..13694fd321 100644 --- a/target/alpha/gdbstub.c +++ b/target/alpha/gdbstub.c @@ -23,8 +23,7 @@ int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(cs); uint64_t val; CPU_DoubleU d; @@ -59,8 +58,7 @@ int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int alpha_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(cs); target_ulong tmp = ldtul_p(mem_buf); CPU_DoubleU d; diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 970c869771..d6d4353edd 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -286,11 +286,10 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr, hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - AlphaCPU *cpu = ALPHA_CPU(cs); target_ulong phys; int prot, fail; - fail = get_physical_address(&cpu->env, addr, 0, 0, &phys, &prot); + fail = get_physical_address(cpu_env(cs), addr, 0, 0, &phys, &prot); return (fail >= 0 ? -1 : phys); } @@ -298,8 +297,7 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(cs); target_ulong phys; int prot, fail; @@ -325,8 +323,7 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, void alpha_cpu_do_interrupt(CPUState *cs) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(cs); int i = cs->exception_index; if (qemu_loglevel_mask(CPU_LOG_INT)) { @@ -435,8 +432,7 @@ void alpha_cpu_do_interrupt(CPUState *cs) bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(cs); int idx = -1; /* We never take interrupts while in PALmode. */ @@ -487,8 +483,7 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags) "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", "t10", "t11", "ra", "t12", "at", "gp", "sp" }; - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(cs); int i; qemu_fprintf(f, "PC " TARGET_FMT_lx " PS %02x\n", diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index a39b52c5dd..872955f5e7 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -42,18 +42,14 @@ static void do_unaligned_access(CPUAlphaState *env, vaddr addr, uintptr_t retadd void alpha_cpu_record_sigbus(CPUState *cs, vaddr addr, MMUAccessType access_type, uintptr_t retaddr) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; - - do_unaligned_access(env, addr, retaddr); + do_unaligned_access(cpu_env(cs), addr, retaddr); } #else void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(cs); do_unaligned_access(env, addr, retaddr); cs->exception_index = EXCP_UNALIGN; @@ -67,8 +63,7 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr) { - AlphaCPU *cpu = ALPHA_CPU(cs); - CPUAlphaState *env = &cpu->env; + CPUAlphaState *env = cpu_env(cs); env->trap_arg0 = addr; env->trap_arg1 = access_type == MMU_DATA_STORE ? 1 : 0; diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 882cf6cea0..a97cd54f0c 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2903,8 +2903,8 @@ static void alpha_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - CPUAlphaState *env = cpu_env(cpu); - uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next); + uint32_t insn = translator_ldl(cpu_env(cpu), &ctx->base, + ctx->base.pc_next); ctx->base.pc_next += 4; ctx->base.is_jmp = translate_one(ctx, insn); From patchwork Tue Mar 12 12:43:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 779723 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2003147wrt; Tue, 12 Mar 2024 05:56:47 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXSFoXmBxlr4BoP/n9lrY67xXuyOZX94JD9qCLbtpIQ3NmzhnbqwAR9OZUMD/sqyFyKIxx4HwSTkw/EYqK+EYGy X-Google-Smtp-Source: AGHT+IFrCAF091R1+Oo5cfYgF4WhN3Vd1UqRI8ceIMy1j256zx8pbfruHVZFPbJG55uFZA3IJRf8 X-Received: by 2002:a05:6808:159c:b0:3c2:1191:763d with SMTP id t28-20020a056808159c00b003c21191763dmr1951703oiw.27.1710248206933; Tue, 12 Mar 2024 05:56:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1710248206; cv=none; d=google.com; s=arc-20160816; b=GmVFu4IsezfOX2mL7HTIrwE/vOERXk6POmACCuq/Z7IV4JjuIDFJD23JK4RwlMC/59 X1DF10qvk/iygFcYDstm5nnTCTe41ZR0GYP0Gs0x809c0h0AJ2k/BBrDvCLEMLarYR7Y RAXh8M4yQ8KKPSwACcU9qu3LTJkGUaN3O050T1QBaqTRnumI3UPempa4qw6daubY5LCQ F+8DPAcCsxp886JIJtzAU4fhoyTwhCXG++Y1TTSd7aZZVEhKdm5SKK1KMsXz8nuib5oD vIirUTAnIMsB/QF/2WpzqhOHmIOEhLD/ykqPYX2DEtn1GPD9ywRJ5ailM+cSSW64E3Sz SpBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vYzPphBUZCi3YUzQfX0LOgd/O70Elz1BT5b0qwjiLdk=; fh=MVtmONGgcwaswePOsQaFbzD/JigNLxHXgB5l4X9593E=; b=HAdX2vmQaeRi4DXzxY+1NL8xjCpdiYU7BYXaIyyrSRtGwpel3srLU2mC1tedOKyLGz YyeJegITIQLuG4kmm1F/MZNrkQ2XC7rLcncsQp1gyKgs7PZsuTpQDiXyJIXe5YqfaW89 ZXfcqbCl1YJNmtSR0lqHmfRlJqPQrYIaB51T3c92rQBE6Q17RVtLfujWBkoq/huiyATI ygo3plvnXCe2x5MiDsslja4sK1YjfaoWKXE31LaiQ/RFH9L1g006kZJsoROxfTcyUolF +2Bjiiz9bnnMwkg4sEaz17yBYJFI1psxuwpErs0DkiZ06S71VgIO57UAYwgoHJ2bs+nl a+YA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=HUDlexiU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q12-20020a05620a038c00b00787b4590845si7362637qkm.107.2024.03.12.05.56.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:56:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=HUDlexiU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1XC-0007aQ-V4; Tue, 12 Mar 2024 08:47:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VC-0004TU-B1 for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:09 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1V7-0000Y9-Pg for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:06 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247500; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vYzPphBUZCi3YUzQfX0LOgd/O70Elz1BT5b0qwjiLdk=; b=HUDlexiUcZEY7ZP/0QcqLYayQURO+g0qFce7+YagrPiI4y14vmyBrom4TEl5/S7+QnlMl4 mOrIhcVBKxe+60QwhUi6iEK4xbyAkAQGp7Gm0ZamIuIfR0s2j4W9CBeCyEBzATvJq/2K1U BPtyjQEveaWdZ+kcpm66Bf0aFCI447Y= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-580-Pja9Xor7MxGYKKsUed_c4A-1; Tue, 12 Mar 2024 08:44:56 -0400 X-MC-Unique: Pja9Xor7MxGYKKsUed_c4A-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 57B57811E81; Tue, 12 Mar 2024 12:44:56 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id 38130492BC4; Tue, 12 Mar 2024 12:44:54 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Richard Henderson Subject: [PULL 39/55] target/avr: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Tue, 12 Mar 2024 13:43:23 +0100 Message-ID: <20240312124339.761630-40-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20240129164514.73104-10-philmd@linaro.org> Signed-off-by: Thomas Huth --- target/avr/cpu.c | 27 +++++++-------------------- target/avr/gdbstub.c | 6 ++---- target/avr/helper.c | 10 +++------- target/avr/translate.c | 3 +-- 4 files changed, 13 insertions(+), 33 deletions(-) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 950f6cccf0..45ee1b5f89 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -43,11 +43,8 @@ static vaddr avr_cpu_get_pc(CPUState *cs) static bool avr_cpu_has_work(CPUState *cs) { - AVRCPU *cpu = AVR_CPU(cs); - CPUAVRState *env = &cpu->env; - return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET)) - && cpu_interrupts_enabled(env); + && cpu_interrupts_enabled(cpu_env(cs)); } static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) @@ -58,21 +55,15 @@ static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) static void avr_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - AVRCPU *cpu = AVR_CPU(cs); - CPUAVRState *env = &cpu->env; - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); - env->pc_w = tb->pc / 2; /* internally PC points to words */ + cpu_env(cs)->pc_w = tb->pc / 2; /* internally PC points to words */ } static void avr_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - AVRCPU *cpu = AVR_CPU(cs); - CPUAVRState *env = &cpu->env; - - env->pc_w = data[0]; + cpu_env(cs)->pc_w = data[0]; } static void avr_cpu_reset_hold(Object *obj) @@ -170,8 +161,7 @@ static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - AVRCPU *cpu = AVR_CPU(cs); - CPUAVRState *env = &cpu->env; + CPUAVRState *env = cpu_env(cs); int i; qemu_fprintf(f, "\n"); @@ -281,8 +271,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) */ static void avr_avr5_initfn(Object *obj) { - AVRCPU *cpu = AVR_CPU(obj); - CPUAVRState *env = &cpu->env; + CPUAVRState *env = cpu_env(CPU(obj)); set_avr_feature(env, AVR_FEATURE_LPM); set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); @@ -310,8 +299,7 @@ static void avr_avr5_initfn(Object *obj) */ static void avr_avr51_initfn(Object *obj) { - AVRCPU *cpu = AVR_CPU(obj); - CPUAVRState *env = &cpu->env; + CPUAVRState *env = cpu_env(CPU(obj)); set_avr_feature(env, AVR_FEATURE_LPM); set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); @@ -340,8 +328,7 @@ static void avr_avr51_initfn(Object *obj) */ static void avr_avr6_initfn(Object *obj) { - AVRCPU *cpu = AVR_CPU(obj); - CPUAVRState *env = &cpu->env; + CPUAVRState *env = cpu_env(CPU(obj)); set_avr_feature(env, AVR_FEATURE_LPM); set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); diff --git a/target/avr/gdbstub.c b/target/avr/gdbstub.c index 150344d8b9..2eeee2bf4e 100644 --- a/target/avr/gdbstub.c +++ b/target/avr/gdbstub.c @@ -23,8 +23,7 @@ int avr_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - AVRCPU *cpu = AVR_CPU(cs); - CPUAVRState *env = &cpu->env; + CPUAVRState *env = cpu_env(cs); /* R */ if (n < 32) { @@ -53,8 +52,7 @@ int avr_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int avr_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - AVRCPU *cpu = AVR_CPU(cs); - CPUAVRState *env = &cpu->env; + CPUAVRState *env = cpu_env(cs); /* R */ if (n < 32) { diff --git a/target/avr/helper.c b/target/avr/helper.c index fdc9884ea0..eeca415c43 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -30,8 +30,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - AVRCPU *cpu = AVR_CPU(cs); - CPUAVRState *env = &cpu->env; + CPUAVRState *env = cpu_env(cs); /* * We cannot separate a skip from the next instruction, @@ -69,8 +68,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) void avr_cpu_do_interrupt(CPUState *cs) { - AVRCPU *cpu = AVR_CPU(cs); - CPUAVRState *env = &cpu->env; + CPUAVRState *env = cpu_env(cs); uint32_t ret = env->pc_w; int vector = 0; @@ -144,9 +142,7 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (probe) { page_size = 1; } else { - AVRCPU *cpu = AVR_CPU(cs); - CPUAVRState *env = &cpu->env; - env->fullacc = 1; + cpu_env(cs)->fullacc = 1; cpu_loop_exit_restore(cs, retaddr); } } diff --git a/target/avr/translate.c b/target/avr/translate.c index e5dd057799..87e2bd5ef1 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2657,11 +2657,10 @@ static bool canonicalize_skip(DisasContext *ctx) static void avr_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - CPUAVRState *env = cpu_env(cs); uint32_t tb_flags = ctx->base.tb->flags; ctx->cs = cs; - ctx->env = env; + ctx->env = cpu_env(cs); ctx->npc = ctx->base.pc_first / 2; ctx->skip_cond = TCG_COND_NEVER; From patchwork Tue Mar 12 12:43:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 779717 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2001816wrt; Tue, 12 Mar 2024 05:53:22 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCViRCtsS8Q+a7QQZldxQLIbHukEn+fD2Sj8/QtH0UcSw+sgLjVtx1x65ugZeQSAf6DR49+5pUNGpnVSIjycz03r X-Google-Smtp-Source: AGHT+IFcb0pb8LpdQRgrLpLa+NBqGdKciNSIsRZMrWL5VG1v038NQWCI/ASOfWCdUBfewfzjMbCN X-Received: by 2002:a05:620a:2904:b0:788:7d9e:44bf with SMTP id m4-20020a05620a290400b007887d9e44bfmr1401423qkp.25.1710248001875; Tue, 12 Mar 2024 05:53:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1710248001; cv=none; d=google.com; s=arc-20160816; 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[209.51.188.17]) by mx.google.com with ESMTPS id wj16-20020a05620a575000b007887cc54392si1071501qkn.689.2024.03.12.05.53.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:53:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=DVyGJn90; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1WA-00069z-1F; Tue, 12 Mar 2024 08:46:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VF-0004Xh-VW for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:12 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VA-0000aF-Fl for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:07 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247503; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=j38YhxI5+1cvhXh9Ttj8PoXcMG7tNmX/38Gr4jWwNug=; b=DVyGJn901fi4vOb/EUMV8NvoLUMaDxKqPfIcp2i+LqNpQKYA+u4BETr/pjACZbyMOo+bp+ MroFnIV/JbIxJF+oIZJRRIJZ3dW3yaXAPRsO7juvbQWXAEgDHOadgFBfkN5kJZR4AkP3pz FfL7xP1NVGZ2mQf6YC/QxNjaEQRV9E8= Received: from mimecast-mx02.redhat.com (mx-ext.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-461-mttuwsFnP7-kY9gX7Qnwbw-1; Tue, 12 Mar 2024 08:44:58 -0400 X-MC-Unique: mttuwsFnP7-kY9gX7Qnwbw-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id E85EC1C41A19; Tue, 12 Mar 2024 12:44:57 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id BDD1F492BC4; Tue, 12 Mar 2024 12:44:56 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Richard Henderson Subject: [PULL 40/55] target/cris: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Tue, 12 Mar 2024 13:43:24 +0100 Message-ID: <20240312124339.761630-41-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20240129164514.73104-11-philmd@linaro.org> Signed-off-by: Thomas Huth --- target/cris/cpu.c | 10 +++------- target/cris/gdbstub.c | 9 +++------ target/cris/helper.c | 12 ++++-------- target/cris/translate.c | 6 ++---- 4 files changed, 12 insertions(+), 25 deletions(-) diff --git a/target/cris/cpu.c b/target/cris/cpu.c index ab2f169f21..eb4bddcb7e 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -63,10 +63,9 @@ static int cris_cpu_mmu_index(CPUState *cs, bool ifetch) static void cris_cpu_reset_hold(Object *obj) { - CPUState *s = CPU(obj); - CRISCPU *cpu = CRIS_CPU(s); + CPUState *cs = CPU(obj); CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj); - CPUCRISState *env = &cpu->env; + CPUCRISState *env = cpu_env(cs); uint32_t vr; if (ccc->parent_phases.hold) { @@ -147,10 +146,7 @@ static void cris_cpu_set_irq(void *opaque, int irq, int level) static void cris_disas_set_info(CPUState *cpu, disassemble_info *info) { - CRISCPU *cc = CRIS_CPU(cpu); - CPUCRISState *env = &cc->env; - - if (env->pregs[PR_VR] != 32) { + if (cpu_env(cpu)->pregs[PR_VR] != 32) { info->mach = bfd_mach_cris_v0_v10; info->print_insn = print_insn_crisv10; } else { diff --git a/target/cris/gdbstub.c b/target/cris/gdbstub.c index 25c0ca33a5..9e87069da8 100644 --- a/target/cris/gdbstub.c +++ b/target/cris/gdbstub.c @@ -23,8 +23,7 @@ int crisv10_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - CRISCPU *cpu = CRIS_CPU(cs); - CPUCRISState *env = &cpu->env; + CPUCRISState *env = cpu_env(cs); if (n < 15) { return gdb_get_reg32(mem_buf, env->regs[n]); @@ -55,8 +54,7 @@ int crisv10_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int cris_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - CRISCPU *cpu = CRIS_CPU(cs); - CPUCRISState *env = &cpu->env; + CPUCRISState *env = cpu_env(cs); uint8_t srs; srs = env->pregs[PR_SRS]; @@ -90,8 +88,7 @@ int cris_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int cris_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - CRISCPU *cpu = CRIS_CPU(cs); - CPUCRISState *env = &cpu->env; + CPUCRISState *env = cpu_env(cs); uint32_t tmp; if (n > 49) { diff --git a/target/cris/helper.c b/target/cris/helper.c index c0bf987e3e..1c3f86876f 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -53,8 +53,7 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - CRISCPU *cpu = CRIS_CPU(cs); - CPUCRISState *env = &cpu->env; + CPUCRISState *env = cpu_env(cs); struct cris_mmu_result res; int prot, miss; target_ulong phy; @@ -97,8 +96,7 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, void crisv10_cpu_do_interrupt(CPUState *cs) { - CRISCPU *cpu = CRIS_CPU(cs); - CPUCRISState *env = &cpu->env; + CPUCRISState *env = cpu_env(cs); int ex_vec = -1; D_LOG("exception index=%d interrupt_req=%d\n", @@ -159,8 +157,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) void cris_cpu_do_interrupt(CPUState *cs) { - CRISCPU *cpu = CRIS_CPU(cs); - CPUCRISState *env = &cpu->env; + CPUCRISState *env = cpu_env(cs); int ex_vec = -1; D_LOG("exception index=%d interrupt_req=%d\n", @@ -262,8 +259,7 @@ hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc = CPU_GET_CLASS(cs); - CRISCPU *cpu = CRIS_CPU(cs); - CPUCRISState *env = &cpu->env; + CPUCRISState *env = cpu_env(cs); bool ret = false; if (interrupt_request & CPU_INTERRUPT_HARD diff --git a/target/cris/translate.c b/target/cris/translate.c index 8f74b6c53f..b3a4d61d0a 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3002,7 +3002,6 @@ static void cris_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); - CPUCRISState *env = cpu_env(cs); unsigned int insn_len; /* Pretty disas. */ @@ -3010,7 +3009,7 @@ static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) dc->clear_x = 1; - insn_len = dc->decoder(env, dc); + insn_len = dc->decoder(cpu_env(cs), dc); dc->ppc = dc->pc; dc->pc += insn_len; dc->base.pc_next += insn_len; @@ -3176,8 +3175,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - CRISCPU *cpu = CRIS_CPU(cs); - CPUCRISState *env = &cpu->env; + CPUCRISState *env = cpu_env(cs); const char * const *regnames; const char * const *pregnames; int i; From patchwork Tue Mar 12 12:43:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 779721 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2002840wrt; Tue, 12 Mar 2024 05:56:01 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXbiGKaTesnFFtm+d6OI2B9m3FSpEvypFYsLEsG3XADIvJHzMBGbZatqENjnxlrmGwSvwwo910cwjzCBrr6Mf06 X-Google-Smtp-Source: AGHT+IETrdPzjV/3atOeHMUTZQkV7HfqwIssFDHIMUtSyQ/277HO/AGybRXpKyjwKBDovc0YnHK4 X-Received: by 2002:a05:620a:4c:b0:788:1ce1:828 with SMTP id t12-20020a05620a004c00b007881ce10828mr10896247qkt.23.1710248161226; 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[209.51.188.17]) by mx.google.com with ESMTPS id g27-20020a05620a219b00b007885a2d38d2si7210764qka.483.2024.03.12.05.56.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:56:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=XToerOhG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1VU-0005B6-5w; Tue, 12 Mar 2024 08:45:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VI-0004cA-M3 for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:16 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VA-0000aT-Qm for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247504; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BTy1j2FcNx/LRv42hVeztNg1Pww4AJJ67w4oKt1Dfo0=; b=XToerOhGL7/haQvhyxvyZsFX2LWt6tXX4F9e+jxszM4VObFaoXfmpMJjuBnZu31nt/Q+W1 3NM1sddvbxTEM9liDA6E+2mCPuogkux6r65QzNg5WWcB/Ll/OBp8jYAG/G2x3M0IC1O7sL MwkD11iu0o2vG3/yo4f37n8t+9WYupc= Received: from mimecast-mx02.redhat.com (mx-ext.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-606-ujwf2IJYMU2Mv4rLfFNuVA-1; Tue, 12 Mar 2024 08:45:00 -0400 X-MC-Unique: ujwf2IJYMU2Mv4rLfFNuVA-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 585853C0F18F; Tue, 12 Mar 2024 12:44:59 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id 378B5492BC4; Tue, 12 Mar 2024 12:44:58 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Brian Cain , Richard Henderson Subject: [PULL 41/55] target/hexagon: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Tue, 12 Mar 2024 13:43:25 +0100 Message-ID: <20240312124339.761630-42-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Brian Cain Reviewed-by: Richard Henderson Message-ID: <20240129164514.73104-12-philmd@linaro.org> Signed-off-by: Thomas Huth --- target/hexagon/cpu.c | 25 ++++++------------------- target/hexagon/gdbstub.c | 6 ++---- 2 files changed, 8 insertions(+), 23 deletions(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index d41c6452a2..3a716b9be3 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -236,10 +236,7 @@ static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags) static void hexagon_dump_state(CPUState *cs, FILE *f, int flags) { - HexagonCPU *cpu = HEXAGON_CPU(cs); - CPUHexagonState *env = &cpu->env; - - hexagon_dump(env, f, flags); + hexagon_dump(cpu_env(cs), f, flags); } void hexagon_debug(CPUHexagonState *env) @@ -249,25 +246,19 @@ void hexagon_debug(CPUHexagonState *env) static void hexagon_cpu_set_pc(CPUState *cs, vaddr value) { - HexagonCPU *cpu = HEXAGON_CPU(cs); - CPUHexagonState *env = &cpu->env; - env->gpr[HEX_REG_PC] = value; + cpu_env(cs)->gpr[HEX_REG_PC] = value; } static vaddr hexagon_cpu_get_pc(CPUState *cs) { - HexagonCPU *cpu = HEXAGON_CPU(cs); - CPUHexagonState *env = &cpu->env; - return env->gpr[HEX_REG_PC]; + return cpu_env(cs)->gpr[HEX_REG_PC]; } static void hexagon_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - HexagonCPU *cpu = HEXAGON_CPU(cs); - CPUHexagonState *env = &cpu->env; tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); - env->gpr[HEX_REG_PC] = tb->pc; + cpu_env(cs)->gpr[HEX_REG_PC] = tb->pc; } static bool hexagon_cpu_has_work(CPUState *cs) @@ -279,18 +270,14 @@ static void hexagon_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - HexagonCPU *cpu = HEXAGON_CPU(cs); - CPUHexagonState *env = &cpu->env; - - env->gpr[HEX_REG_PC] = data[0]; + cpu_env(cs)->gpr[HEX_REG_PC] = data[0]; } static void hexagon_cpu_reset_hold(Object *obj) { CPUState *cs = CPU(obj); - HexagonCPU *cpu = HEXAGON_CPU(cs); HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(obj); - CPUHexagonState *env = &cpu->env; + CPUHexagonState *env = cpu_env(cs); if (mcc->parent_phases.hold) { mcc->parent_phases.hold(obj); diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c index 6007e6462b..502c6987f0 100644 --- a/target/hexagon/gdbstub.c +++ b/target/hexagon/gdbstub.c @@ -22,8 +22,7 @@ int hexagon_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - HexagonCPU *cpu = HEXAGON_CPU(cs); - CPUHexagonState *env = &cpu->env; + CPUHexagonState *env = cpu_env(cs); if (n == HEX_REG_P3_0_ALIASED) { uint32_t p3_0 = 0; @@ -42,8 +41,7 @@ int hexagon_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - HexagonCPU *cpu = HEXAGON_CPU(cs); - CPUHexagonState *env = &cpu->env; + CPUHexagonState *env = cpu_env(cs); if (n == HEX_REG_P3_0_ALIASED) { uint32_t p3_0 = ldtul_p(mem_buf); From patchwork Tue Mar 12 12:43:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 779710 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2001050wrt; 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envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé QEMU coding style recommend using structure typedefs: https://www.qemu.org/docs/master/devel/style.html#typedefs Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu Message-ID: <20240129164514.73104-14-philmd@linaro.org> [thuth: Break long lines to avoid checkpatch.pl errors] Signed-off-by: Thomas Huth --- target/i386/hvf/x86.h | 26 +++++++++++++------------- target/i386/hvf/x86_descr.h | 14 +++++++------- target/i386/hvf/x86_emu.h | 4 ++-- target/i386/hvf/x86_mmu.h | 6 +++--- target/i386/hvf/x86.c | 26 +++++++++++++------------- target/i386/hvf/x86_descr.c | 11 +++++++---- target/i386/hvf/x86_mmu.c | 14 +++++++------- 7 files changed, 52 insertions(+), 49 deletions(-) diff --git a/target/i386/hvf/x86.h b/target/i386/hvf/x86.h index 947b98da41..3570f29aa9 100644 --- a/target/i386/hvf/x86.h +++ b/target/i386/hvf/x86.h @@ -248,30 +248,30 @@ typedef struct x68_segment_selector { #define BH(cpu) RH(cpu, R_EBX) /* deal with GDT/LDT descriptors in memory */ -bool x86_read_segment_descriptor(struct CPUState *cpu, +bool x86_read_segment_descriptor(CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel); -bool x86_write_segment_descriptor(struct CPUState *cpu, +bool x86_write_segment_descriptor(CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel); -bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc, +bool x86_read_call_gate(CPUState *cpu, struct x86_call_gate *idt_desc, int gate); /* helpers */ -bool x86_is_protected(struct CPUState *cpu); -bool x86_is_real(struct CPUState *cpu); -bool x86_is_v8086(struct CPUState *cpu); -bool x86_is_long_mode(struct CPUState *cpu); -bool x86_is_long64_mode(struct CPUState *cpu); -bool x86_is_paging_mode(struct CPUState *cpu); -bool x86_is_pae_enabled(struct CPUState *cpu); +bool x86_is_protected(CPUState *cpu); +bool x86_is_real(CPUState *cpu); +bool x86_is_v8086(CPUState *cpu); +bool x86_is_long_mode(CPUState *cpu); +bool x86_is_long64_mode(CPUState *cpu); +bool x86_is_paging_mode(CPUState *cpu); +bool x86_is_pae_enabled(CPUState *cpu); enum X86Seg; -target_ulong linear_addr(struct CPUState *cpu, target_ulong addr, enum X86Seg seg); -target_ulong linear_addr_size(struct CPUState *cpu, target_ulong addr, int size, +target_ulong linear_addr(CPUState *cpu, target_ulong addr, enum X86Seg seg); +target_ulong linear_addr_size(CPUState *cpu, target_ulong addr, int size, enum X86Seg seg); -target_ulong linear_rip(struct CPUState *cpu, target_ulong rip); +target_ulong linear_rip(CPUState *cpu, target_ulong rip); static inline uint64_t rdtscp(void) { diff --git a/target/i386/hvf/x86_descr.h b/target/i386/hvf/x86_descr.h index c356932fa4..9f06014b56 100644 --- a/target/i386/hvf/x86_descr.h +++ b/target/i386/hvf/x86_descr.h @@ -29,29 +29,29 @@ typedef struct vmx_segment { } vmx_segment; /* deal with vmstate descriptors */ -void vmx_read_segment_descriptor(struct CPUState *cpu, +void vmx_read_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, enum X86Seg seg); void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, enum X86Seg seg); -x68_segment_selector vmx_read_segment_selector(struct CPUState *cpu, +x68_segment_selector vmx_read_segment_selector(CPUState *cpu, enum X86Seg seg); -void vmx_write_segment_selector(struct CPUState *cpu, +void vmx_write_segment_selector(CPUState *cpu, x68_segment_selector selector, enum X86Seg seg); -uint64_t vmx_read_segment_base(struct CPUState *cpu, enum X86Seg seg); -void vmx_write_segment_base(struct CPUState *cpu, enum X86Seg seg, +uint64_t vmx_read_segment_base(CPUState *cpu, enum X86Seg seg); +void vmx_write_segment_base(CPUState *cpu, enum X86Seg seg, uint64_t base); -void x86_segment_descriptor_to_vmx(struct CPUState *cpu, +void x86_segment_descriptor_to_vmx(CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc); uint32_t vmx_read_segment_limit(CPUState *cpu, enum X86Seg seg); uint32_t vmx_read_segment_ar(CPUState *cpu, enum X86Seg seg); -void vmx_segment_to_x86_descriptor(struct CPUState *cpu, +void vmx_segment_to_x86_descriptor(CPUState *cpu, struct vmx_segment *vmx_desc, struct x86_segment_descriptor *desc); diff --git a/target/i386/hvf/x86_emu.h b/target/i386/hvf/x86_emu.h index 4b846ba80e..8bd97608c4 100644 --- a/target/i386/hvf/x86_emu.h +++ b/target/i386/hvf/x86_emu.h @@ -26,8 +26,8 @@ void init_emu(void); bool exec_instruction(CPUX86State *env, struct x86_decode *ins); -void load_regs(struct CPUState *cpu); -void store_regs(struct CPUState *cpu); +void load_regs(CPUState *cpu); +void store_regs(CPUState *cpu); void simulate_rdmsr(CPUX86State *env); void simulate_wrmsr(CPUX86State *env); diff --git a/target/i386/hvf/x86_mmu.h b/target/i386/hvf/x86_mmu.h index 9ae8a548de..9447ae072c 100644 --- a/target/i386/hvf/x86_mmu.h +++ b/target/i386/hvf/x86_mmu.h @@ -36,9 +36,9 @@ #define MMU_PAGE_US (1 << 2) #define MMU_PAGE_NX (1 << 3) -bool mmu_gva_to_gpa(struct CPUState *cpu, target_ulong gva, uint64_t *gpa); +bool mmu_gva_to_gpa(CPUState *cpu, target_ulong gva, uint64_t *gpa); -void vmx_write_mem(struct CPUState *cpu, target_ulong gva, void *data, int bytes); -void vmx_read_mem(struct CPUState *cpu, void *data, target_ulong gva, int bytes); +void vmx_write_mem(CPUState *cpu, target_ulong gva, void *data, int bytes); +void vmx_read_mem(CPUState *cpu, void *data, target_ulong gva, int bytes); #endif /* X86_MMU_H */ diff --git a/target/i386/hvf/x86.c b/target/i386/hvf/x86.c index 8ceea6398e..80e36136d0 100644 --- a/target/i386/hvf/x86.c +++ b/target/i386/hvf/x86.c @@ -46,7 +46,7 @@ return ar; }*/ -bool x86_read_segment_descriptor(struct CPUState *cpu, +bool x86_read_segment_descriptor(CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel) { @@ -76,7 +76,7 @@ bool x86_read_segment_descriptor(struct CPUState *cpu, return true; } -bool x86_write_segment_descriptor(struct CPUState *cpu, +bool x86_write_segment_descriptor(CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel) { @@ -99,7 +99,7 @@ bool x86_write_segment_descriptor(struct CPUState *cpu, return true; } -bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc, +bool x86_read_call_gate(CPUState *cpu, struct x86_call_gate *idt_desc, int gate) { target_ulong base = rvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_BASE); @@ -115,30 +115,30 @@ bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc, return true; } -bool x86_is_protected(struct CPUState *cpu) +bool x86_is_protected(CPUState *cpu) { uint64_t cr0 = rvmcs(cpu->accel->fd, VMCS_GUEST_CR0); return cr0 & CR0_PE_MASK; } -bool x86_is_real(struct CPUState *cpu) +bool x86_is_real(CPUState *cpu) { return !x86_is_protected(cpu); } -bool x86_is_v8086(struct CPUState *cpu) +bool x86_is_v8086(CPUState *cpu) { X86CPU *x86_cpu = X86_CPU(cpu); CPUX86State *env = &x86_cpu->env; return x86_is_protected(cpu) && (env->eflags & VM_MASK); } -bool x86_is_long_mode(struct CPUState *cpu) +bool x86_is_long_mode(CPUState *cpu) { return rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA; } -bool x86_is_long64_mode(struct CPUState *cpu) +bool x86_is_long64_mode(CPUState *cpu) { struct vmx_segment desc; vmx_read_segment_descriptor(cpu, &desc, R_CS); @@ -146,24 +146,24 @@ bool x86_is_long64_mode(struct CPUState *cpu) return x86_is_long_mode(cpu) && ((desc.ar >> 13) & 1); } -bool x86_is_paging_mode(struct CPUState *cpu) +bool x86_is_paging_mode(CPUState *cpu) { uint64_t cr0 = rvmcs(cpu->accel->fd, VMCS_GUEST_CR0); return cr0 & CR0_PG_MASK; } -bool x86_is_pae_enabled(struct CPUState *cpu) +bool x86_is_pae_enabled(CPUState *cpu) { uint64_t cr4 = rvmcs(cpu->accel->fd, VMCS_GUEST_CR4); return cr4 & CR4_PAE_MASK; } -target_ulong linear_addr(struct CPUState *cpu, target_ulong addr, X86Seg seg) +target_ulong linear_addr(CPUState *cpu, target_ulong addr, X86Seg seg) { return vmx_read_segment_base(cpu, seg) + addr; } -target_ulong linear_addr_size(struct CPUState *cpu, target_ulong addr, int size, +target_ulong linear_addr_size(CPUState *cpu, target_ulong addr, int size, X86Seg seg) { switch (size) { @@ -179,7 +179,7 @@ target_ulong linear_addr_size(struct CPUState *cpu, target_ulong addr, int size, return linear_addr(cpu, addr, seg); } -target_ulong linear_rip(struct CPUState *cpu, target_ulong rip) +target_ulong linear_rip(CPUState *cpu, target_ulong rip) { return linear_addr(cpu, rip, R_CS); } diff --git a/target/i386/hvf/x86_descr.c b/target/i386/hvf/x86_descr.c index c2d2e9ee84..f33836d6cb 100644 --- a/target/i386/hvf/x86_descr.c +++ b/target/i386/hvf/x86_descr.c @@ -67,12 +67,12 @@ x68_segment_selector vmx_read_segment_selector(CPUState *cpu, X86Seg seg) return sel; } -void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector selector, X86Seg seg) +void vmx_write_segment_selector(CPUState *cpu, x68_segment_selector selector, X86Seg seg) { wvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector, selector.sel); } -void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment *desc, X86Seg seg) +void vmx_read_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, X86Seg seg) { desc->sel = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector); desc->base = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].base); @@ -90,7 +90,9 @@ void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, X86Se wvmcs(cpu->accel->fd, sf->ar_bytes, desc->ar); } -void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc) +void x86_segment_descriptor_to_vmx(CPUState *cpu, x68_segment_selector selector, + struct x86_segment_descriptor *desc, + struct vmx_segment *vmx_desc) { vmx_desc->sel = selector.sel; vmx_desc->base = x86_segment_base(desc); @@ -107,7 +109,8 @@ void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selector se desc->type; } -void vmx_segment_to_x86_descriptor(struct CPUState *cpu, struct vmx_segment *vmx_desc, struct x86_segment_descriptor *desc) +void vmx_segment_to_x86_descriptor(CPUState *cpu, struct vmx_segment *vmx_desc, + struct x86_segment_descriptor *desc) { x86_set_segment_limit(desc, vmx_desc->limit); x86_set_segment_base(desc, vmx_desc->base); diff --git a/target/i386/hvf/x86_mmu.c b/target/i386/hvf/x86_mmu.c index 8cd08622a1..649074a7d2 100644 --- a/target/i386/hvf/x86_mmu.c +++ b/target/i386/hvf/x86_mmu.c @@ -49,7 +49,7 @@ struct gpt_translation { bool exec_access; }; -static int gpt_top_level(struct CPUState *cpu, bool pae) +static int gpt_top_level(CPUState *cpu, bool pae) { if (!pae) { return 2; @@ -73,7 +73,7 @@ static inline int pte_size(bool pae) } -static bool get_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, +static bool get_pt_entry(CPUState *cpu, struct gpt_translation *pt, int level, bool pae) { int index; @@ -95,7 +95,7 @@ static bool get_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, } /* test page table entry */ -static bool test_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, +static bool test_pt_entry(CPUState *cpu, struct gpt_translation *pt, int level, bool *is_large, bool pae) { uint64_t pte = pt->pte[level]; @@ -166,7 +166,7 @@ static inline uint64_t large_page_gpa(struct gpt_translation *pt, bool pae) -static bool walk_gpt(struct CPUState *cpu, target_ulong addr, int err_code, +static bool walk_gpt(CPUState *cpu, target_ulong addr, int err_code, struct gpt_translation *pt, bool pae) { int top_level, level; @@ -205,7 +205,7 @@ static bool walk_gpt(struct CPUState *cpu, target_ulong addr, int err_code, } -bool mmu_gva_to_gpa(struct CPUState *cpu, target_ulong gva, uint64_t *gpa) +bool mmu_gva_to_gpa(CPUState *cpu, target_ulong gva, uint64_t *gpa) { bool res; struct gpt_translation pt; @@ -225,7 +225,7 @@ bool mmu_gva_to_gpa(struct CPUState *cpu, target_ulong gva, uint64_t *gpa) return false; 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[209.51.188.17]) by mx.google.com with ESMTPS id x12-20020a05622a000c00b0042c0509f5e9si7475560qtw.324.2024.03.12.05.52.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:52:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=bggdwVil; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1Xh-00005K-0T; Tue, 12 Mar 2024 08:47:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VI-0004bo-IK for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:16 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VB-0000ag-9R for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247504; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=03aM9ZkSlQzTFx1pPNJmZ+WHNGA5kWbpYfHnIYTnn7w=; b=bggdwVil89ZqR6lgLAfwqyQm4BTRy17kVDnOP02kHBnO3kLzTCCmtKuYWRs4xtxnXAi5Rk KcntYir3cREAkOPDTZnshVHiBamZCVxnF+PUsnYZz3DFUSLlD0xB+7XMFqBQV8dgFyFPZ4 7LpwGR+h+TpYl25snHKGlyAnqIynWmc= Received: from mimecast-mx02.redhat.com (mx-ext.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-390-HGlgJFTGP1Cvx2s0O71RCw-1; Tue, 12 Mar 2024 08:45:03 -0400 X-MC-Unique: HGlgJFTGP1Cvx2s0O71RCw-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id CEA36386A0A9; Tue, 12 Mar 2024 12:45:02 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id B681F492BC4; Tue, 12 Mar 2024 12:45:01 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Richard Henderson Subject: [PULL 43/55] target/loongarch: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Tue, 12 Mar 2024 13:43:27 +0100 Message-ID: <20240312124339.761630-44-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20240129164514.73104-16-philmd@linaro.org> Reviewed-by: Richard Henderson [thuth: Adjusted patch for hunk that moved to cpu_helper.c] Signed-off-by: Thomas Huth --- target/loongarch/cpu.c | 39 ++++++++--------------------- target/loongarch/cpu_helper.c | 3 +-- target/loongarch/gdbstub.c | 6 ++--- target/loongarch/kvm/kvm.c | 41 +++++++++---------------------- target/loongarch/tcg/tlb_helper.c | 3 +-- 5 files changed, 26 insertions(+), 66 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index e935c79b68..f6ffb3aadb 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -91,18 +91,12 @@ void G_NORETURN do_raise_exception(CPULoongArchState *env, static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) { - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; - - set_pc(env, value); + set_pc(cpu_env(cs), value); } static vaddr loongarch_cpu_get_pc(CPUState *cs) { - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; - - return env->pc; + return cpu_env(cs)->pc; } #ifndef CONFIG_USER_ONLY @@ -157,8 +151,7 @@ static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) #ifndef CONFIG_USER_ONLY static void loongarch_cpu_do_interrupt(CPUState *cs) { - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); bool update_badinstr = 1; int cause = -1; const char *name; @@ -308,8 +301,7 @@ static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, MemTxResult response, uintptr_t retaddr) { - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); if (access_type == MMU_INST_FETCH) { do_raise_exception(env, EXCCODE_ADEF, retaddr); @@ -321,8 +313,7 @@ static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); if (cpu_loongarch_hw_interrupts_enabled(env) && cpu_loongarch_hw_interrupts_pending(env)) { @@ -339,21 +330,15 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request) static void loongarch_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); - set_pc(env, tb->pc); + set_pc(cpu_env(cs), tb->pc); } static void loongarch_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; - - set_pc(env, data[0]); + set_pc(cpu_env(cs), data[0]); } #endif /* CONFIG_TCG */ @@ -362,12 +347,10 @@ static bool loongarch_cpu_has_work(CPUState *cs) #ifdef CONFIG_USER_ONLY return true; #else - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; bool has_work = false; if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && - cpu_loongarch_hw_interrupts_pending(env)) { + cpu_loongarch_hw_interrupts_pending(cpu_env(cs))) { has_work = true; } @@ -509,9 +492,8 @@ static void loongarch_max_initfn(Object *obj) static void loongarch_cpu_reset_hold(Object *obj) { CPUState *cs = CPU(obj); - LoongArchCPU *cpu = LOONGARCH_CPU(cs); LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(obj); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); if (lacc->parent_phases.hold) { lacc->parent_phases.hold(obj); @@ -694,8 +676,7 @@ static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); int i; qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 45f821d086..960eec9567 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -218,8 +218,7 @@ int get_physical_address(CPULoongArchState *env, hwaddr *physical, hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); hwaddr phys_addr; int prot; diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c index 22c6889011..a0e1439bd0 100644 --- a/target/loongarch/gdbstub.c +++ b/target/loongarch/gdbstub.c @@ -33,8 +33,7 @@ void write_fcc(CPULoongArchState *env, uint64_t val) int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); uint64_t val; if (0 <= n && n < 32) { @@ -60,8 +59,7 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); target_ulong tmp; int read_length; int length = 0; diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c index c19978a970..df5e199860 100644 --- a/target/loongarch/kvm/kvm.c +++ b/target/loongarch/kvm/kvm.c @@ -38,8 +38,7 @@ static int kvm_loongarch_get_regs_core(CPUState *cs) int ret = 0; int i; struct kvm_regs regs; - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); /* Get the current register set as KVM seems it */ ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); @@ -62,8 +61,7 @@ static int kvm_loongarch_put_regs_core(CPUState *cs) int ret = 0; int i; struct kvm_regs regs; - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); /* Set the registers based on QEMU's view of things */ for (i = 0; i < 32; i++) { @@ -82,8 +80,7 @@ static int kvm_loongarch_put_regs_core(CPUState *cs) static int kvm_loongarch_get_csr(CPUState *cs) { int ret = 0; - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); ret |= kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CRMD), &env->CSR_CRMD); @@ -253,8 +250,7 @@ static int kvm_loongarch_get_csr(CPUState *cs) static int kvm_loongarch_put_csr(CPUState *cs, int level) { int ret = 0; - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); ret |= kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CRMD), &env->CSR_CRMD); @@ -430,9 +426,7 @@ static int kvm_loongarch_get_regs_fp(CPUState *cs) { int ret, i; struct kvm_fpu fpu; - - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); ret = kvm_vcpu_ioctl(cs, KVM_GET_FPU, &fpu); if (ret < 0) { @@ -456,9 +450,7 @@ static int kvm_loongarch_put_regs_fp(CPUState *cs) { int ret, i; struct kvm_fpu fpu; - - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); fpu.fcsr = env->fcsr0; fpu.fcc = 0; @@ -487,8 +479,7 @@ static int kvm_loongarch_get_mpstate(CPUState *cs) { int ret = 0; struct kvm_mp_state mp_state; - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); if (cap_has_mp_state) { ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state); @@ -505,12 +496,8 @@ static int kvm_loongarch_get_mpstate(CPUState *cs) static int kvm_loongarch_put_mpstate(CPUState *cs) { int ret = 0; - - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; - struct kvm_mp_state mp_state = { - .mp_state = env->mp_state + .mp_state = cpu_env(cs)->mp_state }; if (cap_has_mp_state) { @@ -527,8 +514,7 @@ static int kvm_loongarch_get_cpucfg(CPUState *cs) { int i, ret = 0; uint64_t val; - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); for (i = 0; i < 21; i++) { ret = kvm_get_one_reg(cs, KVM_IOC_CPUCFG(i), &val); @@ -549,8 +535,7 @@ static int kvm_check_cpucfg2(CPUState *cs) .attr = 2, .addr = (uint64_t)&val, }; - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); ret = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr); @@ -575,8 +560,7 @@ static int kvm_check_cpucfg2(CPUState *cs) static int kvm_loongarch_put_cpucfg(CPUState *cs) { int i, ret = 0; - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); uint64_t val; for (i = 0; i < 21; i++) { @@ -758,8 +742,7 @@ bool kvm_arch_cpu_check_are_resettable(void) int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) { int ret = 0; - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); MemTxAttrs attrs = {}; attrs.requester_id = env_cpu(env)->cpu_index; diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index a08c08b05a..22be031ac7 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -449,8 +449,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - LoongArchCPU *cpu = LOONGARCH_CPU(cs); - CPULoongArchState *env = &cpu->env; + CPULoongArchState *env = cpu_env(cs); hwaddr physical; int prot; int ret; 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[209.51.188.17]) by mx.google.com with ESMTPS id c24-20020ae9e218000000b00787ccc153b9si7272433qkc.192.2024.03.12.05.52.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:52:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=Si13aIjS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1XG-0007eP-Np; Tue, 12 Mar 2024 08:47:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VK-0004eP-9w for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:16 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VG-0000bR-6g for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:14 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247508; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=c5lHu+U43t6L8WpuhAtWEE4Tx07L6LU4E0h1kK66uE8=; b=Si13aIjSDiKuG3i9Z36FMlcvK64UhZ9DFEv8QhMp8yhJ1UZC1QSucqsLbZJ5EQxgxRr/HV IsRSwv3e73WRAsmCNjwyVx12hnnh4lWgi3jGcZNY1lCmai/cmokveydmgLTNDDTIadPx+4 tL3m381zUjHL4q9vPDhkoM5glnpLLuo= Received: from mimecast-mx02.redhat.com (mx-ext.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-428-KL6iIMSfNnWewChIA9WDSA-1; Tue, 12 Mar 2024 08:45:04 -0400 X-MC-Unique: KL6iIMSfNnWewChIA9WDSA-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 3633D1C41A19; Tue, 12 Mar 2024 12:45:04 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1C8B8492BC4; Tue, 12 Mar 2024 12:45:02 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Richard Henderson Subject: [PULL 44/55] target/m68k: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Tue, 12 Mar 2024 13:43:28 +0100 Message-ID: <20240312124339.761630-45-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20240129164514.73104-17-philmd@linaro.org> Signed-off-by: Thomas Huth --- target/m68k/cpu.c | 33 +++++++++++---------------------- target/m68k/gdbstub.c | 6 ++---- target/m68k/helper.c | 6 ++---- target/m68k/m68k-semi.c | 6 ++---- target/m68k/op_helper.c | 11 +++-------- target/m68k/translate.c | 3 +-- 6 files changed, 21 insertions(+), 44 deletions(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 9cc1de567f..7c8efbb42c 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -74,9 +74,8 @@ static void m68k_unset_feature(CPUM68KState *env, int feature) static void m68k_cpu_reset_hold(Object *obj) { CPUState *cs = CPU(obj); - M68kCPU *cpu = M68K_CPU(cs); M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(cs); floatx80 nan = floatx80_default_nan(NULL); int i; @@ -122,8 +121,7 @@ static ObjectClass *m68k_cpu_class_by_name(const char *cpu_model) static void m5206_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); m68k_set_feature(env, M68K_FEATURE_MOVEFROMSR_PRIV); @@ -132,8 +130,7 @@ static void m5206_cpu_initfn(Object *obj) /* Base feature set, including isns. for m68k family */ static void m68000_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68k_set_feature(env, M68K_FEATURE_M68K); m68k_set_feature(env, M68K_FEATURE_USP); @@ -147,8 +144,7 @@ static void m68000_cpu_initfn(Object *obj) */ static void m68010_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68000_cpu_initfn(obj); m68k_set_feature(env, M68K_FEATURE_M68010); @@ -168,8 +164,7 @@ static void m68010_cpu_initfn(Object *obj) */ static void m68020_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68010_cpu_initfn(obj); m68k_unset_feature(env, M68K_FEATURE_M68010); @@ -199,8 +194,7 @@ static void m68020_cpu_initfn(Object *obj) */ static void m68030_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68020_cpu_initfn(obj); m68k_unset_feature(env, M68K_FEATURE_M68020); @@ -226,8 +220,7 @@ static void m68030_cpu_initfn(Object *obj) */ static void m68040_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68030_cpu_initfn(obj); m68k_unset_feature(env, M68K_FEATURE_M68030); @@ -247,8 +240,7 @@ static void m68040_cpu_initfn(Object *obj) */ static void m68060_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68040_cpu_initfn(obj); m68k_unset_feature(env, M68K_FEATURE_M68040); @@ -261,8 +253,7 @@ static void m68060_cpu_initfn(Object *obj) static void m5208_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); m68k_set_feature(env, M68K_FEATURE_CF_ISA_APLUSC); @@ -274,8 +265,7 @@ static void m5208_cpu_initfn(Object *obj) static void cfv4e_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); m68k_set_feature(env, M68K_FEATURE_CF_ISA_B); @@ -288,8 +278,7 @@ static void cfv4e_cpu_initfn(Object *obj) static void any_cpu_initfn(Object *obj) { - M68kCPU *cpu = M68K_CPU(obj); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(CPU(obj)); m68k_set_feature(env, M68K_FEATURE_CF_ISA_A); m68k_set_feature(env, M68K_FEATURE_CF_ISA_B); diff --git a/target/m68k/gdbstub.c b/target/m68k/gdbstub.c index 1e5f033a12..15547e2313 100644 --- a/target/m68k/gdbstub.c +++ b/target/m68k/gdbstub.c @@ -23,8 +23,7 @@ int m68k_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(cs); if (n < 8) { /* D0-D7 */ @@ -50,8 +49,7 @@ int m68k_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int m68k_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(cs); uint32_t tmp; tmp = ldl_p(mem_buf); diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 44b245884e..1a475f082a 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -906,8 +906,7 @@ txfail: hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(cs); hwaddr phys_addr; int prot; int access_type; @@ -955,8 +954,7 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType qemu_access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(cs); hwaddr physical; int prot; int access_type; diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c index b4ffb70f8b..546cff2246 100644 --- a/target/m68k/m68k-semi.c +++ b/target/m68k/m68k-semi.c @@ -77,8 +77,7 @@ static int host_to_gdb_errno(int err) static void m68k_semi_u32_cb(CPUState *cs, uint64_t ret, int err) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(cs); target_ulong args = env->dregs[1]; if (put_user_u32(ret, args) || @@ -95,8 +94,7 @@ static void m68k_semi_u32_cb(CPUState *cs, uint64_t ret, int err) static void m68k_semi_u64_cb(CPUState *cs, uint64_t ret, int err) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(cs); target_ulong args = env->dregs[1]; if (put_user_u32(ret >> 32, args) || diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 956e76eb5f..125f6c1b08 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -441,10 +441,7 @@ static void do_interrupt_all(CPUM68KState *env, int is_hw) void m68k_cpu_do_interrupt(CPUState *cs) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; - - do_interrupt_all(env, 0); + do_interrupt_all(cpu_env(cs), 0); } static inline void do_interrupt_m68k_hardirq(CPUM68KState *env) @@ -457,8 +454,7 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(cs); cpu_restore_state(cs, retaddr); @@ -511,8 +507,7 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - M68kCPU *cpu = M68K_CPU(cs); - CPUM68KState *env = &cpu->env; + CPUM68KState *env = cpu_env(cs); if (interrupt_request & CPU_INTERRUPT_HARD && ((env->sr & SR_I) >> SR_I_SHIFT) < env->pending_level) { diff --git a/target/m68k/translate.c b/target/m68k/translate.c index d7d5ff4300..6ae3df43bc 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6100,8 +6100,7 @@ static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low) void m68k_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - M68kCPU *cpu = M68K_CPU(cs); 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[209.51.188.17]) by mx.google.com with ESMTPS id j19-20020a05620a147300b0078875de472asi2589663qkl.482.2024.03.12.05.52.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:52:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=hoYr82GQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1Xw-0000Rs-7x; Tue, 12 Mar 2024 08:47:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VK-0004eQ-9s for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:16 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VI-0000bZ-3Y for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:14 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247509; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xXkoorxlTSEReqUP0thEsel8IhSLhhmlljcP3i1qTlY=; b=hoYr82GQA2xwQYTmtkr/NhNSBeaVAZo0YOYJJ5J3X8CMFPH7zBDp5BfqyKWY2qi3vYJ6j+ TrWcEc6VAYX2GOQYo0fdUKQXRld64XenMRzHKaJ3TvTI3U9BTn37nBjL0fp6xHj6FCw8o0 MtU7pMyTqjocA7j4pyJiQtyurheL9DM= Received: from mimecast-mx02.redhat.com (mx-ext.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-599-fuQxiqVOPj-Uykq2VpXB-A-1; Tue, 12 Mar 2024 08:45:06 -0400 X-MC-Unique: fuQxiqVOPj-Uykq2VpXB-A-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id A77A5386A0A7; Tue, 12 Mar 2024 12:45:05 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id AF0FA492BC4; Tue, 12 Mar 2024 12:45:04 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Richard Henderson Subject: [PULL 45/55] target/microblaze: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Tue, 12 Mar 2024 13:43:29 +0100 Message-ID: <20240312124339.761630-46-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20240129164514.73104-18-philmd@linaro.org> Signed-off-by: Thomas Huth --- target/microblaze/gdbstub.c | 3 +-- target/microblaze/helper.c | 3 +-- target/microblaze/translate.c | 6 ++---- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index eb168d1007..09d74e164d 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -110,9 +110,8 @@ int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *mem_buf, int n) int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUClass *cc = CPU_GET_CLASS(cs); - CPUMBState *env = &cpu->env; + CPUMBState *env = cpu_env(cs); uint32_t tmp; if (n > cc->gdb_num_core_regs) { diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 460eee0cf5..d25c9eb4d3 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -252,8 +252,7 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - CPUMBState *env = &cpu->env; + CPUMBState *env = cpu_env(cs); if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->msr & MSR_IE) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a465c2d245..4e52ef32db 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1630,7 +1630,6 @@ static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs) static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) { DisasContext *dc = container_of(dcb, DisasContext, base); - CPUMBState *env = cpu_env(cs); uint32_t ir; /* TODO: This should raise an exception, not terminate qemu. */ @@ -1641,7 +1640,7 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) dc->tb_flags_to_set = 0; - ir = cpu_ldl_code(env, dc->base.pc_next); + ir = cpu_ldl_code(cpu_env(cs), dc->base.pc_next); if (!decode(dc, ir)) { trap_illegal(dc, true); } @@ -1800,8 +1799,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - CPUMBState *env = &cpu->env; + CPUMBState *env = cpu_env(cs); uint32_t iflags; int i; From patchwork Tue Mar 12 12:43:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 779706 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2000039wrt; Tue, 12 Mar 2024 05:48:34 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXU4wB2EUjlyY1WCPgbqyeZXaL4RrDmQykInEPCiNpXxjOu3ZXUhHYBdGmO/BCUTVV5vVJYfEo57475uOLIl0SD X-Google-Smtp-Source: AGHT+IF1izgrVFi5S9f4S8AdhDWql1Lf/WvV40LcLOVbbsXuVFVe2kX3sbmQDatv2CyMa1bo/XER X-Received: by 2002:a05:6808:1a02:b0:3c2:5184:6972 with SMTP id bk2-20020a0568081a0200b003c251846972mr4421893oib.1.1710247714085; Tue, 12 Mar 2024 05:48:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1710247714; cv=none; d=google.com; s=arc-20160816; b=pT5rjVNSV2FsuEpD0arr1iPy8g/EnmGUT7BCKnQbKpxTGoHdyxAtZhXFXMAwlx6iQg qYjnpRXCaDb7TXCHVlrcElPx3bh+3sjmkTkKsR2B9Ikd3ZgU3bM2tfiC6vYmmL0ROkR1 MahPkflJI45N1t0IyqTdqO8UMP3gGt4a4qLRUG9rwMBY06fIk61qaYTwl6AejjOIxTj8 3mGmmFtndJAwRAm+h+Xk5qPfXHmijJQRHkg60HOjeKeykfkWHWqNakYDvuGZW//01W+i G8SFgE3N4ytDUkitsMGjQIJH0qkX8f0sNYiRdbDB/RrjV0WXRw7gfbzAQRCi4/qLcKnC CscA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=j7I6jHo21DMFd87Ral8MDWR+mZHxqH8tAK1NYyYQ85A=; fh=MVtmONGgcwaswePOsQaFbzD/JigNLxHXgB5l4X9593E=; b=LMIMv3H4/2t/97pc4+u5G4NSW2FSD82pHH/t4UUGGRWTXstIuCteBM06SLe/W52Zuc Ku2MXwemvExYsH+fNIX6RhqBOyaBaK2Y4vBEOn5or7eKWE/AnPRSMRyovSUM4NTqC8fk B8VAef2Fxy6SLxtEDnlo1cMHBYw5TvoC/lrjBq1cM/LBGnFGy9VHVZpcGJOzKlBsttBc SxHYF/hDufkxhIz+w4cBPGlLRXAXfQqbcVvn8eq6cIKhMiTdRSqm8tWTKlEKLSavTgU+ 8Rg8Z9DLjqipHa1H8C77isVjc5WCw9bsuPa3qQj0zpE3weGTIUIlrS3myuR29nokxgaB 9I8g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b="XytPF/S9"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-ID: <20240129164514.73104-19-philmd@linaro.org> Signed-off-by: Thomas Huth --- target/mips/cpu.c | 15 ++++---------- target/mips/gdbstub.c | 6 ++---- target/mips/kvm.c | 27 +++++++++---------------- target/mips/sysemu/physaddr.c | 3 +-- target/mips/tcg/exception.c | 3 +-- target/mips/tcg/op_helper.c | 8 +++----- target/mips/tcg/sysemu/special_helper.c | 3 +-- target/mips/tcg/sysemu/tlb_helper.c | 6 ++---- target/mips/tcg/translate.c | 3 +-- 9 files changed, 24 insertions(+), 50 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 98ef073631..8d8f690a53 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -80,8 +80,7 @@ static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); int i; qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx @@ -123,9 +122,7 @@ void cpu_set_exception_base(int vp_index, target_ulong address) static void mips_cpu_set_pc(CPUState *cs, vaddr value) { - MIPSCPU *cpu = MIPS_CPU(cs); - - mips_env_set_pc(&cpu->env, value); + mips_env_set_pc(cpu_env(cs), value); } static vaddr mips_cpu_get_pc(CPUState *cs) @@ -137,8 +134,7 @@ static vaddr mips_cpu_get_pc(CPUState *cs) static bool mips_cpu_has_work(CPUState *cs) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); bool has_work = false; /* @@ -433,10 +429,7 @@ static void mips_cpu_reset_hold(Object *obj) static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) { - MIPSCPU *cpu = MIPS_CPU(s); - CPUMIPSState *env = &cpu->env; - - if (!(env->insn_flags & ISA_NANOMIPS32)) { + if (!(cpu_env(s)->insn_flags & ISA_NANOMIPS32)) { #if TARGET_BIG_ENDIAN info->print_insn = print_insn_big_mips; #else diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index 62d7b72407..169d47416a 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -25,8 +25,7 @@ int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); if (n < 32) { return gdb_get_regl(mem_buf, env->active_tc.gpr[n]); @@ -78,8 +77,7 @@ int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); target_ulong tmp; tmp = ldtul_p(mem_buf); diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 15d0cf9adb..6c52e59f55 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -63,8 +63,7 @@ int kvm_arch_irqchip_create(KVMState *s) int kvm_arch_init_vcpu(CPUState *cs) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); int ret = 0; qemu_add_vm_change_state_handler(kvm_mips_update_state, cs); @@ -460,8 +459,7 @@ static inline int kvm_mips_change_one_reg(CPUState *cs, uint64_t reg_id, */ static int kvm_mips_save_count(CPUState *cs) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); uint64_t count_ctl; int err, ret = 0; @@ -502,8 +500,7 @@ static int kvm_mips_save_count(CPUState *cs) */ static int kvm_mips_restore_count(CPUState *cs) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); uint64_t count_ctl; int err_dc, err, ret = 0; @@ -590,8 +587,7 @@ static void kvm_mips_update_state(void *opaque, bool running, RunState state) static int kvm_mips_put_fpu_registers(CPUState *cs, int level) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); int err, ret = 0; unsigned int i; @@ -670,8 +666,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int level) static int kvm_mips_get_fpu_registers(CPUState *cs) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); int err, ret = 0; unsigned int i; @@ -751,8 +746,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs) static int kvm_mips_put_cp0_registers(CPUState *cs, int level) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); int err, ret = 0; (void)level; @@ -974,8 +968,7 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level) static int kvm_mips_get_cp0_registers(CPUState *cs) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); int err, ret = 0; err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); @@ -1181,8 +1174,7 @@ static int kvm_mips_get_cp0_registers(CPUState *cs) int kvm_arch_put_registers(CPUState *cs, int level) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); struct kvm_regs regs; int ret; int i; @@ -1217,8 +1209,7 @@ int kvm_arch_put_registers(CPUState *cs, int level) int kvm_arch_get_registers(CPUState *cs) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); int ret = 0; struct kvm_regs regs; int i; diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c index 13c8bc8f47..5c5184e136 100644 --- a/target/mips/sysemu/physaddr.c +++ b/target/mips/sysemu/physaddr.c @@ -230,8 +230,7 @@ int get_physical_address(CPUMIPSState *env, hwaddr *physical, hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); hwaddr phys_addr; int prot; diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c index da49a93912..13275d1ded 100644 --- a/target/mips/tcg/exception.c +++ b/target/mips/tcg/exception.c @@ -79,8 +79,7 @@ void helper_wait(CPUMIPSState *env) void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); env->active_tc.PC = tb->pc; diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c index 98935b5e64..65403f1a87 100644 --- a/target/mips/tcg/op_helper.c +++ b/target/mips/tcg/op_helper.c @@ -279,8 +279,7 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); int error_code = 0; int excp; @@ -306,9 +305,8 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr) { - MIPSCPU *cpu = MIPS_CPU(cs); - MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); - CPUMIPSState *env = &cpu->env; + MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cs); + CPUMIPSState *env = cpu_env(cs); if (access_type == MMU_INST_FETCH) { do_raise_exception(env, EXCP_IBE, retaddr); diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/sysemu/special_helper.c index 518d3fbc34..5baa25348e 100644 --- a/target/mips/tcg/sysemu/special_helper.c +++ b/target/mips/tcg/sysemu/special_helper.c @@ -90,8 +90,7 @@ static void debug_post_eret(CPUMIPSState *env) bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && !(cs->tcg_cflags & CF_PCREL) && env->active_tc.PC != tb->pc) { diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index cdae42ffdd..119eae771e 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -906,8 +906,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); hwaddr physical; int prot; int ret = TLBRET_BADADDR; @@ -1340,8 +1339,7 @@ void mips_cpu_do_interrupt(CPUState *cs) bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); if (cpu_mips_hw_interrupts_enabled(env) && cpu_mips_hw_interrupts_pending(env)) { diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 3ba2101647..06c108cc9c 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15566,8 +15566,7 @@ void mips_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; + CPUMIPSState *env = cpu_env(cs); env->active_tc.PC = data[0]; env->hflags &= ~MIPS_HFLAG_BMASK; From patchwork Tue Mar 12 12:43:31 2024 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id dv11-20020a05620a1b8b00b00787c0bd8f36si8165500qkb.333.2024.03.12.05.58.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:58:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=PxcGU3pv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1VW-0005Og-Rb; Tue, 12 Mar 2024 08:45:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VN-0004iu-9T for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:17 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VK-0000e0-Uy for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:16 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247514; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2xkv1d+pDqlLaGpZUXCqazMlAaMszsBS0Rn/yJvBmLk=; b=PxcGU3pvIwwpHVS+zJkacqSL8WHS2CzbxTXxI5obcrsyB3FvTj8QEe6tA1nC0eFSLd6epV jXs4r2KzWSa9UnVIJtPo9AREKDM698exvi4Fyc4r5P/KOr33sAImdHHDg9z/TlguU/0qi4 4GJOZB8pfu4AfoeAPlFxeHzVpyt3LOk= Received: from mimecast-mx02.redhat.com (mx-ext.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-198-LOVkDdj0Md61OUOd-lX6Fg-1; Tue, 12 Mar 2024 08:45:08 -0400 X-MC-Unique: LOVkDdj0Md61OUOd-lX6Fg-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 89CF31C41A0B; Tue, 12 Mar 2024 12:45:08 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1CA21492BC4; Tue, 12 Mar 2024 12:45:06 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Richard Henderson Subject: [PULL 47/55] target/nios2: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Tue, 12 Mar 2024 13:43:31 +0100 Message-ID: <20240312124339.761630-48-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20240129164514.73104-20-philmd@linaro.org> Signed-off-by: Thomas Huth --- target/nios2/cpu.c | 15 +++------------ target/nios2/helper.c | 3 +-- target/nios2/nios2-semi.c | 6 ++---- target/nios2/translate.c | 3 +-- 4 files changed, 7 insertions(+), 20 deletions(-) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index b10693618b..679aff5730 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -28,28 +28,19 @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value) { - Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; - - env->pc = value; + cpu_env(cs)->pc = value; } static vaddr nios2_cpu_get_pc(CPUState *cs) { - Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; - - return env->pc; + return cpu_env(cs)->pc; } static void nios2_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; - - env->pc = data[0]; + cpu_env(cs)->pc = data[0]; } static bool nios2_cpu_has_work(CPUState *cs) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index bb3b09e5a7..ac57121afc 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -287,8 +287,7 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; + CPUNios2State *env = cpu_env(cs); env->ctrl[CR_BADADDR] = addr; cs->exception_index = EXCP_UNALIGN; diff --git a/target/nios2/nios2-semi.c b/target/nios2/nios2-semi.c index 0b84fcb6b6..420702e293 100644 --- a/target/nios2/nios2-semi.c +++ b/target/nios2/nios2-semi.c @@ -75,8 +75,7 @@ static int host_to_gdb_errno(int err) static void nios2_semi_u32_cb(CPUState *cs, uint64_t ret, int err) { - Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; + CPUNios2State *env = cpu_env(cs); target_ulong args = env->regs[R_ARG1]; if (put_user_u32(ret, args) || @@ -93,8 +92,7 @@ static void nios2_semi_u32_cb(CPUState *cs, uint64_t ret, int err) static void nios2_semi_u64_cb(CPUState *cs, uint64_t ret, int err) { - Nios2CPU *cpu = NIOS2_CPU(cs); - CPUNios2State *env = &cpu->env; + CPUNios2State *env = cpu_env(cs); target_ulong args = env->regs[R_ARG1]; if (put_user_u32(ret >> 32, args) || diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 612556b297..7ddc6ac1a2 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -970,7 +970,6 @@ static void nios2_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); - CPUNios2State *env = cpu_env(cs); const Nios2Instruction *instr; uint32_t code, pc; uint8_t op; @@ -980,7 +979,7 @@ static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) dc->base.pc_next = pc + 4; /* Decode an instruction */ - code = cpu_ldl_code(env, pc); + code = cpu_ldl_code(cpu_env(cs), pc); op = get_opcode(code); if (unlikely(op >= ARRAY_SIZE(i_type_instructions))) { From patchwork Tue Mar 12 12:43:32 2024 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id ks30-20020a056214311e00b0069006d7edccsi7241816qvb.48.2024.03.12.05.53.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:53:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=GMiko05j; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1WY-0006Yk-BG; Tue, 12 Mar 2024 08:46:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VO-0004q7-Mm for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:19 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VL-0000e5-Dz for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247514; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xieoYGueSKQRx2dY4qb6pT/kLUxu+l9alBvnl/FYwuk=; b=GMiko05jsMlvha4nOLJZZ0EmXIq4D4Ys5JOJjYrL4bY4sUnTW9HYVA3L8vMrbs5y1eTv32 JQYLQ+BecadkEP2od9wZMR2C1J2f9oKsFT0loDRfJXemXIdzpMab3jzqlskbxbzxGWSQcV zgJSY2u4igZuF5f194lMsLW+iLhPauw= Received: from mimecast-mx02.redhat.com (mx-ext.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-679-X1DmHwTUPdilceCizWY65A-1; Tue, 12 Mar 2024 08:45:10 -0400 X-MC-Unique: X1DmHwTUPdilceCizWY65A-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 1B320386A0AC; Tue, 12 Mar 2024 12:45:10 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id D20CB492BC4; Tue, 12 Mar 2024 12:45:08 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Richard Henderson Subject: [PULL 48/55] target/openrisc: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Tue, 12 Mar 2024 13:43:32 +0100 Message-ID: <20240312124339.761630-49-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20240129164514.73104-21-philmd@linaro.org> Signed-off-by: Thomas Huth --- target/openrisc/gdbstub.c | 6 ++---- target/openrisc/interrupt.c | 6 ++---- target/openrisc/translate.c | 6 ++---- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c index d1074a0581..c2a77d5d4d 100644 --- a/target/openrisc/gdbstub.c +++ b/target/openrisc/gdbstub.c @@ -23,8 +23,7 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - CPUOpenRISCState *env = &cpu->env; + CPUOpenRISCState *env = cpu_env(cs); if (n < 32) { return gdb_get_reg32(mem_buf, cpu_get_gpr(env, n)); @@ -48,9 +47,8 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - OpenRISCCPU *cpu = OPENRISC_CPU(cs); CPUClass *cc = CPU_GET_CLASS(cs); - CPUOpenRISCState *env = &cpu->env; + CPUOpenRISCState *env = cpu_env(cs); uint32_t tmp; if (n > cc->gdb_num_core_regs) { diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index d4fdb8ce8e..b3b5b40577 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -29,8 +29,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) { - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - CPUOpenRISCState *env = &cpu->env; + CPUOpenRISCState *env = cpu_env(cs); int exception = cs->exception_index; env->epcr = env->pc; @@ -105,8 +104,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - CPUOpenRISCState *env = &cpu->env; + CPUOpenRISCState *env = cpu_env(cs); int idx = -1; if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) { diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 785bcb6552..23fff46084 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1564,8 +1564,7 @@ static void openrisc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - uint32_t insn = translator_ldl(&cpu->env, &dc->base, dc->base.pc_next); + uint32_t insn = translator_ldl(cpu_env(cs), &dc->base, dc->base.pc_next); if (!decode(dc, insn)) { gen_illegal_exception(dc); @@ -1668,8 +1667,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - CPUOpenRISCState *env = &cpu->env; + CPUOpenRISCState *env = cpu_env(cs); int i; qemu_fprintf(f, "PC=%08x\n", env->pc); From patchwork Tue Mar 12 12:43:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 779705 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp1999766wrt; Tue, 12 Mar 2024 05:47:55 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWgBib6yNKOkbT3HJQGZW+E96sZIP1a5VV2RetQCp7sR1ma8XDxPfFmIsN30XVzUHTvZpWGQ6C8HAXUCJVq4TL9 X-Google-Smtp-Source: AGHT+IFq+8od3rnMUyZt2csmZX9bP5Y9fLJhKOY6e9iayjULNulGvIUOi4lI7Hc5hqqg7680c/ii X-Received: by 2002:a05:620a:1346:b0:787:e5ed:4fb7 with SMTP id c6-20020a05620a134600b00787e5ed4fb7mr10141211qkl.25.1710247675782; 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[209.51.188.17]) by mx.google.com with ESMTPS id os18-20020a05620a811200b0078876151244si2422903qkn.441.2024.03.12.05.47.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:47:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b="K//7U/Dx"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1W6-00064J-Ox; Tue, 12 Mar 2024 08:46:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VP-0004rN-3t for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:19 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VL-0000dm-EJ for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247513; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dPBLvJtmZt/V5XmTVh2Kpqf3n4PfUcn0CyV12CErBiM=; b=K//7U/DxkwIRPwUCnshhSPq2tNTd/eY+2KtoDF2eSbANi9e4W8UawtiswBBx0GonT7PEkW aTfkXy2kB58IFDYaI03IxsH0tD4qVGJU7tIzceQ1YEWG7oR7FsJEc7A/p7b0AkiY33T2jX jOblX3GLM5ndDDnWEJgtW6bHyjCF+Ew= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-647-CrRMgCH4N-2ZMHDRVSNDXw-1; Tue, 12 Mar 2024 08:45:11 -0400 X-MC-Unique: CrRMgCH4N-2ZMHDRVSNDXw-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 5A57286C049; Tue, 12 Mar 2024 12:45:11 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id 59F96492BC4; Tue, 12 Mar 2024 12:45:10 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Richard Henderson Subject: [PULL 49/55] target/ppc: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Tue, 12 Mar 2024 13:43:33 +0100 Message-ID: <20240312124339.761630-50-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20240129164514.73104-22-philmd@linaro.org> Signed-off-by: Thomas Huth --- hw/ppc/mpc8544_guts.c | 3 +-- hw/ppc/pnv.c | 3 +-- hw/ppc/pnv_xscom.c | 5 +---- hw/ppc/ppce500_spin.c | 3 +-- hw/ppc/spapr.c | 3 +-- hw/ppc/spapr_caps.c | 7 ++----- target/ppc/cpu_init.c | 11 +++-------- target/ppc/excp_helper.c | 3 +-- target/ppc/gdbstub.c | 12 ++++-------- target/ppc/kvm.c | 12 ++++-------- target/ppc/ppc-qmp-cmds.c | 3 +-- target/ppc/user_only_helper.c | 3 +-- 12 files changed, 21 insertions(+), 47 deletions(-) diff --git a/hw/ppc/mpc8544_guts.c b/hw/ppc/mpc8544_guts.c index a26e83d048..e3540b0281 100644 --- a/hw/ppc/mpc8544_guts.c +++ b/hw/ppc/mpc8544_guts.c @@ -71,8 +71,7 @@ static uint64_t mpc8544_guts_read(void *opaque, hwaddr addr, unsigned size) { uint32_t value = 0; - PowerPCCPU *cpu = POWERPC_CPU(current_cpu); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(current_cpu); addr &= MPC8544_GUTS_MMIO_SIZE - 1; switch (addr) { diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 93d550988f..c2f2cc27be 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -2412,8 +2412,7 @@ static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); cpu_synchronize_state(cs); ppc_cpu_do_system_reset(cs); diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index 805b1d0c87..a17816d072 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -44,15 +44,12 @@ static void xscom_complete(CPUState *cs, uint64_t hmer_bits) * passed for the cpu, and no CPU completion is generated. */ if (cs) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; - /* * TODO: Need a CPU helper to set HMER, also handle generation * of HMIs */ cpu_synchronize_state(cs); - env->spr[SPR_HMER] |= hmer_bits; + cpu_env(cs)->spr[SPR_HMER] |= hmer_bits; } } diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index bbce63e8a4..dfbe759481 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -90,8 +90,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, static void spin_kick(CPUState *cs, run_on_cpu_data data) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); SpinInfo *curspin = data.host_ptr; hwaddr map_size = 64 * MiB; hwaddr map_start; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index f8980b62ec..394091830d 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3481,8 +3481,7 @@ static void spapr_machine_finalizefn(Object *obj) void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) { SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); cpu_synchronize_state(cs); /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index e889244e52..cc91d59c57 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -194,8 +194,7 @@ static void cap_htm_apply(SpaprMachineState *spapr, uint8_t val, Error **errp) static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **errp) { ERRP_GUARD(); - PowerPCCPU *cpu = POWERPC_CPU(first_cpu); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(first_cpu); if (!val) { /* TODO: We don't support disabling vsx yet */ @@ -213,14 +212,12 @@ static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **errp) static void cap_dfp_apply(SpaprMachineState *spapr, uint8_t val, Error **errp) { ERRP_GUARD(); - PowerPCCPU *cpu = POWERPC_CPU(first_cpu); - CPUPPCState *env = &cpu->env; if (!val) { /* TODO: We don't support disabling dfp yet */ return; } - if (!(env->insns_flags2 & PPC2_DFP)) { + if (!(cpu_env(first_cpu)->insns_flags2 & PPC2_DFP)) { error_setg(errp, "DFP support not available"); error_append_hint(errp, "Try appending -machine cap-dfp=off\n"); } diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 6d9c5a6c9a..1487e2e3c0 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7196,12 +7196,9 @@ static void ppc_cpu_reset_hold(Object *obj) static bool ppc_cpu_is_big_endian(CPUState *cs) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; - cpu_synchronize_state(cs); - return !FIELD_EX64(env->msr, MSR, LE); + return !FIELD_EX64(cpu_env(cs)->msr, MSR, LE); } static bool ppc_get_irq_stats(InterruptStatsProvider *obj, @@ -7288,8 +7285,7 @@ static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best) static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); if ((env->hflags >> MSR_LE) & 1) { info->endian = BFD_ENDIAN_LITTLE; @@ -7445,8 +7441,7 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) #define RGPL 4 #define RFPL 4 - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); int i; qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 98952de267..6bb6fee8f6 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -2597,8 +2597,7 @@ void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector) bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); int interrupt; if ((interrupt_request & CPU_INTERRUPT_HARD) == 0) { diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index 122ea9d0c0..769551e0ab 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -108,8 +108,7 @@ void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len) int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); uint8_t *mem_buf; int r = ppc_gdb_register_len(n); @@ -152,8 +151,7 @@ int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n) int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); uint8_t *mem_buf; int r = ppc_gdb_register_len_apple(n); @@ -206,8 +204,7 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n) int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); int r = ppc_gdb_register_len(n); if (!r) { @@ -253,8 +250,7 @@ int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) } int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); int r = ppc_gdb_register_len_apple(n); if (!r) { diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 9f5a890655..6dfa5de444 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -546,8 +546,7 @@ static void kvm_sw_tlb_put(PowerPCCPU *cpu) static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); /* Init 'val' to avoid "uninitialised value" Valgrind warnings */ union { uint32_t u32; @@ -581,8 +580,7 @@ static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr) static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); union { uint32_t u32; uint64_t u64; @@ -615,8 +613,7 @@ static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr) static int kvm_put_fp(CPUState *cs) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); struct kvm_one_reg reg; int i; int ret; @@ -682,8 +679,7 @@ static int kvm_put_fp(CPUState *cs) static int kvm_get_fp(CPUState *cs) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); struct kvm_one_reg reg; int i; int ret; diff --git a/target/ppc/ppc-qmp-cmds.c b/target/ppc/ppc-qmp-cmds.c index ee0b99fce7..a25d86a8d1 100644 --- a/target/ppc/ppc-qmp-cmds.c +++ b/target/ppc/ppc-qmp-cmds.c @@ -137,8 +137,7 @@ static int ppc_cpu_get_reg_num(const char *numstr, int maxnum, int *pregnum) int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval) { int i, regnum; - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); /* General purpose registers */ if ((qemu_tolower(name[0]) == 'r') && diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c index 7ff76f7a06..a4d07a0d0d 100644 --- a/target/ppc/user_only_helper.c +++ b/target/ppc/user_only_helper.c @@ -27,8 +27,7 @@ void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address, MMUAccessType access_type, bool maperr, uintptr_t retaddr) { - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; + CPUPPCState *env = cpu_env(cs); int exception, error_code; /* From patchwork Tue Mar 12 12:43:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 779718 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2002283wrt; Tue, 12 Mar 2024 05:54:32 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWZlP+nx+yaemd2URBnuLfOcxb1n9a4QtJhKe99dUtrWt9069YIcfwj+p9/vGJG7oDVX9F/NeKkt5zUULx9tGbJ X-Google-Smtp-Source: AGHT+IGBZfHpXDltB48I/BDYfkS4So+p33Vce/KgRd82tQqowlGHM8YOxcPz8/66/vcQj4m+FguT X-Received: by 2002:a0d:d8c9:0:b0:609:546a:4ae6 with SMTP id a192-20020a0dd8c9000000b00609546a4ae6mr9558294ywe.0.1710248072042; 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[209.51.188.17]) by mx.google.com with ESMTPS id u13-20020ac858cd000000b0042ef1c1c10fsi7659394qta.402.2024.03.12.05.54.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:54:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=A0kvg1FW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1Y3-0000tm-25; Tue, 12 Mar 2024 08:48:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VQ-0004yU-1J for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:20 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VN-0000eU-4K for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:19 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247516; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=y6ZbGTCAWeBMMZ2CTH7Cqh0akX4u3D/q5yzE4MTVwog=; b=A0kvg1FWVuvTo6N6dB0Yd/lI3oy9ui0jw7J24tBUDc4m6vSw84Rr0lTpqDN8p551HzgNbS vzq5sWQvUhbpZ3P4RoCst1t0mrGgAA9O9Dc9i945tdo4FP1QaQ1ZbVm/U17vArAzQrPJEp 0qUweNuJRpEvCtelrXBg34OelHprMIk= Received: from mimecast-mx02.redhat.com (mx-ext.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-404-iSGEBXR4PX61l84jtGLlwg-1; Tue, 12 Mar 2024 08:45:13 -0400 X-MC-Unique: iSGEBXR4PX61l84jtGLlwg-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id E1EFD386A0B7; Tue, 12 Mar 2024 12:45:12 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id BB59C492BD0; Tue, 12 Mar 2024 12:45:11 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Richard Henderson Subject: [PULL 50/55] target/rx: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Tue, 12 Mar 2024 13:43:34 +0100 Message-ID: <20240312124339.761630-51-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-ID: <20240129164514.73104-24-philmd@linaro.org> Signed-off-by: Thomas Huth --- target/rx/cpu.c | 4 ++-- target/rx/gdbstub.c | 6 ++---- target/rx/helper.c | 6 ++---- target/rx/translate.c | 3 +-- 4 files changed, 7 insertions(+), 12 deletions(-) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 26ff822e71..da673a595d 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -71,9 +71,9 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifunc) static void rx_cpu_reset_hold(Object *obj) { - RXCPU *cpu = RX_CPU(obj); + CPUState *cs = CPU(obj); RXCPUClass *rcc = RX_CPU_GET_CLASS(obj); - CPURXState *env = &cpu->env; + CPURXState *env = cpu_env(cs); uint32_t *resetvec; if (rcc->parent_phases.hold) { diff --git a/target/rx/gdbstub.c b/target/rx/gdbstub.c index d7e0e6689b..f222bf003b 100644 --- a/target/rx/gdbstub.c +++ b/target/rx/gdbstub.c @@ -21,8 +21,7 @@ int rx_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - RXCPU *cpu = RX_CPU(cs); - CPURXState *env = &cpu->env; + CPURXState *env = cpu_env(cs); switch (n) { case 0 ... 15: @@ -53,8 +52,7 @@ int rx_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int rx_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - RXCPU *cpu = RX_CPU(cs); - CPURXState *env = &cpu->env; + CPURXState *env = cpu_env(cs); uint32_t psw; switch (n) { case 0 ... 15: diff --git a/target/rx/helper.c b/target/rx/helper.c index dad5fb4976..80912e8dcb 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -45,8 +45,7 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte) #define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR) void rx_cpu_do_interrupt(CPUState *cs) { - RXCPU *cpu = RX_CPU(cs); - CPURXState *env = &cpu->env; + CPURXState *env = cpu_env(cs); int do_irq = cs->interrupt_request & INT_FLAGS; uint32_t save_psw; @@ -122,8 +121,7 @@ void rx_cpu_do_interrupt(CPUState *cs) bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - RXCPU *cpu = RX_CPU(cs); - CPURXState *env = &cpu->env; + CPURXState *env = cpu_env(cs); int accept = 0; /* hardware interrupt (Normal) */ if ((interrupt_request & CPU_INTERRUPT_HARD) && diff --git a/target/rx/translate.c b/target/rx/translate.c index f6bf68e00e..f6e9e0ec90 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -131,8 +131,7 @@ static int bdsp_s(DisasContext *ctx, int d) void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - RXCPU *cpu = RX_CPU(cs); - CPURXState *env = &cpu->env; + CPURXState *env = cpu_env(cs); int i; uint32_t psw; From patchwork Tue Mar 12 12:43:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 779722 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2002928wrt; Tue, 12 Mar 2024 05:56:16 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWqnckApq1F3hnsj3nPV8zpzxLcViWpyEFMba2DEmhSwTGFgp9C/42Ko4bSIcCaCY98ZpIP296gnk+f8cbzQFfG X-Google-Smtp-Source: AGHT+IGbKni+u57iTU9K/+WqJIfCAEjFEwYKsf9s6h6Gd+qDlMhrDaFYQR0pnAuBzRrjYLmV448l X-Received: by 2002:a9d:7d93:0:b0:6e4:ec2e:1df1 with SMTP id j19-20020a9d7d93000000b006e4ec2e1df1mr1947326otn.3.1710248175977; Tue, 12 Mar 2024 05:56:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1710248175; cv=none; d=google.com; s=arc-20160816; b=fNuiuw1JedtDmClhq4kegR2FRFIf/ZHiAurNlo7JP+9XdH2UnR+5J9pnuLKPQNyf/Z UzwOGLzjbhV8IJqEbOro7LKsQrXRwgI+6p3TSUgRDG3rAAMvgda9qLH/Zz+MgpYoXo9g 1saS/8XfeyT48dHo9Gxp1yBlw4EW9RjjKt403O7hhEgcD2ih2cuZeiuEUbhFg//+H4Qv 9MrcT+muP8CCm0c3GEgzEakp3OdlZwMfyew7MfOz8UnYbVlYi6h030CWMvRxSaiAh4Bz d5z6aq8wt7z7wK1MMuLITyJwGWlzxzg2Evu/a+h2XnE3WSKmTOW9K07M1If8K+LzOK41 n38g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4xozeGQhwIBngkiKbaCD6gMNeCrtvDlcM6z3DqF/RLw=; fh=MVtmONGgcwaswePOsQaFbzD/JigNLxHXgB5l4X9593E=; b=YKNzkbdL4vE+YkClNgSqiKl1ycXLcBSEvWzjbtSRsv1VOAL5f0yDHgzHmbh9VM89pk twDMvZHaHPY6xiy/Xr1nB6h686FfZ+vXHDXfcMbW114B2kvDomqzBhbcp5mI2DTg915p u+tVQ+UNLZpVrLEdrgmCFwgxqsxas+fJak1PyrVnKfvq2LkRuU2NsuhRPLsTYoa+uhdG n2/LWj6Bw0gTL2BWg90npAZHjJ/xLs8rfldqi1PeywZSkY0JWW5ds2HW52YjhCB5WsQI N9HTPPvzfXMv2EjLrX5VhpTgqEQ7E57GqZXQ+F9CMNPN5KP+a32O5mffzdde34gsSS8b wl6g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=Sf6C3vzy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20240129164514.73104-26-philmd@linaro.org> Signed-off-by: Thomas Huth --- target/sh4/cpu.c | 18 ++++++------------ target/sh4/gdbstub.c | 6 ++---- target/sh4/helper.c | 14 ++++---------- target/sh4/translate.c | 6 ++---- 4 files changed, 14 insertions(+), 30 deletions(-) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index eb7c551e9b..4f5a4a3d98 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -71,8 +71,7 @@ static void superh_restore_state_to_opc(CPUState *cs, static bool superh_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb) { - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(cs); if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND)) && !(cs->tcg_cflags & CF_PCREL) && env->pc != tb->pc) { @@ -107,9 +106,8 @@ static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch) static void superh_cpu_reset_hold(Object *obj) { CPUState *cs = CPU(obj); - SuperHCPU *cpu = SUPERH_CPU(cs); SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(obj); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(cs); if (scc->parent_phases.hold) { scc->parent_phases.hold(obj); @@ -159,8 +157,7 @@ out: static void sh7750r_cpu_initfn(Object *obj) { - SuperHCPU *cpu = SUPERH_CPU(obj); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(CPU(obj)); env->id = SH_CPU_SH7750R; env->features = SH_FEATURE_BCR3_AND_BCR4; @@ -177,8 +174,7 @@ static void sh7750r_class_init(ObjectClass *oc, void *data) static void sh7751r_cpu_initfn(Object *obj) { - SuperHCPU *cpu = SUPERH_CPU(obj); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(CPU(obj)); env->id = SH_CPU_SH7751R; env->features = SH_FEATURE_BCR3_AND_BCR4; @@ -195,8 +191,7 @@ static void sh7751r_class_init(ObjectClass *oc, void *data) static void sh7785_cpu_initfn(Object *obj) { - SuperHCPU *cpu = SUPERH_CPU(obj); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(CPU(obj)); env->id = SH_CPU_SH7785; env->features = SH_FEATURE_SH4A; @@ -231,8 +226,7 @@ static void superh_cpu_realizefn(DeviceState *dev, Error **errp) static void superh_cpu_initfn(Object *obj) { - SuperHCPU *cpu = SUPERH_CPU(obj); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(CPU(obj)); env->movcal_backup_tail = &(env->movcal_backup); } diff --git a/target/sh4/gdbstub.c b/target/sh4/gdbstub.c index d8e199fc06..75926d4e04 100644 --- a/target/sh4/gdbstub.c +++ b/target/sh4/gdbstub.c @@ -26,8 +26,7 @@ int superh_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(cs); switch (n) { case 0 ... 7: @@ -76,8 +75,7 @@ int superh_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int superh_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(cs); switch (n) { case 0 ... 7: diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 5a6f653c12..7c6f9d374a 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -55,8 +55,7 @@ int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr) void superh_cpu_do_interrupt(CPUState *cs) { - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(cs); int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD; int do_exp, irq_vector = cs->exception_index; @@ -432,11 +431,10 @@ static int get_physical_address(CPUSH4State * env, target_ulong * physical, hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - SuperHCPU *cpu = SUPERH_CPU(cs); target_ulong physical; int prot; - if (get_physical_address(&cpu->env, &physical, &prot, addr, MMU_DATA_LOAD) + if (get_physical_address(cpu_env(cs), &physical, &prot, addr, MMU_DATA_LOAD) == MMU_OK) { return physical; } @@ -782,11 +780,8 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; - /* Delay slots are indivisible, ignore interrupts */ - if (env->flags & TB_FLAG_DELAY_SLOT_MASK) { + if (cpu_env(cs)->flags & TB_FLAG_DELAY_SLOT_MASK) { return false; } else { superh_cpu_do_interrupt(cs); @@ -800,8 +795,7 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(cs); int ret; target_ulong physical; diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 6a6d862b10..a9b1bc7524 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -159,8 +159,7 @@ void sh4_translate_init(void) void superh_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - SuperHCPU *cpu = SUPERH_CPU(cs); - CPUSH4State *env = &cpu->env; + CPUSH4State *env = cpu_env(cs); int i; qemu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n", @@ -2186,7 +2185,6 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env) static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - CPUSH4State *env = cpu_env(cs); uint32_t tbflags; int bound; @@ -2196,7 +2194,7 @@ static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) /* We don't know if the delayed pc came from a dynamic or static branch, so assume it is a dynamic branch. */ ctx->delayed_pc = -1; /* use delayed pc from env pointer */ - ctx->features = env->features; + ctx->features = cpu_env(cs)->features; ctx->has_movcal = (tbflags & TB_FLAG_PENDING_MOVCA); ctx->gbank = ((tbflags & (1 << SR_MD)) && (tbflags & (1 << SR_RB))) * 0x10; From patchwork Tue Mar 12 12:43:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 779720 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2002813wrt; Tue, 12 Mar 2024 05:55:59 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXX0S5MnVFdMuyGwMZlg7Ta3/WH4gvrS8u+beVAdZ3fsT2xuhkQptCIooYzHXNRgfuWhEXfGBjOpDcI67orU6jf X-Google-Smtp-Source: AGHT+IEFIspmCCLkwsAj7rrj9LzbsR4ceQKbsLHTH8u48alHUUYlHT0U12F1tYelb+zoSdigZ0Ev X-Received: by 2002:a05:622a:1822:b0:42f:1145:71f6 with SMTP id t34-20020a05622a182200b0042f114571f6mr17624835qtc.13.1710248158755; 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[209.51.188.17]) by mx.google.com with ESMTPS id u38-20020a05622a19a600b0042ed109d771si7506649qtc.308.2024.03.12.05.55.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:55:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=bi5YcP9T; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1Y5-0000yg-OY; Tue, 12 Mar 2024 08:48:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VQ-00051B-Im for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:20 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VO-0000eu-Dl for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:20 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247517; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vlTemT5AJCiw9sCMWBos6k90WSpsfIrujLVatOF4rkU=; b=bi5YcP9ThFq2Wk4gzmeStI1UtA3776h0oqnckgcRBWCMRrpnvwfSF9AdYvf7kzaPxpyZ5g 2kr2fUN84JthvRh7bh07KU4qQVEcPZaoDBzPBvj96aE26/IW1JloURlcQSLkGWmeUFscJC lViD0sptN+78GjHrvYoSvo5COqjPJ6A= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-329-wU68TWe1MGGO0uKscs37Iw-1; Tue, 12 Mar 2024 08:45:16 -0400 X-MC-Unique: wU68TWe1MGGO0uKscs37Iw-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id B3274800267; Tue, 12 Mar 2024 12:45:15 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8F8B6492BD0; Tue, 12 Mar 2024 12:45:14 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Richard Henderson , Mark Cave-Ayland Subject: [PULL 52/55] target/sparc: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Tue, 12 Mar 2024 13:43:36 +0100 Message-ID: <20240312124339.761630-53-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Reviewed-by: Mark Cave-Ayland Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20240129164514.73104-27-philmd@linaro.org> Signed-off-by: Thomas Huth --- target/sparc/cpu.c | 17 +++++------------ target/sparc/gdbstub.c | 3 +-- target/sparc/int32_helper.c | 3 +-- target/sparc/int64_helper.c | 3 +-- target/sparc/ldst_helper.c | 6 ++---- target/sparc/mmu_helper.c | 15 +++++---------- target/sparc/translate.c | 9 +++------ 7 files changed, 18 insertions(+), 38 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index ce6aab6bcb..dc9ead21fc 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -32,9 +32,8 @@ static void sparc_cpu_reset_hold(Object *obj) { CPUState *cs = CPU(obj); - SPARCCPU *cpu = SPARC_CPU(cs); SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); if (scc->parent_phases.hold) { scc->parent_phases.hold(obj); @@ -83,8 +82,7 @@ static void sparc_cpu_reset_hold(Object *obj) static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) { int pil = env->interrupt_index & 0xf; @@ -613,8 +611,7 @@ static void cpu_print_cc(FILE *f, uint32_t cc) static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); int i, x; qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, @@ -711,11 +708,8 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, static bool sparc_cpu_has_work(CPUState *cs) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - return (cs->interrupt_request & CPU_INTERRUPT_HARD) && - cpu_interrupts_enabled(env); + cpu_interrupts_enabled(cpu_env(cs)); } static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch) @@ -777,8 +771,7 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) CPUState *cs = CPU(dev); SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev); Error *local_err = NULL; - SPARCCPU *cpu = SPARC_CPU(dev); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); #if defined(CONFIG_USER_ONLY) /* We are emulating the kernel, which will trap and emulate float128. */ diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index d1586b2392..07ea81ab5f 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -29,8 +29,7 @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); if (n < 8) { /* g0..g7 */ diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c index 058dd712b5..6b7d65b031 100644 --- a/target/sparc/int32_helper.c +++ b/target/sparc/int32_helper.c @@ -99,8 +99,7 @@ void cpu_check_irqs(CPUSPARCState *env) void sparc_cpu_do_interrupt(CPUState *cs) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); int cwp, intno = cs->exception_index; if (qemu_loglevel_mask(CPU_LOG_INT)) { diff --git a/target/sparc/int64_helper.c b/target/sparc/int64_helper.c index 27df9dba89..bd14c7a0db 100644 --- a/target/sparc/int64_helper.c +++ b/target/sparc/int64_helper.c @@ -130,8 +130,7 @@ void cpu_check_irqs(CPUSPARCState *env) void sparc_cpu_do_interrupt(CPUState *cs) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); int intno = cs->exception_index; trap_state *tsptr; diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 1ecd58e8ff..e581bb42ac 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -418,8 +418,7 @@ static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, bool is_write, bool is_exec, int is_asi, unsigned size, uintptr_t retaddr) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); int fault_type; #ifdef DEBUG_UNASSIGNED @@ -480,8 +479,7 @@ static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, bool is_write, bool is_exec, int is_asi, unsigned size, uintptr_t retaddr) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); #ifdef DEBUG_UNASSIGNED printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index e7b1997d54..ad1591d9fd 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -206,8 +206,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); CPUTLBEntryFull full = {}; target_ulong vaddr; int error_code = 0, access_index; @@ -391,8 +390,7 @@ void dump_mmu(CPUSPARCState *env) int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf, int len, bool is_write) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); target_ulong addr = address; int i; int len1; @@ -759,8 +757,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); CPUTLBEntryFull full = {}; int error_code = 0, access_index; @@ -898,8 +895,7 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); hwaddr phys_addr; int mmu_idx = cpu_mmu_index(cs, false); @@ -916,8 +912,7 @@ G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, int mmu_idx, uintptr_t retaddr) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); #ifdef TARGET_SPARC64 env->dmmu.sfsr = build_sfsr(env, mmu_idx, access_type); diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 692ce0b010..319934d9bd 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4844,13 +4844,12 @@ TRANS(FCMPEq, ALL, do_fcmpq, a, true) static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); - CPUSPARCState *env = cpu_env(cs); int bound; dc->pc = dc->base.pc_first; dc->npc = (target_ulong)dc->base.tb->cs_base; dc->mem_idx = dc->base.tb->flags & TB_FLAG_MMU_MASK; - dc->def = &env->def; + dc->def = &cpu_env(cs)->def; dc->fpu_enabled = tb_fpu_enabled(dc->base.tb->flags); dc->address_mask_32bit = tb_am_enabled(dc->base.tb->flags); #ifndef CONFIG_USER_ONLY @@ -4900,10 +4899,9 @@ static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); - CPUSPARCState *env = cpu_env(cs); unsigned int insn; - insn = translator_ldl(env, &dc->base, dc->pc); + insn = translator_ldl(cpu_env(cs), &dc->base, dc->pc); dc->base.pc_next += 4; if (!decode(dc, insn)) { @@ -5106,8 +5104,7 @@ void sparc_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; + CPUSPARCState *env = cpu_env(cs); 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[209.51.188.17]) by mx.google.com with ESMTPS id w15-20020a05622a134f00b0042ec2a49e0bsi7689839qtk.441.2024.03.12.05.58.39 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:58:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=M23zDx1E; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1Xu-0000Mn-GJ; Tue, 12 Mar 2024 08:47:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VV-0005Mo-Uz for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:25 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VT-0000s9-FW for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:25 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247521; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=V47akZkB3MNNJPOVhp+e0c7sV+XYzBjWKfYo7JWtsuc=; b=M23zDx1EPjpc/Mgo4ggBl46oOLGro7HjC2jqq7W7ULTWFX/I7qGK7HAz9fzmofVm8plcGs eLS2xwbVJ2LQBeL5YqTCDrzgPgMlrD/qXfWXZizWmFxleC/WiYfS+V8HYnlHcoBAETGTl4 xbHE72RqAp3ismFe7DNmOWpkilzBDYw= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-21-0plU7JbWPmSiAZsOXp7tsQ-1; Tue, 12 Mar 2024 08:45:18 -0400 X-MC-Unique: 0plU7JbWPmSiAZsOXp7tsQ-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 0A4C880026F; Tue, 12 Mar 2024 12:45:18 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1C9CD492BC4; Tue, 12 Mar 2024 12:45:15 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Richard Henderson , Bastian Koppelmann Subject: [PULL 53/55] target/tricore: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Tue, 12 Mar 2024 13:43:37 +0100 Message-ID: <20240312124339.761630-54-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Bastian Koppelmann Message-ID: <20240129164514.73104-28-philmd@linaro.org> Signed-off-by: Thomas Huth --- target/tricore/cpu.c | 24 +++++------------------- target/tricore/gdbstub.c | 6 ++---- target/tricore/helper.c | 3 +-- target/tricore/translate.c | 3 +-- 4 files changed, 9 insertions(+), 27 deletions(-) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 682fc290ac..a9af73aeb5 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -36,52 +36,38 @@ static const gchar *tricore_gdb_arch_name(CPUState *cs) static void tricore_cpu_set_pc(CPUState *cs, vaddr value) { - TriCoreCPU *cpu = TRICORE_CPU(cs); - CPUTriCoreState *env = &cpu->env; - - env->PC = value & ~(target_ulong)1; + cpu_env(cs)->PC = value & ~(target_ulong)1; } static vaddr tricore_cpu_get_pc(CPUState *cs) { - TriCoreCPU *cpu = TRICORE_CPU(cs); - CPUTriCoreState *env = &cpu->env; - - return env->PC; + return cpu_env(cs)->PC; } static void tricore_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - TriCoreCPU *cpu = TRICORE_CPU(cs); - CPUTriCoreState *env = &cpu->env; - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); - env->PC = tb->pc; + cpu_env(cs)->PC = tb->pc; } static void tricore_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - TriCoreCPU *cpu = TRICORE_CPU(cs); - CPUTriCoreState *env = &cpu->env; - - env->PC = data[0]; + cpu_env(cs)->PC = data[0]; } static void tricore_cpu_reset_hold(Object *obj) { CPUState *cs = CPU(obj); - TriCoreCPU *cpu = TRICORE_CPU(cs); TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(obj); - CPUTriCoreState *env = &cpu->env; if (tcc->parent_phases.hold) { tcc->parent_phases.hold(obj); } - cpu_state_reset(env); + cpu_state_reset(cpu_env(cs)); } static bool tricore_cpu_has_work(CPUState *cs) diff --git a/target/tricore/gdbstub.c b/target/tricore/gdbstub.c index e8f8e5e6ea..f9309c5e27 100644 --- a/target/tricore/gdbstub.c +++ b/target/tricore/gdbstub.c @@ -106,8 +106,7 @@ static void tricore_cpu_gdb_write_csfr(CPUTriCoreState *env, int n, int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - TriCoreCPU *cpu = TRICORE_CPU(cs); - CPUTriCoreState *env = &cpu->env; + CPUTriCoreState *env = cpu_env(cs); if (n < 16) { /* data registers */ return gdb_get_reg32(mem_buf, env->gpr_d[n]); @@ -121,8 +120,7 @@ int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - TriCoreCPU *cpu = TRICORE_CPU(cs); - CPUTriCoreState *env = &cpu->env; + CPUTriCoreState *env = cpu_env(cs); uint32_t tmp; tmp = ldl_p(mem_buf); diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 649373a9cb..6d9e80cc0c 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -67,8 +67,7 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType rw, int mmu_idx, bool probe, uintptr_t retaddr) { - TriCoreCPU *cpu = TRICORE_CPU(cs); - CPUTriCoreState *env = &cpu->env; + CPUTriCoreState *env = cpu_env(cs); hwaddr physical; int prot; int ret = 0; diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 278c514ab0..c45e1d992e 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -95,8 +95,7 @@ enum { void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - TriCoreCPU *cpu = TRICORE_CPU(cs); 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[209.51.188.17]) by mx.google.com with ESMTPS id r11-20020a05622a034b00b0042e3fff1872si7670127qtw.107.2024.03.12.05.49.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:49:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b="bCEy/fup"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1YF-0001BC-Sf; Tue, 12 Mar 2024 08:48:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VV-0005I5-38 for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:25 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VT-0000s3-0Z for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:24 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247521; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PDNGuJuE3CMD4uIYpxofUQytc2L1YnHyiLboUK11HuU=; b=bCEy/fupTVlse0m4YNUHoitchjCj+ljwPv21TvQ5d+7mXpVUS+xSpntUqqe26Ka16ab4PF Gu3NGD4987jwMNbNL9d0sNffwi+xZWAOTbRZQNr0QGG29zLd/UI+UybkteDN31Dpfykoug /EDXUFe453pzEVTzDjaQ1w8WKw7qqvc= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-634-xygKlefXNLKGeSFzWnjREg-1; Tue, 12 Mar 2024 08:45:19 -0400 X-MC-Unique: xygKlefXNLKGeSFzWnjREg-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 8E11786C046; Tue, 12 Mar 2024 12:45:19 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id 4E356492BC4; Tue, 12 Mar 2024 12:45:18 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Richard Henderson Subject: [PULL 54/55] target/xtensa: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Tue, 12 Mar 2024 13:43:38 +0100 Message-ID: <20240312124339.761630-55-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20240129164514.73104-29-philmd@linaro.org> Signed-off-by: Thomas Huth --- target/xtensa/cpu.c | 3 +-- target/xtensa/dbg_helper.c | 3 +-- target/xtensa/exc_helper.c | 3 +-- target/xtensa/gdbstub.c | 6 ++---- target/xtensa/helper.c | 9 +++------ target/xtensa/translate.c | 6 ++---- 6 files changed, 10 insertions(+), 20 deletions(-) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c1cedf3f35..875cf843c9 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -96,9 +96,8 @@ bool xtensa_abi_call0(void) static void xtensa_cpu_reset_hold(Object *obj) { CPUState *cs = CPU(obj); - XtensaCPU *cpu = XTENSA_CPU(cs); XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); - CPUXtensaState *env = &cpu->env; + CPUXtensaState *env = cpu_env(cs); bool dfpu = xtensa_option_enabled(env->config, XTENSA_OPTION_DFP_COPROCESSOR); diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index 497dafca71..5546c82ecd 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -66,8 +66,7 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) bool xtensa_debug_check_breakpoint(CPUState *cs) { - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; + CPUXtensaState *env = cpu_env(cs); unsigned int i; if (xtensa_get_cintlevel(env) >= env->config->debug_level) { diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index 168419a505..0514c2c1f3 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -205,8 +205,7 @@ static void handle_interrupt(CPUXtensaState *env) /* Called from cpu_handle_interrupt with BQL held */ void xtensa_cpu_do_interrupt(CPUState *cs) { - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; + CPUXtensaState *env = cpu_env(cs); if (cs->exception_index == EXC_IRQ) { qemu_log_mask(CPU_LOG_INT, diff --git a/target/xtensa/gdbstub.c b/target/xtensa/gdbstub.c index 4b3bfb7e59..4748fb6532 100644 --- a/target/xtensa/gdbstub.c +++ b/target/xtensa/gdbstub.c @@ -65,8 +65,7 @@ void xtensa_count_regs(const XtensaConfig *config, int xtensa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; + CPUXtensaState *env = cpu_env(cs); const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; #ifdef CONFIG_USER_ONLY int num_regs = env->config->gdb_regmap.num_core_regs; @@ -120,8 +119,7 @@ int xtensa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; + CPUXtensaState *env = cpu_env(cs); uint32_t tmp; const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; #ifdef CONFIG_USER_ONLY diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index a9f8907083..ca214b948a 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -217,8 +217,7 @@ static uint32_t check_hw_breakpoints(CPUXtensaState *env) void xtensa_breakpoint_handler(CPUState *cs) { - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; + CPUXtensaState *env = cpu_env(cs); if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { @@ -266,8 +265,7 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; + CPUXtensaState *env = cpu_env(cs); uint32_t paddr; uint32_t page_size; unsigned access; @@ -297,8 +295,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr) { - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; + CPUXtensaState *env = cpu_env(cs); cpu_restore_state(cs, retaddr); HELPER(exception_cause_vaddr)(env, env->pc, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index e4772462b5..b206d57fc4 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1127,10 +1127,9 @@ static void xtensa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); - CPUXtensaState *env = cpu_env(cpu); uint32_t tb_flags = dc->base.tb->flags; - dc->config = env->config; + dc->config = cpu_env(cpu)->config; dc->pc = dc->base.pc_first; dc->ring = tb_flags & XTENSA_TBFLAG_RING_MASK; dc->cring = (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring; @@ -1248,8 +1247,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - XtensaCPU *cpu = XTENSA_CPU(cs); - CPUXtensaState *env = &cpu->env; + CPUXtensaState *env = cpu_env(cs); xtensa_isa isa = env->config->isa; int i, j; From patchwork Tue Mar 12 12:43:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 779708 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp2000482wrt; Tue, 12 Mar 2024 05:49:49 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVcJmSxyeunRIe5TOGCbnu+JAeNu1zx7L6e1HlRThH3TbGCw0DtY/QAXxB2Erily9T31T1VPvGEWbEcVuyxHTZ3 X-Google-Smtp-Source: AGHT+IGYJhSMB93r9GGN3ekZfeb+GLRL0o/Qk/IOPPkS0uek5gAr1/1V/l3JTSwoodPZhHpEvpw2 X-Received: by 2002:a05:620a:22b1:b0:788:1652:b192 with SMTP id p17-20020a05620a22b100b007881652b192mr8817837qkh.25.1710247789636; Tue, 12 Mar 2024 05:49:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1710247789; cv=none; d=google.com; s=arc-20160816; b=nJnX0AJ340dp3oF6yqPMR9WdHkf+tnLKNiU5E4Hxz28suEdqvoifWuuxjv0XPilag2 CeUGsDJRo2VvesU/yBTHoUicKMD6FI2Zeeep4vpGE9au4KuOI8ORomMa2vcP97GhE5WJ dhB1HksLKb0jk4wxJ1XhnK9ts6M66Rgb31H1Y8d4D6q6e28QKq5/lWB439gt97pab9Tj u5mPRFDHjp0Y/SeMQ0ulessQSz9aeS/g8AcmLjU3ecNpygGZ3U6aDuE5Wnzz79cBS2XB WibJjvkku6u2hcO//nKKz3xseyeqb2kbW/92WLK65d27DVym00gKtp2aOIJCrJzc78su 7Bcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mOZ+n16hSmdhLc1QeYUQIA8GPqXkcZgaeKwVr7g+qTU=; fh=k29BKSfEelS3RA88OrKO4TcDMHy8iBEk/E7SsHM1dhQ=; b=n4ldE5gruiSdfPgdwxGDKQ88IVK7Ykd6VdCio5AGRVoJT80I/iMKbfV5z2U1kROXLx NNa9wJS5af3eLQcLPfMeVB1zBMyZ+MiMElcVQuSzGkb2OLseLZLVlKDdAufm4u+QtKFB J2h99x3FrJmDHgpvTi5ZBtuCoIp+rhgRHotxcPF9rVt3z7Ac+TN0C2mUDKmupEArw7Co basoBUeMm9rdTnKbWPeNJtRq/Lk0dd2VhEb3S7RCyJvXtA41skc7p7XCG7pvVC33NbHf LVyDbaQ8inklhrCNydvtMqRHHmDUQ+q1uhHmMsAtsBZVW7ggHbaTo/sr8zkwAejnmYWj 3cxQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=Ku1HuOox; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h4-20020a05620a244400b007884b4d87e3si8216285qkn.411.2024.03.12.05.49.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Mar 2024 05:49:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=Ku1HuOox; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk1XN-0007n8-9N; Tue, 12 Mar 2024 08:47:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VX-0005Rt-O5 for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:28 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk1VU-0000tl-4c for qemu-devel@nongnu.org; Tue, 12 Mar 2024 08:45:27 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1710247523; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mOZ+n16hSmdhLc1QeYUQIA8GPqXkcZgaeKwVr7g+qTU=; b=Ku1HuOoxoGRig4YQVkKwd6HJFgpVXciV6Znd1pjO+nVLdwW7e0GUnyPZ/RtU/DqjdraLvo CU4S+GbCM7ixXaspFwOSP5GGm5QyZJDCwBXV/vf13leFAMareQKsP5Zbnao0hMVLWDQPTh yMkUa729FeAzQGDXWEyoa1PpgPzzFZQ= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-267-GfFjSG8COkutb5_eOVSdDw-1; Tue, 12 Mar 2024 08:45:21 -0400 X-MC-Unique: GfFjSG8COkutb5_eOVSdDw-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 6DE66800264; Tue, 12 Mar 2024 12:45:21 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.192.69]) by smtp.corp.redhat.com (Postfix) with ESMTP id 12E53492BD0; Tue, 12 Mar 2024 12:45:19 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Richard Henderson , Warner Losh Subject: [PULL 55/55] user: Prefer fast cpu_env() over slower CPU QOM cast macro Date: Tue, 12 Mar 2024 13:43:39 +0100 Message-ID: <20240312124339.761630-56-thuth@redhat.com> In-Reply-To: <20240312124339.761630-1-thuth@redhat.com> References: <20240312124339.761630-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.687, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Warner Losh Message-ID: <20240129164514.73104-30-philmd@linaro.org> Signed-off-by: Thomas Huth --- bsd-user/signal.c | 3 +-- linux-user/signal.c | 6 ++---- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/bsd-user/signal.c b/bsd-user/signal.c index e9f80a06d3..3ac50c2d71 100644 --- a/bsd-user/signal.c +++ b/bsd-user/signal.c @@ -463,14 +463,13 @@ static int fatal_signal(int sig) void force_sig_fault(int sig, int code, abi_ulong addr) { CPUState *cpu = thread_cpu; - CPUArchState *env = cpu_env(cpu); target_siginfo_t info = {}; info.si_signo = sig; info.si_errno = 0; info.si_code = code; info.si_addr = addr; - queue_signal(env, sig, QEMU_SI_FAULT, &info); + queue_signal(cpu_env(cpu), sig, QEMU_SI_FAULT, &info); } static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) diff --git a/linux-user/signal.c b/linux-user/signal.c index cc7dd78e41..1aebf3fc47 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -623,7 +623,6 @@ void signal_init(void) void force_sig(int sig) { CPUState *cpu = thread_cpu; - CPUArchState *env = cpu_env(cpu); target_siginfo_t info = {}; info.si_signo = sig; @@ -631,7 +630,7 @@ void force_sig(int sig) info.si_code = TARGET_SI_KERNEL; info._sifields._kill._pid = 0; info._sifields._kill._uid = 0; - queue_signal(env, info.si_signo, QEMU_SI_KILL, &info); + queue_signal(cpu_env(cpu), info.si_signo, QEMU_SI_KILL, &info); } /* @@ -641,14 +640,13 @@ void force_sig(int sig) void force_sig_fault(int sig, int code, abi_ulong addr) { CPUState *cpu = thread_cpu; - CPUArchState *env = cpu_env(cpu); target_siginfo_t info = {}; info.si_signo = sig; info.si_errno = 0; info.si_code = code; info._sifields._sigfault._addr = addr; - queue_signal(env, sig, QEMU_SI_FAULT, &info); + queue_signal(cpu_env(cpu), sig, QEMU_SI_FAULT, &info); } /* Force a SIGSEGV if we couldn't write to memory trying to set