From patchwork Wed Oct 2 11:38:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 174970 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp637386ill; Wed, 2 Oct 2019 04:38:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqyySxPhPIZROrC9KzRAJNaGkXzgao7GWmg3XtYtdnUnDqH//bG6cuahnQWb+LHyUCQm6VrQ X-Received: by 2002:a17:906:f4a:: with SMTP id h10mr2524435ejj.158.1570016312259; Wed, 02 Oct 2019 04:38:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570016312; cv=none; d=google.com; s=arc-20160816; b=BumEvhQO1C+djOhC80ZLStmxDLys3QEQTsCtYGgEilfLXHZTTJbKNFfRC/0gIvMlpz 2NuIYuE/7VkapWOsOgQWeRMivKOUG7e/dsfoPySXIsl+K8E88Cv0p7hxCyiso7p6LtdL kMZ3TR3ZZXQNJ7qxdj/9SCcpvNXVVfnfogpqgAFg1I6Hjke2sWskDjfU0JOmEeNku4b/ ZToSFg9c9FURZnbNnN7LExzWTnPzJlXkmU81gLSJGKXjKeBb60p5LUnQif2KUrh8wez3 2H/RJB5XLIEMOxHUsKZMK9NhnJiTYkTu0HvkWcggVbLc6dfn8/6WVA0S7Qz/9yuXrMmc gBNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=Aqd+0N9DK4RPDIWd3OXKq9bYDzE//xBJ4F1SiyVcLPg=; b=GJVffcWDUhcBBEWD5Bbsi9Kw5wexDW6cBEkE4LVcY+I45Rt6Dw4bdYvDaghTJidLgr FWdhXvrOUH1B41ICC8Y6v4vwvsozvpWu2yCff7xuY2aU0jgpDcQ/2Zw2wVKt7224JkXx iAob/subm+eIKBokVe7Ga1bWqIUZv/DCw9eDVh9B7Pe5tMd6tfqLTPNeVjdpUHabq/Gd Mv8cb7Blkmfd8BZKbxlZrl2uBhpZzuOJUwmouojpV6T6N1j1QCpO/WGZigVa7YisdKu2 aEMKLMrLpdsSI0D9mwM9WU4sAaVAn89DMSbfQFGy5O3bmaN7nmkqya3v0jfOqetZZAAg o+HQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b8IdKvle; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h10si3762646ejf.371.2019.10.02.04.38.31; Wed, 02 Oct 2019 04:38:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b8IdKvle; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726942AbfJBLi2 (ORCPT + 5 others); Wed, 2 Oct 2019 07:38:28 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:39694 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726917AbfJBLi1 (ORCPT ); Wed, 2 Oct 2019 07:38:27 -0400 Received: by mail-lj1-f194.google.com with SMTP id y3so16752261ljj.6 for ; Wed, 02 Oct 2019 04:38:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Aqd+0N9DK4RPDIWd3OXKq9bYDzE//xBJ4F1SiyVcLPg=; b=b8IdKvlekM1g/jmCK/dcdiFc6DMxiq3XaGknGYm8WiW6N3tsbhidLAT3L6mv2tHPFz 4ds7r5KyKiwjKaXfiBcRAp/zsPfpo1wAclVI5ii5JKvX9iQuh6kiwlA6xKEgjL43h3ss ujT5c0MCqAltRnILKx/30FMc+AIk56boR73selhdWs9dxwHCyNQ1EkVh1ni0o0et8YEb lf59//nQgRqX/HcLl2ziBwhsxTh36rh/PGGdyZy5oOu8ob4mxy9vExkuyOWTfy7eHH23 A1WlTTpDtt0/geRtIXmkVkVfMbmd3y+ETPtkIlbnjrR/Pem4Otcja+lL7xgqHEh+NUKB GXig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Aqd+0N9DK4RPDIWd3OXKq9bYDzE//xBJ4F1SiyVcLPg=; b=hegngU1XSJommeA04IaeGsdp6ruSdit68uxiKBM61u6O0I4ij67tmBttwj5VihQzwO Rn1T+eFoUv67R3v5w2XeNTxRNQV6nBJoy7ZEjbuk01YkQ64ErozZn/+hAx4qemZxJ8pG /QiQoumsPL3pSfNghFmNnfNFI3Qqt0WCWS7RIhTxvjcjsl5I1lwlaDQt8BcJjxSn/Rwe v0TqKLOXGaMuSOyBasmwwFWe4kVXRcorvL28+n+o17P1icWS6Yc5bSi+F+7R04ipshdM 2TILO+MomxzcVYtcnrei541I4DThGiXoP+Mq4yAyTViSOWY9LzJv9MKJKLr4hMogTzm7 PjcA== X-Gm-Message-State: APjAAAXRqAzsY2l4BCJISU7E2hlGBVrfAzzrLM5renQYZtrSp6/bPZEP M5qGMGtvAccggZ1ylz1Frl6+V33Bg2vVTA== X-Received: by 2002:a2e:412:: with SMTP id 18mr2183811lje.96.1570016305326; Wed, 02 Oct 2019 04:38:25 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id y26sm5317149ljj.90.2019.10.02.04.38.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Oct 2019 04:38:24 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Bartosz Golaszewski , Linus Walleij , Neil Armstrong , Thierry Reding Subject: [PATCH] pinctrl: oxnas: Pass irqchip when adding gpiochip Date: Wed, 2 Oct 2019 13:38:19 +0200 Message-Id: <20191002113819.4927-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Neil Armstrong Cc: Thierry Reding Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-oxnas.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) -- 2.21.0 diff --git a/drivers/pinctrl/pinctrl-oxnas.c b/drivers/pinctrl/pinctrl-oxnas.c index 55488ca246f1..40dc1251432a 100644 --- a/drivers/pinctrl/pinctrl-oxnas.c +++ b/drivers/pinctrl/pinctrl-oxnas.c @@ -1197,6 +1197,7 @@ static int oxnas_gpio_probe(struct platform_device *pdev) unsigned int id, ngpios; int irq, ret; struct resource *res; + struct gpio_irq_chip *girq; if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &pinspec)) { @@ -1232,6 +1233,18 @@ static int oxnas_gpio_probe(struct platform_device *pdev) bank->gpio_chip.parent = &pdev->dev; bank->gpio_chip.of_node = np; bank->gpio_chip.ngpio = ngpios; + girq = &bank->gpio_chip.irq; + girq->chip = &bank->irq_chip; + girq->parent_handler = oxnas_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + ret = gpiochip_add_data(&bank->gpio_chip, bank); if (ret < 0) { dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n", @@ -1239,18 +1252,6 @@ static int oxnas_gpio_probe(struct platform_device *pdev) return ret; } - ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip, - 0, handle_level_irq, IRQ_TYPE_NONE); - if (ret < 0) { - dev_err(&pdev->dev, "Failed to add IRQ chip %u: %d\n", - id, ret); - gpiochip_remove(&bank->gpio_chip); - return ret; - } - - gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip, - irq, oxnas_gpio_irq_handler); - return 0; }