From patchwork Tue Mar 26 22:28:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 782841 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0EED1CAAE; Tue, 26 Mar 2024 22:30:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492202; cv=none; b=iccQygX1oHmdK3kVkVXhF9SfSGL0Mwpato2uDIux27XCH9UL3L63nKiUGjgJ2BLOClUhYiklwqz+kCCZ8tJxID0X0Tbu8GsIqpNjNJC39RPsJ9n5Pem/x14cLqCSqdNeW4nYEiolzb+jGEJ92XEIWCmD1ICUwouDfMSQT94sn74= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492202; c=relaxed/simple; bh=bugga9cZQ1roDkO5l268TivF8rxs6k+Y5Y4rN4jKL9k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=orS9Uels7hUclMjh7tmrOFA/qjSmhWzrFVC2wYBREbZdlrD3omZTnpNsJH5RCphGlusD9BNK+y0jTOOLwVY28PoiRtCCMgnx/wQ2syGnh3WNnLu6XYsIHPym1rYSn5Y/NaBYaYlbuEuXOodiKB6Gl4g3PEs+peiCvIeTFHTOM9w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=iwFXfbWq; arc=none smtp.client-ip=209.85.221.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="iwFXfbWq" Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-33ed7ba1a42so4090090f8f.2; Tue, 26 Mar 2024 15:30:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711492199; x=1712096999; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x+RRCFo/tZsR/Haja5eHVQcmQZbdp2NA025wefazOWY=; b=iwFXfbWqP/iyA+xTG0cKs/65NMdJxtR3I8+IVVVZEKqYTErQAYbd1hOkZdauYpViP0 HEU2MD40/4dcs0qXCvSXNxM5DcSjduNXi1+8k2FApZFhCtF6oMkxEE5gKrve8Spcp4NW mGmV49Bs27kHAEszMI8hjk4/JjVJkMLKZX9usATURkjPLrKjSNEwPn6xA2zINQAtQxR/ 4AV0tnI/2hFXo2+k2AsuyeFDmRKYm83HgpUk03/Hcj6DaEOlZSQ5WI8/xD6M2W/4B8pM OYJHEOJfOnf4WXNTS6GZs1EyTQ7uuX30bwzXYtLqxaz+/hKjTbhydF/cUFX0l2VxKaSs YvyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711492199; x=1712096999; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x+RRCFo/tZsR/Haja5eHVQcmQZbdp2NA025wefazOWY=; b=Pc3ndrZulzAtkosU5e/7poJESRCQmCjQuHvS/C9hqT7tfwQxwLb5ChuT131olBWc8R Z+z7NNWHB+xGdzF9SmoL3RkxDtjxLVloaS9pvJW2Kurwf67kOq/UuUFsINMqoeAQd/9k 4qDsud0ZtKizJChtFmQ2BqaEtgTdtMq4mN95r+03ybRK2cNfvUveRFuen/bdS8c9EiOD tK9uSwb6AAGdDeURjwkkqDxV+7uZPjvYYpzVVlz+ntL1qlZEulHvNiDDdnA2yPRVgVdj 3ImZ+gxDWXdS1ng/+uHo3kTBu676c/caYJ/KSVkuYgI3Sk6A9dLO0gkBX+hnWJdej4lx 4fKw== X-Forwarded-Encrypted: i=1; AJvYcCUe0ZRu7oWaCS3g9zsczEA//rR2WDH71KEE773XCNU++weiJMZHIWja3Nyu1Zf17pU0jayzdQdmxjRF54YsjEggcsg1+d3lAJhXjTqZ2/sJ8y5S2JAiVSJj58kCfWKIm85N3SEb+pAcPCJX3I8ADrBkBlf/y3uJFfmRzk4FRwlp8HX6wWo= X-Gm-Message-State: AOJu0YzzXoUAzJUG9C1/kirhXnq/s2QhbaBX2ZflwGwTCq7aRpjyTYrl 8JmgAavfkK1oOJq1C264VKSIzImDjOwhruvYrwxud4ctAjxctBznhPRk9Xyr X-Google-Smtp-Source: AGHT+IEPMrUBUUwtny3YepxD28JQ5sY0RhOEuq5NO31RpVzVMT8KqCp09tGGnE9tOks4vlCR1wElgQ== X-Received: by 2002:a05:6000:e52:b0:33e:d229:35a1 with SMTP id dy18-20020a0560000e5200b0033ed22935a1mr7899822wrb.65.1711492199205; Tue, 26 Mar 2024 15:29:59 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:90ec:252a:cdf5:54e9]) by smtp.gmail.com with ESMTPSA id bs20-20020a056000071400b00341de138a2esm600647wrb.94.2024.03.26.15.29.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 15:29:58 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [RFC PATCH 01/13] dt-bindings: pinctrl: renesas, rzg2l-pinctrl: Remove the check from the object Date: Tue, 26 Mar 2024 22:28:32 +0000 Message-Id: <20240326222844.1422948-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Drop the bogus check from object as this didn't really add restriction check. Signed-off-by: Lad Prabhakar Reviewed-by: Rob Herring --- .../bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 4d5a957fa232..881e992adca3 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -79,21 +79,6 @@ additionalProperties: - $ref: pincfg-node.yaml# - $ref: pinmux-node.yaml# - - if: - properties: - compatible: - contains: - enum: - - renesas,r9a08g045-pinctrl - then: - properties: - drive-strength: false - output-impedance-ohms: false - slew-rate: false - else: - properties: - drive-strength-microamp: false - description: Pin controller client devices use pin configuration subnodes (children and grandchildren) for desired pin configuration. From patchwork Tue Mar 26 22:28:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 784245 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AE1E13DDB6; Tue, 26 Mar 2024 22:30:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492204; cv=none; b=EYIoFgr+r/T/AQ/IpYLo3luzrYCxWTeboe+ITqQG12gcUqjdwQQ7w3BQ0/yu/ogvJvncDi+XFPxVB73ElQEIE2goPE8jq+Fa3kColXuxp77tgDqtA/vDKSYk+fottMYTW58kEUIEBnlLPAfUCU8LzEzQz7eVxVYBws7dkz93iTw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492204; c=relaxed/simple; bh=VeJKb2fk+31D3xOPMXg7kpkc3Jz8DarzPDHEXGjXkeE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=edpKHw6Syj0Xu1Su0WIlnWD5D/lzQCE96ZsQCXD3ftSlF0fF9foFTf24NXJO5J5MHgGfND75pxi7UNOUigE5/d8peR509gc3pvbNiH6iS5tH6ZeUP7pA5xI4HmdKSLmU7Jyx+A1kGUfUbWxaoZeHsmuEOeOp1dGa+Qb4EMFePoU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=P7Y1p6A4; arc=none smtp.client-ip=209.85.221.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="P7Y1p6A4" Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-341cf28e013so1653412f8f.3; Tue, 26 Mar 2024 15:30:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711492201; x=1712097001; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e1T53gZiofVkC2dq0zi+t8YvzI14Q1dNLsQbFYj0uK0=; b=P7Y1p6A4T74McLTpr73gDMHs+cjyHMghbEA9gplM2KerlyCPRGXuFLXutPTne/lBYU nOwK2onjL0p2C7K/ziVfqW9VahaG0CpIdMK94K0YkSWJtJz0T3yZyKOSdbFwvYVF40IU 0EvhrnR6BW0RMuKNoA8nZGC21EE49WLVugBlGIgRTytXm+ZUBDQlkky5V5g7JeLuSmTL vE9ksiN5Y1B2pb2uVOlGptLYcHCYlf/ovVe9Uo/BPiOqPcLfMpt3KmHHlkAcd8E3+Prl EWh/it2wCSth682feObP5twzZ2ZMBzNXQso5Oy+EVgHWQ2vH6HZrPprtmRbhfRchEoWS NRuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711492201; x=1712097001; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e1T53gZiofVkC2dq0zi+t8YvzI14Q1dNLsQbFYj0uK0=; b=I+JWsne57i/IH+gh9rR8XIvOBgH2gpHk/PbZ5LGuIG2hkW/PhAB1LQZOx7pdFLTvMe OCaqdN1FIZauBvHaE6U2fKGCbZZYZsoPuppPVnKZz5hTbCTpJG3+vnRrUfqofUQclVg1 fw46rop0E2rrkuyucjz9bR8LoW1F7wIMM45pYYuhFD8z+UsZxBoh4ARpsCGO/kqpCC3X zQM/T4eqvOewSHEucMSVQeANePq0rmMV2PUnNlZXW5d1GF8n6QMHwqUEaHOfzKkWfAj4 zJ2bCzUSntaZPZbkGvYzBpc0toksuQdRop5eQa0WHNe4nnKwggZvNnGla9U93hM1Qkso lZWQ== X-Forwarded-Encrypted: i=1; AJvYcCW50A2jBBI63KF5HHI4ln/FFGODVL89alKFkSLwyFjdfNwhwXU13vjbaNhABLNn3h/tcE3BZOdLgEfqzV4w3bWO/z6whogREL7UlqLwaZy/7qWN3uH1fGmcMEUJV8CVHpvJemgfZcNzYobwSmGAhxpSZQPU237m8mgjaVoqNLeVYYoVVr8= X-Gm-Message-State: AOJu0YzJkPWJ1onP8+LZ3rg+0oXYugaYi29DGv7ymPnoNwy1vRePJPmZ 7DjIYfRC1TMDVI7bXl6JGuQZKTnj56tZPiL+bM6J7lO2hVQxMgZ7 X-Google-Smtp-Source: AGHT+IF6AGExfxy1qp2zfxzzfFJWrRM8pqNzivPeUgfzfLxilALD3fa6dic7sTGJ8zNnatNeoxnqRg== X-Received: by 2002:a5d:6d86:0:b0:341:d3b0:ae7d with SMTP id l6-20020a5d6d86000000b00341d3b0ae7dmr4172985wrs.45.1711492200592; Tue, 26 Mar 2024 15:30:00 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:90ec:252a:cdf5:54e9]) by smtp.gmail.com with ESMTPSA id bs20-20020a056000071400b00341de138a2esm600647wrb.94.2024.03.26.15.29.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 15:29:59 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [RFC PATCH 02/13] dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoC Date: Tue, 26 Mar 2024 22:28:33 +0000 Message-Id: <20240326222844.1422948-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add documentation for the pin controller found on the Renesas RZ/V2H(P) (R9A09G057) SoC. Compared to RZ/G2L family of SoCs there are slight differences on the RZ/V2H(P) SoC for pinmuxing. Also add 'renesas-rzv2h,output-impedance' property. Drive strength setting on RZ/V2H(P) depends on the different power rails which are coming out from the PMIC (connected via i2c). These power rails (required for drive strength) can be 1.2/1.8/3.3V. Pin are grouped into 4 groups, Group1: Impedance - 150/75/38/25 ohms (at 3.3 V) - 130/65/33/22 ohms (at 1.8 V) Group2: Impedance - 50/40/33/25 ohms (at 1.8 V) Group3: Impedance - 150/75/37.5/25 ohms (at 3.3 V) - 130/65/33/22 ohms (at 1.8 V) Group4: Impedance - 110/55/30/20 ohms (at 1.8 V) - 150/75/38/25 ohms (at 1.2 V) 'renesas-rzv2h,output-impedance' property as documented which can be [1, 2, 4, 6] indicates x Value strength. As the power rail information cannot be available very early in the boot process as 'renesas-rzv2h,output-impedance' property is added instead of reusing output-impedance-ohms property. Signed-off-by: Lad Prabhakar --- .../pinctrl/renesas,rzg2l-pinctrl.yaml | 22 +++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 881e992adca3..77f4fc7f4a21 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - renesas,r9a08g045-pinctrl # RZ/G3S + - renesas,r9a09g057-pinctrl # RZ/V2H(P) - items: - enum: @@ -66,10 +67,14 @@ properties: maxItems: 1 resets: - items: - - description: GPIO_RSTN signal - - description: GPIO_PORT_RESETN signal - - description: GPIO_SPARE_RESETN signal + oneOf: + - items: + - description: GPIO_RSTN signal + - description: GPIO_PORT_RESETN signal + - description: GPIO_SPARE_RESETN signal + - items: + - description: PFC main reset + - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins additionalProperties: anyOf: @@ -111,6 +116,15 @@ additionalProperties: output-high: true output-low: true line-name: true + renesas-rzv2h,output-impedance: + description: | + Output impedance for pins on RZ/V2H(P) SoC. + x1: Corresponds to 0 in IOLH register. + x2: Corresponds to 1 in IOLH register. + x4: Corresponds to 2 in IOLH register. + x6: Corresponds to 3 in IOLH register. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 6] - type: object additionalProperties: From patchwork Tue Mar 26 22:28:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 782840 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B548B1F61C; Tue, 26 Mar 2024 22:30:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492205; cv=none; b=MDm5ZXYR5N0od2bipuCyshIhSTCnwuhxzE5jc5WCzR0/n9Y+rgCJQY/sX9OP0NL1nDoBElhVZgC9tDozU4X9qfQfrL3xAQyMiBvA/GmdStEDDdWjHivc18jQGxVKq9SR86gXo5bhtoHbNzW2y6K4Q32QYPjyDBFwnrW5PuhwbKM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492205; c=relaxed/simple; bh=qFmXNPqUc7gduLPOXircsQfDl6z4dtGtk7mEji1PhTQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ejI4OEl7c8G60pjSFKeWrqxxbG07o+U48gftY1IyI35cNG/Pk5j4gG4rDVd9GS985MWW7glrvugnDAFDAQ+6FdpKusW8e5yz3C06A9yPfBtM8DbrcTMPmAazCJguTCMmUGqIpCsvOOygfoPPnZqCKhwLETeg47n+UtQua6S1JbQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=PhRd12f7; arc=none smtp.client-ip=209.85.221.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PhRd12f7" Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-33edbc5932bso4271463f8f.3; Tue, 26 Mar 2024 15:30:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711492202; x=1712097002; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ohJJQxLFbEg3u3dqq9yefZu6nixhdieVYsl2IVgizdA=; b=PhRd12f7o07jaurhM2XzDtFvo1T4clDK5KCAyCvt+XFLNWv2Z9WHt+huBB/GsKKHZm 9E2ejbScbJp/i8Q9aFgJDJ4YN1rrOfZVPc8L0pRlE7EtJr5278iIf3+tZS82xK7mkyrR P3GWB6YcsKKfcpyk+2oM2jlLayAjVEGv9ByItLvBtE/4MhLPk0NZi+t4Ea68ZST+VbFU Ja4qfhZD86dAe70dmWcfaATu++l/IynU/pDmt1PdhDduchipHvQxsvZWuIl01u5hVUtI NZGWH7LTTEYmzbpL3AqBrB4YkOWX8wIifEDmV8aR5kGrG0Xc5wtTqIU8e763Z5XgY0fa zcGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711492202; x=1712097002; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ohJJQxLFbEg3u3dqq9yefZu6nixhdieVYsl2IVgizdA=; b=Pwe38lKJcbm0cZnWKK7Gn1jvW+3lYhLgbA6oc8BGUyE4kX1vHhQIvLoVRVr5o4cW1i XAzVt1Otfr2dKEb9q+GPwfBRgFFfbFldvgclvFRIZ2ebOLJDMoynYVfoelcymY6hXtyR oYJE4pK+raB6cUe9EJ6CBfF3Z765VKs/CEhOSOhBzevEcXH8aaPVov0LTdXvkYRj8PHH 9xwLFgpBVrqDpdpvnYmuyp4ulbohp64u/vgV89ftlgvYUbX/traoWuZ9yDhm8SFXyq6A za8rNYEhGeVUV+kssDfv7QK8HT76sIdCUm3aHwLbZENzwYkK+6eB3gjHpAc2ytnZRecK POJA== X-Forwarded-Encrypted: i=1; AJvYcCWEJALpfwgIJHFjK1/Z1anwKngeNsL5DR/qZYCys2Y/aEVyOqoAi4ebcQOKHs3V0WY/ywc0e6bPaQm5ctFV7lCqP60au3gVbL/fyfx4uXvAm8I6ZBKbJ0nnpQeWfMTp/2N3PR3sxqpKyT21P693+27k8hZaLWwkZkGEGOxf2uQiLbo6ha4= X-Gm-Message-State: AOJu0Yyq1v1zL1z0m1udmDUopASsCS0PvYRM7O0tqLaNtQJrHqAjJGcL LvVhkviyjaOJFZfFh4qir7WFsCsVIM25UYLmsfifmFUYC63fatOF X-Google-Smtp-Source: AGHT+IF9r73ePlThd37uiocuW1pDDFlQ17+q38ybNH8DnK1yncu8sypWKrjVTWJiHvZD8dWdWJ5ymg== X-Received: by 2002:a5d:6785:0:b0:341:a802:3d25 with SMTP id v5-20020a5d6785000000b00341a8023d25mr1694963wru.53.1711492201975; Tue, 26 Mar 2024 15:30:01 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:90ec:252a:cdf5:54e9]) by smtp.gmail.com with ESMTPSA id bs20-20020a056000071400b00341de138a2esm600647wrb.94.2024.03.26.15.30.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 15:30:01 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [RFC PATCH 03/13] pinctrl: renesas: pinctrl-rzg2l: Remove extra space in function parameter Date: Tue, 26 Mar 2024 22:28:34 +0000 Message-Id: <20240326222844.1422948-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Remove unnecessary space in rzg2l_pinctrl_pm_setup_pfc() function parameter. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index eb5a8c654260..fccac6d199cd 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -2502,7 +2502,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b } } -static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) +static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) { u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; From patchwork Tue Mar 26 22:28:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 784244 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B73B813E03D; Tue, 26 Mar 2024 22:30:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492206; cv=none; b=asYaAThRgQKA98wvrjk6Yh1I7oZhhY+dfhJ0+E9zmnZBJ5iRy2jxmDT4q1PpaGD3XrS//NczmrtQKs00MfpLLv9Rcdy5n1B2zUbpSeeJIlyPczFo4ZAWaBvI318eTLQslK9HjxnRoYvMND6wXQUQuxHm4ajSswmBJex5KShc1HU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492206; c=relaxed/simple; bh=QeYjK/TMtPSocGnoRUFMmCD1HcnoJ81gUzd/wF12x4s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pVMnGVe03ok0Auu63cLV7hLIW1M0KtEYdSlGTdZrBZ1/w4cKpxOfFFicLvNAW2HJsoc6ZgnnBta5TIX2fyVVJE9oiwyHbQM6bt2qFM6cmvZalfETJnc18AIQ4y5pexsAALYsEXsYezqipuHAkW76JlK53bZJ5hpNTncVSZXrMto= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Bo/GodDS; arc=none smtp.client-ip=209.85.221.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Bo/GodDS" Received: by mail-wr1-f44.google.com with SMTP id ffacd0b85a97d-33ed7ba1a42so4090118f8f.2; Tue, 26 Mar 2024 15:30:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711492203; x=1712097003; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=S7slSHrluo/yZHTT9IkQat6c1ty1R252Rsn9mmiwCGQ=; b=Bo/GodDS9r8ouSvLIuAYDKcx3gs3cZI4NgsPMCkuToWM5wTH9ztrm9f5BKNYU4SeaN owEV5Dgg0sAwl+sp2Biv0PQDevmplJySvX6E6coJgTmggpSFvUS8OIsyB/m9n/SVx6sD 7eNoXwFlhtIqNjzES4PeGRedl5qFnEYfuFQg0sIF473FNHUznyeqsO99bUy0/8Aijx/l 58qG5G8yMMJvrVOq26zKTZi3OlBWXN1Y9yUhiDLMHg2xiWvBu45t+6URSsVfzEp32+Nl tXXcaEL5+PgYGrIGLZpRfkf88s0xdqXhqryFQx4/XmB9AKOT1h+0MdrboEmlweD8Dv+W b+GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711492203; x=1712097003; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S7slSHrluo/yZHTT9IkQat6c1ty1R252Rsn9mmiwCGQ=; b=cZAvfvpqAex33RTS2X3qrcan3/1CCN4H2FIW8jw0n+NRxGvUBVPSN0Kfs61IDrhHFs KxGAGrAgjUsMxdOxsqroEp6NN5Xs9BTSnMxqyQSLlPfOV8I6J1EbKAj7gsfKI5D7vxn7 rX3oJjzrANjkyKfuy9Jte3kUD82y34FgXRQ0+l+em3jzmROROemZ2A6d9dp2CNQR8rFI 4fUyGRCru2NeL0UsxUrkiCy0ZPAHcpdXnOcP0UMZL6t9fCx8kPHVTYXQ6UliL3Bhwdrq C0CuOCbbui2Pjz0XYL8o6U0CqohrlX2vhp5hBlr9FEjmbYLihsFxXOO0tAf+Y81w8N6o UFRQ== X-Forwarded-Encrypted: i=1; AJvYcCUpYNDBSoDD0oNbLGTthbk07VYQflRUIHARK/SCld1iZ09wNpvfFFwUW7iBeVH6Wmahrnxe8EjSn1JZURD/nKIs7Zrvlnwoeuapfk681VuGFWDepBTbv3T4fvQoGbWZfYlsEFvlSmgHCU1vRv8B1XIyRaA7ohGnSB7d195RVPHo6r+5QDY= X-Gm-Message-State: AOJu0YyjTPtis9E+Li0wxv/hUD/Ph7cpMCxgNMxWA1kiEH1ixK2WKWwa MBID1yDcPjI9aCgFxp4yALDV0d/UEaAyfoudp5yrincJW+iOXkc8 X-Google-Smtp-Source: AGHT+IGttCqHFnX55tKbvHYsZRUySNn+bm/lcNxQPQ4W7052Y5DqPlhwDpWFvRwf31oB56Tb9JUeIg== X-Received: by 2002:a5d:4705:0:b0:33e:c271:8c90 with SMTP id y5-20020a5d4705000000b0033ec2718c90mr8694797wrq.10.1711492203016; Tue, 26 Mar 2024 15:30:03 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:90ec:252a:cdf5:54e9]) by smtp.gmail.com with ESMTPSA id bs20-20020a056000071400b00341de138a2esm600647wrb.94.2024.03.26.15.30.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 15:30:02 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [RFC PATCH 04/13] pinctrl: renesas: pinctrl-rzg2l: Allow more bits for pin configuration Date: Tue, 26 Mar 2024 22:28:35 +0000 Message-Id: <20240326222844.1422948-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The pin configuration bits have been growing for every new SoCs being added for the pinctrl-rzg2l driver which would mean updating the macros every time for each new configuration. To avoid this allocate additional bits for pin configuration by relocating the known fixed bits to the very end of the configuration. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index fccac6d199cd..f2c71462de92 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -78,9 +78,9 @@ PIN_CFG_FILNUM | \ PIN_CFG_FILCLKSEL) -#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(35, 28) -#define PIN_CFG_PIN_REG_MASK GENMASK(27, 20) -#define PIN_CFG_MASK GENMASK(19, 0) +#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(62, 55) +#define PIN_CFG_PIN_REG_MASK GENMASK(54, 47) +#define PIN_CFG_MASK GENMASK(46, 0) /* * m indicates the bitmap of supported pins, a is the register index @@ -102,8 +102,8 @@ * (b * 8) and f is the pin configuration capabilities supported. */ #define RZG2L_SINGLE_PIN BIT_ULL(63) -#define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK(30, 24) -#define RZG2L_SINGLE_PIN_BITS_MASK GENMASK(22, 20) +#define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK(62, 56) +#define RZG2L_SINGLE_PIN_BITS_MASK GENMASK(55, 53) #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \ From patchwork Tue Mar 26 22:28:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 782839 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E1E61CAAE; Tue, 26 Mar 2024 22:30:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492207; cv=none; b=COIOLV2CMBZHi1wZ2/z4LpqAErZn8i75VZyIsedmRPXVumAr8BKq/TLL5GRpsRh34Wf5BoI7xUN271Fkubz1IN7wOYsGkXIRvX4PJLnqZETfR1Cl/H4Zo3keyAr9zS6JId8gxJSroEsl07FWkzEDNSPyaKNSy77cZJlMs0JTmFY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492207; c=relaxed/simple; bh=nr1KyEnr6RNBT94GwrGI82jLNrmEMY7aUvTUBIXU3UI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jzpCg6CzX6Yxg+YOrowM42AkmbAlDVsX4YTICTeswpDiPgEAsdM4rqzV1FGOXuD9UNnFunrP74Zrdy0iI1TAJDlOTYeqGBiCv6kFAFHIWeJaVl4oYoHW94BFoKQ2g2ap/j4jcj/Cex0LEuyi6dleKOGq3PTin8BrRE5TS5RCIi8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=OzHC9gB5; arc=none smtp.client-ip=209.85.221.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OzHC9gB5" Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-341cf77b86bso1754315f8f.2; Tue, 26 Mar 2024 15:30:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711492204; x=1712097004; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FgohSLyg2e0nbKWx+Eeh0sacbPLQWN8SXQaLV85doCI=; b=OzHC9gB5GCs3+g8a2od9FODGdBlba7+IvgWxXwQnjbtm+ihnZLn+oLs00gl4NPDc92 LMQne+WBwIDyICOJ+AfBUwahyfgj9/9KbmwtOINPDsT/VQISboEDUoiqaFR9rW7ar+8X 2naoTvf8E4yuidk32zgk57PJklAesYxgubH0RnM62ovKvQkhQ/rjRvYEzJAC+2G9YfvZ kBpy9guEiDOLkwy9R8Zsfhxu25VHP7Tytjp0cMTQEeRj9qqKZIY0dZfW5cURiQrzseGG CPJWhYcNLCNkgdc46R4C12RQqc0msw+cx8zJFJlhSfBMkUGU1ixO/fK0rM+CacdQk5hO gqVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711492204; x=1712097004; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FgohSLyg2e0nbKWx+Eeh0sacbPLQWN8SXQaLV85doCI=; b=fYyAHF7NVXg+TwsphicVdUow1593DONNjLnksqtyiRRErg9uDJ5BG1zXr+776uZxp1 0/wUczeTJYQeBg//lffEwa+DtQC0y1uWPh1Q3cNklz4V9UWZJpu84Tx6XGNAE4hhaAR8 MEx1csbt+vBRYiQK9JkLfxu3mKkQ4wEY/hAmT6kITmPHgPA9AxSS8i2MUhkAeUAM4xHQ bjxS6GuGj4YTHJ0Q1zYUNOrMnmZg6e5Uvi2jl1lK6fkryNHolq6CsJtH/tEl6DbSh5O3 oF8am9AI/T+16Mb3yrooTv7yZuHXEfT5YHkATphfTwzUausprNaRayoBRDtIuivq0T1i hDbQ== X-Forwarded-Encrypted: i=1; AJvYcCWhxJ067ZF+KZYk5j1AB1kcFYrlYbMnWAAfiJx4ZzBWchwiIzqV2ibHdSnBYsT5PJBvGr9JQmty1oEa4doi1DYlm/5kL6jBhhL2eBAjGWJJlBZGA7DI+LHyvmqrpfIl6hup7uMk0vegi9zU8gXCj0RjfnQjlgl8chT95zwnxd/MbaJ2ADU= X-Gm-Message-State: AOJu0Yys3Itfhiui1WEwOm1ZsT3KOpUSrnf0f1JCxf/hGfVmFLfSZ8Vv L5ZcVH4Noe08FuG6jA7yyiQrcn7qr7Weoqm+5MrC+8hIx/I0LNEm X-Google-Smtp-Source: AGHT+IG8PXu9DEd+H8iSzgcHcIGuHZ4afYLUbWDKQpVwoIRdyO1PLyIF0JXTT/u9/McJl2CuLnup3g== X-Received: by 2002:a5d:4b08:0:b0:33d:b2d6:b3a6 with SMTP id v8-20020a5d4b08000000b0033db2d6b3a6mr570127wrq.48.1711492204432; Tue, 26 Mar 2024 15:30:04 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:90ec:252a:cdf5:54e9]) by smtp.gmail.com with ESMTPSA id bs20-20020a056000071400b00341de138a2esm600647wrb.94.2024.03.26.15.30.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 15:30:03 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [RFC PATCH 05/13] pinctrl: renesas: pinctrl-rzg2l: Allow parsing of variable configuration for all architectures Date: Tue, 26 Mar 2024 22:28:36 +0000 Message-Id: <20240326222844.1422948-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Enable parsing of variable configuration for all architectures. This patch is in preparation for adding support for the RZ/V2H SoC, which utilizes the ARM64 architecture and features port pins with variable configuration. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index f2c71462de92..da3a54b7b06a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -322,7 +322,6 @@ struct rzg2l_pinctrl { static const u16 available_ps[] = { 1800, 2500, 3300 }; -#ifdef CONFIG_RISCV static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, u64 pincfg, unsigned int port, @@ -339,6 +338,7 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, return 0; } +#ifdef CONFIG_RISCV static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = { { .port = 20, @@ -2285,13 +2285,11 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) if (i && !(i % RZG2L_PINS_PER_PORT)) j++; pin_data[i] = pctrl->data->port_pin_configs[j]; -#ifdef CONFIG_RISCV if (pin_data[i] & PIN_CFG_VARIABLE) pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl, pin_data[i], j, i % RZG2L_PINS_PER_PORT); -#endif pins[i].drv_data = &pin_data[i]; } From patchwork Tue Mar 26 22:28:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 784243 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6527713E413; Tue, 26 Mar 2024 22:30:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492209; cv=none; b=C7aUEdjFkptahRy5cEr65yeR8gL+PA05IwZnIJbMDbwUVRKHk0g5LCMX6C5L98QzWy1bJaUXreQZQ9Wxrc6LkvMCimIoHfsERu02B2rp/SMMWnvpP1aeUZDr2rexw0IV52ex3888kvINc79idhlV+mjIQldX7KfmakDYmGB9ko0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492209; c=relaxed/simple; bh=G1FREJmgcUsk+GMF47Ku1uU6ZZU4d26S4OPEd6UM5F0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LWELowAW5e0ekiw5z62BVQXVfUjc/cYArUT0d/cfUySSPvWrvBGCYvb4MH924+7kxgJkD4kGz9MM/UO/om3vuuJukGtRwui+eoUBFlYOQIHlu/ySa+UvDYa2SSwbhpqVgJYa1tnQYRq4K0BbwisOvW2rmx6T43J+RwqjJn1WlkM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=REaK8O9h; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="REaK8O9h" Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-33ececeb19eso4017949f8f.3; Tue, 26 Mar 2024 15:30:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711492206; x=1712097006; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yMiTWsMKQUkHwbX3xcVwucmg3pH3xhNFm3FsyybLIuw=; b=REaK8O9h2kScKTsGi4t2kFSovZC18h6JhfIkcoDa9WW/Tnp8GWLQx0vfZKxLZxAGkV 6AP1jMzzn8GrdyyL/klNy3pT1EqXwBWSuwfSrVUROpb/mh1zlWFucEe5/3p3zAEU7cXn APx+CS7Av1ZteE66rKDzQWZVJviTDQKpU3lDE4HZduzRwNPLyEsKLzypqEIR16eAz6DR xVKq89qTKZAd46RkiC/Gt1W4VhGn3uGIx4D2wXneqV+z9rFlWrpTlw4P3HOVZa7InJXu /b8EYHYaF/sIYv9HdTdITZN+8vQMTMV6YzjKzovHfg07/JbsDbYC1qiEbv8YFjBI62Ln udUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711492206; x=1712097006; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yMiTWsMKQUkHwbX3xcVwucmg3pH3xhNFm3FsyybLIuw=; b=JqppT4TC1GM79D2mA0MSNZFlWN7l5AsfsdYB0FlhjT3IUfe15v/D5rBxZIR1S9vgRa DCwvrnbs7DpdmFcFYyqV8z3nRBHBh/RufFxBRBqtqKLuosttEBJhFaxM2gIzknkWc6iA diyHYaAylObGwH2RFeVQVzr9IhlakGbv+Vs3w8SGU/2QlOWvolKaLfrmiFqgW/Nk4UHR xXMM37Af4g4GLqeenR2nOrUl2B6u3K+k9z0z8kiXC32mPFkTUAePJOXwkLXibxzB7UgP C4wnKIZX6giU0uNqBEbjyDd6azzOIKBuxApmhOI5eE1g5hbsh0x6gKDNc6ivbYGKWmMp BXXQ== X-Forwarded-Encrypted: i=1; AJvYcCXLSDdS94KQM5ledEBzj4c/hv5BwlYjqfeDEXd+PTvrmFjeX3GNanN2R9ocgzOjSB9g/e2XTLJizSGDxTBNvxZ2g1NiF1oNdrWyYpn94wEXTqoQpJaHmoUdxKRE2IIb/x90RwiHRwO7ZzxrqygiI16mosbAT3LhYB56sxt1neVqrAvlBKs= X-Gm-Message-State: AOJu0YwOH3NyDEwuXvAuHJ7m3gaIZuTmWHhaZOoE3pUrsK2lle+scFW3 UJYLUj1i/J3ELHJe+SnmPnDiTZdB593bA4/SysSK2/5Z+iocIylt X-Google-Smtp-Source: AGHT+IHzlQZgHd7VQJLmUYWux8BGBJV6oO+i8et7nP8IzjyiR13CAPhi+rC4IHjytmfAYw5J37WmRA== X-Received: by 2002:a5d:410f:0:b0:341:db72:14f0 with SMTP id l15-20020a5d410f000000b00341db7214f0mr584290wrp.19.1711492205825; Tue, 26 Mar 2024 15:30:05 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:90ec:252a:cdf5:54e9]) by smtp.gmail.com with ESMTPSA id bs20-20020a056000071400b00341de138a2esm600647wrb.94.2024.03.26.15.30.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 15:30:05 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [RFC PATCH 06/13] pinctrl: renesas: pinctrl-rzg2l: Make cfg to u64 in struct rzg2l_variable_pin_cfg Date: Tue, 26 Mar 2024 22:28:37 +0000 Message-Id: <20240326222844.1422948-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Now that we have updated the macro PIN_CFG_MASK to allow for the maximum configuration bits, update the size of 'cfg' to 'u64' in the 'struct rzg2l_variable_pin_cfg'. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index da3a54b7b06a..348fdccaff72 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -241,7 +241,7 @@ struct rzg2l_dedicated_configs { * @pin: port pin */ struct rzg2l_variable_pin_cfg { - u32 cfg:20; + u64 cfg:46; u32 port:5; u32 pin:3; }; From patchwork Tue Mar 26 22:28:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 782838 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C254F1F61C; Tue, 26 Mar 2024 22:30:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492210; cv=none; b=FlNc10HX3ULARwCCsuOij/B+aVK5de5cya4+hnRqBG5TkyfOMQhtEVT182rI+Gk2TEX1V2Xr/ywUjYGCOUPFYEGWvg6bgLaOZpMfpJmj9kQa2RG8O3VBlnoJiu9fxRjm3FeD5j9+gkoELoueQvswi/WspkecypP+1s+y+o9h1KQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492210; c=relaxed/simple; bh=/pDeMHeqvYkpWe2yYgrSSYVEYoN52aRaMxU3QektXds=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WPFiNkfq5TXKgNsAyd+vWUbhXt4joHUbcwgWbayGBSgy8YDZ54Vy5S4HpQWpbJ2tVMM9Nflj+ECVp7MgeFy8A6kTiAXiVdn/DVkxf+9Bphf9uIRR7cjMd3few/YLsH8mDsu59PIESX0SYXSlwYKuxrFba0KlmpNKRTmuUuk9dro= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=A8eNC/93; arc=none smtp.client-ip=209.85.221.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="A8eNC/93" Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-33fd12a06fdso4318130f8f.1; Tue, 26 Mar 2024 15:30:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711492207; x=1712097007; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zSimU1CbyugwQOMg7TphS7eBhLoLw2mavmtx882jjic=; b=A8eNC/93UNba0nJjAMpPmP2GKVFhlYvWbGYUgpnq1JUc8MhXqot2FXX8nhm7CMCVfh j1UOUcGCZLeAzoC49ocb4pGQl6FgjbbUloAGnzV7tgmOYVCRjQPwzKCn+kSD5Q4NfTvU lav4DFDflEzFppA1qIPhb8nfwIsZ2xtIxT++1HutgakJLq7UxY+bX2e/+SdtGyq3OSis 22tRiUnDUZmlIB9H28Pbcen6ICFLd0Kg1XBoNTAjK5uNhvFln34O1Y3fyDj5z4w2p4QZ qH2DZEcBVF0+mVy/Dy88uEApzbWk8+pqxLoxAVskO4CZQ0PP9XehdCirvaif6ztl0gnc 4+KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711492207; x=1712097007; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zSimU1CbyugwQOMg7TphS7eBhLoLw2mavmtx882jjic=; b=L/MVRX3GKrfOAWrvpewb2l88/vBU69i+vrPJy31HR44SBkW8l+scZLQmbXm0BuJJrr 6eFcuk0uDpOTADtzkKbmDRblDoqaPuAyN7s2B1FU1Y9x8N9j2gP/pxLQW9lvqOIubVYW DPCLSNbebkm0it6E4lxsaP6LpSiZTou3g2Ur0CeWfcnrcw5wF6HVcKyYO5+ef84QNEAL /D0H8ejgGOd7EdmakKJCT9oKpfNjg9ykCbGrsv0ZsJi2mHnd3XzpJgzIAQsd42c8lcJ+ LgMW29YCtV58msN2HS1CPDb/VJkUT0owZRsmX0vsj71hZHA2II4lOIu7iewM9dyfyOQE gB/A== X-Forwarded-Encrypted: i=1; AJvYcCVHvCnstB5ZDK+LS/XxSovKVm8kUMlu5lIIcfTkOiO+p+N5r9P07ZlRqM7LzZl8+3c0z81o56StDK9DtYxNoZjMKQhDbeSn4r0L0A7Ea0g5hjX5MujwaRQhyjs/JuzEAU6oGQi9+C9nTj7X0CSh4yLVUQq//3nIVWlDyRDPzCaJPBuy7VY= X-Gm-Message-State: AOJu0YyeCO/fmPfkcaHsdSn/oSPAhctCKBOMJ16wBK11Y0YXxVuDC6br AZnGQhOOPOV/0hxzxs7LpTajqwFC0pEWbE+HlI6bqxgbAOAnN2wb X-Google-Smtp-Source: AGHT+IHUmNqXbAuG9ebm/RAQnQZyNG6/KlomjZUIhdQfBpuLpROQHVzZLyqbivlJ0FFo0A2paHwd4w== X-Received: by 2002:a5d:550d:0:b0:33e:c974:1290 with SMTP id b13-20020a5d550d000000b0033ec9741290mr533448wrv.18.1711492207281; Tue, 26 Mar 2024 15:30:07 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:90ec:252a:cdf5:54e9]) by smtp.gmail.com with ESMTPSA id bs20-20020a056000071400b00341de138a2esm600647wrb.94.2024.03.26.15.30.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 15:30:06 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [RFC PATCH 07/13] pinctrl: renesas: pinctrl-rzg2l: Validate power registers for SD and ETH Date: Tue, 26 Mar 2024 22:28:38 +0000 Message-Id: <20240326222844.1422948-8-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar On RZ/V2H(P) SoC, the power registers for SD and ETH do not exist, resulting in invalid register offsets. Ensure that the register offsets are valid before any read/write operations are performed. If the power registers are not available, both SD and ETH will be set to -EINVAL. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 348fdccaff72..705372faaeff 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -184,8 +184,8 @@ */ struct rzg2l_register_offsets { u16 pwpr; - u16 sd_ch; - u16 eth_poc; + int sd_ch; + int eth_poc; }; /** @@ -2567,8 +2567,10 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev) rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true); for (u8 i = 0; i < 2; i++) { - cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); - cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); + if (regs->sd_ch != -EINVAL) + cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); + if (regs->eth_poc != -EINVAL) + cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); } cache->qspi = readb(pctrl->base + QSPI); @@ -2599,8 +2601,10 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) writeb(cache->qspi, pctrl->base + QSPI); writeb(cache->eth_mode, pctrl->base + ETH_MODE); for (u8 i = 0; i < 2; i++) { - writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); - writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); + if (regs->sd_ch != -EINVAL) + writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); + if (regs->eth_poc != -EINVAL) + writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); } rzg2l_pinctrl_pm_setup_pfc(pctrl); From patchwork Tue Mar 26 22:28:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 784242 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4299313E03D; Tue, 26 Mar 2024 22:30:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492212; cv=none; b=fodvRPvWH9WWn2SfBjM1DNjepf1nVQk81lp9lWpqwJI4lZ+HZVYmt4hNLiOlk+Xh6Efc2i5sc8yokIz79HALUvZvskbEVsptVil9ZePTbUPeYg41rZWRuPUJXBU9VmX5BrwuIj+2C512JJ+XzrBPdSpyCgUT773GgmdVajs+HF0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492212; c=relaxed/simple; bh=0H2ZfDNM6t107tCbGNszRTnw+5bTLOhziox96iYRPp8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FSmMFBS3l+06tjBOmW26LX3Wluv+omZrjddI0Tx5uCwY6J/h67ESznReMV15JwhBbNI8mbslRCZgiMsvKf16FZ6Tizn4owvNDPChKicIUInUM5TQ6gXTmUCUnfux91+yazdJmi6wtWxPns9c0KBqY/QJ9BQ3QAuGpOXDLx1LykE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=l051wszG; arc=none smtp.client-ip=209.85.221.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="l051wszG" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-33ed6078884so149120f8f.1; Tue, 26 Mar 2024 15:30:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711492208; x=1712097008; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c/PlD95PTusZrY9bo1CqW5ZAjeK4ledYfN/qKGSQZW4=; b=l051wszGUI7eT+a/SHSj6xNCkI99kmHoii6DsBJv2a+vDGc10v9xKOk770pCRMuJmG R/Dt2kXCJ2AJh6knUOmrEib98sMHRLehERcO8YjqU3t0Y2AoC43AFeAAh4ar780LRaX+ 31REGRMT4UXKlG2rnIqcJuXuvZ36V3nVggJpJkuksz6WSlU6r2fBPf7CyvjsXnrKon9w Gc0qEH87e6tsIZJOLqVhXyP1ywbTcC/iYFASi1NOK5vz3135n9xTNJ4N4CsVDmkUYVQb CtcW25dzIXI4piRcwMs9Cuu03yXLST7xBLbcqWgzrKpZF6BulaR3eASlpCOT+nTnrBjt E8Zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711492208; x=1712097008; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c/PlD95PTusZrY9bo1CqW5ZAjeK4ledYfN/qKGSQZW4=; b=kkcijoKCnxcllEZnSp6CfFGn5CufuhUIGcFoMP3bgfhthxjweTOtqyOEDGhXwNR8/5 FyIhg7dtMMxqHOUpLkoTAcMp+OhBeIRhEIXn5CocZVWszOXL0RVcSgBdOwaaOtKEuzXu RxiY83IrTDolO8VzbR5R7YML8fuGQKcnorSfUlswCspi38i7U8YXwrwZ/uoAXlOVZZFB DgWyFPTtrDffFVJX6/x8rau1FJitCmwucnlmYrtiDyWRLztGociNYuPYG7xDf0/mL6O/ ARchLGSRw639WeHjNAdRHviqOAlS1UCNB9DYoKFYIsRl3g8NeEbKgmM4IdB7UJ5yrZ1R r02Q== X-Forwarded-Encrypted: i=1; AJvYcCWBKNQuKWqjj62kx4HbtbLnCrWdfVh6XPCQvGrLSnTFrszskuo66J29zXSgiaUACvGe/6X/zk1/hmntDcWNHLfKK7jEX3hr5llQHlSCZYs9M4TJdB+pbiwj6bxYf8pSj6G0OnuYnmOU3LdHAutUv0PmK6i7KefTXthzc8UbkjAf8Weu68M= X-Gm-Message-State: AOJu0YxioeBv6IGR52nKG36sZ42ZNFxJhdQSinUQ8GRwC2x/331Pylo5 kTNv6PTFyeTlh6hjweb5J63N/8Db9jKnoOZCe/1IRmiUwBLnhN/w X-Google-Smtp-Source: AGHT+IFP1rkzrdRjJDxHgm+Xx2xHI1J5l15F1U7nMF4j6udTZsLIdM/nVw4EW8KSnBpScrjEFKaJXA== X-Received: by 2002:adf:e68e:0:b0:341:cb34:780a with SMTP id r14-20020adfe68e000000b00341cb34780amr2063276wrm.28.1711492208604; Tue, 26 Mar 2024 15:30:08 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:90ec:252a:cdf5:54e9]) by smtp.gmail.com with ESMTPSA id bs20-20020a056000071400b00341de138a2esm600647wrb.94.2024.03.26.15.30.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 15:30:07 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [RFC PATCH 08/13] pinctrl: renesas: pinctrl-rzg2l: Add function pointers for writing to PFC Date: Tue, 26 Mar 2024 22:28:39 +0000 Message-Id: <20240326222844.1422948-9-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar On the RZ/G2L SoC, the PFCWE bit controls writing to PFC registers. However, on the RZ/V2H(P) SoC, the PFCWE (REGWE_A on RZ/V2H) bit controls writing to both PFC and PMC registers. To accommodate these differences across SoC variants, introduce set_pfc_mode() and pm_set_pfc() function pointers. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 705372faaeff..4cdebdbd8a04 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -246,6 +246,8 @@ struct rzg2l_variable_pin_cfg { u32 pin:3; }; +struct rzg2l_pinctrl; + struct rzg2l_pinctrl_data { const char * const *port_pins; const u64 *port_pin_configs; @@ -256,6 +258,8 @@ struct rzg2l_pinctrl_data { const struct rzg2l_hwcfg *hwcfg; const struct rzg2l_variable_pin_cfg *variable_pin_cfg; unsigned int n_variable_pin_cfg; + void (*set_pfc_mode)(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func); + void (*pm_set_pfc)(struct rzg2l_pinctrl *pctrl); }; /** @@ -526,7 +530,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); - rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); + pctrl->data->set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); } return 0; @@ -2607,7 +2611,7 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); } - rzg2l_pinctrl_pm_setup_pfc(pctrl); + pctrl->data->pm_set_pfc(pctrl); rzg2l_pinctrl_pm_setup_regs(pctrl, false); rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, false); rzg2l_gpio_irq_restore(pctrl); @@ -2672,6 +2676,8 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { .variable_pin_cfg = r9a07g043f_variable_pin_cfg, .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg), #endif + .set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode, + .pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc, }; static struct rzg2l_pinctrl_data r9a07g044_data = { @@ -2683,6 +2689,8 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), .hwcfg = &rzg2l_hwcfg, + .set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode, + .pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc, }; static struct rzg2l_pinctrl_data r9a08g045_data = { @@ -2693,6 +2701,8 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins), .hwcfg = &rzg3s_hwcfg, + .set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode, + .pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc, }; static const struct of_device_id rzg2l_pinctrl_of_table[] = { From patchwork Tue Mar 26 22:28:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 782837 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E68413DDAA; Tue, 26 Mar 2024 22:30:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492213; cv=none; b=Zkv8oqm3kA/DMJhma3LuJzLZPQCTaet08y4enWQG97cWSbu5DJmQo8mUe/s4N0r3Yl7zDFkvu5klNPWrvDdfzIU38uXSAffEqVhB1KpY4OIHdhyoMe6x//vasd6mTmWGEdVTyPkVgJnUgo5n22ZIFxLxfxRm4KMNedvRYxWk9lQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492213; c=relaxed/simple; bh=fJZONua1k722F9DXtUVDTt7l/NoLflwhpFArfpFPmMc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mVL9eOTjooXYnu1dACkQ18NgDiALFSxEAvCW8dmP+xn1aTxBjMO53QDK4JEHF/Wl4HbRuc6ruS/f8xV6HmMp4uJGW323XDWHNBP0FaU/WDWDh1ChZ8VN6IO/uZmwlQm6GHxj+Ne2i7/Jl/k0soswBrE6DoHXWnX0HA88lspkgYI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=VAu4Ayjy; arc=none smtp.client-ip=209.85.221.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VAu4Ayjy" Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-33ed4d8e9edso4466493f8f.2; Tue, 26 Mar 2024 15:30:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711492210; x=1712097010; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Wa48IttRtjWW//hX/ph7skdP07JnPzQIrLm9sytmiaY=; b=VAu4AyjyvdhyGcQIfxQRawVrY6KxWKD9HpKI5S/0/XuNLK+xnAdMV+GZw33SLBiRWw NGGPigMbP1IhPaYhytdzD5AhsHhGPMO3ao0cAuQO4zua+mFo3XgxSPqVGqI4Y/wVmQNS 7l31c2NHpaKLR8km1r+MnNLqVaRwFV+dW0RcGauoY1dFyo2YNQi1T2uDeTMShV3sK7KM m1hLnApMKCCRzteaJtcF/M7frwSF2rvV6vXya6t8vQ+eOe/SdrV/cT1QSwSMSLNW7ZwT jOfO/7HdaISpeE4rmWtfbAjYEJtuTgLSQBadK/pETJtNvLVeh+xnfQ+CwRfxQ5L+2tpw hKSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711492210; x=1712097010; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Wa48IttRtjWW//hX/ph7skdP07JnPzQIrLm9sytmiaY=; b=bJGoFp4DffcFqQucoU+G+t/dgPEYl51lRhgBm7tqrRQ3J1mAgZFzxch3Mul8S/8Aa7 mJsBUhnz5HflsjJS/HO+UxjEtsGoYii+RnVOp7XXez/Eqf7fXQvuD12Y9Xo0TC/RtjIu uSeFykBHKZzBXI1wzG9eLJWxGy6wUWCha+EOs9A9p0PS6qrHQsBdLLxCyWYEF86jyOLU Gh4aVDrjtrWqaQVjdce3LSHwEOla807FfMgc0zQKEOsgWpO3zVHdZ8QqrE9BzUZxm9Gg RD4BOzgzP4SzupkK82N6u5KCaK4GRFKrYeI3muVSBnfAkpiI/+60GpZekxb9yTxHftDH qn4w== X-Forwarded-Encrypted: i=1; AJvYcCV52Y16zkUxvvR4kFZGJoAniNW7BQfBeaeob5f2IAdS87AxSUdetVCAzmSgVJrbSCBJZr0f2Tx/11I5NuRFd5JTbWAk02TcDIlQp9C3OP6iiQ2p+3ansNvrLZYEi9GzPkDoOBqPOPV40zvDDXO5pD4C/iZAmrT+QsxzDb9peezI3yj1Ew8= X-Gm-Message-State: AOJu0YyGb4ataGUtivsbCGNDzapcoRrPb+225EuB1RR+SxYUIlHmVLP3 Kof72MtEPLaaOb10U6C1eCbgUkUjrnq/o8up0gru+laOFnmCmwWu X-Google-Smtp-Source: AGHT+IHNJXnk4Rb+kaIaJJ+gRnAXbAhv2vuLHJntLquc7vC7kHATLeErtiNu0Kn1h5Z4T7ckZVFdGQ== X-Received: by 2002:adf:f412:0:b0:33d:64c7:5619 with SMTP id g18-20020adff412000000b0033d64c75619mr2673028wro.70.1711492209711; Tue, 26 Mar 2024 15:30:09 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:90ec:252a:cdf5:54e9]) by smtp.gmail.com with ESMTPSA id bs20-20020a056000071400b00341de138a2esm600647wrb.94.2024.03.26.15.30.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 15:30:09 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [RFC PATCH 09/13] pinctrl: renesas: pinctrl-rzg2l: Add function pointer for writing to PMC register Date: Tue, 26 Mar 2024 22:28:40 +0000 Message-Id: <20240326222844.1422948-10-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar This patch introduces a function pointer, pmc_writeb(), in the struct rzg2l_pinctrl_data to facilitate writing to the PMC register. On the RZ/V2H(P) SoC, unlocking the PWPR.REGWE_A bit before writing to PMC registers is required, whereas this is not the case for the existing RZ/G2L family. This addition enables the reuse of existing code for RZ/V2H(P). Additionally, this patch populates this function pointer with appropriate data for existing SoCs. Note that this functionality is only handled in rzg2l_gpio_request(), as PMC unlock/lock during PFC setup will be taken care of in the set_pfc_mode/pm_set_pfc callbacks. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 4cdebdbd8a04..3de97d5e198a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -260,6 +260,7 @@ struct rzg2l_pinctrl_data { unsigned int n_variable_pin_cfg; void (*set_pfc_mode)(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func); void (*pm_set_pfc)(struct rzg2l_pinctrl *pctrl); + void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, void __iomem *addr); }; /** @@ -463,6 +464,11 @@ static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = { }; #endif +static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, void __iomem *addr) +{ + writeb(val, addr); +} + static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { @@ -1413,7 +1419,7 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) /* Select GPIO mode in PMC Register */ reg8 = readb(pctrl->base + PMC(off)); reg8 &= ~BIT(bit); - writeb(reg8, pctrl->base + PMC(off)); + pctrl->data->pmc_writeb(pctrl, reg8, pctrl->base + PMC(off)); spin_unlock_irqrestore(&pctrl->lock, flags); @@ -2678,6 +2684,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { #endif .set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode, .pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc, + .pmc_writeb = &rzg2l_pmc_writeb, }; static struct rzg2l_pinctrl_data r9a07g044_data = { @@ -2691,6 +2698,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { .hwcfg = &rzg2l_hwcfg, .set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode, .pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc, + .pmc_writeb = &rzg2l_pmc_writeb, }; static struct rzg2l_pinctrl_data r9a08g045_data = { @@ -2703,6 +2711,7 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { .hwcfg = &rzg3s_hwcfg, .set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode, .pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc, + .pmc_writeb = &rzg2l_pmc_writeb, }; static const struct of_device_id rzg2l_pinctrl_of_table[] = { From patchwork Tue Mar 26 22:28:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 784241 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB58D13F420; Tue, 26 Mar 2024 22:30:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492214; cv=none; b=dlauUB+i48V7VvvUsoA35XVO5LX67vTNwREjtNLkMgx2kTcq9lvSpc+FFAgplPI9OlHn1rL279DYMyJrFbppByRUIQ05MQ56301raic0NUHAkYa2dlX9qDhIXVIFxfcnN8j22qf4CwCvUgiEXPrwowNTwGuXnQoFGHBrJhXZfbY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492214; c=relaxed/simple; bh=ry/DihWBqFAS5czADTnqSvM71OrE0DpTnMruEEdq/64=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SrDpOBolCZfh/3ctzh4f2sfJ52SD4jlvfG3ClF40sIfH7ln9sZVXOqDWnM+p8uoGAcS7TAchpTxJzUWzP/7eLonyNBQV0YG2spvdY4G8P6W5K2T3VCms8ofvIGJVRFbpL/2KtKvVX9bUGT3as8o560malty8QGbJzrkmZqJkS5o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=CagB35W+; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CagB35W+" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-33ed7ef0ae8so4319103f8f.0; Tue, 26 Mar 2024 15:30:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711492211; x=1712097011; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lIIuyjYgKvlbHZWyIDIL4+6J6/vl+xy082AgaZCuG00=; b=CagB35W+j0YsYHrAkY6GNr4dmrGyUmbxTZPnJ5uJTFXvraUfv5tqZKxWgDr1O4lGI3 N5g5Jk1fZ1iBhP8uykTzittPIJ+MhBnOmCD9wA52LKhp4gpGEJ+K2kPVxH81dODcCaJh FbDsd1CnkaZsAeMtQ/gzJl+fUmmkxQxM5tN3g/oOH+yKa2R0yOXOsOxRjvZnpdVdIeWr BgbDSVc6rMnlGaluzVfRDwRoa6zsWT1Rp0ZL10Z3Qnk7vICAZUPNWO3ROJ0sjT9mzpJl TqHyMGugRDL/Hapc/CMQo8JEptlz/kiljZGiYv2JqqQIv+nyjNXsUnX/AU94n5YjGtF0 aoDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711492211; x=1712097011; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lIIuyjYgKvlbHZWyIDIL4+6J6/vl+xy082AgaZCuG00=; b=iasTWao2HbLE9YZW06KbbiOPKJuz+vdCte9T2yxEGa3ZgO8fkQWGkAaAxiHZPXtx/K UYUN0Yyyn5ckN5KO5BlrBW8iLRuLzkftlpmiAjOB9Y3VVQwPAE6tu0hg6uBB3AMXRULv Lld7vsf2GqiJZlBRAHNAdZzn+A6HWTfnp2o7ywipWDEZXl0tEhraiHsGtqKZlC15gObA CCIzNBZGaSjoy1DDS/YGwhcGpf8RF6/SJ9i9RAWaJvVRQ5JCH/AektaTe0h3iGDg8DFL J5gRdPVkQ8B0XENF41MtiG8SoYOsRYsThedKNGp8FC3xGix9S245pTDlvOzBB80qXv27 tMOg== X-Forwarded-Encrypted: i=1; AJvYcCU8U87Vl476AhYWaRuYM1PKlTTEjzBd/aiUo6I1O2eeOmrzzf57dg7iEyCuHYC/uFsSA/EZffY+0rQ44BdPs7wM7YW9QJBUlhzzQx4TwyM2boYZV9pu+M4TgjyWkzCiuoPT9Gwt/ctiVrKTQDo5V7MyJNT45wJqlKofhdBdPojWqEwAbrg= X-Gm-Message-State: AOJu0Ywoic0Vq/FWKHBoNxZfzxNt7MeLUHxW07gVFDDZ1WFggzd0u6Jm Qt5DwNSLnWyP2woqdERZr36lt0o8xPtx23XmXEGP3+vL378fuYZ8 X-Google-Smtp-Source: AGHT+IF6MheTIv2ZJKp1Ji444fGpvCoXRwse0B6F+l4zy5HfHc9jBwkXEVn9+727Bjia8vH/z02VDA== X-Received: by 2002:a5d:4b81:0:b0:33e:bfb8:7320 with SMTP id b1-20020a5d4b81000000b0033ebfb87320mr9288720wrt.7.1711492211096; Tue, 26 Mar 2024 15:30:11 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:90ec:252a:cdf5:54e9]) by smtp.gmail.com with ESMTPSA id bs20-20020a056000071400b00341de138a2esm600647wrb.94.2024.03.26.15.30.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 15:30:10 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [RFC PATCH 10/13] pinctrl: renesas: pinctrl-rzg2l: Add function pointers for reading/writing OEN register Date: Tue, 26 Mar 2024 22:28:41 +0000 Message-Id: <20240326222844.1422948-11-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar This patch introduces function pointers, read_oen() and write_oen(), in the struct rzg2l_pinctrl_data to facilitate reading and writing to the PFC_OEN register. On the RZ/V2H SoC, unlocking the PWPR.REGWE_B bit before writing to the PFC_OEN register is necessary, and the PFC_OEN register has more bits compared to the RZ/G2L family. To handle these differences between RZ/G2L and RZ/V2H and to reuse the existing code for RZ/V2H, these function pointers are introduced. Additionally, this patch populates these function pointers with appropriate data for existing SoCs. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 3de97d5e198a..9bc110b00cbb 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -261,6 +261,8 @@ struct rzg2l_pinctrl_data { void (*set_pfc_mode)(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func); void (*pm_set_pfc)(struct rzg2l_pinctrl *pctrl); void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, void __iomem *addr); + u32 (*read_oen)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin); + int (*write_oen)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen); }; /** @@ -1120,7 +1122,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, break; case PIN_CONFIG_OUTPUT_ENABLE: - arg = rzg2l_read_oen(pctrl, cfg, _pin, bit); + arg = pctrl->data->read_oen(pctrl, cfg, _pin, bit); if (!arg) return -EINVAL; break; @@ -1228,7 +1230,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, case PIN_CONFIG_OUTPUT_ENABLE: arg = pinconf_to_config_argument(_configs[i]); - ret = rzg2l_write_oen(pctrl, cfg, _pin, bit, !!arg); + ret = pctrl->data->write_oen(pctrl, cfg, _pin, bit, !!arg); if (ret) return ret; break; @@ -2685,6 +2687,8 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { .set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode, .pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc, .pmc_writeb = &rzg2l_pmc_writeb, + .read_oen = &rzg2l_read_oen, + .write_oen = &rzg2l_write_oen, }; static struct rzg2l_pinctrl_data r9a07g044_data = { @@ -2699,6 +2703,8 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { .set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode, .pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc, .pmc_writeb = &rzg2l_pmc_writeb, + .read_oen = &rzg2l_read_oen, + .write_oen = &rzg2l_write_oen, }; static struct rzg2l_pinctrl_data r9a08g045_data = { @@ -2712,6 +2718,8 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { .set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode, .pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc, .pmc_writeb = &rzg2l_pmc_writeb, + .read_oen = &rzg2l_read_oen, + .write_oen = &rzg2l_write_oen, }; static const struct of_device_id rzg2l_pinctrl_of_table[] = { From patchwork Tue Mar 26 22:28:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 782836 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04EC313F006; Tue, 26 Mar 2024 22:30:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492215; cv=none; b=M3s75BApBP/1rL9wYnNhWSwm5NRkdf791pkjSDVobEoHraugR6uq8eqigyVTej0U+ZMvpbgHbS+ao7KVO1bwoNW3/WTxLcaCdmA2/rg66rd20CryQezbTH3auiLwAeIfwAhcpXe6m+Pw51/uaidqQj0diGGCQO/tOWUKQkVobpQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492215; c=relaxed/simple; bh=QmVeROJQ0lincNy5m4Pr7PglStdcHgCo7503gRfib4c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cECGzSlnzb8kD/YTwQMgpTkYRbe1mFRBwyL9Y7Av513YuoQlal4ToK+vO4Ks5QCRE9P1Pkz86bq+QMdZOntBc6kO71s9lAO8leL1aVjfzJK2we3Nsfxyvro3LNbtTw35Q/kE7JxdoE6C0a+lDKkC5aYTySYpzbZdPyIUDtmzUiU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=nOU073AP; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="nOU073AP" Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-33ed7ba1a42so4090200f8f.2; Tue, 26 Mar 2024 15:30:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711492212; x=1712097012; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/LQJQZwwgTr2u1m9ejwhwibmgi3bRpdcmBpljIJFhSk=; b=nOU073AP0KdX0qqb9Z/thlM4ZMQsjdsV8t/2+SrMHB30+nMPoEYJDMB9yCOluN+3um gpSbunEzMM8hR5cSnlW+Izr5er4/O/yqlKvz3tmRAuxq8UgLySS5YtDnAYskekgkPMzu hNYHLF9siCO/iwL1W05HyLjn3r63uPsXgwg7od/9ZeczrIqkb9ns6eArSa88eLonL+uv WjA8lPPgoXJbkVZA/7Lwy8XFP5G8ai8bY60I+3Vww46lA8sFl4O0vMld17SvMRpgU3Yd IELscmqT4iyANeYAMIlJgK0/eQCvI+4qQe1W8t2ONjFgvRvZtKRk7AWwIPHyjy6kXXsP n74w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711492212; x=1712097012; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/LQJQZwwgTr2u1m9ejwhwibmgi3bRpdcmBpljIJFhSk=; b=Z/6mOXq+dFZNoYytVPmhJvMT7TI/nQk8KDAhMPhWDziuMsZ3RqxOBD6czvQDVhozIb 4uM19LeqNbnJJo9usUWs6BNHAsdBFQ4KSV8t5Ko/fyI9/ns6MMVMfp03tzOVD/gpK8m2 Jic7issJ22wc8FWydbQ5jRc1M6Nqdxi6bwGiJ2nom2UX7iYZDhs1NDLi2G2hWMhp9nFN 7FUup+UFgybF0Y/1SFgVxKz6tfZ5pE9ztZ3djNvsXWp0W+i9Cf2y7p75BHQCI+DM9AtV 5PRz3yORi/RAz64fU/xO0YnkyjIweWss+WpEDU3SP5eU1Vok71hOo15xy2WRcZjzAGwd mE7Q== X-Forwarded-Encrypted: i=1; AJvYcCUf93Sp9dK5hgueEcl2eh5fQUOrYygV/gNPysP8xBQRdVqSZdnP98Mg03UdAYIPq/tbM1A/fF3m7XfhQcv+Bb0ggPH0fVYMBTaUy3+ZuKs8yEHS6wJvimMkSYK1ZAJWCRT7zYW0s4VDi0fYtbWM7t/2RR7plH5MIexSxX6zoQfuOLdFu2M= X-Gm-Message-State: AOJu0Ywrzjo9d0rfHDr7VSQ1FFTC3eMUEq8pWVWdrFWGZq6pvvCr4+N2 eJ7t35wmTaZluXXAzUrW/CFejCDjxbrRNruT5pn3BH6RmzaF9K8K X-Google-Smtp-Source: AGHT+IGFop1rfyOa3Etq788IIziOHriMpNXijb1nTDHg9zB8DC6W8pChR/LTy4mbgyV4cbXiDJWT+w== X-Received: by 2002:a5d:51d1:0:b0:33e:6cce:c2ea with SMTP id n17-20020a5d51d1000000b0033e6ccec2eamr9089661wrv.51.1711492212359; Tue, 26 Mar 2024 15:30:12 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:90ec:252a:cdf5:54e9]) by smtp.gmail.com with ESMTPSA id bs20-20020a056000071400b00341de138a2esm600647wrb.94.2024.03.26.15.30.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 15:30:11 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [RFC PATCH 11/13] pinctrl: renesas: pinctrl-rzg2l: Pass pincontrol device pointer to pinconf_generic_parse_dt_config() Date: Tue, 26 Mar 2024 22:28:42 +0000 Message-Id: <20240326222844.1422948-12-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Pass pincontrol device pointer to pinconf_generic_parse_dt_config() in prepration for passing custom params. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 9bc110b00cbb..d64a441b4f55 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -611,7 +611,7 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, return -EINVAL; } - ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); + ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs); if (ret < 0) return ret; From patchwork Tue Mar 26 22:28:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 784240 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1193F13FD95; Tue, 26 Mar 2024 22:30:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492216; cv=none; b=YLw/qfJEqpxteb7PWDlInyfTmmQBetynZK1ZRhEjG4Ga1hdFLbM8hji0NYLGmvPj3s6Ws1ijjIuHhXM+e5sB8TRtbNob81WDiz37FxUYigTmA8WdXehzdBsoFLDRfWH79eGr8bKWnoHPb5tvjApSj2IVvNqrPaJxM06OgZHqEo8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492216; c=relaxed/simple; bh=n4Q+rAJxdl0L0vlun3nV+RMJS1ynmTK2ySSf1lNNzPo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QzyUhqvBnIdIIXokQUxEMtO5MeT5sDzydAyvqlchLSclqKNBOkWr/c57LK3jil/l/RlEUvTYnK0ygGQlx0jlEshMTEXjzQhOLf64QRJlTX53FKD8S08uemM/suSjnsY8SR9EFa6eFI0jiOjfCeyEIxsrb6nV2a/1Do3lYL7dkqs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Qz3eHuq7; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Qz3eHuq7" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-33d90dfe73cso156822f8f.0; Tue, 26 Mar 2024 15:30:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711492213; x=1712097013; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cSLnzc4A97kNjNoMOdC35aW8lG2J1TDCsRnvXQtRKDw=; b=Qz3eHuq7uJcWgHKp6PCMMNqTZnJedJnZQLRNLufTClv0J2u4vaUgH4nqbC+5+14xjW WqhZemS6hBMKXAz+UJ4SzXCznY2xPtar45sexLMV1wwndJAqfPIOKQWFeWNAKYqdsiA0 NVhdJduYlAvbX0QODCyGS+sqZ/E9Bzn10jqovxPsDeStXZSPd15gvvyUf/e6PLEjVUla LohLeZj22Njvycyi/MBTi9gWzTyvgI+jDgUfwyad3eelEFRfH7gZcJtJhhrhwk9zvz9l ZcpgYnl/6x1kVcyfUjn0dkiczyJQUc5p2FxBnUqeRlqTJJNOXojQHERTbXYaYHDEkZt1 4Fzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711492213; x=1712097013; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cSLnzc4A97kNjNoMOdC35aW8lG2J1TDCsRnvXQtRKDw=; b=qlShSehx1l5Swjh5VySGULavRK14fmYWkMPDr4qIZUp0iXPtbdzSmlFcXBnJnqo009 oJyJjOR1LbvgNiIZMtvb5QPGISxUx6MERFpkmKWCTu2BDzEdVgmEX6THdspj/0lKvjVm Q2ncV7KYWuQ+AgIg5+0fw/gorhA5Lnq9Wp3G59qdvOEY21EeHfT1Y+Dj8pdYCND7wCsi yTW7KCufvLBgYGYFu+U+ZpaFik+bNtqanc2Nl4t9MymGPELTz78jN2zD4KXnjBsykFqe 3kEUsjqSRKf7a3AFFvQ2dCOfX84481bN9bsD6H3vxcoRdNRRUWamIneU2GrwJjc26xcb 1Cmw== X-Forwarded-Encrypted: i=1; AJvYcCVL970M3W1h6puxDQKgoUQZz8AjZyM84m88hwxl9KzM0j3QCf2C6KWxkefG93RBM7ivF9qHfyh7PattU1aXseLSyMz9lPIAFW48/uS2nE8nXM4FsDIVtDVgEqURUosBJ39Q7zRriD8o/Cqy7rbUepFtszM1JBbXyNKatkkKMV1H5Qb7SWA= X-Gm-Message-State: AOJu0Yw/61R+w2vPKdWHwepBglxoR0cSJPRtnIFGT8lp0ySM4nVvTXfp pDlBcsCqAVwtJ9pQ5qszPVWTd/HbJNPWc8Iu+6WTsTVPIU0Amo5f X-Google-Smtp-Source: AGHT+IG6TIFa95hfm5ChJDL88OhPCN8Jp40y+qh+csWO8ZlPV31k/sWIZOWbQ1RnTVqRtdkTOs2tvQ== X-Received: by 2002:a5d:6d04:0:b0:341:c473:2919 with SMTP id e4-20020a5d6d04000000b00341c4732919mr3238048wrq.14.1711492213427; Tue, 26 Mar 2024 15:30:13 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:90ec:252a:cdf5:54e9]) by smtp.gmail.com with ESMTPSA id bs20-20020a056000071400b00341de138a2esm600647wrb.94.2024.03.26.15.30.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 15:30:12 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [RFC PATCH 12/13] pinctrl: renesas: pinctrl-rzg2l: Add support to pass custom params Date: Tue, 26 Mar 2024 22:28:43 +0000 Message-Id: <20240326222844.1422948-13-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar In prepration for passing custom params for RZ/V2H(P) SoC assign the custom params that is being passed of struct rzg2l_pinctrl_data. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index d64a441b4f55..6f0c85bb97a8 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -258,6 +258,9 @@ struct rzg2l_pinctrl_data { const struct rzg2l_hwcfg *hwcfg; const struct rzg2l_variable_pin_cfg *variable_pin_cfg; unsigned int n_variable_pin_cfg; + unsigned int num_custom_params; + const struct pinconf_generic_params *custom_params; + const struct pin_config_item *custom_conf_items; void (*set_pfc_mode)(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func); void (*pm_set_pfc)(struct rzg2l_pinctrl *pctrl); void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, void __iomem *addr); @@ -2278,6 +2281,13 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; pctrl->desc.confops = &rzg2l_pinctrl_confops; pctrl->desc.owner = THIS_MODULE; + if (pctrl->data->num_custom_params) { + pctrl->desc.num_custom_params = pctrl->data->num_custom_params; + pctrl->desc.custom_params = pctrl->data->custom_params; +#ifdef CONFIG_DEBUG_FS + pctrl->desc.custom_conf_items = pctrl->data->custom_conf_items; +#endif + } pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); if (!pins) From patchwork Tue Mar 26 22:28:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 782835 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98F591411CB; Tue, 26 Mar 2024 22:30:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492219; cv=none; b=uO7bWVEEsagQdLX+p2aW5TQQ1ZBAX2Zg3yW4uCyIWRGhZWyN0WO1XWRsmA2N0gkwJLtZ8WoZzZXSvyEw3zw+EPJPCFUisgZsy9db0c8uPBUGC9ZJOO7+zyBk30ls6YOX268Bg2lycVGYtrmgwIu1A69YPkt6aQZcV/PM7KQXgTM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711492219; c=relaxed/simple; bh=JwJWMDuWKG7jB0KKjrnJyPt1GfNoAJUbekvIJ+GaHhA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UthXukDJFMDMHxEy6xM166aGPDVeEZPNo/SEe+fXbhiBCQ7YC9IEKoZdFZV/3q8YNbjBQo8HZ4L/PsRwe6570qsufxajURk+u3dAR/RkHy57plWych1+vLm2HLBDZQFpXPN5OdugTzlQ7XlKvyGEJlM3TkKdEdK/aWzZYgzyBzo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=OPgoSSzS; arc=none smtp.client-ip=209.85.221.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OPgoSSzS" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-341cf77b86bso1754431f8f.2; Tue, 26 Mar 2024 15:30:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711492215; x=1712097015; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JoIu7Td2GlNTSNXOZJhq13YmHgWD3Jk9mFKbP6NmLHg=; b=OPgoSSzSRVvqOWQYsRE46Cw5RiWJc/uaYook34yyXsH8rA5tsMfieuuKgZMMtxhNr/ vQ9o6iV8LtHsr9v5L4vP7x8boescUJvhnSjge4CJSawUDv40rRU5SX5Zvv62z6h3kLTW 0Wj1MJ5IUrDwHW1ch+qGZyhwfRBj7Ax0r4wDGBrHli6nmDcIwNLtELHqqoEELn1EgV6O w9gtjzeAYWolf9NAj0oh7tWgdWYvari2RtgbZ1xZpssDLXnpa/1ScItcr3PwbDIeXE8i 56Xhm85tNtIMDYu4mI5YfhXdQeaK4nbBexvePdkehhCZoAby8iAVyxp93/h2q0pbcGN7 QXog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711492215; x=1712097015; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JoIu7Td2GlNTSNXOZJhq13YmHgWD3Jk9mFKbP6NmLHg=; b=BUewrECsbCwxDMrqMvg7JFgrCPDD+spXoZj8ayG75uw/d054KhdYbi7Jywf0PtCZ42 PFldNcuV6Zeq+4t1BFaWhNRv8aUb8Lqqsqr+aHptq+yADuavvXa5nWO5qypd03Xand1E hbet+qkXdDdWlaoHjcifvlK6vagOQr7/PQhxUSG+pdowdqtwtKVPPTr8K5gwnqeULKT+ qK8wQvxOdDCSG93G6WDVhcxkl98rbj7aVWgdGF7og36os5TktJsNtAd966dpE/x+qw46 /5Zt6EHGUTRyYX+JbkL6aM1nT1YDlvkNLdQJHmaE5JHaHxBTNDJthrFaqGiChgA1fMJK hm4g== X-Forwarded-Encrypted: i=1; AJvYcCW2b2S6xShI3uGCxLiLaOkeFm7negsiqYomjjJhsf+QMJdF6k4GNZ1Piuczmvf3vzDX5L19vNJcb/AWnG4gSouuh67mFYRRFe41S/PZz34F5Bvhl5cfHqTnyGHvddiqz75IrhqhRmjjG0N/WWosLWRCftT779a9n7oqSRERb3we4O1UEj0= X-Gm-Message-State: AOJu0YwsZIG4TO2teGKlN3C0e2SjoDTSVn/wsZF80CJu1e3v8XPUdElr i8iIeWrYYAt/8cPQX6XHOtYy3+8z0BP2d8R5Meij7gLDSRopGva4 X-Google-Smtp-Source: AGHT+IF40tcB4K2nTuKxHMWi+PQSLrXQKqNzTdOt0RCe4doJH42o0HJ5Vlc+ApB68YRE6z+yb1ic2Q== X-Received: by 2002:a5d:5b88:0:b0:33e:c0a9:79c with SMTP id df8-20020a5d5b88000000b0033ec0a9079cmr581527wrb.23.1711492214853; Tue, 26 Mar 2024 15:30:14 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:90ec:252a:cdf5:54e9]) by smtp.gmail.com with ESMTPSA id bs20-20020a056000071400b00341de138a2esm600647wrb.94.2024.03.26.15.30.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 15:30:13 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [RFC PATCH 13/13] pinctrl: renesas: pinctrl-rzg2l: Add support for RZ/V2H SoC Date: Tue, 26 Mar 2024 22:28:44 +0000 Message-Id: <20240326222844.1422948-14-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add pinctrl driver support for RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 483 +++++++++++++++++++++++- 1 file changed, 481 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 6f0c85bb97a8..716c11ca5a8f 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -59,6 +59,13 @@ #define PIN_CFG_OEN BIT(15) #define PIN_CFG_VARIABLE BIT(16) #define PIN_CFG_NOGPIO_INT BIT(17) +#define PIN_CFG_OPEN_DRAIN BIT(18) +#define PIN_CFG_SCHMIT_CTRL BIT(19) +#define PIN_CFG_ELC BIT(20) +#define PIN_CFG_IOLH_1 BIT(21) +#define PIN_CFG_IOLH_2 BIT(22) +#define PIN_CFG_IOLH_3 BIT(23) +#define PIN_CFG_IOLH_4 BIT(24) #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ (PIN_CFG_IOLH_##group | \ @@ -70,6 +77,10 @@ #define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \ PIN_CFG_SR) +#define RZV2H_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \ + PIN_CFG_OPEN_DRAIN | \ + PIN_CFG_SR) + #define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \ PIN_CFG_SOFT_PS) @@ -133,6 +144,8 @@ #define PWPR_B0WI BIT(7) /* Bit Write Disable */ #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ +#define PWPR_REGWE_A BIT(6) /* PFC and PMC Register Write Enable */ +#define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable */ #define PM_MASK 0x03 #define PFC_MASK 0x07 @@ -149,6 +162,19 @@ #define RZG2L_TINT_IRQ_START_INDEX 9 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) +/* Custom pinconf parameters */ +#define RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE (PIN_CONFIG_END + 1) + +static const struct pinconf_generic_params renesas_rzv2h_custom_bindings[] = { + { "renesas-rzv2h,output-impedance", RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, 1 }, +}; + +#ifdef CONFIG_DEBUG_FS +static const struct pin_config_item renesas_rzv2h_conf_items[] = { + PCONFDUMP(RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, "output-impedance", "x", true), +}; +#endif + /* Read/write 8 bits register */ #define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) \ do { \ @@ -324,6 +350,8 @@ struct rzg2l_pinctrl { spinlock_t lock; /* lock read/write registers */ struct mutex mutex; /* serialize adding groups and functions */ + raw_spinlock_t pwpr_lock; /* serialize PWPR register access */ + struct rzg2l_pinctrl_pin_settings *settings; struct rzg2l_pinctrl_reg_cache *cache; struct rzg2l_pinctrl_reg_cache *dedicated_cache; @@ -348,6 +376,79 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, return 0; } +static const struct rzg2l_variable_pin_cfg r9a09g057_variable_pin_cfg[] = { + { + .port = 9, + .pin = 0, + .cfg = RZV2H_MPXED_PIN_FUNCS(2) | PIN_CFG_SCHMIT_CTRL, + }, + { + .port = 9, + .pin = 1, + .cfg = RZV2H_MPXED_PIN_FUNCS(2) | PIN_CFG_SCHMIT_CTRL, + }, + { + .port = 9, + .pin = 2, + .cfg = RZV2H_MPXED_PIN_FUNCS(2) | PIN_CFG_SCHMIT_CTRL, + }, + { + .port = 9, + .pin = 3, + .cfg = RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL, + }, + { + .port = 9, + .pin = 4, + .cfg = RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL, + }, + { + .port = 9, + .pin = 5, + .cfg = RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL, + }, + { + .port = 9, + .pin = 6, + .cfg = RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL, + }, + { + .port = 9, + .pin = 7, + .cfg = RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL, + }, + { + .port = 11, + .pin = 0, + .cfg = RZV2H_MPXED_PIN_FUNCS(2) | PIN_CFG_SCHMIT_CTRL, + }, + { + .port = 11, + .pin = 1, + .cfg = RZV2H_MPXED_PIN_FUNCS(2) | PIN_CFG_SCHMIT_CTRL | PIN_CFG_IEN, + }, + { + .port = 11, + .pin = 2, + .cfg = RZV2H_MPXED_PIN_FUNCS(2) | PIN_CFG_SCHMIT_CTRL | PIN_CFG_IEN, + }, + { + .port = 11, + .pin = 3, + .cfg = RZV2H_MPXED_PIN_FUNCS(2) | PIN_CFG_SCHMIT_CTRL | PIN_CFG_IEN, + }, + { + .port = 11, + .pin = 4, + .cfg = RZV2H_MPXED_PIN_FUNCS(2) | PIN_CFG_SCHMIT_CTRL | PIN_CFG_IEN, + }, + { + .port = 11, + .pin = 5, + .cfg = RZV2H_MPXED_PIN_FUNCS(2) | PIN_CFG_SCHMIT_CTRL | PIN_CFG_IEN, + }, +}; + #ifdef CONFIG_RISCV static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = { { @@ -474,6 +575,19 @@ static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, void __iomem * writeb(val, addr); } +static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, void __iomem *addr) +{ + const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; + u8 pwpr; + + raw_spin_lock(&pctrl->pwpr_lock); + pwpr = readb(pctrl->base + regs->pwpr); + writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr); + writeb(val, addr); + writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); + raw_spin_unlock(&pctrl->pwpr_lock); +} + static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { @@ -512,6 +626,47 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, spin_unlock_irqrestore(&pctrl->lock, flags); }; +static void rzv2h_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, + u8 pin, u8 off, u8 func) +{ + const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; + unsigned long flags; + u32 reg; + u8 pwpr; + + spin_lock_irqsave(&pctrl->lock, flags); + + /* Set pin to 'Non-use (Hi-Z input protection)' */ + reg = readw(pctrl->base + PM(off)); + reg &= ~(PM_MASK << (pin * 2)); + writew(reg, pctrl->base + PM(off)); + + /* Set the PWPR register to allow PFC and PMC register to write */ + raw_spin_lock(&pctrl->pwpr_lock); + pwpr = readb(pctrl->base + regs->pwpr); + writeb(PWPR_PFCWE | pwpr, pctrl->base + regs->pwpr); + + /* Temporarily switch to GPIO mode with PMC register */ + reg = readb(pctrl->base + PMC(off)); + writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); + + /* Select Pin function mode with PFC register */ + reg = readl(pctrl->base + PFC(off)); + reg &= ~(PFC_MASK << (pin * 4)); + writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); + + /* Switch to Peripheral pin function with PMC register */ + reg = readb(pctrl->base + PMC(off)); + writeb(reg | BIT(pin), pctrl->base + PMC(off)); + + /* Set the PWPR register to be write-protected */ + pwpr = readb(pctrl->base + regs->pwpr); + writeb(pwpr & ~PWPR_PFCWE, pctrl->base + regs->pwpr); + raw_spin_unlock(&pctrl->pwpr_lock); + + spin_unlock_irqrestore(&pctrl->lock, flags); +}; + static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, unsigned int group_selector) @@ -1087,14 +1242,26 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 return 0; } +static u32 rzv2h_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin) +{ + /* stub */ + return 0; +} + +static int rzv2h_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen) +{ + /* stub */ + return -EINVAL; +} + static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, unsigned int _pin, unsigned long *config) { struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param = pinconf_to_config_param(*config); const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; + u32 param = pinconf_to_config_param(*config); u64 *pin_data = pin->drv_data; unsigned int arg = 0; u32 off, cfg; @@ -1180,6 +1347,30 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, break; } + case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: { + u8 val; + + if (!(cfg & (PIN_CFG_IOLH_1 | PIN_CFG_IOLH_2 | PIN_CFG_IOLH_3 | PIN_CFG_IOLH_4))) + return -EINVAL; + + val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); + switch (val) { + case 0: + arg = 1; + break; + case 1: + arg = 2; + break; + case 2: + arg = 4; + break; + default: + arg = 6; + break; + } + break; + } + default: return -ENOTSUPP; } @@ -1199,9 +1390,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; u64 *pin_data = pin->drv_data; - enum pin_config_param param; unsigned int i, arg, index; u32 cfg, off; + u32 param; int ret; u8 bit; @@ -1283,6 +1474,32 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); break; + case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: + arg = pinconf_to_config_argument(_configs[i]); + + if (!(cfg & (PIN_CFG_IOLH_1 | PIN_CFG_IOLH_2 | + PIN_CFG_IOLH_3 | PIN_CFG_IOLH_4))) + return -EINVAL; + + switch (arg) { + case 1: + index = 0; + break; + case 2: + index = 1; + break; + case 4: + index = 2; + break; + case 6: + index = 3; + break; + default: + return -EINVAL; + } + rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); + break; + default: return -EOPNOTSUPP; } @@ -1730,6 +1947,38 @@ static const u64 r9a08g045_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */ }; +static const char * const rzv2h_gpio_names[] = { + "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07", + "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17", + "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27", + "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37", + "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47", + "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57", + "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67", + "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77", + "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87", + "P90", "P91", "P92", "P93", "P94", "P95", "P96", "P97", + "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", + "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", +}; + +static const u64 r9a09g057_gpio_configs[] = { + RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL), /* P0 */ + RZG2L_GPIO_PORT_PACK(6, 0x21, RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL), /* P1 */ + RZG2L_GPIO_PORT_PACK(2, 0x22, RZV2H_MPXED_PIN_FUNCS(4)), /* P2 */ + RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL), /* P3 */ + RZG2L_GPIO_PORT_PACK(8, 0x24, RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL), /* P4 */ + RZG2L_GPIO_PORT_PACK(8, 0x25, RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL), /* P5 */ + RZG2L_GPIO_PORT_PACK(8, 0x26, RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL | + PIN_CFG_ELC), /* P6 */ + RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL), /* P7 */ + RZG2L_GPIO_PORT_PACK(8, 0x28, RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL | + PIN_CFG_ELC), /* P8 */ + RZG2L_GPIO_PORT_PACK(8, 0x29, PIN_CFG_VARIABLE), /* P9 */ + RZG2L_GPIO_PORT_PACK(8, 0x2a, RZV2H_MPXED_PIN_FUNCS(3) | PIN_CFG_SCHMIT_CTRL), /* PA */ + RZG2L_GPIO_PORT_PACK(6, 0x2b, PIN_CFG_VARIABLE), /* PB */ +}; + static const struct { struct rzg2l_dedicated_configs common[35]; struct rzg2l_dedicated_configs rzg2l_pins[7]; @@ -1856,6 +2105,139 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { PIN_CFG_IO_VMC_SD1)) }, }; +static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = { + { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | + PIN_CFG_FILCLKSEL)) }, + { "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_1 | PIN_CFG_SR | + PIN_CFG_IEN)) }, + { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_1 | PIN_CFG_SR)) }, + { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_1 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_1 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_1 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_1 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD | PIN_CFG_OEN)) }, + { "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD | PIN_CFG_OEN)) }, + { "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_1 | PIN_CFG_SR | + PIN_CFG_PUPD | PIN_CFG_OEN)) }, + { "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_1 | PIN_CFG_SR | + PIN_CFG_PUPD | PIN_CFG_OEN)) }, + { "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) }, + { "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) }, + { "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) }, + { "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR)) }, + { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR)) }, + { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_IOLH_2 | PIN_CFG_PUPD)) }, + { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR)) }, + { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD1_DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD1_DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD1_DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD1_DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_1 | PIN_CFG_SR)) }, + { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_1 | PIN_CFG_SR)) }, + { "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) }, + { "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) }, + { "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) }, + { "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD | PIN_CFG_OEN)) }, + { "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) }, + { "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) }, + { "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) }, + { "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) }, + { "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) }, + { "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) }, + { "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_SR | PIN_CFG_IEN | + PIN_CFG_PUPD)) }, + { "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) }, + { "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) }, + { "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) }, + { "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD | PIN_CFG_OEN)) }, + { "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) }, + { "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) }, + { "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_2 | PIN_CFG_SR | + PIN_CFG_PUPD)) }, + { "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) }, + { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) }, + { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) }, + { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) }, +}; + static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) { const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; @@ -2380,6 +2762,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT > ARRAY_SIZE(rzg2l_gpio_names)); + BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT > + ARRAY_SIZE(rzv2h_gpio_names)); + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) return -ENOMEM; @@ -2402,6 +2787,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) spin_lock_init(&pctrl->lock); spin_lock_init(&pctrl->bitmap_lock); + raw_spin_lock_init(&pctrl->pwpr_lock); mutex_init(&pctrl->mutex); atomic_set(&pctrl->wakeup_path, 0); @@ -2578,6 +2964,65 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ } +static void rzv2h_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) +{ + u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; + const struct rzg2l_register_offsets *regs = &hwcfg->regs; + u8 pwpr; + + /* Set the PWPR register to allow PFC + PMC register to write. */ + raw_spin_lock(&pctrl->pwpr_lock); + pwpr = readb(pctrl->base + regs->pwpr); + writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr); /* REGWE_A=1 */ + + /* Restore port registers. */ + for (u32 port = 0; port < nports; port++) { + unsigned long pinmap; + u8 pmc = 0, max_pin; + u32 off, pfc = 0; + u64 cfg; + u16 pm; + u8 pin; + + cfg = pctrl->data->port_pin_configs[port]; + off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); + pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); + max_pin = fls(pinmap); + + pm = readw(pctrl->base + PM(off)); + for_each_set_bit(pin, &pinmap, max_pin) { + struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; + + /* Nothing to do if PFC was not configured before. */ + if (!(cache->pmc[port] & BIT(pin))) + continue; + + /* Set pin to 'Non-use (Hi-Z input protection)' */ + pm &= ~(PM_MASK << (pin * 2)); + writew(pm, pctrl->base + PM(off)); + + /* Temporarily switch to GPIO mode with PMC register */ + pmc &= ~BIT(pin); + writeb(pmc, pctrl->base + PMC(off)); + + /* Select Pin function mode. */ + pfc &= ~(PFC_MASK << (pin * 4)); + pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4))); + writel(pfc, pctrl->base + PFC(off)); + + /* Switch to Peripheral pin function. */ + pmc |= BIT(pin); + writeb(pmc, pctrl->base + PMC(off)); + } + } + + /* Set the PWPR register to be write-protected. */ + pwpr = readb(pctrl->base + regs->pwpr); + writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); /* REGWE_A=0 */ + raw_spin_unlock(&pctrl->pwpr_lock); +} + static int rzg2l_pinctrl_suspend_noirq(struct device *dev) { struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); @@ -2682,6 +3127,14 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = { .oen_max_port = 7, /* P7_1 is the maximum OEN port. */ }; +static const struct rzg2l_hwcfg rzv2h_hwcfg = { + .regs = { + .pwpr = 0x3c04, + .sd_ch = 0x0, + .eth_poc = 0x0, + }, +}; + static struct rzg2l_pinctrl_data r9a07g043_data = { .port_pins = rzg2l_gpio_names, .port_pin_configs = r9a07g043_gpio_configs, @@ -2732,6 +3185,28 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { .write_oen = &rzg2l_write_oen, }; +static struct rzg2l_pinctrl_data r9a09g057_data = { + .port_pins = rzv2h_gpio_names, + .port_pin_configs = r9a09g057_gpio_configs, + .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs), + .dedicated_pins = rzv2h_dedicated_pins, + .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT, + .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins), + .hwcfg = &rzv2h_hwcfg, + .variable_pin_cfg = r9a09g057_variable_pin_cfg, + .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg), + .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings), + .custom_params = renesas_rzv2h_custom_bindings, +#ifdef CONFIG_DEBUG_FS + .custom_conf_items = renesas_rzv2h_conf_items, +#endif + .set_pfc_mode = &rzv2h_pinctrl_set_pfc_mode, + .pm_set_pfc = &rzv2h_pinctrl_pm_setup_pfc, + .pmc_writeb = &rzv2h_pmc_writeb, + .read_oen = &rzv2h_read_oen, + .write_oen = &rzv2h_write_oen, +}; + static const struct of_device_id rzg2l_pinctrl_of_table[] = { { .compatible = "renesas,r9a07g043-pinctrl", @@ -2745,6 +3220,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = { .compatible = "renesas,r9a08g045-pinctrl", .data = &r9a08g045_data, }, + { + .compatible = "renesas,r9a09g057-pinctrl", + .data = &r9a09g057_data, + }, { /* sentinel */ } };