From patchwork Wed Mar 27 12:24:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 784238 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 216E713EFE1; Wed, 27 Mar 2024 12:25:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711542306; cv=none; b=G5LstJAughHiascoijtT448F7Ko46z6srs3D3lEtlRvELGqoQwOgT3zmbEm6ORFjNsnlTmc6sXUU9YvL42YYgCyBjr2u63nHO9XvDB+wPrcBevjozFE2Arxg5pcmTSDzkOhCXfRO9EFI+Uma4aIBP1vkxMKx0eXcBICTRU5Fa2g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711542306; c=relaxed/simple; bh=X6Q17iok1lsELRt2E1A4QpgQ+0x+/0qVC3vmN5bsp/U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mBr5r/J9WP+RUE4zqz6CkSmp3qWdVr18Nqgz7ffd9ryy/T9q4Gz+2yHi5rawGTB+ZD3xTJilzOAVbXv/5J0AyypyGIXHpQyfP6CYgyyqqTWXYYSDkF/5a2wxpCKOJDrMxhJCdmiUo+i+dyfUgOQoTSKIuc85gOODjcYy+VsVnuo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qHLddTCl; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qHLddTCl" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B3AE4C433F1; Wed, 27 Mar 2024 12:25:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711542306; bh=X6Q17iok1lsELRt2E1A4QpgQ+0x+/0qVC3vmN5bsp/U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qHLddTCldCQc+zy2KauTb0OEL19C/ZeAtYJN6nFb+A8mdqD6YkBN+M8Bxh/AdNikO buRI0qewxr/ZaIWGFYdzCTl6Gv+RsoBnAlcfBmr9KGMxBuXI3pJYbMh+P8L1zLyhx2 iLtM94jJ11V1gz7lLelQfy94vpn6TRB1kTWBvyVzm0aNi5tVHT8vPmz8oEGt3l6fvE QdGQtL8OjrgA1mCZf6OFDsqL3HwWRyd4+/E8wGZNsqkG7tjxf05SR/bswKgUpn9tFQ cxX8P48S5ffTReyax34KkflEXjTW48yOhRDn4aAzKNgI7xxcpWj0iR93pGTAkac01F GSF764hUTtFPg== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Jamie Gibbons , Valentina Fernandez , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v1 1/5] dt-bindings: riscv: microchip: document beaglev-fire Date: Wed, 27 Mar 2024 12:24:36 +0000 Message-ID: <20240327-camper-brownnose-6392076d8699@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240327-parkway-dodgy-f0fe1fa20892@spud> References: <20240327-parkway-dodgy-f0fe1fa20892@spud> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=888; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=IXE+G6TXDdUlSmW7mF73cGLzEXQoXwEvNEi4hyJZUcA=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGksAqyWxyxDf27KOX45Wc6gK/FjWPo5fVG+mL6XUyzOG oavaJ3XUcrCIMbBICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgInUljAytJzJPjW94muSCof5 xEw/ruBlqzbOO3DwwKtM0Svf5VZUHmBkOHtBweWu0Nv2tfc3HlrA9/9UdZEFM8duP4nZh9WX7jv Zxg0A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Conor Dooley The BeagleV Fire is a BeagleBone Black form-factor board with a PolarFire SoC. Link: https://www.beagleboard.org/boards/beaglev-fire Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/microchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 4a29c890619a..78ce76ae1b6d 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -29,6 +29,7 @@ properties: - enum: - aldec,tysom-m-mpfs250t-rev2 - aries,m100pfsevp + - beagle,beaglev-fire - microchip,mpfs-sev-kit - sundance,polarberry - const: microchip,mpfs From patchwork Wed Mar 27 12:24:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 783327 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7ACC1304A6; Wed, 27 Mar 2024 12:25:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711542309; cv=none; b=D1lZjuHNfHqIChXzbVXJVNcN7IdnTYKN44BoljArMMomZddzOONr49NK0qzUS7JxJZ1IUenytnYioOKmj5TDdKi4BHQ7eLlpxS1Xd50rNH9daGbX9g5Q5UA+QOyEpYZYGEdjGgYVW/kz1g85JY2+qWfUuul4PqSJBvC7UxpQ9q8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711542309; c=relaxed/simple; bh=gPsBJl3+lGsrZ281LklEHOtcSRqfcnJMec/DLgQQb8o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aVxD+Ps+HcTqAWErD6OlFUULNDjRe2t8URgpxPASIoSxvw0YeXt5Ug+fBkM2A9ceQPfJT8whbJ6ezPVp07hG/KhcQj3SPk+06HLhHSAoiVuGkTSUIct9YysW46kEwBJpxxarKbMJwRIBjzRuW3zh4k+85P+5O4lCHt+kLgrmDwg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZW0wI5Tc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZW0wI5Tc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6C66DC43394; Wed, 27 Mar 2024 12:25:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711542309; bh=gPsBJl3+lGsrZ281LklEHOtcSRqfcnJMec/DLgQQb8o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZW0wI5TcjqElnMJHmeOioieZAl/zxdpw5U71hNTwAiAOmdOqr5q57K4xXpMTNQlBJ 6e+ut/LCN1zr7rhWDODQTIhyaGsz/yh0n0UwnqPd2EMLtSGSTH2JBnm0p8kF8FTUWF F/3Gvz8GPQ+FkMlTLULmuhkOMb4LUvPzx++1I+ojrCBvOAX1do3NRcymbivSJA7D2H OX+QqBB06vYQxtVrF3KHwgrhGaxnrPU3HS6SK11uiB0QF3caMzPMbuu+pVKBYNfTzz pvSOT4kzC3+TfCifJDNMaRLnoaXfWC2tpSig0c7hZlBJfYf3zUa7w20oWjayF8El8t MOnvJgJ3IHZ8g== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Jamie Gibbons , Valentina Fernandez , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v1 2/5] dt-bindings: gpio: mpfs: add coreGPIO support Date: Wed, 27 Mar 2024 12:24:37 +0000 Message-ID: <20240327-procurer-rascal-33bca7d5d14b@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240327-parkway-dodgy-f0fe1fa20892@spud> References: <20240327-parkway-dodgy-f0fe1fa20892@spud> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1550; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=IMTT4E9wFHswzy76N6YWQpUY7X5/7P9UPRxEwIXGGcY=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGksAqwlMoeOTjkgsrLk+pXsCh2fyQc/lKY92M0gOH2W/ 432/QYKHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZhI/XdGhuN8d3y0a4TunTev fNci3W7XI797eZTd4m2zI8QWsjrJPWdkmBsmwLN97pkHCSZ/pzQrpjxmr73q8vSSXd9OEc71i/1 k2AA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Jamie Gibbons The GPIO controllers on PolarFire SoC were based on the "soft" IP CoreGPIO, but the inp/outp registers are at different offsets. Add compatible to allow for support of both sets of offsets. The soft core will not always have interrupts wired up, so only enforce them for the "hard" core on PolarFire SoC. Signed-off-by: Jamie Gibbons Signed-off-by: Conor Dooley Reviewed-by: Rob Herring --- .../bindings/gpio/microchip,mpfs-gpio.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml index d481e78958a7..6884dacb2865 100644 --- a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml @@ -14,6 +14,7 @@ properties: items: - enum: - microchip,mpfs-gpio + - microchip,coregpio-rtl-v3 reg: maxItems: 1 @@ -62,12 +63,21 @@ patternProperties: - gpio-hog - gpios +allOf: + - if: + properties: + compatible: + contains: + const: microchip,mpfs-gpio + then: + required: + - interrupts + - "#interrupt-cells" + - interrupt-controller + required: - compatible - reg - - interrupts - - "#interrupt-cells" - - interrupt-controller - "#gpio-cells" - gpio-controller - clocks From patchwork Wed Mar 27 12:24:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 784237 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E44F818148F; Wed, 27 Mar 2024 12:25:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711542314; cv=none; b=NannlXB46Tx+Kywwx60Zmc6f6MwAL2o70MZnBuwcolJeXGXDc6zXQ9IJAjFZ8XPkfjD4GtpiC/eKA1PwUTnKgMLVdpf8j7La+cUuftA/oVKUHFYDOH2Y8kPu/1ikZweO0KGwWfHrudbra8S6LRL0M9xt7TOZ7KTDye4K1qNqdtM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711542314; c=relaxed/simple; bh=038VBIDo7wOXasBPUdMTZ8PLRSWfD0Ugbh34YKcaqAw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ii19KBDOEH7YAYN2vV+X0tWKB8Jqr/aaBuqcOXNrcnDMDA9s9z24vvP3/YVDFs5S3NQ41KYm5NGDiXsdRO/2QUJ+RKXIMTg56k2vyqcgYFu7O2yPtK31yJBNubtwcpqMmXny6hUSozQfEjz4mgH6A+5OjIXkTuoHnyBxeqt+Qls= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Kwr1lYv2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Kwr1lYv2" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 23145C43399; Wed, 27 Mar 2024 12:25:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711542313; bh=038VBIDo7wOXasBPUdMTZ8PLRSWfD0Ugbh34YKcaqAw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Kwr1lYv2X1QC6vcz5l+zu2KW28jKDMcUCckfHzTia2WHhQHNUkkqzcxlIhuH8bH0V oHRouwHNl91AZtFpfS8uSq4B8BjUJgT486AJqQp4NaDGbAoH+TEFEEZWT4AZusOaye ZNM0LetAPWIAXXHZHwqm7me/VV/2c/Mrj3fM3pvBRJkG7thwftZ8ovy/oN874gGMNa Ya4K0P3ZAtuGs68/oELfhLaGSxxvqRF3HHkpASq14EzDDMcOoNNu2QpGaPK3yNH8+q gZl+bRFZmz7AaPGs47pDBXEfvJz7WJebsBOGGgbXxhsynKneIAdK3NkdTNVFQ4ijgr at8b6J9qN8j7w== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Jamie Gibbons , Valentina Fernandez , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v1 3/5] dt-bindings: gpio: mpfs: allow gpio-line-names Date: Wed, 27 Mar 2024 12:24:38 +0000 Message-ID: <20240327-overrate-overuse-1e32abccd001@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240327-parkway-dodgy-f0fe1fa20892@spud> References: <20240327-parkway-dodgy-f0fe1fa20892@spud> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=815; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=DQ/xOk1TKoK84RFxAr9nUQRMqrU2scD4cxuVi4j2DRs=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGksAqyTq1tfxFl23mh4eOftRUHLExaKZ7ubjEPOpDEK3 2X0bLvVUcrCIMbBICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgIk08TEyXHq56IBz2p6VonO0 3HTV9HW9zr01q1DPEmzO9hK6UpOUxcjwbcfUFsHNTqqXMqcvmMXHE3Zk3bklDh+7eJ8t2SI0c4Y FPwA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Jamie Gibbons The BeagleV Fire devicetree will make use of gpio-line-names, allow it in the binding. Signed-off-by: Jamie Gibbons Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml index 6884dacb2865..d61569b3f15b 100644 --- a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml @@ -44,6 +44,7 @@ properties: default: 32 gpio-controller: true + gpio-line-names: true patternProperties: "^.+-hog(-[0-9]+)?$": From patchwork Wed Mar 27 12:24:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 783326 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3752E181BAC; Wed, 27 Mar 2024 12:25:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711542317; cv=none; b=nG+remQwbAF3tjdIFEfSFO1iZCgTmRdAaZieNi4Y16NJz1b887tMXVLbmpAa7EVV8cmmBCuMCKY8Qk04C8O2EjrpO+eyVTWlWwOUJ5KzhJMaCBZycQaixIdz7HsWrp20WQAP4rmF/9DBacXAwfslihgiceHIXdJ+UoVPtZO6fI0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711542317; c=relaxed/simple; bh=Lbr7IoAyrDhiLzvuJzo9IGXeuw1UGQU0B8IX5xK2H+U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gBOj9NrONB4SWqylfRFcsTcVHbfPr3MKxdJcAVHdLtHhW1bArcA4PN8EJcM1Xo9qlQg2B84vfL8AHhFs3DqERoQDiggBrASIffsZPAzN8XgTVUzApj2Jt3AH+JpQA9aN0n9V4HXjLWnFxpEeKad4351r/Vyt87oOtxSjAX5dHuM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IKG0/+Kx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IKG0/+Kx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CEB2CC433A6; Wed, 27 Mar 2024 12:25:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711542317; bh=Lbr7IoAyrDhiLzvuJzo9IGXeuw1UGQU0B8IX5xK2H+U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IKG0/+KxX65U8B6XpOGDDqAnJTt+kb8aYVgZVTGIIpD0/6rdJUY93+ccYMTxo7IFf LxuZ3RXakM8fegH9uin6VNqDqC6iqCpicoHl1u0Mgi7spfRpjl9uPpFtDKdqmp4RLm QfDGm/DmxnEoUsPk15G/Z29HFv2bws5U7xOtI004KDQd/i+VD5JBOc1sSlWqEThj5A x294jM3hfwg8lL4SkUw7/S7jPbQ4nTp+3lqWRFPO1e43J1L8cMG+/8AO9xhf6tx3YO YzakB6MjgI2zzH1QsxN2LECunJvf1q9iMk6HaJiFSnHNxxvVAC6oHU4GvECZfehSSa DyY8OGa8cEwNg== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Jamie Gibbons , Valentina Fernandez , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v1 4/5] dt-bindings: PCI: microchip: increase number of items in ranges property Date: Wed, 27 Mar 2024 12:24:39 +0000 Message-ID: <20240327-debunk-perky-f5514ca332be@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240327-parkway-dodgy-f0fe1fa20892@spud> References: <20240327-parkway-dodgy-f0fe1fa20892@spud> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=945; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=buQq0yDz7uxZQBF0BhuHfxwtzcUDoTRsuZxOB+uRXCE=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGksAmxvph4tLRbY8dV+n4ex5fzX1dfyc423lMvFPOeWm sV8+UZsRykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACay7BfDP7UKSWH7FpHjCadu feA3O8MZbdTkc5atf4PHCgsfw0v5exgZFh1rWJJvfVfzX/L1688fGPueFpf4EHqXuWSm3bu3h9s ncwMA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Valentina Fernandez Increase the number of items in the ranges property to allow up to 3 ranges. For example a prefetchable range, a non-prefetchable range and an IO range, depending on configuration. Signed-off-by: Valentina Fernandez Signed-off-by: Conor Dooley Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index f7a3c2636355..e8212a05b7b1 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -65,7 +65,8 @@ properties: - const: msi ranges: - maxItems: 1 + minItems: 1 + maxItems: 3 dma-ranges: minItems: 1 From patchwork Wed Mar 27 12:24:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 784236 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDC7A181CE2; Wed, 27 Mar 2024 12:25:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711542321; cv=none; b=HGIrGTL4DY5oYYjEB5kcDCVV1qq80/la0SoSXsEDp4iyS4uWARFc/mJVVHrZfFvXJ6Tua2yHwxD4kF7cYxltxq3xkDIbh6w1GRZzMPzTwDYhfNwuF4L6TFu9vqtN1Hc8Ke2YoSeUwpGc8oqLWQ2/um/qZ/B9wUob1qbjNeACfGE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711542321; c=relaxed/simple; bh=Fi5YANMykhXfh/CWBHTWx+veKXkxaKsp6BEQ+wOOAdk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ru+DrK+1ywPqszQl75Gry02bMeM3zAu09Bt3i7IjaG7szMSL7XaFDGjrxwsPCMMmbP+T39cRinpkudfPqodrTvjqt90uGVECQZAl/EIJcckMcCnGo9x7kPIO1Tv/ojttANTg6Fw0aMymUaraGJWzLLmvmzO70/qPx/FYFbXFDnI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BE6DnJ3z; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BE6DnJ3z" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 85912C43601; Wed, 27 Mar 2024 12:25:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711542320; bh=Fi5YANMykhXfh/CWBHTWx+veKXkxaKsp6BEQ+wOOAdk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BE6DnJ3zQ940NFCKlMHYxj5eF9TXRc1Le2NrUQRMiw2Cd3KfJ5zMK/6fYjXSPVehI zRm88FyCd0hBvDlr6IfDOWyRZDqCQ9OrbbR4X2mWqg4J8xhE7GuBTfh3lnwn+H1Tid 7r9GuyFwt4v+5KSpsnqfohxsssbGUTWCEgjpeHwT8qxGy4qj+tguWyWs/gIpDDH0F4 LrSu5HTLq5JRpT3mKeMjJK8NlBaZvSFW4sMqup7+wALbnXk+fOZ8oZAvt4xPxZRV37 Xb/by73t9T/2L8HkiO79S0/lbjKQfBOcRnKr3I3Sr6fgLFjTO9JqyXnUJq2ks2RfQn r024H5GsnRovQ== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Jamie Gibbons , Valentina Fernandez , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v1 5/5] riscv: dts: microchip: add an initial devicetree for the BeagleV Fire Date: Wed, 27 Mar 2024 12:24:40 +0000 Message-ID: <20240327-hurry-escapable-e3212bf3cdd8@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240327-parkway-dodgy-f0fe1fa20892@spud> References: <20240327-parkway-dodgy-f0fe1fa20892@spud> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=10766; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=VzkOrHaeB0MJo+Fuu8Q8iocE4H/HvHELUhz5DPz+Uls=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGksAmyZ0wrjJVa9PrtY7bqA8CefW9NY3iu4hUytzBRXf H6HbeG9jlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAEzkRjnDP8UZWr+YD6z5dHfu miq7+znRDZkGm0xmnfxWq12yzFSX8Qwjw4VbweqZ32/0BPwI+HfhhLZV79wA/2Xck60uxmr8bA7 k5AMA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Conor Dooley Add an initial devicetree for the BeagleV Fire. This devicetree differs from that in the BeagleBoard BSP as it has a different memory configuration, however it will boot on the same FPGA images. PCI is disabled for now, as the Linux PCI driver (and the binding) assume which root port instance is in use. This will need to be fixed before PCI can be enabled. Link: https://www.beagleboard.org/boards/beaglev-fire Co-developed-by: Jamie Gibbons Signed-off-by: Jamie Gibbons Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../microchip/mpfs-beaglev-fire-fabric.dtsi | 124 ++++++++++ .../boot/dts/microchip/mpfs-beaglev-fire.dts | 223 ++++++++++++++++++ 3 files changed, 348 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index e177815bf1a2..f51aeeb9fd3b 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-beaglev-fire.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi new file mode 100644 index 000000000000..0abd0dc540be --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/ { + fabric_clk3: fabric-clk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + fabric_clk1: fabric-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + fabric-bus@40000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, /* FIC3-FAB */ + <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>, /* FIC0, LO */ + <0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000>, /* FIC1, LO */ + <0x20 0x0 0x20 0x0 0x10 0x0>, /* FIC0,HI */ + <0x30 0x0 0x30 0x0 0x10 0x0>; /* FIC1,HI */ + + cape_gpios_p8: gpio@41100000 { + compatible = "microchip,coregpio-rtl-v3"; + reg = <0x0 0x41100000 0x0 0x1000>; + clocks = <&fabric_clk3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + gpio-line-names = "P8_PIN31", "P8_PIN32", "P8_PIN33", "P8_PIN34", + "P8_PIN35", "P8_PIN36", "P8_PIN37", "P8_PIN38", + "P8_PIN39", "P8_PIN40", "P8_PIN41", "P8_PIN42", + "P8_PIN43", "P8_PIN44", "P8_PIN45", "P8_PIN46"; + }; + + cape_gpios_p9: gpio@41200000 { + compatible = "microchip,coregpio-rtl-v3"; + reg = <0x0 0x41200000 0x0 0x1000>; + clocks = <&fabric_clk3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <20>; + gpio-line-names = "P9_PIN11", "P9_PIN12", "P9_PIN13", "P9_PIN14", + "P9_PIN15", "P9_PIN16", "P9_PIN17", "P9_PIN18", + "P9_PIN21", "P9_PIN22", "P9_PIN23", "P9_PIN24", + "P9_PIN25", "P9_PIN26", "P9_PIN27", "P9_PIN28", + "P9_PIN29", "P9_PIN31", "P9_PIN41", "P9_PIN42"; + }; + + hsi_gpios: gpio@44000000 { + compatible = "microchip,coregpio-rtl-v3"; + reg = <0x0 0x44000000 0x0 0x1000>; + clocks = <&fabric_clk3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <20>; + gpio-line-names = "B0_HSIO70N", "B0_HSIO71N", "B0_HSIO83N", + "B0_HSIO73N_C2P_CLKN", "B0_HSIO70P", "B0_HSIO71P", + "B0_HSIO83P", "B0_HSIO73N_C2P_CLKP", "XCVR1_RX_VALID", + "XCVR1_LOCK", "XCVR1_ERROR", "XCVR2_RX_VALID", + "XCVR2_LOCK", "XCVR2_ERROR", "XCVR3_RX_VALID", + "XCVR3_LOCK", "XCVR3_ERROR", "XCVR_0B_REF_CLK_PLL_LOCK", + "XCVR_0C_REF_CLK_PLL_LOCK", "B0_HSIO81N"; + }; + }; + + fabric-pcie-bus@3000000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, + <0x30 0x0 0x30 0x0 0x10 0x0>; + + pcie: pcie@3000000000 { + compatible = "microchip,pcie-host-1.0"; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + device_type = "pci"; + reg = <0x30 0x0 0x0 0x8000000>, + <0x0 0x43000000 0x0 0x10000>; + reg-names = "cfg", "apb"; + bus-range = <0x0 0x7f>; + interrupt-parent = <&plic>; + interrupts = <119>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, + <&ccc_nw CLK_CCC_PLL0_OUT3>; + clock-names = "fic1", "fic3"; + ranges = <0x43000000 0x0 0x9000000 0x30 0x9000000 0x0 0xf000000>, + <0x1000000 0x0 0x8000000 0x30 0x8000000 0x0 0x1000000>, + <0x3000000 0x0 0x18000000 0x30 0x18000000 0x0 0x70000000>; + msi-parent = <&pcie>; + msi-controller; + status = "disabled"; + + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; + + refclk_ccc: cccrefclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; +}; + +&ccc_nw { + clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, + <&refclk_ccc>, <&refclk_ccc>; + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", + "dll0_ref", "dll1_ref"; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts new file mode 100644 index 000000000000..47cf693beb68 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2021 Microchip Technology Inc */ + +/dts-v1/; + +#include +#include "mpfs.dtsi" +#include "mpfs-beaglev-fire-fabric.dtsi" + +/* Clock frequency (in Hz) of MTIMER */ +#define MTIMER_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "BeagleBoard BeagleV-Fire"; + compatible = "beagle,beaglev-fire", "microchip,mpfs"; + + aliases { + serial0 = &mmuart0; + serial1 = &mmuart1; + serial2 = &mmuart2; + serial3 = &mmuart3; + serial4 = &mmuart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + timebase-frequency = ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + status = "okay"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hss: hss-buffer@103fc00000 { + compatible = "shared-dma-pool"; + reg = <0x10 0x3fc00000 0x0 0x400000>; + no-map; + }; + }; + + imx219_clk: camera-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + imx219_vana: fixedregulator-0 { + compatible = "regulator-fixed"; + regulator-name = "imx219_vana"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + imx219_vdig: fixedregulator-1 { + compatible = "regulator-fixed"; + regulator-name = "imx219_vdig"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + imx219_vddl: fixedregulator-2 { + compatible = "regulator-fixed"; + regulator-name = "imx219_vddl"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + +}; + +&gpio2 { + interrupts = <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + ngpios=<32>; + gpio-line-names = "P8_PIN3_USER_LED_0", "P8_PIN4_USER_LED_1", "P8_PIN5_USER_LED_2", + "P8_PIN6_USER_LED_3", "P8_PIN7_USER_LED_4", "P8_PIN8_USER_LED_5", + "P8_PIN9_USER_LED_6", "P8_PIN10_USER_LED_7", "P8_PIN11_USER_LED_8", + "P8_PIN12_USER_LED_9", "P8_PIN13_USER_LED_10", "P8_PIN14_USER_LED_11", + "P8_PIN15", "P8_PIN16", "P8_PIN17", "P8_PIN18", "P8_PIN19", "P8_PIN20", + "P8_PIN21", "P8_PIN22", "P8_PIN23", "P8_PIN24", "P8_PIN25", "P8_PIN26", + "P8_PIN27", "P8_PIN28", "P8_PIN29", "P8_PIN30", "M2_W_DISABLE1", + "M2_W_DISABLE2", "VIO_ENABLE", "SD_DET"; + status = "okay"; + + vio-enable-hog { + gpio-hog; + gpios = <30 30>; + output-high; + line-name = "VIO_ENABLE"; + }; + + sd-det-hog { + gpio-hog; + gpios = <31 31>; + input; + line-name = "SD_DET"; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + + imx219: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&imx219_clk>; + VANA-supply = <&imx219_vana>; /* 2.8v */ + VDIG-supply = <&imx219_vdig>; /* 1.8v */ + VDDL-supply = <&imx219_vddl>; /* 1.2v */ + + port { + imx219_0: endpoint { + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; +}; + +&mac0 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mbox { + status = "okay"; +}; + +&mmc { + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&mmuart0 { + status = "okay"; +}; + +&mmuart1 { + status = "okay"; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&refclk_ccc { + clock-frequency = <50000000>; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&syscontroller { + microchip,bitstream-flash = <&sys_ctrl_flash>; + status = "okay"; +}; + +&syscontroller_qspi { + status = "okay"; + + sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + spi-rx-bus-width = <1>; + reg = <0>; + }; +}; + +&usb { + status = "okay"; + dr_mode = "otg"; +};