From patchwork Fri Oct 4 15:52:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 175231 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp889713ill; Fri, 4 Oct 2019 08:57:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqwJ6HnXDTYUCvAbtPVkf9i6uWdS/1wbYBevRuaRZsnP4Gwl//rx9DWGTvXfzVdJX5vC+lti X-Received: by 2002:ae9:de84:: with SMTP id s126mr10590431qkf.245.1570204653473; Fri, 04 Oct 2019 08:57:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570204653; cv=none; d=google.com; s=arc-20160816; b=I7+f8Tm5IwSk6rA8Ynr3q38B3bOv0TKrIohkcvdOiK+GbcuBJXVs192aKIWpoXv8Nz w6548UD91rEsWb8RuSZRO8K7TQqUf/OB/u6Zw09mpmIcjOgcuAXhrkZYuQKSTYS0ERMS O2uGbl4rTKoRMztOLWGeZPvvVY6DVOWkQhabZHiPwbpxhbMwyh5miI1rDfTvEMDL5Fr/ EjjxxBdHzWUrdbRfQJXxpvcfMN03t+fKXZtCCbh9flIQyZuCFaTu8m0axIk4hx4rLa02 V+waaX5wPS5OYl0i9nmAN8ISPiwAH6VW5cqbtvinfLMB+4qpjrHCpekFnH40vp9Dy1mL rmVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version:references :in-reply-to:message-id:date:subject:to:from; bh=8im/z8BRcG2cgBR/bymEYRODDEPl3un3kKapyjA7hHI=; b=Mo3d3aYyr55em/CGbN022On91PmJhqIsj3wAGR/HIZsfDM7nuqYjshE7+l0K0f+6C0 B//pBngAHg/0ZGcoPLRn13t/1fyid2WhTZL37NQ/Ml6TH/CfXJ7dPNsL2L/VxbeJz3it ghyk+15p8Y1H9JcpfQnlVEtSbAO8fxWPYjyzcFx60FeumI3e8OyRgc/vCk0ZALguvD9a 8XpkzKyoZXxlpNMI3qs2P3KlCYAjfjmzHo4hYjcUBAe4sfKj4IIqmDe5DC6i9CgUcRum 6bwLqRX4poSlyGtMk1SV02lmhx5nCgKHsBdFzTmF/RxZo09klVvjpf7ie4ObFijVOEwK CR5Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v10si6103335qta.300.2019.10.04.08.57.33 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 04 Oct 2019 08:57:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:50024 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iGPxU-00076e-JX for patch@linaro.org; Fri, 04 Oct 2019 11:57:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42236) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iGPuU-0006Ll-H9 for qemu-devel@nongnu.org; Fri, 04 Oct 2019 11:54:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iGPuS-0000Y2-JI for qemu-devel@nongnu.org; Fri, 04 Oct 2019 11:54:25 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:44636 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iGPuO-0000QO-93; Fri, 04 Oct 2019 11:54:20 -0400 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id BB987C4B2364335D9FB1; Fri, 4 Oct 2019 23:54:12 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Fri, 4 Oct 2019 23:54:03 +0800 From: Shameer Kolothum To: , , , Subject: [PATCH 1/5] hw/arm: Align ACPI blob len to PAGE size Date: Fri, 4 Oct 2019 16:52:58 +0100 Message-ID: <20191004155302.4632-2-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20191004155302.4632-1-shameerali.kolothum.thodi@huawei.com> References: <20191004155302.4632-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, lersek@redhat.com, linuxarm@huawei.com, xuwei5@hisilicon.com, shannon.zhaosl@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" If ACPI blob length modifications happens after the initial virt_acpi_build() call, and the changed blob length is within the PAGE size boundary, then the revised size is not seen by the firmware on Guest reboot. The is because in the virt_acpi_build_update() -> acpi_ram_update() -> qemu_ram_resize() path, qemu_ram_resize() uses ram_block size which is aligned to PAGE size and the "resize callback" to update the size seen by firmware is not getting invoked. Hence align ACPI blob sizes to PAGE boundary. Signed-off-by: Shameer Kolothum --- More details on this issue can be found here, https://patchwork.kernel.org/patch/11154757/ --- hw/arm/virt-acpi-build.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.17.1 diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 4cd50175e0..074e0c858e 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -790,6 +790,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) GArray *table_offsets; unsigned dsdt, xsdt; GArray *tables_blob = tables->table_data; + GArray *cmd_blob = tables->linker->cmd_blob; MachineState *ms = MACHINE(vms); table_offsets = g_array_new(false, true /* clear */, @@ -854,6 +855,19 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) build_rsdp(tables->rsdp, tables->linker, &rsdp_data); } + /* + * Align the ACPI blob lengths to PAGE size so that on ACPI table + * regeneration, the length that firmware sees really gets updated + * through 'resize' callback in qemu_ram_resize() in the + * virt_acpi_build_update() -> acpi_ram_update() -> qemu_ram_resize() + * path. + */ + g_array_set_size(tables_blob, + TARGET_PAGE_ALIGN(acpi_data_len(tables_blob))); + g_array_set_size(tables->rsdp, + TARGET_PAGE_ALIGN(acpi_data_len(tables->rsdp))); + g_array_set_size(cmd_blob, + TARGET_PAGE_ALIGN(acpi_data_len(cmd_blob))); /* Cleanup memory that's no longer used. */ g_array_free(table_offsets, true); } From patchwork Fri Oct 4 15:52:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 175238 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp909064ill; Fri, 4 Oct 2019 09:11:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqzjKvKUtwqTmCLVrhJ8ltEss/svcOdrA0EjuO4dgQHAJKPndtTZd9nG+xYUfk5H+WApGtX+ X-Received: by 2002:ac8:724d:: with SMTP id l13mr16859998qtp.381.1570205513054; Fri, 04 Oct 2019 09:11:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570205513; cv=none; d=google.com; s=arc-20160816; b=CH0xxsF2+SFSUOiYHW2wx3o8HY3p+se7ysFA4LfOsIBk3vJ7jcnc7hwpfdgBBMgWt0 22ZZOu6cXCOOU0k3or+ltjGfVndKUOhXUl0Ezn44YgPF8Jc2jRMcCrv8YUE/IfohUKql WjBRqYRwf4TD0X8PUuEQFOeTzlLj5GMCu1EtIYBgYiyXfV4mIWZ7RXqH5yx2mdxtmMkx QpV7+4Zt340vPne0TG+zUAeBylqZsFeMykSxoeR7JAXPUBzIMUwo5Of403Nth0yHZLzg +SUflxlib5opqNc6RpqN6GztGnvhBHQBE/coGAe0MMz8FPYaYzmD/BEtNH2nCkXmRQE2 FUkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version:references :in-reply-to:message-id:date:subject:to:from; bh=KIEyf/R457NMzfLU3J09H2kufqg7IvgFwl1u5n+FEDA=; b=KqCexr+nnDwyrCznXllTNH5dvTuMj/Cgv+yYcSw7H14REVeYyOUtUjXTa51UFy2vho SKSC5UgeAsEEgUHUYOOJVhgWD9bN02f9rda609EuuidjLkYiktTaDpxf2iNcc2jk2RuO oQGuQL1KDIg6zZHcDsFA1pP9RIzyVXWLNKGgps/GQx5katQq0LfiqKvM/VdXUi2SFmiU 0uHzG3Q582fd1JcM5KUr1dXb+Ir9NuMd4GdYoDJKhsNbuHNDNgCvz6IWOitV5JS1af0q 28FjzUSFG/qlbLgGRrGWJJka4hltEUYZPt35PVUvPkCQ8eQzgomaoSdKAhANj6ddbGf2 NwLA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x8si5250494qtq.112.2019.10.04.09.11.52 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 04 Oct 2019 09:11:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:50114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iGQBL-00080e-Ne for patch@linaro.org; Fri, 04 Oct 2019 12:11:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42294) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iGPuc-0006MM-C3 for qemu-devel@nongnu.org; Fri, 04 Oct 2019 11:54:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iGPua-0000dL-AD for qemu-devel@nongnu.org; Fri, 04 Oct 2019 11:54:34 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:44630 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iGPuO-0000QM-94; Fri, 04 Oct 2019 11:54:21 -0400 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id B36C77D93F924710ECAC; Fri, 4 Oct 2019 23:54:12 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Fri, 4 Oct 2019 23:54:05 +0800 From: Shameer Kolothum To: , , , Subject: [PATCH 2/5] nvdimm: Use configurable ACPI IO base and size Date: Fri, 4 Oct 2019 16:52:59 +0100 Message-ID: <20191004155302.4632-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20191004155302.4632-1-shameerali.kolothum.thodi@huawei.com> References: <20191004155302.4632-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, lersek@redhat.com, linuxarm@huawei.com, xuwei5@hisilicon.com, shannon.zhaosl@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Kwangwoo Lee This patch makes IO base and size configurable to create NPIO AML for ACPI NFIT. Since a different architecture like AArch64 does not use port-mapped IO, a configurable IO base is required to create correct mapping of ACPI IO address and size. Signed-off-by: Kwangwoo Lee Signed-off-by: Eric Auger Signed-off-by: Shameer Kolothum --- hw/acpi/nvdimm.c | 32 ++++++++++++++++++++++---------- hw/i386/acpi-build.c | 6 ++++++ hw/i386/acpi-build.h | 3 +++ hw/i386/pc_piix.c | 2 ++ hw/i386/pc_q35.c | 2 ++ include/hw/mem/nvdimm.h | 3 +++ 6 files changed, 38 insertions(+), 10 deletions(-) -- 2.17.1 diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index 9fdad6dc3f..f91eea3802 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -926,11 +926,13 @@ void nvdimm_acpi_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev) } void nvdimm_init_acpi_state(NVDIMMState *state, MemoryRegion *io, + struct AcpiGenericAddress dsm_io, FWCfgState *fw_cfg, Object *owner) { + state->dsm_io = dsm_io; memory_region_init_io(&state->io_mr, owner, &nvdimm_dsm_ops, state, - "nvdimm-acpi-io", NVDIMM_ACPI_IO_LEN); - memory_region_add_subregion(io, NVDIMM_ACPI_IO_BASE, &state->io_mr); + "nvdimm-acpi-io", dsm_io.bit_width >> 3); + memory_region_add_subregion(io, dsm_io.address, &state->io_mr); state->dsm_mem = g_array_new(false, true /* clear */, 1); acpi_data_push(state->dsm_mem, sizeof(NvdimmDsmIn)); @@ -959,12 +961,14 @@ void nvdimm_init_acpi_state(NVDIMMState *state, MemoryRegion *io, #define NVDIMM_QEMU_RSVD_UUID "648B9CF2-CDA1-4312-8AD9-49C4AF32BD62" -static void nvdimm_build_common_dsm(Aml *dev) +static void nvdimm_build_common_dsm(Aml *dev, + NVDIMMState *nvdimm_state) { Aml *method, *ifctx, *function, *handle, *uuid, *dsm_mem, *elsectx2; Aml *elsectx, *unsupport, *unpatched, *expected_uuid, *uuid_invalid; Aml *pckg, *pckg_index, *pckg_buf, *field, *dsm_out_buf, *dsm_out_buf_size; uint8_t byte_list[1]; + AmlRegionSpace rs; method = aml_method(NVDIMM_COMMON_DSM, 5, AML_SERIALIZED); uuid = aml_arg(0); @@ -975,9 +979,16 @@ static void nvdimm_build_common_dsm(Aml *dev) aml_append(method, aml_store(aml_name(NVDIMM_ACPI_MEM_ADDR), dsm_mem)); + if (nvdimm_state->dsm_io.space_id == AML_AS_SYSTEM_IO) { + rs = AML_SYSTEM_IO; + } else { + rs = AML_SYSTEM_MEMORY; + } + /* map DSM memory and IO into ACPI namespace. */ - aml_append(method, aml_operation_region(NVDIMM_DSM_IOPORT, AML_SYSTEM_IO, - aml_int(NVDIMM_ACPI_IO_BASE), NVDIMM_ACPI_IO_LEN)); + aml_append(method, aml_operation_region(NVDIMM_DSM_IOPORT, rs, + aml_int(nvdimm_state->dsm_io.address), + nvdimm_state->dsm_io.bit_width >> 3)); aml_append(method, aml_operation_region(NVDIMM_DSM_MEMORY, AML_SYSTEM_MEMORY, dsm_mem, sizeof(NvdimmDsmIn))); @@ -992,7 +1003,7 @@ static void nvdimm_build_common_dsm(Aml *dev) field = aml_field(NVDIMM_DSM_IOPORT, AML_DWORD_ACC, AML_NOLOCK, AML_PRESERVE); aml_append(field, aml_named_field(NVDIMM_DSM_NOTIFY, - NVDIMM_ACPI_IO_LEN * BITS_PER_BYTE)); + (nvdimm_state->dsm_io.bit_width >> 3) * BITS_PER_BYTE)); aml_append(method, field); /* @@ -1260,7 +1271,8 @@ static void nvdimm_build_nvdimm_devices(Aml *root_dev, uint32_t ram_slots) } static void nvdimm_build_ssdt(GArray *table_offsets, GArray *table_data, - BIOSLinker *linker, GArray *dsm_dma_area, + BIOSLinker *linker, + NVDIMMState *nvdimm_state, uint32_t ram_slots) { Aml *ssdt, *sb_scope, *dev; @@ -1288,7 +1300,7 @@ static void nvdimm_build_ssdt(GArray *table_offsets, GArray *table_data, */ aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0012"))); - nvdimm_build_common_dsm(dev); + nvdimm_build_common_dsm(dev, nvdimm_state); /* 0 is reserved for root device. */ nvdimm_build_device_dsm(dev, 0); @@ -1307,7 +1319,7 @@ static void nvdimm_build_ssdt(GArray *table_offsets, GArray *table_data, NVDIMM_ACPI_MEM_ADDR); bios_linker_loader_alloc(linker, - NVDIMM_DSM_MEM_FILE, dsm_dma_area, + NVDIMM_DSM_MEM_FILE, nvdimm_state->dsm_mem, sizeof(NvdimmDsmIn), false /* high memory */); bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, mem_addr_offset, sizeof(uint32_t), @@ -1329,7 +1341,7 @@ void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data, return; } - nvdimm_build_ssdt(table_offsets, table_data, linker, state->dsm_mem, + nvdimm_build_ssdt(table_offsets, table_data, linker, state, ram_slots); device_list = nvdimm_get_device_list(); diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 1d077a7cb7..b5170912a8 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -126,6 +126,12 @@ typedef struct FwCfgTPMConfig { static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg); +const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { + .space_id = AML_AS_SYSTEM_IO, + .address = NVDIMM_ACPI_IO_BASE, + .bit_width = NVDIMM_ACPI_IO_LEN << 3 +}; + static void init_common_fadt_data(MachineState *ms, Object *o, AcpiFadtData *data) { diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h index 007332e51c..74df5fc612 100644 --- a/hw/i386/acpi-build.h +++ b/hw/i386/acpi-build.h @@ -1,6 +1,9 @@ #ifndef HW_I386_ACPI_BUILD_H #define HW_I386_ACPI_BUILD_H +#include "hw/acpi/acpi-defs.h" + +extern const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio; void acpi_setup(void); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 6824b72124..78521cf017 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -58,6 +58,7 @@ #include "migration/misc.h" #include "kvm_i386.h" #include "sysemu/numa.h" +#include "hw/i386/acpi-build.h" #define MAX_IDE_BUS 2 @@ -303,6 +304,7 @@ else { if (machine->nvdimms_state->is_enabled) { nvdimm_init_acpi_state(machine->nvdimms_state, system_io, + x86_nvdimm_acpi_dsmio, pcms->fw_cfg, OBJECT(pcms)); } } diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 8fad20f314..d53ee8de84 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -53,6 +53,7 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/numa.h" +#include "hw/i386/acpi-build.h" /* ICH9 AHCI has 6 ports */ #define MAX_SATA_PORTS 6 @@ -330,6 +331,7 @@ static void pc_q35_init(MachineState *machine) if (machine->nvdimms_state->is_enabled) { nvdimm_init_acpi_state(machine->nvdimms_state, system_io, + x86_nvdimm_acpi_dsmio, pcms->fw_cfg, OBJECT(pcms)); } } diff --git a/include/hw/mem/nvdimm.h b/include/hw/mem/nvdimm.h index 523a9b3d4a..5fe440861e 100644 --- a/include/hw/mem/nvdimm.h +++ b/include/hw/mem/nvdimm.h @@ -25,6 +25,7 @@ #include "hw/mem/pc-dimm.h" #include "hw/acpi/bios-linker-loader.h" +#include "hw/acpi/aml-build.h" #define NVDIMM_DEBUG 0 #define nvdimm_debug(fmt, ...) \ @@ -140,10 +141,12 @@ struct NVDIMMState { */ int32_t persistence; char *persistence_string; + struct AcpiGenericAddress dsm_io; }; typedef struct NVDIMMState NVDIMMState; void nvdimm_init_acpi_state(NVDIMMState *state, MemoryRegion *io, + struct AcpiGenericAddress dsm_io, FWCfgState *fw_cfg, Object *owner); void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data, BIOSLinker *linker, NVDIMMState *state, From patchwork Fri Oct 4 15:53:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 175236 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp904362ill; Fri, 4 Oct 2019 09:08:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqyKBK2sqKGzi1ZmS+3frYidp1pZqm4TFnLkYkPJCQNgdyzd0Lvnquf+u9yq/WxhfX50LP4F X-Received: by 2002:aed:30aa:: with SMTP id 39mr17007934qtf.9.1570205308740; Fri, 04 Oct 2019 09:08:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570205308; cv=none; d=google.com; s=arc-20160816; b=E3ohPXEmLnrhXsLZsl1jv+VnpQKljgieJYQXegIVD1m0Zr6UFToOyHMSrg+oZnGuzi zWMjYaGluDbWxt4jdtiMsLSTwSlblxihcyul28lu3OvNJrrvABGJ0Sc+I5HzrbTpRWZe vIpapam15VjxIyWxNkozlHGcuFoFeVIolGc7rDo023xQju8KF/kNI+9vPcgEYxvFqifJ GJWlkMNTYNVvomsMlKy+uFjJokB+e6eA/65J6MJ2vuoSObJXpChuEd+a3shQJufacyhX eTpCINNoeg2yOi1p60X+rZfoSGYygdg9lBUbGDh0E2UB1BvBE6eGQadyh01sy+jgNO+s mmKQ== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id z25si5853699qkj.297.2019.10.04.09.08.28 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 04 Oct 2019 09:08:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:50096 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iGQ82-00053V-FI for patch@linaro.org; Fri, 04 Oct 2019 12:08:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42293) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iGPuc-0006MI-C6 for qemu-devel@nongnu.org; Fri, 04 Oct 2019 11:54:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iGPuZ-0000ck-C0 for qemu-devel@nongnu.org; Fri, 04 Oct 2019 11:54:34 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2244 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iGPuP-0000Un-QR; Fri, 04 Oct 2019 11:54:22 -0400 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id C259B1E99BED508086FD; Fri, 4 Oct 2019 23:54:17 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Fri, 4 Oct 2019 23:54:08 +0800 From: Shameer Kolothum To: , , , Subject: [PATCH 3/5] hw/arm/virt: Add nvdimm hot-plug infrastructure Date: Fri, 4 Oct 2019 16:53:00 +0100 Message-ID: <20191004155302.4632-4-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20191004155302.4632-1-shameerali.kolothum.thodi@huawei.com> References: <20191004155302.4632-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, lersek@redhat.com, linuxarm@huawei.com, xuwei5@hisilicon.com, shannon.zhaosl@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Kwangwoo Lee Pre-plug and plug handlers are prepared for NVDIMM support. Please note nvdimm_support is not yet enabled. Signed-off-by: Eric Auger Signed-off-by: Kwangwoo Lee Signed-off-by: Shameer Kolothum --- hw/arm/Kconfig | 1 + hw/arm/virt-acpi-build.c | 6 ++++++ hw/arm/virt.c | 22 +++++++++++++++++++++- hw/mem/Kconfig | 2 +- include/hw/arm/virt.h | 1 + 5 files changed, 30 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index c6e7782580..851dd81289 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -24,6 +24,7 @@ config ARM_VIRT select DIMM select ACPI_MEMORY_HOTPLUG select ACPI_HW_REDUCED + select ACPI_NVDIMM config CHEETAH bool diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 074e0c858e..4e63f5da48 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -44,6 +44,7 @@ #include "hw/pci/pcie_host.h" #include "hw/pci/pci.h" #include "hw/arm/virt.h" +#include "hw/mem/nvdimm.h" #include "sysemu/numa.h" #include "sysemu/reset.h" #include "kvm_arm.h" @@ -835,6 +836,11 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) } } + if (ms->nvdimms_state->is_enabled) { + nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, + ms->nvdimms_state, ms->ram_slots); + } + if (its_class_name() && !vmc->no_its) { acpi_add_table(table_offsets, tables_blob); build_iort(tables_blob, tables->linker, vms); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d4bedc2607..30bc8a7803 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -143,6 +143,7 @@ static const MemMapEntry base_memmap[] = { [VIRT_SMMU] = { 0x09050000, 0x00020000 }, [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, + [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, @@ -1750,6 +1751,18 @@ static void machvirt_init(MachineState *machine) create_platform_bus(vms, pic); + if (machine->nvdimms_state->is_enabled) { + const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { + .space_id = AML_AS_SYSTEM_MEMORY, + .address = vms->memmap[VIRT_NVDIMM_ACPI].base, + .bit_width = NVDIMM_ACPI_IO_LEN << 3 + }; + + nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, + arm_virt_nvdimm_acpi_dsmio, + vms->fw_cfg, OBJECT(vms)); + } + vms->bootinfo.ram_size = machine->ram_size; vms->bootinfo.nb_cpus = smp_cpus; vms->bootinfo.board_id = -1; @@ -1916,9 +1929,10 @@ static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) { VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); + MachineState *ms = MACHINE(hotplug_dev); const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); - if (is_nvdimm) { + if (is_nvdimm && (!ms->nvdimms_state->is_enabled)) { error_setg(errp, "nvdimm is not yet supported"); return; } @@ -1937,6 +1951,8 @@ static void virt_memory_plug(HotplugHandler *hotplug_dev, { HotplugHandlerClass *hhc; VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); + MachineState *ms = MACHINE(hotplug_dev); + bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); Error *local_err = NULL; pc_dimm_plug(PC_DIMM(dev), MACHINE(vms), &local_err); @@ -1944,6 +1960,10 @@ static void virt_memory_plug(HotplugHandler *hotplug_dev, goto out; } + if (is_nvdimm) { + nvdimm_plug(ms->nvdimms_state); + } + hhc = HOTPLUG_HANDLER_GET_CLASS(vms->acpi_dev); hhc->plug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &error_abort); out: diff --git a/hw/mem/Kconfig b/hw/mem/Kconfig index 620fd4cb59..0d5f8f321a 100644 --- a/hw/mem/Kconfig +++ b/hw/mem/Kconfig @@ -8,4 +8,4 @@ config MEM_DEVICE config NVDIMM bool default y - depends on PC + depends on PC || ARM_VIRT diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 0b41083e9d..06d5e75611 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -79,6 +79,7 @@ enum { VIRT_SECURE_MEM, VIRT_PCDIMM_ACPI, VIRT_ACPI_GED, + VIRT_NVDIMM_ACPI, VIRT_LOWMEMMAP_LAST, }; From patchwork Fri Oct 4 15:53:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 175239 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp909537ill; Fri, 4 Oct 2019 09:12:14 -0700 (PDT) X-Google-Smtp-Source: APXvYqxfzygf+Zn92wb/5cSlPTiIj6vLrzFXMCYvIpPoq2x6oBf0QT0cqz/RAEz7lx2T+Xj+sMMx X-Received: by 2002:ac8:3644:: with SMTP id n4mr16248815qtb.92.1570205534149; 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[209.51.188.17]) by mx.google.com with ESMTPS id w3si6039838qvl.29.2019.10.04.09.12.14 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 04 Oct 2019 09:12:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:50136 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iGQBg-0001SE-OD for patch@linaro.org; Fri, 04 Oct 2019 12:12:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42291) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iGPuc-0006MH-CB for qemu-devel@nongnu.org; Fri, 04 Oct 2019 11:54:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iGPuZ-0000cl-Bv for qemu-devel@nongnu.org; Fri, 04 Oct 2019 11:54:34 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2245 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iGPuP-0000Uo-Pn; Fri, 04 Oct 2019 11:54:22 -0400 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id C8CD5155CB26E3B1BFA7; Fri, 4 Oct 2019 23:54:17 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Fri, 4 Oct 2019 23:54:11 +0800 From: Shameer Kolothum To: , , , Subject: [PATCH 4/5] hw/arm/boot: Expose the pmem nodes in the DT Date: Fri, 4 Oct 2019 16:53:01 +0100 Message-ID: <20191004155302.4632-5-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20191004155302.4632-1-shameerali.kolothum.thodi@huawei.com> References: <20191004155302.4632-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, lersek@redhat.com, linuxarm@huawei.com, xuwei5@hisilicon.com, shannon.zhaosl@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger In case of NV-DIMM slots, let's add /pmem DT nodes. Signed-off-by: Eric Auger Signed-off-by: Shameer Kolothum --- hw/arm/boot.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) -- 2.17.1 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index c264864c11..bd6d72b33e 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -20,6 +20,7 @@ #include "hw/boards.h" #include "sysemu/reset.h" #include "hw/loader.h" +#include "hw/mem/memory-device.h" #include "elf.h" #include "sysemu/device_tree.h" #include "qemu/config-file.h" @@ -523,6 +524,44 @@ static void fdt_add_psci_node(void *fdt) qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); } +static int fdt_add_pmem_node(void *fdt, uint32_t acells, uint32_t scells) +{ + MemoryDeviceInfoList *info, *info_list = qmp_memory_device_list(); + MemoryDeviceInfo *mi; + int ret; + + for (info = info_list; info != NULL; info = info->next) { + mi = info->value; + + if (mi->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) { + PCDIMMDeviceInfo *di = mi->u.nvdimm.data; + char *nodename; + + nodename = g_strdup_printf("/pmem@%" PRIx64, di->addr); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "pmem-region"); + ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, + di->addr, scells, di->size); + /* only set the NUMA ID if it is specified */ + if (!ret && di->node >= 0) { + ret = qemu_fdt_setprop_cell(fdt, nodename, "numa-node-id", + di->node); + } + + g_free(nodename); + + if (ret < 0) { + fprintf(stderr, "couldn't add NVDIMM /memory@%"PRIx64" node\n", + di->addr); + goto out; + } + } + } +out: + qapi_free_MemoryDeviceInfoList(info_list); + return ret; +} + int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, hwaddr addr_limit, AddressSpace *as, MachineState *ms) { @@ -622,6 +661,12 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, } } + rc = fdt_add_pmem_node(fdt, acells, scells); + if (rc < 0) { + fprintf(stderr, "couldn't add pmem memory nodes\n"); + goto fail; + } + rc = fdt_path_offset(fdt, "/chosen"); if (rc < 0) { qemu_fdt_add_subnode(fdt, "/chosen"); From patchwork Fri Oct 4 15:53:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 175237 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp905589ill; Fri, 4 Oct 2019 09:09:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqyVaZGFfEQEyH2OJN6i4A/qqneLFoW7KkJ+ArU/Jmsp0iaNdIIZtwz/XDyE+J1HuHoLZhKj X-Received: by 2002:aa7:dd11:: with SMTP id i17mr16479912edv.147.1570205362190; Fri, 04 Oct 2019 09:09:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570205362; cv=none; d=google.com; s=arc-20160816; b=Yj8MmJTCf5LNkZ7z7zxTRT4YvQMRC71LFFagRzuOLm674ZIPKd2WsmmGeLnSAbKZse K9sGNjWx4JqAfHB2T8faIQpu2D3B+kXgLAx0CBoN52RF8+SazyMybnQ7FMyPPx3HAqSI z9PvThusqvJxy4KMhiooXmnQaZyHN4zLZ9NtxY5tXQv6NKgqpALnYTl5QtS5Z5ItIGkx IEY192gp4ZOdT1lnaSyEBy2Lv8dsGz9uO+nuTXeMPPBapB7RAVHr1mcMdmJSA/MDPs8q UPNGwCV+PV3FBqt5L6srYoDsC1WLU4ZefbUzZDM+gYOHZeoSSknjOuk1naEUFD8srVZ4 Alyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version:references :in-reply-to:message-id:date:subject:to:from; bh=QIeaf2KKxKy3+uiwxAPUjJoc6ZRrwX01qOPMG1NRRJk=; b=wW9ECCW/TIJZ67arrStB6jRUBOgacFWen3Cz0qqYOIO6bV+ILzVd8Di3uDB7cYmOnu LRYZ1qFDCkWzfk78jkEeW8cUfhiJjjVk8xarYIj+Ta64ycLXJtlPkGFVbs12GUYwV0eO /UbvMgooZgmTThffM8MQXQsHKrZ+o+yGFLXNl9Njnm/OI8hNsbH10FvEBwh1jO5SCEz6 ANGh67Xxm2/8TqjfyAXSGX8RHgQxlKvnXTyxMNNIlDOmgRRpHbDtJez5/JMa/EQwkNT3 g4F5POIpViqm048Wk5v7WfTnK4VBZCUIFyIxEx2ovqZ2Rc2+xQJm1zYdbitVfBElbB81 Jifw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w10si3111549eju.156.2019.10.04.09.09.21 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 04 Oct 2019 09:09:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:50110 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iGQ8u-0007VD-PM for patch@linaro.org; Fri, 04 Oct 2019 12:09:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42328) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iGPuf-0006N3-60 for qemu-devel@nongnu.org; Fri, 04 Oct 2019 11:54:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iGPud-0000f7-TQ for qemu-devel@nongnu.org; Fri, 04 Oct 2019 11:54:37 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:50966 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iGPuU-0000XK-GF; Fri, 04 Oct 2019 11:54:26 -0400 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id D6CA060ED9B3CA423F9F; Fri, 4 Oct 2019 23:54:22 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Fri, 4 Oct 2019 23:54:13 +0800 From: Shameer Kolothum To: , , , Subject: [PATCH 5/5] hw/arm/virt: Add nvdimm hotplug support Date: Fri, 4 Oct 2019 16:53:02 +0100 Message-ID: <20191004155302.4632-6-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20191004155302.4632-1-shameerali.kolothum.thodi@huawei.com> References: <20191004155302.4632-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, lersek@redhat.com, linuxarm@huawei.com, xuwei5@hisilicon.com, shannon.zhaosl@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This adds support for nvdimm hotplug events through GED and enables nvdimm for the arm/virt. Now Guests with DT boot can have nvdimm cold plug and with ACPI both cold/hot plug. Hot removal functionality is not yet supported. Signed-off-by: Shameer Kolothum --- docs/specs/acpi_hw_reduced_hotplug.rst | 1 + hw/acpi/generic_event_device.c | 13 +++++++++++++ hw/arm/virt.c | 20 +++++++++++++++----- include/hw/acpi/generic_event_device.h | 1 + 4 files changed, 30 insertions(+), 5 deletions(-) -- 2.17.1 Reviewed-by: Igor Mammedov diff --git a/docs/specs/acpi_hw_reduced_hotplug.rst b/docs/specs/acpi_hw_reduced_hotplug.rst index 911a98255b..e3abe975bf 100644 --- a/docs/specs/acpi_hw_reduced_hotplug.rst +++ b/docs/specs/acpi_hw_reduced_hotplug.rst @@ -63,6 +63,7 @@ GED IO interface (4 byte access) bits: 0: Memory hotplug event 1: System power down event + 2: NVDIMM hotplug event 2-31: Reserved **write_access:** diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index 9cee90cc70..ad1b684304 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -16,6 +16,7 @@ #include "hw/acpi/generic_event_device.h" #include "hw/irq.h" #include "hw/mem/pc-dimm.h" +#include "hw/mem/nvdimm.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "qemu/error-report.h" @@ -23,6 +24,7 @@ static const uint32_t ged_supported_events[] = { ACPI_GED_MEM_HOTPLUG_EVT, ACPI_GED_PWR_DOWN_EVT, + ACPI_GED_NVDIMM_HOTPLUG_EVT, }; /* @@ -110,6 +112,11 @@ void build_ged_aml(Aml *table, const char *name, HotplugHandler *hotplug_dev, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), aml_int(0x80))); break; + case ACPI_GED_NVDIMM_HOTPLUG_EVT: + aml_append(if_ctx, + aml_notify(aml_name("\\_SB.NVDR"), + aml_int(0x80))); + break; default: /* * Please make sure all the events in ged_supported_events[] @@ -175,7 +182,11 @@ static void acpi_ged_device_plug_cb(HotplugHandler *hotplug_dev, AcpiGedState *s = ACPI_GED(hotplug_dev); if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { + if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { + nvdimm_acpi_plug_cb(hotplug_dev, dev); + } else { acpi_memory_plug_cb(hotplug_dev, &s->memhp_state, dev, errp); + } } else { error_setg(errp, "virt: device plug request for unsupported device" " type: %s", object_get_typename(OBJECT(dev))); @@ -192,6 +203,8 @@ static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev) sel = ACPI_GED_MEM_HOTPLUG_EVT; } else if (ev & ACPI_POWER_DOWN_STATUS) { sel = ACPI_GED_PWR_DOWN_EVT; + } else if (ev & ACPI_NVDIMM_HOTPLUG_STATUS) { + sel = ACPI_GED_NVDIMM_HOTPLUG_EVT; } else { /* Unknown event. Return without generating interrupt. */ warn_report("GED: Unsupported event %d. No irq injected", ev); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 30bc8a7803..acdcba9638 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -543,6 +543,10 @@ static inline DeviceState *create_acpi_ged(VirtMachineState *vms, qemu_irq *pic) event |= ACPI_GED_MEM_HOTPLUG_EVT; } + if (ms->nvdimms_state->is_enabled) { + event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; + } + dev = qdev_create(NULL, TYPE_ACPI_GED); qdev_prop_set_uint32(dev, "ged-event", event); @@ -1938,9 +1942,12 @@ static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, } if (!vms->acpi_dev) { - error_setg(errp, - "memory hotplug is not enabled: missing acpi-ged device"); - return; + /* Allow nvdimm DT or cold plug */ + if (!(is_nvdimm && !dev->hotplugged)) { + error_setg(errp, + "memory hotplug is not enabled: missing acpi-ged device"); + return; + } } pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); @@ -1964,8 +1971,10 @@ static void virt_memory_plug(HotplugHandler *hotplug_dev, nvdimm_plug(ms->nvdimms_state); } - hhc = HOTPLUG_HANDLER_GET_CLASS(vms->acpi_dev); - hhc->plug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &error_abort); + if (vms->acpi_dev) { + hhc = HOTPLUG_HANDLER_GET_CLASS(vms->acpi_dev); + hhc->plug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &error_abort); + } out: error_propagate(errp, local_err); } @@ -2073,6 +2082,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) hc->plug = virt_machine_device_plug_cb; hc->unplug_request = virt_machine_device_unplug_request_cb; mc->numa_mem_supported = true; + mc->nvdimm_supported = true; mc->auto_enable_numa_with_memhp = true; } diff --git a/include/hw/acpi/generic_event_device.h b/include/hw/acpi/generic_event_device.h index d157eac088..9eb86ca4fd 100644 --- a/include/hw/acpi/generic_event_device.h +++ b/include/hw/acpi/generic_event_device.h @@ -82,6 +82,7 @@ */ #define ACPI_GED_MEM_HOTPLUG_EVT 0x1 #define ACPI_GED_PWR_DOWN_EVT 0x2 +#define ACPI_GED_NVDIMM_HOTPLUG_EVT 0x4 typedef struct GEDState { MemoryRegion io;