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[98.197.58.203]) by smtp.gmail.com with ESMTPSA id ld22-20020a0568702b1600b0022e8f9fa89bsm75622oab.57.2024.04.02.12.25.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Apr 2024 12:25:58 -0700 (PDT) From: Alexandru Gagniuc To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: ansuelsmth@gmail.com, robimarko@gmail.com, Alexandru Gagniuc , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/7] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 Date: Tue, 2 Apr 2024 14:25:49 -0500 Message-Id: <20240402192555.1955204-1-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.40.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add defines for the missing PCIe PIPE clocks. Signed-off-by: Alexandru Gagniuc --- include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index 08fd3a37acaa..52123c5a09fa 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -216,4 +216,8 @@ #define GCC_CRYPTO_AHB_CLK 207 #define GCC_USB0_PIPE_CLK 208 #define GCC_USB0_SLEEP_CLK 209 +#define GCC_PCIE0_PIPE_CLK 210 +#define GCC_PCIE1_PIPE_CLK 211 +#define GCC_PCIE2_PIPE_CLK 212 +#define GCC_PCIE3_PIPE_CLK 213 #endif From patchwork Tue Apr 2 19:25:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Gagniuc X-Patchwork-Id: 785196 Received: from mail-oa1-f41.google.com (mail-oa1-f41.google.com [209.85.160.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32BF115CD56; Tue, 2 Apr 2024 19:26:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712085966; cv=none; b=SEu12x4IkgTcaIWNLyo6NyodxTGXDS0mNt00oaARjYCfaXQQF8Jur8P3THTjHNZMXtvIaw6pw28TdFodyJlQJKlUW2IH48pu52OyKEAajMAo8FW+7Z+euVFj7T84CjxbfLtCZuzhbJWGb7+6ZFlpHYmThB8kitz4LA14gCVcpAc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712085966; c=relaxed/simple; bh=Y3sQe52k1yICnNk6VsdMH27lecC3GY2DlpewVQmBUI0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=KfJOjZ7ew6uC6EON7yevdJCEP2dAhtOC3hZFwEHRZMTevSqnGizaGTVpQGLzJh63gz65h2J2h3Xxm8b47q4/QJhYbYVqh8W2dkKXBn13ejmVKFqddIbX+JePDTTvgKSrU7do3vggDDvdgqwwjzvDT5V7iOSBrmwUjZcdXJ7ngW4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Tr18FGWj; arc=none smtp.client-ip=209.85.160.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Tr18FGWj" Received: by mail-oa1-f41.google.com with SMTP id 586e51a60fabf-221a9e5484aso3768413fac.0; Tue, 02 Apr 2024 12:26:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1712085964; x=1712690764; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u509fpdTL3x8h0sKnxRrMd2Q/Sm/IRVlvPpLmK46sCY=; b=Tr18FGWjEOEZS6x+L5oiytweebci5kfquabcQS/5Lrl7kK8s8OHbQ/5p6XFor88Tzv u/JLvY//oCZ0uASc7bSdWzf76QIx8gxlEO67r/bJGOWpDNOu3d1p91sSYW3KtZCobnVC 7RqtPOd2wGMJy960XutmRNy7ak4aIH5U6w1K5JpCQacU4rpxX1TIdYdijYd/qbEh0h0z prZ/2JTqF3kXlB/iyzTZxlQtPYJ+rWybzNMKUeUQmcbd0TYVyXmbb5sZfDMngcdiqbp0 9YS9u0QUTaT6/RRlYM+Z7cCP+GHAK0pZTrDugX0hGe/atdJb9lQbNaWdPuaAw63VPuEb wNVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712085964; x=1712690764; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u509fpdTL3x8h0sKnxRrMd2Q/Sm/IRVlvPpLmK46sCY=; b=hOe41AOo16w79Z+TVYhR2XPvVRyXb7jsiV5NaZB8bjtJED/g7/jx1dqPY5xg4xzQ7Q rzuB2pFw8WrkBhISEOIrknkPcWXIvbPZ39WyydaWZUFZyeOzNSlacpAN5LoZ39Iyp4AL 7WO4rtV2OZHoGKZtOIGYsyKWH9COHPkGmzlYjS6O9XWl+e3ZfXNTwnsGM5AEOUqZp4bH Os7ucodUp8r29lFRnHGTE8Moi0qhNjpFaJLJJRetMTJ0OO/5riK+82Z4+9tKsE4kaLhP 4tV/Py9Ni16q3Er/oaWUVDmJxJTTd+uBBsGgvhrUsWWTh8nThi44l7o4zGRnsPRuK6Ao n9WQ== X-Forwarded-Encrypted: i=1; AJvYcCUiGy/KRyylaooJEc7OXAPzNQKSdf7PHSZ3/ds8NGIQOIiC/baamZl4K0dJ202JCjgZqyOn9LD8L6tonU8JOxhf8cZMfDuED2ax4EEznOJZOL5PM3U8eKbsmDU2x37J/tvp1hz3l0GS8lCy2qO14RoDTxNMYlLhgNCvh5HQS1Psn2gFxQGISA== X-Gm-Message-State: AOJu0Yz5WdmPEYMXXS9ZhFjCYqoS6LI4gyfZslgPN/77C46sk9tWGAut 1azDgCgnXYrlT+hWhzh2L0EBHyIelmqcBKgJslpp+41tz9NLuJRo X-Google-Smtp-Source: AGHT+IGXiX0R+pjBUbuLZzc0JHffXaS4BXKCPOLEoUc822a2Ltjo0ljUMsaoACrgDM5sNkY1dTpe7w== X-Received: by 2002:a05:6871:1d5:b0:22e:7de8:c745 with SMTP id q21-20020a05687101d500b0022e7de8c745mr791919oad.56.1712085964262; Tue, 02 Apr 2024 12:26:04 -0700 (PDT) Received: from nukework.lan (c-98-197-58-203.hsd1.tx.comcast.net. [98.197.58.203]) by smtp.gmail.com with ESMTPSA id ld22-20020a0568702b1600b0022e8f9fa89bsm75622oab.57.2024.04.02.12.26.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Apr 2024 12:26:03 -0700 (PDT) From: Alexandru Gagniuc To: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Cc: ansuelsmth@gmail.com, robimarko@gmail.com, Alexandru Gagniuc , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/7] PCI: qcom: Add support for IPQ9574 Date: Tue, 2 Apr 2024 14:25:52 -0500 Message-Id: <20240402192555.1955204-4-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240402192555.1955204-1-mr.nuke.me@gmail.com> References: <20240402192555.1955204-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for the PCIe on IPQ9574. The main difference from ipq6018 is that the "iface" clock is not necessarry. Add a special case in qcom_pcie_get_resources_2_9_0() to handle this. Signed-off-by: Alexandru Gagniuc --- drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 14772edcf0d3..10560d6d6336 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1101,15 +1101,19 @@ static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; - int ret; + int ret, num_clks = ARRAY_SIZE(res->clks) - 1; - res->clks[0].id = "iface"; + res->clks[0].id = "rchng"; res->clks[1].id = "axi_m"; res->clks[2].id = "axi_s"; res->clks[3].id = "axi_bridge"; - res->clks[4].id = "rchng"; - ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + if (!of_device_is_compatible(dev->of_node, "qcom,pcie-ipq9574")) { + res->clks[4].id = "iface"; + num_clks++; + } + + ret = devm_clk_bulk_get(dev, num_clks, res->clks); if (ret < 0) return ret; @@ -1664,6 +1668,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 }, { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 }, + { .compatible = "qcom,pcie-ipq9574", .data = &cfg_2_9_0 }, { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp }, From patchwork Tue Apr 2 19:25:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Gagniuc X-Patchwork-Id: 785195 Received: from mail-oa1-f53.google.com (mail-oa1-f53.google.com [209.85.160.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B52CA15CD62; Tue, 2 Apr 2024 19:26:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[98.197.58.203]) by smtp.gmail.com with ESMTPSA id ld22-20020a0568702b1600b0022e8f9fa89bsm75622oab.57.2024.04.02.12.26.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Apr 2024 12:26:05 -0700 (PDT) From: Alexandru Gagniuc To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: ansuelsmth@gmail.com, robimarko@gmail.com, Alexandru Gagniuc , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY Date: Tue, 2 Apr 2024 14:25:53 -0500 Message-Id: <20240402192555.1955204-5-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240402192555.1955204-1-mr.nuke.me@gmail.com> References: <20240402192555.1955204-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The IPQ9574 gen3x2 PHY is very similar to IPQ6018. It requires two extra clocks named "anoc" and "snoc". Document this, and add a new compatible string for this PHY. Signed-off-by: Alexandru Gagniuc --- .../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 47 +++++++++++++++++-- 1 file changed, 42 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml index 634cec5d57ea..b0dbd2726acd 100644 --- a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml @@ -19,19 +19,19 @@ properties: - qcom,ipq6018-qmp-pcie-phy - qcom,ipq8074-qmp-gen3-pcie-phy - qcom,ipq8074-qmp-pcie-phy + - qcom,ipq9574-qmp-gen3x2-pcie-phy reg: items: - description: serdes clocks: - maxItems: 3 + minItems: 3 + maxItems: 5 clock-names: - items: - - const: aux - - const: cfg_ahb - - const: pipe + minItems: 3 + maxItems: 5 resets: maxItems: 2 @@ -61,6 +61,43 @@ required: - clock-output-names - "#phy-cells" +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq6018-qmp-pcie-phy + - qcom,ipq8074-qmp-gen3-pcie-phy + - qcom,ipq8074-qmp-pcie-phy + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: pipe + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq9574-qmp-gen3x2-pcie-phy + then: + properties: + clocks: + maxItems: 5 + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: pipe + - const: anoc + - const: snoc + additionalProperties: false examples: From patchwork Tue Apr 2 19:25:55 2024 Content-Type: text/plain; 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[98.197.58.203]) by smtp.gmail.com with ESMTPSA id ld22-20020a0568702b1600b0022e8f9fa89bsm75622oab.57.2024.04.02.12.26.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Apr 2024 12:26:08 -0700 (PDT) From: Alexandru Gagniuc To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: ansuelsmth@gmail.com, robimarko@gmail.com, Alexandru Gagniuc , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] arm64: dts: qcom: ipq9574: add PCIe2 nodes Date: Tue, 2 Apr 2024 14:25:55 -0500 Message-Id: <20240402192555.1955204-7-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240402192555.1955204-1-mr.nuke.me@gmail.com> References: <20240402192555.1955204-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On ipq9574, there are 4 PCIe controllers. Describe the pcie2 node, and its PHY in devicetree. Only pcie2 is described, because only hardware using that controller was available for testing. Signed-off-by: Alexandru Gagniuc --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 93 ++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 7f2e5cbf3bbb..626d6359d750 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -300,7 +300,7 @@ gcc: clock-controller@1800000 { <0>, <0>, <0>, - <0>, + <&pcie2_qmp_phy>, <0>, <0>; #clock-cells = <1>; @@ -745,6 +745,97 @@ frame@b128000 { status = "disabled"; }; }; + + pcie2_qmp_phy: phy@8c000 { + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; + reg = <0x0008c000 0x14f4>; + + clocks = <&gcc GCC_PCIE2_AUX_CLK>, + <&gcc GCC_PCIE2_AHB_CLK>, + <&gcc GCC_PCIE2_PIPE_CLK>, + <&gcc GCC_ANOC_PCIE2_2LANE_M_CLK>, + <&gcc GCC_SNOC_PCIE2_2LANE_S_CLK>; + clock-names = "aux", + "cfg_ahb", + "pipe", + "anoc", + "snoc"; + + clock-output-names = "pcie_phy2_pipe_clk"; + #clock-cells = <0>; + #phy-cells = <0>; + + resets = <&gcc GCC_PCIE2_PHY_BCR>, + <&gcc GCC_PCIE2PHY_PHY_BCR>; + reset-names = "phy", + "common"; + status = "disabled"; + }; + + pcie2: pcie@20000000 { + compatible = "qcom,pcie-ipq9574"; + reg = <0x20000000 0xf1d>, + <0x20000f20 0xa8>, + <0x20001000 0x1000>, + <0x00088000 0x4000>, + <0x20100000 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <3>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + max-link-speed = <3>; + #address-cells = <3>; + #size-cells = <2>; + + phys = <&pcie2_qmp_phy>; + phy-names = "pciephy"; + + ranges = <0x81000000 0x0 0x20200000 0x20200000 0x0 0x00100000>, /* I/O */ + <0x82000000 0x0 0x20300000 0x20300000 0x0 0x07d00000>; /* MEM */ + + interrupts = ; + interrupt-names = "msi"; + msi-parent = <&v2m0>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 164 + IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 165 + IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 186 + IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 187 + IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE2_AXI_M_CLK>, + <&gcc GCC_PCIE2_AXI_S_CLK>, + <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE2_RCHNG_CLK>; + clock-names = "axi_m", + "axi_s", + "axi_bridge", + "rchng"; + + resets = <&gcc GCC_PCIE2_PIPE_ARES>, + <&gcc GCC_PCIE2_CORE_STICKY_ARES>, + <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE2_AXI_S_ARES>, + <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE2_AXI_M_ARES>, + <&gcc GCC_PCIE2_AUX_ARES>, + <&gcc GCC_PCIE2_AHB_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + status = "disabled"; + }; }; thermal-zones {