From patchwork Sat Apr 6 01:04:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 786797 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 618261FDA; Sat, 6 Apr 2024 00:58:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712365096; cv=none; b=mU32/180Hs9iA7aVHqXGjhyM8CCnZkUizHNVabvSqyEf0BTL/fD57pnxfU4GSoxjAGNV9mG9IvtaPGn892XVJsY6/7fs06fYbgwTLWFs2vU87lRM/J062WywnR38os3ixpySr26NLRk3nk2iOJitQBR9fbMsl/BiL/XXSyE3sV4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712365096; c=relaxed/simple; bh=M2NpUF0GpEYkCm0hpvAgVNS5+2TcRpN8c57fAIjoOvc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=umtZtv9iSwTTMaTZEosxrdlCW+S//Ma+eRYtAH+jxEJ/vpAWUaaCAvXSjRWmC3NjLKdkCKLnLtrLzxr66J2uDqMxTE2UsLZC10WlfwZpDth3P2WMnO8z0Cv4rPRq3oChPLsNo3Omha9J3t7BSVa49orFsaeEazti+pQ6gbS3GFU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dB4PADLG; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dB4PADLG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712365093; x=1743901093; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=M2NpUF0GpEYkCm0hpvAgVNS5+2TcRpN8c57fAIjoOvc=; b=dB4PADLGl5ewOfk+9gA7SZFsOBn7QVyyqUxq2X4HcTbhyRBHg7X6jm5v kBOgoenZEdy0SuGQuCG/eo4SGOEOTg/PEgY3r4z02tlgCPx1yFfdVOTZ4 7VIBauvjrbHXy034/xJoLR/UnDeVhttQjubU8N3EaZlJ8nk7IDOmDZUjQ lVIp/4YF6G7H7tjByw16JzN+hxv3wBUuLrDF/9TXdrwFaJ+iOrEhsFLnz iDq2eblumvZHaLcB/JmnMACCJ/L/nvftpj3t8GQFVnk6KPz3w/GI+9RWs tsWbKEIawD3C+Si205pn2DpRS5O3sxo24uCK10YXPs/HNuSSVoMzIlDdD w==; X-CSE-ConnectionGUID: znTeJ8cWSHasj041cU1b5A== X-CSE-MsgGUID: PUbXdbdIQoS73QY4TQ8DEg== X-IronPort-AV: E=McAfee;i="6600,9927,11035"; a="25153873" X-IronPort-AV: E=Sophos;i="6.07,182,1708416000"; d="scan'208";a="25153873" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Apr 2024 17:58:11 -0700 X-CSE-ConnectionGUID: uC34GYp+QSCYAP2KhqIrcA== X-CSE-MsgGUID: 3mzLzgSMQuiqh+5MUcc3NQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,182,1708416000"; d="scan'208";a="19252363" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orviesa009.jf.intel.com with ESMTP; 05 Apr 2024 17:58:11 -0700 From: Ricardo Neri To: "Rafael J. Wysocki" , Zhang Rui , Jean Delvare , Guenter Roeck Cc: Srinivas Pandruvada , Lukasz Luba , Daniel Lezcano , linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH 1/3] thermal: intel: intel_tcc: Add model checks for temperature registers Date: Fri, 5 Apr 2024 18:04:14 -0700 Message-Id: <20240406010416.4821-2-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240406010416.4821-1-ricardo.neri-calderon@linux.intel.com> References: <20240406010416.4821-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The register MSR_TEMPERATURE_TARGET is not architectural. Its fields may be defined differently for each processor model. TCC_OFFSET is an example of such case. Despite being specified as architectural, the registers IA32_[PACKAGE]_ THERM_STATUS have become model-specific: in recent processors, the digital temperature readout uses bits [23:16] whereas the Intel Software Developer's manual specifies bits [22:16]. Create an array of processor models and their bitmasks for TCC_OFFSET and the digital temperature readout fields. Do not include recent processors. Instead, use the bitmasks of these recent processors as default. Use these model-specific bitmasks when reading TCC_OFFSET or the temperature sensors. Initialize a model-specific data structure during subsys_initcall() to have it ready when thermal drivers are loaded. Expose the new interfaces get_tcc_offset_mask() and intel_tcc_get_temp_mask(). The hwmon/coretemp and the intel_tcc_cooling drivers need to use model-specific bitmasks. Include stubs that reflect minimum support for !CONFIG_INTEL_TCC. Signed-off-by: Ricardo Neri --- Cc: Daniel Lezcano Cc: Lukasz Luba Cc: Srinivas Pandruvada Cc: linux-hwmon@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org # v6.7+ --- drivers/thermal/intel/intel_tcc.c | 177 +++++++++++++++++++++++++++++- include/linux/intel_tcc.h | 8 ++ 2 files changed, 180 insertions(+), 5 deletions(-) diff --git a/drivers/thermal/intel/intel_tcc.c b/drivers/thermal/intel/intel_tcc.c index 5e8b7f34b395..1f595f174ab0 100644 --- a/drivers/thermal/intel/intel_tcc.c +++ b/drivers/thermal/intel/intel_tcc.c @@ -6,8 +6,170 @@ #include #include +#include +#include #include +/** + * struct temp_masks - Bitmasks for temperature readings + * @tcc_offset: TCC offset in MSR_TEMPERATURE_TARGET + * @digital_readout: Digital readout in MSR_IA32_THERM_STATUS + * @pkg_digital_readout: Digital readout in MSR_IA32_PACKAGE_THERM_STATUS + * + * Bitmasks to extract the fields of the MSR_TEMPERATURE and IA32_[PACKAGE]_ + * THERM_STATUS registers for different processor models. + * + * The bitmask of TjMax is not included in this structure. It is always 0xff. + */ +struct temp_masks { + u32 tcc_offset; + u32 digital_readout; + u32 pkg_digital_readout; +}; + +#define TCC_FAM6_MODEL_TEMP_MASKS(model, _tcc_offset, _digital_readout, \ + _pkg_digital_readout) \ + static const struct temp_masks temp_##model __initconst = { \ + .tcc_offset = _tcc_offset, \ + .digital_readout = _digital_readout, \ + .pkg_digital_readout = _pkg_digital_readout \ + } + +TCC_FAM6_MODEL_TEMP_MASKS(nehalem, 0, 0x7f, 0x7f); +TCC_FAM6_MODEL_TEMP_MASKS(haswell_x, 0xf, 0x7f, 0x7f); +TCC_FAM6_MODEL_TEMP_MASKS(broadwell, 0x3f, 0x7f, 0x7f); +TCC_FAM6_MODEL_TEMP_MASKS(goldmont, 0x7f, 0x7f, 0x7f); +TCC_FAM6_MODEL_TEMP_MASKS(tigerlake, 0x3f, 0xff, 0xff); +TCC_FAM6_MODEL_TEMP_MASKS(sapphirerapids, 0x3f, 0x7f, 0xff); + +/* Use these masks for processors not included in @tcc_cpu_ids. */ +static struct temp_masks intel_tcc_temp_masks __ro_after_init = { + .tcc_offset = 0x7f, + .digital_readout = 0xff, + .pkg_digital_readout = 0xff, +}; + +static const struct x86_cpu_id intel_tcc_cpu_ids[] __initconst = { + X86_MATCH_INTEL_FAM6_MODEL(CORE_YONAH, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(CORE2_MEROM, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(CORE2_MEROM_L, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(CORE2_PENRYN, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(CORE2_DUNNINGTON, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(NEHALEM, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_G, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EX, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(WESTMERE, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EP, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EX, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &temp_haswell_x), + X86_MATCH_INTEL_FAM6_MODEL(HASWELL, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &temp_haswell_x), + X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(BROADWELL, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &temp_haswell_x), + X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &temp_haswell_x), + X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &temp_haswell_x), + X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_NNPI, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &temp_tigerlake), + X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &temp_tigerlake), + X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &temp_sapphirerapids), + X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X, &temp_sapphirerapids), + X86_MATCH_INTEL_FAM6_MODEL(LAKEFIELD, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &temp_tigerlake), + X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &temp_tigerlake), + X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &temp_tigerlake), + X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, &temp_tigerlake), + X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, &temp_tigerlake), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL_MID, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL_MID, &temp_nehalem), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT_MID, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT_NP, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &temp_goldmont), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &temp_goldmont), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &temp_goldmont), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, &temp_tigerlake), + X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &temp_broadwell), + X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &temp_broadwell), + {} +}; + +static int __init intel_tcc_init(void) +{ + const struct x86_cpu_id *id; + + id = x86_match_cpu(intel_tcc_cpu_ids); + if (id) + memcpy(&intel_tcc_temp_masks, (const void *)id->driver_data, + sizeof(intel_tcc_temp_masks)); + + return 0; +} +/* + * Use subsys_initcall to ensure temperature bitmasks are initialized before + * the drivers that use this library. + */ +subsys_initcall(intel_tcc_init); + +/** + * get_tcc_offset_mask() - Returns the model-specific bitmask for TCC offset + * + * Get the model-specific bitmask to extract TCC_OFFSET from the MSR_TEMPERATURE_ + * TARGET register. If the mask is 0, it means the processor does not support TCC offset. + * + * Return: The model-specific bitmask for TCC offset. + */ +u32 get_tcc_offset_mask(void) +{ + return intel_tcc_temp_masks.tcc_offset; +} +EXPORT_SYMBOL_NS(get_tcc_offset_mask, INTEL_TCC); + +/** + * intel_tcc_get_temp_mask() - Returns the model-specific bitmask for temperature + * + * @pkg: true: Package Thermal Sensor. false: Core Thermal Sensor. + * + * Get the model-specific bitmask to extract the temperature reading from the + * MSR_IA32_[PACKAGE]_THERM_STATUS register. + * + * Callers must check if the thermal status registers are supported. + * + * Return: The model-specific bitmask for temperature reading + */ +u32 intel_tcc_get_temp_mask(bool pkg) +{ + return pkg ? intel_tcc_temp_masks.pkg_digital_readout : + intel_tcc_temp_masks.digital_readout; +} +EXPORT_SYMBOL_NS(intel_tcc_get_temp_mask, INTEL_TCC); + /** * intel_tcc_get_tjmax() - returns the default TCC activation Temperature * @cpu: cpu that the MSR should be run on, nagative value means any cpu. @@ -56,7 +218,7 @@ int intel_tcc_get_offset(int cpu) if (err) return err; - return (low >> 24) & 0x3f; + return (low >> 24) & intel_tcc_temp_masks.tcc_offset; } EXPORT_SYMBOL_NS_GPL(intel_tcc_get_offset, INTEL_TCC); @@ -76,7 +238,10 @@ int intel_tcc_set_offset(int cpu, int offset) u32 low, high; int err; - if (offset < 0 || offset > 0x3f) + if (!intel_tcc_temp_masks.tcc_offset) + return -ENODEV; + + if (offset < 0 || offset > intel_tcc_temp_masks.tcc_offset) return -EINVAL; if (cpu < 0) @@ -90,7 +255,7 @@ int intel_tcc_set_offset(int cpu, int offset) if (low & BIT(31)) return -EPERM; - low &= ~(0x3f << 24); + low &= ~(intel_tcc_temp_masks.tcc_offset << 24); low |= offset << 24; if (cpu < 0) @@ -113,8 +278,8 @@ EXPORT_SYMBOL_NS_GPL(intel_tcc_set_offset, INTEL_TCC); */ int intel_tcc_get_temp(int cpu, int *temp, bool pkg) { - u32 low, high; u32 msr = pkg ? MSR_IA32_PACKAGE_THERM_STATUS : MSR_IA32_THERM_STATUS; + u32 low, high, mask; int tjmax, err; tjmax = intel_tcc_get_tjmax(cpu); @@ -132,7 +297,9 @@ int intel_tcc_get_temp(int cpu, int *temp, bool pkg) if (!(low & BIT(31))) return -ENODATA; - *temp = tjmax - ((low >> 16) & 0x7f); + mask = intel_tcc_get_temp_mask(pkg); + + *temp = tjmax - ((low >> 16) & mask); return 0; } diff --git a/include/linux/intel_tcc.h b/include/linux/intel_tcc.h index 8ff8eabb4a98..e281cf06aeab 100644 --- a/include/linux/intel_tcc.h +++ b/include/linux/intel_tcc.h @@ -14,5 +14,13 @@ int intel_tcc_get_tjmax(int cpu); int intel_tcc_get_offset(int cpu); int intel_tcc_set_offset(int cpu, int offset); int intel_tcc_get_temp(int cpu, int *temp, bool pkg); +#ifdef CONFIG_INTEL_TCC +u32 get_tcc_offset_mask(void); +u32 intel_tcc_get_temp_mask(bool pkg); +#else +static inline u32 get_tcc_offset_mask(void) { return 0; } +/* Use the architectural bitmask of the temperature readout. No model checks. */ +static inline u32 intel_tcc_get_temp_mask(bool pkg) { return 0x7f; } +#endif #endif /* __INTEL_TCC_H__ */ From patchwork Sat Apr 6 01:04:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 786657 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D80C65695; Sat, 6 Apr 2024 00:58:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712365095; cv=none; b=Ka7WXxIiZ45k8wSo//RlNFOxdew6cGJjyNgnqOKkO1kCb3PVReA1JSkgE7dbL9iMImVludMHpntNs/0vJ6VQmi5/h52rC4QnqysyU/yujLt9Ni8QC9UH4ZAEbYA/Lf0AuolekLy7fogHYwwWl/NMyoRMYvp1CuQbG+N3dA5VDXg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712365095; c=relaxed/simple; bh=KCAYWXnfTfIof0z3ccXzlxFYy3XY+yZ85HhlAqLhXHc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=DtuFOrWCltaBL8uBraJov0nAUeSZYrHDdsYQeS7rYugJ8kMTJlSk8gTy7QQad2yxgrieuKiY6h1H6gQF5UasJRKETkBCcPqLqeswR075qkbey5Jq9aVy0XamZczxtqDdceP+o0wCf2/9ekuNepWEWTvWIwiXNFdPWlKtV047u30= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=UpX3lwKI; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="UpX3lwKI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712365094; x=1743901094; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=KCAYWXnfTfIof0z3ccXzlxFYy3XY+yZ85HhlAqLhXHc=; b=UpX3lwKIJZMqQu7GEcSBxmHMuP9BMorZ9xz0pcBY+260V3q4uJMYhajt xaGkS+ebEViei+JzNYmCrUYMIo07Dem5OjvRINz7NMxuGKYIiMHi8gHUv S3oXusRjrKK7HxB+rqLfTcJn+bqZyOT2DKMLTYa972fHSr8gZj2rjwISG gq1u/KK0RFsUIzXWL9t2uYyurbFZmvyFZj4GrOUW/mjxmjUojjGNX6o/+ M22CqUCxPKuLR1W96ksjhDekh8mUj9LWSN5Nl9DyJqUY1pI/2FHZwENaL d9lVIW7fjmjEAvGvsFOfCCZZdDUYNCYVdMWSZObzyQiSm4R56Kja0DiGT g==; X-CSE-ConnectionGUID: T8cX7N7wTJexSsaZYiaR8g== X-CSE-MsgGUID: zP9PIpUyS66hufb1wHwokQ== X-IronPort-AV: E=McAfee;i="6600,9927,11035"; a="25153878" X-IronPort-AV: E=Sophos;i="6.07,182,1708416000"; d="scan'208";a="25153878" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Apr 2024 17:58:12 -0700 X-CSE-ConnectionGUID: 7oUEoezVS+uoDoEUGK9v7w== X-CSE-MsgGUID: LIl4jerqRay0FJkOJbMslQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,182,1708416000"; d="scan'208";a="19252366" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orviesa009.jf.intel.com with ESMTP; 05 Apr 2024 17:58:12 -0700 From: Ricardo Neri To: "Rafael J. Wysocki" , Zhang Rui , Jean Delvare , Guenter Roeck Cc: Srinivas Pandruvada , Lukasz Luba , Daniel Lezcano , linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH 2/3] thermal: intel: intel_tcc_cooling: Use a model-specific bitmask for TCC offset Date: Fri, 5 Apr 2024 18:04:15 -0700 Message-Id: <20240406010416.4821-3-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240406010416.4821-1-ricardo.neri-calderon@linux.intel.com> References: <20240406010416.4821-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The TCC offset field in the register MSR_TEMPERATURE_TARGET is not architectural. The TCC library provides a model-specific bitmask. Use it to determine the maximum TCC offset. Suggested-by: Zhang Rui Signed-off-by: Ricardo Neri --- Cc: Daniel Lezcano Cc: Lukasz Luba Cc: Srinivas Pandruvada Cc: linux-hwmon@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org # v6.7+ --- drivers/thermal/intel/intel_tcc_cooling.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/intel/intel_tcc_cooling.c b/drivers/thermal/intel/intel_tcc_cooling.c index 6c392147e6d1..308946853cdd 100644 --- a/drivers/thermal/intel/intel_tcc_cooling.c +++ b/drivers/thermal/intel/intel_tcc_cooling.c @@ -20,7 +20,7 @@ static struct thermal_cooling_device *tcc_cdev; static int tcc_get_max_state(struct thermal_cooling_device *cdev, unsigned long *state) { - *state = 0x3f; + *state = get_tcc_offset_mask(); return 0; } From patchwork Sat Apr 6 01:04:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 786656 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 997F8EEB3; Sat, 6 Apr 2024 00:58:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712365097; cv=none; b=rXmNcE/SWbdeX81V+qJ754O4cYsWCRLLszTUj6V8x91lqmGm8hwPSM0yzbhgj01IjdwhLECQ0ouVA/HGyJQilaE2IVqAqnzP606Y4x5WGNLizeeFLNUmYw6w/pYc1/HfJ5yvIp/S7dpEX+75xzTbRqwomaM2XJ2/5Apeh3m0fhE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712365097; c=relaxed/simple; bh=LvJf7IpSrSk0ODEovUEZymwOVnvp4IWE/x7bmgvJpPE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=U+fOkC29Vuns77v3UKs5A1flwKDO/R451LNe1iPUmY5ZmkTB4oPXd+GwmC+1j9FRurTmRIi6UNZuhrjHjxM2SqjbeoANxeigV6aqXnKgosyHcxA6MVybIvNHp7bGihVaejROyUNmsVDy0iG7U8ntPiKUAe7joG0Wf6UB9XXVulI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=K1yIZBdG; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="K1yIZBdG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712365096; x=1743901096; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=LvJf7IpSrSk0ODEovUEZymwOVnvp4IWE/x7bmgvJpPE=; b=K1yIZBdG+7sjaUxlEtCVrl/Jd9PdI9efY/1LbaDTQ28msICnTRK9I3S3 wkE8P1uXl8h/xtSg00C8u9h75ff/cIrczBa7bE3AIYEuza5iblNGHaVQM Cr6atgtxrWYPt8ceGjebeUgLVEEvkC4O93hj2VKEHQfkVfMwO0TFIEwQS w3TwPvGKm9YankUjsoRJhtWJbidjiaQ6HgWOC5IZMcPTV3GrPsgVOkUyr DCRIlEu1B7Ci7pOJ8Hhdgu8T6z5RXSdoUz6ipl4b1YSx6TJvUbgenSC6g cfsKneobfK/2NYLhkFSZvjMg8ka2pBhqAzJBPuGXR3eZRnMgpuO/NynFx w==; X-CSE-ConnectionGUID: /9cJtAYFSG+8mHGkSNXjRA== X-CSE-MsgGUID: m7LQNKegR8aYfHo8NTTxVQ== X-IronPort-AV: E=McAfee;i="6600,9927,11035"; a="25153884" X-IronPort-AV: E=Sophos;i="6.07,182,1708416000"; d="scan'208";a="25153884" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Apr 2024 17:58:12 -0700 X-CSE-ConnectionGUID: pysUpNznTUKUAfBlXx2RyQ== X-CSE-MsgGUID: xTKN75TDQoyumuzIHGfrAg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,182,1708416000"; d="scan'208";a="19252369" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orviesa009.jf.intel.com with ESMTP; 05 Apr 2024 17:58:12 -0700 From: Ricardo Neri To: "Rafael J. Wysocki" , Zhang Rui , Jean Delvare , Guenter Roeck Cc: Srinivas Pandruvada , Lukasz Luba , Daniel Lezcano , linux-pm@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH 3/3] hwmon: (coretemp) Use a model-specific bitmask to read registers Date: Fri, 5 Apr 2024 18:04:16 -0700 Message-Id: <20240406010416.4821-4-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240406010416.4821-1-ricardo.neri-calderon@linux.intel.com> References: <20240406010416.4821-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The Intel Software Development manual defines states the temperature digital readout as the bits [22:16] of the IA32_[PACKAGE]_THERM_STATUS registers. In recent processor, however, the range is [23:16]. Use a model-specific bitmask to extract the temperature readout correctly. Instead of re-implementing model checks, extract the correct bitmask using the intel_tcc library. Add an 'imply' weak reverse dependency on CONFIG_INTEL_TCC. This captures the dependency and lets user to unselect them if they are so inclined. In such case, the bitmask used for the digital readout is [22:16] as specified in the Intel Software Developer's manual. Signed-off-by: Ricardo Neri --- Cc: Daniel Lezcano Cc: Lukasz Luba Cc: Srinivas Pandruvada Cc: linux-hwmon@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org # v6.7+ --- drivers/hwmon/Kconfig | 1 + drivers/hwmon/coretemp.c | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 83945397b6eb..11d72b3009bf 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -847,6 +847,7 @@ config SENSORS_I5500 config SENSORS_CORETEMP tristate "Intel Core/Core2/Atom temperature sensor" depends on X86 + imply INTEL_TCC help If you say yes here you get support for the temperature sensor inside your CPU. Most of the family 6 CPUs diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c index 616bd1a5b864..5632e1b1dfb1 100644 --- a/drivers/hwmon/coretemp.c +++ b/drivers/hwmon/coretemp.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -404,6 +405,8 @@ static ssize_t show_temp(struct device *dev, tjmax = get_tjmax(tdata, dev); /* Check whether the time interval has elapsed */ if (time_after(jiffies, tdata->last_updated + HZ)) { + u32 mask = intel_tcc_get_temp_mask(is_pkg_temp_data(tdata)); + rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx); /* * Ignore the valid bit. In all observed cases the register @@ -411,7 +414,7 @@ static ssize_t show_temp(struct device *dev, * Return it instead of reporting an error which doesn't * really help at all. */ - tdata->temp = tjmax - ((eax >> 16) & 0x7f) * 1000; + tdata->temp = tjmax - ((eax >> 16) & mask) * 1000; tdata->last_updated = jiffies; } @@ -838,4 +841,5 @@ module_exit(coretemp_exit) MODULE_AUTHOR("Rudolf Marek "); MODULE_DESCRIPTION("Intel Core temperature monitor"); +MODULE_IMPORT_NS(INTEL_TCC); MODULE_LICENSE("GPL");