From patchwork Tue Apr 9 19:08:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Gagniuc X-Patchwork-Id: 787270 Received: from mail-ot1-f45.google.com (mail-ot1-f45.google.com [209.85.210.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4EAB15623E; Tue, 9 Apr 2024 19:08:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712689722; cv=none; b=fV1Z9qr0wf1as18hJJ1d6y3p2779EQLkOdeSFgKoQkcSoDZyI5z/ewBrp4sBZz/1ADdILd0ZZFr20KVpPQLEswM53bOFfwuaD4SRwrvPYzwBhY7K+EAcis3HNFCv0PX5ADh7QHZgvUnxh27QmnKPE9en3hEmfrg5h9+hpbTk37A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712689722; c=relaxed/simple; bh=/LW5UP24d3M9gnDJHKsZY3AjzrEnrgPIA21IZxGWV+o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aMLNv3WVgqa4wVvq7RRdLbZSsUz2DVBNQABxsWeIXjRxZvOh7ooFKlsMnMFOKQcO1D7MTq74W2GDzhaBXnV9fSGQzTKpXByMCgh6xKqel1z1qSLpJJ+BMCKL4KUiuS0+vY1gugSWfamtM41A4Ey02xvIZKuBdGfF9/+NgFEGq1c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=jzFWE3te; arc=none smtp.client-ip=209.85.210.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jzFWE3te" Received: by mail-ot1-f45.google.com with SMTP id 46e09a7af769-6ea1f98f3b9so901707a34.1; Tue, 09 Apr 2024 12:08:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1712689720; x=1713294520; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eQII4bd5vU3iEBUOJRNxIf3Y2tkmIxs3qzEGZCMfEv8=; b=jzFWE3teKpUJ5wl862mddPBr8HyYqumW7+TUQUfqgfnxAk0FERYfRgUpEAWQHmvX/Z b7hpQ/I8JQXrv15s7jgABYJRxwc2Sd+WEt/j2LYf3AJcywE/27N7Ny15ZdMHRN7ZS+TP HWquuz1a71ZoYYr5ZOvUrB0dT64q8mcypTeOEIU/eBE+SSr5o1qU5AmnSgT2r1mSFUqU zXVhtnEPoNCyDamZUWsf4Lt3IsHXmLYPMhlPk+vM3E4gMNaUM+3YOyCkypC3HY2jv/QW 3/tqQbea23nROABQX92mWZxcf8B5YZUgupXE6dG/B/NK1eONJB8GMq6jMBqNbA9w8jPp 3PZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712689720; x=1713294520; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eQII4bd5vU3iEBUOJRNxIf3Y2tkmIxs3qzEGZCMfEv8=; b=HVbsvJ2B6kp75tPCHe/4wbT3Vep3RgZBjb7w7lrXhpNG9OHEFUIdCGsSoOifbrxhsp H9KQm/y2yiWF4Xpi0G82a/gTjFIfY5lzh1j7ui44AUwWh+vk7aVFzkCqeds07fFwPtdK M+MymysjHrW2q2qk8UrUnncWtlpcmm6DCBnbmui20PeMx6HtCTsjJRi4UZWVU7QtqHTK Pgc3T/tRwjO48TRG5coYiN+nzzLXKwobBqRclElAZhqhPUD2lgvEvSkxrdHFL/0CfeyI 5760zsPTse+I85xjT666DrAndRyJlTIBDWTOKGYcu9ug30eeLFqnAQ7HLBDzK1o2FSFX Eo4w== X-Forwarded-Encrypted: i=1; AJvYcCXA6GcEZgJRq+8kri3Q7enlv3Vf6XBm30u2g5vibfywuGHzxN77XjBldnz6wUjwjPCIC2SURhHr2MpZM1CZK7/XgQWlhYePz4R+01mz05ATviKKej9mBSktlrXUGmUphuBm9SEkCXo3v/rQYtTU2reDTLw4C2m0jfkuEXgtJEdHNw4mZFjukeAcz77MOFJtxaQ5ssn4/g9Ob4GC6/PsahlsuTo= X-Gm-Message-State: AOJu0YzIppBYf8lImc4XE3JA78uNYmgIJu9YAeBAp5DzFbWNOMFA4Fhq mFwo32o+HGILauMCjsbAzQ/pRvjEfMayQzYVvWct72zGJxcP42vI X-Google-Smtp-Source: AGHT+IHnHq4Yzw2dp8mXx3ucVbabpjqSL5KTYckari/WPAcfuM42DCdJWg9oNA/1AS81eRtwKhtJBQ== X-Received: by 2002:a9d:748f:0:b0:6ea:109f:ea50 with SMTP id t15-20020a9d748f000000b006ea109fea50mr601491otk.15.1712689719902; Tue, 09 Apr 2024 12:08:39 -0700 (PDT) Received: from nukework.lan (c-98-197-58-203.hsd1.tx.comcast.net. [98.197.58.203]) by smtp.gmail.com with ESMTPSA id f11-20020a9d7b4b000000b006ea1cf91a8dsm674920oto.40.2024.04.09.12.08.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Apr 2024 12:08:39 -0700 (PDT) From: Alexandru Gagniuc To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Alexandru Gagniuc , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/7] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 Date: Tue, 9 Apr 2024 14:08:27 -0500 Message-Id: <20240409190833.3485824-2-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240409190833.3485824-1-mr.nuke.me@gmail.com> References: <20240409190833.3485824-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add defines for the missing PCIe PIPE clocks. Signed-off-by: Alexandru Gagniuc Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index 08fd3a37acaa..52123c5a09fa 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -216,4 +216,8 @@ #define GCC_CRYPTO_AHB_CLK 207 #define GCC_USB0_PIPE_CLK 208 #define GCC_USB0_SLEEP_CLK 209 +#define GCC_PCIE0_PIPE_CLK 210 +#define GCC_PCIE1_PIPE_CLK 211 +#define GCC_PCIE2_PIPE_CLK 212 +#define GCC_PCIE3_PIPE_CLK 213 #endif From patchwork Tue Apr 9 19:08:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Gagniuc X-Patchwork-Id: 787599 Received: from mail-ot1-f41.google.com (mail-ot1-f41.google.com [209.85.210.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DE24156F5D; Tue, 9 Apr 2024 19:08:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712689723; cv=none; b=GgpvSqxw1Qr0VaxVmffrMKOnB2LLixzwtZIvbyumnY9NoBspvss1giZrxBu+Hqp0tgA+on2oSHp63ScoOB3CyNFTAah877klgQWVe/MxTi001iyNO+myEePPG5zSpZouHnyPxnEmI3rIh9HH6bPDpPTWpakyeSBvE99VJPxAvUE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712689723; c=relaxed/simple; bh=2SGSOf9MraG0urfLafHVpTPVh0NeYydXJoNcIM3qPUk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HpBkZGwJfaVqy4RNlSAXhJ3h4+SJ94iaR2CzrdyKJ72jdFCC7EZQj51AjUzCOtTS+JlNnUVWCfCIhFI7Y+7fk17DCh/2Z86lYkx1avcvRKzjTFNzESWquOZzi/Jxx+Qfs/ih5JfdQcr4fcNVmRoZNbcCf+esQ3oXRpjEk+y2U+k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=drkuT0Hu; arc=none smtp.client-ip=209.85.210.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="drkuT0Hu" Received: by mail-ot1-f41.google.com with SMTP id 46e09a7af769-6ea15e25a06so1725809a34.0; Tue, 09 Apr 2024 12:08:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1712689721; x=1713294521; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HBuC8pqgFsd4wEiPMqmBqwIDKCnuRqVAfWjdldEDdmk=; b=drkuT0HuZ+8zVc3aK1nhWEMyEIpZNorsKISaCCwQvFNDL5xbJ2B+V+YCjHoiNDjkDS F+kuc63NsjC6JLhnr5HiF1f4uQXI8nWpURDG/sg+6Q+rUBMkwyx1iQvNJp2lFC/9UKA0 MU4GNgA6jx9PQgfgwun43E5J++WQ2p6BYV7D/vplrW0VrZMiUVlIYxz4g09DUNbvjVeq BxiK7Gd/xfERBFLMVp3nVBVh4MagbRqm2138DASxrEJ2F9q3tlYKwZHyn1jzW8PWfG7G d5zlDytNm+d4x290vU43kr8KaHbOJwv3XWhFmerbuq2J6XZRtjEqfbZ//6a+YL1TiGxK 8+Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712689721; x=1713294521; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HBuC8pqgFsd4wEiPMqmBqwIDKCnuRqVAfWjdldEDdmk=; b=t9imA0vnoOd9iSMhvxV4G5cnH1fd0KCA+eeQwvSwOIzkeqmXzVsF3ob9olX7Sy6XqE Wc4REbB7ZJbbJ740dapq855BLbRwk8whEpdB+BhFP3NQqlDiIkftBXQxQypAptUvx2G1 DiDZCqWXeSZ+61TvXSX8dz4Qg2oLnem4tTnB6NMMYIqaMGT81WjmOeh/Jgn+y35P4qaB oN5+ePxQ9SB4HhHgYSvFqWJQRxy6Gr1FikdWaGCCjPzuImPXhzE0dhQO3mTr7jd6xrYh DSLhTep+jPCLomHA0DlsnrkwmkPNA5Jxvet6AjGrPXdTqX0/+Az5Qz8p4ESRThgLxSfV aYjQ== X-Forwarded-Encrypted: i=1; AJvYcCXwJaXo1n1xYUDv2nJ82EJzGZ2AeDmUdW03yIMBqOVqxNwxEvR09Cb9TlUafXc8gR5fhd/HIIjIGTo4CXle56F6gVbc29eSkGhvp/Iq9jR69hPEfArJvTN6AQ2E9U9/5MG4cdiqmFq9rjtI7zVt6Db0oi61QwE9QraNJXNRiSUt3lqeePdXeQ== X-Gm-Message-State: AOJu0YxGOpHd3a1gp97XL7zTklWXT28nD7Q3hxsubs6ky0HvEvqcexKz ggoeLjuKYbaARSZkDO8MRt4ZvhACK9AcT4f6W40P4uIlw3/v+yoOmTRlrIP/JZOa5A== X-Google-Smtp-Source: AGHT+IHJ2x7wyJuwaDEleEnuz1j3q5JK70qW3MNUIhjGajZK7FoAI+SBypCk+J8RF2L4o0hdjBdftg== X-Received: by 2002:a9d:7f94:0:b0:6ea:767:9dc5 with SMTP id t20-20020a9d7f94000000b006ea07679dc5mr772361otp.3.1712689721325; Tue, 09 Apr 2024 12:08:41 -0700 (PDT) Received: from nukework.lan (c-98-197-58-203.hsd1.tx.comcast.net. [98.197.58.203]) by smtp.gmail.com with ESMTPSA id f11-20020a9d7b4b000000b006ea1cf91a8dsm674920oto.40.2024.04.09.12.08.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Apr 2024 12:08:40 -0700 (PDT) From: Alexandru Gagniuc To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: Alexandru Gagniuc , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/7] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks Date: Tue, 9 Apr 2024 14:08:28 -0500 Message-Id: <20240409190833.3485824-3-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240409190833.3485824-1-mr.nuke.me@gmail.com> References: <20240409190833.3485824-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The IPQ9574 has four PCIe "pipe" clocks. These clocks are required by PCIe PHYs. Port the pipe clocks from the downstream kernel. Signed-off-by: Alexandru Gagniuc Cc: Krzysztof Kozlowski --- drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 0a3f846695b8..c748d2f124f3 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -1569,6 +1569,24 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie0_pipe_clk = { + .halt_reg = 0x28044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x28044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie0_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie0_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { .reg = 0x29064, .clkr = { @@ -1583,6 +1601,24 @@ static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie1_pipe_clk = { + .halt_reg = 0x29044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x29044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie1_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie1_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_regmap_phy_mux pcie2_pipe_clk_src = { .reg = 0x2a064, .clkr = { @@ -1597,6 +1633,24 @@ static struct clk_regmap_phy_mux pcie2_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie2_pipe_clk = { + .halt_reg = 0x2a044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x2a044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_pcie2_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie2_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_regmap_phy_mux pcie3_pipe_clk_src = { .reg = 0x2b064, .clkr = { @@ -1611,6 +1665,24 @@ static struct clk_regmap_phy_mux pcie3_pipe_clk_src = { }, }; +static struct clk_branch gcc_pcie3_pipe_clk = { + .halt_reg = 0x2b044, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x2b044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "gcc_pcie3_pipe_clk", + .parent_hws = (const struct clk_hw *[]) { + &pcie3_pipe_clk_src.clkr.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = { F(24000000, P_XO, 1, 0, 0), F(100000000, P_GPLL0, 8, 0, 0), @@ -4141,6 +4213,10 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr, [GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr, [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr, + [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr, + [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, + [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, + [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, }; static const struct qcom_reset_map gcc_ipq9574_resets[] = { From patchwork Tue Apr 9 19:08:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Gagniuc X-Patchwork-Id: 787269 Received: from mail-ot1-f42.google.com (mail-ot1-f42.google.com [209.85.210.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1F1415748E; Tue, 9 Apr 2024 19:08:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712689725; cv=none; b=oxSsU1YiF5w/u4PjNWIIRtUsolZo7eGiVkbOZSjYGFoULECrN7XfzOa5ZABFV14CFux0anid7NEycWtbqO/nYU2dbYuOML8Jv+IELzZwyq++vLWn+wpIdekXwrO5XywGqLTY7pFcgoWIo2tB1AfVz30wvi7KaAx3N/MjMe11sNo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712689725; c=relaxed/simple; bh=qBEff6GBxK4EKDIooOGD6z891Ry9NSi5zZldTEdx4DQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PxQanvBjrUcm/a5IkePAOTKnaq15JzfNlZYlFEZCF0VPFfg/t6OIOp6j7NsMv/bnruVhYhYR6Fln6MJSxkNKtWhZ4rF7SMOGbf2Qd2dsjyIFy5c7zy+cGeEKpiiXBC2YB0fpDC6274S9Wz+qSVdL/TZ9nr7HeD1Zx3PnKylUi9M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Yekc9yEA; arc=none smtp.client-ip=209.85.210.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Yekc9yEA" Received: by mail-ot1-f42.google.com with SMTP id 46e09a7af769-6ea0fd9ca89so1729835a34.3; Tue, 09 Apr 2024 12:08:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1712689723; x=1713294523; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WAUXrnDjVNNhAghGFpeuevgQOeC52MpGlmfKhcik4y8=; b=Yekc9yEAN+kBtYicbuyOXz6xWb0EKQfontp8ogKUTQG+x5L3aGLhF/mnJUZrsriOzz 0rYIiBN36U4qFNggKhXs0Y8H7kXtx4ZeyxnIA1jmGkkBMypSg74qnyyqWjrUz1E1+bWm Y7vTY1SEjLhl1rfdRxEUXX99zCzwaWY+Mwwwcp0cR/QTvdnFGkP1/vXaKXYhyWgg+hcD cbbaKtFG+X4WZd4SoWU8ZsdatxSq/PdqtEEAqW5PjdXXnZe7NZdtd6+YVRiPyBFau98v xBNhaQm3XP2GD6CfMFwJyAnttXa41ZFNevMI9TSanEmfWTgtajjFdwerMNxeWxSzGKZw uDqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712689723; x=1713294523; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WAUXrnDjVNNhAghGFpeuevgQOeC52MpGlmfKhcik4y8=; b=fAe/ZioIjngEm4iIQkYlxjLH45HREyOfwRPD35HqRRps8U05Rc+Ey0eIMPnRXjLKQ8 9YBbyjKP/AkvO25Hmb73z/ZLoRF1xkqa+0LZt6Fc1jJhPSlHBFinGvWghWp/o95v/OY6 5vW8q3LijLlMGjMHiTp/zGGUwo9QxCod0+z1Qdka3vtNqlbg67DtiWVR82+iB7U7X43E H24JN4RkYw06K13MyFTo1J0o/SVJVPCqOuENekCcbqxzKaGTaEb+TkGYtCYwyR0xtw7m uUVkhc5Ulk+4zqeQWto1EiXbaOix/I0fd/ctga5meilnNs/JuJmIp7vIUuYISeoHE5dq 3plg== X-Forwarded-Encrypted: i=1; AJvYcCVgr9q2Cvu7TirNfBi3u/NMGQWEKfnupuAhm4QUMd6QK+AQvxVVcWcF3N2RY+V4Q8uPQYN8a4mTzZWbR7j6u+qjVmwDxeafdrWku0ZBkYuqjDWRov26UOoWKcIy+3/hT6ck4k7uU76CfM7R7CT4NC8g9q3fcqHbc7t309HGuC7zQt++r5xuD2ACtWrW2IPyRtsDnYfVhOYD1g07iS6v6uFdpjE= X-Gm-Message-State: AOJu0Yx3BBT0QMHtmg3fxbIkJSCCdwMaJ596VVBKyQ+a4biysOgI8tCE wxVsfS1wfIjBrsqpdXbOMGWQnv1Qer5/HgIT72vsigiHkXtzSHJj X-Google-Smtp-Source: AGHT+IEWoRotBhgk/BeM3JGvmJbd1EpaVpjJlGZOeL1cB+hdVgtvSIkdiMLKOpa2Odh8VxZIvZm9Tg== X-Received: by 2002:a05:6830:439f:b0:6ea:133f:b0 with SMTP id s31-20020a056830439f00b006ea133f00b0mr892709otv.33.1712689723084; Tue, 09 Apr 2024 12:08:43 -0700 (PDT) Received: from nukework.lan (c-98-197-58-203.hsd1.tx.comcast.net. [98.197.58.203]) by smtp.gmail.com with ESMTPSA id f11-20020a9d7b4b000000b006ea1cf91a8dsm674920oto.40.2024.04.09.12.08.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Apr 2024 12:08:42 -0700 (PDT) From: Alexandru Gagniuc To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam Cc: Alexandru Gagniuc , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/7] dt-bindings: PCI: qcom: Add IPQ9574 PCIe controller Date: Tue, 9 Apr 2024 14:08:29 -0500 Message-Id: <20240409190833.3485824-4-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240409190833.3485824-1-mr.nuke.me@gmail.com> References: <20240409190833.3485824-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 IPQ9574 has PCIe controllers which are almost identical to IPQ6018. The only difference is that the "iface" clock is not required. Document this difference along with the compatible string. Signed-off-by: Alexandru Gagniuc --- .../devicetree/bindings/pci/qcom,pcie.yaml | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index cf9a6910b542..1915bea580d3 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -26,6 +26,7 @@ properties: - qcom,pcie-ipq8064-v2 - qcom,pcie-ipq8074 - qcom,pcie-ipq8074-gen3 + - qcom,pcie-ipq9574 - qcom,pcie-msm8996 - qcom,pcie-qcs404 - qcom,pcie-sdm845 @@ -397,6 +398,37 @@ allOf: - const: axi_m_sticky # AXI Master Sticky reset - const: axi_s_sticky # AXI Slave Sticky reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq9574 + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: axi_m # AXI Master clock + - const: axi_s # AXI Slave clock + - const: axi_bridge # AXI bridge clock + - const: rchng + resets: + minItems: 8 + maxItems: 8 + reset-names: + items: + - const: pipe # PIPE reset + - const: sleep # Sleep reset + - const: sticky # Core Sticky reset + - const: axi_m # AXI Master reset + - const: axi_s # AXI Slave reset + - const: ahb # AHB Reset + - const: axi_m_sticky # AXI Master Sticky reset + - const: axi_s_sticky # AXI Slave Sticky reset + - if: properties: compatible: @@ -507,6 +539,7 @@ allOf: - qcom,pcie-ipq8064v2 - qcom,pcie-ipq8074 - qcom,pcie-ipq8074-gen3 + - qcom,pcie-ipq9574 - qcom,pcie-qcs404 then: required: @@ -566,6 +599,7 @@ allOf: - qcom,pcie-ipq8064-v2 - qcom,pcie-ipq8074 - qcom,pcie-ipq8074-gen3 + - qcom,pcie-ipq9574 - qcom,pcie-qcs404 then: properties: From patchwork Tue Apr 9 19:08:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Gagniuc X-Patchwork-Id: 787598 Received: from mail-oo1-f45.google.com (mail-oo1-f45.google.com [209.85.161.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7D99157A5F; Tue, 9 Apr 2024 19:08:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712689727; cv=none; b=uVGUegO8lIz+lgZEMOEANbAHxXFahwnLpL9MJKgK9N25hI+KCd3URb/86Q71VH84/PPPLELxmhsv/mmCqiupelZR1RgIt//0ye7why//jsOu/zmMu22nTwLNKbMW3BDeg4z39OFLVun+z+wLL1fRk73wgrsMYnpWB8H/iG6rfTA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712689727; c=relaxed/simple; bh=TF34Kiq3IULPX0vZLKg5UujAr20o/F0a7repIuGYPOs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BYcVFtCcUMUxTRJFAKjWls6GrSIAxcLpQc2/BKIwpEbvDKvQeJTErKUs+Ot7hlrLCPDRYluLL0j4a3pgN+dOyRkBytKoEPz+tF1j9gn/hdFZ2vNfqyIN3f8UKh1MpFYRkMHbH09+8+qogJGFe8ebC/vLeVJ4qZHQDS740w6zo2g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=EJm/ZN6l; arc=none smtp.client-ip=209.85.161.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EJm/ZN6l" Received: by mail-oo1-f45.google.com with SMTP id 006d021491bc7-5aa1fe2ad39so2064493eaf.2; Tue, 09 Apr 2024 12:08:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1712689724; x=1713294524; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r7AD4q8JSZ6BP9Ctt3D7xQmOd/l0E0VUTJ6hrw2gcfc=; b=EJm/ZN6laHXIj+J/WMRVMVpNLfTkz3xwAK2eEEAvDRLQ+iPu7cxHoTCeN23LqsN4FW cVEcbBmIYypA4Rr3aLxg8s8Bna0peMWOYQQFlAZZ4aCTZlXW0PVZAHWn+SO++GuvV5m1 xDUOw5YGRkRn0EezdWO1SXjvlmqq4uzNRe+9ivcSIV/2y6Ro6S6vXQcGGpoYKCVvneQZ oZ5q7N4Li66zeRjhx4JOYj04JHKe/WKLCF1WJvCokpNf52Eucxpm7v2c/d8rUJsHLHX4 XeM0misdgJPQuG9ssah8GiwyhpDOQC7nGlSd1l9RDWa7QydVZJeyRwrt2KFwQKQeA+bC WQ/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712689724; x=1713294524; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r7AD4q8JSZ6BP9Ctt3D7xQmOd/l0E0VUTJ6hrw2gcfc=; b=CqoCmcqxL8btxYH6vf3KIvU7ZdNvVHVkfLlmQNkU0X7D9xjmKZUILl/z/jOhkYdcpj hRzmvrToW1GpxRgAW9LrNYXDfGz5fmQt6kzm1pBDITth4Ji6uMe+FJuOZjsXBF8pRNCc X40+q4GrLPZTPdJZ5yX/n0pN+lBK+A97dm6Y93lJAgIZ5UPI2KhnRiMdGBIl3mf6FURV f1tupBOrVMOFNhU9VrpYBeUU2lA23K6g17x1DSRUrFIaUOoxGJUf8/ugleAsHZxqd1L2 lJ43kRTycQ0xHhvDkT3Iftp1ONvIawTbAJNJuKXGVax3yp+Q9t0udPAJMxIAyMHBrMP9 Febw== X-Forwarded-Encrypted: i=1; AJvYcCVzcYwsBegeGvhI11aZHsNV0nek5XAsMELiDpgUj64KVQVkC/gvc9/ASAu1YT+7zOdq3JIdnsGEVf6AVjVLP79Mo8/utjxD76xKKyXBSGCVblMnffR/cpSOIqk1GjXkqiyFEgvMs5EOQ98De+Vx01FjJVvM8GlBSW/znJ+9uvtPAeQLmVjZKg== X-Gm-Message-State: AOJu0YzwZdQjnUDDgznDZx8PT3dAEC76U+xWCz+GwsHBImDd8xWBc80H NitZ19sBb3gSN5lNqribHlIQhMEiKT0Qtb3QGarEUQ7vJD4V+YLf X-Google-Smtp-Source: AGHT+IEp6pqikQ+dKpBJfShL46ppdQkFdslYVen1TbCPJt9rJq3/rmmJsLo2FExk5FWOsuBQCNzs3A== X-Received: by 2002:a05:6820:2d49:b0:5aa:53ea:ffd0 with SMTP id dz9-20020a0568202d4900b005aa53eaffd0mr897099oob.1.1712689724695; Tue, 09 Apr 2024 12:08:44 -0700 (PDT) Received: from nukework.lan (c-98-197-58-203.hsd1.tx.comcast.net. [98.197.58.203]) by smtp.gmail.com with ESMTPSA id f11-20020a9d7b4b000000b006ea1cf91a8dsm674920oto.40.2024.04.09.12.08.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Apr 2024 12:08:44 -0700 (PDT) From: Alexandru Gagniuc To: Manivannan Sadhasivam , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Cc: Alexandru Gagniuc , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/7] PCI: qcom: Add support for IPQ9574 Date: Tue, 9 Apr 2024 14:08:30 -0500 Message-Id: <20240409190833.3485824-5-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240409190833.3485824-1-mr.nuke.me@gmail.com> References: <20240409190833.3485824-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for the PCIe on IPQ9574. The main difference from ipq6018 is that the "iface" clock is not necessarry. Add a special case in qcom_pcie_get_resources_2_9_0() to handle this. Signed-off-by: Alexandru Gagniuc Cc: Krzysztof Kozlowski --- drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 14772edcf0d3..10560d6d6336 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1101,15 +1101,19 @@ static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; - int ret; + int ret, num_clks = ARRAY_SIZE(res->clks) - 1; - res->clks[0].id = "iface"; + res->clks[0].id = "rchng"; res->clks[1].id = "axi_m"; res->clks[2].id = "axi_s"; res->clks[3].id = "axi_bridge"; - res->clks[4].id = "rchng"; - ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + if (!of_device_is_compatible(dev->of_node, "qcom,pcie-ipq9574")) { + res->clks[4].id = "iface"; + num_clks++; + } + + ret = devm_clk_bulk_get(dev, num_clks, res->clks); if (ret < 0) return ret; @@ -1664,6 +1668,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 }, { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 }, + { .compatible = "qcom,pcie-ipq9574", .data = &cfg_2_9_0 }, { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp }, From patchwork Tue Apr 9 19:08:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Gagniuc X-Patchwork-Id: 787268 Received: from mail-oo1-f49.google.com (mail-oo1-f49.google.com [209.85.161.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E86D157E66; Tue, 9 Apr 2024 19:08:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712689728; cv=none; b=mHG/jjvVEDe1vahCLKo0r81EDhCR9aZm4pPIrpkQcolvWSiSCZm6W2Mo76DJ1R0S87nJln5nm+jtc3+thaJVmPNkJ+0LN9WhRTRyrH2NuoZlBRIZL7vpNzDEoEInui4mZlXknFl+meDGEBu+t9+CwRVu6VnashIpvGfaHno7HHM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712689728; c=relaxed/simple; bh=WrOGNkfl6FdnCGOJ7wXflZrinARRn6qOE75KPRt97Dw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AjjObN0ocsOJ7Jc16LZuI012gEcltrkOrLGNxa/VR/2fSIpqRbhtcLa5G32IQ7T/yzm59uQU8TPSo+uUgkDuaQhW+2ojVFs+xKqhC8SUBuyXUBi+PiLnRYZo84I4SOKPSpL/+uGC4mAWyzKpHoS4KjngrjVP2Gqj6lV413mOxUM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=UgregSBu; arc=none smtp.client-ip=209.85.161.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UgregSBu" Received: by mail-oo1-f49.google.com with SMTP id 006d021491bc7-5a9c875ceecso3318818eaf.2; Tue, 09 Apr 2024 12:08:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1712689726; x=1713294526; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KZgmkaydqDgMItdlvtLLtr4XRisZHdvGf+UHvwLYIo0=; b=UgregSBuwqKUlxQhWW2zUQQraZkXmXiZrllo2BS+S7Wega5OBZPx0G7KarRq/DPmW/ rHAfoVmUhKZRcqDTcwQyiMxZKr51c0mDoEpBTPUBxLGKQyaTisuVlxTl0qqCf33XJSuD 6LxmaBo15+JFRJn7NkfJDwFaVgRLRPvZkXUGnkXd3RRkQktut8wwVyqs6uIb6+tCagIQ 0QTD544QWWjZiw6kX+YLiLSmhxkU9yXBIGcYGHBPbBp11fIqTZQqUlruE0s6QU7hp4i+ 3ggmUPPx0eqj9FTkuT+APmSXtuPHxGc7mXs12SB33YKkIrT0ESxnE6mZpq3QvXnb8b/j Zt/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712689726; x=1713294526; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KZgmkaydqDgMItdlvtLLtr4XRisZHdvGf+UHvwLYIo0=; b=qLU+lOvfeY7T504I/7VPYSnwVUVr1pJwyHyn1l/vYRVTmCOInvGs0hL1JmprfzHlOU WY5kmwyQE6Fky2096UVmOBeU3K7geigsJH7Muw0WqYaX425/jQ1Rz5rPPprUbq7u9hrs dH7k9KIpon8Rl4wkN2SXu+d5hvqX4ysQ3E34ER1XyG4B78icmpoDgQMkxfFWInmy6DSF hosWKeI1Rn4ufpu9fc6WJXSZYqIAEBSopeNoPARFlOdAH5wL48Ju0Xw868V5DGMtdj1R 74SxGtIBo/gKaZudtiSooXLH5BZdBjNEoyxXRWEzMI/EGV61FrY8975JGzP544WYj0y+ If6A== X-Forwarded-Encrypted: i=1; AJvYcCXFAak/fPhxtF0Jo2y5VVJnZPte1ii5VfMM6yCVaI7JGGhNP9hg+N3VkN7mfh6Kw98FVoT/frrir8Z/K6y5sjnu50xofUo97B5lGHF3XI5o2XFZVyzpgqJzHN0w94F+w2yefHY9WeTO0OXHB8lg/Q7MAKfBm8qPURlqlyE8/Kg4PihWvo/gYGY= X-Gm-Message-State: AOJu0YxrC3vHugwnbb+Trt5qMykOD6hlfAKvOn95r+bEbo0Q+O6yuw9U bkdnoF7mKxycD6w7iYszYsGJRWEDgFrIqIpA9O+4TpBS9ElJ3I7Z X-Google-Smtp-Source: AGHT+IGiME8d4pJkFeFHGfQFDyNAq9/Vl7xfXdxtFnHfzc4Tw8Y6pdQ+xVXSrnZR01C24EMRzlNnog== X-Received: by 2002:a05:6820:1e02:b0:5a5:21df:7eef with SMTP id dh2-20020a0568201e0200b005a521df7eefmr877211oob.2.1712689726402; Tue, 09 Apr 2024 12:08:46 -0700 (PDT) Received: from nukework.lan (c-98-197-58-203.hsd1.tx.comcast.net. [98.197.58.203]) by smtp.gmail.com with ESMTPSA id f11-20020a9d7b4b000000b006ea1cf91a8dsm674920oto.40.2024.04.09.12.08.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Apr 2024 12:08:45 -0700 (PDT) From: Alexandru Gagniuc To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Alexandru Gagniuc , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/7] dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY Date: Tue, 9 Apr 2024 14:08:31 -0500 Message-Id: <20240409190833.3485824-6-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240409190833.3485824-1-mr.nuke.me@gmail.com> References: <20240409190833.3485824-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The IPQ9574 gen3x2 PHY is very similar to IPQ6018. It requires two extra clocks named "anoc" and "snoc". Document this, and add a new compatible string for this PHY. Signed-off-by: Alexandru Gagniuc --- .../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 31 ++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml index 634cec5d57ea..017ad65a9a3c 100644 --- a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml @@ -19,19 +19,22 @@ properties: - qcom,ipq6018-qmp-pcie-phy - qcom,ipq8074-qmp-gen3-pcie-phy - qcom,ipq8074-qmp-pcie-phy + - qcom,ipq9574-qmp-gen3x2-pcie-phy reg: items: - description: serdes clocks: - maxItems: 3 + minItems: 3 clock-names: items: - const: aux - const: cfg_ahb - const: pipe + - const: anoc + - const: snoc resets: maxItems: 2 @@ -61,6 +64,32 @@ required: - clock-output-names - "#phy-cells" +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq6018-qmp-pcie-phy + - qcom,ipq8074-qmp-gen3-pcie-phy + - qcom,ipq8074-qmp-pcie-phy + then: + properties: + clocks: + maxItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq9574-qmp-gen3x2-pcie-phy + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + additionalProperties: false examples: From patchwork Tue Apr 9 19:08:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Gagniuc X-Patchwork-Id: 787597 Received: from mail-ot1-f52.google.com (mail-ot1-f52.google.com [209.85.210.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA4AD157E88; Tue, 9 Apr 2024 19:08:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712689730; cv=none; b=L8jpao3M4kfCszkF+A/Q24TTTZFk/5o6Uz9P/MkWhpEt6usDelYjyDHAEkiBRF+jIsnAmlaMGv+GUi2DPWCaJUqhaOenDyeuKYH2117mcPBOyio5CxAIR7XrF3lHWZzOTVejX6ei+iGH8jTXnJmX3WDIPxORz/u6c0OsTUAyvX0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712689730; c=relaxed/simple; bh=K3wtnUHlnd83c7e2by3+ZGsUNPcapx6xI/kSLEUipKQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ilpTqiyC+r5SowfT6d5O3F8Pgr/bdQukhtfe4u3/VAWhSOWtQSa9VQoX+EbRzNcsBA5FeGCnTl4zgSFQ63OMc/OFvE2QIwWsWSwW1BIjL0nO5bVpXaZpZNv+wrvlHgSUkeqwiqwco9NLaMMThUKrNm4xOvZdOiWQEGFRV/uvJ5o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=V083H5Wf; arc=none smtp.client-ip=209.85.210.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="V083H5Wf" Received: by mail-ot1-f52.google.com with SMTP id 46e09a7af769-6ea243406f0so477788a34.2; Tue, 09 Apr 2024 12:08:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1712689728; x=1713294528; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ypmL3L8VbfyFDiBe9rYezVE5zYPXjmGvZhaqr+UnTBg=; b=V083H5Wf0H4x+Xz8XjD5hNA5eEGbWTGov57g11pBWFHwezsiwEDNQ0LCqYjHEom/+B 8WTZuyvF6FpHOFw349hIuSbC0CEgiU930q0uVlWmYCoTXTMsUBeR92yI44ndJhP/dNSj /F1VyaXI5h6K+MUiDxTqKIlAmRoOnfvS4al/Tkj9JaaVdK/83u0pv+4qMPCbUfbpzGA9 8xKRNYE4RH5E3iWx/Y7+wYUIkpdMVzcULyVuKazpuYOZ84XKVaXlLjubMIpo39ZgGQ8P JkNz0dn8baAlSEUkffE62lkBvNo8NADdRe8mm5Jr1anZDNXjN0Rlk85J4kw52yhYF1eJ XDPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712689728; x=1713294528; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ypmL3L8VbfyFDiBe9rYezVE5zYPXjmGvZhaqr+UnTBg=; b=c1w8b1UMglRdkIAtlq0aKoBE3RudKT1ATVzVldtq4cFrOGgpMNaD6YtmnYRJclxRyS 7gdUlOTHZ4ZJmQZ14UwDKyWjUd6oar8ugGF73z+gxd9dAkfFbN6/ZqyLCmllR1i+I5OO ti2mlO6WJr1uA3sYOWlvsTfZU7jL/QrRYzulqlFH4jA3SHO2SHweht8iOF/iKeowjffM gcDZInwA6Fg8t/TalfNPDFq+fC5tV5rz2n55RKDNJp6HcrPfp8DdQDXY6K7fuI77YGyv PPADaqJfyvm8Cf8eOGB/AVrLPv68J7yQGQLi2tNkr3s6bHtYzHfGBSC8xvamauuxtBuu 24Hw== X-Forwarded-Encrypted: i=1; AJvYcCXbOjUHD5zA5s1gTeO6M0Jms4CxpTt6zzudviHyx5ysiygz/UEWEkX/G3k7xeYUhXIc7T0DS+QdZYYtQfLT6XKFjB9KLTk7AIRY7z/PHn7hPmFtRz172fo/HAKkPAWAzOZ81fsGv25uw5+7FQ== X-Gm-Message-State: AOJu0YymFWxkbMscAowypFlmc+/2/kEQzQYdUwiwtirgYBg+OTziWtlf POXsv4OWR8D/M6wSvL73KINpdBoI+lwjrobR+deXAFUTS30IH48p X-Google-Smtp-Source: AGHT+IEtvC1o5ZUedgbdo3LduD2qvO8REHsn72fv6NsPszF5IKWYIecvMYP/PWH6CPw+MKbXbYoIEA== X-Received: by 2002:a05:6830:10cf:b0:6ea:2ef7:d73d with SMTP id z15-20020a05683010cf00b006ea2ef7d73dmr623068oto.37.1712689727992; Tue, 09 Apr 2024 12:08:47 -0700 (PDT) Received: from nukework.lan (c-98-197-58-203.hsd1.tx.comcast.net. [98.197.58.203]) by smtp.gmail.com with ESMTPSA id f11-20020a9d7b4b000000b006ea1cf91a8dsm674920oto.40.2024.04.09.12.08.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Apr 2024 12:08:47 -0700 (PDT) From: Alexandru Gagniuc To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I Cc: Alexandru Gagniuc , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/7] phy: qcom-qmp-pcie: add support for ipq9574 gen3x2 PHY Date: Tue, 9 Apr 2024 14:08:32 -0500 Message-Id: <20240409190833.3485824-7-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240409190833.3485824-1-mr.nuke.me@gmail.com> References: <20240409190833.3485824-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for the gen3x2 PCIe PHY on IPQ9574, ported form downstream 5.4 kernel. Only the serdes and pcs_misc tables are new, the others being reused from IPQ8074 and IPQ6018 PHYs. Signed-off-by: Alexandru Gagniuc Cc: Krzysztof Kozlowski --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 136 +++++++++++++++++- .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 ++ 2 files changed, 149 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 8836bb1ff0cc..a4a79ddf50a5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -487,6 +487,100 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), }; +static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89), + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10), +}; + +static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0b), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2a), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), +}; + static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), @@ -2448,7 +2542,7 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) /* list of clocks required by phy */ static const char * const qmp_pciephy_clk_l[] = { - "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", + "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", "anoc", "snoc" }; /* list of regulators */ @@ -2499,6 +2593,16 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = { .rx = 0x0400, }; +static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = { + .serdes = 0, + .pcs = 0x1000, + .pcs_misc = 0x1400, + .tx = 0x0200, + .rx = 0x0400, + .tx2 = 0x0600, + .rx2 = 0x0800, +}; + static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = { .serdes = 0, .pcs = 0x0a00, @@ -2728,6 +2832,33 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { .phy_status = PHYSTATUS, }; +static const struct qmp_phy_cfg ipq9574_pciephy_gen3x2_cfg = { + .lanes = 2, + + .offsets = &qmp_pcie_offsets_ipq9574, + + .tbls = { + .serdes = ipq9574_gen3x2_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl), + .tx = ipq8074_pcie_gen3_tx_tbl, + .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), + .rx = ipq6018_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), + .pcs = ipq6018_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), + .pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl), + }, + .reset_list = ipq8074_pciephy_reset_l, + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), + .vreg_list = NULL, + .num_vregs = 0, + .regs = pciephy_v4_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, +}; + static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { .lanes = 2, @@ -3935,6 +4066,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { }, { .compatible = "qcom,ipq8074-qmp-pcie-phy", .data = &ipq8074_pciephy_cfg, + }, { + .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy", + .data = &ipq9574_pciephy_gen3x2_cfg, }, { .compatible = "qcom,msm8998-qmp-pcie-phy", .data = &msm8998_pciephy_cfg, diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h index a469ae2a10a1..fa15a03055de 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h @@ -11,8 +11,22 @@ #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14 #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 +#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x44 +#define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x48 +#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x4c +#define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x50 #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 +#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1 0x5c +#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2 0x60 +#define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4 0x68 +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x7c +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x84 +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x88 +#define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x8c #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 +#define QPHY_V5_PCS_PCIE_EQ_CONFIG1 0xa4 #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 +#define QPHY_V5_PCS_PCIE_PRESET_P10_PRE 0xc0 +#define QPHY_V5_PCS_PCIE_PRESET_P10_POST 0xe4 #endif From patchwork Tue Apr 9 19:08:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Gagniuc X-Patchwork-Id: 787267 Received: from mail-ot1-f43.google.com (mail-ot1-f43.google.com [209.85.210.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73AFF1581E9; Tue, 9 Apr 2024 19:08:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712689732; cv=none; b=H0snSKh8iVMGctE4/UCpEmywHjmgD9Ntyggba3+llDrY/ayqrwjtccgT7EjEi1T66E+wS9Ms08y3K1JPcQ1usZzZMzsMX5BHMEgcGIgx4vNe9ohUDrzXc7x7lEpEwRQfd8iTbl5lFdoJVKws5rO9h8JrW0HJdjCle4nnQRNoNEo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712689732; c=relaxed/simple; bh=/HQoYouMyd4m4GJGvNYVAIPjvnrP+JB97VJJEEcC1X8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=moJH5vOZh0yBT0xM5mh2e9tnqt2Q2bilZZ5Imsuhk+EMY6j8CinVfK5fbDy5xwaQOncGfhb9LZdkTl7de29k4H/PNz2FciNFk2+lrnOyN61+9TgdkkdymEtvWxrmn25HLI7GXaMd/F26VPFVnIEIZeENDWSjeafkW3xoHLfLDK0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=AsTsAHrC; arc=none smtp.client-ip=209.85.210.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="AsTsAHrC" Received: by mail-ot1-f43.google.com with SMTP id 46e09a7af769-6ea26393116so715836a34.0; Tue, 09 Apr 2024 12:08:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1712689729; x=1713294529; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VG4gX0gqtcPyBLH5Dknw/zIzUHmrrHhMR9dznIhdZtg=; b=AsTsAHrC/bVVKk4GAQEH1JM5Rr02urh9xDLFgSAMD9ORc2OxZRlem1IdMcNcBM1wDM dKc84aJNYCAU1JE0/i0e1cZQ2w64fz0oh3Hcquz4FIttnJTEfp7hiMciXYcHdDvztHIx 3shYMhb9VujGyrC2wm+TdAKbWglasLNW2QSq4/0Ey+uSZUPMtn1MOUg8mNqqtbcVvM1Q YxPVFkPARSDrcmE7iXqDmhh+xLJiRrGJkYxXs7YnqKIDDKeEtekIWhCT0oPvYbMLy3wG Si7YnYa3WwdY0Mwc4CHvIzeXVlJcy/OcbjeBrbyS+TEdhPUNCPwDtwcMOeO+1B7jlN1i Mxmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712689729; x=1713294529; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VG4gX0gqtcPyBLH5Dknw/zIzUHmrrHhMR9dznIhdZtg=; b=UxcpS8826jp+BLtFzvLhP2E4rSejdkjF7mjtp83g4Giz7aLLLG3Z8BcnqYW7Lmgkeg IsfnAjQveep7z8sj3JDilKmnfMlJmQhp0ucfIrcBe9Yg5AYn9jJ5nS/dTCLU8tRt6A6S R3vXEWn+ZOlDK/RnqnOkMMJRv0pxwifu3JRh/J9gonA9ISnrpKNUuMqBCprBnUAaCytC ScQ5woxOPjZBv+WPxAWSix4Y2v4128+QfHgBLpUpIdg+cxqgJpa5F37brUZ5LDu/k684 xtStPZg0UDILfRlfjsMHQiNONr1vdtD1bdr8LqskGHTXrvVKyqkDgUIS66KOnWgrW/VX +5Xw== X-Forwarded-Encrypted: i=1; AJvYcCVr8O8YCDsXjP5CxCBtAlNtIp8SERsGjJ9HCom216FhXHnpycvlCiE6X84y8iA2MaYQonpPw7/HDu2ifSspGi4KX2KmsPh+QJYqR6420/j83q+gQqKfZu6EPbrNiR23PDAO6PbqvPs+0d0xnBZBC7JjkgXVMR1fpJ7utLv1cMFh3i0TfSQpmlY= X-Gm-Message-State: AOJu0YwpSEd345fB8655+zDbv5w+eqtULwP5aKtOKz6xO1qsDH9chHbF WZ8qCFUJKizYzkvYB/faGXwb6xZLjbOzVoWlyb2pFheeRC9vp5c7 X-Google-Smtp-Source: AGHT+IHpg3s9XTt/dwVQJebWvhrYPSQJAoRkPk1Px8mFr+MPXCTkPub7ix8hf34bwA0iRcmErWDMPQ== X-Received: by 2002:a9d:7e92:0:b0:6ea:23af:2bcb with SMTP id m18-20020a9d7e92000000b006ea23af2bcbmr740934otp.32.1712689729588; Tue, 09 Apr 2024 12:08:49 -0700 (PDT) Received: from nukework.lan (c-98-197-58-203.hsd1.tx.comcast.net. [98.197.58.203]) by smtp.gmail.com with ESMTPSA id f11-20020a9d7b4b000000b006ea1cf91a8dsm674920oto.40.2024.04.09.12.08.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Apr 2024 12:08:48 -0700 (PDT) From: Alexandru Gagniuc To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Alexandru Gagniuc , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/7] arm64: dts: qcom: ipq9574: add PCIe2 nodes Date: Tue, 9 Apr 2024 14:08:33 -0500 Message-Id: <20240409190833.3485824-8-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240409190833.3485824-1-mr.nuke.me@gmail.com> References: <20240409190833.3485824-1-mr.nuke.me@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On ipq9574, there are 4 PCIe controllers. Describe the pcie2 node, and its PHY in devicetree. Only pcie2 is described, because only hardware using that controller was available for testing. Signed-off-by: Alexandru Gagniuc --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 94 ++++++++++++++++++++++++++- 1 file changed, 93 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 7f2e5cbf3bbb..61c518f2a05a 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -300,7 +300,7 @@ gcc: clock-controller@1800000 { <0>, <0>, <0>, - <0>, + <&pcie2_phy>, <0>, <0>; #clock-cells = <1>; @@ -745,6 +745,98 @@ frame@b128000 { status = "disabled"; }; }; + + pcie2_phy: phy@8c000 { + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; + reg = <0x0008c000 0x14f4>; + + clocks = <&gcc GCC_PCIE2_AUX_CLK>, + <&gcc GCC_PCIE2_AHB_CLK>, + <&gcc GCC_PCIE2_PIPE_CLK>, + <&gcc GCC_ANOC_PCIE2_2LANE_M_CLK>, + <&gcc GCC_SNOC_PCIE2_2LANE_S_CLK>; + clock-names = "aux", + "cfg_ahb", + "pipe", + "anoc", + "snoc"; + + clock-output-names = "pcie_phy2_pipe_clk"; + #clock-cells = <0>; + #phy-cells = <0>; + + resets = <&gcc GCC_PCIE2_PHY_BCR>, + <&gcc GCC_PCIE2PHY_PHY_BCR>; + reset-names = "phy", + "common"; + status = "disabled"; + }; + + pcie2: pcie@20000000 { + compatible = "qcom,pcie-ipq9574"; + reg = <0x20000000 0xf1d>, + <0x20000f20 0xa8>, + <0x20001000 0x1000>, + <0x00088000 0x4000>, + <0x20100000 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; + + ranges = <0x81000000 0x0 0x20200000 0x20200000 0x0 0x00100000>, /* I/O */ + <0x82000000 0x0 0x20300000 0x20300000 0x0 0x07d00000>; /* MEM */ + + device_type = "pci"; + linux,pci-domain = <3>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + max-link-speed = <3>; + #address-cells = <3>; + #size-cells = <2>; + + phys = <&pcie2_phy>; + phy-names = "pciephy"; + + interrupts = ; + interrupt-names = "msi"; + msi-parent = <&v2m0>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 164 + IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 165 + IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 186 + IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 187 + IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE2_AXI_M_CLK>, + <&gcc GCC_PCIE2_AXI_S_CLK>, + <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE2_RCHNG_CLK>; + clock-names = "axi_m", + "axi_s", + "axi_bridge", + "rchng"; + + resets = <&gcc GCC_PCIE2_PIPE_ARES>, + <&gcc GCC_PCIE2_CORE_STICKY_ARES>, + <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>, + <&gcc GCC_PCIE2_AXI_S_ARES>, + <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>, + <&gcc GCC_PCIE2_AXI_M_ARES>, + <&gcc GCC_PCIE2_AUX_ARES>, + <&gcc GCC_PCIE2_AHB_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + status = "disabled"; + }; }; thermal-zones {