From patchwork Tue Oct 8 12:55:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 175482 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp5662581ill; Tue, 8 Oct 2019 05:56:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqzTx+69d3mVRpDXN7f7gRQ1tYQN8ftKoRcACCqxsgW9iQHhhZdq+3p4SUDel9YFArbi/nji X-Received: by 2002:a50:fd86:: with SMTP id o6mr33880209edt.139.1570539362981; Tue, 08 Oct 2019 05:56:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570539362; cv=none; d=google.com; s=arc-20160816; b=LJ2qgsQeRTF87eKRA0MUqIkhRG/EmiCrxR5jwNeiB6UFT+SWqawKbdvm6BRvaVf5fk /Au/P2OLSGvx7vjwogKNwiTI2nOTeBeAkvR0VwBU0fU5N3n12ev8ohS0n3I2/QpXkIbg YgpIYQnt6jmk291K9oaT/OJSeZetQTFruFyDXnb9am4fZrztfem7EmsibwlxW7Agphkd 39dw5dewT57FKNCxWPg3p58FlyGmTy0Ig/uRmqSG8pbaqiehq6XTEkqgz4xCTT4tfxzM LOjy1E3SuyUuazD7latwZ5RO8UI9qdKmNfgaLgpxwbAJTBiPZg2ThvCYvbOMQJ6BCwck hBAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=5NjhrYu8nXMN27ChfH5ORG8Z1ERJZGAOrQx8/HEKMSw=; b=WoVYmLBqvhFo1rBKbJvj4/3+WadvffiH7NIiDqeSwpUrnZZNC9D3LI8I81wr8ByVfm 3F7f7kos7KTRRUKrg4fgY2XOKE4BwgZ5h6vqqxJMLNSXeWD5rp7IrwEdSgpIzNw3aizM MyBs4/JfDXs8Wnd0C7rD4Ht9+R+MEbIntm5yV673KjsQ8GDflVO4x9N473zVSag+G7PQ FUd7QRGOspnpLMaoatNFbU4fdgSh7n97E1Vbcqna7YamqczR9/MAJXKv2NTY8KziW0F/ 8yaPsTDIyLBspqv3Swiz68TLaVuKXkEO6rRBLqQZ1j5FuaxpsQ5F4ESfNYehc7ttCjlt AdUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hnL6JwOU; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r18si8900282ejr.189.2019.10.08.05.56.02; Tue, 08 Oct 2019 05:56:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hnL6JwOU; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730829AbfJHM4C (ORCPT + 8 others); Tue, 8 Oct 2019 08:56:02 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35978 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730555AbfJHM4C (ORCPT ); Tue, 8 Oct 2019 08:56:02 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x98CtpQB128825; Tue, 8 Oct 2019 07:55:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1570539351; bh=5NjhrYu8nXMN27ChfH5ORG8Z1ERJZGAOrQx8/HEKMSw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hnL6JwOUbAorQa+JlkF66iuqQ+gwHIGnxi9pDSazL1cvBxeLvz7nEAhddwzWBNO3C BuGFjVSTOMU9TIhAaftNJ/Oq4D0IDEVue4lT6Xmmq4Sg09LVnPMI2QM/Hs+TGSFJWY eHKhmGTLA/ezwiihGUit7uPFarYYSy7aze4/3Aho= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x98CtpAT104014; Tue, 8 Oct 2019 07:55:51 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 8 Oct 2019 07:55:48 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 8 Oct 2019 07:55:50 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x98Ctk58046741; Tue, 8 Oct 2019 07:55:49 -0500 From: Tero Kristo To: , CC: , , , , Subject: [PATCHv8 1/9] dt-bindings: omap: add new binding for PRM instances Date: Tue, 8 Oct 2019 15:55:36 +0300 Message-ID: <20191008125544.20679-2-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191008125544.20679-1-t-kristo@ti.com> References: <20191008125544.20679-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add new binding for OMAP PRM (Power and Reset Manager) instances. Each of these will act as a power domain controller and potentially as a reset provider. Signed-off-by: Tero Kristo Reviewed-by: Rob Herring Reviewed-by: Tony Lindgren --- v7: - dropped clocks property from example .../devicetree/bindings/arm/omap/prm-inst.txt | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/omap/prm-inst.txt -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/arm/omap/prm-inst.txt b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt new file mode 100644 index 000000000000..dfe7c7789ca7 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt @@ -0,0 +1,29 @@ +OMAP PRM instance bindings + +Power and Reset Manager is an IP block on OMAP family of devices which +handle the power domains and their current state, and provide reset +handling for the domains and/or separate IP blocks under the power domain +hierarchy. + +Required properties: +- compatible: Must contain one of the following: + "ti,am3-prm-inst" + "ti,am4-prm-inst" + "ti,omap4-prm-inst" + "ti,omap5-prm-inst" + "ti,dra7-prm-inst" + and additionally must contain: + "ti,omap-prm-inst" +- reg: Contains PRM instance register address range + (base address and length) + +Optional properties: +- #reset-cells: Should be 1 if the PRM instance in question supports resets. + +Example: + +prm_dsp2: prm@1b00 { + compatible = "ti,omap-prm-inst", "ti,dra7-prm-inst"; + reg = <0x1b00 0x40>; + #reset-cells = <1>; +}; From patchwork Tue Oct 8 12:55:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 175484 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp5662660ill; Tue, 8 Oct 2019 05:56:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqzYB6zer8iMPGuMMT2aKW9X9TkiHEWHeDhzgj8ORNK30W/CpKymblULk4fI+nL7GDZA1OhI X-Received: by 2002:a17:906:3746:: with SMTP id e6mr27626418ejc.238.1570539367675; Tue, 08 Oct 2019 05:56:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570539367; cv=none; d=google.com; s=arc-20160816; b=ZEKuEiyLUCkDIYQ3vfu7zeOkvR98p9NcsvqY3QEXAZFh65nOsrjSSnJ2SjEdPzvYu9 xj1hUvSKWamCQkFrPWPOQt1sIMfEceJOfdF9yQip5sN9wdV+ImnVlTsbXKiDCxV2GYJR pOVmvnOBCpjy3uvO3tuo5ptIj4Btx+KvIPnU2OGYuqwYzKq1PErAS4CSgPMZLjsxOnjt hMljUC2H8w8pLFTWpCVsfPbOH6VwsQc4Ewjd1BbgrgPHrZmALPRmgjHJAWJmJak3H5yb Po0TOmD/3pQpzbazrxRh5EARTgl39eIIK2qg9dUkU4jI293v22Gy1FHkzVbm/zW1X/Mt EkxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=G8289aRJfVA/dSJ5JOSz2CwWIP3g5BD8CiOjzDc3inA=; b=inYmKqOzpqUCuGEqrtp+JIlPTADTtibdKJwd8qz7SC7DzLfTfRTVAOcWeibnF5yGmp 44IeBf7Bx9p+mG3JO2DH1l0YX2ZjjEbziWzYdCE5e3ti0sGd65Ik08tShRO+USqE1Iil QANeiyZfGGrDnadVTxrjk/6BYBdTlxfgu3KY+Bhw5PPOm48EISsfhqOBF+2hm03Evowp MM5vUQTG4YZQflQ847Xcr5lUEEIZ8hI+3iki7nOj+eIfLe9gXV93NcUdQK43jyj5VcDR Wcu+mH67mFlIbSzg9akWTZSly7NrYm2MGZaUVEY3eOqgOzYbTmMBpgACkBoPvuoImR6W mwww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Aa3yMMjo; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g5si10344318edb.324.2019.10.08.05.56.07; Tue, 08 Oct 2019 05:56:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Aa3yMMjo; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730936AbfJHM4D (ORCPT + 8 others); Tue, 8 Oct 2019 08:56:03 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:35980 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730583AbfJHM4D (ORCPT ); Tue, 8 Oct 2019 08:56:03 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x98Ctr9V128830; Tue, 8 Oct 2019 07:55:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1570539353; bh=G8289aRJfVA/dSJ5JOSz2CwWIP3g5BD8CiOjzDc3inA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Aa3yMMjol+7uOWNTZNQFPPWNEeOWAvNewtV6V3vLuGrIHPOO21DnBt8FTZKUy3+jR iHc0jmNAwanbmTbcYgzijKdpKbOcHcFCDjG7Zp0uMBLrWZGJCnG/8AHiRUp4ZlxquX 9933uOicKl87N4IhIOlfvdwSGs4AvbXQfGUoqQrQ= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x98CtrmR009992 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Oct 2019 07:55:53 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 8 Oct 2019 07:55:50 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 8 Oct 2019 07:55:50 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x98Ctk59046741; Tue, 8 Oct 2019 07:55:51 -0500 From: Tero Kristo To: , CC: , , , , Subject: [PATCHv8 2/9] soc: ti: add initial PRM driver with reset control support Date: Tue, 8 Oct 2019 15:55:37 +0300 Message-ID: <20191008125544.20679-3-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191008125544.20679-1-t-kristo@ti.com> References: <20191008125544.20679-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add initial PRM (Power and Reset Management) driver for TI OMAP class SoCs. Initially this driver only supports reset control, but can be extended to support rest of the functionality, like powerdomain control, PRCM irq support etc. Signed-off-by: Tero Kristo Reviewed-by: Philipp Zabel --- v8: only write single bit as one when clearing reset status arch/arm/mach-omap2/Kconfig | 1 + drivers/soc/ti/Makefile | 1 + drivers/soc/ti/omap_prm.c | 259 ++++++++++++++++++++++++++++++++++++ 3 files changed, 261 insertions(+) create mode 100644 drivers/soc/ti/omap_prm.c -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index fdb6743760a2..ad08d470a2ca 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -109,6 +109,7 @@ config ARCH_OMAP2PLUS select TI_SYSC select OMAP_IRQCHIP select CLKSRC_TI_32K + select ARCH_HAS_RESET_CONTROLLER help Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile index b3868d392d4f..788b5cd1e180 100644 --- a/drivers/soc/ti/Makefile +++ b/drivers/soc/ti/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_KEYSTONE_NAVIGATOR_QMSS) += knav_qmss.o knav_qmss-y := knav_qmss_queue.o knav_qmss_acc.o obj-$(CONFIG_KEYSTONE_NAVIGATOR_DMA) += knav_dma.o obj-$(CONFIG_AMX3_PM) += pm33xx.o +obj-$(CONFIG_ARCH_OMAP2PLUS) += omap_prm.o obj-$(CONFIG_WKUP_M3_IPC) += wkup_m3_ipc.o obj-$(CONFIG_TI_SCI_PM_DOMAINS) += ti_sci_pm_domains.o obj-$(CONFIG_TI_SCI_INTA_MSI_DOMAIN) += ti_sci_inta_msi.o diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c new file mode 100644 index 000000000000..ab0b66ad715d --- /dev/null +++ b/drivers/soc/ti/omap_prm.c @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OMAP2+ PRM driver + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Tero Kristo + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct omap_rst_map { + s8 rst; + s8 st; +}; + +struct omap_prm_data { + u32 base; + const char *name; + u16 rstctrl; + u16 rstst; + const struct omap_rst_map *rstmap; + u8 flags; +}; + +struct omap_prm { + const struct omap_prm_data *data; + void __iomem *base; +}; + +struct omap_reset_data { + struct reset_controller_dev rcdev; + struct omap_prm *prm; + u32 mask; + spinlock_t lock; +}; + +#define to_omap_reset_data(p) container_of((p), struct omap_reset_data, rcdev) + +#define OMAP_MAX_RESETS 8 +#define OMAP_RESET_MAX_WAIT 10000 + +#define OMAP_PRM_HAS_RSTCTRL BIT(0) +#define OMAP_PRM_HAS_RSTST BIT(1) + +#define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST) + +static const struct of_device_id omap_prm_id_table[] = { + { }, +}; + +static bool _is_valid_reset(struct omap_reset_data *reset, unsigned long id) +{ + if (reset->mask & BIT(id)) + return true; + + return false; +} + +static int omap_reset_get_st_bit(struct omap_reset_data *reset, + unsigned long id) +{ + const struct omap_rst_map *map = reset->prm->data->rstmap; + + while (map->rst >= 0) { + if (map->rst == id) + return map->st; + + map++; + } + + return id; +} + +static int omap_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct omap_reset_data *reset = to_omap_reset_data(rcdev); + u32 v; + int st_bit = omap_reset_get_st_bit(reset, id); + bool has_rstst = reset->prm->data->rstst || + (reset->prm->data->flags & OMAP_PRM_HAS_RSTST); + + /* Check if we have rstst */ + if (!has_rstst) + return -ENOTSUPP; + + /* Check if hw reset line is asserted */ + v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); + if (v & BIT(id)) + return 1; + + /* + * Check reset status, high value means reset sequence has been + * completed successfully so we can return 0 here (reset deasserted) + */ + v = readl_relaxed(reset->prm->base + reset->prm->data->rstst); + v >>= st_bit; + v &= 1; + + return !v; +} + +static int omap_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct omap_reset_data *reset = to_omap_reset_data(rcdev); + u32 v; + unsigned long flags; + + /* assert the reset control line */ + spin_lock_irqsave(&reset->lock, flags); + v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); + v |= 1 << id; + writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); + spin_unlock_irqrestore(&reset->lock, flags); + + return 0; +} + +static int omap_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct omap_reset_data *reset = to_omap_reset_data(rcdev); + u32 v; + int st_bit; + bool has_rstst; + unsigned long flags; + + has_rstst = reset->prm->data->rstst || + (reset->prm->data->flags & OMAP_PRM_HAS_RSTST); + + if (has_rstst) { + st_bit = omap_reset_get_st_bit(reset, id); + + /* Clear the reset status by writing 1 to the status bit */ + v = 1 << st_bit; + writel_relaxed(v, reset->prm->base + reset->prm->data->rstst); + } + + /* de-assert the reset control line */ + spin_lock_irqsave(&reset->lock, flags); + v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); + v &= ~(1 << id); + writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); + spin_unlock_irqrestore(&reset->lock, flags); + + return 0; +} + +static const struct reset_control_ops omap_reset_ops = { + .assert = omap_reset_assert, + .deassert = omap_reset_deassert, + .status = omap_reset_status, +}; + +static int omap_prm_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + struct omap_reset_data *reset = to_omap_reset_data(rcdev); + + if (!_is_valid_reset(reset, reset_spec->args[0])) + return -EINVAL; + + return reset_spec->args[0]; +} + +static int omap_prm_reset_init(struct platform_device *pdev, + struct omap_prm *prm) +{ + struct omap_reset_data *reset; + const struct omap_rst_map *map; + + /* + * Check if we have controllable resets. If either rstctrl is non-zero + * or OMAP_PRM_HAS_RSTCTRL flag is set, we have reset control register + * for the domain. + */ + if (!prm->data->rstctrl && !(prm->data->flags & OMAP_PRM_HAS_RSTCTRL)) + return 0; + + map = prm->data->rstmap; + if (!map) + return -EINVAL; + + reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); + if (!reset) + return -ENOMEM; + + reset->rcdev.owner = THIS_MODULE; + reset->rcdev.ops = &omap_reset_ops; + reset->rcdev.of_node = pdev->dev.of_node; + reset->rcdev.nr_resets = OMAP_MAX_RESETS; + reset->rcdev.of_xlate = omap_prm_reset_xlate; + reset->rcdev.of_reset_n_cells = 1; + spin_lock_init(&reset->lock); + + reset->prm = prm; + + while (map->rst >= 0) { + reset->mask |= BIT(map->rst); + map++; + } + + return devm_reset_controller_register(&pdev->dev, &reset->rcdev); +} + +static int omap_prm_probe(struct platform_device *pdev) +{ + struct resource *res; + const struct omap_prm_data *data; + struct omap_prm *prm; + const struct of_device_id *match; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + match = of_match_device(omap_prm_id_table, &pdev->dev); + if (!match) + return -ENOTSUPP; + + prm = devm_kzalloc(&pdev->dev, sizeof(*prm), GFP_KERNEL); + if (!prm) + return -ENOMEM; + + data = match->data; + + while (data->base != res->start) { + if (!data->base) + return -EINVAL; + data++; + } + + prm->data = data; + + prm->base = devm_ioremap_resource(&pdev->dev, res); + if (!prm->base) + return -ENOMEM; + + return omap_prm_reset_init(pdev, prm); +} + +static struct platform_driver omap_prm_driver = { + .probe = omap_prm_probe, + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = omap_prm_id_table, + }, +}; +builtin_platform_driver(omap_prm_driver); From patchwork Tue Oct 8 12:55:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 175491 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp5662682ill; Tue, 8 Oct 2019 05:56:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqxPkQF57nQfuo2kOkoqURUKqx3ouJKhvAqSCxO4hje0p9VCdcJODglRLuZ3hYWJuCwdB1Cp X-Received: by 2002:a50:9734:: with SMTP id c49mr34047187edb.93.1570539368381; Tue, 08 Oct 2019 05:56:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570539368; cv=none; d=google.com; s=arc-20160816; b=O9h8kNXpe80Zou6VHgn7B/llcwRmcevEuNSIXwTYIyITccroT4Xi7Vr1EnJuM5lZzl mkTy+EK0Fm55g6psX4CQjrd4vEUerRneBTCP22QntfxgnJUL2RH5APtKsLJCapGMpAZA zpavjPuGMMygDDAoZ63pvyPAdqzvBExme+dE3zzzKN8P3LAe5gnA9cwZivN6nSUvB4UF WUEmnMffEXvxnFbo6Q1tuNSA8PrXU5bLC35mi/ieGl82BTOym/a1Gn1NwP4IaG8zt/5y t/60w3sQBsrN2fXE7K55Y2grlQMdugD+HypAxRXUR6sFKrgXdJ1pdQhTnNUw1A5q3do4 2rbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=0U7cEQcBhntH5Gw0+k1lJPKNZLpQWi0nd7i4zRZ3HpQ=; b=qr4o59wSV9psUFCYHT/6CfTxCWctdmuiu7w/KYS9DkdQ1z7b2M4//C/FKaApHM51KX tLsx2JjZYEAaD+w6tOPZfgDjBL4M2Gyl1feTxSaXlk7lUNuKWOiUYMwkhIOIzID50IdF IQvODOVbyaO3JYDhkRDYkDwYWjo4vZYyxr61MMgWim1LNC7PIxkQF25rhoC2iHJEJDmu 0mh+qR7foOQDUE+5xxJNcl8OVbdaXvLvHBJxnF0T15QH2zYDkjB7srzr41ViucUia2Nm yaAYmfQOlAQ+zB6TaVICXi9nY0R2t4A5Ov40Bmdwzrex9SsbH86vOif2ljtmjuZ0zApW qgYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=CTPvp1lX; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Tero Kristo Reviewed-by: Philipp Zabel --- drivers/soc/ti/omap_prm.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index ab0b66ad715d..96fa2aad9b93 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -153,6 +153,18 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); spin_unlock_irqrestore(&reset->lock, flags); + if (!has_rstst) + return 0; + + /* wait for the status to be set */ + ret = readl_relaxed_poll_timeout(reset->prm->base + + reset->prm->data->rstst, + v, v & BIT(st_bit), 1, + OMAP_RESET_MAX_WAIT); + if (ret) + pr_err("%s: timedout waiting for %s:%lu\n", __func__, + reset->prm->data->name, id); + return 0; } From patchwork Tue Oct 8 12:55:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 175485 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp5662699ill; Tue, 8 Oct 2019 05:56:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqwG4RWkql9yJnRf8tCFWs6qiUVpzKDJ3pr5wV81nIW73jeej/fuowIMBh604Qox4wyGyquY X-Received: by 2002:a17:906:95cf:: with SMTP id n15mr28558415ejy.183.1570539369025; Tue, 08 Oct 2019 05:56:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570539369; cv=none; d=google.com; s=arc-20160816; b=hePnX24eKTY2AXS23iOgB9KBf99tfp2p9Sal80HRhilQMVfFZZIEHrZfp1cHYzXAdA ajMqJfeUzOXmyYMdEpfv3JetYaxTPLxQvK0LlNaCLsedlEvkONoCV8Ff5eAsLjw5WjTH 95F4iQ/PbI8NPjFWIYt0R6d9SIBU6Ghz9sT8JNUQnwGMrkbgt3CXN7arz8fEpKT/fWZT EYYrOQ5bxaP0alvwgLMSE64vJg+eqpcr8OvrBwOJeaBwChXOeWMj1CTTdTof6A3kBVdW rRccGRhR4DcJGoGfqnaquWtcw+PWEMFDds6QtwiKg5ZjrUsjpcD3jO7KYKnrQeZhULzf auew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=0tln0NRFdBItHIltiQcebxGnUnAgfgYhStbd62D0/jM=; b=MYGByx2FS+RyI56dEWcQRjoIx8sdGPn1PFMSeDxm2QdRSd7XaNOn4o1AOjPv9XdS1A nsLo5uSfZY9D7U2eu+VqmP1tzW6dty0lj6Hf7zyagp0huqMfh5deEWFwsq/OSNx87e/C 8LmouzZQPbJe+ZJNHp+BYxNEZ3hnob9v8yrfgaQMXG8qNz747AqPqmjG4KNuheq7IoWx 0Xio1y2qjb7waGbsqPuxyl8l5EwfslWZ4XoRlDkJSUkjFBi3+W+kQO4m9WQHWIzaTulo IGfGsMpmalbEfXfHTSHzh/ql1bC0LFClhLUhbI8ROg/RUXiWZH/Cjv5/0SVOvYh6BODs hDWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=j3B7Mmrc; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g5si10344318edb.324.2019.10.08.05.56.08; Tue, 08 Oct 2019 05:56:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=j3B7Mmrc; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730958AbfJHM4F (ORCPT + 8 others); Tue, 8 Oct 2019 08:56:05 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:52458 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730915AbfJHM4F (ORCPT ); Tue, 8 Oct 2019 08:56:05 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x98CtvRK068248; Tue, 8 Oct 2019 07:55:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1570539357; bh=0tln0NRFdBItHIltiQcebxGnUnAgfgYhStbd62D0/jM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=j3B7Mmrc2hm6LY+Jg1ZdhZ8GstURcnTriZXoOLFEzkWhiju3n49A5orRlffcSbzDj gPcTHPj9O0PuqNwXcWTPenfFAuCVrfL0YJV9QugsYVwNSQdMYNVw21OjeEGn5Q1rO7 QpgEMs3nMOuDiSRT5I242SDpq4EzJ8bRCJwq3Nq0= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x98Ctv4C010029 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Oct 2019 07:55:57 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 8 Oct 2019 07:55:56 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 8 Oct 2019 07:55:56 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x98Ctk5B046741; Tue, 8 Oct 2019 07:55:55 -0500 From: Tero Kristo To: , CC: , , , , Subject: [PATCHv8 4/9] soc: ti: omap-prm: add support for denying idle for reset clockdomain Date: Tue, 8 Oct 2019 15:55:39 +0300 Message-ID: <20191008125544.20679-5-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191008125544.20679-1-t-kristo@ti.com> References: <20191008125544.20679-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org TI SoCs hardware reset signals require the parent clockdomain to be in force wakeup mode while de-asserting the reset, otherwise it may never complete. To support this, add pdata hooks to control the clockdomain directly. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 36 ++++++++++++++++++++++++++-- include/linux/platform_data/ti-prm.h | 21 ++++++++++++++++ 2 files changed, 55 insertions(+), 2 deletions(-) create mode 100644 include/linux/platform_data/ti-prm.h -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index 96fa2aad9b93..3d9393ff67e3 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -16,6 +16,8 @@ #include #include +#include + struct omap_rst_map { s8 rst; s8 st; @@ -24,6 +26,7 @@ struct omap_rst_map { struct omap_prm_data { u32 base; const char *name; + const char *clkdm_name; u16 rstctrl; u16 rstst; const struct omap_rst_map *rstmap; @@ -40,6 +43,8 @@ struct omap_reset_data { struct omap_prm *prm; u32 mask; spinlock_t lock; + struct clockdomain *clkdm; + struct device *dev; }; #define to_omap_reset_data(p) container_of((p), struct omap_reset_data, rcdev) @@ -49,6 +54,7 @@ struct omap_reset_data { #define OMAP_PRM_HAS_RSTCTRL BIT(0) #define OMAP_PRM_HAS_RSTST BIT(1) +#define OMAP_PRM_HAS_NO_CLKDM BIT(2) #define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST) @@ -133,6 +139,8 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, int st_bit; bool has_rstst; unsigned long flags; + struct ti_prm_platform_data *pdata = dev_get_platdata(reset->dev); + int ret = 0; has_rstst = reset->prm->data->rstst || (reset->prm->data->flags & OMAP_PRM_HAS_RSTST); @@ -146,6 +154,9 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, writel_relaxed(v, reset->prm->base + reset->prm->data->rstst); } + if (reset->clkdm) + pdata->clkdm_deny_idle(reset->clkdm); + /* de-assert the reset control line */ spin_lock_irqsave(&reset->lock, flags); v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); @@ -154,7 +165,7 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, spin_unlock_irqrestore(&reset->lock, flags); if (!has_rstst) - return 0; + goto exit; /* wait for the status to be set */ ret = readl_relaxed_poll_timeout(reset->prm->base + @@ -165,7 +176,11 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, pr_err("%s: timedout waiting for %s:%lu\n", __func__, reset->prm->data->name, id); - return 0; +exit: + if (reset->clkdm) + pdata->clkdm_allow_idle(reset->clkdm); + + return ret; } static const struct reset_control_ops omap_reset_ops = { @@ -190,6 +205,8 @@ static int omap_prm_reset_init(struct platform_device *pdev, { struct omap_reset_data *reset; const struct omap_rst_map *map; + struct ti_prm_platform_data *pdata = dev_get_platdata(&pdev->dev); + char buf[32]; /* * Check if we have controllable resets. If either rstctrl is non-zero @@ -199,6 +216,11 @@ static int omap_prm_reset_init(struct platform_device *pdev, if (!prm->data->rstctrl && !(prm->data->flags & OMAP_PRM_HAS_RSTCTRL)) return 0; + /* Check if we have the pdata callbacks in place */ + if (!pdata || !pdata->clkdm_lookup || !pdata->clkdm_deny_idle || + !pdata->clkdm_allow_idle) + return -EINVAL; + map = prm->data->rstmap; if (!map) return -EINVAL; @@ -213,10 +235,20 @@ static int omap_prm_reset_init(struct platform_device *pdev, reset->rcdev.nr_resets = OMAP_MAX_RESETS; reset->rcdev.of_xlate = omap_prm_reset_xlate; reset->rcdev.of_reset_n_cells = 1; + reset->dev = &pdev->dev; spin_lock_init(&reset->lock); reset->prm = prm; + sprintf(buf, "%s_clkdm", prm->data->clkdm_name ? prm->data->clkdm_name : + prm->data->name); + + if (!(prm->data->flags & OMAP_PRM_HAS_NO_CLKDM)) { + reset->clkdm = pdata->clkdm_lookup(buf); + if (!reset->clkdm) + return -EINVAL; + } + while (map->rst >= 0) { reset->mask |= BIT(map->rst); map++; diff --git a/include/linux/platform_data/ti-prm.h b/include/linux/platform_data/ti-prm.h new file mode 100644 index 000000000000..28154c3226c2 --- /dev/null +++ b/include/linux/platform_data/ti-prm.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * TI PRM (Power & Reset Manager) platform data + * + * Copyright (C) 2019 Texas Instruments, Inc. + * + * Tero Kristo + */ + +#ifndef _LINUX_PLATFORM_DATA_TI_PRM_H +#define _LINUX_PLATFORM_DATA_TI_PRM_H + +struct clockdomain; + +struct ti_prm_platform_data { + void (*clkdm_deny_idle)(struct clockdomain *clkdm); + void (*clkdm_allow_idle)(struct clockdomain *clkdm); + struct clockdomain * (*clkdm_lookup)(const char *name); +}; + +#endif /* _LINUX_PLATFORM_DATA_TI_PRM_H */ From patchwork Tue Oct 8 12:55:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 175488 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp5662759ill; Tue, 8 Oct 2019 05:56:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqyUjXiz7oy3rl25pDyq0i8G/p3zEIqdd5bCe1N4lUWfkvI/ml6E9llIwjYznyKrHwGJ+FJo X-Received: by 2002:a50:aa96:: with SMTP id q22mr33702899edc.179.1570539371467; Tue, 08 Oct 2019 05:56:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570539371; cv=none; d=google.com; s=arc-20160816; b=Cq1VPZBkQFQRWGTXrC4c2o/60smMt2dlhcd++5Cb2TxO4mQKVDYJnvUSLFe108XbYP 7eIOy/5geFLhtYh7cXXp3/7GfNKIErknNh26K6phn3DwxBW+qauaBMwfFRRs6Ylqf1fu jGqEufzmJC331DkZ/gDOBDojUowsFCYfCnpmZH1+89MzQZPLFWiJZwUc/b0YNypTF5Ec pehXxyJByGtahwSLNQUwk/Kef6h9s6fs6MEE5dNyBfikxpkujJakEZu6dp66Y+ivXdRP h/yheCI//lU+mHUvUcOSopnxomx30rXNmL13f7FcNNsXnXcxhZAuOejDke4UTImVm/Zl mikw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=pt9ZUil/2B5wcm+TkD0BrIf3fmHoBR66aLscI2ljxIs=; b=Wp64ZlAHHn5CU3tpHDUlmh3XM1SsalkAr43GzuyHMkIrg1el/GtNAO00gCVT7vg69A 7K40a4i8uUbC2buHTUfDVl9SccIpAqvLfOXDLCY03/kSV5DaB9gBn1ZS3/EvMlAu+Wtg bbYkcw6W+KaSfOuO+sTXfN8zgYtyizq9hb6kBxpgxmYzu7PLENd4sgZr6DLnISz9Orki spwii7qtTGdJZ1P+WVJyK1p+h1N7UY2rLq20SduubzInu/01yqjvrGSwCZIg6PohX+0V fXT0M2kTzxIRE5gfrwzu8MS1GQm/4AQXS+2X7PYajARIR2jm+d8Ac++1UGP+IFRseoez p3XQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ISjQqBPf; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Initially this is just used to provide reset support. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index a5fde34f6afd..de11ce08ff7b 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -84,6 +84,19 @@ static const struct omap_prm_data omap4_prm_data[] = { { }, }; +static const struct omap_prm_data dra7_prm_data[] = { + { .name = "dsp1", .base = 0x4ae06400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "ipu", .base = 0x4ae06500, .rstctrl = 0x10, .rstst = 0x14, .clkdm_name = "ipu1", .rstmap = rst_map_012 }, + { .name = "core", .base = 0x4ae06700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu2", .rstmap = rst_map_012 }, + { .name = "iva", .base = 0x4ae06f00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 }, + { .name = "dsp2", .base = 0x4ae07b00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "eve1", .base = 0x4ae07b40, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "eve2", .base = 0x4ae07b80, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "eve3", .base = 0x4ae07bc0, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "eve4", .base = 0x4ae07c00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { }, +}; + static const struct omap_rst_map am3_per_rst_map[] = { { .rst = 1 }, { .rst = -1 }, @@ -104,6 +117,7 @@ static const struct omap_prm_data am3_prm_data[] = { static const struct of_device_id omap_prm_id_table[] = { { .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data }, + { .compatible = "ti,dra7-prm-inst", .data = dra7_prm_data }, { .compatible = "ti,am3-prm-inst", .data = am3_prm_data }, { }, }; From patchwork Tue Oct 8 12:55:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 175489 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp5662789ill; Tue, 8 Oct 2019 05:56:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqwGgVxTDCiByAdr87ImHIHzDVf7cZYRXOQ1RBmemMnizHMxE78diy3O0slpk/uhqxmaWGIB X-Received: by 2002:aa7:cf86:: with SMTP id z6mr32893230edx.230.1570539372853; Tue, 08 Oct 2019 05:56:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570539372; cv=none; d=google.com; s=arc-20160816; b=vxurFfhdWXyerKMFwLKlJb8dquk0XJSEJMRi66d1V/UtVi7BGSK4boUhFfNM8c6+mR ZqC3MGoE3CJ+cDgR9FQI5zYAQId0c6p1q92QhTiSjOoFYrCWTLeAcFVh2egrrO31PIgQ +yGBJvzqg0gru7+q9muusJDYHfwGMsO7yjGwzzJDKHjtrdL1+mh+Vzv/k3vRhNxwP5IQ Q5ODlOwPh9Wk1SbxG09nBc8hfscLQztFzWKAoqDXhHIMmTy21sKkp5QaUnU+d7GHTQ9j QBmsnGjeq1ji1TWzjgxU8JDh4M5KXUxPYeP3zRxV5w+p9V2Mf7NUMqJlGPAqZxEz+JOQ X+5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=TLJzFaDGrfR7zYUgMJnTM6uHF4H+5qrJ9lcRIUGwjDw=; b=N260DmVKV0Jxa9z1EygNwC4qvsfO0NMWYly48O4vnU+nvQvZR/e0LU/uhiXDHGQX3U bZzl2LpXULltg0IDvTM3Nib0LCISlJ46T+7Fv+/LNNi3GeCXaf+Pf2eXFDgF47DZyWEd ZErbj8dS2Rqjr460IaO+EMNjRuqgtUocIAsP9T8mxZ22HDxgAXv/zHUDxHMJcGqnTNKh 9Z5a1XgBXQj1hoVwk4G61n1FoMW3fTm8w33LLO3jirC84A7Bb/0OleTWoBqDr4VLmS9e GtcLnuAN6v/08DJwdYtUm8VlMxcZ3GrHuBHQhw02i1ApAdrxymysntI3ckjxxK7HqYkL 2paA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Ue0LmDXn; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Initially this is just used to provide reset support. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index de11ce08ff7b..73ea64896770 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -115,10 +115,30 @@ static const struct omap_prm_data am3_prm_data[] = { { }, }; +static const struct omap_rst_map am4_per_rst_map[] = { + { .rst = 1, .st = 0 }, + { .rst = -1 }, +}; + +static const struct omap_rst_map am4_device_rst_map[] = { + { .rst = 0, .st = 1 }, + { .rst = 1, .st = 0 }, + { .rst = -1 }, +}; + +static const struct omap_prm_data am4_prm_data[] = { + { .name = "gfx", .base = 0x44df0400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3" }, + { .name = "per", .base = 0x44df0800, .rstctrl = 0x10, .rstst = 0x14, .rstmap = am4_per_rst_map, .clkdm_name = "pruss_ocp" }, + { .name = "wkup", .base = 0x44df2000, .rstctrl = 0x10, .rstst = 0x14, .rstmap = am3_wkup_rst_map, .flags = OMAP_PRM_HAS_NO_CLKDM }, + { .name = "device", .base = 0x44df4000, .rstctrl = 0x0, .rstst = 0x4, .rstmap = am4_device_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM }, + { }, +}; + static const struct of_device_id omap_prm_id_table[] = { { .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data }, { .compatible = "ti,dra7-prm-inst", .data = dra7_prm_data }, { .compatible = "ti,am3-prm-inst", .data = am3_prm_data }, + { .compatible = "ti,am4-prm-inst", .data = am4_prm_data }, { }, }; From patchwork Tue Oct 8 12:55:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 175490 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp5662847ill; Tue, 8 Oct 2019 05:56:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqy/V0m4+zX1gaiVjFKhDlLAUvA5MdQqqTHB2hP78tg6WXcU3A2aqL0lbRPDAgdjXHtr0OAR X-Received: by 2002:a17:906:8246:: with SMTP id f6mr28829735ejx.179.1570539377198; Tue, 08 Oct 2019 05:56:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570539377; cv=none; d=google.com; s=arc-20160816; b=xGwKxchySiUhQ5a+mGAyzra+f+HTOucweIR0NWeMI01nBDUvOn9Xc4+5vxVAWGUAMk o9hEwqwWE7cPEb/A114LvrIqLB06/8Whzc8Ik81wLZeZasgT/jyCqgEyomZVam6Zf0Bj Jg6LkYwWYvbtn6YCRz5K3x3iXaMEs7X8LPX9u/Zd2PU8uoB8iGTwj5yhEmCVciz7Ci1I gpn3c1wlx9c8Q1pdsJZdFKqwTKWp3WwSQAIP3EkkVftzclXEn3WWb7huvdZl8PDMcb+d g843cR0DDZNnyCdE3Yv6sTeb71pOgWtZPc+P5q5AVmr4Fp6DXwec+FI0fRyZ7jv+OWB1 O0Fg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=fLZbcw5wepXuSeFrsWtd637NuzfIOkB+KDiZWWlKW2M=; b=D8hcS0+5ia8XCZGZOuEo+3hr8RyVeXpuBaR24lN0DEMI3okFWz+1UD9SMxFErMLie6 Jfa1eigDVh36sfE/CczXVldD8vu3eaQe1c0f/fW1A95FjJdb8STx5wVN5Soj1PcLRO7e NqrZUw6oQ1t1/bqdt6IStceLyS/HwWutsOTqprCurj6K9yw1fdrIS0pebXr6K+hQZigy K32Yi2hck6NwkI3tsnMNEQb5VBONBshjipob8WzwgPV3SrIbGiEmBkp5AjgNJtvPXy/V FdVS1SrmoAqpP3tUMflBqz4FcWN4acbJ/SIrphrVeZKMQLkz26vs+QcCM2wRbS8n4JZg vqjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=nKb+EMpl; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g5si10344318edb.324.2019.10.08.05.56.17; Tue, 08 Oct 2019 05:56:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=nKb+EMpl; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730963AbfJHM4Q (ORCPT + 8 others); Tue, 8 Oct 2019 08:56:16 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:44338 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730670AbfJHM4Q (ORCPT ); Tue, 8 Oct 2019 08:56:16 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x98Cu7VX106632; Tue, 8 Oct 2019 07:56:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1570539367; bh=fLZbcw5wepXuSeFrsWtd637NuzfIOkB+KDiZWWlKW2M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nKb+EMpl73YpbffPEHXneacRz4aEFgQTaZzLlJGXySP2Kc3BNCpDc1I26w459+atd YldPqahkYbo7s1swE6xc8rzNAnK89CauD66rVjplgWKDv1wMv8Y4d3gk5U1X08zuMA oTVUB8SjVRbD+40S4ay5p54IF4SJHE+9c/Jvo8tI= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x98Cu7LK126820 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Oct 2019 07:56:07 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 8 Oct 2019 07:56:06 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 8 Oct 2019 07:56:06 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x98Ctk5G046741; Tue, 8 Oct 2019 07:56:05 -0500 From: Tero Kristo To: , CC: , , , , Subject: [PATCHv8 9/9] soc: ti: omap-prm: add omap5 PRM data Date: Tue, 8 Oct 2019 15:55:44 +0300 Message-ID: <20191008125544.20679-10-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191008125544.20679-1-t-kristo@ti.com> References: <20191008125544.20679-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add PRM instance data for omap5 family of SoCs. Initially this is just used to provide reset support. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index 73ea64896770..38e8704c51ad 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -84,6 +84,14 @@ static const struct omap_prm_data omap4_prm_data[] = { { }, }; +static const struct omap_prm_data omap5_prm_data[] = { + { .name = "dsp", .base = 0x4ae06400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "core", .base = 0x4ae06700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu", .rstmap = rst_map_012 }, + { .name = "iva", .base = 0x4ae07200, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 }, + { .name = "device", .base = 0x4ae07c00, .rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM }, + { }, +}; + static const struct omap_prm_data dra7_prm_data[] = { { .name = "dsp1", .base = 0x4ae06400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, { .name = "ipu", .base = 0x4ae06500, .rstctrl = 0x10, .rstst = 0x14, .clkdm_name = "ipu1", .rstmap = rst_map_012 }, @@ -136,6 +144,7 @@ static const struct omap_prm_data am4_prm_data[] = { static const struct of_device_id omap_prm_id_table[] = { { .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data }, + { .compatible = "ti,omap5-prm-inst", .data = omap5_prm_data }, { .compatible = "ti,dra7-prm-inst", .data = dra7_prm_data }, { .compatible = "ti,am3-prm-inst", .data = am3_prm_data }, { .compatible = "ti,am4-prm-inst", .data = am4_prm_data },