From patchwork Tue Jun 13 14:06:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 105356 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp431958qgd; Tue, 13 Jun 2017 07:23:59 -0700 (PDT) X-Received: by 10.55.98.17 with SMTP id w17mr159847qkb.106.1497363839769; Tue, 13 Jun 2017 07:23:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497363839; cv=none; d=google.com; s=arc-20160816; b=R+8BEVOjDWwPFKZTfnm+N/81iPSPmBdrVJ/DxXgsabUqssKxIuCaZThT6ybu/q1mmn jR6hiEQRqcOHTbhkfkeQ13eO196ZyhP+KqUlaUI5jVzMcHQm1DTD/jBVG2Cgqimsg+LO O0qHBBGPT4x7uX3l+JCDj/8KSwcgnPftmxfnN+srLKTWg/vlStNhMLrP7noV1/VW9ay9 pKp8znnqS467Ohm2tCVeBJojgDrRYqBYZho4dA4d2FDquDcAKbgErSQk04T1ClzMZUHV 7AknC9fAngJd6dUER0ufUFZHTPAerJiimv5LfmUr8chnc3k2NLw0nAIy0u3izd5qMkqT MCag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=GdOt0m2LQz5Q0AX2C4jabU/jRlLGlPk65c1RsOWnw/I=; b=tNR9tCYFovghuw/bAYGTB5eN0VeX3qowQfcqZSsIYgu1gUkOMzhc0P6SX/nHexQQjS AxVuS7mEwJpdL8zV1vaL4u/z2tX6BiyqZ2REIa1X+JSkWo9sdhzefgLkvA9myMyAiOnZ YfYtfMjfXUCJkoBrLCJDUGewz0vZf3C1FLOrU6Jl051Cjs3+5kTcCAWYzXpmo8NbTwd2 7ujctTMii6lwdM5mQ9k/x+dKrJ8AaEJtgpyLxxtwcCll8DlGwRE6rlrHfrrjl2qgZNw0 Awpd6l4jeVDjk+cAJ/8AOV8k/6Kpw2g+6d95ffu0wiZltrWWtbAqKi4K5gjvSOq+bejo 6qYg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id n96si38718qte.216.2017.06.13.07.23.59 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 13 Jun 2017 07:23:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43549 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmjd-00035g-86 for patch@linaro.org; Tue, 13 Jun 2017 10:23:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33129) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmTb-0005Gu-68 for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKmTW-0006f1-C6 for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:23 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37257) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKmTW-0006cz-3n for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:18 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dKmTM-00011D-NP for qemu-devel@nongnu.org; Tue, 13 Jun 2017 15:07:08 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 15:06:50 +0100 Message-Id: <1497362826-21125-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> References: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 01/17] hw/intc/exynos4210_gic: Use more meaningful name for local variable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Krzysztof Kozlowski There are to SysBusDevice variables in exynos4210_gic_realize() function: one for the device itself and second for arm_gic device. Add a prefix "gic" to the second one so it will be easier to understand the code. While at it, put local uninitialized 'i' variable at the end, next to other uninitialized ones. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- hw/intc/exynos4210_gic.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.7.4 diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c index 2a55817..62acede 100644 --- a/hw/intc/exynos4210_gic.c +++ b/hw/intc/exynos4210_gic.c @@ -286,21 +286,21 @@ static void exynos4210_gic_init(Object *obj) DeviceState *dev = DEVICE(obj); Exynos4210GicState *s = EXYNOS4210_GIC(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - uint32_t i; const char cpu_prefix[] = "exynos4210-gic-alias_cpu"; const char dist_prefix[] = "exynos4210-gic-alias_dist"; char cpu_alias_name[sizeof(cpu_prefix) + 3]; char dist_alias_name[sizeof(cpu_prefix) + 3]; - SysBusDevice *busdev; + SysBusDevice *gicbusdev; + uint32_t i; s->gic = qdev_create(NULL, "arm_gic"); qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ); qdev_init_nofail(s->gic); - busdev = SYS_BUS_DEVICE(s->gic); + gicbusdev = SYS_BUS_DEVICE(s->gic); /* Pass through outbound IRQ lines from the GIC */ - sysbus_pass_irq(sbd, busdev); + sysbus_pass_irq(sbd, gicbusdev); /* Pass through inbound GPIO lines to the GIC */ qdev_init_gpio_in(dev, exynos4210_gic_set_irq, @@ -316,7 +316,7 @@ static void exynos4210_gic_init(Object *obj) sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); memory_region_init_alias(&s->cpu_alias[i], obj, cpu_alias_name, - sysbus_mmio_get_region(busdev, 1), + sysbus_mmio_get_region(gicbusdev, 1), 0, EXYNOS4210_GIC_CPU_REGION_SIZE); memory_region_add_subregion(&s->cpu_container, @@ -326,7 +326,7 @@ static void exynos4210_gic_init(Object *obj) sprintf(dist_alias_name, "%s%x", dist_prefix, i); memory_region_init_alias(&s->dist_alias[i], obj, dist_alias_name, - sysbus_mmio_get_region(busdev, 0), + sysbus_mmio_get_region(gicbusdev, 0), 0, EXYNOS4210_GIC_DIST_REGION_SIZE); memory_region_add_subregion(&s->dist_container, From patchwork Tue Jun 13 14:06:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 105368 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp438382qgd; Tue, 13 Jun 2017 07:37:41 -0700 (PDT) X-Received: by 10.223.153.114 with SMTP id x105mr2170984wrb.18.1497364661793; Tue, 13 Jun 2017 07:37:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497364661; cv=none; d=google.com; s=arc-20160816; b=wePAcGU/6w0J3UZOCr1NqLkA9ZgAudCUes3+pjetEGTpY9Vk3xQjZJLLFwoqTyZul6 hoyCOjZd+QNzmJ0FEesiWjVcDcMyGTYgSE682qehNbc9tNzFS4BbwpdsTyumGPSV8Qof kr1VIVdU7OdPpEZm+RRwlYtKdDuWFhG0PoEygehygd4eROl4+K8oCfqM3p83K3f+N+53 eu2WIAOHhTHa+Vo0BcgYBAG4xhpNnwltnFIL1fkOZq0vysxYl7XAM/BUdxuYr57SeX/X ZzQe6rcBal/+JgacqzOwJd025VerIcI4NqWJH9NIG62eKYMxdltMxHZhj+OneA01FAYc Cehg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=uv2xONiX+AH1RnkFuies96sqGbeg/2lO+uoaa6TmVPw=; b=zsi3LWZ+xNGvsI8VtaA4ptgfCKmSFoFu92LSA0MIoT/9BKabzSKrf121k95/jXO+hB VnRlgD4wavMmWNUhAfo2fT7gbw/Q9vTIqai0FJjbL5ZWXwSs7UnQ4Toito5YwEe0udEI ROBdPtSjeCfZ15jFHGfEqri7XYBYWOH6dN+5XXLW1NqhO4TVy87vviz3rzgDEMpAFWaF xA+yT4m0FycfTlpGDDlygB/X1rTfPqbchCQUcuNjHkjeUCKmqXc7I34uU32kwDIBToWZ GunnBsMuRfwR0ZAVUqB1lTqlu/XnqNylRMegz4MetY+JcJ+t7Y7LFUQZkK2s/+fKGFlh yp5g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id k10si113506wrc.86.2017.06.13.07.37.41 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 13 Jun 2017 07:37:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43643 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmwu-00044P-Kn for patch@linaro.org; Tue, 13 Jun 2017 10:37:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33272) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmTh-0005NC-D2 for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKmTf-0006lD-5g for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:29 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37257) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKmTe-0006cz-Tr for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:27 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dKmTN-00011R-El for qemu-devel@nongnu.org; Tue, 13 Jun 2017 15:07:09 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 15:06:51 +0100 Message-Id: <1497362826-21125-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> References: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 02/17] hw/timer/exynos4210_mct: Fix checkpatch style errors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Krzysztof Kozlowski Fix checkpatch errors: 1. ERROR: spaces required around that '+' (ctx:VxV) 2. ERROR: spaces required around that '&' (ctx:VxV) No functional changes. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- hw/timer/exynos4210_mct.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c index a2ec392..2404fb7 100644 --- a/hw/timer/exynos4210_mct.c +++ b/hw/timer/exynos4210_mct.c @@ -937,7 +937,7 @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s) { uint32_t freq = s->freq; s->freq = 24000000 / - ((MCT_CFG_GET_PRESCALER(s->reg_mct_cfg)+1) * + ((MCT_CFG_GET_PRESCALER(s->reg_mct_cfg) + 1) * MCT_CFG_GET_DIVIDER(s->reg_mct_cfg)); if (freq != s->freq) { @@ -1162,7 +1162,7 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift); - if (offset&0x4) { + if (offset & 0x4) { s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index); } else { s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index); From patchwork Tue Jun 13 14:06:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 105365 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp436504qgd; Tue, 13 Jun 2017 07:33:30 -0700 (PDT) X-Received: by 10.55.17.138 with SMTP id 10mr197801qkr.244.1497364410199; Tue, 13 Jun 2017 07:33:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497364410; cv=none; d=google.com; s=arc-20160816; b=G82vAwsAvjAck+oT1RE+9LtWWzl7n1s+O5sYirlUEqDqqZBzibzw8Dkd1sFNmyEbwJ ymUdbUQBzjZs5nlEBXJzwnsaOCs92NJHt2WBtEhji4kRS/GuRJZJO0JSHU83slnxV0Mz QCpC7+C1T5GrF2DD60ged8azWoD4vaWPXb1kJc1wZbwQvwEP1VKNkaNEHplKpIRg59HQ ZPw/7nOz+9JQcY6ixtsl5zi52Fu8WH4EbTBPUUF6ENkzQ6jQFhvVdmQqglZlpzyVmx4k UwYlFFPCA/BeZUwGdxTI8PS7cAJgz96h8RQoEy8YQ013JbfzO6l0gtCMxwukjZxHHM91 m3Pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=BazycaOkXhgkG6jnz2ywI2M9FeeZVKrAkqBIBH7R8Pg=; b=s0+QOoE9PE3M+PEgfyOedHVK7yEyk7FMRXG0/1NzvnKhUiPcg5eG3UIeqpzsPkm+W+ JSFLPQziD4OrV62vAjie8N1MY3FWQgbeQtm/poSP71haQ43uAPlWGLneSOrEBeiWU1rJ vr3Tx0BIjUxKCOfe53Gl61/IQQR91GphKyO8Pl3lzOBWLBQ2Be1bjQlzr7nbk/cdrTHY aEGj/pOjnhFYNEYCDj04hWtDHaZwoxa0xzaaKyEzZbFwjVyZjAIDu9R65Z0sn2OKb7KL ZvhvDrov3R67ftJvNGl7CJFb67je3ULeUYn8p6Elt5XMO92/B1qM9N3vt1WBdSqXtfkB Xk/Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id b37si55211qtc.320.2017.06.13.07.33.29 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 13 Jun 2017 07:33:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43609 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmsp-00081r-Jm for patch@linaro.org; Tue, 13 Jun 2017 10:33:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33237) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmTf-0005LJ-FQ for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKmTe-0006kk-74 for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:27 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37257) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKmTd-0006cz-V3 for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:26 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dKmTO-000123-3f for qemu-devel@nongnu.org; Tue, 13 Jun 2017 15:07:10 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 15:06:52 +0100 Message-Id: <1497362826-21125-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> References: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 03/17] hw/timer/exynos4210_mct: Cleanup indentation and empty new lines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Krzysztof Kozlowski Statements under 'case' were in some places wrongly indented bringing confusion and making the code less readable. Remove also few unneeded blank lines. No functional changes. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- hw/timer/exynos4210_mct.c | 45 ++++++++++++++++++++------------------------- 1 file changed, 20 insertions(+), 25 deletions(-) -- 2.7.4 diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c index 2404fb7..ea5f99d 100644 --- a/hw/timer/exynos4210_mct.c +++ b/hw/timer/exynos4210_mct.c @@ -1016,9 +1016,9 @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset, case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3): case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3): - index = GET_G_COMP_IDX(offset); - shift = 8 * (offset & 0x4); - value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift); + index = GET_G_COMP_IDX(offset); + shift = 8 * (offset & 0x4); + value = UINT32_MAX & (s->g_timer.reg.comp[index] >> shift); break; case G_TCON: @@ -1067,7 +1067,6 @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset, lt_i = GET_L_TIMER_IDX(offset); value = exynos4210_lfrc_get_count(&s->l_timer[lt_i]); - break; case L0_TCON: case L1_TCON: @@ -1153,23 +1152,23 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3): case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3): - index = GET_G_COMP_IDX(offset); - shift = 8 * (offset & 0x4); - s->g_timer.reg.comp[index] = - (s->g_timer.reg.comp[index] & - (((uint64_t)UINT32_MAX << 32) >> shift)) + - (value << shift); + index = GET_G_COMP_IDX(offset); + shift = 8 * (offset & 0x4); + s->g_timer.reg.comp[index] = + (s->g_timer.reg.comp[index] & + (((uint64_t)UINT32_MAX << 32) >> shift)) + + (value << shift); - DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift); + DPRINTF("comparator %d write 0x%llx val << %d\n", index, value, shift); - if (offset & 0x4) { - s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index); - } else { - s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index); - } + if (offset & 0x4) { + s->g_timer.reg.wstat |= G_WSTAT_COMP_U(index); + } else { + s->g_timer.reg.wstat |= G_WSTAT_COMP_L(index); + } - exynos4210_gfrc_restart(s); - break; + exynos4210_gfrc_restart(s); + break; case G_TCON: old_val = s->g_timer.reg.tcon; @@ -1207,7 +1206,6 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, break; case G_INT_ENB: - /* Raise IRQ if transition from disabled to enabled and CSTAT pending */ for (i = 0; i < MCT_GT_CMP_NUM; i++) { if ((value & G_INT_ENABLE(i)) > (s->g_timer.reg.tcon & @@ -1288,7 +1286,6 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, break; case L0_TCNTB: case L1_TCNTB: - lt_i = GET_L_TIMER_IDX(offset); index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i); @@ -1316,7 +1313,6 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, break; case L0_ICNTB: case L1_ICNTB: - lt_i = GET_L_TIMER_IDX(offset); index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i); @@ -1353,13 +1349,12 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, if (icntb_max[lt_i] < value) { icntb_max[lt_i] = value; } -DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n", - lt_i, value, icntb_max[lt_i], icntb_min[lt_i]); + DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n", + lt_i, value, icntb_max[lt_i], icntb_min[lt_i]); #endif -break; + break; case L0_FRCNTB: case L1_FRCNTB: - lt_i = GET_L_TIMER_IDX(offset); index = GET_L_TIMER_CNT_REG_IDX(offset, lt_i); From patchwork Tue Jun 13 14:06:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 105359 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp433054qgd; Tue, 13 Jun 2017 07:26:33 -0700 (PDT) X-Received: by 10.200.43.221 with SMTP id n29mr177318qtn.190.1497363993883; Tue, 13 Jun 2017 07:26:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497363993; cv=none; d=google.com; s=arc-20160816; b=fxNjlm9k1Ys6j3+EdXNvmYvP+zaJ5oFzGlSOBJ+CDJ2KtGsk+h3tIHxbKTgtrvTvCe Y5F1IYZ92poRiDPnqhB8/UNSu8MzsuFQtKlBNFaYEqt1ghKmNlPAIEVPerrCTwNvPOvL ItSJXQfwChYgDQxEhzkfP2pKO7KUqSQ4xiD1bTdNCOF3/k9UcBO+9JW4/Qx13s5L8GRY 9vLFOmvXB8Eqa5swxvgZhKVFLCG7203MmkJNBO20jJFKOz93k6ugJsDVZ/T8HJKuIIVt BZg3fnuK1HoR1siWvXSyTBxczvPDHLntgxMmR44F/sdGPwhfQjvMqMO+6AbOQOX567zy WM9Q== ARC-Message-Signature: i=1; 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[208.118.235.17]) by mx.google.com with ESMTPS id c199si65587qke.42.2017.06.13.07.26.33 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 13 Jun 2017 07:26:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43576 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmm7-0000o9-Fv for patch@linaro.org; Tue, 13 Jun 2017 10:26:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33284) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmTi-0005O7-5W for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKmTd-0006kP-HL for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:30 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37258) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKmTd-0006fN-9Q for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:25 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dKmTO-00012Q-Nq for qemu-devel@nongnu.org; Tue, 13 Jun 2017 15:07:10 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 15:06:53 +0100 Message-Id: <1497362826-21125-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> References: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 04/17] hw/timer/exynos4210_mct: Remove unused defines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Krzysztof Kozlowski Remove defines not used anywhere. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/timer/exynos4210_mct.c | 3 --- 1 file changed, 3 deletions(-) -- 2.7.4 diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c index ea5f99d..e4ef4cf 100644 --- a/hw/timer/exynos4210_mct.c +++ b/hw/timer/exynos4210_mct.c @@ -173,13 +173,10 @@ enum LocalTimerRegCntIndexes { L_REG_CNT_AMOUNT }; -#define MCT_NIRQ 6 #define MCT_SFR_SIZE 0x444 #define MCT_GT_CMP_NUM 4 -#define MCT_GT_MAX_VAL UINT64_MAX - #define MCT_GT_COUNTER_STEP 0x100000000ULL #define MCT_LT_COUNTER_STEP 0x100000000ULL #define MCT_LT_CNT_LOW_LIMIT 0x100 From patchwork Tue Jun 13 14:06:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 105363 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp435603qgd; Tue, 13 Jun 2017 07:31:42 -0700 (PDT) X-Received: by 10.80.208.2 with SMTP id j2mr87270edf.115.1497364302496; Tue, 13 Jun 2017 07:31:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497364302; cv=none; d=google.com; s=arc-20160816; b=gyb+WW00RIx7COqMuuQ/P27dwcssXoa0LYrVbTDOFSoD0Pi0ofUwWH2eexRPztWdMn lCqU1LYYqiTbXeLLmdsAz0sfybrXqJMkLBaCeBDNyBG96w2eWfT8XpYcPDf4PRGzHuEA omNn7aoNiDFthYN1gWNnui3SViuFaeqKwUVqvwMJjlcbfEzCI6VCezLcoSmRzMNApdKd +TBNWaQLOAXG0+WA56t2CywiWX2hB36YfjasvYaPpLFE1suGjLOOwltSSk47hi9/+7BZ Ji+ZFBiaD/6YovsHYzYfFZUvX0Uj0w5ig7DpDfSoHuFBK0LUftSt9eDpTBV54bO+JjJi ILbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=pgFz4+2s2EG1iAKVf+eZ1NX1wn3yxIJ3xCwAMrlLC1c=; b=R7TFtzSKsDJgXG6tvY8YDzgHLG7pyglIAAHLpoyUkdTee6S787CPLhD/u24hydmH0Z 9r7+9CYqEI0t9inlOaVqwZ8lWCZ0h90F+T11Q79oeKkmrNVM91g+INcZvN+c4UqIHOLF 4UYPsE7/QIHTNzHZOBfAsDZSgqAdk4NLRQGKsxqbWGgbjN3k6a99l471Ah+kphpCUERj iqNNl11P/zcB0G2voBE6kezFueBImWw+ToY24AyDVgII7g2vVDtXG1CXG/v33kAxygpM XLuKJ/JZqeKAnTxnmspw1ox0NU8tzmEtpQt5XKcKht0IW0/ytNDVOfThEAT+dodFaC65 j7yg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id l26si45711edj.227.2017.06.13.07.31.42 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 13 Jun 2017 07:31:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43603 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmr7-0005w6-7u for patch@linaro.org; Tue, 13 Jun 2017 10:31:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33215) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmTe-0005KM-Ju for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKmTd-0006kE-8M for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:26 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37257) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKmTc-0006cz-W9 for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:25 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dKmTP-00012e-GU for qemu-devel@nongnu.org; Tue, 13 Jun 2017 15:07:11 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 15:06:54 +0100 Message-Id: <1497362826-21125-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> References: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 05/17] hw/arm/exynos: Move DRAM initialization next boards X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Krzysztof Kozlowski Before QOM-ifying the Exynos4 SoC model, move the DRAM initialization from exynos4210.c to exynos4_boards.c because DRAM is board specific, not SoC. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- include/hw/arm/exynos4210.h | 5 +---- hw/arm/exynos4210.c | 20 +----------------- hw/arm/exynos4_boards.c | 50 ++++++++++++++++++++++++++++++++++++++------- 3 files changed, 45 insertions(+), 30 deletions(-) -- 2.7.4 diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index d9e0801..098a69e 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -93,8 +93,6 @@ typedef struct Exynos4210State { MemoryRegion iram_mem; MemoryRegion irom_mem; MemoryRegion irom_alias_mem; - MemoryRegion dram0_mem; - MemoryRegion dram1_mem; MemoryRegion boot_secondary; MemoryRegion bootreg_mem; I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; @@ -103,8 +101,7 @@ typedef struct Exynos4210State { void exynos4210_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info); -Exynos4210State *exynos4210_init(MemoryRegion *system_mem, - unsigned long ram_size); +Exynos4210State *exynos4210_init(MemoryRegion *system_mem); /* Initialize exynos4210 IRQ subsystem stub */ qemu_irq *exynos4210_init_irq(Exynos4210Irq *env); diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 960f27e..0da877f 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -160,13 +160,11 @@ static uint64_t exynos4210_calc_affinity(int cpu) return mp_affinity; } -Exynos4210State *exynos4210_init(MemoryRegion *system_mem, - unsigned long ram_size) +Exynos4210State *exynos4210_init(MemoryRegion *system_mem) { int i, n; Exynos4210State *s = g_new(Exynos4210State, 1); qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; - unsigned long mem_size; DeviceState *dev; SysBusDevice *busdev; ObjectClass *cpu_oc; @@ -299,22 +297,6 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem, memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, &s->iram_mem); - /* DRAM */ - mem_size = ram_size; - if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) { - memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1", - mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_fatal); - vmstate_register_ram_global(&s->dram1_mem); - memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR, - &s->dram1_mem); - mem_size = EXYNOS4210_DRAM_MAX_SIZE; - } - memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size, - &error_fatal); - vmstate_register_ram_global(&s->dram0_mem); - memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, - &s->dram0_mem); - /* PMU. * The only reason of existence at the moment is that secondary CPU boot * loader uses PMU INFORM5 register as a holding pen. diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index 4853c31..6240b26 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -22,6 +22,7 @@ */ #include "qemu/osdep.h" +#include "qapi/error.h" #include "qemu/error-report.h" #include "qemu-common.h" #include "cpu.h" @@ -56,6 +57,12 @@ typedef enum Exynos4BoardType { EXYNOS4_NUM_OF_BOARDS } Exynos4BoardType; +typedef struct Exynos4BoardState { + Exynos4210State *soc; + MemoryRegion dram0_mem; + MemoryRegion dram1_mem; +} Exynos4BoardState; + static int exynos4_board_id[EXYNOS4_NUM_OF_BOARDS] = { [EXYNOS4_BOARD_NURI] = 0xD33, [EXYNOS4_BOARD_SMDKC210] = 0xB16, @@ -96,9 +103,34 @@ static void lan9215_init(uint32_t base, qemu_irq irq) } } -static Exynos4210State *exynos4_boards_init_common(MachineState *machine, - Exynos4BoardType board_type) +static void exynos4_boards_init_ram(Exynos4BoardState *s, + MemoryRegion *system_mem, + unsigned long ram_size) +{ + unsigned long mem_size = ram_size; + + if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) { + memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1", + mem_size - EXYNOS4210_DRAM_MAX_SIZE, + &error_fatal); + vmstate_register_ram_global(&s->dram1_mem); + memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR, + &s->dram1_mem); + mem_size = EXYNOS4210_DRAM_MAX_SIZE; + } + + memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size, + &error_fatal); + vmstate_register_ram_global(&s->dram0_mem); + memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, + &s->dram0_mem); +} + +static Exynos4BoardState * +exynos4_boards_init_common(MachineState *machine, + Exynos4BoardType board_type) { + Exynos4BoardState *s = g_new(Exynos4BoardState, 1); MachineClass *mc = MACHINE_GET_CLASS(machine); if (smp_cpus != EXYNOS4210_NCPUS && !qtest_enabled()) { @@ -127,8 +159,12 @@ static Exynos4210State *exynos4_boards_init_common(MachineState *machine, machine->kernel_cmdline, machine->initrd_filename); - return exynos4210_init(get_system_memory(), - exynos4_board_ram_size[board_type]); + exynos4_boards_init_ram(s, get_system_memory(), + exynos4_board_ram_size[board_type]); + + s->soc = exynos4210_init(get_system_memory()); + + return s; } static void nuri_init(MachineState *machine) @@ -140,11 +176,11 @@ static void nuri_init(MachineState *machine) static void smdkc210_init(MachineState *machine) { - Exynos4210State *s = exynos4_boards_init_common(machine, - EXYNOS4_BOARD_SMDKC210); + Exynos4BoardState *s = exynos4_boards_init_common(machine, + EXYNOS4_BOARD_SMDKC210); lan9215_init(SMDK_LAN9118_BASE_ADDR, - qemu_irq_invert(s->irq_table[exynos4210_get_irq(37, 1)])); + qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)])); arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo); } From patchwork Tue Jun 13 14:06:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 105370 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp439862qgd; Tue, 13 Jun 2017 07:41:00 -0700 (PDT) X-Received: by 10.200.49.147 with SMTP id h19mr275099qte.176.1497364860082; Tue, 13 Jun 2017 07:41:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497364860; cv=none; d=google.com; s=arc-20160816; b=lCpyWzNNeqKOICHvEktzHWT5daYOfWbSnfgdMkdkbnAWgZmg82te0DyMoY9mRl74fh UV3mCq+09cTaWFwedKeLz0i9i8yr/UkkOXWZJukNsHZsFC04GeSbnk+gRRYypI6LSVld 9Xze04sRg3J3Gf6QND9qHyWgazgPgAUdqEb+0HraXZyiON3TtLgOv/of4nVjcd5oxkSh MxIaeNJlzukM+uQvJzbJPbUTa+qGVGkqUHIQafbDRUNul9ldS4zI8SO1jVrqIQ7/q/l/ QXgigPsVLvG9seqtyQVz2R5f3uvUFOkURA33C4zkaek0I/TmO8EZDKUE2MpXFfJBOG/f a7EQ== ARC-Message-Signature: i=1; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id w6si74085qtb.322.2017.06.13.07.40.59 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 13 Jun 2017 07:41:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43659 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKn05-0006Vr-OV for patch@linaro.org; Tue, 13 Jun 2017 10:40:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33185) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmTd-0005JF-GM for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKmTc-0006ie-J5 for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:25 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37258) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKmTc-0006fN-CB for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:24 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dKmTQ-00012s-5B for qemu-devel@nongnu.org; Tue, 13 Jun 2017 15:07:12 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 15:06:55 +0100 Message-Id: <1497362826-21125-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> References: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 06/17] hw/arm/exynos: Declare local variables in some order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Krzysztof Kozlowski Bring some more readability by declaring local function variables: first initialized ones and then the rest (with reversed-christmas-tree order). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- hw/arm/exynos4210.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 0da877f..27a7bf2 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -162,12 +162,12 @@ static uint64_t exynos4210_calc_affinity(int cpu) Exynos4210State *exynos4210_init(MemoryRegion *system_mem) { - int i, n; Exynos4210State *s = g_new(Exynos4210State, 1); qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; - DeviceState *dev; SysBusDevice *busdev; ObjectClass *cpu_oc; + DeviceState *dev; + int i, n; cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9"); assert(cpu_oc); From patchwork Tue Jun 13 14:06:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 105371 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp439948qgd; Tue, 13 Jun 2017 07:41:11 -0700 (PDT) X-Received: by 10.55.221.220 with SMTP id u89mr246234qku.236.1497364871378; Tue, 13 Jun 2017 07:41:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497364871; cv=none; d=google.com; s=arc-20160816; b=ZW0dAShuxzJ5ugQweFvQtJaD1sYOoRAbKrQDoWszfW/zQ68zYQ4cg2e5zOqgamyfZp fLtmHs8xqyeX/C93W2lIaK8APA6riTVVfv8BtSMCF36popZZrR/nyg2ixIH4k0IDLk3E WGBYPQAxhVZvG8HrVs7aRLB8RFBCibthjGeETQuDH6/aUnJP4yTR1nG3saAiGV+6lqSc pjDmUNESsyYBIj5mReVnVHAyIJApMltSIutMkqJaInjwZKAJkPIi9Ods8eKA+OjEEPZn XLBYZaqpZ/C4iHBYnRW8AfOkWBG+MCd/PkoltnKp+g6YTno52ux3E30UIky84bkUhEuk 8ioA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=orxIsyuQkY9mZODw8/6bo+fX7GYlT8ZbfMmeJo1Pv9g=; b=oLGCDHNoW4jv74OAdLt+xm5q23DLMl0qjTHrxlrAkdZ/dm4reeTuqNt+hPQIB8Rsgw h3SpOb/OG95pjWw/JJ4MSpjSPiI86HSQAdUkBGkr7L2z2Ztz+aW+R2zld06TygypIrkt DAooKQiwvCOPjenpaD9rNwbonJhBliM4TDdii5bayjJ3HOS0gcQBIcL8/Oeivxcmad9J R0WKdLNLo54llG5m4x7WgFr78GNNxpB5Zu+GWreOmdqBXVKeCz4Cq/b0C2ifW1mZyJBQ /mtv4dw/gM3rFKg00r2mVDvYFdAHpFdcV41J2l0aq3wdp8mKUBue+5xmAAWeHmFsaEbK zy6w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id i31si86252qtc.198.2017.06.13.07.41.11 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 13 Jun 2017 07:41:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43660 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKn0H-0006nN-3T for patch@linaro.org; Tue, 13 Jun 2017 10:41:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33298) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmTl-0005Q5-J6 for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKmTc-0006iM-9c for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:33 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37257) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKmTc-0006cz-2E for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:24 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dKmTQ-000136-Ox for qemu-devel@nongnu.org; Tue, 13 Jun 2017 15:07:12 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 15:06:56 +0100 Message-Id: <1497362826-21125-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> References: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 07/17] hw/arm/exynos: Use type define instead of hard-coded a9mpcore_priv string X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Krzysztof Kozlowski Use a define for a9mpcore_priv device type name instead of hard-coded string. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- hw/arm/exynos4210.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 27a7bf2..0050626 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -26,6 +26,7 @@ #include "qemu-common.h" #include "qemu/log.h" #include "cpu.h" +#include "hw/cpu/a9mpcore.h" #include "hw/boards.h" #include "sysemu/sysemu.h" #include "hw/sysbus.h" @@ -211,7 +212,7 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem) } /* Private memory region and Internal GIC */ - dev = qdev_create(NULL, "a9mpcore_priv"); + dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); qdev_init_nofail(dev); busdev = SYS_BUS_DEVICE(dev); From patchwork Tue Jun 13 14:06:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 105366 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp436950qgd; Tue, 13 Jun 2017 07:34:28 -0700 (PDT) X-Received: by 10.55.15.9 with SMTP id z9mr19708533qkg.195.1497364468537; Tue, 13 Jun 2017 07:34:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497364468; cv=none; d=google.com; s=arc-20160816; b=aixgTBPdiKTCcqWzYkh61W7r7veXDLy9f6XJ7zLW48ZjI2UoxAK83+2bBIDL4cB1E5 Rc2JylGRYn/ZbVoWPYhr2k4T9dSXLK67WsIq3lWe3+Whf0+ycVAx85ABZYNrnKLDZdEn Er1kX0grwcyl5yIWgJqYvdd1Z16HybDi+cVe2TE3UvL4D+/It5ck8ULLx9FNYsjvFCwl gc1NVKXVLotS4MOji0bw2PhsXm+FUxjmh4RWA3wUjhUEfUVrNeBacfCVrNFll5aMHcEh ARCaBDVu6YpRq4V4veACdTqzNNSQIueGWi+eWGkW4QQp0QaKAZ7FRhH7GfoCxmMntntU cpQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=oPWrO03rECRuJgmjQTExOdSnWQ/4v35YponjuZf33n8=; b=LCyWtSLrrIbFA7pnfcrpLInUltqdk2829y3p50Z19e7C9KzqX6pYP7sKpM+G7+brsl vEugiWGDH7aTb9C3dL7bAZfzja5b5Brd4HwgHc51mVe3lXbjhR/ooRQnVUkNq3oDqoVv AyoYsHfsCsxNLJazYJrC1HjtTfrduE75A9s+52f2LXFvV9npgDVvC8R9RZMdLn4/HJpB 6SzncQyZ9sEMntIYzYkaf6S2YLJDbx2yFsarhQWLNYqX9MSZmDoXYpEdxmhJZ6eaWLg3 lW5dCl+Y799dLxDOBdgUOEG9nFSb5IGn1iIb6bHaYkSaJVnvtB5F3N78LI1vd6u/q3s9 P9Dw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id i29si83878qtf.132.2017.06.13.07.34.28 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 13 Jun 2017 07:34:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43617 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmtl-0001GQ-Se for patch@linaro.org; Tue, 13 Jun 2017 10:34:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33302) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmTl-0005QF-NF for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKmTb-0006hy-Mk for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:33 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37258) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKmTb-0006fN-Gm for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:23 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dKmTR-00013T-DG for qemu-devel@nongnu.org; Tue, 13 Jun 2017 15:07:13 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 15:06:57 +0100 Message-Id: <1497362826-21125-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> References: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 08/17] hw/intc/exynos4210_gic: Constify array of combiner interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Krzysztof Kozlowski The static array of interrupt combiner mappings is not modified so it can be made const for code safeness. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- hw/intc/exynos4210_gic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c index 62acede..b6b00a4 100644 --- a/hw/intc/exynos4210_gic.c +++ b/hw/intc/exynos4210_gic.c @@ -116,7 +116,7 @@ enum ExtInt { * which is INTG16 in Internal Interrupt Combiner. */ -static uint32_t +static const uint32_t combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = { /* int combiner groups 16-19 */ { }, { }, { }, { }, From patchwork Tue Jun 13 14:06:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 105362 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp434177qgd; Tue, 13 Jun 2017 07:29:11 -0700 (PDT) X-Received: by 10.80.158.99 with SMTP id z90mr100703ede.144.1497364151475; Tue, 13 Jun 2017 07:29:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497364151; cv=none; d=google.com; s=arc-20160816; b=r3PKTpe/jvJD9Du2zz23DL0OsBll2uJqluLerhW9ObLN1srUvvj02ToFIUzFQBq85Z 0227mOJkYkDkPHCnWOp0iPzqCP7sEK/io21e5B/mbRO8hboErHSCVA9b/nFqwnP9qlHp T+NSSOfeg/t7endFViZ/SgcPNHmac1/5qUzaiptZgXXFmPTYg/fRXlnBqzn4/h3aFb2Q 01m3BMb+wrqmJ6DUNrjn0UNqLIefnbLIuTYId1duCFlVf5TP0S+ZVu67ERat3NwWRoKj +4lrGPBRA5l7mQhJfivE5eweA1caDB1r2SUC1XW1zWRW+YEShkugWnr04tsC5rCdqIAe 0FkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=N4pJS9rzk1K/McKb6daImjK6VWwWAaqu5zFemsXS7VA=; b=wci5xx9zOCitrEbmyjdMUQIE/2WtibRhUMXdR/3hfzo7VT/tfxSeNFGZhExMHfiGpu HqWUbPHjhah36+0uTh2wCQMtgVbXc2BqgOCDJV8DxV3ho/cVHjWV356Gx8nGB0UjkQCK of3goOVhSwKu//tP850xvd2tG4LL0ZxCmEQCKg8DNZ5SduRODaQjE93bckKQ+XXWIlEx Gmn5nPjuM2rpYzhdOBJ8MsVpz55KIo56wBLic6sNw5BH5RxD7LbSCH90LyriHMU546HZ jdjtmKWMYH0ijAcXyae/X4gVaWuPEeO7CthuX4ttYsPvpc9JZkftHnZ7E3sBrTS2q2xZ UEfg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id p10si38487edl.263.2017.06.13.07.29.11 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 13 Jun 2017 07:29:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43590 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmog-0003Th-9A for patch@linaro.org; Tue, 13 Jun 2017 10:29:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33160) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmTc-0005I4-BN for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKmTb-0006hn-CD for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:24 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37257) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKmTb-0006cz-4B for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:23 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dKmTS-00013q-0R for qemu-devel@nongnu.org; Tue, 13 Jun 2017 15:07:14 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 15:06:58 +0100 Message-Id: <1497362826-21125-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> References: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 09/17] hw/misc/exynos4210_pmu: Add support for system poweroff X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Krzysztof Kozlowski On all Exynos-based boards, the system powers down itself by driving PS_HOLD signal low - eight bit in PS_HOLD_CONTROL register of PMU. Handle writing to respective PMU register to fix power off failure: reboot: Power down Unable to poweroff system shutdown: 31 output lines suppressed due to ratelimiting Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000000 CPU: 0 PID: 1 Comm: shutdown Not tainted 4.11.0-rc8 #846 Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [] (show_stack) from [] (dump_stack+0x88/0x9c) [] (dump_stack) from [] (panic+0xdc/0x268) [] (panic) from [] (do_exit+0xa90/0xab4) [] (do_exit) from [] (SyS_reboot+0x164/0x1d0) [] (SyS_reboot) from [] (ret_fast_syscall+0x0/0x3c) Additionally the initial value of PS_HOLD has to be changed because recent Linux kernel (v4.12-rc1) uses regmap cache for this access. When the register is kept at reset value, the kernel will not issue a write to it. Usually the bootloader sets the eight bit of PS_HOLD high so mimic its existence here. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- hw/misc/exynos4210_pmu.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/hw/misc/exynos4210_pmu.c b/hw/misc/exynos4210_pmu.c index 63a8ccd..0d7b64c 100644 --- a/hw/misc/exynos4210_pmu.c +++ b/hw/misc/exynos4210_pmu.c @@ -26,6 +26,7 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" +#include "sysemu/sysemu.h" #ifndef DEBUG_PMU #define DEBUG_PMU 0 @@ -350,7 +351,11 @@ static const Exynos4210PmuReg exynos4210_pmu_regs[] = { {"PAD_RETENTION_MMCB_OPTION", PAD_RETENTION_MMCB_OPTION, 0x00000000}, {"PAD_RETENTION_EBIA_OPTION", PAD_RETENTION_EBIA_OPTION, 0x00000000}, {"PAD_RETENTION_EBIB_OPTION", PAD_RETENTION_EBIB_OPTION, 0x00000000}, - {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200}, + /* + * PS_HOLD_CONTROL: reset value and manually toggle high the DATA bit. + * DATA bit high, set usually by bootloader, keeps system on. + */ + {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200 | BIT(8)}, {"XUSBXTI_CONFIGURATION", XUSBXTI_CONFIGURATION, 0x00000001}, {"XUSBXTI_STATUS", XUSBXTI_STATUS, 0x00000001}, {"XUSBXTI_DURATION", XUSBXTI_DURATION, 0xFFF00000}, @@ -397,6 +402,12 @@ typedef struct Exynos4210PmuState { uint32_t reg[PMU_NUM_OF_REGISTERS]; } Exynos4210PmuState; +static void exynos4210_pmu_poweroff(void) +{ + PRINT_DEBUG("QEMU PMU: PS_HOLD bit down, powering off\n"); + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); +} + static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset, unsigned size) { @@ -428,6 +439,13 @@ static void exynos4210_pmu_write(void *opaque, hwaddr offset, PRINT_DEBUG_EXTEND("%s <0x%04x> <- 0x%04x\n", reg_p->name, (uint32_t)offset, (uint32_t)val); s->reg[i] = val; + if ((offset == PS_HOLD_CONTROL) && ((val & BIT(8)) == 0)) { + /* + * We are interested only in setting data bit + * of PS_HOLD_CONTROL register to indicate power off request. + */ + exynos4210_pmu_poweroff(); + } return; } reg_p++; From patchwork Tue Jun 13 14:06:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 105364 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp436138qgd; Tue, 13 Jun 2017 07:32:43 -0700 (PDT) X-Received: by 10.55.151.69 with SMTP id z66mr233240qkd.90.1497364363813; Tue, 13 Jun 2017 07:32:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497364363; cv=none; d=google.com; s=arc-20160816; b=ckxK5AfLKWXOBKeNOW3VH5qN2o99VOCXaOwQtbd7sKwovf6uVZOdWBUc8WjSIkg2nF bOgeyVkJklachfwQmA3V7g48JBgHbgLIXoOo6j5f7wg2j123oZ/MieTlp3zZ4XZfOJgS AL4FYQ/ycNXuCNNM/O3t7nT5ZgLbbsaApcr2HNC2sv0Ip3V6yrsKR2QY7a0GKrpQGbWm mqvf9dKD35/DfxmWaKU3o9gZTpB0U8CnbqI+dsjBEtQUrpDG4OGsnQBA5hs7j858HC/v U4ow84wQGHLnGCWm56Afw3X1YcguxogYNrrjgBZXMANTipbl8RRVTOl9vu+gznO4LBKM Lx9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=2xiCgdGqMHsJas8/O7Zbd3Nz+PG9IV7kAgfIju7QZn4=; b=YJvXDg4dYTgFA9fbQCwo6PU61Pn0IxTyE86JwSWRsvb3DI/KbXquUNJwGb9WPLSjMt 7EokDVXNxRpod4tOuHsJQF4P+qRyU5ymcevCnEDF2ifhqfBgxZLugURH7oqghi50SNHI aXVfKMabycAVbrJTlOJg/1DVAgYa5ffSYG6U4jlkGsFreVV3SJDq1+b/oEqYYTCmiItw tPZtsXKhIbkujngUNAa2aRQlGCrnzrFtkrm7B2qBOEyfx5zoaT8TXLzAKLZuAeCvLAvQ DGM4Lc7nkfIfBucuaQY9K4JYsNDyCMHIafLc7SfpH6gLsZMV7IpU3/ADXKWne2IeDvOB UuCw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id y123si59396qkb.242.2017.06.13.07.32.43 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 13 Jun 2017 07:32:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43608 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKms5-0007QE-9i for patch@linaro.org; Tue, 13 Jun 2017 10:32:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33258) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmTg-0005Mh-PE for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKmTa-0006hR-SJ for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:28 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37258) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKmTa-0006fN-Cq for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:22 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dKmTS-000144-L5 for qemu-devel@nongnu.org; Tue, 13 Jun 2017 15:07:14 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 15:06:59 +0100 Message-Id: <1497362826-21125-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> References: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/17] timer.h: Provide better monotonic time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Pranith Kumar Tested and confirmed that the stretch i386 debian qcow2 image on a raspberry pi 2 works. Fixes: LP#: 893208 Signed-off-by: Pranith Kumar Reviewed-by: Paolo Bonzini Message-id: 20170418191817.10430-1-bobby.prani@gmail.com Signed-off-by: Peter Maydell --- include/qemu/timer.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/include/qemu/timer.h b/include/qemu/timer.h index 8a1eb74..1b518bc 100644 --- a/include/qemu/timer.h +++ b/include/qemu/timer.h @@ -1020,10 +1020,9 @@ static inline int64_t cpu_get_host_ticks(void) /* The host CPU doesn't have an easily accessible cycle counter. Just return a monotonically increasing value. This will be totally wrong, but hopefully better than nothing. */ -static inline int64_t cpu_get_host_ticks (void) +static inline int64_t cpu_get_host_ticks(void) { - static int64_t ticks = 0; - return ticks++; + return get_clock(); } #endif From patchwork Tue Jun 13 14:07:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 105361 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp434129qgd; Tue, 13 Jun 2017 07:29:05 -0700 (PDT) X-Received: by 10.28.232.133 with SMTP id f5mr11399574wmi.113.1497364145172; Tue, 13 Jun 2017 07:29:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497364145; cv=none; d=google.com; s=arc-20160816; b=qXgbR++WIff9PNhIXJV2XMe7c9myGlySttmWW44unWOoITVa1V8csgD0/6E/8rm5q+ bQEtGtdWURXx0KpDv00k1R4a8AG67AXu3QKGe4FE4ZLd1kcM6Vcm6tict8MXUk3IaWQ2 JKLFBsosJHtuewiARgBgdpTSHrzKDVzVLg2dYojFRNBEGSQbx/v806sf4n5mmVaRYiaF LovrFFa4aUeby/i0VYQBmBKFbr7BGABf+k8RysdElWDFYsCn9A/LuL2OoDoFs5Xs6Ity c/NvIjWk12ZsfaQEkdCBzb7EwxMV2ILR7Ls72oBiWp0Z88brNJi1dg2/kUvsYnkjJ+Z4 W7cQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=0NR6T1rLSvawCNZlU7aLj7wTo716n5Zf4qOZbhHOlOw=; b=QYuQhVdtEn4p6nnPfySJ3/81xBKjqnicO+fJsiLYz2X5f6WYxPVjJCgL/ZoFSbd6ol r/Rz+wNcz29nXn0H9s447CfFr8CgfO6I/bTgjZiqHYCNvrOKRtYFYfycTIb6Cx/Ir28f SYggO6p2JyRLjrW6KdNFk0awwGi0Tfn4VscjZTexZIzIePnGvy0vX8qWrDzAXtlPagyZ buwGNqN/t/7QhKpTq9Aztmmf/S+ZTaYPzrTgFodyjYu8hph6cNi5PoisbpsNtNYaRReq RE5nFAZf3dCPPEMh3j0XL1rEOCc7h3zSnOCn0VO6nrbVT3m8jHzzP1UWDgKKTpfhAnJv CyuA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id k58si61820wrk.226.2017.06.13.07.29.04 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 13 Jun 2017 07:29:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43587 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmoZ-00037U-Va for patch@linaro.org; Tue, 13 Jun 2017 10:29:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33169) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmTc-0005Ij-SA for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKmTa-0006h9-DZ for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:24 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37257) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKmTa-0006cz-1X for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:22 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dKmTT-00014R-EV for qemu-devel@nongnu.org; Tue, 13 Jun 2017 15:07:15 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 15:07:00 +0100 Message-Id: <1497362826-21125-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> References: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 11/17] hw/misc: add a TMP42{1, 2, 3} device model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Largely inspired by the TMP105 temperature sensor, here is a model for the TMP42{1,2,3} temperature sensors. Specs can be found here : http://www.ti.com/lit/gpn/tmp421 Signed-off-by: Cédric Le Goater Message-id: 1496739230-32109-2-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell --- hw/misc/Makefile.objs | 1 + hw/misc/tmp421.c | 402 ++++++++++++++++++++++++++++++++++++++++ default-configs/arm-softmmu.mak | 1 + 3 files changed, 404 insertions(+) create mode 100644 hw/misc/tmp421.c -- 2.7.4 diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index c8b4893..2019846 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -1,6 +1,7 @@ common-obj-$(CONFIG_APPLESMC) += applesmc.o common-obj-$(CONFIG_MAX111X) += max111x.o common-obj-$(CONFIG_TMP105) += tmp105.o +common-obj-$(CONFIG_TMP421) += tmp421.o common-obj-$(CONFIG_ISA_DEBUG) += debugexit.o common-obj-$(CONFIG_SGA) += sga.o common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o diff --git a/hw/misc/tmp421.c b/hw/misc/tmp421.c new file mode 100644 index 0000000..4a505ab --- /dev/null +++ b/hw/misc/tmp421.c @@ -0,0 +1,402 @@ +/* + * Texas Instruments TMP421 temperature sensor. + * + * Copyright (c) 2016 IBM Corporation. + * + * Largely inspired by : + * + * Texas Instruments TMP105 temperature sensor. + * + * Copyright (C) 2008 Nokia Corporation + * Written by Andrzej Zaborowski + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "hw/i2c/i2c.h" +#include "qapi/error.h" +#include "qapi/visitor.h" + +/* Manufacturer / Device ID's */ +#define TMP421_MANUFACTURER_ID 0x55 +#define TMP421_DEVICE_ID 0x21 +#define TMP422_DEVICE_ID 0x22 +#define TMP423_DEVICE_ID 0x23 + +typedef struct DeviceInfo { + int model; + const char *name; +} DeviceInfo; + +static const DeviceInfo devices[] = { + { TMP421_DEVICE_ID, "tmp421" }, + { TMP422_DEVICE_ID, "tmp422" }, + { TMP423_DEVICE_ID, "tmp423" }, +}; + +typedef struct TMP421State { + /*< private >*/ + I2CSlave i2c; + /*< public >*/ + + int16_t temperature[4]; + + uint8_t status; + uint8_t config[2]; + uint8_t rate; + + uint8_t len; + uint8_t buf[2]; + uint8_t pointer; + +} TMP421State; + +typedef struct TMP421Class { + I2CSlaveClass parent_class; + DeviceInfo *dev; +} TMP421Class; + +#define TYPE_TMP421 "tmp421-generic" +#define TMP421(obj) OBJECT_CHECK(TMP421State, (obj), TYPE_TMP421) + +#define TMP421_CLASS(klass) \ + OBJECT_CLASS_CHECK(TMP421Class, (klass), TYPE_TMP421) +#define TMP421_GET_CLASS(obj) \ + OBJECT_GET_CLASS(TMP421Class, (obj), TYPE_TMP421) + +/* the TMP421 registers */ +#define TMP421_STATUS_REG 0x08 +#define TMP421_STATUS_BUSY (1 << 7) +#define TMP421_CONFIG_REG_1 0x09 +#define TMP421_CONFIG_RANGE (1 << 2) +#define TMP421_CONFIG_SHUTDOWN (1 << 6) +#define TMP421_CONFIG_REG_2 0x0A +#define TMP421_CONFIG_RC (1 << 2) +#define TMP421_CONFIG_LEN (1 << 3) +#define TMP421_CONFIG_REN (1 << 4) +#define TMP421_CONFIG_REN2 (1 << 5) +#define TMP421_CONFIG_REN3 (1 << 6) + +#define TMP421_CONVERSION_RATE_REG 0x0B +#define TMP421_ONE_SHOT 0x0F + +#define TMP421_RESET 0xFC +#define TMP421_MANUFACTURER_ID_REG 0xFE +#define TMP421_DEVICE_ID_REG 0xFF + +#define TMP421_TEMP_MSB0 0x00 +#define TMP421_TEMP_MSB1 0x01 +#define TMP421_TEMP_MSB2 0x02 +#define TMP421_TEMP_MSB3 0x03 +#define TMP421_TEMP_LSB0 0x10 +#define TMP421_TEMP_LSB1 0x11 +#define TMP421_TEMP_LSB2 0x12 +#define TMP421_TEMP_LSB3 0x13 + +static const int32_t mins[2] = { -40000, -55000 }; +static const int32_t maxs[2] = { 127000, 150000 }; + +static void tmp421_get_temperature(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + TMP421State *s = TMP421(obj); + bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE); + int offset = ext_range * 64 * 256; + int64_t value; + int tempid; + + if (sscanf(name, "temperature%d", &tempid) != 1) { + error_setg(errp, "error reading %s: %m", name); + return; + } + + if (tempid >= 4 || tempid < 0) { + error_setg(errp, "error reading %s", name); + return; + } + + value = ((s->temperature[tempid] - offset) * 1000 + 128) / 256; + + visit_type_int(v, name, &value, errp); +} + +/* Units are 0.001 centigrades relative to 0 C. s->temperature is 8.8 + * fixed point, so units are 1/256 centigrades. A simple ratio will do. + */ +static void tmp421_set_temperature(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + TMP421State *s = TMP421(obj); + Error *local_err = NULL; + int64_t temp; + bool ext_range = (s->config[0] & TMP421_CONFIG_RANGE); + int offset = ext_range * 64 * 256; + int tempid; + + visit_type_int(v, name, &temp, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + if (temp >= maxs[ext_range] || temp < mins[ext_range]) { + error_setg(errp, "value %" PRId64 ".%03" PRIu64 " °C is out of range", + temp / 1000, temp % 1000); + return; + } + + if (sscanf(name, "temperature%d", &tempid) != 1) { + error_setg(errp, "error reading %s: %m", name); + return; + } + + if (tempid >= 4 || tempid < 0) { + error_setg(errp, "error reading %s", name); + return; + } + + s->temperature[tempid] = (int16_t) ((temp * 256 - 128) / 1000) + offset; +} + +static void tmp421_read(TMP421State *s) +{ + TMP421Class *sc = TMP421_GET_CLASS(s); + + s->len = 0; + + switch (s->pointer) { + case TMP421_MANUFACTURER_ID_REG: + s->buf[s->len++] = TMP421_MANUFACTURER_ID; + break; + case TMP421_DEVICE_ID_REG: + s->buf[s->len++] = sc->dev->model; + break; + case TMP421_CONFIG_REG_1: + s->buf[s->len++] = s->config[0]; + break; + case TMP421_CONFIG_REG_2: + s->buf[s->len++] = s->config[1]; + break; + case TMP421_CONVERSION_RATE_REG: + s->buf[s->len++] = s->rate; + break; + case TMP421_STATUS_REG: + s->buf[s->len++] = s->status; + break; + + /* FIXME: check for channel enablement in config registers */ + case TMP421_TEMP_MSB0: + s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 8); + s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0; + break; + case TMP421_TEMP_MSB1: + s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 8); + s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0; + break; + case TMP421_TEMP_MSB2: + s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 8); + s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0; + break; + case TMP421_TEMP_MSB3: + s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 8); + s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0; + break; + case TMP421_TEMP_LSB0: + s->buf[s->len++] = (((uint16_t) s->temperature[0]) >> 0) & 0xf0; + break; + case TMP421_TEMP_LSB1: + s->buf[s->len++] = (((uint16_t) s->temperature[1]) >> 0) & 0xf0; + break; + case TMP421_TEMP_LSB2: + s->buf[s->len++] = (((uint16_t) s->temperature[2]) >> 0) & 0xf0; + break; + case TMP421_TEMP_LSB3: + s->buf[s->len++] = (((uint16_t) s->temperature[3]) >> 0) & 0xf0; + break; + } +} + +static void tmp421_reset(I2CSlave *i2c); + +static void tmp421_write(TMP421State *s) +{ + switch (s->pointer) { + case TMP421_CONVERSION_RATE_REG: + s->rate = s->buf[0]; + break; + case TMP421_CONFIG_REG_1: + s->config[0] = s->buf[0]; + break; + case TMP421_CONFIG_REG_2: + s->config[1] = s->buf[0]; + break; + case TMP421_RESET: + tmp421_reset(I2C_SLAVE(s)); + break; + } +} + +static int tmp421_rx(I2CSlave *i2c) +{ + TMP421State *s = TMP421(i2c); + + if (s->len < 2) { + return s->buf[s->len++]; + } else { + return 0xff; + } +} + +static int tmp421_tx(I2CSlave *i2c, uint8_t data) +{ + TMP421State *s = TMP421(i2c); + + if (s->len == 0) { + /* first byte is the register pointer for a read or write + * operation */ + s->pointer = data; + s->len++; + } else if (s->len == 1) { + /* second byte is the data to write. The device only supports + * one byte writes */ + s->buf[0] = data; + tmp421_write(s); + } + + return 0; +} + +static int tmp421_event(I2CSlave *i2c, enum i2c_event event) +{ + TMP421State *s = TMP421(i2c); + + if (event == I2C_START_RECV) { + tmp421_read(s); + } + + s->len = 0; + return 0; +} + +static const VMStateDescription vmstate_tmp421 = { + .name = "TMP421", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_UINT8(len, TMP421State), + VMSTATE_UINT8_ARRAY(buf, TMP421State, 2), + VMSTATE_UINT8(pointer, TMP421State), + VMSTATE_UINT8_ARRAY(config, TMP421State, 2), + VMSTATE_UINT8(status, TMP421State), + VMSTATE_UINT8(rate, TMP421State), + VMSTATE_INT16_ARRAY(temperature, TMP421State, 4), + VMSTATE_I2C_SLAVE(i2c, TMP421State), + VMSTATE_END_OF_LIST() + } +}; + +static void tmp421_reset(I2CSlave *i2c) +{ + TMP421State *s = TMP421(i2c); + TMP421Class *sc = TMP421_GET_CLASS(s); + + memset(s->temperature, 0, sizeof(s->temperature)); + s->pointer = 0; + + s->config[0] = 0; /* TMP421_CONFIG_RANGE */ + + /* resistance correction and channel enablement */ + switch (sc->dev->model) { + case TMP421_DEVICE_ID: + s->config[1] = 0x1c; + break; + case TMP422_DEVICE_ID: + s->config[1] = 0x3c; + break; + case TMP423_DEVICE_ID: + s->config[1] = 0x7c; + break; + } + + s->rate = 0x7; /* 8Hz */ + s->status = 0; +} + +static int tmp421_init(I2CSlave *i2c) +{ + TMP421State *s = TMP421(i2c); + + tmp421_reset(&s->i2c); + + return 0; +} + +static void tmp421_initfn(Object *obj) +{ + object_property_add(obj, "temperature0", "int", + tmp421_get_temperature, + tmp421_set_temperature, NULL, NULL, NULL); + object_property_add(obj, "temperature1", "int", + tmp421_get_temperature, + tmp421_set_temperature, NULL, NULL, NULL); + object_property_add(obj, "temperature2", "int", + tmp421_get_temperature, + tmp421_set_temperature, NULL, NULL, NULL); + object_property_add(obj, "temperature3", "int", + tmp421_get_temperature, + tmp421_set_temperature, NULL, NULL, NULL); +} + +static void tmp421_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); + TMP421Class *sc = TMP421_CLASS(klass); + + k->init = tmp421_init; + k->event = tmp421_event; + k->recv = tmp421_rx; + k->send = tmp421_tx; + dc->vmsd = &vmstate_tmp421; + sc->dev = (DeviceInfo *) data; +} + +static const TypeInfo tmp421_info = { + .name = TYPE_TMP421, + .parent = TYPE_I2C_SLAVE, + .instance_size = sizeof(TMP421State), + .class_size = sizeof(TMP421Class), + .instance_init = tmp421_initfn, + .abstract = true, +}; + +static void tmp421_register_types(void) +{ + int i; + + type_register_static(&tmp421_info); + for (i = 0; i < ARRAY_SIZE(devices); ++i) { + TypeInfo ti = { + .name = devices[i].name, + .parent = TYPE_TMP421, + .class_init = tmp421_class_init, + .class_data = (void *) &devices[i], + }; + type_register(&ti); + } +} + +type_init(tmp421_register_types) diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 78d7af0..93e995d 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -15,6 +15,7 @@ CONFIG_TWL92230=y CONFIG_TSC2005=y CONFIG_LM832X=y CONFIG_TMP105=y +CONFIG_TMP421=y CONFIG_STELLARIS=y CONFIG_STELLARIS_INPUT=y CONFIG_STELLARIS_ENET=y From patchwork Tue Jun 13 14:07:01 2017 Content-Type: text/plain; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id w39si53111edw.93.2017.06.13.07.28.12 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 13 Jun 2017 07:28:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43585 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmnj-0002B8-6f for patch@linaro.org; Tue, 13 Jun 2017 10:28:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33122) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmTb-0005Gk-19 for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKmTZ-0006gt-Lt for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:22 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37258) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKmTZ-0006fN-Eo for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:21 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dKmTU-00014f-2I for qemu-devel@nongnu.org; Tue, 13 Jun 2017 15:07:16 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 15:07:01 +0100 Message-Id: <1497362826-21125-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> References: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 12/17] aspeed: add a temp sensor device on I2C bus 3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Temperatures can be changed from the monitor with : (qemu) qom-set /machine/unattached/device[2] temperature0 12000 Signed-off-by: Cédric Le Goater Message-id: 1496739230-32109-3-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell --- hw/arm/aspeed.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.7.4 diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index e824ea8..155eeb2 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -239,10 +239,19 @@ static void aspeed_board_init(MachineState *machine, static void palmetto_bmc_i2c_init(AspeedBoardState *bmc) { AspeedSoCState *soc = &bmc->soc; + DeviceState *dev; /* The palmetto platform expects a ds3231 RTC but a ds1338 is * enough to provide basic RTC features. Alarms will be missing */ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68); + + /* add a TMP423 temperature sensor */ + dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2), + "tmp423", 0x4c); + object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort); + object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort); + object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort); + object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort); } static void palmetto_bmc_init(MachineState *machine) From patchwork Tue Jun 13 14:07:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 105358 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp432646qgd; Tue, 13 Jun 2017 07:25:35 -0700 (PDT) X-Received: by 10.200.54.152 with SMTP id a24mr200762qtc.66.1497363935649; Tue, 13 Jun 2017 07:25:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497363935; cv=none; d=google.com; s=arc-20160816; b=MisDp5lMditExUOd953B/wlojB847PjkNNEhi72D3eJsKUju8hn4atnPEvT+udkljp dNtnzpz/T7SrjgSVns7yH47X7hy0cuci8Gn7IqUiJP1rbAtgQCU9rSnJodM0wbrztQPA CLflGtxo9hQgLD/AKPtZQR3BuKWhDOWExr/cS4bX2w88K0BBTmQA+AfksZBC9yZD6BP2 4A1l7TJsWEVBQpRast1xeh8zr9NAZKeA1XYmAFc541PLwpVzn1/cwhgh6PToowqZlfft lR5AmDxEl9perueF76ZirnD2MTRty90IK4Ju5KKm1GaM3rxa0IFvKatl8hQ3SbF9/E2i oVMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=tXMPNGT2vv5BX82hxTWW9hNlFdaHAS8QRDkFhu5ssak=; b=ZorPVMVsPzw06uqDHoF+zJ99VYhjTWYkORT2FQphsj0LZyNWz0mvayjCyTBGIrhE8X 1bpM1DtGr65Bpf175+FyBj4ArFFG264hwoMZ56PHl14KV7M0U7oDvhh/wYTtSeKq65ec AIu7YDHE8awPK5ADRjbdZiisWBzJ8vjBRfVYiILwee87Nmh3nEpHlQ2wCSpgbxEewYzZ hAJleHpvKnLmrlBLGdG8xSARJ0XYUjbP12KV6EpHDUdf4xXtnxcfJI6M0QMIxs/BT1rY XsTt6/7dNM7NQR5E3N7B9qh1zXQAh5dD7TF4KMpAddgg8SVSh2UlRYY1EXU2DsLocA2y TyjQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [208.118.235.17]) by mx.google.com with ESMTPS id b128si11670199qkf.321.2017.06.13.07.25.35 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 13 Jun 2017 07:25:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43560 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmlA-0005Gl-VI for patch@linaro.org; Tue, 13 Jun 2017 10:25:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33241) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmTf-0005LO-IA for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKmTZ-0006gg-Ar for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:27 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37257) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKmTZ-0006cz-2G for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:21 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dKmTU-00014t-MH for qemu-devel@nongnu.org; Tue, 13 Jun 2017 15:07:16 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 15:07:02 +0100 Message-Id: <1497362826-21125-14-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> References: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 13/17] timer/aspeed: fix timer enablement when a reload is not set X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater When a timer is enabled before a reload value is set, the controller waits for a reload value to be set before starting decrementing. This fix tries to cover that case by changing the timer expiry only when a reload value is valid. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Message-id: 1496739312-32304-1-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell --- hw/timer/aspeed_timer.c | 37 +++++++++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 8 deletions(-) -- 2.7.4 diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 9b70ee0..50acbf5 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -130,15 +130,26 @@ static uint64_t calculate_next(struct AspeedTimer *t) next = seq[1]; } else if (now < seq[2]) { next = seq[2]; - } else { + } else if (t->reload) { reload_ns = muldiv64(t->reload, NANOSECONDS_PER_SECOND, rate); t->start = now - ((now - t->start) % reload_ns); + } else { + /* no reload value, return 0 */ + break; } } return next; } +static void aspeed_timer_mod(AspeedTimer *t) +{ + uint64_t next = calculate_next(t); + if (next) { + timer_mod(&t->timer, next); + } +} + static void aspeed_timer_expire(void *opaque) { AspeedTimer *t = opaque; @@ -164,7 +175,7 @@ static void aspeed_timer_expire(void *opaque) qemu_set_irq(t->irq, t->level); } - timer_mod(&t->timer, calculate_next(t)); + aspeed_timer_mod(t); } static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg) @@ -227,10 +238,23 @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg, uint32_t value) { AspeedTimer *t; + uint32_t old_reload; trace_aspeed_timer_set_value(timer, reg, value); t = &s->timers[timer]; switch (reg) { + case TIMER_REG_RELOAD: + old_reload = t->reload; + t->reload = value; + + /* If the reload value was not previously set, or zero, and + * the current value is valid, try to start the timer if it is + * enabled. + */ + if (old_reload || !t->reload) { + break; + } + case TIMER_REG_STATUS: if (timer_enabled(t)) { uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -238,17 +262,14 @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg, uint32_t rate = calculate_rate(t); t->start += muldiv64(delta, NANOSECONDS_PER_SECOND, rate); - timer_mod(&t->timer, calculate_next(t)); + aspeed_timer_mod(t); } break; - case TIMER_REG_RELOAD: - t->reload = value; - break; case TIMER_REG_MATCH_FIRST: case TIMER_REG_MATCH_SECOND: t->match[reg - 2] = value; if (timer_enabled(t)) { - timer_mod(&t->timer, calculate_next(t)); + aspeed_timer_mod(t); } break; default: @@ -268,7 +289,7 @@ static void aspeed_timer_ctrl_enable(AspeedTimer *t, bool enable) trace_aspeed_timer_ctrl_enable(t->id, enable); if (enable) { t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - timer_mod(&t->timer, calculate_next(t)); + aspeed_timer_mod(t); } else { timer_del(&t->timer); } From patchwork Tue Jun 13 14:07:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 105357 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp432384qgd; Tue, 13 Jun 2017 07:24:58 -0700 (PDT) X-Received: by 10.237.53.33 with SMTP id a30mr83943qte.207.1497363898170; Tue, 13 Jun 2017 07:24:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497363898; cv=none; d=google.com; s=arc-20160816; b=CHx44WUxDfv2cgTY3d6+tm7Xy6WrAKeseWIfWLO05Hw4EYNtXT0AUWG4YDz4eMjDLF UdeIfomXOQN06wNXhkZeiLJ09FOkJZInwgAJRP5d+kk7y8UW+aKvseRbeYERSNDNcmAb 9fd9RAea0vcV9CbK1ii2PEQ56AN/ObGyhI7ROPNZSR70zaQmqrt0bfJzLnoTclvC9J7z pTTCF+QOrSq04G9xx9dtRQuk6Hn5oqsI4phbmHmjzML0MmCuqMOtJQ/5QQmTaUNjzao2 /FIzg8aiB/z5YYH+6EEe0uH47cEE5AUqJsVjmDsNtAwMNhMj+eX474rft5PE4jXmw59W aGIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=cvA2MYg4miBiY+Jztf7/y2pSDl+jgURFNhXknMFR3kw=; b=O9Fvi5x+ARjqsQ+ZR9T8q8ZEsARrdZK1DtbhsaVL7EI6Zo2VMkvITTN6BsdN8E57G9 DllvXWpRA7Dlx1qIQaIA8x2gHX0zqdPdSeEFArXyQr61dOvCFayfLRB11R19n0WoMO9q il3WYKV8hsjD2RIfUJ1dlzJ5d4ygQNrsu61lpLybC6hDuv9jT1aePErZn51DAh1kVw/Q UPleCA4vz+SgKtqJrr0VeKZQLt6D8beud1s+cWyxgwx2GLjpWZ3wrvcIoWGsJPFz8S1A x6J9j/9d6CZnDg9gmjkdgFj0l/IewtLdzcHuR5J3Js+R9+xAwUGcZLP0BP2dRgbt4bLH 7QfQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id r32si46608qta.195.2017.06.13.07.24.57 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 13 Jun 2017 07:24:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43559 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmkZ-00045w-G8 for patch@linaro.org; Tue, 13 Jun 2017 10:24:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33121) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmTb-0005Gj-0r for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKmTY-0006gH-QJ for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:22 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37258) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKmTY-0006fN-Fu for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:20 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dKmTV-00015G-Ax for qemu-devel@nongnu.org; Tue, 13 Jun 2017 15:07:17 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 15:07:03 +0100 Message-Id: <1497362826-21125-15-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> References: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 14/17] kvm-all: Pass an error object to kvm_device_access X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger In some circumstances, we don't want to abort if the kvm_device_access fails. This will be the case during ITS migration, in case the ITS table save/restore fails because the guest did not program the vITS correctly. So let's pass an error object to the function and return the ioctl value. New callers will be able to make a decision upon this returned value. Existing callers pass &error_abort which will cause the function to abort on failure. Signed-off-by: Eric Auger Reviewed-by: Juan Quintela Reviewed-by: Peter Xu Message-id: 1497023553-18411-2-git-send-email-eric.auger@redhat.com [PMM: wrapped long line] Signed-off-by: Peter Maydell --- include/sysemu/kvm.h | 11 +++++++---- hw/intc/arm_gic_kvm.c | 9 +++++---- hw/intc/arm_gicv3_its_kvm.c | 2 +- hw/intc/arm_gicv3_kvm.c | 14 +++++++------- kvm-all.c | 14 ++++++++------ 5 files changed, 28 insertions(+), 22 deletions(-) -- 2.7.4 diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index a45c145..1e91613 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -294,12 +294,15 @@ int kvm_device_check_attr(int fd, uint32_t group, uint64_t attr); * @attr: the attribute of that group to set or get * @val: pointer to a storage area for the value * @write: true for set and false for get operation + * @errp: error object handle * - * This function is not allowed to fail. Use kvm_device_check_attr() - * in order to check for the availability of optional attributes. + * Returns: 0 on success + * < 0 on error + * Use kvm_device_check_attr() in order to check for the availability + * of optional attributes. */ -void kvm_device_access(int fd, int group, uint64_t attr, - void *val, bool write); +int kvm_device_access(int fd, int group, uint64_t attr, + void *val, bool write, Error **errp); /** * kvm_create_device - create a KVM device for the device control API diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index af5cd36..ae095d0 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -100,14 +100,14 @@ static void kvm_gicd_access(GICState *s, int offset, int cpu, uint32_t *val, bool write) { kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, - KVM_VGIC_ATTR(offset, cpu), val, write); + KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort); } static void kvm_gicc_access(GICState *s, int offset, int cpu, uint32_t *val, bool write) { kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_REGS, - KVM_VGIC_ATTR(offset, cpu), val, write); + KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort); } #define for_each_irq_reg(_ctr, _max_irq, _field_width) \ @@ -538,13 +538,14 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp) if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0)) { uint32_t numirqs = s->num_irq; kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0, - &numirqs, true); + &numirqs, true, &error_abort); } /* Tell the kernel to complete VGIC initialization now */ if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, KVM_DEV_ARM_VGIC_CTRL_INIT)) { kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, - KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true); + KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, + &error_abort); } } else if (ret != -ENODEV && ret != -ENOTSUP) { error_setg_errno(errp, -ret, "error creating in-kernel VGIC"); diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index a0441d6..340c2b0 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -78,7 +78,7 @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) /* explicit init of the ITS */ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, - KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true); + KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); /* register the base address */ kvm_arm_register_device(&s->iomem_its_cntrl, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 4ee2baa..b70ee27 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -93,7 +93,7 @@ static inline void kvm_gicd_access(GICv3State *s, int offset, { kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, KVM_VGIC_ATTR(offset, 0), - val, write); + val, write, &error_abort); } static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu, @@ -101,7 +101,7 @@ static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu, { kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS, KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer), - val, write); + val, write, &error_abort); } static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu, @@ -109,7 +109,7 @@ static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu, { kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer), - val, write); + val, write, &error_abort); } static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu, @@ -119,7 +119,7 @@ static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu, KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) | (VGIC_LEVEL_INFO_LINE_LEVEL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT), - val, write); + val, write, &error_abort); } /* Loop through each distributor IRQ related register; since bits @@ -630,7 +630,7 @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) /* Initialize to actual HW supported configuration */ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity), - &c->icc_ctlr_el1[GICV3_NS], false); + &c->icc_ctlr_el1[GICV3_NS], false, &error_abort); c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; } @@ -717,11 +717,11 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) } kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, - 0, &s->num_irq, true); + 0, &s->num_irq, true, &error_abort); /* Tell the kernel to complete VGIC initialization now */ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, - KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true); + KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); kvm_arm_register_device(&s->iomem_dist, -1, KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd); diff --git a/kvm-all.c b/kvm-all.c index 44b3cf4..ab8262f 100644 --- a/kvm-all.c +++ b/kvm-all.c @@ -23,6 +23,7 @@ #include "qemu/option.h" #include "qemu/config-file.h" #include "qemu/error-report.h" +#include "qapi/error.h" #include "hw/hw.h" #include "hw/pci/msi.h" #include "hw/pci/msix.h" @@ -2216,8 +2217,8 @@ int kvm_device_check_attr(int dev_fd, uint32_t group, uint64_t attr) return kvm_device_ioctl(dev_fd, KVM_HAS_DEVICE_ATTR, &attribute) ? 0 : 1; } -void kvm_device_access(int fd, int group, uint64_t attr, - void *val, bool write) +int kvm_device_access(int fd, int group, uint64_t attr, + void *val, bool write, Error **errp) { struct kvm_device_attr kvmattr; int err; @@ -2231,11 +2232,12 @@ void kvm_device_access(int fd, int group, uint64_t attr, write ? KVM_SET_DEVICE_ATTR : KVM_GET_DEVICE_ATTR, &kvmattr); if (err < 0) { - error_report("KVM_%s_DEVICE_ATTR failed: %s", - write ? "SET" : "GET", strerror(-err)); - error_printf("Group %d attr 0x%016" PRIx64 "\n", group, attr); - abort(); + error_setg_errno(errp, -err, + "KVM_%s_DEVICE_ATTR failed: Group %d " + "attr 0x%016" PRIx64, + write ? "SET" : "GET", group, attr); } + return err; } /* Return 1 on success, 0 on failure */ From patchwork Tue Jun 13 14:07:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 105355 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp430712qgd; Tue, 13 Jun 2017 07:21:23 -0700 (PDT) X-Received: by 10.80.175.165 with SMTP id h34mr45132edd.87.1497363683260; Tue, 13 Jun 2017 07:21:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497363683; cv=none; d=google.com; s=arc-20160816; b=tdDsXaMb3leF8pntlX1yD/OSWqz/q/ML4FG5Hyp0zDMCdZeEqbJ681BZOtdGNQx3dQ Z5j/i63q1n5mY1j2CgKpGaS/1w98+IenhwUjnYPKoNqgyrkD3AzH1Rhii/FEfu4xrTFf M4VurBSff0wEOEEEd9ZJXc1JjM4sX8AwpXIJJRY+QH1cFc8OG/x+Kv7kYEN2UaVyQQnJ gv9o3ATfGdamJNH50FroXAdEyIV0BrIKPiUwLpATnTI+swpszZR22Vt/bQ8oadqic53y Fn0nOD4MIk5dz6h63Va0UNDT1kweehumOCOPXzxpwN0KBLIT8HedmO+j4dfKbL5/e6PM bPSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=bbm1SXF0hlcPb9ulCpiwHBIc7MZkzvz5jRzVIMqmVyQ=; b=Jer3Z7CoMryfvDAWdG6LkihfC4SJtuCQhZQzVZ2R40eqhwxQDK4driV/FkCB/CaLPf P35uMOEP4CbOnNzfNxF9o/rGz/guwb3USMfDEY5MyZ0xrtog2ia5TMAaYzPS9/PKDcZj LJk7JKH+oysYX7eSxKlcXkgpqFR8mbK2PZuF5i6wz2p1jrINfFn/BXyyRvluT4wTsPO9 Op9SJu5T5oKHuDSDAwpw1lngyvG2SAp5nTxEsr2yFM+4JV+RY7kPxktv0KvUd74/s2gu yZtjPCC/gdm37f5javxrGRkIzuzDMSRABVK22RDKrccW/TZg7gzCHnfjlLs2tK01rySg vs9Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [208.118.235.17]) by mx.google.com with ESMTPS id g39si28323edb.262.2017.06.13.07.21.22 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 13 Jun 2017 07:21:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43534 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmh7-0000oV-Ua for patch@linaro.org; Tue, 13 Jun 2017 10:21:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33072) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmTY-0005Em-Nc for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKmTX-0006fe-Co for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:20 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37257) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKmTX-0006cz-39 for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:19 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dKmTV-00015V-Ux for qemu-devel@nongnu.org; Tue, 13 Jun 2017 15:07:17 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 15:07:04 +0100 Message-Id: <1497362826-21125-16-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> References: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 15/17] hw/intc/arm_gicv3_its: Implement state save/restore X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger We need to handle both registers and ITS tables. While register handling is standard, ITS table handling is more challenging since the kernel API is devised so that the tables are flushed into guest RAM and not in vmstate buffers. Flushing the ITS tables on device pre_save() is too late since the guest RAM is already saved at this point. Table flushing needs to happen when we are sure the vcpus are stopped and before the last dirty page saving. The right point is RUN_STATE_FINISH_MIGRATE but sometimes the VM gets stopped before migration launch so let's simply flush the tables each time the VM gets stopped. For regular ITS registers we just can use vmstate pre_save() and post_load() callbacks. Signed-off-by: Eric Auger Message-id: 1497023553-18411-3-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/intc/arm_gicv3_its_common.h | 8 +++ hw/intc/arm_gicv3_its_common.c | 10 ++++ hw/intc/arm_gicv3_its_kvm.c | 105 +++++++++++++++++++++++++++++++++ 3 files changed, 123 insertions(+) -- 2.7.4 diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_gicv3_its_common.h index 1ba1894..fd1fe64 100644 --- a/include/hw/intc/arm_gicv3_its_common.h +++ b/include/hw/intc/arm_gicv3_its_common.h @@ -28,6 +28,13 @@ #define ITS_TRANS_SIZE 0x10000 #define ITS_SIZE (ITS_CONTROL_SIZE + ITS_TRANS_SIZE) +#define GITS_CTLR 0x0 +#define GITS_IIDR 0x4 +#define GITS_CBASER 0x80 +#define GITS_CWRITER 0x88 +#define GITS_CREADR 0x90 +#define GITS_BASER 0x100 + struct GICv3ITSState { SysBusDevice parent_obj; @@ -43,6 +50,7 @@ struct GICv3ITSState { /* Registers */ uint32_t ctlr; + uint32_t iidr; uint64_t cbaser; uint64_t cwriter; uint64_t creadr; diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c index 9d67c5c..696c11c 100644 --- a/hw/intc/arm_gicv3_its_common.c +++ b/hw/intc/arm_gicv3_its_common.c @@ -49,6 +49,15 @@ static const VMStateDescription vmstate_its = { .pre_save = gicv3_its_pre_save, .post_load = gicv3_its_post_load, .unmigratable = true, + .fields = (VMStateField[]) { + VMSTATE_UINT32(ctlr, GICv3ITSState), + VMSTATE_UINT32(iidr, GICv3ITSState), + VMSTATE_UINT64(cbaser, GICv3ITSState), + VMSTATE_UINT64(cwriter, GICv3ITSState), + VMSTATE_UINT64(creadr, GICv3ITSState), + VMSTATE_UINT64_ARRAY(baser, GICv3ITSState, 8), + VMSTATE_END_OF_LIST() + }, }; static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset, @@ -118,6 +127,7 @@ static void gicv3_its_common_reset(DeviceState *dev) s->cbaser = 0; s->cwriter = 0; s->creadr = 0; + s->iidr = 0; memset(&s->baser, 0, sizeof(s->baser)); gicv3_its_post_load(s, 0); diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index 340c2b0..4cd8f5f 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -53,6 +53,33 @@ static int kvm_its_send_msi(GICv3ITSState *s, uint32_t value, uint16_t devid) return kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi); } +/** + * vm_change_state_handler - VM change state callback aiming at flushing + * ITS tables into guest RAM + * + * The tables get flushed to guest RAM whenever the VM gets stopped. + */ +static void vm_change_state_handler(void *opaque, int running, + RunState state) +{ + GICv3ITSState *s = (GICv3ITSState *)opaque; + Error *err = NULL; + int ret; + + if (running) { + return; + } + + ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_ITS_SAVE_TABLES, NULL, true, &err); + if (err) { + error_report_err(err); + } + if (ret < 0 && ret != -EFAULT) { + abort(); + } +} + static void kvm_arm_its_realize(DeviceState *dev, Error **errp) { GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); @@ -89,6 +116,8 @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) kvm_msi_use_devid = true; kvm_gsi_direct_mapping = false; kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); + + qemu_add_vm_change_state_handler(vm_change_state_handler, s); } static void kvm_arm_its_init(Object *obj) @@ -102,6 +131,80 @@ static void kvm_arm_its_init(Object *obj) &error_abort); } +/** + * kvm_arm_its_pre_save - handles the saving of ITS registers. + * ITS tables are flushed into guest RAM separately and earlier, + * through the VM change state handler, since at the moment pre_save() + * is called, the guest RAM has already been saved. + */ +static void kvm_arm_its_pre_save(GICv3ITSState *s) +{ + int i; + + for (i = 0; i < 8; i++) { + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, + GITS_BASER + i * 8, &s->baser[i], false, + &error_abort); + } + + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, + GITS_CTLR, &s->ctlr, false, &error_abort); + + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, + GITS_CBASER, &s->cbaser, false, &error_abort); + + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, + GITS_CREADR, &s->creadr, false, &error_abort); + + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, + GITS_CWRITER, &s->cwriter, false, &error_abort); + + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, + GITS_IIDR, &s->iidr, false, &error_abort); +} + +/** + * kvm_arm_its_post_load - Restore both the ITS registers and tables + */ +static void kvm_arm_its_post_load(GICv3ITSState *s) +{ + int i; + + if (!s->iidr) { + return; + } + + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, + GITS_IIDR, &s->iidr, true, &error_abort); + + /* + * must be written before GITS_CREADR since GITS_CBASER write + * access resets GITS_CREADR. + */ + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, + GITS_CBASER, &s->cbaser, true, &error_abort); + + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, + GITS_CREADR, &s->creadr, true, &error_abort); + + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, + GITS_CWRITER, &s->cwriter, true, &error_abort); + + + for (i = 0; i < 8; i++) { + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, + GITS_BASER + i * 8, &s->baser[i], true, + &error_abort); + } + + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_ITS_RESTORE_TABLES, NULL, true, + &error_abort); + + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, + GITS_CTLR, &s->ctlr, true, &error_abort); +} + static void kvm_arm_its_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -109,6 +212,8 @@ static void kvm_arm_its_class_init(ObjectClass *klass, void *data) dc->realize = kvm_arm_its_realize; icc->send_msi = kvm_its_send_msi; + icc->pre_save = kvm_arm_its_pre_save; + icc->post_load = kvm_arm_its_post_load; } static const TypeInfo kvm_arm_its_info = { From patchwork Tue Jun 13 14:07:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 105369 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp439057qgd; Tue, 13 Jun 2017 07:39:10 -0700 (PDT) X-Received: by 10.80.143.166 with SMTP id y35mr159548edy.40.1497364750237; Tue, 13 Jun 2017 07:39:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497364750; cv=none; d=google.com; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id o35si46636edb.318.2017.06.13.07.39.10 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 13 Jun 2017 07:39:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43648 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmyL-0005Bd-44 for patch@linaro.org; Tue, 13 Jun 2017 10:39:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33077) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmTY-0005F1-VO for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKmTX-0006fl-PF for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:20 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37258) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKmTX-0006fN-HO for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:19 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dKmTW-00015w-Iw for qemu-devel@nongnu.org; Tue, 13 Jun 2017 15:07:18 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 15:07:05 +0100 Message-Id: <1497362826-21125-17-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> References: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 16/17] hw/intc/arm_gicv3_kvm: Implement pending table save X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger This patch adds the flush of the LPI pending bits into the redistributor pending tables. This happens on VM stop. There is no explicit restore as the tables are implicitly sync'ed on ITS table restore and on LPI enable at redistributor level. Signed-off-by: Eric Auger Message-id: 1497023553-18411-4-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_kvm.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) -- 2.7.4 diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index b70ee27..6051c77 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -25,6 +25,7 @@ #include "hw/sysbus.h" #include "qemu/error-report.h" #include "sysemu/kvm.h" +#include "sysemu/sysemu.h" #include "kvm_arm.h" #include "gicv3_internal.h" #include "vgic_common.h" @@ -680,6 +681,35 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { REGINFO_SENTINEL }; +/** + * vm_change_state_handler - VM change state callback aiming at flushing + * RDIST pending tables into guest RAM + * + * The tables get flushed to guest RAM whenever the VM gets stopped. + */ +static void vm_change_state_handler(void *opaque, int running, + RunState state) +{ + GICv3State *s = (GICv3State *)opaque; + Error *err = NULL; + int ret; + + if (running) { + return; + } + + ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES, + NULL, true, &err); + if (err) { + error_report_err(err); + } + if (ret < 0 && ret != -EFAULT) { + abort(); + } +} + + static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) { GICv3State *s = KVM_ARM_GICV3(dev); @@ -751,6 +781,10 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) return; } } + if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) { + qemu_add_vm_change_state_handler(vm_change_state_handler, s); + } } static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data) From patchwork Tue Jun 13 14:07:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 105367 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp437347qgd; Tue, 13 Jun 2017 07:35:21 -0700 (PDT) X-Received: by 10.55.26.82 with SMTP id a79mr241128qka.136.1497364521851; Tue, 13 Jun 2017 07:35:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497364521; cv=none; d=google.com; s=arc-20160816; b=R5egdUX5Ijap1Cec8hpv0OOswUxVfG0Hi7nxSIb8jRdxU39BFe52FAbGfWDYYNZurh wCE7Lc5HHzAADEoNuYr8wozqRjzoQH6fPrjFIrpT2c5BwirG1fgzGgg2WITV9IBLUhjq UhzbPG++cghPyvNQCN1vLPLijy7zDkb9527Bq+KAkDmAtuSG8D5TFNsKiANVUOmM1cj0 zkxPe7dYDcRtQ6lwP1t+Zs3fFlHfJ2wvBeaiiwIkGKZu4ObaCQIM9HnQJOLxvtGMTBqs 3f5LAGTHdiF3nUO0qnM5jfRMuTptk86cchgzTWofGGVOK0GBZuwfeRYbzhwOGYkXPK9C /NiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=YwXeliAOoN+aR2uTOERv5ZtNBgWj9uoXQPHjz+o9HTo=; b=PxKa4+dp7MQmlgf57nzf13sbI6r6rkgxL0HaJ1f4jreaURv2fx1hNy/B7hVl8Q/zVF 8sxb/8Ft1AUafKmopkzy+ksNcVHbijVQxOy7g6Wx2NeMwjO/IYAveJmIXqOP6dfsZKKY 9eD197nrcVGLkZ5iQxu10DzYa61FODtZZU905kDfeKjDBlMvt2w0fTxgMROVQ7kO1r/O NwaLTvdbvQVQhn1uWlztHJMGWWG+SVYsY5H0YWVENeJkcFoLbjzxkQcfoVW+tMOJ9dyg hxLWnZbxLKurSVEB1tQod3GESvqinMEbl4N5kZlaQdnCj+zsAbqJ/JyZ4BM7/EfHfuF6 V2nA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id c6si64235qta.275.2017.06.13.07.35.21 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 13 Jun 2017 07:35:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43619 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmuc-0001wy-Uw for patch@linaro.org; Tue, 13 Jun 2017 10:35:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33186) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKmTd-0005JI-Gr for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKmTY-0006fx-BH for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:25 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37257) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dKmTY-0006cz-2O for qemu-devel@nongnu.org; Tue, 13 Jun 2017 10:07:20 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dKmTX-000168-7U for qemu-devel@nongnu.org; Tue, 13 Jun 2017 15:07:19 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 13 Jun 2017 15:07:06 +0100 Message-Id: <1497362826-21125-18-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> References: <1497362826-21125-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 17/17] hw/intc/arm_gicv3_its: Allow save/restore X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger We change the restoration priority of both the GICv3 and ITS. The GICv3 must be restored before the ITS and the ITS needs to be restored before PCIe devices since it translates their MSI transactions. Signed-off-by: Eric Auger Reviewed-by: Juan Quintela Message-id: 1497023553-18411-5-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell --- include/migration/vmstate.h | 2 ++ hw/intc/arm_gicv3_common.c | 1 + hw/intc/arm_gicv3_its_common.c | 2 +- hw/intc/arm_gicv3_its_kvm.c | 24 ++++++++++++------------ 4 files changed, 16 insertions(+), 13 deletions(-) -- 2.7.4 diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index 79a4b35..f3f3c2a 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -149,6 +149,8 @@ enum VMStateFlags { typedef enum { MIG_PRI_DEFAULT = 0, MIG_PRI_IOMMU, /* Must happen before PCI devices */ + MIG_PRI_GICV3_ITS, /* Must happen before PCI devices */ + MIG_PRI_GICV3, /* Must happen before the ITS */ MIG_PRI_MAX, } MigrationPriority; diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index c6493d6..4228b7c 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -145,6 +145,7 @@ static const VMStateDescription vmstate_gicv3 = { .minimum_version_id = 1, .pre_save = gicv3_pre_save, .post_load = gicv3_post_load, + .priority = MIG_PRI_GICV3, .fields = (VMStateField[]) { VMSTATE_UINT32(gicd_ctlr, GICv3State), VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2), diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c index 696c11c..68b20fc 100644 --- a/hw/intc/arm_gicv3_its_common.c +++ b/hw/intc/arm_gicv3_its_common.c @@ -48,7 +48,7 @@ static const VMStateDescription vmstate_its = { .name = "arm_gicv3_its", .pre_save = gicv3_its_pre_save, .post_load = gicv3_its_post_load, - .unmigratable = true, + .priority = MIG_PRI_GICV3_ITS, .fields = (VMStateField[]) { VMSTATE_UINT32(ctlr, GICv3ITSState), VMSTATE_UINT32(iidr, GICv3ITSState), diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index 4cd8f5f..1f8991b 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -85,18 +85,6 @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); Error *local_err = NULL; - /* - * Block migration of a KVM GICv3 ITS device: the API for saving and - * restoring the state in the kernel is not yet available - */ - error_setg(&s->migration_blocker, "vITS migration is not implemented"); - migrate_add_blocker(s->migration_blocker, &local_err); - if (local_err) { - error_propagate(errp, local_err); - error_free(s->migration_blocker); - return; - } - s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_ITS, false); if (s->dev_fd < 0) { error_setg_errno(errp, -s->dev_fd, "error creating in-kernel ITS"); @@ -113,6 +101,18 @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) gicv3_its_init_mmio(s, NULL); + if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, + GITS_CTLR)) { + error_setg(&s->migration_blocker, "This operating system kernel " + "does not support vITS migration"); + migrate_add_blocker(s->migration_blocker, &local_err); + if (local_err) { + error_propagate(errp, local_err); + error_free(s->migration_blocker); + return; + } + } + kvm_msi_use_devid = true; kvm_gsi_direct_mapping = false; kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled();