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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id g13-20020a5d488d000000b00347321735a6sm7931517wrq.66.2024.04.15.05.44.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Apr 2024 05:44:32 -0700 (PDT) From: Caleb Connolly Date: Mon, 15 Apr 2024 13:44:20 +0100 Subject: [PATCH 1/3] clk/qcom: apq8016: return valid rate when setting UART clock MIME-Version: 1.0 Message-Id: <20240415-b4-msm-serial-bitrate-v1-1-5a89f84fd9e7@linaro.org> References: <20240415-b4-msm-serial-bitrate-v1-0-5a89f84fd9e7@linaro.org> In-Reply-To: <20240415-b4-msm-serial-bitrate-v1-0-5a89f84fd9e7@linaro.org> To: Lukasz Majewski , Sean Anderson , Caleb Connolly , Neil Armstrong , Sumit Garg , Tom Rini Cc: Robert Marko , u-boot-qcom@groups.io, u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=920; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=z+mdt6z8O9e9zBFdjcbWdLQu5FVirlaHaG+3os0axxg=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjRZRb0d3LdXCW2bNdOk5/undYlPL01obZ76l8tU8/ud2 9oSt6Rmd5SyMAhyMMiKKbKIn1hm2bT2sr3G9gUXYOawMoEMYeDiFICJaF5gZFi8MP/mD3UGx1t8 ZmdmHM07dHf+ollRZ16fP6904G7LHsHrjAyr/Po/lHQy6m/41jZ976MPXlMXBNeZRiT/nqv3o2n G76XyAA== X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The clk_init_uart() helper always returns 0, but we're meant to return a real clock rate. Given that we hardcode 115200 baud, just return the clock rate that we set. Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-apq8016.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 5a5868169c89..6210fba87984 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -99,10 +99,10 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate) case GCC_SDCC2_APPS_CLK: /* SDC2 */ return clk_init_sdc(priv, 1, rate); break; case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */ - return apq8016_clk_init_uart(priv->base); - break; + apq8016_clk_init_uart(priv->base); + return 7372800; default: return 0; } } From patchwork Mon Apr 15 12:44:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 788966 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp1885013wrm; Mon, 15 Apr 2024 05:44:55 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU0vY7a2JDWQSrTzmvhi0pLgJsHu6F6TF2Vq0a5rn3rv7hxKhf0JLoGiCXoWmjaXrd3d0u9A9NsLVDEbHKaRIUu X-Google-Smtp-Source: AGHT+IFVjvyMvXi6RZoOX2I973bwaTPHPTbQ+ivNDhN1YqExERmCUq5xHebhbIXZn+uhx0/AgrB2 X-Received: by 2002:a17:906:37c7:b0:a51:ab81:6062 with SMTP id o7-20020a17090637c700b00a51ab816062mr10059397ejc.30.1713185095755; Mon, 15 Apr 2024 05:44:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713185095; cv=none; d=google.com; s=arc-20160816; b=gPc/hCrexFnkv6U17UC/Q2JNJM/R8L0qMV8CH9QXyEH+xx4e8AKaH7+mtzPh2AA9R4 ibGWqPIZLroOCUhsoPpQfvjW5qqC83ZebY30D7Ceu7sI7q6odPdrPVu6rBmGiRnzPxEP OndogHQ3WyNJhyRcE6l3NQDdC971wjYCchUFkauiI00MwU6KsCyJeLhV6o9jBTLLRzl8 V1pxyWjRB0X8pmB5ya0ieAw5m7AHQwmle1PrULvg2O9ahUwjlN0tjSbiiBRtVl9OHLSu zSJf37N92ZzOKdD7rw9jMxHK7k5itjUaxjF2Yt7JKLdNYzKIOv0+aZLcNe/dJny17wxa /cgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=75JeNrH2fm9Dj7m4XrOpiemG5n9ITOmRPsU5m9vbyek=; fh=NUUNJJl/YJo7iuqXsGXQuuqqe5OpjLYih7RYbUR8JPA=; b=gxSqWTfmPdo7mqBbY55lbryoPEBs4Vh1Rt0h3rnjP4u9p9ru6HxDOPbTcZf7ZPvoiP VxRCJGKShs0YnLSJ3JPdXXoS2OI/AACqnN8fBTZSk23B2crlkcPnrCopbTcTVp8avEkx 5ky1NugELJrz465K0NUvm2RCRksQ1axzCyHHsX5chS2epemFOJC9GYOVyy4f4svbO8XH ghtKGK+kE9M0eKbcjQaN0c1oKbzXlkq5QnWTwzTddxyZ6WRjTlBGCsgbmSRQaMntLFww n4YE79HC/svVd0bVKGZvbrg/BsFDCk5RSSM9p5mXfjPlf/nYHH3HdTORrQUR202RjTDY gqPg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eF14+iIH; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id g13-20020a5d488d000000b00347321735a6sm7931517wrq.66.2024.04.15.05.44.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Apr 2024 05:44:33 -0700 (PDT) From: Caleb Connolly Date: Mon, 15 Apr 2024 13:44:21 +0100 Subject: [PATCH 2/3] clk/qcom: ipq4019: return valid rate when setting UART clock MIME-Version: 1.0 Message-Id: <20240415-b4-msm-serial-bitrate-v1-2-5a89f84fd9e7@linaro.org> References: <20240415-b4-msm-serial-bitrate-v1-0-5a89f84fd9e7@linaro.org> In-Reply-To: <20240415-b4-msm-serial-bitrate-v1-0-5a89f84fd9e7@linaro.org> To: Lukasz Majewski , Sean Anderson , Caleb Connolly , Neil Armstrong , Sumit Garg , Tom Rini Cc: Robert Marko , u-boot-qcom@groups.io, u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=979; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=jbE4uxM05hys6K6aPZcowyfpb9rgLC2loD8Pu1qX1Mc=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjRZRf3ST2ca1/PWLnhWfufwFE2d4u0ndYNPxZdfbeb/q a0RYnmqo5SFQZCDQVZMkUX8xDLLprWX7TW2L7gAM4eVCWQIAxenAEzEXpSRoZ2hPXbC2/gt67xP 5f6acfnp9JJL/m/KRG699Ir59/jJs6kM/+OFm7VYlZjMCpZeU594L2Beg7ws574FRe3yNtyKS/v fNAAA X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean clk_set_rate() should return the clock rate that was set. The IPQ4019 clock driver doesn't set any rates yet but it should still return the expected value so that drivers can work properly. For a baud rate of 115200 with an expected bit clock divisor of 16, the clock rate should be 1843200 so return that frequency. Signed-off-by: Caleb Connolly --- drivers/clk/qcom/clock-ipq4019.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c index d693776d339d..72f235eab212 100644 --- a/drivers/clk/qcom/clock-ipq4019.c +++ b/drivers/clk/qcom/clock-ipq4019.c @@ -20,9 +20,9 @@ static ulong ipq4019_clk_set_rate(struct clk *clk, ulong rate) { switch (clk->id) { case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/ /* This clock is already initialized by SBL1 */ - return 0; + return 1843200; default: return -EINVAL; } } From patchwork Mon Apr 15 12:44:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caleb Connolly X-Patchwork-Id: 788967 Delivered-To: patch@linaro.org Received: by 2002:adf:e6ca:0:b0:346:15ad:a2a with SMTP id y10csp1885102wrm; Mon, 15 Apr 2024 05:45:07 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUkQ6Lea62NS/NgZv00TH3dW+lacj3cxbedFyMuXnkC4QY2/MrWig1yjvAQPdaXzE/cX9eC4AJTXudos5a36fYJ X-Google-Smtp-Source: AGHT+IGPoEHgesYGv3nMvCAnXEcgN2toy6ldI6e5Qkow+jSvI+7uJAEoW0BsXY23fkIoDiIkOlag X-Received: by 2002:a50:cd59:0:b0:570:388:ee0b with SMTP id d25-20020a50cd59000000b005700388ee0bmr4895846edj.42.1713185106900; Mon, 15 Apr 2024 05:45:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713185106; cv=none; d=google.com; s=arc-20160816; b=0Ik43r24i8eOXlJw1haRLoaoiQ6y8gp+YMAQ78DHnXMZfRHq1DgIUQwRTbhIlrlOVG x7/zaZ2TGUDbSafvm8LiHVJdsVDV/6+BuTNUAndnorTqxfuggoyqqHxlxRp+J2RMeERW 7ZBQJq+D/gJdhE7ibUi4yOltj4Pfc0SatqL3VwHIibKe3xWvYl3bmnKdJgyFfeZjwwtF 1TyZxrQv0lt0UB1OhUWXJele3jQmD6gepcbGf5MUMBWuumiJ1ZiAm0CwMocRRm2Bxtt6 cUoeo8qLRjIvpbb2Tk5nudj8DJJNJ7FHaz0wJ5LPSc6IigjbTCfWf0lN0I6bsjlE+Cix ANYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:cc:to:in-reply-to:references :message-id:content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=KKToaQHgyHh55DwkywJHtqMYEmkaeGoRmi5Lqi5pt+A=; fh=aiHXGNf+b6GCEqqkMzWkuypN7SwSWRSg5x8m3A4yDZo=; b=YHbw8ThK5KGH5TWK/glkU1OJBcJiMPak6HN8sGFLYGPgJTqTgBn92Vv3CAXadhijRR y5yxayElF2m+tMMu9VOs6e4fXu743r+IjZUpFLYXDjd3SXs9C1kNQa2Z7ouyaFc7ozFN n3KTHLjByciwc099ih9KmjIx27b18KpJcGrEcu/rsA8TyM3NhENqKxddLGqfwglMK7U4 whXH+cgYjDkEQRaUiQjR5oxoVUCgj/PS03gTPYHEYYOraont9c9CWUeOVF6io4kERMTx h7tK5ugsA/2aM54duaRlx/eTCmo+wB6jdGIDH5QF3GtY97BNlYtKeqXoiO0Z43GFLrco Flag==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qKzySZTa; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id g13-20020a5d488d000000b00347321735a6sm7931517wrq.66.2024.04.15.05.44.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Apr 2024 05:44:34 -0700 (PDT) From: Caleb Connolly Date: Mon, 15 Apr 2024 13:44:22 +0100 Subject: [PATCH 3/3] serial: msm: calculate bit clock divider MIME-Version: 1.0 Message-Id: <20240415-b4-msm-serial-bitrate-v1-3-5a89f84fd9e7@linaro.org> References: <20240415-b4-msm-serial-bitrate-v1-0-5a89f84fd9e7@linaro.org> In-Reply-To: <20240415-b4-msm-serial-bitrate-v1-0-5a89f84fd9e7@linaro.org> To: Lukasz Majewski , Sean Anderson , Caleb Connolly , Neil Armstrong , Sumit Garg , Tom Rini Cc: Robert Marko , u-boot-qcom@groups.io, u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=7267; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=KjPPA7P49WyT2oc9h6P0tIcvUxSXbvhrv6AJT0MLtXg=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjRZRf0cneqnr2U0r0wwuyS0I9l9oYzZJ+e/pzN3bNA63 DVpzV7ejlIWBkEOBlkxRRbxE8ssm9ZettfYvuACzBxWJpAhDFycAjCRS/8Z/gq1+aczeX1uUUud oFA8ofjwtm3tpooS+muj9l/LaGD41crwP0z4i/W0JRG+Xk+1Ot77y4rtO3Fgvmgiz305xQ6eUz7 /PgEA X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The driver currently requires the bit clock divider be hardcoded in devicetree (or use the hardcoded default from apq8016). The bit clock divider is used to derive the baud rate from the core clock: baudrate = clk_rate / csr_div clk_rate is the actual programmed core clock rate which is returned by clk_set_rate(), and this UART driver only supports a baudrate of 115200. We can therefore determine the appropriate value for UARTDM_CSR by iterating over the possible values and finding the one where the equation above holds true for a baudrate of 115200. Implement this logic and drop the non-standard DT bindings for this driver. Tested on dragonboard410c. Signed-off-by: Caleb Connolly Tested-by: Robert Marko --- Cc: Robert Marko --- doc/device-tree-bindings/serial/msm-serial.txt | 10 --- drivers/serial/serial_msm.c | 87 +++++++++++++++++++++----- 2 files changed, 70 insertions(+), 27 deletions(-) diff --git a/doc/device-tree-bindings/serial/msm-serial.txt b/doc/device-tree-bindings/serial/msm-serial.txt deleted file mode 100644 index dca995798a90..000000000000 --- a/doc/device-tree-bindings/serial/msm-serial.txt +++ /dev/null @@ -1,10 +0,0 @@ -Qualcomm UART (Data Mover mode) - -Required properties: -- compatible: must be "qcom,msm-uartdm-v1.4" -- reg: start address and size of the registers -- clock: interface clock (must accept baudrate as a frequency) - -Optional properties: -- bit-rate: Data Mover bit rate register value - (If not defined then 0xCC is used as default) diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index 8044d38518db..e461929b4338 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -31,8 +31,18 @@ #define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer */ #define UARTDM_RXFS_BUF_MASK 0x7 #define UARTDM_MR1 0x00 #define UARTDM_MR2 0x04 +/* + * This is documented on page 1817 of the apq8016e technical reference manual. + * section 6.2.5.3.26 + * + * The upper nybble contains the bit clock divider for the RX pin, the lower + * nybble defines the TX pin. In almost all cases these should be the same value. + * + * The baud rate is the core clock frequency divided by the fixed divider value + * programmed into this register (defined in calc_csr_bitrate()). + */ #define UARTDM_CSR 0xA0 #define UARTDM_SR 0xA4 /* Status register */ #define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */ @@ -52,9 +62,8 @@ #define UARTDM_TF 0x100 /* UART Transmit FIFO register */ #define UARTDM_RF 0x140 /* UART Receive FIFO register */ -#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC #define MSM_BOOT_UART_DM_8_N_1_MODE 0x34 #define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10 #define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20 @@ -63,9 +72,9 @@ DECLARE_GLOBAL_DATA_PTR; struct msm_serial_data { phys_addr_t base; unsigned chars_cnt; /* number of buffered chars */ uint32_t chars_buf; /* buffered chars */ - uint32_t clk_bit_rate; /* data mover mode bit rate register value */ + uint32_t clk_rate; /* core clock rate */ }; static int msm_serial_fetch(struct udevice *dev) { @@ -155,34 +164,63 @@ static const struct dm_serial_ops msm_serial_ops = { .pending = msm_serial_pending, .getc = msm_serial_getc, }; -static int msm_uart_clk_init(struct udevice *dev) +static long msm_uart_clk_init(struct udevice *dev) { - uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), - "clock-frequency", 115200); + struct msm_serial_data *priv = dev_get_priv(dev); struct clk clk; int ret; + long rate; ret = clk_get_by_name(dev, "core", &clk); if (ret < 0) { pr_warn("%s: Failed to get clock: %d\n", __func__, ret); - return ret; + return 0; } - ret = clk_set_rate(&clk, clk_rate); - if (ret < 0) - return ret; + rate = clk_set_rate(&clk, priv->clk_rate); - return 0; + return rate; +} + +static int calc_csr_bitrate(struct msm_serial_data *priv) +{ + /* This table is from the TRE. See the definition of UARTDM_CSR */ + unsigned int csr_div_table[] = {24576, 12288, 6144, 3072, 1536, 768, 512, 384, + 256, 192, 128, 96, 64, 48, 32, 16}; + int i = ARRAY_SIZE(csr_div_table) - 1; + /* Currently we only support one baudrate */ + int baud = 115200; + + for (; i >= 0; i--) { + int x = priv->clk_rate / csr_div_table[i]; + + if (x == baud) + /* Duplicate the configuration for RX + * as the lower nybble only configures TX + */ + return i + (i << 4); + } + + return -EINVAL; } static void uart_dm_init(struct msm_serial_data *priv) { /* Delay initialization for a bit to let pins stabilize if necessary */ mdelay(5); + int bitrate = calc_csr_bitrate(priv); + if (bitrate < 0) { + log_warning("Couldn't calculate bit clock divider! Using default\n"); + /* This happens to be the value used on MSM8916 for the hardcoded clockrate + * in clock-apq8016. It's at least a better guess than a value we *know* + * is wrong... + */ + bitrate = 0xCC; + } - writel(priv->clk_bit_rate, priv->base + UARTDM_CSR); + writel(bitrate, priv->base + UARTDM_CSR); writel(0x0, priv->base + UARTDM_MR1); writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2); writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR); writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR); @@ -191,18 +229,27 @@ static void uart_dm_init(struct msm_serial_data *priv) writel(0x0, priv->base + UARTDM_DMEN); } static int msm_serial_probe(struct udevice *dev) { - int ret; struct msm_serial_data *priv = dev_get_priv(dev); + long rate; /* No need to reinitialize the UART after relocation */ if (gd->flags & GD_FLG_RELOC) return 0; - ret = msm_uart_clk_init(dev); - if (ret) - return ret; + rate = msm_uart_clk_init(dev); + if (rate < 0) + return rate; + if (!rate) { + log_err("Got core clock rate of 0... Please fix your clock driver\n"); + return -EINVAL; + } + + /* Update the clock rate to the actual programmed rate returned by the + * clock driver + */ + priv->clk_rate = rate; uart_dm_init(priv); return 0; @@ -210,15 +257,20 @@ static int msm_serial_probe(struct udevice *dev) static int msm_serial_of_to_plat(struct udevice *dev) { struct msm_serial_data *priv = dev_get_priv(dev); + int ret; priv->base = dev_read_addr(dev); if (priv->base == FDT_ADDR_T_NONE) return -EINVAL; - priv->clk_bit_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "bit-rate", UART_DM_CLK_RX_TX_BIT_RATE); + ret = dev_read_u32(dev, "clock-frequency", &priv->clk_rate); + if (ret < 0) { + log_debug("No clock frequency specified, using default rate\n"); + /* Default for APQ8016 */ + priv->clk_rate = 7372800; + } return 0; } @@ -241,8 +293,9 @@ U_BOOT_DRIVER(serial_msm) = { #ifdef CONFIG_DEBUG_UART_MSM static struct msm_serial_data init_serial_data = { .base = CONFIG_VAL(DEBUG_UART_BASE), + .clk_rate = 7372800, }; #include