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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.48.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:48:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 01/22] target/arm: Add MTE_ACTIVE to tb_flags Date: Fri, 11 Oct 2019 09:47:23 -0400 Message-Id: <20191011134744.2477-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b41 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When MTE is fully enabled, i.e. access to tags are enabled and tag checks affect the PE, then arrange to perform the check while stripping the TBI. The check is not yet implemented, just the plumbing to that point. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Clean TBI bits exactly. Fix license to lgpl 2.1. v3: Remove stub helper_mte_check; moved to a later patch. --- target/arm/cpu.h | 12 ++++++++ target/arm/internals.h | 19 ++++++++++++ target/arm/translate.h | 2 ++ target/arm/helper.c | 61 ++++++++++++++++++++++++++++++-------- target/arm/translate-a64.c | 1 + 5 files changed, 82 insertions(+), 13 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 297ad5e47a..408d749b7a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1201,6 +1201,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_BTYPE (3U << 10) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) +#define PSTATE_TCO (1U << 25) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) @@ -3196,6 +3197,7 @@ FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) FIELD(TBFLAG_A64, TBID, 12, 2) +FIELD(TBFLAG_A64, MTE_ACTIVE, 14, 1) static inline bool bswap_code(bool sctlr_b) { @@ -3598,6 +3600,16 @@ static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; } +static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; +} + +static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 232d963875..dcc5d6cca3 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -983,6 +983,7 @@ typedef struct ARMVAParameters { bool tbid : 1; bool epd : 1; bool hpd : 1; + bool tcma : 1; bool using16k : 1; bool using64k : 1; } ARMVAParameters; @@ -1007,6 +1008,24 @@ static inline int exception_target_el(CPUARMState *env) return target_el; } +/* Determine if allocation tags are available. */ +static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, + uint64_t sctlr) +{ + if (el < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_ATA)) { + return false; + } + if (el < 2 + && arm_feature(env, ARM_FEATURE_EL2) + && !(arm_hcr_el2_eff(env) & HCR_ATA)) { + return false; + } + sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA); + return sctlr != 0; +} + #ifndef CONFIG_USER_ONLY /* Security attributes for an address, as returned by v8m_security_lookup. */ diff --git a/target/arm/translate.h b/target/arm/translate.h index dd24f91f26..9913c35cc2 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -75,6 +75,8 @@ typedef struct DisasContext { bool is_ldex; /* True if v8.3-PAuth is active. */ bool pauth_active; + /* True if v8.5-MTE tag checks affect the PE. */ + bool mte_active; /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ bool bt; /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 0d9a2d2ab7..b690eda136 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1904,6 +1904,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_pauth, cpu)) { valid_mask |= SCR_API | SCR_APK; } + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |= SCR_ATA; + } /* Clear all-context RES0 bits. */ value &= valid_mask; @@ -4158,22 +4161,31 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, { ARMCPU *cpu = env_archcpu(env); - if (raw_read(env, ri) == value) { - /* Skip the TLB flush if nothing actually changed; Linux likes - * to do a lot of pointless SCTLR writes. - */ - return; - } - if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { /* M bit is RAZ/WI for PMSA with no MPU implemented */ value &= ~SCTLR_M; } - raw_write(env, ri, value); + if (!cpu_isar_feature(aa64_mte, cpu)) { + if (ri->opc1 == 6) { /* SCTLR_EL3 */ + value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); + } else { + value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | + SCTLR_ATA0 | SCTLR_ATA); + } + } + /* ??? Lots of these bits are not implemented. */ - /* This may enable/disable the MMU, so do a TLB flush. */ - tlb_flush(CPU(cpu)); + + if (raw_read(env, ri) != value) { + /* + * This may enable/disable the MMU, so do a TLB flush. + * Skip the TLB flush if nothing actually changed; + * Linux likes to do a lot of pointless SCTLR writes. + */ + raw_write(env, ri, value); + tlb_flush(CPU(cpu)); + } } static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4679,6 +4691,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_pauth, cpu)) { valid_mask |= HCR_API | HCR_APK; } + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |= HCR_ATA; + } /* Clear RES0 bits. */ value &= valid_mask; @@ -9302,7 +9317,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint32_t el = regime_el(env, mmu_idx); - bool tbi, tbid, epd, hpd, using16k, using64k; + bool tbi, tbid, epd, hpd, tcma, using16k, using64k; int select, tsz; /* @@ -9317,11 +9332,12 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, using16k = extract32(tcr, 15, 1); if (mmu_idx == ARMMMUIdx_S2NS) { /* VTCR_EL2 */ - tbi = tbid = hpd = false; + tbi = tbid = hpd = tcma = false; } else { tbi = extract32(tcr, 20, 1); hpd = extract32(tcr, 24, 1); tbid = extract32(tcr, 29, 1); + tcma = extract32(tcr, 30, 1); } epd = false; } else if (!select) { @@ -9332,6 +9348,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, tbi = extract64(tcr, 37, 1); hpd = extract64(tcr, 41, 1); tbid = extract64(tcr, 51, 1); + tcma = extract64(tcr, 57, 1); } else { int tg = extract32(tcr, 30, 2); using16k = tg == 1; @@ -9341,6 +9358,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, tbi = extract64(tcr, 38, 1); hpd = extract64(tcr, 42, 1); tbid = extract64(tcr, 52, 1); + tcma = extract64(tcr, 58, 1); } tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ @@ -9352,6 +9370,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, .tbid = tbid, .epd = epd, .hpd = hpd, + .tcma = tcma, .using16k = using16k, .using64k = using64k, }; @@ -11065,6 +11084,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (is_a64(env)) { ARMCPU *cpu = env_archcpu(env); uint64_t sctlr; + int tbid; *pc = env->pc; flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); @@ -11073,7 +11093,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, { ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); - int tbii, tbid; + int tbii; /* FIXME: ARMv8.1-VHE S2 translation regime. */ if (regime_el(env, stage1) < 2) { @@ -11126,6 +11146,21 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } + + /* + * Set MTE_ACTIVE if any access may be Checked, and leave clear + * if all accesses must be Unchecked: + * 1) If no TBI, then there are no tags in the address to check, + * 2) If Tag Check Override, then all accesses are Unchecked, + * 3) If Tag Check Fail == 0, then Checked access have no effect, + * 4) If no Allocation Tag Access, then all accesses are Unchecked. + */ + if (tbid + && !(env->pstate & PSTATE_TCO) + && (sctlr & (current_el == 0 ? SCTLR_TCF0 : SCTLR_TCF)) + && allocation_tag_access_enabled(env, current_el, sctlr)) { + flags = FIELD_DP32(flags, TBFLAG_A64, MTE_ACTIVE, 1); + } } else { *pc = env->regs[15]; flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2d6cd09634..51f3af9cd9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14161,6 +14161,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT); dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); + dc->mte_active = FIELD_EX32(tb_flags, TBFLAG_A64, MTE_ACTIVE); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; From patchwork Fri Oct 11 13:47:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175949 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp958477ocf; Fri, 11 Oct 2019 06:49:43 -0700 (PDT) X-Google-Smtp-Source: APXvYqzKS0cxXmkDOxTeGImaZ8CEFxUtR/P6/dAPHVmKqNxxdgOagzFRinFGN7o2NOezKT6TZ4ao X-Received: by 2002:a37:ab1a:: with SMTP id u26mr15923237qke.401.1570801783104; Fri, 11 Oct 2019 06:49:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570801783; cv=none; d=google.com; s=arc-20160816; b=v2NWrjRJhtPnmBPZePOY83LamkU01IX+V6kltDrZHejsijIdlJkK3CqUqhTH8aq5Co s+gYivwI4aSi/O8Z3YPadJSPZK0BDyTtwKGpQ/LIcU35zosjec2qpo2NgUQLIjG1P0pd /yq4ivjKKEpzpLQ+NqRygk5emSNQqHexZspnLTPBejP7fQLKGi8t7rMIZvORy9NQIPcQ 2T5PoiezBWuYfUsu0fM0Z/K3Uj2Qev8ZSk8DI3E+aWt/qursKUGVjs0HUWJ9QDG3yQtk tEWdPw9+kYu9GQPxqYMI+YdlQMuSD9C9SZDlcl36mhdaEeODykZNrLwwebg0+AKRbDMs rG9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=kRVYi/cd4sJBmkOfsvOkC48A2821IfvOweyDTIJZmas=; b=ObwIQrkPqzAnvrTNPihiB5sSzVCOdpnNqTUmXZKx2j1/OHxCv/wLuJIuji50h01QKp Aq2v8UdUe2/Jps1P0y6bt+jsZQdb36zLiuGOvUfQ/7vqoOBMT88JYLloLtlF7l14vwWl olBWrqm/4HdeNcpTu6yPLp9DLNvLOrdvRu3BcDIsaWn7ugl0fb5s9EdeWikUamVuZWbS L4h4izfLVSC5g9temnGZEvBtveINdMxIaddFqzsUwrpb94KIKbhNVipBfxjDj3+8Eqvp 4ayoNMhFeP9qOE24RidSW7LGeYyFoQYrvteo9kJV+ksi5tysVr6ceF/6AvgJAsuQuXxU mINQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="Yu/oJVtW"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.48.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:48:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 02/22] target/arm: Add regime_has_2_ranges Date: Fri, 11 Oct 2019 09:47:24 -0400 Message-Id: <20191011134744.2477-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c41 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" A translation with 2 ranges has both positive and negative addresses. This is true for the EL1&0 and the as-yet unimplemented EL2&0 regimes. Signed-off-by: Richard Henderson --- target/arm/internals.h | 14 ++++++++++++++ target/arm/helper.c | 22 +++++----------------- target/arm/translate-a64.c | 3 +-- 3 files changed, 20 insertions(+), 19 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/internals.h b/target/arm/internals.h index dcc5d6cca3..9486680b87 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -804,6 +804,20 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu) } } +/* Return true if this address translation regime has two ranges. */ +static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_S12NSE0: + case ARMMMUIdx_S12NSE1: + case ARMMMUIdx_S1NSE0: + case ARMMMUIdx_S1NSE1: + return true; + default: + return false; + } +} + /* Return true if this address translation regime is secure */ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) { diff --git a/target/arm/helper.c b/target/arm/helper.c index b690eda136..f9dee51ede 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8774,15 +8774,8 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, } if (is_aa64) { - switch (regime_el(env, mmu_idx)) { - case 1: - if (!is_user) { - xn = pxn || (user_rw & PAGE_WRITE); - } - break; - case 2: - case 3: - break; + if (regime_has_2_ranges(mmu_idx) && !is_user) { + xn = pxn || (user_rw & PAGE_WRITE); } } else if (arm_feature(env, ARM_FEATURE_V7)) { switch (regime_el(env, mmu_idx)) { @@ -9316,7 +9309,6 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx) { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; - uint32_t el = regime_el(env, mmu_idx); bool tbi, tbid, epd, hpd, tcma, using16k, using64k; int select, tsz; @@ -9326,7 +9318,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, */ select = extract64(va, 55, 1); - if (el > 1) { + if (!regime_has_2_ranges(mmu_idx)) { tsz = extract32(tcr, 0, 6); using64k = extract32(tcr, 14, 1); using16k = extract32(tcr, 15, 1); @@ -9486,10 +9478,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, param = aa64_va_parameters(env, address, mmu_idx, access_type != MMU_INST_FETCH); level = 0; - /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it - * invalid. - */ - ttbr1_valid = (el < 2); + ttbr1_valid = regime_has_2_ranges(mmu_idx); addrsize = 64 - 8 * param.tbi; inputsize = 64 - param.tsz; } else { @@ -11095,8 +11084,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); int tbii; - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - if (regime_el(env, stage1) < 2) { + if (regime_has_2_ranges(mmu_idx)) { ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); tbid = (p1.tbi << 1) | p0.tbi; tbii = tbid & ~((p1.tbid << 1) | p0.tbid); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 51f3af9cd9..c85db69db4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -175,8 +175,7 @@ static void gen_top_byte_ignore(DisasContext *s, TCGv_i64 dst, if (tbi == 0) { /* Load unmodified address */ tcg_gen_mov_i64(dst, src); - } else if (s->current_el >= 2) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ + } else if (!regime_has_2_ranges(s->mmu_idx)) { /* Force tag byte to all zero */ tcg_gen_extract_i64(dst, src, 0, 56); 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.48.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:48:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 03/22] target/arm: Add MTE system registers Date: Fri, 11 Oct 2019 09:47:25 -0400 Message-Id: <20191011134744.2477-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, RGSR_EL1, GCR_EL1, GMID_EL1, and PSTATE.TCO. Signed-off-by: Richard Henderson --- v3: Add GMID; add access_mte. v4: Define only TCO at mte_insn_reg. --- target/arm/cpu.h | 3 ++ target/arm/internals.h | 6 ++++ target/arm/helper.c | 73 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 11 ++++++ 4 files changed, 93 insertions(+) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 408d749b7a..d99bb5e956 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -486,6 +486,9 @@ typedef struct CPUARMState { uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ uint64_t vpidr_el2; /* Virtualization Processor ID Register */ uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ + uint64_t tfsr_el[4]; /* tfsrel0_el1 is index 0. */ + uint64_t gcr_el1; + uint64_t rgsr_el1; } cp15; struct { diff --git a/target/arm/internals.h b/target/arm/internals.h index 9486680b87..bfa243be06 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1079,4 +1079,10 @@ void arm_log_exception(int idx); #endif /* !CONFIG_USER_ONLY */ +/* + * The log2 of the words in the tag block, for GMID_EL1.BS. + * The is the maximum, 256 bytes, which manipulates 64-bits of tags. + */ +#define GMID_EL1_BS 6 + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index f9dee51ede..f435a8d8bd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5921,6 +5921,73 @@ static const ARMCPRegInfo rndr_reginfo[] = { .access = PL0_R, .readfn = rndr_readfn }, REGINFO_SENTINEL }; + +static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el = arm_current_el(env); + + if (el < 2 && + arm_feature(env, ARM_FEATURE_EL2) && + !(arm_hcr_el2_eff(env) & HCR_ATA)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && + arm_feature(env, ARM_FEATURE_EL3) && + !(env->cp15.scr_el3 & SCR_ATA)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_TCO; +} + +static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) +{ + env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); +} + +static const ARMCPRegInfo mte_reginfo[] = { + { .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 6, .crm = 6, .opc2 = 1, + .access = PL1_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) }, + { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 6, .crm = 5, .opc2 = 0, + .access = PL1_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) }, + { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 5, .opc2 = 0, + .access = PL2_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) }, + { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 6, .opc2 = 0, + .access = PL3_RW, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) }, + { .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5, + .access = PL1_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) }, + { .name = "GCR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, + .access = PL1_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, + { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo mte_tco_reginfo[] = { + { .name = "TCO", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, + .type = ARM_CP_NO_RAW, + .access = PL0_RW, .readfn = tco_read, .writefn = tco_write }, + REGINFO_SENTINEL +}; #endif static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, @@ -6881,6 +6948,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_rndr, cpu)) { define_arm_cp_regs(cpu, rndr_reginfo); } + if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { + define_arm_cp_regs(cpu, mte_tco_reginfo); + } + if (cpu_isar_feature(aa64_mte, cpu)) { + define_arm_cp_regs(cpu, mte_reginfo); + } #endif /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c85db69db4..62bdf50796 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1611,6 +1611,17 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, s->base.is_jmp = DISAS_UPDATE; break; + case 0x1c: /* TCO */ + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_TCO); + } else { + clear_pstate_bits(PSTATE_TCO); + } + break; + default: do_unallocated: unallocated_encoding(s); From patchwork Fri Oct 11 13:47:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175955 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp964173ocf; Fri, 11 Oct 2019 06:54:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqxj3aFnEOLuVAOPQcD57N/0ws3ucH9Eg2CuALji9v3C3NrTBBx1RWQK4ddmuXm+vFE00Ppp X-Received: by 2002:ac8:73d5:: with SMTP id v21mr16734065qtp.337.1570802080176; Fri, 11 Oct 2019 06:54:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570802080; cv=none; d=google.com; s=arc-20160816; b=VMA1MBkWHS+Q0TJbRusbtLMXFC5v/u/iR8SPKsCrSCaU/6WGx1ny+paQuRHr+5VKVp tx+g1SrFtNjlgQ4bLvQzEq90IfHiene5Zde9KPGSGWI/9/3P7XtsxiC235dEmJc52aAV BsJM71d8mVACXr/mO5YtESu4taWZB6aBxOsPX+0e08ggKm2E9q2fLAaZwNAq1UV1vQsX fB3wiNvLo+F0HxeUajGLbPl+xvWzLqXNeuBaIks+JGVosOXgTPhs0qi2VkcDZ0reWU1+ Oge19xFqo5UpoZijB6haN/hSZdHNyQOjNzJI/0E9xyoYQtemi82bWIaI7mbqjFhAeQ3a 0ZYg== ARC-Message-Signature: i=1; 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.48.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:49:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 04/22] target/arm: Add helper_mte_check{1,2,3} Date: Fri, 11 Oct 2019 09:47:26 -0400 Message-Id: <20191011134744.2477-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b30 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implements the rules of "PE generation of Checked and Unchecked accesses" which aren't already implied by TB_FLAGS_MTE_ACTIVE. Implements the rules of "PE handling of Tag Check Failure". Does not implement tag physical address space, so all operations reduce to unchecked so far. Signed-off-by: Richard Henderson --- v2: Fix TFSR update. v3: Split helper_mte_check per {1,2} IAs; take tbi data from translate. v5: Split helper_mte_check3, the only one that needs a runtime check for tbi. --- target/arm/helper-a64.h | 4 + target/arm/mte_helper.c | 167 +++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 15 +++- target/arm/Makefile.objs | 1 + 4 files changed, 186 insertions(+), 1 deletion(-) create mode 100644 target/arm/mte_helper.c -- 2.17.1 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index a915c1247f..a82e21f15a 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -102,3 +102,7 @@ DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) + +DEF_HELPER_FLAGS_2(mte_check1, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(mte_check2, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_3(mte_check3, TCG_CALL_NO_WG, i64, env, i64, i32) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c new file mode 100644 index 0000000000..bbb90cbe86 --- /dev/null +++ b/target/arm/mte_helper.c @@ -0,0 +1,167 @@ +/* + * ARM v8.5-MemTag Operations + * + * Copyright (c) 2019 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "exec/cpu_ldst.h" +#include "exec/helper-proto.h" + + +static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) +{ + /* Tag storage not implemented. */ + return -1; +} + +static int allocation_tag_from_addr(uint64_t ptr) +{ + ptr += 1ULL << 55; /* carry ptr[55] into ptr[59:56]. */ + return extract64(ptr, 56, 4); +} + +/* + * Perform a checked access for MTE. + * On arrival, TBI is known to enabled, as is allocation_tag_access_enabled. + */ +static uint64_t do_mte_check(CPUARMState *env, uint64_t dirty_ptr, + uint64_t clean_ptr, uint32_t select, + uintptr_t ra) +{ + ARMMMUIdx stage1 = arm_stage1_mmu_idx(env); + int ptr_tag, mem_tag; + + /* + * If TCMA is enabled, then physical tag 0 is unchecked. + * Note the rules in D6.8.1 are written with logical tags, where + * the corresponding physical tag rule is simpler: equal to 0. + * We will need the physical tag below anyway. + */ + ptr_tag = allocation_tag_from_addr(dirty_ptr); + if (ptr_tag == 0) { + ARMVAParameters p = aa64_va_parameters(env, dirty_ptr, stage1, true); + if (p.tcma) { + return clean_ptr; + } + } + + /* + * If an access is made to an address that does not provide tag + * storage, the result is IMPLEMENTATION DEFINED. We choose to + * treat the access as unchecked. + * This is similar to MemAttr != Tagged, which are also unchecked. + */ + mem_tag = get_allocation_tag(env, clean_ptr, ra); + if (mem_tag < 0) { + return clean_ptr; + } + + /* If the tags do not match, the tag check operation fails. */ + if (unlikely(ptr_tag != mem_tag)) { + int el, regime_el, tcf; + uint64_t sctlr; + + el = arm_current_el(env); + regime_el = (el ? el : 1); /* TODO: ARMv8.1-VHE EL2&0 regime */ + sctlr = env->cp15.sctlr_el[regime_el]; + if (el == 0) { + tcf = extract64(sctlr, 38, 2); + } else { + tcf = extract64(sctlr, 40, 2); + } + + switch (tcf) { + case 1: + /* + * Tag check fail causes a synchronous exception. + * + * In restore_state_to_opc, we set the exception syndrome + * for the load or store operation. Do that first so we + * may overwrite that with the syndrome for the tag check. + */ + cpu_restore_state(env_cpu(env), ra, true); + env->exception.vaddress = dirty_ptr; + raise_exception(env, EXCP_DATA_ABORT, + syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, 0x11), + exception_target_el(env)); + /* noreturn; fall through to assert anyway */ + + case 0: + /* + * Tag check fail does not affect the PE. + * We eliminate this case by not setting MTE_ACTIVE + * in tb_flags, so that we never make this runtime call. + */ + g_assert_not_reached(); + + case 2: + /* Tag check fail causes asynchronous flag set. */ + env->cp15.tfsr_el[regime_el] |= 1 << select; + break; + + default: + /* Case 3: Reserved. */ + qemu_log_mask(LOG_GUEST_ERROR, + "Tag check failure with SCTLR_EL%d.TCF " + "set to reserved value %d\n", regime_el, tcf); + break; + } + } + + return clean_ptr; +} + +/* + * Perform check in translation regime w/single IA range. + * It is known that TBI is enabled on entry. + */ +uint64_t HELPER(mte_check1)(CPUARMState *env, uint64_t dirty_ptr) +{ + uint64_t clean_ptr = extract64(dirty_ptr, 0, 56); + return do_mte_check(env, dirty_ptr, clean_ptr, 0, GETPC()); +} + +/* + * Perform check in translation regime w/two IA ranges. + * It is known that TBI is enabled on entry. + */ +uint64_t HELPER(mte_check2)(CPUARMState *env, uint64_t dirty_ptr) +{ + uint32_t select = extract64(dirty_ptr, 55, 1); + uint64_t clean_ptr = sextract64(dirty_ptr, 0, 56); + return do_mte_check(env, dirty_ptr, clean_ptr, select, GETPC()); +} + +/* + * Perform check in translation regime w/two IA ranges. + * The TBI argument is the concatenation of TBI1:TBI0. + */ +uint64_t HELPER(mte_check3)(CPUARMState *env, uint64_t dirty_ptr, uint32_t tbi) +{ + uint32_t select = extract64(dirty_ptr, 55, 1); + uint64_t clean_ptr = sextract64(dirty_ptr, 0, 56); + + if ((tbi >> select) & 1) { + return do_mte_check(env, dirty_ptr, clean_ptr, select, GETPC()); + } else { + /* TBI is disabled; the access is unchecked. */ + return dirty_ptr; + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 62bdf50796..8e4fea6b4c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -214,7 +214,20 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) { TCGv_i64 clean = new_tmp_a64(s); - gen_top_byte_ignore(s, clean, addr, s->tbid); + + /* Note that s->mte_active already includes a check for s->tbid != 0. */ + if (!s->mte_active) { + gen_top_byte_ignore(s, clean, addr, s->tbid); + } else if (!regime_has_2_ranges(s->mmu_idx)) { + gen_helper_mte_check1(clean, cpu_env, addr); + } else if (s->tbid == 3) { + /* Both TBI1:TBI0 are set; no need to check at runtime. */ + gen_helper_mte_check2(clean, cpu_env, addr); + } else { + TCGv_i32 tbi = tcg_const_i32(s->tbid); + gen_helper_mte_check3(clean, cpu_env, addr, tbi); + tcg_temp_free_i32(tbi); + } return clean; } diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index cf26c16f5f..8fd7d086c8 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -67,3 +67,4 @@ obj-$(CONFIG_SOFTMMU) += psci.o obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o obj-$(TARGET_AARCH64) += pauth_helper.o +obj-$(TARGET_AARCH64) += mte_helper.o From patchwork Fri Oct 11 13:47:27 2019 Content-Type: text/plain; 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.49.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:49:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 05/22] target/arm: Suppress tag check for sp+offset Date: Fri, 11 Oct 2019 09:47:27 -0400 Message-Id: <20191011134744.2477-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" R0078 specifies that base register, or base register plus immediate offset, is unchecked when the base register is SP. Signed-off-by: Richard Henderson --- v2: Include writeback addresses as checked. --- target/arm/translate-a64.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8e4fea6b4c..18d45fba87 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -211,12 +211,12 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) * This is always a fresh temporary, as we need to be able to * increment this independently of a dirty write-back address. */ -static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) +static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr, bool check) { TCGv_i64 clean = new_tmp_a64(s); /* Note that s->mte_active already includes a check for s->tbid != 0. */ - if (!s->mte_active) { + if (!check || !s->mte_active) { gen_top_byte_ignore(s, clean, addr, s->tbid); } else if (!regime_has_2_ranges(s->mmu_idx)) { gen_helper_mte_check1(clean, cpu_env, addr); @@ -2334,7 +2334,7 @@ static void gen_compare_and_swap(DisasContext *s, int rs, int rt, if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, size | MO_ALIGN | s->be_data); } @@ -2352,7 +2352,7 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); if (size == 2) { TCGv_i64 cmp = tcg_temp_new_i64(); @@ -2477,7 +2477,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); return; @@ -2486,7 +2486,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); s->is_ldex = true; gen_load_exclusive(s, rt, rt2, clean_addr, size, false); if (is_lasr) { @@ -2506,7 +2506,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) gen_check_sp_alignment(s); } tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; @@ -2522,7 +2522,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -2536,7 +2536,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); return; } @@ -2554,7 +2554,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); s->is_ldex = true; gen_load_exclusive(s, rt, rt2, clean_addr, size, true); if (is_lasr) { @@ -2744,7 +2744,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) if (!postindex) { tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, wback || rn != 31); if (is_vector) { if (is_load) { @@ -2882,7 +2882,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, if (!post_index) { tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); } - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, writeback || rn != 31); if (is_vector) { if (is_store) { @@ -2989,7 +2989,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, true); if (is_vector) { if (is_store) { @@ -3074,7 +3074,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, dirty_addr = read_cpu_reg_sp(s, rn, 1); offset = imm12 << size; tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, rn != 31); if (is_vector) { if (is_store) { @@ -3158,7 +3158,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31); tcg_rs = read_cpu_reg(s, rs, true); if (o3_opc == 1) { /* LDCLR */ @@ -3220,7 +3220,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); /* Note that "clean" and "dirty" here refer to TBI not PAC. */ - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, is_wback || rn != 31); tcg_rt = cpu_reg(s, rt); do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, @@ -3380,7 +3380,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) elements = (is_q ? 16 : 8) / ebytes; tcg_rn = cpu_reg_sp(s, rn); - clean_addr = clean_data_tbi(s, tcg_rn); + clean_addr = clean_data_tbi(s, tcg_rn, is_postidx || rn != 31); tcg_ebytes = tcg_const_i64(ebytes); for (r = 0; r < rpt; r++) { @@ -3523,7 +3523,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) } tcg_rn = cpu_reg_sp(s, rn); - clean_addr = clean_data_tbi(s, tcg_rn); + clean_addr = clean_data_tbi(s, tcg_rn, is_postidx || rn != 31); tcg_ebytes = tcg_const_i64(ebytes); for (xs = 0; xs < selem; xs++) { From patchwork Fri Oct 11 13:47:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175952 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp961979ocf; Fri, 11 Oct 2019 06:52:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqyJdm9xGFYpYFgtIDZZNxV9C89AQBrAWB/i1dYQmGrQ7Ld26KKk7JCfWokAoBEL1TN7CK1n X-Received: by 2002:a17:906:6d08:: with SMTP id m8mr13879234ejr.150.1570801953221; Fri, 11 Oct 2019 06:52:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570801953; cv=none; d=google.com; s=arc-20160816; b=IharQFizu3HsyuopiqDFTJvEvL7IS0JB2OqgMJDusKlyyKfh9bvL/U+2hy9qIi+AbO BHBTaSaS+QxDjNxQ9JEBlUesecBjBaeJR3vx/eWoKVtRWqBeoCV5xhBDazUrshMzwcXu qLqVvgz21cw88XbdqYmGl8g2Wz1BhL8JN5vXk61HiwyKbA75jdcYj2fP2VyaIjHXg2Jg v8SJm2YZWFdnuJX82iTwTnhdylB3nKZyyogrGHzhF5qbGVVtR6B88MCXZyKFQZs6mro4 oE82rP+1v1/Z/3VU+Gd/dkgMF2/4IQrGDNR7Rn4QeXK45xAypkW5JD8yieBvKXLD0KIe tGYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=DBn82VDoTIkQHKrcIDGuEVCWKjWKbpPGI9lxXV47UXY=; b=RGQoZlk4/l0N2Fc2rD7rDSOxxZrYlkuXPksz5VBuWTz2ktExKla/w3fPLEQam5N0WK O8c0sEi4xCATNmPhtweqlcz+XOKiuPvOFqtQt1fbchMeFEJi0e5OSmnUdQV6ew09c9f+ mvjYb60SIo00Thjf2T3+NgFc4WLi/tBuBueMLzuhJZcCLlS8L7BszL+voek/rpWKDjY3 aC2RuFbO5vqTiuQ5XElNoTV8DMWPgZ3eL3ZJR7TQRwPhHtbsmwwKIBCybgKObRFWRs5l mVmxE5qTfJ2mVPziGZhX+/XnKm+o1R/Pj69J3XKR3Ku1LlMq619fISsCg2Nchfw5efMf OXMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ufd5x4g0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.49.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:49:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 06/22] target/arm: Implement the IRG instruction Date: Fri, 11 Oct 2019 09:47:28 -0400 Message-Id: <20191011134744.2477-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- v2: Update to 00eac5. Merge choose_random_nonexcluded_tag into helper_irg since that pseudo function no longer exists separately. --- target/arm/helper-a64.h | 1 + target/arm/mte_helper.c | 57 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 7 +++++ 3 files changed, 65 insertions(+) -- 2.17.1 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index a82e21f15a..6ff7f5b756 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -106,3 +106,4 @@ DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(mte_check1, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(mte_check2, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(mte_check3, TCG_CALL_NO_WG, i64, env, i64, i32) +DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index bbb90cbe86..9848849a91 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -37,6 +37,31 @@ static int allocation_tag_from_addr(uint64_t ptr) return extract64(ptr, 56, 4); } +static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) +{ + if (exclude == 0xffff) { + return 0; + } + if (offset == 0) { + while (exclude & (1 << tag)) { + tag = (tag + 1) & 15; + } + } else { + do { + do { + tag = (tag + 1) & 15; + } while (exclude & (1 << tag)); + } while (--offset > 0); + } + return tag; +} + +static uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) +{ + rtag -= extract64(ptr, 55, 1); + return deposit64(ptr, 56, 4, rtag); +} + /* * Perform a checked access for MTE. * On arrival, TBI is known to enabled, as is allocation_tag_access_enabled. @@ -165,3 +190,35 @@ uint64_t HELPER(mte_check3)(CPUARMState *env, uint64_t dirty_ptr, uint32_t tbi) return dirty_ptr; } } + +uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + int rtag = 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + /* + * Our IMPDEF choice for GCR_EL1.RRND==1 is to behave as if + * GCR_EL1.RRND==0, always producing deterministic results. + */ + uint16_t exclude = extract32(rm | env->cp15.gcr_el1, 0, 16); + int start = extract32(env->cp15.rgsr_el1, 0, 4); + int seed = extract32(env->cp15.rgsr_el1, 8, 16); + int offset, i; + + /* RandomTag */ + for (i = offset = 0; i < 4; ++i) { + /* NextRandomTagBit */ + int top = (extract32(seed, 5, 1) ^ extract32(seed, 3, 1) ^ + extract32(seed, 2, 1) ^ extract32(seed, 0, 1)); + seed = (top << 15) | (seed >> 1); + offset |= top << i; + } + rtag = choose_nonexcluded_tag(start, offset, exclude); + + env->cp15.rgsr_el1 = rtag | (seed << 8); + } + + return address_with_allocation_tag(rn, rtag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 18d45fba87..83d253d67f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5156,6 +5156,13 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) case 3: /* SDIV */ handle_div(s, true, sf, rm, rn, rd); break; + case 4: /* IRG */ + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, + cpu_reg_sp(s, rn), cpu_reg(s, rm)); + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break; From patchwork Fri Oct 11 13:47:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175950 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp960261ocf; Fri, 11 Oct 2019 06:51:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqw6jm6xY19NtTrk24JNNV0WCxsOC95wDCKRRHCk94m5camtNBqETmJgK9vErTPwEBCoW2iW X-Received: by 2002:a17:906:4a95:: with SMTP id x21mr14229206eju.18.1570801868834; Fri, 11 Oct 2019 06:51:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570801868; cv=none; d=google.com; s=arc-20160816; b=tqFb4PSknXFPlzPkey9E9bY7kZFAvjymVEaL2Rbt0M9ktnbq9S9EQbGjcr+T7zMEvb ZbnobtqLrXvrGqO2UfGUxvU3QjUuMnp/xOjprhWS4Omagi0hTDMPoAayNCae1cTdTdM9 KMOHMltfkfQVirHguFi8+zi/tgkWCu8IkDzE+t2O5kYXWq36MhcNoNy2bDD1HORuv+8m OdHlU1KLjFTBNINOfHPwLaRbMD38UJZI6gS4MiBM6Yh6DVCTH/uzWAmcGpd/JEq2ZcAU zonxs6H0nwQzVHG7Vgs1piTmRE5jPZ0NW2oZ+235p2M6aYxA/ksV3y0XpzvrSEjQmu/4 qNDQ== ARC-Message-Signature: i=1; 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.49.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:49:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 07/22] target/arm: Implement ADDG, SUBG instructions Date: Fri, 11 Oct 2019 09:47:29 -0400 Message-Id: <20191011134744.2477-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b41 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Shift offset in translate; use extract32. --- target/arm/helper-a64.h | 2 ++ target/arm/internals.h | 4 +++ target/arm/mte_helper.c | 32 +++++++++++++++++ target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++------------ 4 files changed, 86 insertions(+), 23 deletions(-) -- 2.17.1 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 6ff7f5b756..268c114b79 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -107,3 +107,5 @@ DEF_HELPER_FLAGS_2(mte_check1, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(mte_check2, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(mte_check3, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) +DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index bfa243be06..a434743b15 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1085,4 +1085,8 @@ void arm_log_exception(int idx); */ #define GMID_EL1_BS 6 +/* We associate one allocation tag per 16 bytes, the minimum. */ +#define LOG2_TAG_GRANULE 4 +#define TAG_GRANULE (1 << LOG2_TAG_GRANULE) + #endif diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 9848849a91..c3edc51bba 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -222,3 +222,35 @@ uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) return address_with_allocation_tag(rn, rtag); } + +uint64_t HELPER(addg)(CPUARMState *env, uint64_t ptr, + uint32_t offset, uint32_t tag_offset) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + int rtag = 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int start_tag = allocation_tag_from_addr(ptr); + uint16_t exclude = extract32(env->cp15.gcr_el1, 0, 16); + rtag = choose_nonexcluded_tag(start_tag, tag_offset, exclude); + } + + return address_with_allocation_tag(ptr + offset, rtag); +} + +uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr, + uint32_t offset, uint32_t tag_offset) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + int rtag = 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int start_tag = allocation_tag_from_addr(ptr); + uint16_t exclude = extract32(env->cp15.gcr_el1, 0, 16); + rtag = choose_nonexcluded_tag(start_tag, tag_offset, exclude); + } + + return address_with_allocation_tag(ptr - offset, rtag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 83d253d67f..26aee0c1c9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3628,7 +3628,9 @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) * sf: 0 -> 32bit, 1 -> 64bit * op: 0 -> add , 1 -> sub * S: 1 -> set flags - * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12 + * shift: 00 -> LSL imm by 0, + * 01 -> LSL imm by 12 + * 10 -> ADDG, SUBG */ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) { @@ -3639,10 +3641,10 @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) bool setflags = extract32(insn, 29, 1); bool sub_op = extract32(insn, 30, 1); bool is_64bit = extract32(insn, 31, 1); + bool is_tag = false; TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); - TCGv_i64 tcg_result; switch (shift) { case 0x0: @@ -3650,35 +3652,58 @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) case 0x1: imm <<= 12; break; + case 0x2: + /* ADDG, SUBG */ + if (!is_64bit || setflags || (imm & 0x30) || + !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + is_tag = true; + break; default: + do_unallocated: unallocated_encoding(s); return; } - tcg_result = tcg_temp_new_i64(); - if (!setflags) { - if (sub_op) { - tcg_gen_subi_i64(tcg_result, tcg_rn, imm); - } else { - tcg_gen_addi_i64(tcg_result, tcg_rn, imm); - } - } else { - TCGv_i64 tcg_imm = tcg_const_i64(imm); - if (sub_op) { - gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); - } else { - gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); - } - tcg_temp_free_i64(tcg_imm); - } + if (is_tag) { + TCGv_i32 tag_offset = tcg_const_i32(imm & 15); + TCGv_i32 offset = tcg_const_i32((imm >> 6) << LOG2_TAG_GRANULE); - if (is_64bit) { - tcg_gen_mov_i64(tcg_rd, tcg_result); + if (sub_op) { + gen_helper_subg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); + } else { + gen_helper_addg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); + } + tcg_temp_free_i32(tag_offset); + tcg_temp_free_i32(offset); } else { - tcg_gen_ext32u_i64(tcg_rd, tcg_result); - } + TCGv_i64 tcg_result; - tcg_temp_free_i64(tcg_result); + if (!setflags) { + tcg_result = tcg_rd; + if (sub_op) { + tcg_gen_subi_i64(tcg_result, tcg_rn, imm); + } else { + tcg_gen_addi_i64(tcg_result, tcg_rn, imm); + } + } else { + TCGv_i64 tcg_imm = tcg_const_i64(imm); + tcg_result = new_tmp_a64(s); + if (sub_op) { + gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); + } else { + gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); + } + tcg_temp_free_i64(tcg_imm); + } + + if (is_64bit) { + tcg_gen_mov_i64(tcg_rd, tcg_result); + } else { + tcg_gen_ext32u_i64(tcg_rd, tcg_result); + } + } } /* The input should be a value in the bottom e bits (with higher From patchwork Fri Oct 11 13:47:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175954 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp963472ocf; Fri, 11 Oct 2019 06:54:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqzalHBpsHzriNABoKsS9mXQACRPT/ix9spZlccVXhybs7U2JypaBIdDS+NeXAUFgxC+kwzp X-Received: by 2002:ac8:368b:: with SMTP id a11mr16935144qtc.362.1570802043160; Fri, 11 Oct 2019 06:54:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570802043; cv=none; d=google.com; s=arc-20160816; b=u3oa9ob+7JvyCcQK5/g3TwEaADWcCC4+V6h6CihifWcHvcnS7kC7PparZQhb5utPbf O0QKVR79Y7DaxzxFvtEVx12t31a5wYMsD/4BNAicZi1zv3jj67lAqKYLz3DHewGaKD8s mwNhJHtBbEFzoADsS0gic2mcIeC6QF2nupNWxRl1OC7PNE433aXCPd9XJY1JCQWb1KRc aT5NmqHuOXxmyEnt8bceNeu1DI9mUw49FOIKJJbDqGSB17aOgZwVk4GC5jyQ5wjsjWtE bPA7aePJ3osCGdx+C6A421q2Jpd53UBUVcZYa8ottjZHiZ8BzlMn4cEcKtHdEyGUMcg6 kXNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=o8+XY/UcseGCyRDxlQOhrRq4L82DVUKd4GlR/wFLdGQ=; b=bzY1+UDerIUPoKDZ32n4caQOU7ygX/erj/g82BSS+z50EXwfxvDEBDvjyb2lluqRs6 7QgqQ0d3z46rYCDvPIHSHx06/9FX0SgF85VKUV3yzZ2OyT3DciYbSmrYrAOLSRt8HAgb OjIsqEZMUzb8waPBMEtUz4Oozu+AGpI8nT8X0UatU/zs17N7N1HdiR+QPhXNh/neSMqP /5/M/rSZTboOLt37eUMb2Cb8QitErpXmj+OgMxN1nBnMZ/Rjrj+uUZi1sAkQ0ia2Bgbs sVsRKPxoMTxr2sJCfsdWXvFDLRRz10nQIzzrOCc/HFjsUPCYTC9ik3w0/A5Q+WTGGMu+ T0zA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XxMkP3cu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.49.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:50:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 08/22] target/arm: Implement the GMI instruction Date: Fri, 11 Oct 2019 09:47:30 -0400 Message-Id: <20191011134744.2477-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c41 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 1 + target/arm/mte_helper.c | 6 ++++++ target/arm/translate-a64.c | 6 ++++++ 3 files changed, 13 insertions(+) -- 2.17.1 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 268c114b79..31f848ca03 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -109,3 +109,4 @@ DEF_HELPER_FLAGS_3(mte_check3, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) +DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index c3edc51bba..251dfff1e1 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -254,3 +254,9 @@ uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr, return address_with_allocation_tag(ptr - offset, rtag); } + +uint64_t HELPER(gmi)(uint64_t ptr, uint64_t mask) +{ + int tag = allocation_tag_from_addr(ptr); + return mask | (1ULL << tag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 26aee0c1c9..4184d65d97 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5188,6 +5188,12 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, cpu_reg_sp(s, rn), cpu_reg(s, rm)); break; + case 5: /* GMI */ + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + gen_helper_gmi(cpu_reg(s, rd), cpu_reg_sp(s, rn), cpu_reg(s, rm)); + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break; From patchwork Fri Oct 11 13:47:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175953 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp961981ocf; Fri, 11 Oct 2019 06:52:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqzPsD4t82UKEfqHoTQ9nAkQv0JjWo+MxlvHd24Rd/gJgj1cl3ZyYmvT30YnH5uA35/l6vTH X-Received: by 2002:aa7:d908:: with SMTP id a8mr13628181edr.49.1570801953332; Fri, 11 Oct 2019 06:52:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570801953; cv=none; d=google.com; s=arc-20160816; b=oX08sXqBARx74W5JocvrYDcDJdwM3s7leFC6DkGnYrCugQ0VeCP0oTpwnzoYmv1ZTp rE14eOwIcCf9xK8uv6WZa+joMw+w6qTbw47M/bPAh+6Ook4At2k3n8WHOSbfodIzjMaF Q9K1qX2P33og5eeeDWM5mi/iZIWm7PZYUYRtzTP6fwAjvoG9xKdZAhJtK4lF9x9DuklR wsPBXurJSoYicbcnqYJwIVN338h3rFwMWC0pIiaHoT+oS4ke465yJosO1g4mUwRc/tVZ yO9anzterOunBWg2rh91KDBzsUNRkH+xfkVx643qQjsq6gUWlZnpxwZU2aaggDSk0h+U UXbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=pcMD6K9ABOmTlLHKMBTY6fPd9eU2rhpEHRshToPyGV0=; b=KaPgsnLhxRkDlZUXF0+gVTl0gDt4NbcoT+NzMbZoI88Jz1kVshx5rHhje3GO3le3Kt GPpKetEyyFyUrIa0jjNyZD5A1Vm1mkm/L2sM+ZYDcY2RiuQBpsM65eVqh9amY/RSxHAx 6r+g3cSLtyBY2Q7vuUsxUan6gQZOlAJKBsltSWO7ZrMnkCNtQdJr/0Q8eASGMfZy+hrC mDGBNXiZZb6sDxyYs0Hq/CsddyL/CO04UBJl/NKfhrs6Ng8xnvdT9bjC79HMTkFZDMb1 Gd5tlrV4WY2tC48oVwG6nyHP1POAFAUaqxCq257W3KlxglRIJMp3Ze6hmRi2qQpKuCic 9eyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dGxHV+m5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.50.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:50:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 09/22] target/arm: Implement the SUBP instruction Date: Fri, 11 Oct 2019 09:47:31 -0400 Message-Id: <20191011134744.2477-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Fix extraction length. --- target/arm/translate-a64.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4184d65d97..cf341c98d3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5162,19 +5162,39 @@ static void handle_crc32(DisasContext *s, */ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) { - unsigned int sf, rm, opcode, rn, rd; + unsigned int sf, rm, opcode, rn, rd, setflag; sf = extract32(insn, 31, 1); + setflag = extract32(insn, 29, 1); rm = extract32(insn, 16, 5); opcode = extract32(insn, 10, 6); rn = extract32(insn, 5, 5); rd = extract32(insn, 0, 5); - if (extract32(insn, 29, 1)) { + if (setflag && opcode != 0) { unallocated_encoding(s); return; } switch (opcode) { + case 0: /* SUBP(S) */ + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } else { + TCGv_i64 tcg_n, tcg_m, tcg_d; + + tcg_n = read_cpu_reg_sp(s, rn, true); + tcg_m = read_cpu_reg_sp(s, rm, true); + tcg_gen_sextract_i64(tcg_n, tcg_n, 0, 56); + tcg_gen_sextract_i64(tcg_m, tcg_m, 0, 56); + tcg_d = cpu_reg(s, rd); + + if (setflag) { + gen_sub_CC(true, tcg_d, tcg_n, tcg_m); + } else { + tcg_gen_sub_i64(tcg_d, tcg_n, tcg_m); + } + } + break; case 2: /* UDIV */ handle_div(s, false, sf, rm, rn, rd); break; From patchwork Fri Oct 11 13:47:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175959 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp967537ocf; Fri, 11 Oct 2019 06:58:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqxEPxP1cqWO2xfXyMzjvkITI5Ztm63nJ3Kho7/jqT3OLOKqaZ8i4vqfoaMPjdAhBz00WF7a X-Received: by 2002:a05:6214:1ca:: with SMTP id c10mr16192070qvt.233.1570802280027; Fri, 11 Oct 2019 06:58:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570802280; cv=none; d=google.com; s=arc-20160816; b=dcov9G5Jex+5TVPSyZOet82qrjoIJYTE5yVNjKK37IRUJ1VzCzMv3R0uHwUDxhsDmo M2XINKy+f4+IE9xmfX846koT4jHWuQKZAjuBgEgx2PGmAVI7FehCV+jI3IJdtlYnL5dG 7UTuERzepXXD877qPicZYgFt1ZOUrohAh9iwqyL4tPv99QhNbJN1sLt3qSY+I/UgNygU tr17qDKZ9fiXk59TTzF2/1CSxH75Tx2v0JtFJGGDzJHHJW6BxCcT1AG6GdR5yU/XcEdl 4zb3AJoKBpWhd1pNFD/VLXmqMji6DXNkTez7ZIwa0f3im5xkFCra9rH73iRQYSmcRVYp c91A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=loK2jdE9Lal6vbE+5e7UnQvjF9Y+wxx/GDkdqZVvRmE=; b=RMMvMTpa/YDEr9ZmkBTtbrHXtKCCUzNJvngt5QrMJwUqOg6OEBGsxhVroNnpmwEXcx UZP1MZpODWWMsgmnCqFmbmBWJ+6KqSLn1WrOM0WlGRPbBN4AEjxD32SzMxJwRDU4euzj bNjYpXnYK0AEts5zPU1Nz6va4RWZODcMyknR43wSXEgpdL8pSyIuuWhyqZsnTRSCNefD EDHJjq/yryk31T/aO50uZXzOwKQvPCNMHfDo1ZcIWdvB5HSNN8y5loQk0G0bXdGuLdyR pguDZu6MQXnqMFIUdtDc8nGmCu1qExBKXU85I5an6VK4ApBxuc79u5Lx0clvpx8SjHOw +/oA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rgQUFRww; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.50.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:50:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 10/22] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY Date: Fri, 11 Oct 2019 09:47:32 -0400 Message-Id: <20191011134744.2477-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b41 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will need this to raise unaligned exceptions from user mode. Signed-off-by: Richard Henderson --- target/arm/tlb_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- 2.17.1 diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 5feb312941..29b92a1149 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -10,8 +10,6 @@ #include "internals.h" #include "exec/exec-all.h" -#if !defined(CONFIG_USER_ONLY) - static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, bool same_el, bool ea, @@ -122,6 +120,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } +#ifndef CONFIG_USER_ONLY /* * arm_cpu_do_transaction_failed: handle a memory system error response * (eg "no device/memory present at address") by raising an external abort From patchwork Fri Oct 11 13:47:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175957 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp966023ocf; Fri, 11 Oct 2019 06:56:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqz7pALBQM1LkwbaaeMEeY28VOOmyZrpUx4FiRY4Hx7vKmpR+F/aYAZXCo7OY/vo7OXOPPE4 X-Received: by 2002:a05:620a:2051:: with SMTP id d17mr15570905qka.310.1570802189247; Fri, 11 Oct 2019 06:56:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570802189; cv=none; d=google.com; s=arc-20160816; b=jtRP7C5DEwptP9BHtIzbiV2tm8nlPhk9KrBYN9nRxBqRsaGA6pvbqFy8rsx/ml6byb NdIc7yRgvW7nafS1eJSxULnyY9Yki4ubjbKO2rAj3VVLHKIHV6mR1NaR5g3rSe/M5ipG E6R3lhV9YgKmrkGl7SFi7Kaoo4SWaCCDK/URURBcSg1LNz4Q52HBQZObFkoh/5HTXK8k 1GL4nC2xRhlH07mFBCrJigddwodD0q9E2EGuoWEv4HhasgIRIeyseu3ZyZz5Kj0whgvB XXdKlPZYYa6H/gz/lvpNDL93yGyZLVjlQJA575FIDY6u8yOGt1K6NnB5aBg6AczGRdel jbkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=gkEtlZocr6O/mWH7/aygI9iXL6Dz4HHREZjJWg4Qrng=; b=g3c1Zt8DB1Y7kz4V/1d7uVi/pZjoFn1Oe+tUBLHYgr2PBq/z5V9um5NUpwGmfI0+Rk D1g7kQNHzeHrtFOtQtsVUA+z1EjEEhIN7Wd3L0XmwIrYRn6Bm9Rga6V3+07V3T+DD98H SgqYZOj1KcAQGv9WVU5cKmKPGf6QWUwbdGmP3bo74jf95O7RJYA9doWVmItfNMrzRKGJ 2oIcZ+XjnHAeNuX6VMjhQtY2iR6bYTcvpQHRaPBnGPb2jJmujAyvEf+7iqfDpMSsP1gv IkaWwqFAeO1DOPWawzsewcSMtgA9nKC8Bu7gV/6qrCw7Ha2a7iTU592zpPjqT7PozsBq dfBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=wwp8+Qu6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.50.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:50:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 11/22] target/arm: Implement LDG, STG, ST2G instructions Date: Fri, 11 Oct 2019 09:47:33 -0400 Message-Id: <20191011134744.2477-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c44 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- v2: Split out allocation_tag_mem. Handle atomicity of stores. v3: Add X[t] input to these insns; require pre-cleaned addresses. v5: Fix !32-byte aligned operation of st2g. --- target/arm/helper-a64.h | 5 ++ target/arm/mte_helper.c | 154 +++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 115 +++++++++++++++++++++++++++ 3 files changed, 274 insertions(+) -- 2.17.1 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 31f848ca03..88a0241915 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -110,3 +110,8 @@ DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_3(ldg, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(stg, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_3(st2g, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_3(stg_parallel, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 251dfff1e1..f1dd1cc0dd 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -25,8 +25,21 @@ #include "exec/helper-proto.h" +static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, + bool write, uintptr_t ra) +{ + /* Tag storage not implemented. */ + return NULL; +} + static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) { + uint8_t *mem = allocation_tag_mem(env, ptr, false, ra); + + if (mem) { + int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; + return extract32(atomic_read(mem), ofs, 4); + } /* Tag storage not implemented. */ return -1; } @@ -260,3 +273,144 @@ uint64_t HELPER(gmi)(uint64_t ptr, uint64_t mask) int tag = allocation_tag_from_addr(ptr); return mask | (1ULL << tag); } + +uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + int el; + uint64_t sctlr; + int rtag; + + /* Trap if accessing an invalid page. */ + rtag = get_allocation_tag(env, ptr, GETPC()); + + /* + * The tag is squashed to zero if the page does not support tags, + * or if the OS is denying access to the tags. + */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if (rtag < 0 || !allocation_tag_access_enabled(env, el, sctlr)) { + rtag = 0; + } + + return address_with_allocation_tag(xt, rtag); +} + +static void check_tag_aligned(CPUARMState *env, uint64_t ptr, uintptr_t ra) +{ + if (unlikely(!QEMU_IS_ALIGNED(ptr, TAG_GRANULE))) { + arm_cpu_do_unaligned_access(env_cpu(env), ptr, MMU_DATA_STORE, + cpu_mmu_index(env, false), ra); + g_assert_not_reached(); + } +} + +/* For use in a non-parallel context, store to the given nibble. */ +static void store_tag1(uint64_t ptr, uint8_t *mem, int tag) +{ + int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; + uint8_t old = atomic_read(mem); + uint8_t new = deposit32(old, ofs, 4, tag); + + atomic_set(mem, new); +} + +/* For use in a parallel context, atomically store to the given nibble. */ +static void store_tag1_parallel(uint64_t ptr, uint8_t *mem, int tag) +{ + int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4; + uint8_t old = atomic_read(mem); + + while (1) { + uint8_t new = deposit32(old, ofs, 4, tag); + uint8_t cmp = atomic_cmpxchg(mem, old, new); + if (likely(cmp == old)) { + return; + } + old = cmp; + } +} + +typedef void stg_store1(uint64_t, uint8_t *, int); + +static void do_stg(CPUARMState *env, uint64_t ptr, uint64_t xt, + uintptr_t ra, stg_store1 store1) +{ + int el; + uint64_t sctlr; + uint8_t *mem; + + check_tag_aligned(env, ptr, ra); + + /* Trap if accessing an invalid page. */ + mem = allocation_tag_mem(env, ptr, true, ra); + + /* Store if page supports tags and access is enabled. */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if (mem && allocation_tag_access_enabled(env, el, sctlr)) { + store1(ptr, mem, allocation_tag_from_addr(xt)); + } +} + +void HELPER(stg)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + do_stg(env, ptr, xt, GETPC(), store_tag1); +} + +void HELPER(stg_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + do_stg(env, ptr, xt, GETPC(), store_tag1_parallel); +} + +static void do_st2g(CPUARMState *env, uint64_t ptr1, uint64_t xt, + uintptr_t ra, stg_store1 store1) +{ + int el, tag; + uint64_t ptr2, sctlr; + uint8_t *mem1, *mem2; + + check_tag_aligned(env, ptr1, ra); + + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + tag = allocation_tag_from_addr(xt); + + /* + * Trap if accessing an invalid page(s). + * This takes priority over !allocation_tag_access_enabled. + */ + mem1 = allocation_tag_mem(env, ptr1, true, ra); + + if (ptr1 & TAG_GRANULE) { + /* The two stores are unaligned and modify two bytes. */ + ptr2 = ptr1 + TAG_GRANULE; + mem2 = allocation_tag_mem(env, ptr2, true, ra); + + /* Store if page supports tags and access is enabled. */ + if ((mem1 || mem2) && allocation_tag_access_enabled(env, el, sctlr)) { + if (mem1) { + store1(ptr1, mem1, tag); + } + if (mem2) { + store1(ptr2, mem2, tag); + } + } + } else { + /* The two stores are aligned 32, and modify one byte. */ + if (mem1 && allocation_tag_access_enabled(env, el, sctlr)) { + tag |= tag << 4; + atomic_set(mem1, tag); + } + } +} + +void HELPER(st2g)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + do_st2g(env, ptr, xt, GETPC(), store_tag1); +} + +void HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt) +{ + do_st2g(env, ptr, xt, GETPC(), store_tag1_parallel); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index cf341c98d3..c17b36ebb2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3559,6 +3559,118 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) } } +/* + * Load/Store memory tags + * + * 31 30 29 24 22 21 12 10 5 0 + * +-----+-------------+-----+---+------+-----+------+------+ + * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt | + * +-----+-------------+-----+---+------+-----+------+------+ + */ +static void disas_ldst_tag(DisasContext *s, uint32_t insn) +{ + int rt = extract32(insn, 0, 5); + int rn = extract32(insn, 5, 5); + uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; + int op2 = extract32(insn, 10, 3); + int op1 = extract32(insn, 22, 2); + bool is_load = false, is_pair = false, is_zero = false; + int index = 0; + TCGv_i64 dirty_addr, clean_addr, tcg_rt; + + if ((insn & 0xff200000) != 0xd9200000 + || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + + switch (op1) { + case 0: /* STG */ + if (op2 != 0) { + /* STG */ + index = op2 - 2; + break; + } + goto do_unallocated; + case 1: + if (op2 != 0) { + /* STZG */ + is_zero = true; + index = op2 - 2; + } else { + /* LDG */ + is_load = true; + } + break; + case 2: + if (op2 != 0) { + /* ST2G */ + is_pair = true; + index = op2 - 2; + break; + } + goto do_unallocated; + case 3: + if (op2 != 0) { + /* STZ2G */ + is_pair = is_zero = true; + index = op2 - 2; + break; + } + goto do_unallocated; + + default: + do_unallocated: + unallocated_encoding(s); + return; + } + + dirty_addr = read_cpu_reg_sp(s, rn, true); + if (index <= 0) { + /* pre-index or signed offset */ + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + } + + clean_addr = clean_data_tbi(s, dirty_addr, false); + tcg_rt = cpu_reg(s, rt); + + if (is_load) { + gen_helper_ldg(tcg_rt, cpu_env, clean_addr, tcg_rt); + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (is_pair) { + gen_helper_st2g_parallel(cpu_env, clean_addr, tcg_rt); + } else { + gen_helper_stg_parallel(cpu_env, clean_addr, tcg_rt); + } + } else { + if (is_pair) { + gen_helper_st2g(cpu_env, clean_addr, tcg_rt); + } else { + gen_helper_stg(cpu_env, clean_addr, tcg_rt); + } + } + + if (is_zero) { + TCGv_i64 tcg_zero = tcg_const_i64(0); + int mem_index = get_mem_index(s); + int i, n = (1 + is_pair) << LOG2_TAG_GRANULE; + + for (i = 0; i < n; i += 8) { + tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_Q); + tcg_gen_addi_i64(clean_addr, clean_addr, 8); + } + tcg_temp_free_i64(tcg_zero); + } + + if (index != 0) { + /* pre-index or post-index */ + if (index > 0) { + /* post-index */ + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + } + tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); + } +} + /* Loads and stores */ static void disas_ldst(DisasContext *s, uint32_t insn) { @@ -3583,6 +3695,9 @@ static void disas_ldst(DisasContext *s, uint32_t insn) case 0x0d: /* AdvSIMD load/store single structure */ disas_ldst_single_struct(s, insn); break; + case 0x19: /* Load/store tag */ + disas_ldst_tag(s, insn); + break; default: unallocated_encoding(s); break; From patchwork Fri Oct 11 13:47:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175956 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp965371ocf; Fri, 11 Oct 2019 06:55:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqzTgc4cYhwJnDuUkv/B7XjMZ8aq2bhl7NHBmq51QvXaPAjVbEdyzoIeG4in4Wgf0w8pXhOg X-Received: by 2002:ae9:ee06:: with SMTP id i6mr15189320qkg.362.1570802151667; Fri, 11 Oct 2019 06:55:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.50.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:50:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 12/22] target/arm: Implement the STGP instruction Date: Fri, 11 Oct 2019 09:47:34 -0400 Message-Id: <20191011134744.2477-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- v3: Handle atomicity, require pre-cleaned address. --- target/arm/translate-a64.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c17b36ebb2..4ecb0a2fb7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2657,7 +2657,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) * +-----+-------+---+---+-------+---+-------+-------+------+------+ * * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit - * LDPSW 01 + * LDPSW/STGP 01 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit * V: 0 -> GPR, 1 -> Vector * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, @@ -2682,6 +2682,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) bool is_signed = false; bool postindex = false; bool wback = false; + bool set_tag = false; TCGv_i64 clean_addr, dirty_addr; @@ -2694,6 +2695,14 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) if (is_vector) { size = 2 + opc; + } else if (opc == 1 && !is_load) { + /* STGP */ + if (!dc_isar_feature(aa64_mte_insn_reg, s) || index == 0) { + unallocated_encoding(s); + return; + } + size = 3; + set_tag = true; } else { size = 2 + extract32(opc, 1, 1); is_signed = extract32(opc, 0, 1); @@ -2746,6 +2755,15 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) } clean_addr = clean_data_tbi(s, dirty_addr, wback || rn != 31); + if (set_tag) { + TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); + if (tb_cflags(s->base.tb) & CF_PARALLEL) { + gen_helper_stg_parallel(cpu_env, clean_addr, tcg_rn); + } else { + gen_helper_stg(cpu_env, clean_addr, tcg_rn); + } + } + if (is_vector) { if (is_load) { do_fp_ld(s, rt, clean_addr, size); From patchwork Fri Oct 11 13:47:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175960 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp968878ocf; Fri, 11 Oct 2019 06:59:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqzCRAKwukXHlnqBhV2Mr7bgrguse99He2CgwqV2AP6FgTt4J5d0XszbahH9Hgw5uldsDQVL X-Received: by 2002:ac8:73cf:: with SMTP id v15mr16318053qtp.310.1570802360231; Fri, 11 Oct 2019 06:59:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570802360; cv=none; d=google.com; s=arc-20160816; b=UDd2Os+XUw9BsZqrUV6CjtHKpKe1rycSjGH/KYRpo7JjeG8cMoOpHnd/fkQV0P8IR/ ire3Y0zqrTHC+b3a4QL5+STibp3FcI+B/yeSM8XLXWmgr909FO3l5IhBMDQzSP9stE+v q9EqfWNb4y2B/F7oN43XxXJVNyyr8bS9U6M8UtoT/NmMr5/nuxzGcTyG7J729OjO6Q50 S+S/H6a3AM9tSo+Lg1Os5vxo5+CbbMBLubvpA5mpcRoZHjMzSYjgaw9jtaO51l9n67GS UnxKF+3ue7yxFSmxiiyWCPVemRRmdFfzyWL9YnaLXh4xThoooQ5vUuezpVvQCklLUY2Y Rsrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=FsDGTUNWhld8pKv/D95R5WX/niSk10RfgZKCNlYPPEU=; b=Kvx3Myg9CKQqHhqjlnvWeCYmRtGV2PKkQ7ihrCt3gQV4q2NLXoFlvpQFxVet/5MvYS mYqqmgOXfDwkhGDDTzzIz29JFbN1UfpPtojGoruRVKIBJsemEN+NdNLlppPtSev991Rc AmwgpVYjjIRXR+/sX+PVBQvOCUmmJD3a/WveODd6HfAgn9KhnpUg9r779Yk2x2ERqzu8 AJNyEFmMZePHqZu/vKC2Q1xTJ2353eMRehGLNVWD3+9hU+anO6v0m8I8KjfamVXY1hJD TZMo1tvvnA2gSCCYV12E3OcozSDB1oz6qQRdeEeNWRk+M8WBSS6HIcD3eHaILfm8UZ2i mf+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=uQe12jG1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.50.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:50:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 13/22] target/arm: Implement the LDGM and STGM instructions Date: Fri, 11 Oct 2019 09:47:35 -0400 Message-Id: <20191011134744.2477-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b41 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- v3: Require pre-cleaned addresses. --- target/arm/helper-a64.h | 3 ++ target/arm/mte_helper.c | 96 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 42 +++++++++++++---- 3 files changed, 132 insertions(+), 9 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 88a0241915..405aa60016 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -115,3 +115,6 @@ DEF_HELPER_FLAGS_3(stg, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(st2g, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(stg_parallel, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_2(ldgm, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_3(stgm, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_3(stzgm, TCG_CALL_NO_WG, void, env, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index f1dd1cc0dd..f1315bae37 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -414,3 +414,99 @@ void HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt) { do_st2g(env, ptr, xt, GETPC(), store_tag1_parallel); } + +uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) +{ + const int size = 4 << GMID_EL1_BS; + int el; + uint64_t sctlr; + void *mem; + + ptr = QEMU_ALIGN_DOWN(ptr, size); + + /* Trap if accessing an invalid page(s). */ + mem = allocation_tag_mem(env, ptr, false, GETPC()); + + /* + * The tag is squashed to zero if the page does not support tags, + * or if the OS is denying access to the tags. + */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if (!mem || !allocation_tag_access_enabled(env, el, sctlr)) { + return 0; + } + +#if GMID_EL1_BS != 6 +# error "Fill in the blanks for other sizes" +#endif + /* + * We are loading 64-bits worth of tags. The ordering of elements + * within the word corresponds to a 64-bit little-endian operation. + */ + return ldq_le_p(mem); +} + +static uint64_t do_stgm(CPUARMState *env, uint64_t ptr, + uint64_t val, uintptr_t ra) +{ + const int size = 4 << GMID_EL1_BS; + int el; + uint64_t sctlr; + void *mem; + + ptr = QEMU_ALIGN_DOWN(ptr, size); + + /* Trap if accessing an invalid page(s). */ + mem = allocation_tag_mem(env, ptr, true, ra); + + /* + * No action if the page does not support tags, + * or if the OS is denying access to the tags. + */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if (!mem || !allocation_tag_access_enabled(env, el, sctlr)) { + return ptr; + } + +#if GMID_EL1_BS != 6 +# error "Fill in the blanks for other sizes" +#endif + /* + * We are storing 64-bits worth of tags. The ordering of elements + * within the word corresponds to a 64-bit little-endian operation. + */ + stq_le_p(mem, val); + + return ptr; +} + +void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) +{ + do_stgm(env, ptr, val, GETPC()); +} + +void HELPER(stzgm)(CPUARMState *env, uint64_t ptr, uint64_t val) +{ + int i, mmu_idx, size = 4 << GMID_EL1_BS; + uintptr_t ra = GETPC(); + void *mem; + + ptr = do_stgm(env, ptr, val, ra); + + /* + * We will have just probed this virtual address in do_stgm. + * If the tlb_vaddr_to_host fails, then the memory is not ram, + * or is monitored in some other way. Fall back to stores. + */ + mmu_idx = cpu_mmu_index(env, false); + mem = tlb_vaddr_to_host(env, ptr, MMU_DATA_STORE, mmu_idx); + if (mem) { + memset(mem, 0, size); + } else { + for (i = 0; i < size; i += 8) { + cpu_stq_data_ra(env, ptr + i, 0, ra); + } + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4ecb0a2fb7..4e049bb4aa 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3592,7 +3592,7 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; int op2 = extract32(insn, 10, 3); int op1 = extract32(insn, 22, 2); - bool is_load = false, is_pair = false, is_zero = false; + bool is_load = false, is_pair = false, is_zero = false, is_mult = false; int index = 0; TCGv_i64 dirty_addr, clean_addr, tcg_rt; @@ -3602,13 +3602,18 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) } switch (op1) { - case 0: /* STG */ + case 0: if (op2 != 0) { /* STG */ index = op2 - 2; - break; + } else { + /* STZGM */ + if (s->current_el == 0 || offset != 0) { + goto do_unallocated; + } + is_mult = is_zero = true; } - goto do_unallocated; + break; case 1: if (op2 != 0) { /* STZG */ @@ -3624,17 +3629,27 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) /* ST2G */ is_pair = true; index = op2 - 2; - break; + } else { + /* STGM */ + if (s->current_el == 0 || offset != 0) { + goto do_unallocated; + } + is_mult = true; } - goto do_unallocated; + break; case 3: if (op2 != 0) { /* STZ2G */ is_pair = is_zero = true; index = op2 - 2; - break; + } else { + /* LDGM */ + if (s->current_el == 0 || offset != 0) { + goto do_unallocated; + } + is_mult = is_load = true; } - goto do_unallocated; + break; default: do_unallocated: @@ -3651,7 +3666,16 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) clean_addr = clean_data_tbi(s, dirty_addr, false); tcg_rt = cpu_reg(s, rt); - if (is_load) { + if (is_mult) { + if (is_load) { + gen_helper_ldgm(tcg_rt, cpu_env, clean_addr); + } else if (is_zero) { + gen_helper_stzgm(cpu_env, clean_addr, tcg_rt); + } else { + gen_helper_stgm(cpu_env, clean_addr, tcg_rt); + } + return; + } else if (is_load) { gen_helper_ldg(tcg_rt, cpu_env, clean_addr, tcg_rt); } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { if (is_pair) { From patchwork Fri Oct 11 13:47:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175964 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp798441ill; Fri, 11 Oct 2019 07:02:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqxA5pFuK9J+ReLIm/NJyWOGp1/NO8VKEtTmJ0LT9mBcVVHTq2IdmWZJQfqHH+6siEdGZigh X-Received: by 2002:ac8:4311:: with SMTP id z17mr15920632qtm.213.1570802555867; Fri, 11 Oct 2019 07:02:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570802555; cv=none; d=google.com; s=arc-20160816; b=Qgf187zwQ/7+EFn1dIcuO6JAWbU6l6r6SDkyN519UEtjcInMKJzYUQmgj+h0Ep20Py Jp5bAKH3CBH3DmRErpkILBC2csCdHj2yPxR/VBueE7tQnO9oCh2RnfGQYpS8wZACxXXb 0nDimqZc7Da4IDtj3RtZdlaL6Ni2zLHMKEUZFIKSwkzMdGCayvO/tnYLFJfUPtOroQTI tIdZCRUNNIxAiOsPTOMQvFvLCIgGmBjTBiAcVqF3qHZUWm52rxPMjzDr0RLeeFsSiVqb hmKaFxadFOd/W9v9cQx/WaO01KZYSG0k+HL7KuVjaCySxGIs7YoVxYH5kK/Qolw6B7jZ 8RgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=FHNQuXQMvSWOnALEsyFOBKvFsuWLGIwZ/NlmLTA2nkE=; b=Hp/IOzMn08WFRqJISD76I70ON7YeLu2N0F2PxKGoUE7KwmWC/YSo1BNFnTeXS5GYeQ nXT4mXKz+8m9s2f0p6Gezyy24VQmUSgQAxmIQQGdX5QNrXpLNavk+nYJKGvoF7i6LcBS zNkQvsTh23YKovfo4Dbmy5vqImi7/4falQrL4l84QYcuEvQccBSK09tOXCCikB2H8QLA Z6zCX3vOLeAjSJCXa2XIK9UGC7qVe7aJku2wFaZ8bofhTgNjQcwCHefAMzLyVraUGWO2 wMbaBvbacoxO48KCTIcPwFUxz+VMgSp+4LD9+mbVT0z1mJd8OXw2gPh7c66r7LyW1OkB bOAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=l3D16d5t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.50.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:50:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 14/22] target/arm: Implement the access tag cache flushes Date: Fri, 11 Oct 2019 09:47:36 -0400 Message-Id: <20191011134744.2477-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Like the regular data cache flushes, these are nops within qemu. Signed-off-by: Richard Henderson --- target/arm/helper.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index f435a8d8bd..33bc176e1c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5978,6 +5978,54 @@ static const ARMCPRegInfo mte_reginfo[] = { { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, + { .name = "IGVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "IGSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "IGDVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "IGDSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGDSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGVAP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDVAP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGVADP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CGDVADP", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3, + .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "CIGDVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL1_W }, REGINFO_SENTINEL }; From patchwork Fri Oct 11 13:47:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175962 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp970876ocf; Fri, 11 Oct 2019 07:00:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqzhq16ADYw2vOHqML5AMgey+dA/feEwBCxdEs+plNCBTPww/05Lnh5r5QaaqGjyZFXU4Ou3 X-Received: by 2002:a05:620a:20cc:: with SMTP id f12mr15243173qka.472.1570802457601; Fri, 11 Oct 2019 07:00:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570802457; cv=none; d=google.com; s=arc-20160816; b=eZYFQCJUZ7NQ9GJeSlBR3yhOXGvTtA026NYWxDmf7Zg8lgDPSF5Dt+5TzSfqhyOWy1 rK4aCbFy61tms7oHl3MosXvvFx6XHkM95Z91iRG69fMGzi0L5vS6md2RCjAygybdEP1Z DZjdW1aDsC4/1uCQz1lRn+Jqy3Kkhpz8yW1tN4alDNj70JOSTvibyc79Fp0UBXKE9tpX WmrjFfs/ijVRed498/+yrdviFOWGtNfo5ZiAFGfSnvn0K7K53rerZPmE6vBpH74eaQen rxuU8ga21CONkzDayBM2339h8kcj5Wpv0oGvT4ts0wHEbqbaMnOTCk5XzZHPw/D6rZrp uhdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=PbD/qSofe9qS2Crqciyp9o1Gyg/ozYNCw40WhU0Rn+Y=; b=wHLn8NDZDU6rgSu1cZslcJrh5GEhj0PWblaZCaqstD4rexYDuMpyx5M385zjHEwIE5 AVnxpWnatdjhljE9TcThgmCS4DcPYbEgL7XzVTWwteN5sWnS307cOUuYVZQPCL2MLRAh AF2VavuK3Bkw3DLAGNRGFetp9HAGWxSqslhWYt/wm376KyIoLt10Th46uipyYbMvVy5c WnaEUlQ9Zmb3j1lYu5jiKT5GNKSc3i6VALjXxuZPANelji7kwl3WdRvSHmy/1Ns1m+GW 2OqwTHm5iO8KkDZihv7RiccHa1z9KZV/5rPfcjvasFQp/O4lmS4jSaoNzLol01zavyFU Ygyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fXc73B8+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.50.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:50:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 15/22] target/arm: Clean address for DC ZVA Date: Fri, 11 Oct 2019 09:47:37 -0400 Message-Id: <20191011134744.2477-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This data access was forgotten in the previous patch. Fixes: 3a471103ac1823ba Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4e049bb4aa..49817b96ae 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1766,7 +1766,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, return; case ARM_CP_DC_ZVA: /* Writes clear the aligned block of memory which rt points into. */ - tcg_rt = cpu_reg(s, rt); + tcg_rt = clean_data_tbi(s, cpu_reg(s, rt), false); gen_helper_dc_zva(cpu_env, tcg_rt); return; default: From patchwork Fri Oct 11 13:47:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175968 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp800939ill; Fri, 11 Oct 2019 07:04:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqyqQHjY0xNneFTQUCEDwvTRSj5iNQAcxcpg5kJRTkyoNdXuLBSGefq4O2+poxlCNAiLNLL9 X-Received: by 2002:ae9:f204:: with SMTP id m4mr13167290qkg.300.1570802659198; Fri, 11 Oct 2019 07:04:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570802659; cv=none; d=google.com; s=arc-20160816; b=dwPwweMxbxPF5szn1g8T0Vw7QsaKi9S2R2kNN9FIhCQq2f0KwaW0Zbe9VFKrXonD31 0FPn+eczxnu9O4wY79t++D5dzvTWGBv8FKASu4HVmxh4yLh7l8AB++yI4dpnuh76tPS1 DTVXudoR2bUSRNFX0GfHIE+VIkUY2vmYT5iV8BpOS+9npYk3YXYrN9IpalzrBUz/4Rvj pcQGJrrTWM/J5mAfJ2WrVDsmKOWd6mK+Z8252fQs7S43LVsLUAOgpaRXegPoWPoORy2J a8YMCSmNqdnkk9eaq7TAWD/G7lwLDg8R51UdrpDK32ZOdXEL4gBZGY59zUOsM3ppMwiO u1Vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=wjJWQXa8PHF/9CUSCdjQIeze++rnO7qWx/Jq9my6hS8=; b=Dxbg18qp0GEsixpkr6O7K4/qboPf2eh9XKaJ3RoKAteD6RaVFesfjRXVOdVD0U5298 +sp3uKUohreTmUJn7/Zqr9T6rHqr6KyVCyZkZzuVLH1kPTpNWHwRFSrkBvGLzlgQRsUH 2o+BhHMJYiiTlXGt1T1euKOfsCtXXZjPBmZ8SN8TVBZRhjskFcqdODyORlsQahDs+7qC qZwwIj5m76G09mTF/T613frCuOjNS56iuRS6z+7yGoxNZWZqpDi/w2OFRQi4uBq6cATK K7SpeRZGhDtZkZqhBGODSg4rw5xC43gfL+BSZwZU2jkKkvsGG+alnreAMDSf6cF7lVNP cE1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KqewMvke; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i18si8750952qvg.159.2019.10.11.07.04.19 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 Oct 2019 07:04:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KqewMvke; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50880 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIvWj-000685-Vz for patch@linaro.org; Fri, 11 Oct 2019 10:04:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39256) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIvJK-00061q-47 for qemu-devel@nongnu.org; Fri, 11 Oct 2019 09:50:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iIvJI-000477-PU for qemu-devel@nongnu.org; Fri, 11 Oct 2019 09:50:25 -0400 Received: from mail-yw1-xc32.google.com ([2607:f8b0:4864:20::c32]:34918) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iIvJI-00046V-LT for qemu-devel@nongnu.org; Fri, 11 Oct 2019 09:50:24 -0400 Received: by mail-yw1-xc32.google.com with SMTP id r134so3502750ywg.2 for ; Fri, 11 Oct 2019 06:50:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wjJWQXa8PHF/9CUSCdjQIeze++rnO7qWx/Jq9my6hS8=; b=KqewMvkeTcgDKXIXvRKl8YQq3gdtG8d0vAfGj0x5/UCx30nwHJ7a8c9CMILG9GPtbH aF/XP2UBATG0EuHzkyJn1FiqDEgA5LwxWJW7AvQl2gsX/pEEqFZuW4wAXCUP2O0SDB2X 7W+sBhV4p9RHOsnoVmrRToj2UGru0jMI+9avcjCtkAjEirHlBtw6w1FamIV8I5B6Dm7S IzD8xsnjf9+x8F90I54Sr+9dXeauhaNyZgZgTIAVyHRhooYTGZt+25SLSWM4LppAGcaT ARHZUN+uk7Sy7txxtBpA+ORgW+kHOOF6+If6djnph4TycA/Gmg6q4LVGwTZu7InVj6fu cMeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wjJWQXa8PHF/9CUSCdjQIeze++rnO7qWx/Jq9my6hS8=; b=j2z92qTVWentyNgborlUFZxtOYtblhmvppUCBNqwP7Kza5kCOA2YUAPNOHqBkTBaS9 DEvzKgM9xnzhZuID7q417x2qwWunWE71wwyp4mo13OLsnsTl0ECf3R+6qkUk3s5uo6sM iyUckPby9I4+N8fcvv9tHzY9hG8stPvxh0xWKMi7d9UcGPBTMUBuLeH1NBCKqUTHvLLq Q/71R9aYhEe7wnTSLj9hYvRQCSa9xyX9hv1Ajqk/QwrM1HBSWBf2zaUcnagybDiYHFtd BO6swNb7dKnDGwDVHB+l5cAR4Mtyu5sy7uP1wQDu15klD1Qi6xQc68WtxBgdDHEe8lb3 Z3gg== X-Gm-Message-State: APjAAAWQTVRj9VQlx5XpZhe+Sk1brJxtEynTdH7u+9jBo1JNsV/ZZgf0 1bmVBgrAMvZ4lW0It5p+Yy1F4cg8afc= X-Received: by 2002:a0d:c945:: with SMTP id l66mr2377982ywd.286.1570801823649; Fri, 11 Oct 2019 06:50:23 -0700 (PDT) Received: from cloudburst.gateway.pace.com (67.216.151.25.pool.hargray.net. [67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.50.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:50:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 16/22] target/arm: Implement data cache set allocation tags Date: Fri, 11 Oct 2019 09:47:38 -0400 Message-Id: <20191011134744.2477-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is DC GVA and DC GZVA. Signed-off-by: Richard Henderson --- v2: Use allocation_tag_mem + memset. v3: Require pre-cleaned addresses. --- target/arm/cpu.h | 4 +++- target/arm/helper-a64.h | 1 + target/arm/helper.c | 16 ++++++++++++++++ target/arm/mte_helper.c | 28 ++++++++++++++++++++++++++++ target/arm/translate-a64.c | 9 +++++++++ 5 files changed, 57 insertions(+), 1 deletion(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d99bb5e956..93a362708b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2233,7 +2233,9 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) -#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA +#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) +#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) +#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 #define ARM_CP_NO_GDB 0x4000 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 405aa60016..c82605b51e 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -118,3 +118,4 @@ DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_2(ldgm, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(stgm, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(stzgm, TCG_CALL_NO_WG, void, env, i64, i64) +DEF_HELPER_FLAGS_2(dc_gva, TCG_CALL_NO_RWG, void, env, i64) diff --git a/target/arm/helper.c b/target/arm/helper.c index 33bc176e1c..eec9064d88 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6026,6 +6026,22 @@ static const ARMCPRegInfo mte_reginfo[] = { { .name = "CIGDVAC", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, .type = ARM_CP_NOP, .access = PL1_W }, + { .name = "GVA", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3, + .access = PL0_W, .type = ARM_CP_DC_GVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode */ + .accessfn = aa64_zva_access, +#endif + }, + { .name = "GZVA", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4, + .access = PL0_W, .type = ARM_CP_DC_GZVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode */ + .accessfn = aa64_zva_access, +#endif + }, REGINFO_SENTINEL }; diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index f1315bae37..e8d8a6bedb 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -510,3 +510,31 @@ void HELPER(stzgm)(CPUARMState *env, uint64_t ptr, uint64_t val) } } } + +void HELPER(dc_gva)(CPUARMState *env, uint64_t ptr) +{ + ARMCPU *cpu = env_archcpu(env); + size_t blocklen = 4 << cpu->dcz_blocksize; + int el; + uint64_t sctlr; + uint8_t *mem; + int rtag; + + ptr = QEMU_ALIGN_DOWN(ptr, blocklen); + + /* Trap if accessing an invalid page. */ + mem = allocation_tag_mem(env, ptr, true, GETPC()); + + /* No action if page does not support tags, or if access is disabled. */ + el = arm_current_el(env); + sctlr = arm_sctlr(env, el); + if (!mem || !allocation_tag_access_enabled(env, el, sctlr)) { + return; + } + + rtag = allocation_tag_from_addr(ptr); + rtag |= rtag << 4; + + assert(QEMU_IS_ALIGNED(blocklen, 2 * TAG_GRANULE)); + memset(mem, rtag, blocklen / (2 * TAG_GRANULE)); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 49817b96ae..31260f97f9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1769,6 +1769,15 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, tcg_rt = clean_data_tbi(s, cpu_reg(s, rt), false); gen_helper_dc_zva(cpu_env, tcg_rt); return; + case ARM_CP_DC_GVA: + tcg_rt = clean_data_tbi(s, cpu_reg(s, rt), false); + gen_helper_dc_gva(cpu_env, tcg_rt); + return; + case ARM_CP_DC_GZVA: + tcg_rt = clean_data_tbi(s, cpu_reg(s, rt), false); + gen_helper_dc_zva(cpu_env, tcg_rt); + gen_helper_dc_gva(cpu_env, tcg_rt); + return; default: break; } From patchwork Fri Oct 11 13:47:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175963 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp797410ill; Fri, 11 Oct 2019 07:01:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqy3aN+tnv0QNJ9g601UGV8zBE4ssdZAyL4GviTmh+KhjpAn53wRa56r7BlyVEkCCa9o78bY X-Received: by 2002:ac8:2a83:: with SMTP id b3mr17109047qta.244.1570802516014; Fri, 11 Oct 2019 07:01:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570802516; cv=none; d=google.com; s=arc-20160816; b=Ev2oMHQTocak50ZQzSoe3xwQyEPIFLN3yXaTp1CTFMwWq+/JQ1kfPIvjfJXngA/XpD ddYR8x4lNyxe+Q4Yad0PQjp2XYDNMLs2mQTiNbEUgHlsKhh61uBOTLS1gaYvI/pPxSxF k6NcNv3Hi+DuLAkgnWUaUP7vMDNwxBc8oenOzj02lukyQC02oLK5DLH5wYgfqjGDuuKt g3vVq0pEn9TBg2fflKBTJYY+QUu8K3ckHyI9Ep4jzHhotpayg4wtx3f/zBWXYq1TZQqa ooa9kdeuaC5QooJnnE92H31dcd7Scwlb18Z5IEfsfvMiOZSjVbjA0LQjTnOZAwiqOwfJ S2VA== ARC-Message-Signature: i=1; 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.50.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:50:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 17/22] target/arm: Set PSTATE.TCO on exception entry Date: Fri, 11 Oct 2019 09:47:39 -0400 Message-Id: <20191011134744.2477-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c44 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" D1.10 specifies that exception handlers begin with tag checks overridden. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Only set if MTE feature present. --- target/arm/helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index eec9064d88..e988398fce 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8401,6 +8401,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) target_ulong addr = env->cp15.vbar_el[new_el]; unsigned int new_mode = aarch64_pstate_mode(new_el, true); unsigned int cur_el = arm_current_el(env); + unsigned int new_pstate; /* * Note that new_el can never be 0. If cur_el is 0, then @@ -8494,7 +8495,11 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", env->elr_el[new_el]); - pstate_write(env, PSTATE_DAIF | new_mode); + new_pstate = new_mode | PSTATE_DAIF; + if (cpu_isar_feature(aa64_mte, cpu)) { + new_pstate |= PSTATE_TCO; + } + pstate_write(env, new_pstate); env->aarch64 = 1; aarch64_restore_sp(env, new_el); From patchwork Fri Oct 11 13:47:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175967 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp800268ill; Fri, 11 Oct 2019 07:03:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqyFv8pbN/TB7JF7keMGK2ns5YhcoktVgyyrvRJREpLkreb3pumPxghfpCeqg97bkXWclhsA X-Received: by 2002:ad4:4503:: with SMTP id k3mr15359139qvu.155.1570802630412; Fri, 11 Oct 2019 07:03:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570802630; cv=none; d=google.com; s=arc-20160816; b=jBR+/+fJ3VSzOpANamcL9/EC7JwKCGBLDuv6VVWuYfess5xvGZ2yyOMzF4tcuglqAY /MZy6E5lRrOGmTDmXEu8Bee74if+koqdRTh6V99rHq0qiB52fBecznPoxSIHfq7uDlNk IwPFiWRdCnlxoti2oVAp8i/0MhkV/jylUaFy3Y5ctXzkt4t53RygPwaGkztJBeDT16xy X5LVxEmwAs+wAlLVxV57+oIAUDwJ60UMt9TLilqLnwl+Wd2V3UL4cdgTBF1VydzWRclQ 83cAiOzew/dWNy1XCc9tSyNzd8xsfZ/JApz6W8GlJS3yO7gwX4U6Xfg6x+CPeovabyq/ CX7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=XGJIZDe8e48mjnd3S1UnH/xuMhjquSRYJ/YgYFRxSl4=; b=y05fjx9ZDuBwHI4dOEvxrcLbKuiPCIzRE6NVec7mVr3VS3ZaMdTMG3/UwIK2Mq4qNb Kos86LyrPV04EYnLJIHyku1SDQgBhriTH2cvvNQwDYz8F1FxjRGpWJr2w0M69NHL5df1 Ub70ro7WowIOQrcOu9lD+0CjC1VqyxsmVK2HzYZu70RsankO9GhHVSlADQckFMbHEcfx C87fTF9DszTw/SaxAFzqlWFMOx2W1dyBR5vzHNGf2LGSkZVBRY1+WRNfGSHUuO77GS3q vJZqS74Kz2Xv11zZ3+oeWlhcfy5k0Ee0yuWKPyuBB00YXZlAogHlVaxNc/Bx2EUOKQx8 u5Gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=W6SHTLM1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.50.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:50:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 18/22] target/arm: Enable MTE Date: Fri, 11 Oct 2019 09:47:40 -0400 Message-Id: <20191011134744.2477-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We now implement all of the components of MTE, without actually supporting any tagged memory. All MTE instructions will work, trivially, so we can enable support. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 10 ++++++++++ target/arm/cpu64.c | 1 + 2 files changed, 11 insertions(+) -- 2.17.1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2399c14471..12fffa3ee4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -209,6 +209,16 @@ static void arm_cpu_reset(CPUState *s) * make no difference to the user-level emulation. */ env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); + /* Enable MTE allocation tags. */ + env->cp15.hcr_el2 |= HCR_ATA; + env->cp15.scr_el3 |= SCR_ATA; + env->cp15.sctlr_el[1] |= SCTLR_ATA0; + /* Enable synchronous tag check failures. */ + env->cp15.sctlr_el[1] |= 1ull << 38; +#ifdef TARGET_AARCH64 + /* Set MTE seed to non-zero value, otherwise RandomTag fails. */ + env->cp15.rgsr_el1 = 0x123400; +#endif #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d7f5bf610a..ac1e2dc2c4 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -350,6 +350,7 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64pfr1; t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); cpu->isar.id_aa64pfr1 = t; t = cpu->isar.id_aa64mmfr1; From patchwork Fri Oct 11 13:47:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175970 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp805352ill; Fri, 11 Oct 2019 07:07:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqwUEfhcOSboMNY8Pb9mk02aeVCotTqFDBCl9xWDOfJk/wsSDzOAZ03SpsDE7YwXBtnEojoJ X-Received: by 2002:ae9:f204:: with SMTP id m4mr13185154qkg.300.1570802839405; Fri, 11 Oct 2019 07:07:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570802839; cv=none; d=google.com; s=arc-20160816; b=sTNUvZLkL7ia1h5V8cyd1Uk//xjzln++rWZuT1NO5STQKBg+vzPCCz+sphbKCLQNxh Mc2Wu9cqaae9yvdkc/cm86z9Im1CzLblrrm5scFZE4GVkOnpnsPRV91tsB5287BypeTp 2US1vb+OXdhOWBKpLnBOUrY0OlJ+kXqyOxvIPHYV4cv+bkCL3QEI2Vh+BP4TJLh1JfUy /+AatEnPaRaycGYFHhUNUzyD9a4RMvJAQm8i5i0R6N4sDVnoMSf1+lmfS9aS6JCTz1f2 tNX8YJIFrnJpb1btz3Ay7sNlRhpRRg/elP5KmngII86XukT17LJ7njKqHv95UOMsUZJp Pv1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=fmdmkU2Zh+ktxeMt/gay8d04S3LmhLt8jnMCWxeDlf4=; b=xKUXZISwPa6e+I2BEhH7GXFOI+zy2w5+8ERBLwaUKqMentuwecC96Jd/eYhW5sdbB9 UzCHqzaHKZ+9KKVQDRwkyU/4x5Qb0xY/Bj2MZ6JCgPMuxtV+kqKRgw97IdYQyDs8vjd+ 19FnQ1VIFUbFpragW6pt3qPbIo643qqMQa5SajrCm+3O67QwohRlTo005fKSLc5z+a5P kZV2OIB7s5CaGdqnnKsqXYs65NAUkU2diPj9tLgBhoGf7V8s2UPHhpmUV5TZAIrUDclY GPva0rS+xvO4ZE7VUG1nJMRcjsj6mZi7DHMphlpnB31cHBdtv6ZZeIh1uqYdd1qaNScu eJrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JpUbxzlV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.50.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:50:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 19/22] target/arm: Cache the Tagged bit for a page in MemTxAttrs Date: Fri, 11 Oct 2019 09:47:41 -0400 Message-Id: <20191011134744.2477-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This "bit" is a particular value of the page's MemAttr. Signed-off-by: Richard Henderson --- target/arm/helper.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index e988398fce..17981d7c48 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9609,6 +9609,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); bool guarded = false; + uint8_t memattr; /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -9836,17 +9837,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, txattrs->target_tlb_bit0 = true; } + if (mmu_idx == ARMMMUIdx_S2NS) { + memattr = convert_stage2_attrs(env, extract32(attrs, 0, 4)); + } else { + /* Index into MAIR registers for cache attributes */ + uint64_t mair = env->cp15.mair_el[el]; + memattr = extract64(mair, extract32(attrs, 0, 3) * 8, 8); + } + + /* When in aarch64 mode, and MTE is enabled, remember Tagged in IOTLB. */ + if (aarch64 && memattr == 0xf0 && cpu_isar_feature(aa64_mte, cpu)) { + txattrs->target_tlb_bit1 = true; + } + if (cacheattrs != NULL) { - if (mmu_idx == ARMMMUIdx_S2NS) { - cacheattrs->attrs = convert_stage2_attrs(env, - extract32(attrs, 0, 4)); - } else { - /* Index into MAIR registers for cache attributes */ - uint8_t attrindx = extract32(attrs, 0, 3); - uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; - assert(attrindx <= 7); - cacheattrs->attrs = extract64(mair, attrindx * 8, 8); - } + cacheattrs->attrs = memattr; cacheattrs->shareability = extract32(attrs, 6, 2); } From patchwork Fri Oct 11 13:47:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175969 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp801487ill; Fri, 11 Oct 2019 07:04:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqyjp63MBo4eP79KoJiMI4WR1vaGHhyDKOCsNvx5Ob+ji6CfFx/tqFDKw3u11evNyjh3gt8Q X-Received: by 2002:a50:fa94:: with SMTP id w20mr13971350edr.47.1570802682653; Fri, 11 Oct 2019 07:04:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570802682; cv=none; d=google.com; s=arc-20160816; b=YNDSf6rR/57AHFgp2Kd7mh/3HSXIVor7pBC+lgVgOPw82pgkDRrIYkHdDhxqpPXdeK UUlcIoDPPpUDaUKr6pUvA28bLGs+nubawgQkkyrXK2QvZ8+tp5NomBbB61DOffU89fTV cr3aKMbhCfJI2t/8vbjCA2VDvcCpPOHMyHXlO/7DZ5nQVAx3JxfroLo3C9ws50hO9oJR OgGCoGbvp1iYavJsKPel87iFtGLZnw3gg1/OJj5Y4SrxVaNWYfMwU6lkN1u6D50PfJmC IElTBTl9g44H8EUh+sPBUVpe4tD91gVbxpAUrChm5ZfmMg3qgp1f5+8awmSaUPPiDqWa Xfqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=sQCxz2oMYepQwc17fX+5BMmc0MrbQQ1A+BstlG5vP/M=; b=Lk+8toPuPNxOjiKgT6QJXsvmDKGkIJsD5oBSnRKOxuECZ/dJVEYe9AT0xPMDBeIsSG dsomvU+0lT2IMtCR3M5oMRm1nyVnVOy1YWECXyYbNljR/R96NdtQBzGz4GZPCuimWRF7 CIh41r2RgftXjuRU5pa+SmFg8E46leqYe+NN878vumYKXZ2H+PZcgVneXGHfvqP+SLs2 6nBRu3n4JCaMnzduenW9UDLsYnhFah6XGFARAr/CeEx0Gs+249OPG+O0Qwr8hpo4Y2LP f+HhEQP/cprYCrf/uz6oU6AAprnV38VELko28dIdG79rl1xtR2R7Uw85za8p187u5+IZ k6Zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UBCRIpGv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k32si5763632ede.244.2019.10.11.07.04.42 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 Oct 2019 07:04:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UBCRIpGv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50890 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIvX6-0006V8-OE for patch@linaro.org; Fri, 11 Oct 2019 10:04:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39356) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIvJO-0006AE-TR for qemu-devel@nongnu.org; Fri, 11 Oct 2019 09:50:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iIvJN-0004Cp-DD for qemu-devel@nongnu.org; Fri, 11 Oct 2019 09:50:30 -0400 Received: from mail-yb1-xb43.google.com ([2607:f8b0:4864:20::b43]:33118) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iIvJN-0004CM-9T for qemu-devel@nongnu.org; Fri, 11 Oct 2019 09:50:29 -0400 Received: by mail-yb1-xb43.google.com with SMTP id h7so1025165ybp.0 for ; Fri, 11 Oct 2019 06:50:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sQCxz2oMYepQwc17fX+5BMmc0MrbQQ1A+BstlG5vP/M=; b=UBCRIpGv826pFo7+smVnIhRkHKPbU6YQUY9q02165kRzu21ZvBwJaqgccZJzMNr10H dMK1bWWuajt8miGs07UjI9S/IPdANX+UV2s6y0T/k7mr9aBRArMThHlmHL3MRzYsO8yB 1ZwqqyXp5gc8jxjg33dLjR8ouq+r/9aWbhgVKSeqfmDRwI3Mms3or81+8tBR51U8jekL NbC39GCyBvTWig1zgGfxf9QqrT4gIIktsLLsCdSpdiY7puPYyvPFQxJp4v9GvEeZ9ngq ycQ50MDoBYy43K4rxf3EKRLN6ZQNdTxJWqkzOfLr7+/ik8kIE+GFbpqPPknYlz4GP4vZ OizQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sQCxz2oMYepQwc17fX+5BMmc0MrbQQ1A+BstlG5vP/M=; b=VLGTBct04G3DZmepPFVBwNo01oJ4bQM8KqI3WCEFh6gf1WujyW3T8zIOJRRn7E4m+A 12yMf+3NU2xZv4W54gYcdlEPHn4a68UzX76yHNTOb7ez3T2ymMrJknZxO04SGgihd2Ql FFTPrujy0zRSQ7DaaMJdpYRTUnzLzYODQ6zZCUs30kZ18+Ev2KkmllNBTnWJl3p7d2Ro +mZFBQXX8AcGS/XVPRR/vXPX7SozVG8ckOd6C5F4ctFK6Lk5ym4pmdASjp0boo/3Pbix q1/fsgUszjv6ESQEIQkcnvmhAMqZ0Olwt5iIoeqDcJhRRTPKrDXUwcq+PXo8sGFTC57Q 9o6A== X-Gm-Message-State: APjAAAXeUmQXWDL0sRnPkpF/4n1XW2NtGsKkvpXclLwfLfeVvcC9434Q 44yupN/FV+ABQdHvx1SBewcUh+lMEPE= X-Received: by 2002:a25:5:: with SMTP id 5mr5481277yba.310.1570801828237; Fri, 11 Oct 2019 06:50:28 -0700 (PDT) Received: from cloudburst.gateway.pace.com (67.216.151.25.pool.hargray.net. [67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.50.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:50:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 20/22] target/arm: Create tagged ram when MTE is enabled Date: Fri, 11 Oct 2019 09:47:42 -0400 Message-Id: <20191011134744.2477-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- v5: Assign cs->num_ases to the final value first. Downgrade to ID_AA64PFR1.MTE=1 if tag memory is not available. v6: Add secure tag memory for EL3. --- target/arm/cpu.h | 6 ++++++ hw/arm/virt.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++ target/arm/cpu.c | 53 ++++++++++++++++++++++++++++++++++++++++++++--- 3 files changed, 110 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 93a362708b..faca43ea78 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -765,6 +765,10 @@ struct ARMCPU { /* MemoryRegion to use for secure physical accesses */ MemoryRegion *secure_memory; + /* MemoryRegion to use for allocation tag accesses */ + MemoryRegion *tag_memory; + MemoryRegion *secure_tag_memory; + /* For v8M, pointer to the IDAU interface provided by board/SoC */ Object *idau; @@ -2956,6 +2960,8 @@ int cpu_mmu_index(CPUARMState *env, bool ifetch); typedef enum ARMASIdx { ARMASIdx_NS = 0, ARMASIdx_S = 1, + ARMASIdx_TagNS = 2, + ARMASIdx_TagS = 3, } ARMASIdx; /* Return the Exception Level targeted by debug exceptions. */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d74538b021..573988ba4d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1330,6 +1330,18 @@ static void create_secure_ram(VirtMachineState *vms, g_free(nodename); } +static void create_tag_ram(MemoryRegion *tag_sysmem, + hwaddr base, hwaddr size, + const char *name) +{ + MemoryRegion *tagram = g_new(MemoryRegion, 1); + + memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); + memory_region_add_subregion(tag_sysmem, base / 32, tagram); + + /* ??? Do we really need an fdt entry, or is MemTag enabled sufficient. */ +} + static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) { const VirtMachineState *board = container_of(binfo, VirtMachineState, @@ -1485,6 +1497,8 @@ static void machvirt_init(MachineState *machine) qemu_irq pic[NUM_IRQS]; MemoryRegion *sysmem = get_system_memory(); MemoryRegion *secure_sysmem = NULL; + MemoryRegion *tag_sysmem = NULL; + MemoryRegion *secure_tag_sysmem = NULL; int n, virt_max_cpus; MemoryRegion *ram = g_new(MemoryRegion, 1); bool firmware_loaded; @@ -1652,6 +1666,35 @@ static void machvirt_init(MachineState *machine) "secure-memory", &error_abort); } + /* + * The cpu adds the property iff MemTag is supported. + * If it is, we must allocate the ram to back that up. + */ + if (object_property_find(cpuobj, "tag-memory", NULL)) { + if (!tag_sysmem) { + tag_sysmem = g_new(MemoryRegion, 1); + memory_region_init(tag_sysmem, OBJECT(machine), + "tag-memory", UINT64_MAX / 32); + + if (vms->secure) { + secure_tag_sysmem = g_new(MemoryRegion, 1); + memory_region_init(secure_tag_sysmem, OBJECT(machine), + "secure-tag-memory", UINT64_MAX / 32); + + /* As with ram, secure-tag takes precedence over tag. */ + memory_region_add_subregion_overlap(secure_tag_sysmem, 0, + tag_sysmem, -1); + } + } + + object_property_set_link(cpuobj, OBJECT(tag_sysmem), + "tag-memory", &error_abort); + if (vms->secure) { + object_property_set_link(cpuobj, OBJECT(secure_tag_sysmem), + "secure-tag-memory", &error_abort); + } + } + object_property_set_bool(cpuobj, true, "realized", &error_fatal); object_unref(cpuobj); } @@ -1695,6 +1738,17 @@ static void machvirt_init(MachineState *machine) create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); } + if (tag_sysmem) { + create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, + machine->ram_size, "mach-virt.tag"); + if (vms->secure) { + create_tag_ram(secure_tag_sysmem, + vms->memmap[VIRT_SECURE_MEM].base, + vms->memmap[VIRT_SECURE_MEM].size, + "mach-virt.secure-tag"); + } + } + vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64); create_rtc(vms, pic); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 12fffa3ee4..a3a49cd5bf 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1182,6 +1182,27 @@ void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, &error_abort); + +#ifndef CONFIG_USER_ONLY + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && + cpu_isar_feature(aa64_mte, cpu)) { + object_property_add_link(obj, "tag-memory", + TYPE_MEMORY_REGION, + (Object **)&cpu->tag_memory, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG, + &error_abort); + + if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { + object_property_add_link(obj, "secure-tag-memory", + TYPE_MEMORY_REGION, + (Object **)&cpu->secure_tag_memory, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG, + &error_abort); + } + } +#endif } static void arm_cpu_finalizefn(Object *obj) @@ -1632,17 +1653,43 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) MachineState *ms = MACHINE(qdev_get_machine()); unsigned int smp_cpus = ms->smp.cpus; - if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { + /* + * We must set cs->num_ases to the final value before + * the first call to cpu_address_space_init. + */ + if (cpu->tag_memory != NULL) { + cs->num_ases = 4; + } else if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { cs->num_ases = 2; + } else { + cs->num_ases = 1; + } + if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { if (!cpu->secure_memory) { cpu->secure_memory = cs->memory; } cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", cpu->secure_memory); - } else { - cs->num_ases = 1; } + + if (cpu->tag_memory != NULL) { + cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", + cpu->tag_memory); + if (cpu->has_el3) { + cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", + cpu->secure_tag_memory); + } + } else if (cpu_isar_feature(aa64_mte, cpu)) { + /* + * Since there is no tag memory, we can't meaningfully support MTE + * to its fullest. To avoid problems later, when we would come to + * use the tag memory, downgrade support to insns only. + */ + cpu->isar.id_aa64pfr1 = + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); + } + cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); /* No core_count specified, default to smp_cpus. */ From patchwork Fri Oct 11 13:47:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175971 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp808787ill; Fri, 11 Oct 2019 07:09:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqy+q35sQFghsLHUcBkrpVKYH5ma4kp6WlAREimbxjwEYIc9zEGlZF1h7/o8mtWUZUgSigjO X-Received: by 2002:a05:6402:514:: with SMTP id m20mr14006966edv.187.1570802986378; Fri, 11 Oct 2019 07:09:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570802986; cv=none; d=google.com; s=arc-20160816; b=xSdVP235J5O2PA6TJ2LGQIVEUzHeIeW+XOt3Bvgzqd3tNLKG7ung3vduWzaKkc9+qr Nq/x5PekiUu0l6Irshd2OZKYgYWjSyKXHypAKuQ0y/hPneR9FasDsl8uv2VzPfuhtcy/ pLbuVGZAFISqXNzCS5Pff0LBwvYLBlyj9PCfQ/6hUKu6sEYoz0ASdTaJdqOF6ow9PXwA Iv+C6mWIOPQixFcoCUHNTmYgDTrHsJ8ZbE22ipV0UfLO1O1wxzxXt1fmTv/4qx3ANm04 Iw8POVcpGy99nkGYOMIRW1VRQugPwPl1jPnWKiisHrwTN1ksD6OVDAdADHxh71M+atHv k0sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=gTZdg6dNMnBI75tFG4b9WmQnPaXz16dMYJhebtyMXpQ=; b=k+13vbfra0l91ClJLZIDWFsblcEXE7OohB5J8ZbFLEVXVOFaEXsOkUwV5RUyle4i/i wyDjXGw9GH+VWDM17YOTS+yvaGDCMZcNVtX2t5Unk7EQrDM6Ff2uuDhRZmBc22Nz7t9N kTVONXKF3B3xSeozS/fJAzZoMtcEUWONArknhDTjbyAPPks83DIK9oeKiwNtZ3EYskOq pB+6EvEmitQ8l8YWKb6sWSlV79FaYOj2uys3fOpnhy9ox3IXG/qYH/0BFsTfJSg9DKui UgKcGRgC49NOBHRxPOsJ8O5WUGBNZuWnk9QWY4okP6NYxwG5J/zhaAQiiBDvXYIVEubz CtqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=wBIDAX+a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.50.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:50:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 21/22] target/arm: Add mmu indexes for tag memory Date: Fri, 11 Oct 2019 09:47:43 -0400 Message-Id: <20191011134744.2477-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b44 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The process by which one goes from an address space plus physical address to a host pointer is complex. It is easiest to reuse the mechanism already present within cputlb, and letting that cache the results. Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 12 +++++++++--- target/arm/internals.h | 2 ++ target/arm/helper.c | 25 +++++++++++++++++++++++-- 4 files changed, 35 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 6e6948e960..18ac562346 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -29,6 +29,6 @@ # define TARGET_PAGE_BITS_MIN 10 #endif -#define NB_MMU_MODES 8 +#define NB_MMU_MODES 9 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index faca43ea78..c3609ef9d5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2854,8 +2854,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, #define ARM_MMU_IDX_M_NEGPRI 0x2 #define ARM_MMU_IDX_M_S 0x4 -#define ARM_MMU_IDX_TYPE_MASK (~0x7) -#define ARM_MMU_IDX_COREIDX_MASK 0x7 +#define ARM_MMU_IDX_TYPE_MASK (~0xf) +#define ARM_MMU_IDX_COREIDX_MASK 0xf typedef enum ARMMMUIdx { ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, @@ -2865,6 +2865,9 @@ typedef enum ARMMMUIdx { ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, + ARMMMUIdx_TagNS = 7 | ARM_MMU_IDX_A, + ARMMMUIdx_TagS = 8 | ARM_MMU_IDX_A, + ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M, @@ -2891,6 +2894,8 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_S1SE0 = 1 << 4, ARMMMUIdxBit_S1SE1 = 1 << 5, ARMMMUIdxBit_S2NS = 1 << 6, + ARMMMUIdxBit_TagNS = 1 << 7, + ARMMMUIdxBit_TagS = 1 << 8, ARMMMUIdxBit_MUser = 1 << 0, ARMMMUIdxBit_MPriv = 1 << 1, ARMMMUIdxBit_MUserNegPri = 1 << 2, @@ -3254,7 +3259,8 @@ enum { /* Return the address space index to use for a memory access */ static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) { - return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; + return ((attrs.target_tlb_bit2 ? ARMASIdx_TagNS : ARMASIdx_NS) + + attrs.secure); } /* Return the AddressSpace to use for a memory access diff --git a/target/arm/internals.h b/target/arm/internals.h index a434743b15..dfa395eb35 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -828,6 +828,7 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_S1NSE1: case ARMMMUIdx_S1E2: case ARMMMUIdx_S2NS: + case ARMMMUIdx_TagNS: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: @@ -836,6 +837,7 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_S1E3: case ARMMMUIdx_S1SE0: case ARMMMUIdx_S1SE1: + case ARMMMUIdx_TagS: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: diff --git a/target/arm/helper.c b/target/arm/helper.c index 17981d7c48..3147469899 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8658,9 +8658,18 @@ static inline bool regime_translation_disabled(CPUARMState *env, } } - if (mmu_idx == ARMMMUIdx_S2NS) { + switch (mmu_idx) { + case ARMMMUIdx_S2NS: /* HCR.DC means HCR.VM behaves as 1 */ return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) == 0; + + case ARMMMUIdx_TagS: + case ARMMMUIdx_TagNS: + /* These indexes are qemu internal, and are physically mapped. */ + return true; + + default: + break; } if (env->cp15.hcr_el2 & HCR_TGE) { @@ -10662,7 +10671,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, target_ulong *page_size, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { - if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { + switch (mmu_idx) { + case ARMMMUIdx_S12NSE0: + case ARMMMUIdx_S12NSE1: /* Call ourselves recursively to do the stage 1 and then stage 2 * translations. */ @@ -10713,6 +10724,16 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, */ mmu_idx = stage_1_mmu_idx(mmu_idx); } + break; + + case ARMMMUIdx_TagS: + case ARMMMUIdx_TagNS: + /* Indicate tag memory to arm_asidx_from_attrs. */ + attrs->target_tlb_bit2 = true; + break; + + default: + break; } /* The page table entries may downgrade secure to non-secure, but From patchwork Fri Oct 11 13:47:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175961 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp970781ocf; Fri, 11 Oct 2019 07:00:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqxE25qvfLj9Ah3HnxHZ3gW3bxcr/n5YEMAT0/4isLvoaNVYB+pDjrtvkz0RBirKd4OjGa+L X-Received: by 2002:ac8:2fe5:: with SMTP id m34mr16779264qta.254.1570802452674; Fri, 11 Oct 2019 07:00:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570802452; cv=none; d=google.com; s=arc-20160816; b=hOaXFOqr6LXN6HJaCLtwYKxR/u6K2jZmLFg9hzQlPqVT1QNSEqesJPUSM743HGFZsN cFWaeXvuhVv/2wY1WwF4krbu28ZHQCC+AIUNRG9iKID7+Cz+ABAY3y9z1NWfJuF5Y5Sd FrVGJQHc6D5bBUIeUTLBGF1F4E2Y3HPIfLtSSJbzR41ctkr5gUd7RHcJcCfHI4H4FHvC 6XaVYU78NEY6WOgyKd9GvGxqaWzetCEXq+WJhuF7/SpeWLf3d+TkB5RWb6rX8kT4QXho PV/yiEetbuKDfMqAQXpFkg0y1HuE63JckEASDLOzAVD9WZDVqGpR61qy4NMGIpGOg0mk Y9Tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=0RZ0xvYp1EHUhrR/jUU3w+01QyCWCYmAXLZX7xD3PR8=; b=ANKqAxW1juYhdkV6z2Q9ivI8CQ8majwO4A1cRMmUVUL6VH9N/5u3dgaRTv0h1e/VlV cdm0c4rj/JShaEyv+pipRmjelrfO9up6vGVBaLQsh2nhcXP/H4Vn80O+b7fs8lQ0drAC bUiXcjlNUqZ32YnUcyPHS13Z9VFYWmxkLJ0H4BHNsRYcq9+0apg3RY/rzTM8KJKFq+0C Mb1FFYCOz97SU27C51TkIcL1M5tEPhssUyIs1bvN37guuFbiWsCuJHd+j+benKT/HZiC E0g4DsBay1a3Jxf00ZpV2wL3TpskRtvVzKEIXg/b9fbzOkqCEfprEkX7Ukz31G07wP5X QW6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=uCEGC8kN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.50.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:50:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 22/22] target/arm: Add allocation tag storage for system mode Date: Fri, 11 Oct 2019 09:47:44 -0400 Message-Id: <20191011134744.2477-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 61 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) -- 2.17.1 diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index e8d8a6bedb..657383ba0e 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -28,8 +28,69 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, bool write, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY /* Tag storage not implemented. */ return NULL; +#else + CPUState *cs = env_cpu(env); + uintptr_t index; + int mmu_idx; + CPUTLBEntry *entry; + CPUIOTLBEntry *iotlbentry; + MemoryRegionSection *section; + hwaddr physaddr, tag_physaddr; + + /* + * Find the TLB entry for this access. + * As a side effect, this also raises an exception for invalid access. + * + * TODO: Perhaps there should be a cputlb helper that returns a + * matching tlb entry + iotlb entry. That would also be able to + * make use of the victim tlb cache, which is currently private. + */ + mmu_idx = cpu_mmu_index(env, false); + index = tlb_index(env, mmu_idx, ptr); + entry = tlb_entry(env, mmu_idx, ptr); + if (!tlb_hit(write ? tlb_addr_write(entry) : entry->addr_read, ptr)) { + bool ok = arm_cpu_tlb_fill(cs, ptr, 16, + write ? MMU_DATA_STORE : MMU_DATA_LOAD, + mmu_idx, false, ra); + assert(ok); + index = tlb_index(env, mmu_idx, ptr); + entry = tlb_entry(env, mmu_idx, ptr); + } + + /* If the virtual page MemAttr != Tagged, nothing to do. */ + iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index]; + if (!iotlbentry->attrs.target_tlb_bit1) { + return NULL; + } + + /* + * Find the physical address for the virtual access. + * + * TODO: It should be possible to have the tag mmu_idx map + * from main memory ram_addr to tag memory host address. + * that would allow this lookup step to be cached as well. + */ + section = iotlb_to_section(cs, iotlbentry->addr, iotlbentry->attrs); + physaddr = ((iotlbentry->addr & TARGET_PAGE_MASK) + ptr + + section->offset_within_address_space + - section->offset_within_region); + + /* Convert to the physical address in tag space. */ + tag_physaddr = physaddr >> (LOG2_TAG_GRANULE + 1); + + /* Choose the tlb index to use for the tag physical access. */ + mmu_idx = iotlbentry->attrs.secure ? ARMMMUIdx_TagS : ARMMMUIdx_TagNS; + mmu_idx = arm_to_core_mmu_idx(mmu_idx); + + /* + * FIXME: Get access length and type so that we can use + * probe_access, so that pages are marked dirty for migration. + */ + return tlb_vaddr_to_host(env, tag_physaddr, MMU_DATA_LOAD, mmu_idx); +#endif } static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra)