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(cpc115152-dals23-2-0-cust532.20-2.cable.virginm.net. [86.12.82.21]) by smtp.gmail.com with ESMTPSA id bg11-20020a05600c3c8b00b0041a9c3444a6sm11235579wmb.28.2024.04.25.06.44.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 06:44:44 -0700 (PDT) From: Connor Abbott To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: Connor Abbott Subject: [PATCH 1/6] arm64: dts: qcom: sm8650: Fix GPU cx_mem size Date: Thu, 25 Apr 2024 14:43:49 +0100 Message-Id: <20240425134354.1233862-2-cwabbott0@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20240425134354.1233862-1-cwabbott0@gmail.com> References: <20240425134354.1233862-1-cwabbott0@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This is doubled compared to previous GPUs. We can't access the new SW_FUSE_VALUE register without this. Fixes: db33633b05c0 ("arm64: dts: qcom: sm8650: add GPU nodes") Signed-off-by: Connor Abbott --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 658ad2b41c5a..78b8944eaab2 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2607,7 +2607,7 @@ tcsr: clock-controller@1fc0000 { gpu: gpu@3d00000 { compatible = "qcom,adreno-43051401", "qcom,adreno"; reg = <0x0 0x03d00000 0x0 0x40000>, - <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d9e000 0x0 0x2000>, <0x0 0x03d61000 0x0 0x800>; reg-names = "kgsl_3d0_reg_memory", "cx_mem", From patchwork Thu Apr 25 15:13:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Connor Abbott X-Patchwork-Id: 793118 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27E0F5B1F8 for ; Thu, 25 Apr 2024 15:13:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714058033; cv=none; b=uAUVsXwSjUajPqd47Pvx2yx3c4kXsBFQenn6hftkpB7fKcVvcN4a8UNHiZOG4qhEwNMlXNx9EzymGuvUthz6HJVpSlgkgL5RH2BwimefIcvD7C7RXwmTmW6JurCfaVl8Dezkmo5uEH82F7lE9c7CouG+SwKS8PYqbj56FcGzmhY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714058033; c=relaxed/simple; bh=XUzRs0wXBmoO+YZhtSTXqxFtPZp+CajmtQ3Vq2OGRfs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hTEGG3q5mMCxWE5/He8XGGSUCVHddHzYw2nkz0vqeNHZYrwS6lHX8rFYjuV+oZTgvzIrjoHqgm+npGxFP4tedRFmmHPzaYvEtHTU1K+l0XJXgMRcR7SI4UOr2k3SEXF8gguo2tPwFm/WzUDZhydRgDzc6Hou/+6MZ3mfybqis+w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=WjvTEbU0; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WjvTEbU0" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-41af670185fso8648455e9.0 for ; Thu, 25 Apr 2024 08:13:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1714058030; x=1714662830; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6DmU29abcyY7CYTw3DnjonwAFGdqYAvt0U0EAWoXp+E=; b=WjvTEbU0TpJXl32ZoiIoJgdwz1XvunmjcZNRYwruBi8R0CwHmPf6wVcdOhdtSzh9aa dbVzEQ0iFVUPxn/w6NJ1gwGOIVgD03uIWQE4a1ePDp0XUqUJZNJK38fcxRtHCqHP9Z+H blIfi0HRBdX8A8km2fEs90K2rPp9610WeM1nWjXWvjJiRznJgEuNTTVJm6hmuMgE+Sim P9jrwZQR6TQbkmihHqm9Ey89GswhP0/beWVp3xla9MAvfzs58Av3utCvqGWSxchHL0Yy vioD21/ykmUBI1yHoSyzbvE4o3TOsbq2T1UTHp/O5fBhrlEwCpikRp5VRF8POazyZQk0 NVkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714058030; x=1714662830; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6DmU29abcyY7CYTw3DnjonwAFGdqYAvt0U0EAWoXp+E=; b=AwZLJoWuQCe5Otr2VbFB5dy/x6NnUMpA4I4zGZ0RGhFmELB0uZ8tk5crkgPkBBDcuu qRvs1Zb+XLxPSO9Dto1CUvmXAmJZ3/26NSxdQGXb1DPJsdg/68rW5f/POk/+TFZS5Ks0 aoJeEOyPZB/qTlQ7eYZt99lbjVrn4/qyIn3DNzEYoCv/DnbKX6eQ3iU7adJb0zEFWM5D SpB8aBlru4Af0Z9+5Z+h4TscJ77tRgiyGYsBBKq8IydxT81Ui/28l3uKJAYIWC6BFbDA jm9ODXZWK7J/7N3eSy/9ko9cD6/+k/Xeof+/yvZKMO3ngrDTm1IvqbFOCOHIKfO9RU3n 7taA== X-Forwarded-Encrypted: i=1; AJvYcCU23czHMRdt6bJaY+cOH+pAaa++WD5a1AwsvOlPadeXQU610TXGscJdSdRzT9SqUmji/fwQeP1eDG2QD6DNsFKVFY/ikUZNOb4XMLz3qg== X-Gm-Message-State: AOJu0YybM68v5oBRGDoxHBSMugtBtYfZTTrg4XOlaggpzIaZUtm4lPde WEu/ApeXFMJELrLqo2CqeyqK07nb2sT1ygwnqaEVSLg93987s9qN X-Google-Smtp-Source: AGHT+IFFXYfdQYsPsqfNEjPFCn+04/lZ21MmuP1wB4vqmfruN/lavADhs3HDmd9y9onracT/rTsdAg== X-Received: by 2002:a05:600c:1f91:b0:41a:821b:37f7 with SMTP id je17-20020a05600c1f9100b0041a821b37f7mr4048108wmb.27.1714058030156; Thu, 25 Apr 2024 08:13:50 -0700 (PDT) Received: from lucy.. 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Signed-off-by: Connor Abbott --- drivers/firmware/qcom/qcom_scm.c | 14 ++++++++++++++ drivers/firmware/qcom/qcom_scm.h | 3 +++ include/linux/firmware/qcom/qcom_scm.h | 23 +++++++++++++++++++++++ 3 files changed, 40 insertions(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 06e46267161b..f8623ad0987c 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -1394,6 +1394,20 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, } EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh); +int qcom_scm_gpu_init_regs(u32 gpu_req) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_GPU, + .cmd = QCOM_SCM_SVC_GPU_INIT_REGS, + .arginfo = QCOM_SCM_ARGS(1), + .args[0] = gpu_req, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + return qcom_scm_call(__scm->dev, &desc, NULL); +} +EXPORT_SYMBOL_GPL(qcom_scm_gpu_init_regs); + static int qcom_scm_find_dload_address(struct device *dev, u64 *addr) { struct device_node *tcsr; diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_scm.h index 4532907e8489..484e030bcac9 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -138,6 +138,9 @@ int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_WAITQ_RESUME 0x02 #define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03 +#define QCOM_SCM_SVC_GPU 0x28 +#define QCOM_SCM_SVC_GPU_INIT_REGS 0x01 + /* common error codes */ #define QCOM_SCM_V2_EBUSY -12 #define QCOM_SCM_ENOMEM -5 diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index aaa19f93ac43..2c444c98682e 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -115,6 +115,29 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, int qcom_scm_lmh_profile_change(u32 profile_id); bool qcom_scm_lmh_dcvsh_available(void); +/** + * Request TZ to program set of access controlled registers necessary + * irrespective of any features + */ +#define QCOM_SCM_GPU_ALWAYS_EN_REQ BIT(0) +/** + * Request TZ to program BCL id to access controlled register when BCL is + * enabled + */ +#define QCOM_SCM_GPU_BCL_EN_REQ BIT(1) +/** + * Request TZ to program set of access controlled register for CLX feature + * when enabled + */ +#define QCOM_SCM_GPU_CLX_EN_REQ BIT(2) +/** + * Request TZ to program tsense ids to access controlled registers for reading + * gpu temperature sensors + */ +#define QCOM_SCM_GPU_TSENSE_EN_REQ BIT(3) + +int qcom_scm_gpu_init_regs(u32 gpu_req); + #ifdef CONFIG_QCOM_QSEECOM int qcom_scm_qseecom_app_get_id(const char *app_name, u32 *app_id); From patchwork Thu Apr 25 13:43:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Connor Abbott X-Patchwork-Id: 793121 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10CA8149C7B for ; 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Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 28 +++++++++++++++++-- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml index 78524aaab9d4..43fe90c12679 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml @@ -1227,6 +1227,7 @@ to upconvert to 32b float internally? + @@ -1503,6 +1504,9 @@ to upconvert to 32b float internally? + + + @@ -2842,7 +2846,11 @@ to upconvert to 32b float internally? - + + RB_SAMPLE_COUNT_ADDR register is used up to (and including) a730. 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(cpc115152-dals23-2-0-cust532.20-2.cable.virginm.net. [86.12.82.21]) by smtp.gmail.com with ESMTPSA id bg11-20020a05600c3c8b00b0041a9c3444a6sm11235579wmb.28.2024.04.25.06.44.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 06:44:47 -0700 (PDT) From: Connor Abbott To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org Cc: Connor Abbott Subject: [PATCH 4/6] drm/msm/a7xx: Initialize a750 "software fuse" Date: Thu, 25 Apr 2024 14:43:52 +0100 Message-Id: <20240425134354.1233862-5-cwabbott0@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20240425134354.1233862-1-cwabbott0@gmail.com> References: <20240425134354.1233862-1-cwabbott0@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled. Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 89 ++++++++++++++++++++++++- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 + 2 files changed, 90 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index cf0b1de1c071..fb2722574ae5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -10,6 +10,7 @@ #include #include +#include #include #include @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu) A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \ - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR) + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \ + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \ A6XX_CP_APRIV_CNTL_RBFETCH | \ @@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu) kthread_queue_work(gpu->worker, &gpu->recover_work); } +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu) +{ + u32 status; + + status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS); + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0); + + dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status); + + /* Ignore FASTBLEND violations, because the HW will silently fall back + * to legacy blending. + */ + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) { + del_timer(&gpu->hangcheck_timer); + + kthread_queue_work(gpu->worker, &gpu->recover_work); + } +} + static irqreturn_t a6xx_irq(struct msm_gpu *gpu) { struct msm_drm_private *priv = gpu->dev->dev_private; @@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu) if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) + a7xx_sw_fuse_violation_irq(gpu); + if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) msm_gpu_retire(gpu); @@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct platform_device *pdev, a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL); } +static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu) +{ + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + struct msm_gpu *gpu = &adreno_gpu->base; + u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ; + u32 fuse_val; + int ret; + + if (adreno_is_a740(adreno_gpu)) { + /* Raytracing is always enabled on a740 */ + adreno_gpu->has_ray_tracing = true; + } + + if (!qcom_scm_is_available()) { + /* Assume that if qcom scm isn't available, that whatever + * replacement allows writing the fuse register ourselves. + * Users of alternative firmware need to make sure this + * register is writeable or indicate that it's not somehow. + * Print a warning because if you mess this up you're about to + * crash horribly. + */ + if (adreno_is_a750(adreno_gpu)) { + dev_warn_once(gpu->dev->dev, + "SCM is not available, poking fuse register\n"); + a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE, + A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | + A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND | + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC); + adreno_gpu->has_ray_tracing = true; + } + + return 0; + } + + if (adreno_is_a750(adreno_gpu)) + gpu_req |= QCOM_SCM_GPU_TSENSE_EN_REQ; + + ret = qcom_scm_gpu_init_regs(gpu_req); + if (ret) + return ret; + + /* On a750 raytracing may be disabled by the firmware, find out whether + * that's the case. The scm call above sets the fuse register. + */ + if (adreno_is_a750(adreno_gpu)) { + fuse_val = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE); + adreno_gpu->has_ray_tracing = + !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING); + } + + return 0; +} + + #define GBIF_CLIENT_HALT_MASK BIT(0) #define GBIF_ARB_HALT_MASK BIT(1) #define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0) @@ -3094,6 +3173,14 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) return ERR_PTR(ret); } + if (adreno_is_a7xx(adreno_gpu)) { + ret = a7xx_cx_mem_init(a6xx_gpu); + if (ret) { + a6xx_destroy(&(a6xx_gpu->base.base)); + return ERR_PTR(ret); + } + } + if (gpu->aspace) msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, a6xx_fault_handler); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 77526892eb8c..4180f3149dd8 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -182,6 +182,8 @@ struct adreno_gpu { */ const unsigned int *reg_offsets; bool gmu_is_wrapper; + + bool has_ray_tracing; }; #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) From patchwork Thu Apr 25 13:43:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Connor Abbott X-Patchwork-Id: 793120 Received: from mail-lj1-f180.google.com (mail-lj1-f180.google.com [209.85.208.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E22612BE8C for ; Thu, 25 Apr 2024 13:44:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714052692; cv=none; b=ZP1gJB5FGcBjJJRcO6eUcKvoxeUWso6mPgSCwA+V0SHIYCG4k52cfjExh7a1WgANTrUWbVl7cdxRIcZ1nHFbrsjs44YxAWgFdgzhoG1xQgdNsw55+e6ufONYkH71/1b1Tpdhy3echztW1qFv9p6JdZ/IdMUEymlN+AyxfArfzG4= ARC-Message-Signature: i=1; a=rsa-sha256; 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(cpc115152-dals23-2-0-cust532.20-2.cable.virginm.net. [86.12.82.21]) by smtp.gmail.com with ESMTPSA id bg11-20020a05600c3c8b00b0041a9c3444a6sm11235579wmb.28.2024.04.25.06.44.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 06:44:49 -0700 (PDT) From: Connor Abbott To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org Cc: Connor Abbott Subject: [PATCH 5/6] drm/msm: Add MSM_PARAM_RAYTRACING uapi Date: Thu, 25 Apr 2024 14:43:53 +0100 Message-Id: <20240425134354.1233862-6-cwabbott0@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20240425134354.1233862-1-cwabbott0@gmail.com> References: <20240425134354.1233862-1-cwabbott0@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Expose the value of the software fuse to userspace. Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++ include/uapi/drm/msm_drm.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 074fb498706f..99ad651857b2 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -376,6 +376,9 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, case MSM_PARAM_HIGHEST_BANK_BIT: *value = adreno_gpu->ubwc_config.highest_bank_bit; return 0; + case MSM_PARAM_RAYTRACING: + *value = adreno_gpu->has_ray_tracing; + return 0; default: DBG("%s: invalid param: %u", gpu->name, param); return -EINVAL; diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index d8a6b3472760..3fca72f73861 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -87,6 +87,7 @@ struct drm_msm_timespec { #define MSM_PARAM_VA_START 0x0e /* RO: start of valid GPU iova range */ #define MSM_PARAM_VA_SIZE 0x0f /* RO: size of valid GPU iova range (bytes) */ #define MSM_PARAM_HIGHEST_BANK_BIT 0x10 /* RO */ +#define MSM_PARAM_RAYTRACING 0x11 /* RO */ /* For backwards compat. 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(cpc115152-dals23-2-0-cust532.20-2.cable.virginm.net. [86.12.82.21]) by smtp.gmail.com with ESMTPSA id bg11-20020a05600c3c8b00b0041a9c3444a6sm11235579wmb.28.2024.04.25.06.44.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 06:44:50 -0700 (PDT) From: Connor Abbott To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org Cc: Connor Abbott Subject: [PATCH 6/6] drm/msm/a7xx: Add missing register writes from downstream Date: Thu, 25 Apr 2024 14:43:54 +0100 Message-Id: <20240425134354.1233862-7-cwabbott0@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20240425134354.1233862-1-cwabbott0@gmail.com> References: <20240425134354.1233862-1-cwabbott0@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This isn't known to fix anything yet, but it's a good idea to add it. Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index fb2722574ae5..e015f3b43bac 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1953,6 +1953,14 @@ static int hw_init(struct msm_gpu *gpu) BIT(6) | BIT(5) | BIT(3) | BIT(2) | BIT(1)); } + if (adreno_is_a750(adreno_gpu)) { + gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19)); + + gpu_write(gpu, REG_A6XX_TPL1_DBG_ECO_CNTL1, 0xc0700); + } else if (adreno_is_a7xx(adreno_gpu)) { + gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19)); + } + /* Enable interrupts */ gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, adreno_is_a7xx(adreno_gpu) ? A7XX_INT_MASK : A6XX_INT_MASK);