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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(376005)(36860700004)(1800799015)(82310400014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Apr 2024 06:35:12.6553 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2ccfa2f7-21f3-4b2e-59b3-08dc65bb06cd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000141.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7311 There are some other drivers also need to use the MSR_K7_HWCR_CPB_DIS_BIT for CPB control bit, so it makes sense to move the definition to a common header file to allow other driver to use it. No intentional functional impact. Suggested-by: Gautham Ranjal Shenoy Signed-off-by: Perry Yuan Acked-by: Rafael J. Wysocki Acked-by: Huang Rui --- arch/x86/include/asm/msr-index.h | 2 ++ drivers/cpufreq/acpi-cpufreq.c | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index e72c2b872957..8738a7b3917d 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -782,6 +782,8 @@ #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) #define MSR_K7_FID_VID_CTL 0xc0010041 #define MSR_K7_FID_VID_STATUS 0xc0010042 +#define MSR_K7_HWCR_CPB_DIS_BIT 25 +#define MSR_K7_HWCR_CPB_DIS BIT_ULL(MSR_K7_HWCR_CPB_DIS_BIT) /* K6 MSRs */ #define MSR_K6_WHCR 0xc0000082 diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c index 37f1cdf46d29..2fc82831bddd 100644 --- a/drivers/cpufreq/acpi-cpufreq.c +++ b/drivers/cpufreq/acpi-cpufreq.c @@ -50,8 +50,6 @@ enum { #define AMD_MSR_RANGE (0x7) #define HYGON_MSR_RANGE (0x7) -#define MSR_K7_HWCR_CPB_DIS (1ULL << 25) - struct acpi_cpufreq_data { unsigned int resume; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH2PEPF00000141.mail.protection.outlook.com (10.167.244.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7519.19 via Frontend Transport; Fri, 26 Apr 2024 06:35:19 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 26 Apr 2024 01:35:15 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v8 3/6] cpufreq: amd-pstate: implement cpb_boost sysfs entry for boost control Date: Fri, 26 Apr 2024 14:34:46 +0800 Message-ID: <64eb440fd48d10a55525253bce2e9143db872f67.1714112854.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000141:EE_|SA1PR12MB6948:EE_ X-MS-Office365-Filtering-Correlation-Id: f80683ae-20fe-42b1-04a1-08dc65bb0aa6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: W4AyxeipiLc8BPvRkf0226ehGa+7cfYY/c16iuHJ+g71ykQhUxCKN/vE5ISpVUqSJuW7hkfbDKns3xC/vCtl2QCTHIg53huTfB13pW1OoW/TlTrS9j/ETM0qDQt+NVciRmy6nNGTpuGjHZGrqDq68iIV0XK6RmWGXXy26vRsHt8UC/jgUIytjZ6cZCOoyHUtQ92n0LoXaZLx397ON98ntuwhHV97Hk3AjDuPm0vKadHxIQfHMEvfAOlr3g6KSGBbm2e7loPzI1B4e7JLGIsR8eih6hNWjifL45eN2HTDqRcBEKmPJr4iQ732bYLws0oxpkgoD/EueNSLOc+B8pdPij1h9oIiz/AqByutyAI3cbodzqAE1Da7xkjo4PoiT1o2gfie4WG7yj+VuZnI3cwPdv7pNigQN2hM5c6/Ks90hrUE25TnN5XKIKnNUAgtyVtchZoLlQal4tdyC+ftMIl+7fYJ6jiv2HOwU6GssBqO2PhOgZA1gmVCqVBBNAOGiEbsKwbKKQP6gybSgfA//IRcl+YrCOPbjFvyM7KFGoVnWqasZW2MDbk6Rh/lmnYa3lXwpRcE5zvxTPqHgSA3nDRDhVWGcF9AC7hG/hkxhSALI8AsvNTM9rijGi+If5SzdbiVWONsdyE/FNrEC60Q2ml3blnn9mMAIfT06FpFbepBwHNR//cH9/awVg1jpea79rf1uzYXbfEWuoV+c2ECyIbS+JOierloAe4UbpvdFER5RvAwrQ1Ht3N9GeDtJFR1i/sAzmG4USnzhrPiL8V38IG7QSGrMZjDw+Tx7zH77DW3BeTo7svhl1ouyukcMPrDqrjnr6fdq8MYBuo7QB0dg9KdAS1YOILP2FEQjEhl1hlIixH+i/ObulFqB5S3XeZyeZmBptVZzZCE/mEvbCyjUGeJ0GKDJ8DXiNiMVOHL3Wl/t+rFIXa/2z5CABoz/AG51vnV4vN9wCiQWJztoBsuja9dOr34Ehmrv6WbsKos7OCe2Gw566nPFVvUfauGY+p/y88dVXAgu/EGoyVqLJA8TBqmnQ9bb3vOPsQGazoT3ibECD8CiTsqDRv43mRdE1te77owxm9TJqUD/oopzOYsDuxhOftcdQFTpAaG5FKTQJyqIuCOG/WKNSfoSViTwr51oycxvL4Y6Slryzxt10hixOxDxuIc42jiQR0AA1mQgsJ+Ipl5e6Xjw8Xa7hJrf0XV3K78QQZ4ut1UxEOrx3pxmmmncYgQmzexBWuYTA/J3B3kIHCBeQMd9114Bz1K1qe9lEV3ed/jjgCNd7zBFQfHUdTJ++cyCqfx/ldcgpi/MhVqW9SAtVY8KuPZW1AX/hQTMtS6fhwIoUR/BwNW7NdHDk8Dotx4wZvcUVHWa9CXYzSUshIO6Pw5ujNnoWCxoupzx0lb X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(36860700004)(376005)(1800799015)(82310400014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Apr 2024 06:35:19.1084 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f80683ae-20fe-42b1-04a1-08dc65bb0aa6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000141.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6948 From: Perry Yuan With this new sysfs entry `cpb_boost`created, user can change CPU boost state dynamically under `active`, `guided` and `passive` modes. And the highest perf and frequency will also be updated as the boost state changing. 0): check current boost state cat /sys/devices/system/cpu/amd_pstate/cpb_boost 1): disable CPU boost sudo bash -c "echo 0 > /sys/devices/system/cpu/amd_pstate/cpb_boost" 2): enable CPU boost sudo bash -c "echo 1 > /sys/devices/system/cpu/amd_pstate/cpb_boost" Link: https://bugzilla.kernel.org/show_bug.cgi?id=217931 Link: https://bugzilla.kernel.org/show_bug.cgi?id=217618 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 99 ++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index aa17a3134497..53ef39c6dbfa 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1295,6 +1295,103 @@ static ssize_t prefcore_show(struct device *dev, return sysfs_emit(buf, "%s\n", str_enabled_disabled(amd_pstate_prefcore)); } +static int amd_cpu_boost_update(struct amd_cpudata *cpudata, u32 on) +{ + struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu); + struct cppc_perf_ctrls perf_ctrls; + u32 highest_perf, nominal_perf, nominal_freq, max_freq; + int ret; + + if (!policy) + return -ENODATA; + + highest_perf = READ_ONCE(cpudata->highest_perf); + nominal_perf = READ_ONCE(cpudata->nominal_perf); + nominal_freq = READ_ONCE(cpudata->nominal_freq); + max_freq = READ_ONCE(cpudata->max_freq); + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 value = READ_ONCE(cpudata->cppc_req_cached); + + value &= ~GENMASK_ULL(7, 0); + value |= on ? highest_perf : nominal_perf; + WRITE_ONCE(cpudata->cppc_req_cached, value); + + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + } else { + perf_ctrls.max_perf = on ? highest_perf : nominal_perf; + ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1); + if (ret) { + cpufreq_cpu_release(policy); + pr_debug("failed to set energy perf value (%d)\n", ret); + return ret; + } + } + + if (on) + policy->cpuinfo.max_freq = max_freq; + else + policy->cpuinfo.max_freq = nominal_freq * 1000; + + policy->max = policy->cpuinfo.max_freq; + + if (cppc_state == AMD_PSTATE_PASSIVE) { + ret = freq_qos_update_request(&cpudata->req[1], + policy->cpuinfo.max_freq); + } + + cpufreq_cpu_release(policy); + + return ret; +} + +static ssize_t cpb_boost_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%u\n", amd_pstate_global_params.cpb_boost); +} + +static ssize_t cpb_boost_store(struct device *dev, struct device_attribute *b, + const char *buf, size_t count) +{ + bool new_state; + ssize_t ret; + int cpu; + + if (!amd_pstate_global_params.cpb_supported) { + pr_err("Boost mode is not supported by this processor or SBIOS\n"); + return -EINVAL; + } + + ret = kstrtobool(buf, &new_state); + if (ret) + return ret; + + mutex_lock(&amd_pstate_driver_lock); + amd_pstate_global_params.cpb_boost = !!new_state; + + for_each_present_cpu(cpu) { + + struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); + struct amd_cpudata *cpudata = policy->driver_data; + + if (!cpudata) { + pr_err("cpudata is NULL\n"); + ret = -ENODATA; + cpufreq_cpu_put(policy); + goto err_exit; + } + + amd_cpu_boost_update(cpudata, amd_pstate_global_params.cpb_boost); + refresh_frequency_limits(policy); + cpufreq_cpu_put(policy); + } + +err_exit: + mutex_unlock(&amd_pstate_driver_lock); + return ret < 0 ? ret : count; +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); @@ -1305,6 +1402,7 @@ cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); static DEVICE_ATTR_RW(status); static DEVICE_ATTR_RO(prefcore); +static DEVICE_ATTR_RW(cpb_boost); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, @@ -1329,6 +1427,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { static struct attribute *pstate_global_attributes[] = { &dev_attr_status.attr, &dev_attr_prefcore.attr, + &dev_attr_cpb_boost.attr, NULL }; From patchwork Fri Apr 26 06:34:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Perry Yuan X-Patchwork-Id: 792549 Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam02on2053.outbound.protection.outlook.com [40.107.95.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 001CC13A403; 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Fri, 26 Apr 2024 01:35:22 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v8 5/6] Documentation: cpufreq: amd-pstate: introduce the new cpu boost control method Date: Fri, 26 Apr 2024 14:34:48 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000013D:EE_|IA1PR12MB7518:EE_ X-MS-Office365-Filtering-Correlation-Id: f0200f6c-1cf2-42ff-27db-08dc65bb0e8d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wxF86MDoTt5rtzQXs4xmHnmEQRlew3zbQLSxO8FjNsXVi/7bV/9CczfbRqBMdTYEZSDZ0hHm5ZLO05KK13+L6kIBj3CABcd1I7JzAMCsAHazFCx/gLu/NMHWldag82AxR59b2WaYpENDtW58MF3XkKS7iYkurZrlxQeEmiCSnf6HgG207WB2/fRyNGqLjx6eyC1pFnBx0qCDu8mumhSXXCc7Gvsb17BIR15b85tyLQFhhGzF+8i7eAmOO0omNRQvn66aoNnKkNtpYIslgDt3dCGWimssEfIqMOhmkIxZ023JRODOSvSaRf1bgrzfO6tMLO1FM5qoSpshZoH+mS/pIjEsP3K40yn5YyDh3DWBlBjjQKVp+V7pIB6hEaTdko6aAFQN48rh9cLVQrRihhPzsy+ZlY01HK2FvZiCdZrKdexP3UEFCdMF82oJmXSsQpp+38z0zstE3VuK6KWMc/a35cRZ5urP04LTOje5vMct6bTmpE50AACBvSdxQhk7or72Ht8ad+rofL19roOPtYMaHbmG3nNCeVXrJQ1tQ/IybLe3vq/MB1nTjrrTzoVGtxPaq+6Ckt+BJMZAVTDZz7hVirgCyky4yNpKXsvVzdTebJzjKI349nw7QheCxd6Jmw2f4fem9nKp04vdRYvF9Hw8AMRolD6sz624YwPdVduKFeYB9bB5jr11DEblUaulYCb2NgFzpraLZi3G/kEhZ2bIcoFpzJ0dtkkY4uUUh4svzhbRVrFsDSF/BEZYmuXmA2utYfA5516X37cGkd8Vn/rA+C35kzHWKzValH8UzdZ4yN5UheI26veSDosFFCgcxIs8w6nHTXWbYpn/Q+pgogc78OdIAfGW5YcBSDhEF2axSUFdU3V5jGKJe/NtQc+vvilcfutd5ROTPeOuHulmnNPDDnLh7oOcviFjmN6Zs9qnbOm6P5ZXUhi/w7dv7nJIxhZpfYNixMjfvlhF1Wbc659bJ1oSSWoB2bm9yL0W2dgQZkeXvCB02gBFGDzYc1EPj9XgrjFI8WodmHLgpRuXRfTPaQVT2rsAjH9vPKn8B4jgMWM4gyEdjc2qce8TuvjBFvx0kP6dMot3Wq3VYKOQPonmbkGjgjutIXBsJRn1XEZrJKI6xcvMK3i741MT/3BrY9ZOsRaxjpEK5cLp42CDdF9P64Vci0FL0lyOMPL5pjjoUp3gnidfSf2xTZ4UvEvSChygfzdPZaBb/tfEMYj7+a6InsEuSPVSIM/Z/4/Clram9g16IvO30Je8Jovcf2pLRZwI9DYuYJq3NfAxZvWvWPWA1Tz6FSEN6gRnUQ4b4aGfeTCmNLmRd2FcWshFYNzT/XuzT8BBNcLoJOb2sXT4iuiTrf6kNoZykNyBFD+izuxDJqVgmVyjBQ5dFTy5MsFyZF8e X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(82310400014)(376005)(1800799015)(36860700004); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Apr 2024 06:35:25.6564 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f0200f6c-1cf2-42ff-27db-08dc65bb0e8d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7518 From: Perry Yuan Introduce AMD CPU frequency boosting control sysfs entry which used for switching boost on and boost off. If core performance boost is disabled while a core is in a boosted P-state, the core automatically transitions to the highest performance non-boosted P-state The highest perf and frequency will be limited by the setting value. Signed-off-by: Perry Yuan --- Documentation/admin-guide/pm/amd-pstate.rst | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 1e0d101b020a..82fbd01da658 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -440,6 +440,17 @@ control its functionality at the system level. They are located in the This attribute is read-only to check the state of preferred core set by the kernel parameter. +``cpb_boost`` + Specifies whether core performance boost is requested to be enabled or disabled + If core performance boost is disabled while a core is in a boosted P-state, the + core automatically transitions to the highest performance non-boosted P-state. + AMD Core Performance Boost(CPB) is controlled by this new attribute file which + allow user to change all cores frequency boosting state. It supports both + ``active``, ``passive`` and ``guided`` mode control with below value write to it. + + "0" Disable Core Performance Boosting + "1" Enable Core Performance Boosting + ``cpupower`` tool support for ``amd-pstate`` ===============================================