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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/21] hw/core/clock: allow clock_propagate on child clocks Date: Tue, 30 Apr 2024 17:48:22 +0100 Message-Id: <20240430164842.4074734-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Raphael Poggi clock_propagate() has an assert that clk->source is NULL, i.e. that you are calling it on a clock which has no source clock. This made sense in the original design where the only way for a clock's frequency to change if it had a source clock was when that source clock changed. However, we subsequently added multiplier/divider support, but didn't look at what that meant for propagation. If a clock-management device changes the multiplier or divider value on a clock, it needs to propagate that change down to child clocks, even if the clock has a source clock set. So the assertion is now incorrect. Remove the assertion. Signed-off-by: Raphael Poggi Message-id: 20240419162951.23558-1-raphael.poggi@lynxleap.co.uk Reviewed-by: Peter Maydell [PMM: Rewrote the commit message] Signed-off-by: Peter Maydell --- hw/core/clock.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/core/clock.c b/hw/core/clock.c index a19c7db7df9..e212865307b 100644 --- a/hw/core/clock.c +++ b/hw/core/clock.c @@ -108,7 +108,6 @@ static void clock_propagate_period(Clock *clk, bool call_callbacks) void clock_propagate(Clock *clk) { - assert(clk->source == NULL); trace_clock_propagate(CLOCK_PATH(clk)); clock_propagate_period(clk, true); } From patchwork Tue Apr 30 16:48:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 793336 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp365639wrf; Tue, 30 Apr 2024 09:49:26 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW7ETjMEKurt0DN/1TktdpuXhVpEXVg7JG+W5vfcrnwXKd8cTZ6QRGgwPTnZQg6NSSw4JmeplV+jN1gaYrBqkAI X-Google-Smtp-Source: AGHT+IE/1ck4hsAhZUdyr6OziuBN0rgpdvCGyGyy9EPTy134Rt8xpjakFYEOPOpWFNfvlVziL6f+ X-Received: by 2002:a05:620a:3632:b0:78e:bd2d:1689 with SMTP id da50-20020a05620a363200b0078ebd2d1689mr14471566qkb.36.1714495765873; Tue, 30 Apr 2024 09:49:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714495765; cv=none; d=google.com; s=arc-20160816; b=gbZFKt9RQTebDfNEPpYepGrN4Mv1/+sB2Ifm7/p0QdqBFrvhHm5Kk6bpoO/xlH0CYp Hsf01HWRKk6Omv89heDHMqNxA1DlUly3qgmc8jICkd+eVzJ6una9SA5zh/seW+gAPxud nmOu24FmoRFLyL1duQG6QGIPmdnjNbPvzUO9XmIkXXVPWLUVhrmoiUs05i4Jvm/GLF8/ Hed0bPSYezBw004NzUHFKgsi2uuZATJzi6uV03XpQqafyt2FfyMidkiAqzxLTqBAbdbE ntUE4JAzuIue4iVsZotdzWTxnRPL9hEBkgE0MEPlCATBioSPycGRba3wTSwpzuy/dU8v sVBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rohcqdho/QsiHvs0ZVMO0uh/LJCHZLF+RintcSkxghs=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=SFscfQUSVbwPh+OPnvC8j6ZH0c6JK75lC8AeOhc9ru+92aZ5f/Gg47szOzoAkgXaFl k73g3luH1pFABcK+nJuKoR81K2gwzKaYWnA8mA1x7QbajAeRP9Gh1GAO+1CDY2fWZocf q/neZSUff7tBp3jtEndybvd5XO/Dhp0ElViAcxzRr1Oyd4aXOe4RIcOjHOIJZa94k12l bTlPA1o76KUTo1WQ1x4r+qiUbZvHRn6luk6JmGZhyLwkDp8YmrfAslrsQ0pmMVhA7Ec5 JnWqFB+zL8B+4LrsFmE7l4iXV2dqACylGC6l7ov8DEU6q8anMjsouhwhTit8AWRoAIKt pIlA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="dJSQg/s6"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/21] hvf: arm: Remove PL1_WRITE_MASK Date: Tue, 30 Apr 2024 17:48:23 +0100 Message-Id: <20240430164842.4074734-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Zenghui Yu As it had never been used since the first commit a1477da3ddeb ("hvf: Add Apple Silicon support"). Signed-off-by: Zenghui Yu Message-id: 20240422092715.71973-1-zenghui.yu@linux.dev Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index db628c1cba7..8e942f89b35 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -150,7 +150,6 @@ void hvf_arm_init_debug(void) #define HVF_SYSREG(crn, crm, op0, op1, op2) \ ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) -#define PL1_WRITE_MASK 0x4 #define SYSREG_OP0_SHIFT 20 #define SYSREG_OP0_MASK 0x3 From patchwork Tue Apr 30 16:48:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 793344 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp366219wrf; Tue, 30 Apr 2024 09:50:43 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW/EzMNhBPwCmeq9gj/CyOX54bA2GndnZbW3S/Nbc6qif4WegoeeHeTjflAtUjA3IktM1rSY1ePrf36ZJ4Xff1y X-Google-Smtp-Source: AGHT+IGoX3xhcJFBKa/5xqtHcfsSJP6nZ4Rc6jNczoag3viEpU3udivZj0WIszKA5+vgMtndhr/q X-Received: by 2002:a05:6214:21ec:b0:69b:20c6:a3f1 with SMTP id p12-20020a05621421ec00b0069b20c6a3f1mr17933900qvj.53.1714495842984; Tue, 30 Apr 2024 09:50:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714495842; cv=none; d=google.com; s=arc-20160816; b=atdSanCKYym81MHgAdmvrDYpBMfz0KBQ7z627ZqE6t6btqj+svuROgP3U4uFoDiarC 29vz0o/VP2mf1XyuE1+/Xh1Ew43PX3mkr7Oitw0peEbyClSXio1De6hyDmclI3IESAQI LZdORxo6joS8qqP91QsChsl/USc0ppm8Y5aWCb0mvkoR8CAZ/xQbduiF0N8LFMyEH+/m 6g6c/2xJKibNd0w4mXUnsxfhiZ72bGSLAGil+kSik2z9jifEoNicRKSEqCHCC0zwFQ5Q TVn5rB5iUjF1Ix7jukxKYWyPbse8K0NpKHfzakdfXKDptNGUhQX0yDOmqvmpQM4FkNbg PRVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hthA/3V7Cmo8odD0drLBUjy1wpShyNiLm+eJGK3MJJQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=x5+4YBcoZ8uJmDlAkxIRc3mPBm90aCB0BPL6yVx67O8LBt7b51LZ+0l9Ww2kDVEoh8 XxRRM9VA6YddKhdwMVvI9Thva9BMqoWZQ4cB+gcsHhG8VaeMqG3I0lKXIYwv7/QKaJ28 489ztu+xNiaBQl0oCw5DFEw91H8O3yaR8FaPH7Nu13yYR0LlqZhTvag4BRnt6/F3IXFF qAtumSk/3AmbVPDDh0h+qzJq6qBRo2VkguefP/4pZDMQV/PYs0bgiaeWP6MGJbJlF1BG nARXddDnNsEqpaCUfNOvfzrl+Haj/99WttEUjG6tf9rZDISthc2Zj4AKX8BLEtRGi7Cc /ZuA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="K0ScF/CF"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/21] target/arm: Restrict translation disabled alignment check to VMSA Date: Tue, 30 Apr 2024 17:48:24 +0100 Message-Id: <20240430164842.4074734-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson For cpus using PMSA, when the MPU is disabled, the default memory type is Normal, Non-cachable. This means that it should not have alignment restrictions enforced. Cc: qemu-stable@nongnu.org Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled") Reported-by: Clément Chigot Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Clément Chigot Message-id: 20240422170722.117409-1-richard.henderson@linaro.org [PMM: trivial comment, commit message tweaks] Signed-off-by: Peter Maydell --- target/arm/tcg/hflags.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 5da1b0fc1d4..f03977b4b00 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -38,8 +38,16 @@ static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr) } /* - * If translation is disabled, then the default memory type is - * Device(-nGnRnE) instead of Normal, which requires that alignment + * With PMSA, when the MPU is disabled, all memory types in the + * default map are Normal, so don't need aligment enforcing. + */ + if (arm_feature(env, ARM_FEATURE_PMSA)) { + return false; + } + + /* + * With VMSA, if translation is disabled, then the default memory type + * is Device(-nGnRnE) instead of Normal, which requires that alignment * be enforced. Since this affects all ram, it is most efficient * to handle this during translation. */ From patchwork Tue Apr 30 16:48:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 793340 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp365865wrf; Tue, 30 Apr 2024 09:49:59 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUKeBOjsQkymRaa4QNaBIvHEcY5rGnwpFD2KE2RBVUmaao+lV5evtTKTjfXeMCCGoJK1+8isE5SI22JnRcwX1tY X-Google-Smtp-Source: AGHT+IFlZ4qonouNSUgbKO/KSSyLq0oNMwMMjhVLhPv0igTyEEMWbFnHt6kh8KFVn3rWexwsgXR+ X-Received: by 2002:ac8:7fcc:0:b0:43a:b697:ec8f with SMTP id b12-20020ac87fcc000000b0043ab697ec8fmr10784505qtk.57.1714495799341; Tue, 30 Apr 2024 09:49:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714495799; cv=none; d=google.com; s=arc-20160816; b=wvkXchNPWX+3YUB9YYA3CESr7SaE29wU5kygs5F+EfNFbgn6nb0H8+UJtt1jHVm1Yy T9X1b9jtvZpOFQLk8xf32+KvXxVvA7l+NYsKqG+RA5MzjXBt7DJQg0+Uyhov8SAd3F/Z snAFRdK6Xhs9SJibwgPcwamw3yWE9jL8LAjWyuR1n1wnSCJYLUx5dSSdSB/nV3ycMehy WdJT+vph4pDVdMEDDT9virl/5seY8E+c+4FFHe9e9cMBrVy+Cr9O+/XEePPcmtoZsh5z 2bumAp0eb+WIjOHKV4+OmiEJarzdvGm4VJ9D+/fA8PehwizbacyMGbPlg6iBQOfFyufy FOEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GnJgeVKHvPlaeZft/qWQKP+8OV+SlqGxnSR+/DTTccU=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=FwD2hScvsKfj6WAG13iiYKIchUIb+Ml2c1xJrrDy8001CB96RWWu8DT2l/8NmyVeCy jj8xbPD3pVuWjQZMZt5QVJs3c9CbuXAYTIslC02R5FvWumnU4TdDhIpw1bNMRsNVLbxN BN7bv+aEwqj9cjgYmvLq3kJpuTcWdANVf1LrwhJcHyzj7x12suE+16jE54+heUfsiFiQ eFmbzCnV6wpaJAtsRwSV+qr29cLRgrh+XuruRYSEcOsaaX+cD1bE6YCdA3rLURjDttm5 b3h6jkIvDE8fAOBDdXaDfhs5G/CEqVbwMuT96SU1kgU0/CksubfsSUYvSttrKIPrMwsO 4SKw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OUmHPBF4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/21] docs/system/arm/emulation.rst: Add missing implemented features Date: Tue, 30 Apr 2024 17:48:25 +0100 Message-Id: <20240430164842.4074734-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org As of version DDI0487K.a of the Arm ARM, some architectural features which previously didn't have official names have been named. Add these to the list of features which QEMU's TCG emulation supports. Mostly these are features which we thought of as part of baseline 8.0 support. For SVE and SVE2, the names have been brought into line with the FEAT_* naming convention of other extensions, and some sub-components split into separate FEAT_ items. In a few cases (eg FEAT_CCIDX, FEAT_DPB2) the omission from our list was just an oversight. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240418152004.2106516-2-peter.maydell@linaro.org --- docs/system/arm/emulation.rst | 38 +++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index a9ae7ede9fc..5fdc64a944f 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -8,13 +8,26 @@ Armv8 versions of the A-profile architecture. It also has support for the following architecture extensions: - FEAT_AA32BF16 (AArch32 BFloat16 instructions) +- FEAT_AA32EL0 (Support for AArch32 at EL0) +- FEAT_AA32EL1 (Support for AArch32 at EL1) +- FEAT_AA32EL2 (Support for AArch32 at EL2) +- FEAT_AA32EL3 (Support for AArch32 at EL3) - FEAT_AA32HPD (AArch32 hierarchical permission disables) - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions) +- FEAT_AA64EL0 (Support for AArch64 at EL0) +- FEAT_AA64EL1 (Support for AArch64 at EL1) +- FEAT_AA64EL2 (Support for AArch64 at EL2) +- FEAT_AA64EL3 (Support for AArch64 at EL3) +- FEAT_AdvSIMD (Advanced SIMD Extension) - FEAT_AES (AESD and AESE instructions) +- FEAT_Armv9_Crypto (Armv9 Cryptographic Extension) +- FEAT_ASID16 (16 bit ASID) - FEAT_BBM at level 2 (Translation table break-before-make levels) - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) +- FEAT_CCIDX (Extended cache index) - FEAT_CRC32 (CRC32 instructions) +- FEAT_Crypto (Cryptographic Extension) - FEAT_CSV2 (Cache speculation variant 2) - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) @@ -23,18 +36,27 @@ the following architecture extensions: - FEAT_DGH (Data gathering hint) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) +- FEAT_DPB2 (DC CVADP instruction) +- FEAT_Debugv8p1 (Debug with VHE) - FEAT_Debugv8p2 (Debug changes for v8.2) - FEAT_Debugv8p4 (Debug changes for v8.4) - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_DoubleFault (Double Fault Extension) - FEAT_E0PD (Preventing EL0 access to halves of address maps) - FEAT_ECV (Enhanced Counter Virtualization) +- FEAT_EL0 (Support for execution at EL0) +- FEAT_EL1 (Support for execution at EL1) +- FEAT_EL2 (Support for execution at EL2) +- FEAT_EL3 (Support for execution at EL3) - FEAT_EPAC (Enhanced pointer authentication) - FEAT_ETS (Enhanced Translation Synchronization) - FEAT_EVT (Enhanced Virtualization Traps) +- FEAT_F32MM (Single-precision Matrix Multiplication) +- FEAT_F64MM (Double-precision Matrix Multiplication) - FEAT_FCMA (Floating-point complex number instructions) - FEAT_FGT (Fine-Grained Traps) - FEAT_FHM (Floating-point half-precision multiplication instructions) +- FEAT_FP (Floating Point extensions) - FEAT_FP16 (Half-precision floating-point data processing) - FEAT_FPAC (Faulting on AUT* instructions) - FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions) @@ -60,10 +82,13 @@ the following architecture extensions: - FEAT_LSE (Large System Extensions) - FEAT_LSE2 (Large System Extensions v2) - FEAT_LVA (Large Virtual Address space) +- FEAT_MixedEnd (Mixed-endian support) +- FEAT_MixdEndEL0 (Mixed-endian support at EL0) - FEAT_MOPS (Standardization of memory operations) - FEAT_MTE (Memory Tagging Extension) - FEAT_MTE2 (Memory Tagging Extension) - FEAT_MTE3 (MTE Asymmetric Fault Handling) +- FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults) - FEAT_NMI (Non-maskable Interrupt) - FEAT_NV (Nested Virtualization) - FEAT_NV2 (Enhanced nested virtualization support) @@ -76,6 +101,7 @@ the following architecture extensions: - FEAT_PAuth (Pointer authentication) - FEAT_PAuth2 (Enhancements to pointer authentication) - FEAT_PMULL (PMULL, PMULL2 instructions) +- FEAT_PMUv3 (PMU extension version 3) - FEAT_PMUv3p1 (PMU Extensions v3.1) - FEAT_PMUv3p4 (PMU Extensions v3.4) - FEAT_PMUv3p5 (PMU Extensions v3.5) @@ -97,8 +123,18 @@ the following architecture extensions: - FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode) - FEAT_SME_F64F64 (Double-precision floating-point outer product instructions) - FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions) +- FEAT_SVE (Scalable Vector Extension) +- FEAT_SVE_AES (Scalable Vector AES instructions) +- FEAT_SVE_BitPerm (Scalable Vector Bit Permutes instructions) +- FEAT_SVE_PMULL128 (Scalable Vector PMULL instructions) +- FEAT_SVE_SHA3 (Scalable Vector SHA3 instructions) +- FEAT_SVE_SM4 (Scalable Vector SM4 instructions) +- FEAT_SVE2 (Scalable Vector Extension version 2) - FEAT_SPECRES (Speculation restriction instructions) - FEAT_SSBS (Speculative Store Bypass Safe) +- FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1) +- FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1) +- FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1) - FEAT_TIDCP1 (EL0 use of IMPLEMENTATION DEFINED functionality) - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain) - FEAT_TLBIRANGE (TLB invalidate range instructions) @@ -109,8 +145,6 @@ the following architecture extensions: - FEAT_VHE (Virtualization Host Extensions) - FEAT_VMID16 (16-bit VMID) - FEAT_XNX (Translation table stage 2 Unprivileged Execute-never) -- SVE (The Scalable Vector Extension) -- SVE2 (The Scalable Vector Extension v2) For information on the specifics of these extensions, please refer to the `Armv8-A Arm Architecture Reference Manual From patchwork Tue Apr 30 16:48:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 793346 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp366542wrf; Tue, 30 Apr 2024 09:51:14 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXL7Peuj5qRtHyQAxes2FREZc80xdm6cjw6aOL1vYJXmBb3sqS2PudHGhSN3BzuLJVJDM7GU0/LrSxh61eymFXB X-Google-Smtp-Source: AGHT+IG/j3r3lPW3v/lJVgf1Y0Ga71GA0SrWFtkaXBFqbHndQBJRYgNfwS4Zn+siovyIN4u01T1O X-Received: by 2002:ac8:5a51:0:b0:439:d0c6:6165 with SMTP id o17-20020ac85a51000000b00439d0c66165mr3936300qta.32.1714495873948; Tue, 30 Apr 2024 09:51:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714495873; cv=none; d=google.com; s=arc-20160816; b=YFB7zq2q2MqNjLLrQiMQJJ88MOhXqNuAsksrQaVzHKG0893m85zYeJhqQolBU0D6Nr OkdVBGTXO0Qz8WxUxNAe98QGYL+JpTFimzTC/4sx8/L0uGzGUGPe/COB1UF7PXBorDRi cteIWLOh6c/ej145/fJ7dAvwOuBsnV8G8s7rrvm6ja7Rw8nzA4jgGgcwXPR7+0rJxvNB IRKEy7I6+rp88dgn6M5PwrV1XVi4QM3vwvymMI6FPq0H4NnUDYd/YJBym7SH2++mPM3p MGnsBvbM8NW5JnYWpQwF4mKgRM+7op4GzoyD3qyp3qSrk9BN8kJ6VxbIzHZe6YvZAI3R OFyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OMxck9KpF+SFTheDcuOfZ7ikJRZmZ4fmmOkZUV1rQxg=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=wvoFWz5JWd+8LP/eLkPvGRfrEcOfJEQ6MLMsA7/wqt/AvfySBjO6v5oY6Cs7a/JUMM wEOoh+K1Gdjq1l+cyfpcNzHfYS48ZYTjUgnTaEOin9XIdlpmEuxpvBvgM0gtZqyTzNkE jaqco03mS2HulcZ4aNDVMai324Vo54sD8Io7RXVJB7OsRSd0iOAAzHNY5sXDvVh/PigS vNlrsZwNVBNtZskfRzUZj6FUKTZSzwjnI1nellvamMpZK0anzwztVpAgVZx5CjvR3x0d Nt7eCSs2JGGIylA5zXaEKn2ZENiAFUVEaWhHGYuinGrFSdQVA2yqu/P0UW/++kwhfib1 xsDw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BJORqfn4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/21] target/arm: Enable FEAT_CSV2_3 for -cpu max Date: Tue, 30 Apr 2024 17:48:26 +0100 Message-Id: <20240430164842.4074734-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org FEAT_CSV2_3 adds a mechanism to identify if hardware cannot disclose information about whether branch targets and branch history trained in one hardware described context can control speculative execution in a different hardware context. There is no branch prediction in TCG, so we don't need to do anything to be compliant with this. Upadte the '-cpu max' ID registers to advertise the feature. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240418152004.2106516-3-peter.maydell@linaro.org --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 5fdc64a944f..d70b66f7530 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -32,6 +32,7 @@ the following architecture extensions: - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) - FEAT_CSV2_2 (Cache speculation variant 2, version 2) +- FEAT_CSV2_3 (Cache speculation variant 2, version 3) - FEAT_CSV3 (Cache speculation variant 3) - FEAT_DGH (Data gathering hint) - FEAT_DIT (Data Independent Timing instructions) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 62c4663512b..8ad05c53e8d 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1159,7 +1159,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ - t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ + t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* FEAT_CSV2_3 */ t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ cpu->isar.id_aa64pfr0 = t; @@ -1174,7 +1174,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */ t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ - t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ + t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */ t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */ cpu->isar.id_aa64pfr1 = t; From patchwork Tue Apr 30 16:48:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 793334 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp365580wrf; Tue, 30 Apr 2024 09:49:17 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUus3tpAqxsGaq9uqtWLEzYphcKIRbeOO5NOb2NuPbdHmT9h9vNjONmyu1UUN4jifyU+tL8dXno68SeMNqYI1DU X-Google-Smtp-Source: AGHT+IHjb2ZvyF7FqylNqt22/iiiQchvTf0ta/cMgySe7SxKU5XbuCTUeVekWl2eKxq4DFG4H1PU X-Received: by 2002:a05:620a:450d:b0:78d:6c05:b498 with SMTP id t13-20020a05620a450d00b0078d6c05b498mr4101427qkp.14.1714495757366; Tue, 30 Apr 2024 09:49:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714495757; cv=none; d=google.com; s=arc-20160816; b=y0sVE1IA3Q5E1UVXM+ZqJsc0a2CfabgMAGTQzCeTnOjr0wiuRcs7Z5kdJFhJeLio0X bj1sjQnTYaQZbsN3hyvf3h8+2hbootNUzJF0iuymZbn0R59rwxQwiGoOSAJgvQRl3c7C wuxNounQi5rjAWgxjXBQpT2aSU3rtpj5xTdZ3Fu3+xmFEvc3nk4BjH1XGFPhbkwq8giG QntolDqKMTK3m4O3GCO75WjxwBM5sQHJKfJ7tX1YqsODHxZ62JoQSFK+52ToudtHc/Rd LvsOwV57+wvRIVn9rJ/3KDINtvNXGfFQbFD5rx8/uFUO/7bo6O0ZB1DwG/KGf5XNLaS7 fdLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=c6JJbqohxseNO79U2Bdi9j1VL8AGsp3zzZqnjvDFGr0=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=mupnGKllUkaJiYFh/1a/kCydivomJjoisnSlCy5on+e+ebgVp8nRuV2xEvKBXLmPs4 Hno5lt0Kmmw5A71/hV05WsnLwUoOfyCroiNYqVgNsos5vLQ7gBjUtn9emm1N625e4Ojo KATxGyiEKD0cUxIcym0+3sL5v2N6fZpKSyTq6q3GSx7DTmPUfE+49B0ngYM6rhaQLaJG 6tetBgQ3vmSm3FCR/9Ys8U+aRhU2hmMJJyXyY+kLKwVLTP1fyXZl3xqisFx36SH2NpLc jBw9xdoNZSvd6pOhue5p+NukLUuBP6bQ4dfoZy8PomTY8el+V1M5Gv8ShQYXRwMts5B5 zu3A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y84HdGzK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/21] target/arm: Enable FEAT_ETS2 for -cpu max Date: Tue, 30 Apr 2024 17:48:27 +0100 Message-Id: <20240430164842.4074734-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org FEAT_ETS2 is a tighter set of guarantees about memory ordering involving translation table walks than the old FEAT_ETS; FEAT_ETS has been retired from the Arm ARM and the old ID_AA64MMFR1.ETS == 1 now gives no greater guarantees than ETS == 0. FEAT_ETS2 requires: * the virtual address of a load or store that appears in program order after a DSB cannot be translated until after the DSB completes (section B2.10.9) * TLB maintenance operations that only affect translations without execute permission are guaranteed complete after a DSB (R_BLDZX) * if a memory access RW2 is ordered-before memory access RW2, then RW1 is also ordered-before any translation table walk generated by RW2 that generates a Translation, Address size or Access flag fault (R_NNFPF, I_CLGHP) As with FEAT_ETS, QEMU is already compliant, because we do not reorder translation table walk memory accesses relative to other memory accesses, and we always guarantee to have finished TLB maintenance as soon as the TLB op is done. Update the documentation to list FEAT_ETS2 instead of the no-longer-existent FEAT_ETS, and update the 'max' CPU ID registers. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240418152004.2106516-4-peter.maydell@linaro.org --- docs/system/arm/emulation.rst | 2 +- target/arm/tcg/cpu32.c | 2 +- target/arm/tcg/cpu64.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index d70b66f7530..307539cff91 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -50,7 +50,7 @@ the following architecture extensions: - FEAT_EL2 (Support for execution at EL2) - FEAT_EL3 (Support for execution at EL3) - FEAT_EPAC (Enhanced pointer authentication) -- FEAT_ETS (Enhanced Translation Synchronization) +- FEAT_ETS2 (Enhanced Translation Synchronization) - FEAT_EVT (Enhanced Virtualization Traps) - FEAT_F32MM (Single-precision Matrix Multiplication) - FEAT_F64MM (Double-precision Matrix Multiplication) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index de8f2be9416..b5a60682fa6 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -67,7 +67,7 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_mmfr4 = t; t = cpu->isar.id_mmfr5; - t = FIELD_DP32(t, ID_MMFR5, ETS, 1); /* FEAT_ETS */ + t = FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ cpu->isar.id_mmfr5 = t; t = cpu->isar.id_pfr0; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 8ad05c53e8d..ebb585afd85 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1196,7 +1196,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */ t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ - t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */ + t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 2); /* FEAT_ETS2 */ t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ t = FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */ cpu->isar.id_aa64mmfr1 = t; From patchwork Tue Apr 30 16:48:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 793339 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp365829wrf; Tue, 30 Apr 2024 09:49:55 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUb69y7c3NcY8E8y+LZoBxsPcZCCEFBlqtNbVrZULh6uPKzo9RdgQ4Wq1hezRuMdzp8ktKmxpYhK07FXgDHUt4P X-Google-Smtp-Source: AGHT+IHKCGJkD8tm/t/9VydKZw4vj+3SRgYizBHiKTQVyCs9TMQ0tSjDk/np+iV1CiqFLpqRz5t3 X-Received: by 2002:a05:620a:4111:b0:790:ad98:9fb7 with SMTP id j17-20020a05620a411100b00790ad989fb7mr579379qko.25.1714495795202; Tue, 30 Apr 2024 09:49:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714495795; cv=none; d=google.com; s=arc-20160816; b=ryHqNhfful1znx+l76g4ViiYqB5eEwLlLAX8Ri2CG9eAVUYWrpEWjAT7nz6TR9VysK VrcHKA7fqlYvhpbzt9dAE8ed8L1wNZHmRMLtE11QxM+w47ssXxmaN+UaY7uenMdcdjV6 LcaezwnGnU7EB613OSWv6TnDcZvXbEtYuu2SApO8w1JgoiD4zpdPsNYumaCK1HE/5WVG 8wMMPrDjzZGX/G6P0HjxGdX+jyR28JOmAP2Afeh5RHHSaYHfgqTR3DKBtpDkixyc+R9k 4ycF4cswUsOmDtbUvQ7/BDRMiC9fSu3fCsA52hvCmynuRHhJ3nfYOyj/JQiJXEuEDdI4 bS0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EicQ/uN3TXAQIq8jK5susffL3tHL9yIq4ZmNUswR4uA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=ZJzaFlDV2fnbipAv0AWQoIadIdQGYI+dyObBhjCPR/WhMWx7IHxkcMtj4bj9483b1K ba8DkevBIx0t6m8CHQD3uoix41x7CIB5T8wpecUBN4iELR+Fd5DBMtBV+mBr/3U/BUSu kVoEIThAAk+tf1+0YpWye4Ozvd60ZoezzD3U0M2ygcTeSsKwiDfVF5k+zWLszD0MNFdV 5wSgLx+pSH5ybYkhkSFsjsKD/HfC2+sY882jx2RVKq/HixcIxdx0ZIpwByC6U5pwwNKy 78cxgOUXbxOEmm1fNK6RfxHfmwxErxspUYaNVW1U56eBhxuNGHDd5GckTAkoYUQ/9lO5 3I1w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PxeEydKl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/21] target/arm: Implement ID_AA64MMFR3_EL1 Date: Tue, 30 Apr 2024 17:48:28 +0100 Message-Id: <20240430164842.4074734-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Newer versions of the Arm ARM (e.g. rev K.a) now define fields for ID_AA64MMFR3_EL1. Implement this register, so that we can set the fields if we need to. There's no behaviour change here since we don't currently set the register value to non-zero. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240418152004.2106516-5-peter.maydell@linaro.org --- target/arm/cpu.h | 17 +++++++++++++++++ target/arm/helper.c | 6 ++++-- target/arm/hvf/hvf.c | 2 ++ target/arm/kvm.c | 2 ++ 4 files changed, 25 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 17efc5d565a..1f90590f937 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1011,6 +1011,7 @@ struct ArchCPU { uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; uint64_t id_aa64mmfr2; + uint64_t id_aa64mmfr3; uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; uint64_t id_aa64zfr0; @@ -2206,6 +2207,22 @@ FIELD(ID_AA64MMFR2, BBM, 52, 4) FIELD(ID_AA64MMFR2, EVT, 56, 4) FIELD(ID_AA64MMFR2, E0PD, 60, 4) +FIELD(ID_AA64MMFR3, TCRX, 0, 4) +FIELD(ID_AA64MMFR3, SCTLRX, 4, 4) +FIELD(ID_AA64MMFR3, S1PIE, 8, 4) +FIELD(ID_AA64MMFR3, S2PIE, 12, 4) +FIELD(ID_AA64MMFR3, S1POE, 16, 4) +FIELD(ID_AA64MMFR3, S2POE, 20, 4) +FIELD(ID_AA64MMFR3, AIE, 24, 4) +FIELD(ID_AA64MMFR3, MEC, 28, 4) +FIELD(ID_AA64MMFR3, D128, 32, 4) +FIELD(ID_AA64MMFR3, D128_2, 36, 4) +FIELD(ID_AA64MMFR3, SNERR, 40, 4) +FIELD(ID_AA64MMFR3, ANERR, 44, 4) +FIELD(ID_AA64MMFR3, SDERR, 52, 4) +FIELD(ID_AA64MMFR3, ADERR, 56, 4) +FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) + FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) FIELD(ID_AA64DFR0, TRACEVER, 4, 4) FIELD(ID_AA64DFR0, PMUVER, 8, 4) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6b224826fbb..bb0e1baf628 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9004,11 +9004,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, .resetvalue = cpu->isar.id_aa64mmfr2 }, - { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_AA64MMFR3_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = 0 }, + .resetvalue = cpu->isar.id_aa64mmfr3 }, { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, @@ -9165,6 +9165,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .exported_bits = R_ID_AA64MMFR1_AFP_MASK }, { .name = "ID_AA64MMFR2_EL1", .exported_bits = R_ID_AA64MMFR2_AT_MASK }, + { .name = "ID_AA64MMFR3_EL1", + .exported_bits = 0 }, { .name = "ID_AA64MMFR*_EL1_RESERVED", .is_glob = true }, { .name = "ID_AA64DFR0_EL1", diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 8e942f89b35..08d0757438c 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -497,6 +497,7 @@ static struct hvf_sreg_match hvf_sreg_match[] = { #endif { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) }, { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) }, + /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) }, { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) }, @@ -855,6 +856,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, + /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ }; hv_vcpu_t fd; hv_return_t r = HV_SUCCESS; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 21ebbf3b8f8..7cf5cf31dec 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -331,6 +331,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ARM64_SYS_REG(3, 0, 0, 7, 1)); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, ARM64_SYS_REG(3, 0, 0, 7, 2)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr3, + ARM64_SYS_REG(3, 0, 0, 7, 3)); /* * Note that if AArch32 support is not present in the host, From patchwork Tue Apr 30 16:48:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 793335 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp365632wrf; Tue, 30 Apr 2024 09:49:25 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVAtsBqkzg1ZUpIpfG5GbqcWm+QeMoChnLkWsgZFn5C1JRsjiCN4hwYZgqcrSaSsZLUoV1ZlSZy2xIJ+M0SfbOI X-Google-Smtp-Source: AGHT+IFWrF5P8LYAcuq9kbJtL8YyYu6eu7wAm0VZZoAUQ2QAeFGcHnKMgtsim6BLnbGuh4sBNkDf X-Received: by 2002:a05:6214:19c5:b0:6a0:991b:cea1 with SMTP id j5-20020a05621419c500b006a0991bcea1mr18080223qvc.5.1714495764937; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/21] target/arm: Enable FEAT_Spec_FPACC for -cpu max Date: Tue, 30 Apr 2024 17:48:29 +0100 Message-Id: <20240430164842.4074734-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22e; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org FEAT_Spec_FPACC is a feature describing speculative behaviour in the event of a PAC authontication failure when FEAT_FPACCOMBINE is implemented. FEAT_Spec_FPACC means that the speculative use of pointers processed by a PAC Authentication is not materially different in terms of the impact on cached microarchitectural state (caches, TLBs, etc) between passing and failing of the PAC Authentication. QEMU doesn't do speculative execution, so we can advertise this feature. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240418152004.2106516-6-peter.maydell@linaro.org --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 307539cff91..7fcea54d8db 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -61,6 +61,7 @@ the following architecture extensions: - FEAT_FP16 (Half-precision floating-point data processing) - FEAT_FPAC (Faulting on AUT* instructions) - FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions) +- FEAT_FPACC_SPEC (Speculative behavior of combined pointer authentication instructions) - FEAT_FRINTTS (Floating-point to integer instructions) - FEAT_FlagM (Flag manipulation instructions v2) - FEAT_FlagM2 (Enhancements to flag manipulation instructions) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index ebb585afd85..443cffe3a85 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1217,6 +1217,10 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ cpu->isar.id_aa64mmfr2 = t; + t = cpu->isar.id_aa64mmfr3; + t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ + cpu->isar.id_aa64mmfr3 = t; + t = cpu->isar.id_aa64zfr0; t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ From patchwork Tue Apr 30 16:48:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 793347 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp366613wrf; Tue, 30 Apr 2024 09:51:20 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWKhy0F6pQ1vb5pvMB99pV0kzGRwnO9lEC94eCGAu8WaDVI7H4mRiWicQCOFLWkIkuv5eFsrrPE6s4sTkI8L+y1 X-Google-Smtp-Source: AGHT+IEXOdoydVIcP96bfcr9s7Xi58/7gxbyyNXn6zP1n2duylY0+l0tdU+096wFe5DEx15DfO78 X-Received: by 2002:a05:6808:2911:b0:3c8:68e5:b9af with SMTP id ev17-20020a056808291100b003c868e5b9afmr157574oib.37.1714495880401; Tue, 30 Apr 2024 09:51:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714495880; cv=none; d=google.com; s=arc-20160816; b=PoNrtzGJbg1bfwRmmPB5ZGYJUB3KBKqruUvQM5YYnKQ7YlnV2ghTXSGlndxPzxd+ee IsnoGL1RXEwln1WLlKWYik20d6fB1lJbjdbjI4cY3XCD2Em/ju/QPubMSQlWLoZrb9Vp FRDbfWojDOnXTYaeaYDUtSeP1rD5LhZrSb64K/yg9Tib5WF9L93wTZjmK9viJbWYD69t t+eI+Hj9db6SDItb7Wc0XJnnNZ/vHnxaF7K57B7pZq03ngVadDRJouwFvAXQSWx221TE XeRqzMsagLhRJ8dvk9sLXfFL44f/C2uUcN1TpOzQiVaFcpw/FuT2cTiCb8WTZOOe7+FK hDGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=etAp6WZx3h8E7CdT4MY1xTM+Yr9ybGh3o76qjoMWZ7I=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=dCWBTfANAsqyHyIwXp0GpxodS5dZ1T0En3M/wXIBtR4jFshOlwfUkiDHnK9Hw3bdnx mI9gzs7X4kzCXCp0G5BUjM+uCBRIRx907OxApTf297UAmuxL53Jg0u3bucp0uEq6v26T OEzOqmjhWggVQONlaeRJe3qupVWQwjUFfxJDvrrU+2t8llbKbGQa/WIz6D5bTVhbnh7Z K8vCfoKALzPh2WZWW8Lv0jqQ7ylI7MYEhIy9JC9vq2Ww1UVc3kzaGZncKDlRTrn77xDa B1fpoDVTeBzTvpVteCjbDZfmJioqaR81DzleRCHrLeCA4hE4J78hoSCAY3RLuAmxrk79 N3Ug==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EAn1tIRb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/21] tests/avocado: update sunxi kernel from armbian to 6.6.16 Date: Tue, 30 Apr 2024 17:48:30 +0100 Message-Id: <20240430164842.4074734-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The Linux kernel 5.10.16 binary for sunxi has been removed from apt.armbian.com. This means that the avocado tests for these machines will be skipped (status CANCEL) if the old binary isn't present in the avocado cache. Update to 6.6.16, in the same way we did in commit e384db41d8661 when we moved to 5.10.16 in 2021. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2284 Signed-off-by: Peter Maydell Reviewed-by: Strahinja Jankovic Reviewed-by: Niek Linnenbank Tested-by: Niek Linnenbank Message-id: 20240415151845.1564201-1-peter.maydell@linaro.org --- tests/avocado/boot_linux_console.py | 70 ++++++++++++++--------------- tests/avocado/replay_kernel.py | 8 ++-- 2 files changed, 39 insertions(+), 39 deletions(-) diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py index 180ac17326e..c35fc5e9ba2 100644 --- a/tests/avocado/boot_linux_console.py +++ b/tests/avocado/boot_linux_console.py @@ -646,12 +646,12 @@ def test_arm_cubieboard_initrd(self): :avocado: tags=accel:tcg """ deb_url = ('https://apt.armbian.com/pool/main/l/' - 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb') - deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0' + 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb') + deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b' deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) kernel_path = self.extract_from_deb(deb_path, - '/boot/vmlinuz-5.10.16-sunxi') - dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb' + '/boot/vmlinuz-6.6.16-current-sunxi') + dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb' dtb_path = self.extract_from_deb(deb_path, dtb_path) initrd_url = ('https://github.com/groeck/linux-build-test/raw/' '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' @@ -690,12 +690,12 @@ def test_arm_cubieboard_sata(self): :avocado: tags=accel:tcg """ deb_url = ('https://apt.armbian.com/pool/main/l/' - 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb') - deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0' + 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb') + deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b' deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) kernel_path = self.extract_from_deb(deb_path, - '/boot/vmlinuz-5.10.16-sunxi') - dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb' + '/boot/vmlinuz-6.6.16-current-sunxi') + dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb' dtb_path = self.extract_from_deb(deb_path, dtb_path) rootfs_url = ('https://github.com/groeck/linux-build-test/raw/' '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' @@ -872,13 +872,13 @@ def test_arm_bpim2u(self): :avocado: tags=machine:bpim2u :avocado: tags=accel:tcg """ - deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/' - 'linux-image-current-sunxi_21.02.2_armhf.deb') - deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0' + deb_url = ('https://apt.armbian.com/pool/main/l/' + 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb') + deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b' deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) kernel_path = self.extract_from_deb(deb_path, - '/boot/vmlinuz-5.10.16-sunxi') - dtb_path = ('/usr/lib/linux-image-current-sunxi/' + '/boot/vmlinuz-6.6.16-current-sunxi') + dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/' 'sun8i-r40-bananapi-m2-ultra.dtb') dtb_path = self.extract_from_deb(deb_path, dtb_path) @@ -899,13 +899,13 @@ def test_arm_bpim2u_initrd(self): :avocado: tags=accel:tcg :avocado: tags=machine:bpim2u """ - deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/' - 'linux-image-current-sunxi_21.02.2_armhf.deb') - deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0' + deb_url = ('https://apt.armbian.com/pool/main/l/' + 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb') + deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b' deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) kernel_path = self.extract_from_deb(deb_path, - '/boot/vmlinuz-5.10.16-sunxi') - dtb_path = ('/usr/lib/linux-image-current-sunxi/' + '/boot/vmlinuz-6.6.16-current-sunxi') + dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/' 'sun8i-r40-bananapi-m2-ultra.dtb') dtb_path = self.extract_from_deb(deb_path, dtb_path) initrd_url = ('https://github.com/groeck/linux-build-test/raw/' @@ -946,13 +946,13 @@ def test_arm_bpim2u_gmac(self): """ self.require_netdev('user') - deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/' - 'linux-image-current-sunxi_21.02.2_armhf.deb') - deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0' + deb_url = ('https://apt.armbian.com/pool/main/l/' + 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb') + deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b' deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) kernel_path = self.extract_from_deb(deb_path, - '/boot/vmlinuz-5.10.16-sunxi') - dtb_path = ('/usr/lib/linux-image-current-sunxi/' + '/boot/vmlinuz-6.6.16-current-sunxi') + dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/' 'sun8i-r40-bananapi-m2-ultra.dtb') dtb_path = self.extract_from_deb(deb_path, dtb_path) rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/' @@ -1049,12 +1049,12 @@ def test_arm_orangepi(self): :avocado: tags=accel:tcg """ deb_url = ('https://apt.armbian.com/pool/main/l/' - 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb') - deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0' + 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb') + deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b' deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) kernel_path = self.extract_from_deb(deb_path, - '/boot/vmlinuz-5.10.16-sunxi') - dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb' + '/boot/vmlinuz-6.6.16-current-sunxi') + dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb' dtb_path = self.extract_from_deb(deb_path, dtb_path) self.vm.set_console() @@ -1075,12 +1075,12 @@ def test_arm_orangepi_initrd(self): :avocado: tags=machine:orangepi-pc """ deb_url = ('https://apt.armbian.com/pool/main/l/' - 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb') - deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0' + 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb') + deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b' deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) kernel_path = self.extract_from_deb(deb_path, - '/boot/vmlinuz-5.10.16-sunxi') - dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb' + '/boot/vmlinuz-6.6.16-current-sunxi') + dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb' dtb_path = self.extract_from_deb(deb_path, dtb_path) initrd_url = ('https://github.com/groeck/linux-build-test/raw/' '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' @@ -1121,12 +1121,12 @@ def test_arm_orangepi_sd(self): self.require_netdev('user') deb_url = ('https://apt.armbian.com/pool/main/l/' - 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb') - deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0' + 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb') + deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b' deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) kernel_path = self.extract_from_deb(deb_path, - '/boot/vmlinuz-5.10.16-sunxi') - dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb' + '/boot/vmlinuz-6.6.16-current-sunxi') + dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb' dtb_path = self.extract_from_deb(deb_path, dtb_path) rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/' 'buildroot-baseline/20221116.0/armel/rootfs.ext2.xz') diff --git a/tests/avocado/replay_kernel.py b/tests/avocado/replay_kernel.py index 2c81412dbad..232d287c272 100644 --- a/tests/avocado/replay_kernel.py +++ b/tests/avocado/replay_kernel.py @@ -203,12 +203,12 @@ def test_arm_cubieboard_initrd(self): :avocado: tags=machine:cubieboard """ deb_url = ('https://apt.armbian.com/pool/main/l/' - 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb') - deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0' + 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb') + deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b' deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) kernel_path = self.extract_from_deb(deb_path, - '/boot/vmlinuz-5.10.16-sunxi') - dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb' + '/boot/vmlinuz-6.6.16-current-sunxi') + dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb' dtb_path = self.extract_from_deb(deb_path, dtb_path) initrd_url = ('https://github.com/groeck/linux-build-test/raw/' '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' From patchwork Tue Apr 30 16:48:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 793353 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp367279wrf; Tue, 30 Apr 2024 09:52:53 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWyUaJ6t4d8dL3XETBQur0oRIJTy5fCRJhxDHaY/ZxqnK/AhicJebBNrElUtL5nNtk+brm2GdvI1khinMqEUi+X X-Google-Smtp-Source: AGHT+IEUOzzmCF4eXT6rl1qh9duvC9Xb/kgOUvuZ7Nm3TGIjeOYlPWzSgVnPOaoifD8Z33MWA+xE X-Received: by 2002:a05:6214:2626:b0:6a0:cafc:aaa with SMTP id gv6-20020a056214262600b006a0cafc0aaamr9358935qvb.20.1714495973597; Tue, 30 Apr 2024 09:52:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714495973; cv=none; d=google.com; s=arc-20160816; b=Ai1rfB/0T0dG4kf769EI8pupKkwWta8KtOCM1GXhq1T/otD1afDqjtUgOGuL7QL4Ep x9Bqtr5amba/6vscsj/ERBCnzV8K8egCcjbCr0PwVR+pqWFftKeb0SssTo9D/sjUffUP CP3dVVhg13YAfxY0ykM0/M2x/96Id1WoHMKXsqzr+aAmCv+neaK8+k3WjvOHow2jbgyY 1dOVEp8Ai6gsn1FRlbYH0uT5h5aT0EEO/z2NZB1B34FYa0vwO37lr0ICJsM/L/ryQxLo 5yUk2sZnyKta+qLaS2atTcxo3l4oBJp+cX4HaCnUu++VY3kKL6ds709QrLoSVw6v3s/Y +Osw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8ybX+f9OWY45lhLb2oST3kDQoeWzOe+ZNsl1K+EOruA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=fBqNlrQLJ4WmgIW8VR2K5JhAjgbF40zpw9kYp0dFNbmpyZIeMGsVIzEXM/xF125iky 5ZFQWytSbreH5dX5pKkc4eFyhq5ZeM7s79FvnKAID71zeC5j5bTFLsbtypuB/PN8U+xD GYtb7/49aZc7YaLW1/5c824ydSqoJQgsxH5qbpASYFgL2p4SjAc9HM/GKrLzSqWrdnw5 arQ+ENNTITyXIHkbqjWS5MYuMKW2ByqYyvA2z6QqX7SMDqFk5VyuTrTD2HaGRmeLQzj9 z63E+U+E42mUMoJxr8Oi2qOzRN+KjuU26CDMCT1v8LaZ++uW4sbMUKOVyiIeagIzqOSr altg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JFzQgNhA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/21] target/arm: Refactor default generic timer frequency handling Date: Tue, 30 Apr 2024 17:48:31 +0100 Message-Id: <20240430164842.4074734-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22f; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The generic timer frequency is settable by board code via a QOM property "cntfrq", but otherwise defaults to 62.5MHz. The way this is done includes some complication resulting from how this was originally a fixed value with no QOM property. Clean it up: * always set cpu->gt_cntfrq_hz to some sensible value, whether the CPU has the generic timer or not, and whether it's system or user-only emulation * this means we can always use gt_cntfrq_hz, and never need the old GTIMER_SCALE define * set the default value in exactly one place, in the realize fn The aim here is to pave the way for handling the ARMv8.6 requirement that the generic timer frequency is always 1GHz. We're going to do that by having old CPU types keep their legacy-in-QEMU behaviour and having the default for any new CPU types be a 1GHz rather han 62.5MHz cntfrq, so we want the point where the default is decided to be in one place, and in code, not in a DEFINE_PROP_UINT64() initializer. This commit should have no behavioural changes. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240426122913.3427983-2-peter.maydell@linaro.org --- target/arm/internals.h | 7 ++++--- target/arm/cpu.c | 31 +++++++++++++++++-------------- target/arm/helper.c | 16 ++++++++-------- 3 files changed, 29 insertions(+), 25 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index e40ec453d56..b6c78db0243 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -60,10 +60,11 @@ static inline bool excp_is_internal(int excp) || excp == EXCP_SEMIHOST; } -/* Scale factor for generic timers, ie number of ns per tick. - * This gives a 62.5MHz timer. +/* + * Default frequency for the generic timer, in Hz. + * This is 62.5MHz, which gives a 16 ns tick period. */ -#define GTIMER_SCALE 16 +#define GTIMER_DEFAULT_HZ 62500000 /* Bit definitions for the v7M CONTROL register */ FIELD(V7M_CONTROL, NPRIV, 0, 1) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a152def2413..9f2ca6633a1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1506,9 +1506,12 @@ static void arm_cpu_initfn(Object *obj) } } +/* + * 0 means "unset, use the default value". That default might vary depending + * on the CPU type, and is set in the realize fn. + */ static Property arm_cpu_gt_cntfrq_property = - DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, - NANOSECONDS_PER_SECOND / GTIMER_SCALE); + DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0); static Property arm_cpu_reset_cbar_property = DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); @@ -1954,6 +1957,17 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) return; } + if (!cpu->gt_cntfrq_hz) { + /* + * 0 means "the board didn't set a value, use the default". + * The default value of the generic timer frequency (as seen in + * CNTFRQ_EL0) is 62.5MHz, which corresponds to a period of 16ns. + * This is what you get (a) for a CONFIG_USER_ONLY CPU (b) if the + * board doesn't set it. + */ + cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ; + } + #ifndef CONFIG_USER_ONLY /* The NVIC and M-profile CPU are two halves of a single piece of * hardware; trying to use one without the other is a command line @@ -2002,18 +2016,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) } { - uint64_t scale; - - if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { - if (!cpu->gt_cntfrq_hz) { - error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", - cpu->gt_cntfrq_hz); - return; - } - scale = gt_cntfrq_period_ns(cpu); - } else { - scale = GTIMER_SCALE; - } + uint64_t scale = gt_cntfrq_period_ns(cpu); cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, arm_gt_ptimer_cb, cpu); diff --git a/target/arm/helper.c b/target/arm/helper.c index bb0e1baf628..75876359608 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2474,6 +2474,13 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = { .resetvalue = 0 }, }; +static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque) +{ + ARMCPU *cpu = env_archcpu(env); + + cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz; +} + #ifndef CONFIG_USER_ONLY static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3228,13 +3235,6 @@ void arm_gt_hvtimer_cb(void *opaque) gt_recalc_timer(cpu, GTIMER_HYPVIRT); } -static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque) -{ - ARMCPU *cpu = env_archcpu(env); - - cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz; -} - static const ARMCPRegInfo generic_timer_cp_reginfo[] = { /* * Note that CNTFRQ is purely reads-as-written for the benefit @@ -3514,7 +3514,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */, .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), - .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE, + .resetfn = arm_gt_cntfrq_reset, }, { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, From patchwork Tue Apr 30 16:48:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 793352 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp367269wrf; Tue, 30 Apr 2024 09:52:52 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXyJc2ZUsnZFfan7zMo4nSFpQuoLLIqD4TMASDXnxhxANAdPuHpMfHv7AMyG4spli/VnUwXgXccANQueEakKLYv X-Google-Smtp-Source: AGHT+IF9tnZlHkUfZ90j9XBRPVNt2h6B6kE0XEEDI4csXwBDEIB6lUVV2jH98Jcl3LcAJU0khG6n X-Received: by 2002:a05:690c:884:b0:610:e9b2:f84a with SMTP id cd4-20020a05690c088400b00610e9b2f84amr145110ywb.26.1714495972226; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/21] hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz Date: Tue, 30 Apr 2024 17:48:32 +0100 Message-Id: <20240430164842.4074734-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently QEMU CPUs always run with a generic timer counter frequency of 62.5MHz, but ARMv8.6 CPUs will run at 1GHz. For older versions of the TF-A firmware that sbsa-ref runs, the frequency of the generic timer is hardcoded into the firmware, and so if the CPU actually has a different frequency then timers in the guest will be set incorrectly. The default frequency used by the 'max' CPU is about to change, so make the sbsa-ref board force the CPU frequency to the value which the firmware expects. Newer versions of TF-A will read the frequency from the CPU's CNTFRQ_EL0 register: https://github.com/ARM-software/arm-trusted-firmware/commit/4c77fac98dac0bebc63798aae9101ac865b87148 so in the longer term we could make this board use the 1GHz frequency. We will need to make sure we update the binaries used by our avocado test Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef before we can do that. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Marcin Juszkiewicz Message-id: 20240426122913.3427983-3-peter.maydell@linaro.org --- hw/arm/sbsa-ref.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index f5709d6c141..36f6f717b4b 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -60,6 +60,19 @@ #define NUM_SMMU_IRQS 4 #define NUM_SATA_PORTS 6 +/* + * Generic timer frequency in Hz (which drives both the CPU generic timers + * and the SBSA watchdog-timer). Older versions of the TF-A firmware + * typically used with sbsa-ref (including the binaries in our Avocado test + * Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef + * assume it is this value. + * + * TODO: this value is not architecturally correct for an Armv8.6 or + * better CPU, so we should move to 1GHz once the TF-A fix above has + * made it into a release and into our Avocado test. + */ +#define SBSA_GTIMER_HZ 62500000 + enum { SBSA_FLASH, SBSA_MEM, @@ -767,6 +780,8 @@ static void sbsa_ref_init(MachineState *machine) &error_abort); } + object_property_set_int(cpuobj, "cntfrq", SBSA_GTIMER_HZ, &error_abort); + object_property_set_link(cpuobj, "memory", OBJECT(sysmem), &error_abort); From patchwork Tue Apr 30 16:48:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 793355 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp367532wrf; Tue, 30 Apr 2024 09:53:34 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVhPILPz3aNPJ86l0DIFAlQpSoVZfbqxCTzxYj41Yb808tcojgKUxZL1SfHPTcO15azmhQnqN9nUeYse4iY9AqT X-Google-Smtp-Source: AGHT+IFP0X72+YEgP8TAufUUx90WW/llbAMBwOm4sPunWAkDzMmnu9/c9LzBdk3+XyFt48EFMtLo X-Received: by 2002:a05:6214:1c88:b0:69b:2897:4fc4 with SMTP id ib8-20020a0562141c8800b0069b28974fc4mr18090000qvb.58.1714496013891; Tue, 30 Apr 2024 09:53:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714496013; cv=none; d=google.com; s=arc-20160816; b=kLf4lFXzrmVBXaEqzzFVp7Ym2B9qy7K462y0uqa2HnXD0flo7pD8gklSkWifoL9fEa iIt3KIdd48eLajsRkyLyWBTAE3vTItxvXuTSiuO1BwO/g8PPS5URVhz/R75CWv+UNei9 cNBeMBRnQUEUVQk/3GPH9lQ4tyUbAn/lo1u/l4I7T+nWVdRLK8v0wCwCHgUY29Zz4XYF aFxdKlK6Sj1lL1MSD4bTpIZ36MgSVIm4RTMJIAvRdpE9lUv0HIlahWJyc/guKyUoEDU+ ttC12+wytQ7Cb9GZvKStteLuqNsvAobP9txQcKs8WFGSbSjqzWm+l0UN21ayFpeS+1jO pfug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xqt2LCRNbcncy6L7VTlxADhxm7D7waQ58ubzhGIRJc4=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=KvztVLRzFKE1PLnUc8la3TfX9RiLaT+V/vNuBiwHpDgCqddnktmKgVit9e5HdxCvMX ++Wvz2nBO3MSrlIzBVuWAfYW80dFvI+eqae4Baajuc194Y6Ml8uBeAmoMXS2bRhncC08 mKG4BeeQVBkD1StUm4mB1mbOaO5U/KXPCHHhrJOl9W+RxivsXR9jS0IH1SbUPjKAmbq5 RSJPi7B9uXKEmcRdG9UVyw8lMfKJFnOsqciIzCVZKr+rIBkqIcaG6py2ic44+9MGXcUn oTZ7q5FCGs5uiJpJ3DscT2TLeDwpF0+kCyv01njNyrdE1PZ/gNo2qXFrGJwNoh2bJP+2 MynQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G3kAiy+H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/21] hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property Date: Tue, 30 Apr 2024 17:48:33 +0100 Message-Id: <20240430164842.4074734-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently the sbsa_gdwt watchdog device hardcodes its frequency at 62.5MHz. In real hardware, this watchdog is supposed to be driven from the system counter, which also drives the CPU generic timers. Newer CPU types (in particular from Armv8.6) should have a CPU generic timer frequency of 1GHz, so we can't leave the watchdog on the old QEMU default of 62.5GHz. Make the frequency a QOM property so it can be set by the board, and have our only board that uses this device set that frequency to the same value it sets the CPU frequency. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240426122913.3427983-4-peter.maydell@linaro.org --- include/hw/watchdog/sbsa_gwdt.h | 3 +-- hw/arm/sbsa-ref.c | 1 + hw/watchdog/sbsa_gwdt.c | 15 ++++++++++++++- 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/include/hw/watchdog/sbsa_gwdt.h b/include/hw/watchdog/sbsa_gwdt.h index 70b137de301..4bdc6c6fdb6 100644 --- a/include/hw/watchdog/sbsa_gwdt.h +++ b/include/hw/watchdog/sbsa_gwdt.h @@ -55,8 +55,6 @@ #define SBSA_GWDT_RMMIO_SIZE 0x1000 #define SBSA_GWDT_CMMIO_SIZE 0x1000 -#define SBSA_TIMER_FREQ 62500000 /* Hz */ - typedef struct SBSA_GWDTState { /* */ SysBusDevice parent_obj; @@ -67,6 +65,7 @@ typedef struct SBSA_GWDTState { qemu_irq irq; QEMUTimer *timer; + uint64_t freq; uint32_t id; uint32_t wcs; diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 36f6f717b4b..57c337fd92a 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -543,6 +543,7 @@ static void create_wdt(const SBSAMachineState *sms) SysBusDevice *s = SYS_BUS_DEVICE(dev); int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0]; + qdev_prop_set_uint64(dev, "clock-frequency", SBSA_GTIMER_HZ); sysbus_realize_and_unref(s, &error_fatal); sysbus_mmio_map(s, 0, rbase); sysbus_mmio_map(s, 1, cbase); diff --git a/hw/watchdog/sbsa_gwdt.c b/hw/watchdog/sbsa_gwdt.c index 96895d76369..d437535cc66 100644 --- a/hw/watchdog/sbsa_gwdt.c +++ b/hw/watchdog/sbsa_gwdt.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "sysemu/reset.h" #include "sysemu/watchdog.h" +#include "hw/qdev-properties.h" #include "hw/watchdog/sbsa_gwdt.h" #include "qemu/timer.h" #include "migration/vmstate.h" @@ -109,7 +110,7 @@ static void sbsa_gwdt_update_timer(SBSA_GWDTState *s, WdtRefreshType rtype) timeout = s->woru; timeout <<= 32; timeout |= s->worl; - timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, SBSA_TIMER_FREQ); + timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, s->freq); timeout += qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); if ((rtype == EXPLICIT_REFRESH) || ((rtype == TIMEOUT_REFRESH) && @@ -261,6 +262,17 @@ static void wdt_sbsa_gwdt_realize(DeviceState *dev, Error **errp) dev); } +static Property wdt_sbsa_gwdt_props[] = { + /* + * Timer frequency in Hz. This must match the frequency used by + * the CPU's generic timer. Default 62.5Hz matches QEMU's legacy + * CPU timer frequency default. + */ + DEFINE_PROP_UINT64("clock-frequency", struct SBSA_GWDTState, freq, + 62500000), + DEFINE_PROP_END_OF_LIST(), +}; + static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -271,6 +283,7 @@ static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data) set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories); dc->vmsd = &vmstate_sbsa_gwdt; dc->desc = "SBSA-compliant generic watchdog device"; + device_class_set_props(dc, wdt_sbsa_gwdt_props); } static const TypeInfo wdt_sbsa_gwdt_info = { From patchwork Tue Apr 30 16:48:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 793350 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp366944wrf; Tue, 30 Apr 2024 09:52:01 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXEP2v9oc53jkQlGEZrQJZRBw6DQM3MalDxXjtIzw326fj204k6ZzSpI6em+r67wsOrczFiXJhm6y0HILBn5igq X-Google-Smtp-Source: AGHT+IHNJkIcXUFdBJGQLEOrj38tFxSOw2wg6jjEhDvmTNTjbsNKk+iMb+W1ba/kKHqtaW/elepv X-Received: by 2002:a05:620a:12c4:b0:790:f905:3c4b with SMTP id e4-20020a05620a12c400b00790f9053c4bmr6703081qkl.57.1714495921351; Tue, 30 Apr 2024 09:52:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714495921; cv=none; d=google.com; s=arc-20160816; b=Q0M06pyQYZcH3OqCs6pTdSFlX8Ux/NAvrNIV4vDkCGjRFbe2N7EjWOFSP5FMy6YTG1 OBRPbcRf5KsMej3qxsBLW90YcEK5m2UizyyZfoQMDDfviYps4qkGnKXkvFzsy6ZNlSC6 kAvVC2yNZmSwQdHvBrq5FBqE4+2AioYwmurq0FOCBXGKuPJb4yIJveZIwRwaF0gEROiN 0/+6XYgICIaglJDMMEaheZ7FHMiEMUvSPi3io3df2FQs/KPKp7y/6cf95/TYaNHr4OoM hoYw1Ll76VKonwUlGhsTS/ISzfA1a0SPxViQW742Q6t8itzK/Xg6st2eeKYd5Ja5Gmn3 UEwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZRx6TDLUMLghtjN21VBOwZjWZpZDFLSrLQHG0HuKw1o=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=ZWwuh+jM0rBlCsZnB9pghQsKLYXYQ0FkPE7GUJdfDHT6zQr4SoGywofSghOolsIjy7 +q0t1Hx9WvtAL7YIOd6Y+VGMF4Okg6sFdVIter0H26QJu9sRfQrYs0f2dX1X8fxcrfTv YBrTljB0F5crpqLvhM4PZCDRBhj2Vl8wLXogD95u1OfYYADUzJ0sYcJbgv7C+1hipHES /kgEKH12xFnwhq4XtukzSFthQannw9Xpsz8L6il9nEs+X60HxTkUj3KOM2tIAyAPGfxk 4CakWZ2VTxx4/lSTANGAGm2bJg0yIr3ikMG2I4F2/Wg6hvyvPuz9f5doUwcbPZSI7pmF 6NAA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="WaRW0/qs"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/21] target/arm: Default to 1GHz cntfrq for 'max' and new CPUs Date: Tue, 30 Apr 2024 17:48:34 +0100 Message-Id: <20240430164842.4074734-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In previous versions of the Arm architecture, the frequency of the generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value, and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns. In Armv8.6, the architecture standardized this frequency to 1GHz. Because there is no ID register feature field that indicates whether a CPU is v8.6 or that it ought to have this counter frequency, we implement this by changing our default CNTFRQ value for all CPUs, with exceptions for backwards compatibility: * CPU types which we already implement will retain the old default value. None of these are v8.6 CPUs, so this is architecturally OK. * CPUs used in versioned machine types with a version of 9.0 or earlier will retain the old default value. The upshot is that the only CPU type that changes is 'max'; but any new type we add in future (whether v8.6 or not) will also get the new 1GHz default. It remains the case that the machine model can override the default value via the 'cntfrq' QOM property (regardless of the CPU type). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240426122913.3427983-5-peter.maydell@linaro.org --- target/arm/cpu.h | 11 +++++++++++ target/arm/internals.h | 12 ++++++++++-- hw/core/machine.c | 4 +++- target/arm/cpu.c | 23 +++++++++++++++++------ target/arm/cpu64.c | 2 ++ target/arm/tcg/cpu32.c | 4 ++++ target/arm/tcg/cpu64.c | 18 ++++++++++++++++++ 7 files changed, 65 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1f90590f937..a550bcd25fe 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -956,6 +956,9 @@ struct ArchCPU { */ bool host_cpu_probe_failed; + /* QOM property to indicate we should use the back-compat CNTFRQ default */ + bool backcompat_cntfrq; + /* Specify the number of cores in this CPU cluster. Used for the L2CTLR * register. */ @@ -2373,6 +2376,14 @@ enum arm_features { ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ + /* + * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz + * if the board doesn't set a value, instead of 1GHz. It is for backwards + * compatibility and used only with CPU definitions that were already + * in QEMU before we changed the default. It should not be set on any + * CPU types added in future. + */ + ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/internals.h b/target/arm/internals.h index b6c78db0243..ee3ebd383e1 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -62,9 +62,17 @@ static inline bool excp_is_internal(int excp) /* * Default frequency for the generic timer, in Hz. - * This is 62.5MHz, which gives a 16 ns tick period. + * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before + * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz, + * which gives a 16ns tick period. + * + * We will use the back-compat value: + * - for QEMU CPU types added before we standardized on 1GHz + * - for versioned machine types with a version of 9.0 or earlier + * In any case, the machine model may override via the cntfrq property. */ -#define GTIMER_DEFAULT_HZ 62500000 +#define GTIMER_DEFAULT_HZ 1000000000 +#define GTIMER_BACKCOMPAT_HZ 62500000 /* Bit definitions for the v7M CONTROL register */ FIELD(V7M_CONTROL, NPRIV, 0, 1) diff --git a/hw/core/machine.c b/hw/core/machine.c index 0dec48e8021..4ff60911e74 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -33,7 +33,9 @@ #include "hw/virtio/virtio-iommu.h" #include "audio/audio.h" -GlobalProperty hw_compat_9_0[] = {}; +GlobalProperty hw_compat_9_0[] = { + {"arm-cpu", "backcompat-cntfrq", "true" }, +}; const size_t hw_compat_9_0_len = G_N_ELEMENTS(hw_compat_9_0); GlobalProperty hw_compat_8_2[] = { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9f2ca6633a1..fdc3eda318a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1959,13 +1959,22 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (!cpu->gt_cntfrq_hz) { /* - * 0 means "the board didn't set a value, use the default". - * The default value of the generic timer frequency (as seen in - * CNTFRQ_EL0) is 62.5MHz, which corresponds to a period of 16ns. - * This is what you get (a) for a CONFIG_USER_ONLY CPU (b) if the - * board doesn't set it. + * 0 means "the board didn't set a value, use the default". (We also + * get here for the CONFIG_USER_ONLY case.) + * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before + * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz, + * which gives a 16ns tick period. + * + * We will use the back-compat value: + * - for QEMU CPU types added before we standardized on 1GHz + * - for versioned machine types with a version of 9.0 or earlier */ - cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ; + if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) || + cpu->backcompat_cntfrq) { + cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ; + } else { + cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ; + } } #ifndef CONFIG_USER_ONLY @@ -2574,6 +2583,8 @@ static Property arm_cpu_properties[] = { mp_affinity, ARM64_AFFINITY_INVALID), DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), + /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */ + DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false), DEFINE_PROP_END_OF_LIST() }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 985b1efe160..c15d086049f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -599,6 +599,7 @@ static void aarch64_a57_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_EL2); @@ -656,6 +657,7 @@ static void aarch64_a53_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_EL2); diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index b5a60682fa6..bdd82d912a2 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -457,6 +457,7 @@ static void cortex_a7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_EL2); @@ -505,6 +506,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_EL2); @@ -696,6 +698,7 @@ static void cortex_r52_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_PMSA); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_AUXCR); cpu->midr = 0x411fd133; /* r1p3 */ @@ -924,6 +927,7 @@ static void arm_max_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 443cffe3a85..da41a44f75b 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -63,6 +63,7 @@ static void aarch64_a35_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_EL2); @@ -231,6 +232,7 @@ static void aarch64_a55_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_EL2); @@ -299,6 +301,7 @@ static void aarch64_a72_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_EL2); @@ -354,6 +357,7 @@ static void aarch64_a76_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_EL2); @@ -423,6 +427,7 @@ static void aarch64_a64fx_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); @@ -592,6 +597,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_EL2); @@ -663,6 +669,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_EL2); @@ -885,6 +892,7 @@ static void aarch64_a710_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_EL2); @@ -982,6 +990,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); set_feature(&cpu->env, ARM_FEATURE_AARCH64); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_EL2); @@ -1077,6 +1086,15 @@ void aarch64_max_tcg_initfn(Object *obj) uint64_t t; uint32_t u; + /* + * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default + * to because we started with aarch64_a57_initfn(). A 'max' CPU might + * be a v8.6-or-later one, in which case the cntfrq must be 1GHz; and + * because it is our "may change" CPU type we are OK with it not being + * backwards-compatible with how it worked in old QEMU. + */ + unset_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); + /* * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real * one and try to apply errata workarounds or use impdef features we From patchwork Tue Apr 30 16:48:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 793337 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp365640wrf; Tue, 30 Apr 2024 09:49:26 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW1ccbv+ZqgNbA1MxMP96M/3+viIPQ2ioPQtthPcXovsgJud81l9zPETNNbRqO3tD65EPac1KcwvXP2PsIlSiuP X-Google-Smtp-Source: AGHT+IEk1Upn7JO0p+R+XCe9GtWX3PKNGeH++k+jDWW1zSW8pBokQNrnPjvlhr4aq+IMsX+iqTul X-Received: by 2002:ac8:5996:0:b0:43a:a4e9:6ca8 with SMTP id e22-20020ac85996000000b0043aa4e96ca8mr12430974qte.60.1714495765981; Tue, 30 Apr 2024 09:49:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714495765; cv=none; d=google.com; s=arc-20160816; b=Ex0tnPH8F0xKoSUSjtsdhYfiiOptH0EvYwD+KKFlCEwLRMADpyUNfYKnEyW8ywOByM qLrbpySo135y7C+xjairjQ/McTpEL9oDjwJz+KRjQmveBDRUnqgMN4BHLXpH5wbv0Jvf 7IxRy5J0acqfU0tCmo1F2BED3ZJ6qAH/niQ3Ky/Sd76DoK0g74Ig/TglsCHWcKpXfxvs YEAXJ8OZER6k2gW+G5h/43/R6IfmX10MTMDhFQ90G6uyc62eiklUhaPpGkwsnQfAnuUI Q8eUj7RTEIJm1q9okOHxwte9E1YW3rtVmqvNEjui2L98QJm4kF+vXhcbvqaZbKdGr1SJ wXFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jqDoG7XrOPhSpsms6wDOW1hCXTqugMMNRvD8wRtJzzA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=yak6lXF9QG9RvmrfF3muslrCOsO12z19GIxj3BXImPrzSmoQuU5gcXxpxHdvaiyrIt iAQhdNQ+70sqoCBkSDENzJa7ERZSAa1Scwux0qdbyPNhDpkJTYk6qMGzkdyDTBbmYU3E os259DKjgrJolMj2bO4o3PX4e2TAd/e+GrP/r0tzVPgVyhOhiwnD+D9Z53sXiKSp0XyS kjM3muOU05PWz3W4rAxMCQ0l453Br6Hzs77r1MLMDdL4T8fgOEYtKYrL5tsUWDa+HVaw C6xuuC6+KFCIoPn6Zw+FlyFiJl5fhIiWfCZ8vgkyWisFcqKHkkSFxNxlPi8CLD346IuH AiNw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GuRtOwTR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/21] hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields Date: Tue, 30 Apr 2024 17:48:35 +0100 Message-Id: <20240430164842.4074734-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Alexandra Diupina The DMA descriptor structures for this device have a set of "address extension" fields which extend the 32 bit source addresses with an extra 16 bits to give a 48 bit address: https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/ADDR_EXT-Field However, we misimplemented this address extension in several ways: * we only extracted 12 bits of the extension fields, not 16 * we didn't shift the extension field up far enough * we accidentally did the shift as 32-bit arithmetic, which meant that we would have an overflow instead of setting bits [47:32] of the resulting 64-bit address Add a type cast and use extract64() instead of extract32() to avoid integer overflow on addition. Fix bit fields extraction according to documentation. Found by Linux Verification Center (linuxtesting.org) with SVACE. Cc: qemu-stable@nongnu.org Fixes: d3c6369a96 ("introduce xlnx-dpdma") Signed-off-by: Alexandra Diupina Message-id: 20240428181131.23801-1-adiupina@astralinux.ru [PMM: adjusted commit message] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/dma/xlnx_dpdma.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/dma/xlnx_dpdma.c b/hw/dma/xlnx_dpdma.c index 1f5cd64ed10..530717d1885 100644 --- a/hw/dma/xlnx_dpdma.c +++ b/hw/dma/xlnx_dpdma.c @@ -175,24 +175,24 @@ static uint64_t xlnx_dpdma_desc_get_source_address(DPDMADescriptor *desc, switch (frag) { case 0: - addr = desc->source_address - + (extract32(desc->address_extension, 16, 12) << 20); + addr = (uint64_t)desc->source_address + + (extract64(desc->address_extension, 16, 16) << 32); break; case 1: - addr = desc->source_address2 - + (extract32(desc->address_extension_23, 0, 12) << 8); + addr = (uint64_t)desc->source_address2 + + (extract64(desc->address_extension_23, 0, 16) << 32); break; case 2: - addr = desc->source_address3 - + (extract32(desc->address_extension_23, 16, 12) << 20); + addr = (uint64_t)desc->source_address3 + + (extract64(desc->address_extension_23, 16, 16) << 32); break; case 3: - addr = desc->source_address4 - + (extract32(desc->address_extension_45, 0, 12) << 8); + addr = (uint64_t)desc->source_address4 + + (extract64(desc->address_extension_45, 0, 16) << 32); break; case 4: - addr = desc->source_address5 - + (extract32(desc->address_extension_45, 16, 12) << 20); + addr = (uint64_t)desc->source_address5 + + (extract64(desc->address_extension_45, 16, 16) << 32); break; default: addr = 0; From patchwork Tue Apr 30 16:48:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 793338 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp365687wrf; Tue, 30 Apr 2024 09:49:34 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWAvcbvbg3UOFYwZecSoV9zZ2NGYRjOc10uu4pKgS8x4Ap01bhcDdIGH2+ww32QJxDAnN9HhRjch5yHETH916mv X-Google-Smtp-Source: AGHT+IEeRQrMkWM3aNiG5EJUkFf3DrMBWOabzgYs6lvDHXH5B/gDWq2F7ZxKg8Ex4KYgD7vJehvj X-Received: by 2002:a05:622a:164f:b0:43a:f8d3:f4c4 with SMTP id y15-20020a05622a164f00b0043af8d3f4c4mr7466575qtj.21.1714495773927; Tue, 30 Apr 2024 09:49:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714495773; cv=none; d=google.com; s=arc-20160816; b=GjMP+LWjZ7hi2l19c09rqYbo4HBcRZvHr/jDBFS0AXAFe/cXvVpATKlY60DAiWbJeA EIpBWiX6rWzToORP4vU3XI7mar8bgWG6rD9qDg2bidH02s3E1gpe34aHbny00s9xcDc3 +9VW5PCqo4DQ+p7uvf/lJSMJgCYDPHZ/9nAFSpXm9QSqOypP2DW88qqiJd6PlzTQ/xDy w35UI/L0hE6UfcwEoqQKRd30+1/SK3BOQ9TVAqjIi84a46a7TKHQ4PZKB+2FWdx4vp/C 1IcjqUh1ZulnZGZGUXajLArtIaL6eu0KudLkqGVe/WdKtElhJHI4LPCodIlmLHi69xJo 5IOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jfP2Xs16ecOHAKV51keNnHcyI2sGLGC6VRxN9Ns0ctk=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=KemIfImPOwEu0AVJOxMFP+MaFJwyu7pRO/B2awsXZe+0kZf6bBrAOjXzMqmMO4+NTz YQBFnXY/WiVgM/J2i6q5IyC6xO8l/RH3T3W+e990Og80FBUczPhkOyAzG/T47ZWabkbF sOXfzTdLWltLSUqsz/4HnXoY1c4Z1XGSfTI9MlTn25tg0os5mSTJLUdsLB1y4+g8oW6p oTfjRfYzKxgQJTa9twUtvKJyRmoG3GshSA5masxpg8G9FBTDHQVf1cUpqyH/aRQojMbW Qr+PJbJNgxB7HZGcn6Sd8eG3eLU4/+s6dyl2o2+PMeA7bQqzEHC9u1fdD/ha7U3oSvmU W7kg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="HppNUR/A"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/21] hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size Date: Tue, 30 Apr 2024 17:48:36 +0100 Message-Id: <20240430164842.4074734-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Thomas Huth "make check-qtest-aarch64" recently started failing on FreeBSD builds, and valgrind on Linux also detected that there is something fishy with the new stm32l4x5-usart: The code forgot to set the correct class_size here, so the various class_init functions in this file wrote beyond the allocated buffer when setting the subc->type field. Fixes: 4fb37aea7e ("hw/char: Implement STM32L4x5 USART skeleton") Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240429075908.36302-1-thuth@redhat.com Signed-off-by: Peter Maydell --- hw/char/stm32l4x5_usart.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c index 2627aab8324..02f666308c0 100644 --- a/hw/char/stm32l4x5_usart.c +++ b/hw/char/stm32l4x5_usart.c @@ -617,6 +617,7 @@ static const TypeInfo stm32l4x5_usart_types[] = { .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(Stm32l4x5UsartBaseState), .instance_init = stm32l4x5_usart_base_init, + .class_size = sizeof(Stm32l4x5UsartBaseClass), .class_init = stm32l4x5_usart_base_class_init, .abstract = true, }, { From patchwork Tue Apr 30 16:48:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 793342 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp366009wrf; Tue, 30 Apr 2024 09:50:19 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVlMOcEDTdoSMQNnXmo1VCs42x/T/jPxhtf4/nmY4dz3WRpLJ+Nj8r0dWCccNonO34aByaaM8sbvx4qK7P9neNC X-Google-Smtp-Source: AGHT+IF6OWTa9SV7jZh3/WcWqlVC7KGonQqoNAyHWrgC6Op3pbuTtguPwgSkEH9Z0z+EjZc7Ft7U X-Received: by 2002:ad4:4eee:0:b0:6a0:cb66:4596 with SMTP id dv14-20020ad44eee000000b006a0cb664596mr9248400qvb.38.1714495819543; Tue, 30 Apr 2024 09:50:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714495819; cv=none; d=google.com; s=arc-20160816; b=tWTILK979QZJDK4vJrpXOdKPvWtlAC+E9UdZ9VZ+w3ZaR00p7V9K3CbL8NJM/vvpqe 0jnWVZwEXp6oRz+h8Z5L4pTmviiAeVN1ZDY5fydOxfJWm1630kG4A5HoiJW3ncl7cier ZqPq4rUr9GSdD6ctjiDwtKCL6KIfVbU+02MDmgFJLOQMKWBrApKCBtAO/Lv0GDcwEDvB Lc6yzO0tPxnmZuUvCFeem4AzZAMklFUytTSQhTHBxTOY1LrT5QdB4TDT6xNjWGDp/PmV eeG/IcG5S0jkPbNIgP3koW/eLWmfrxS9pEv5ussugn1H0ch2BKrshpItgXo0a5sMb9tS tnzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VFare7ZkADygwn6ondDR3tguZCHt/fs/mvSL2SvbhYg=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=y2Gr6jRwSBmHi4/VktqW7G9Czuuq0wwgCR7Oc5YmMZL6w733c4ycDwC68NdxMFkyQj xIJYZVssmv6zjiMw5HNTnGISQXQAykTGZILfFXaDi8Qv/6jjJBRsr7henH30AFX/EwPS cltKgzvrFkwn2o5FJe+/xXkk4DqsA7diJw8PqikgYqcHztlJb18DqioLa90wOsO2guEl jh4AoP71VN3nIe60ukAlkw0bEi1deMRMDwMRzp1N0SfAg3wAWa8ApvX2JaszUZRv7AYX imbu8SaRLYXts0rZ0leGcldVUKvdUPd6ewE2/npJib/6ZTnB9aJH+z3PMIuPP+dxZaHA 236Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hIIZsEgU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/21] hw/arm/npcm7xx: Store derivative OTP fuse key in little endian Date: Tue, 30 Apr 2024 17:48:37 +0100 Message-Id: <20240430164842.4074734-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Use little endian for derivative OTP fuse key. Cc: qemu-stable@nongnu.org Fixes: c752bb079b ("hw/nvram: NPCM7xx OTP device model") Suggested-by: Avi Fishman Signed-off-by: Philippe Mathieu-Daudé Message-id: 20240422125813.1403-1-philmd@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/npcm7xx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index cc68b5d8f12..9f2d96c733a 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -24,6 +24,7 @@ #include "hw/qdev-clock.h" #include "hw/qdev-properties.h" #include "qapi/error.h" +#include "qemu/bswap.h" #include "qemu/units.h" #include "sysemu/sysemu.h" #include "target/arm/cpu-qom.h" @@ -386,7 +387,7 @@ static void npcm7xx_init_fuses(NPCM7xxState *s) * The initial mask of disabled modules indicates the chip derivative (e.g. * NPCM750 or NPCM730). */ - value = tswap32(nc->disabled_modules); + value = cpu_to_le32(nc->disabled_modules); npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE, sizeof(value)); } From patchwork Tue Apr 30 16:48:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 793348 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp366612wrf; Tue, 30 Apr 2024 09:51:20 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXyYpRPglJIXrgVvleFuvKI9zwtZRUMcsVeG5YNWjGn5zWgQUGeDzUVQwr/Hg8xkYZRHKamF7BTb8fhA0npATbx X-Google-Smtp-Source: AGHT+IGiwG8obMUUxuqElJc8S6fZVOv7SZiF3P1xsR1pOqDkBFKSERl7sOm6lPNu8TV8IZKuO5nf X-Received: by 2002:a05:622a:43:b0:43a:db77:100a with SMTP id y3-20020a05622a004300b0043adb77100amr3193752qtw.34.1714495880316; Tue, 30 Apr 2024 09:51:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714495880; cv=none; d=google.com; s=arc-20160816; b=oSW8/vn6PGnlnHCsuZu5n1vemxnyoTHrG6Yc21wqPqEhz8pBS7xI8pSrXZQu/2oIYX CYpqVCN8m1vVcg4annNzIqnpRTlXndVj258pSZHSL97EBTfJx6w0kc8Sscwzq9KhYNZc pUkh7nkV1T0ib8RQyfwh2JVelYSS0qX4pRIaFYGljc+MHOCIhHQMYT1ZCMrYSeKiMDEe ThG89kwyBfPm7BEfDUFJd/IXgMNSmE1pT7HpVogvku896Udtze/VDmWNlcLFTQ/Czu8y IeEtxy/oKuPi/1cKm1YYCGNxaEV3stuZyjINCderis8ZxTNcu6UVeaH51nmRlSN+tCBo tgpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/UJg/HxLsW5auAfzXeiLmjSCbsQPM6BkMOVvD5diRo0=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=sJI9znJnt72trX5yhAeT0PzHYosxD46UVm+wHRfXnR0cxkJff/Te2S5XckpiQ3hg1m fFdvwDDUAU+NTa0NG8otcMc9sdy7IsX4LhdG4/l/Y5azW4StSc53mq+LKtp2kZnPiWie vfH1gHpXTy+p190hX/rS0qdAS+8/SRFaB1RcpYW9rCAhOfYiNskkXbp3uw/stquFHmwg CwYa4YjWKckIuBTJFgCNrIhUlCKxayi4oMtPU9asB7a7wP3VvSGhSihFwifas3VbWyeG 6rDwaWawxHeE6pcIsxeLqXQOEMe5ure4m80NEMSCZsNdYQJgYd05GvumdzMZJHSUCB0S /gsg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Cdq4Ezcz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/21] hw/display : Add device DM163 Date: Tue, 30 Apr 2024 17:48:38 +0100 Message-Id: <20240430164842.4074734-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Inès Varhol This device implements the IM120417002 colors shield v1.1 for Arduino (which relies on the DM163 8x3-channel led driving logic) and features a simple display of an 8x8 RGB matrix. The columns of the matrix are driven by the DM163 and the rows are driven externally. Acked-by: Alistair Francis Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240424200929.240921-2-ines.varhol@telecom-paris.fr [PMM: updated to new reset hold method prototype] Signed-off-by: Peter Maydell --- docs/system/arm/b-l475e-iot01a.rst | 3 +- include/hw/display/dm163.h | 59 +++++ hw/display/dm163.c | 349 +++++++++++++++++++++++++++++ hw/display/Kconfig | 3 + hw/display/meson.build | 1 + hw/display/trace-events | 14 ++ 6 files changed, 428 insertions(+), 1 deletion(-) create mode 100644 include/hw/display/dm163.h create mode 100644 hw/display/dm163.c diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst index a76c9976c50..2adcc4b4c16 100644 --- a/docs/system/arm/b-l475e-iot01a.rst +++ b/docs/system/arm/b-l475e-iot01a.rst @@ -12,7 +12,7 @@ USART, I2C, SPI, CAN and USB OTG, as well as a variety of sensors. Supported devices """"""""""""""""" -Currently B-L475E-IOT01A machine's only supports the following devices: +Currently B-L475E-IOT01A machines support the following devices: - Cortex-M4F based STM32L4x5 SoC - STM32L4x5 EXTI (Extended interrupts and events controller) @@ -20,6 +20,7 @@ Currently B-L475E-IOT01A machine's only supports the following devices: - STM32L4x5 RCC (Reset and clock control) - STM32L4x5 GPIOs (General-purpose I/Os) - STM32L4x5 USARTs, UARTs and LPUART (Serial ports) +- optional 8x8 led display (based on DM163 driver) Missing devices """"""""""""""" diff --git a/include/hw/display/dm163.h b/include/hw/display/dm163.h new file mode 100644 index 00000000000..4377f77bb75 --- /dev/null +++ b/include/hw/display/dm163.h @@ -0,0 +1,59 @@ +/* + * QEMU DM163 8x3-channel constant current led driver + * driving columns of associated 8x8 RGB matrix. + * + * Copyright (C) 2024 Samuel Tardieu + * Copyright (C) 2024 Arnaud Minier + * Copyright (C) 2024 Inès Varhol + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_DISPLAY_DM163_H +#define HW_DISPLAY_DM163_H + +#include "qom/object.h" +#include "hw/qdev-core.h" + +#define TYPE_DM163 "dm163" +OBJECT_DECLARE_SIMPLE_TYPE(DM163State, DM163); + +#define RGB_MATRIX_NUM_ROWS 8 +#define RGB_MATRIX_NUM_COLS 8 +#define DM163_NUM_LEDS (RGB_MATRIX_NUM_COLS * 3) +/* The last row is filled with 0 (turned off row) */ +#define COLOR_BUFFER_SIZE (RGB_MATRIX_NUM_ROWS + 1) + +typedef struct DM163State { + DeviceState parent_obj; + + /* DM163 driver */ + uint64_t bank0_shift_register[3]; + uint64_t bank1_shift_register[3]; + uint16_t latched_outputs[DM163_NUM_LEDS]; + uint16_t outputs[DM163_NUM_LEDS]; + qemu_irq sout; + + uint8_t sin; + uint8_t dck; + uint8_t rst_b; + uint8_t lat_b; + uint8_t selbk; + uint8_t en_b; + + /* IM120417002 colors shield */ + uint8_t activated_rows; + + /* 8x8 RGB matrix */ + QemuConsole *console; + uint8_t redraw; + /* Rows currently being displayed on the matrix. */ + /* The last row is filled with 0 (turned off row) */ + uint32_t buffer[COLOR_BUFFER_SIZE][RGB_MATRIX_NUM_COLS]; + uint8_t last_buffer_idx; + uint8_t buffer_idx_of_row[RGB_MATRIX_NUM_ROWS]; + /* Used to simulate retinal persistence of rows */ + uint8_t row_persistence_delay[RGB_MATRIX_NUM_ROWS]; +} DM163State; + +#endif /* HW_DISPLAY_DM163_H */ diff --git a/hw/display/dm163.c b/hw/display/dm163.c new file mode 100644 index 00000000000..f92aee371d9 --- /dev/null +++ b/hw/display/dm163.c @@ -0,0 +1,349 @@ +/* + * QEMU DM163 8x3-channel constant current led driver + * driving columns of associated 8x8 RGB matrix. + * + * Copyright (C) 2024 Samuel Tardieu + * Copyright (C) 2024 Arnaud Minier + * Copyright (C) 2024 Inès Varhol + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * The reference used for the DM163 is the following : + * http://www.siti.com.tw/product/spec/LED/DM163.pdf + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "migration/vmstate.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/display/dm163.h" +#include "ui/console.h" +#include "trace.h" + +#define LED_SQUARE_SIZE 100 +/* Number of frames a row stays visible after being turned off. */ +#define ROW_PERSISTENCE 3 +#define TURNED_OFF_ROW (COLOR_BUFFER_SIZE - 1) + +static const VMStateDescription vmstate_dm163 = { + .name = TYPE_DM163, + .version_id = 1, + .minimum_version_id = 1, + .fields = (const VMStateField[]) { + VMSTATE_UINT64_ARRAY(bank0_shift_register, DM163State, 3), + VMSTATE_UINT64_ARRAY(bank1_shift_register, DM163State, 3), + VMSTATE_UINT16_ARRAY(latched_outputs, DM163State, DM163_NUM_LEDS), + VMSTATE_UINT16_ARRAY(outputs, DM163State, DM163_NUM_LEDS), + VMSTATE_UINT8(dck, DM163State), + VMSTATE_UINT8(en_b, DM163State), + VMSTATE_UINT8(lat_b, DM163State), + VMSTATE_UINT8(rst_b, DM163State), + VMSTATE_UINT8(selbk, DM163State), + VMSTATE_UINT8(sin, DM163State), + VMSTATE_UINT8(activated_rows, DM163State), + VMSTATE_UINT32_2DARRAY(buffer, DM163State, COLOR_BUFFER_SIZE, + RGB_MATRIX_NUM_COLS), + VMSTATE_UINT8(last_buffer_idx, DM163State), + VMSTATE_UINT8_ARRAY(buffer_idx_of_row, DM163State, RGB_MATRIX_NUM_ROWS), + VMSTATE_UINT8_ARRAY(row_persistence_delay, DM163State, + RGB_MATRIX_NUM_ROWS), + VMSTATE_END_OF_LIST() + } +}; + +static void dm163_reset_hold(Object *obj, ResetType type) +{ + DM163State *s = DM163(obj); + + s->sin = 0; + s->dck = 0; + s->rst_b = 0; + /* Ensuring the first falling edge of lat_b isn't missed */ + s->lat_b = 1; + s->selbk = 0; + s->en_b = 0; + /* Reset stops the PWM, not the shift and latched registers. */ + memset(s->outputs, 0, sizeof(s->outputs)); + + s->activated_rows = 0; + s->redraw = 0; + trace_dm163_redraw(s->redraw); + for (unsigned i = 0; i < COLOR_BUFFER_SIZE; i++) { + memset(s->buffer[i], 0, sizeof(s->buffer[0])); + } + s->last_buffer_idx = 0; + memset(s->buffer_idx_of_row, TURNED_OFF_ROW, sizeof(s->buffer_idx_of_row)); + memset(s->row_persistence_delay, 0, sizeof(s->row_persistence_delay)); +} + +static void dm163_dck_gpio_handler(void *opaque, int line, int new_state) +{ + DM163State *s = opaque; + + if (new_state && !s->dck) { + /* + * On raising dck, sample selbk to get the bank to use, and + * sample sin for the bit to enter into the bank shift buffer. + */ + uint64_t *sb = + s->selbk ? s->bank1_shift_register : s->bank0_shift_register; + /* Output the outgoing bit on sout */ + const bool sout = (s->selbk ? sb[2] & MAKE_64BIT_MASK(63, 1) : + sb[2] & MAKE_64BIT_MASK(15, 1)) != 0; + qemu_set_irq(s->sout, sout); + /* Enter sin into the shift buffer */ + sb[2] = (sb[2] << 1) | ((sb[1] >> 63) & 1); + sb[1] = (sb[1] << 1) | ((sb[0] >> 63) & 1); + sb[0] = (sb[0] << 1) | s->sin; + } + + s->dck = new_state; + trace_dm163_dck(new_state); +} + +static void dm163_propagate_outputs(DM163State *s) +{ + s->last_buffer_idx = (s->last_buffer_idx + 1) % RGB_MATRIX_NUM_ROWS; + /* Values are output when reset is high and enable is low. */ + if (s->rst_b && !s->en_b) { + memcpy(s->outputs, s->latched_outputs, sizeof(s->outputs)); + } else { + memset(s->outputs, 0, sizeof(s->outputs)); + } + for (unsigned x = 0; x < RGB_MATRIX_NUM_COLS; x++) { + /* Grouping the 3 RGB channels in a pixel value */ + const uint16_t b = extract16(s->outputs[3 * x + 0], 6, 8); + const uint16_t g = extract16(s->outputs[3 * x + 1], 6, 8); + const uint16_t r = extract16(s->outputs[3 * x + 2], 6, 8); + uint32_t rgba = 0; + + trace_dm163_channels(3 * x + 2, r); + trace_dm163_channels(3 * x + 1, g); + trace_dm163_channels(3 * x + 0, b); + + rgba = deposit32(rgba, 0, 8, r); + rgba = deposit32(rgba, 8, 8, g); + rgba = deposit32(rgba, 16, 8, b); + + /* Led values are sent from the last one to the first one */ + s->buffer[s->last_buffer_idx][RGB_MATRIX_NUM_COLS - x - 1] = rgba; + } + for (unsigned row = 0; row < RGB_MATRIX_NUM_ROWS; row++) { + if (s->activated_rows & (1 << row)) { + s->buffer_idx_of_row[row] = s->last_buffer_idx; + s->redraw |= (1 << row); + trace_dm163_redraw(s->redraw); + } + } +} + +static void dm163_en_b_gpio_handler(void *opaque, int line, int new_state) +{ + DM163State *s = opaque; + + s->en_b = new_state; + dm163_propagate_outputs(s); + trace_dm163_en_b(new_state); +} + +static uint8_t dm163_bank0(const DM163State *s, uint8_t led) +{ + /* + * Bank 0 uses 6 bits per led, so a value may be stored accross + * two uint64_t entries. + */ + const uint8_t low_bit = 6 * led; + const uint8_t low_word = low_bit / 64; + const uint8_t high_word = (low_bit + 5) / 64; + const uint8_t low_shift = low_bit % 64; + + if (low_word == high_word) { + /* Simple case: the value belongs to one entry. */ + return extract64(s->bank0_shift_register[low_word], low_shift, 6); + } + + const uint8_t nb_bits_in_low_word = 64 - low_shift; + const uint8_t nb_bits_in_high_word = 6 - nb_bits_in_low_word; + + const uint64_t bits_in_low_word = \ + extract64(s->bank0_shift_register[low_word], low_shift, + nb_bits_in_low_word); + const uint64_t bits_in_high_word = \ + extract64(s->bank0_shift_register[high_word], 0, + nb_bits_in_high_word); + uint8_t val = 0; + + val = deposit32(val, 0, nb_bits_in_low_word, bits_in_low_word); + val = deposit32(val, nb_bits_in_low_word, nb_bits_in_high_word, + bits_in_high_word); + + return val; +} + +static uint8_t dm163_bank1(const DM163State *s, uint8_t led) +{ + const uint64_t entry = s->bank1_shift_register[led / RGB_MATRIX_NUM_COLS]; + return extract64(entry, 8 * (led % RGB_MATRIX_NUM_COLS), 8); +} + +static void dm163_lat_b_gpio_handler(void *opaque, int line, int new_state) +{ + DM163State *s = opaque; + + if (s->lat_b && !new_state) { + for (int led = 0; led < DM163_NUM_LEDS; led++) { + s->latched_outputs[led] = dm163_bank0(s, led) * dm163_bank1(s, led); + } + dm163_propagate_outputs(s); + } + + s->lat_b = new_state; + trace_dm163_lat_b(new_state); +} + +static void dm163_rst_b_gpio_handler(void *opaque, int line, int new_state) +{ + DM163State *s = opaque; + + s->rst_b = new_state; + dm163_propagate_outputs(s); + trace_dm163_rst_b(new_state); +} + +static void dm163_selbk_gpio_handler(void *opaque, int line, int new_state) +{ + DM163State *s = opaque; + + s->selbk = new_state; + trace_dm163_selbk(new_state); +} + +static void dm163_sin_gpio_handler(void *opaque, int line, int new_state) +{ + DM163State *s = opaque; + + s->sin = new_state; + trace_dm163_sin(new_state); +} + +static void dm163_rows_gpio_handler(void *opaque, int line, int new_state) +{ + DM163State *s = opaque; + + if (new_state) { + s->activated_rows |= (1 << line); + s->buffer_idx_of_row[line] = s->last_buffer_idx; + s->redraw |= (1 << line); + trace_dm163_redraw(s->redraw); + } else { + s->activated_rows &= ~(1 << line); + s->row_persistence_delay[line] = ROW_PERSISTENCE; + } + trace_dm163_activated_rows(s->activated_rows); +} + +static void dm163_invalidate_display(void *opaque) +{ + DM163State *s = (DM163State *)opaque; + s->redraw = 0xFF; + trace_dm163_redraw(s->redraw); +} + +static void update_row_persistence_delay(DM163State *s, unsigned row) +{ + if (s->row_persistence_delay[row]) { + s->row_persistence_delay[row]--; + } else { + /* + * If the ROW_PERSISTENCE delay is up, + * the row is turned off. + */ + s->buffer_idx_of_row[row] = TURNED_OFF_ROW; + s->redraw |= (1 << row); + trace_dm163_redraw(s->redraw); + } +} + +static uint32_t *update_display_of_row(DM163State *s, uint32_t *dest, + unsigned row) +{ + for (unsigned _ = 0; _ < LED_SQUARE_SIZE; _++) { + for (int x = 0; x < RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE; x++) { + /* UI layer guarantees that there's 32 bits per pixel (Mar 2024) */ + *dest++ = s->buffer[s->buffer_idx_of_row[row]][x / LED_SQUARE_SIZE]; + } + } + + dpy_gfx_update(s->console, 0, LED_SQUARE_SIZE * row, + RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE, LED_SQUARE_SIZE); + s->redraw &= ~(1 << row); + trace_dm163_redraw(s->redraw); + + return dest; +} + +static void dm163_update_display(void *opaque) +{ + DM163State *s = (DM163State *)opaque; + DisplaySurface *surface = qemu_console_surface(s->console); + uint32_t *dest; + + dest = surface_data(surface); + for (unsigned row = 0; row < RGB_MATRIX_NUM_ROWS; row++) { + update_row_persistence_delay(s, row); + if (!extract8(s->redraw, row, 1)) { + dest += LED_SQUARE_SIZE * LED_SQUARE_SIZE * RGB_MATRIX_NUM_COLS; + continue; + } + dest = update_display_of_row(s, dest, row); + } +} + +static const GraphicHwOps dm163_ops = { + .invalidate = dm163_invalidate_display, + .gfx_update = dm163_update_display, +}; + +static void dm163_realize(DeviceState *dev, Error **errp) +{ + DM163State *s = DM163(dev); + + qdev_init_gpio_in(dev, dm163_rows_gpio_handler, RGB_MATRIX_NUM_ROWS); + qdev_init_gpio_in(dev, dm163_sin_gpio_handler, 1); + qdev_init_gpio_in(dev, dm163_dck_gpio_handler, 1); + qdev_init_gpio_in(dev, dm163_rst_b_gpio_handler, 1); + qdev_init_gpio_in(dev, dm163_lat_b_gpio_handler, 1); + qdev_init_gpio_in(dev, dm163_selbk_gpio_handler, 1); + qdev_init_gpio_in(dev, dm163_en_b_gpio_handler, 1); + qdev_init_gpio_out_named(dev, &s->sout, "sout", 1); + + s->console = graphic_console_init(dev, 0, &dm163_ops, s); + qemu_console_resize(s->console, RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE, + RGB_MATRIX_NUM_ROWS * LED_SQUARE_SIZE); +} + +static void dm163_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); + + dc->desc = "DM163"; + dc->vmsd = &vmstate_dm163; + dc->realize = dm163_realize; + rc->phases.hold = dm163_reset_hold; + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); +} + +static const TypeInfo dm163_types[] = { + { + .name = TYPE_DM163, + .parent = TYPE_DEVICE, + .instance_size = sizeof(DM163State), + .class_init = dm163_class_init + } +}; + +DEFINE_TYPES(dm163_types) diff --git a/hw/display/Kconfig b/hw/display/Kconfig index 234c7de027c..a4552c8ed78 100644 --- a/hw/display/Kconfig +++ b/hw/display/Kconfig @@ -140,3 +140,6 @@ config XLNX_DISPLAYPORT bool # defaults to "N", enabled by specific boards depends on PIXMAN + +config DM163 + bool diff --git a/hw/display/meson.build b/hw/display/meson.build index 4751aab3ba9..7893b94c8ee 100644 --- a/hw/display/meson.build +++ b/hw/display/meson.build @@ -38,6 +38,7 @@ system_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('next-fb.c')) system_ss.add(when: 'CONFIG_VGA', if_true: files('vga.c')) system_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-dmabuf.c')) +system_ss.add(when: 'CONFIG_DM163', if_true: files('dm163.c')) if (config_all_devices.has_key('CONFIG_VGA_CIRRUS') or config_all_devices.has_key('CONFIG_VGA_PCI') or diff --git a/hw/display/trace-events b/hw/display/trace-events index 2336a0ca157..781f8a33203 100644 --- a/hw/display/trace-events +++ b/hw/display/trace-events @@ -177,3 +177,17 @@ macfb_ctrl_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%"PRI macfb_sense_read(uint32_t value) "video sense: 0x%"PRIx32 macfb_sense_write(uint32_t value) "video sense: 0x%"PRIx32 macfb_update_mode(uint32_t width, uint32_t height, uint8_t depth) "setting mode to width %"PRId32 " height %"PRId32 " size %d" + +# dm163.c +dm163_redraw(uint8_t redraw) "0x%02x" +dm163_dck(unsigned new_state) "dck : %u" +dm163_en_b(unsigned new_state) "en_b : %u" +dm163_rst_b(unsigned new_state) "rst_b : %u" +dm163_lat_b(unsigned new_state) "lat_b : %u" +dm163_sin(unsigned new_state) "sin : %u" +dm163_selbk(unsigned new_state) "selbk : %u" +dm163_activated_rows(int new_state) "Activated rows : 0x%" PRIx32 "" +dm163_bits_ppi(unsigned dest_width) "dest_width : %u" +dm163_leds(int led, uint32_t value) "led %d: 0x%x" +dm163_channels(int channel, uint8_t value) "channel %d: 0x%x" +dm163_refresh_rate(uint32_t rr) "refresh rate %d" From patchwork Tue Apr 30 16:48:39 2024 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/21] hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC Date: Tue, 30 Apr 2024 17:48:39 +0100 Message-Id: <20240430164842.4074734-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Inès Varhol Exposing SYSCFG inputs to the SoC is practical in order to wire the SoC to the optional DM163 display from the board code (GPIOs outputs need to be connected to both SYSCFG inputs and DM163 inputs). STM32L4x5 SYSCFG in-irq interception needed to be changed accordingly. Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240424200929.240921-3-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell --- hw/arm/stm32l4x5_soc.c | 6 ++++-- tests/qtest/stm32l4x5_gpio-test.c | 13 ++++++++----- tests/qtest/stm32l4x5_syscfg-test.c | 17 ++++++++++------- 3 files changed, 22 insertions(+), 14 deletions(-) diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c index 39924822f3d..38f7a2d5d9f 100644 --- a/hw/arm/stm32l4x5_soc.c +++ b/hw/arm/stm32l4x5_soc.c @@ -1,8 +1,8 @@ /* * STM32L4x5 SoC family * - * Copyright (c) 2023 Arnaud Minier - * Copyright (c) 2023 Inès Varhol + * Copyright (c) 2023-2024 Arnaud Minier + * Copyright (c) 2023-2024 Inès Varhol * * SPDX-License-Identifier: GPL-2.0-or-later * @@ -250,6 +250,8 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) } } + qdev_pass_gpios(DEVICE(&s->syscfg), dev_soc, NULL); + /* EXTI device */ busdev = SYS_BUS_DEVICE(&s->exti); if (!sysbus_realize(busdev, errp)) { diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c index 0f6bda54d3c..72a78234066 100644 --- a/tests/qtest/stm32l4x5_gpio-test.c +++ b/tests/qtest/stm32l4x5_gpio-test.c @@ -43,6 +43,9 @@ #define OTYPER_PUSH_PULL 0 #define OTYPER_OPEN_DRAIN 1 +/* SoC forwards GPIOs to SysCfg */ +#define SYSCFG "/machine/soc" + const uint32_t moder_reset[NUM_GPIOS] = { 0xABFFFFFF, 0xFFFFFEBF, @@ -284,7 +287,7 @@ static void test_gpio_output_mode(const void *data) uint32_t gpio = test_gpio_addr(data); unsigned int gpio_id = get_gpio_id(gpio); - qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); + qtest_irq_intercept_in(global_qtest, SYSCFG); /* Set a bit in ODR and check nothing happens */ gpio_set_bit(gpio, ODR, pin, 1); @@ -319,7 +322,7 @@ static void test_gpio_input_mode(const void *data) uint32_t gpio = test_gpio_addr(data); unsigned int gpio_id = get_gpio_id(gpio); - qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); + qtest_irq_intercept_in(global_qtest, SYSCFG); /* Configure a line as input, raise it, and check that the pin is high */ gpio_set_2bits(gpio, MODER, pin, MODER_INPUT); @@ -348,7 +351,7 @@ static void test_pull_up_pull_down(const void *data) uint32_t gpio = test_gpio_addr(data); unsigned int gpio_id = get_gpio_id(gpio); - qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); + qtest_irq_intercept_in(global_qtest, SYSCFG); /* Configure a line as input with pull-up, check the line is set high */ gpio_set_2bits(gpio, MODER, pin, MODER_INPUT); @@ -378,7 +381,7 @@ static void test_push_pull(const void *data) uint32_t gpio = test_gpio_addr(data); uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio); - qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); + qtest_irq_intercept_in(global_qtest, SYSCFG); /* Setting a line high externally, configuring it in push-pull output */ /* And checking the pin was disconnected */ @@ -425,7 +428,7 @@ static void test_open_drain(const void *data) uint32_t gpio = test_gpio_addr(data); uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio); - qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); + qtest_irq_intercept_in(global_qtest, SYSCFG); /* Setting a line high externally, configuring it in open-drain output */ /* And checking the pin was disconnected */ diff --git a/tests/qtest/stm32l4x5_syscfg-test.c b/tests/qtest/stm32l4x5_syscfg-test.c index 59bac829b7d..506ca08bc24 100644 --- a/tests/qtest/stm32l4x5_syscfg-test.c +++ b/tests/qtest/stm32l4x5_syscfg-test.c @@ -1,8 +1,8 @@ /* * QTest testcase for STM32L4x5_SYSCFG * - * Copyright (c) 2023 Arnaud Minier - * Copyright (c) 2023 Inès Varhol + * Copyright (c) 2024 Arnaud Minier + * Copyright (c) 2024 Inès Varhol * * This work is licensed under the terms of the GNU GPL, version 2 or later. * See the COPYING file in the top-level directory. @@ -25,6 +25,10 @@ #define SYSCFG_SWPR2 0x28 #define INVALID_ADDR 0x2C +/* SoC forwards GPIOs to SysCfg */ +#define SYSCFG "/machine/soc" +#define EXTI "/machine/soc/exti" + static void syscfg_writel(unsigned int offset, uint32_t value) { writel(SYSCFG_BASE_ADDR + offset, value); @@ -37,8 +41,7 @@ static uint32_t syscfg_readl(unsigned int offset) static void syscfg_set_irq(int num, int level) { - qtest_set_irq_in(global_qtest, "/machine/soc/syscfg", - NULL, num, level); + qtest_set_irq_in(global_qtest, SYSCFG, NULL, num, level); } static void system_reset(void) @@ -197,7 +200,7 @@ static void test_interrupt(void) * Test that GPIO rising lines result in an irq * with the right configuration */ - qtest_irq_intercept_in(global_qtest, "/machine/soc/exti"); + qtest_irq_intercept_in(global_qtest, EXTI); /* GPIOA is the default source for EXTI lines 0 to 15 */ @@ -230,7 +233,7 @@ static void test_irq_pin_multiplexer(void) * Test that syscfg irq sets the right exti irq */ - qtest_irq_intercept_in(global_qtest, "/machine/soc/exti"); + qtest_irq_intercept_in(global_qtest, EXTI); syscfg_set_irq(0, 1); @@ -257,7 +260,7 @@ static void test_irq_gpio_multiplexer(void) * Test that an irq is generated only by the right GPIO */ - qtest_irq_intercept_in(global_qtest, "/machine/soc/exti"); + qtest_irq_intercept_in(global_qtest, EXTI); /* GPIOA is the default source for EXTI lines 0 to 15 */ From patchwork Tue Apr 30 16:48:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 793341 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp365992wrf; Tue, 30 Apr 2024 09:50:17 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWHeij/cagrHt+nWWfHzsihTvdzKJdtH9BKHPl7ib6O16mZ70gPOpUFnE1ONJ1VK0/3pFjVBzS8+B+jJScyfsq2 X-Google-Smtp-Source: AGHT+IE/skZtOiY2r1h88MG+gocnD/NkAQOrUhA61SobTeL0klkNv+s/OIfL1+tvOwXQ1p4sHnJT X-Received: by 2002:a05:6122:929:b0:4de:d0ee:7751 with SMTP id j41-20020a056122092900b004ded0ee7751mr331780vka.11.1714495817338; Tue, 30 Apr 2024 09:50:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714495817; cv=none; d=google.com; s=arc-20160816; b=NPJOZPip6qSg7+yeyHoIC8kVefM+oVa54U4UtGpAG7vhSR9ShU6rFRc0Zc4ZUHe+4p FZJxGB9/s3nYMxxnwN8rmsLNidsVjSz3SAbczb6ygdInTLHP8Oi6TTXjGluTWl5VDeAh 20PsXMa1npvCdmdHOyhzmSFsYw+/kwe6PGs0WCat77Rg5104y4IFVgSoW8NTppBJQtcS cxUgeGCYLxrghuiNPlWPdrDAIH3a/nS0kjgZrhyl0i3hL7e+etZ1LQZmsNs3tL8mboVt 88I5zZaYx9uzVPtzXvg+Hz80F2/Ok6fOO7qVof5gQwIkfF/pgGCGLSZJcRh8+udPYrsP elUw== ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/21] hw/arm : Create Bl475eMachineState Date: Tue, 30 Apr 2024 17:48:40 +0100 Message-Id: <20240430164842.4074734-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Inès Varhol Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240424200929.240921-4-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell --- hw/arm/b-l475e-iot01a.c | 46 ++++++++++++++++++++++++++++------------- 1 file changed, 32 insertions(+), 14 deletions(-) diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c index d862aa43fc3..970c637ce61 100644 --- a/hw/arm/b-l475e-iot01a.c +++ b/hw/arm/b-l475e-iot01a.c @@ -2,8 +2,8 @@ * B-L475E-IOT01A Discovery Kit machine * (B-L475E-IOT01A IoT Node) * - * Copyright (c) 2023 Arnaud Minier - * Copyright (c) 2023 Inès Varhol + * Copyright (c) 2023-2024 Arnaud Minier + * Copyright (c) 2023-2024 Inès Varhol * * SPDX-License-Identifier: GPL-2.0-or-later * @@ -32,33 +32,51 @@ /* B-L475E-IOT01A implementation is derived from netduinoplus2 */ -static void b_l475e_iot01a_init(MachineState *machine) +#define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a") +OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A) + +typedef struct Bl475eMachineState { + MachineState parent_obj; + + Stm32l4x5SocState soc; +} Bl475eMachineState; + +static void bl475e_init(MachineState *machine) { + Bl475eMachineState *s = B_L475E_IOT01A(machine); const Stm32l4x5SocClass *sc; - DeviceState *dev; - dev = qdev_new(TYPE_STM32L4X5XG_SOC); - object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + object_initialize_child(OBJECT(machine), "soc", &s->soc, + TYPE_STM32L4X5XG_SOC); + sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); - sc = STM32L4X5_SOC_GET_CLASS(dev); - armv7m_load_kernel(ARM_CPU(first_cpu), - machine->kernel_filename, - 0, sc->flash_size); + sc = STM32L4X5_SOC_GET_CLASS(&s->soc); + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0, + sc->flash_size); } -static void b_l475e_iot01a_machine_init(MachineClass *mc) +static void bl475e_machine_init(ObjectClass *oc, void *data) { + MachineClass *mc = MACHINE_CLASS(oc); static const char *machine_valid_cpu_types[] = { ARM_CPU_TYPE_NAME("cortex-m4"), NULL }; mc->desc = "B-L475E-IOT01A Discovery Kit (Cortex-M4)"; - mc->init = b_l475e_iot01a_init; + mc->init = bl475e_init; mc->valid_cpu_types = machine_valid_cpu_types; /* SRAM pre-allocated as part of the SoC instantiation */ mc->default_ram_size = 0; } -DEFINE_MACHINE("b-l475e-iot01a", b_l475e_iot01a_machine_init) +static const TypeInfo bl475e_machine_type[] = { + { + .name = TYPE_B_L475E_IOT01A, + .parent = TYPE_MACHINE, + .instance_size = sizeof(Bl475eMachineState), + .class_init = bl475e_machine_init, + } +}; + +DEFINE_TYPES(bl475e_machine_type) From patchwork Tue Apr 30 16:48:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 793343 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:54f:b0:34d:5089:5a9e with SMTP id b15csp366217wrf; Tue, 30 Apr 2024 09:50:43 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWa5FPCySZqC0qpqfczLz1yGXzSmweyfwKJifWuCbLU3zmuw6VNQk43DdQUooCaIdPcaJj0OPRZ9xsf9f/KovX7 X-Google-Smtp-Source: AGHT+IEUUYcrvNkTmdTEVdMwAyd8x+L7vwJUh/P1suO1m5Svi1Cu3S7qDyAcjiR4H13OdLD5cR7/ X-Received: by 2002:a05:620a:5708:b0:790:efc7:9f8f with SMTP id wi8-20020a05620a570800b00790efc79f8fmr7636055qkn.18.1714495842946; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/21] hw/arm : Connect DM163 to B-L475E-IOT01A Date: Tue, 30 Apr 2024 17:48:41 +0100 Message-Id: <20240430164842.4074734-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Inès Varhol Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240424200929.240921-5-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell --- hw/arm/b-l475e-iot01a.c | 59 +++++++++++++++++++++++++++++++++++++++-- hw/arm/Kconfig | 1 + 2 files changed, 58 insertions(+), 2 deletions(-) diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c index 970c637ce61..5002a40f06d 100644 --- a/hw/arm/b-l475e-iot01a.c +++ b/hw/arm/b-l475e-iot01a.c @@ -27,10 +27,37 @@ #include "hw/boards.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" -#include "hw/arm/stm32l4x5_soc.h" #include "hw/arm/boot.h" +#include "hw/core/split-irq.h" +#include "hw/arm/stm32l4x5_soc.h" +#include "hw/gpio/stm32l4x5_gpio.h" +#include "hw/display/dm163.h" -/* B-L475E-IOT01A implementation is derived from netduinoplus2 */ +/* B-L475E-IOT01A implementation is inspired from netduinoplus2 and arduino */ + +/* + * There are actually 14 input pins in the DM163 device. + * Here the DM163 input pin EN isn't connected to the STM32L4x5 + * GPIOs as the IM120417002 colors shield doesn't actually use + * this pin to drive the RGB matrix. + */ +#define NUM_DM163_INPUTS 13 + +static const unsigned dm163_input[NUM_DM163_INPUTS] = { + 1 * GPIO_NUM_PINS + 2, /* ROW0 PB2 */ + 0 * GPIO_NUM_PINS + 15, /* ROW1 PA15 */ + 0 * GPIO_NUM_PINS + 2, /* ROW2 PA2 */ + 0 * GPIO_NUM_PINS + 7, /* ROW3 PA7 */ + 0 * GPIO_NUM_PINS + 6, /* ROW4 PA6 */ + 0 * GPIO_NUM_PINS + 5, /* ROW5 PA5 */ + 1 * GPIO_NUM_PINS + 0, /* ROW6 PB0 */ + 0 * GPIO_NUM_PINS + 3, /* ROW7 PA3 */ + 0 * GPIO_NUM_PINS + 4, /* SIN (SDA) PA4 */ + 1 * GPIO_NUM_PINS + 1, /* DCK (SCK) PB1 */ + 2 * GPIO_NUM_PINS + 3, /* RST_B (RST) PC3 */ + 2 * GPIO_NUM_PINS + 4, /* LAT_B (LAT) PC4 */ + 2 * GPIO_NUM_PINS + 5, /* SELBK (SB) PC5 */ +}; #define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a") OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A) @@ -39,12 +66,16 @@ typedef struct Bl475eMachineState { MachineState parent_obj; Stm32l4x5SocState soc; + SplitIRQ gpio_splitters[NUM_DM163_INPUTS]; + DM163State dm163; } Bl475eMachineState; static void bl475e_init(MachineState *machine) { Bl475eMachineState *s = B_L475E_IOT01A(machine); const Stm32l4x5SocClass *sc; + DeviceState *dev, *gpio_out_splitter; + unsigned gpio, pin; object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_STM32L4X5XG_SOC); @@ -53,6 +84,30 @@ static void bl475e_init(MachineState *machine) sc = STM32L4X5_SOC_GET_CLASS(&s->soc); armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0, sc->flash_size); + + if (object_class_by_name(TYPE_DM163)) { + object_initialize_child(OBJECT(machine), "dm163", + &s->dm163, TYPE_DM163); + dev = DEVICE(&s->dm163); + qdev_realize(dev, NULL, &error_abort); + + for (unsigned i = 0; i < NUM_DM163_INPUTS; i++) { + object_initialize_child(OBJECT(machine), "gpio-out-splitters[*]", + &s->gpio_splitters[i], TYPE_SPLIT_IRQ); + gpio_out_splitter = DEVICE(&s->gpio_splitters[i]); + qdev_prop_set_uint32(gpio_out_splitter, "num-lines", 2); + qdev_realize(gpio_out_splitter, NULL, &error_fatal); + + qdev_connect_gpio_out(gpio_out_splitter, 0, + qdev_get_gpio_in(DEVICE(&s->soc), dm163_input[i])); + qdev_connect_gpio_out(gpio_out_splitter, 1, + qdev_get_gpio_in(dev, i)); + gpio = dm163_input[i] / GPIO_NUM_PINS; + pin = dm163_input[i] % GPIO_NUM_PINS; + qdev_connect_gpio_out(DEVICE(&s->soc.gpio[gpio]), pin, + qdev_get_gpio_in(DEVICE(gpio_out_splitter), 0)); + } + } } static void bl475e_machine_init(ObjectClass *oc, void *data) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e8b6e5e5ebc..fe1f9643bd9 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -468,6 +468,7 @@ config B_L475E_IOT01A default y depends on TCG && ARM select STM32L4X5_SOC + imply DM163 config STM32L4X5_SOC bool From patchwork Tue Apr 30 16:48:42 2024 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b6-20020a05600c4e0600b0041be3383a2fsm12920384wmq.19.2024.04.30.09.48.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 09:48:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/21] tests/qtest : Add testcase for DM163 Date: Tue, 30 Apr 2024 17:48:42 +0100 Message-Id: <20240430164842.4074734-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430164842.4074734-1-peter.maydell@linaro.org> References: <20240430164842.4074734-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Inès Varhol `test_dm163_bank()` Checks that the pin "sout" of the DM163 led driver outputs the values received on pin "sin" with the expected latency (depending on the bank). `test_dm163_gpio_connection()` Check that changes to relevant STM32L4x5 GPIO pins are propagated to the DM163 device. Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Acked-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240424200929.240921-6-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell --- tests/qtest/dm163-test.c | 194 +++++++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 2 + 2 files changed, 196 insertions(+) create mode 100644 tests/qtest/dm163-test.c diff --git a/tests/qtest/dm163-test.c b/tests/qtest/dm163-test.c new file mode 100644 index 00000000000..3161c9208d8 --- /dev/null +++ b/tests/qtest/dm163-test.c @@ -0,0 +1,194 @@ +/* + * QTest testcase for DM163 + * + * Copyright (C) 2024 Samuel Tardieu + * Copyright (C) 2024 Arnaud Minier + * Copyright (C) 2024 Inès Varhol + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest.h" + +enum DM163_INPUTS { + SIN = 8, + DCK = 9, + RST_B = 10, + LAT_B = 11, + SELBK = 12, + EN_B = 13 +}; + +#define DEVICE_NAME "/machine/dm163" +#define GPIO_OUT(name, value) qtest_set_irq_in(qts, DEVICE_NAME, NULL, name, \ + value) +#define GPIO_PULSE(name) \ + do { \ + GPIO_OUT(name, 1); \ + GPIO_OUT(name, 0); \ + } while (0) + + +static void rise_gpio_pin_dck(QTestState *qts) +{ + /* Configure output mode for pin PB1 */ + qtest_writel(qts, 0x48000400, 0xFFFFFEB7); + /* Write 1 in ODR for PB1 */ + qtest_writel(qts, 0x48000414, 0x00000002); +} + +static void lower_gpio_pin_dck(QTestState *qts) +{ + /* Configure output mode for pin PB1 */ + qtest_writel(qts, 0x48000400, 0xFFFFFEB7); + /* Write 0 in ODR for PB1 */ + qtest_writel(qts, 0x48000414, 0x00000000); +} + +static void rise_gpio_pin_selbk(QTestState *qts) +{ + /* Configure output mode for pin PC5 */ + qtest_writel(qts, 0x48000800, 0xFFFFF7FF); + /* Write 1 in ODR for PC5 */ + qtest_writel(qts, 0x48000814, 0x00000020); +} + +static void lower_gpio_pin_selbk(QTestState *qts) +{ + /* Configure output mode for pin PC5 */ + qtest_writel(qts, 0x48000800, 0xFFFFF7FF); + /* Write 0 in ODR for PC5 */ + qtest_writel(qts, 0x48000814, 0x00000000); +} + +static void rise_gpio_pin_lat_b(QTestState *qts) +{ + /* Configure output mode for pin PC4 */ + qtest_writel(qts, 0x48000800, 0xFFFFFDFF); + /* Write 1 in ODR for PC4 */ + qtest_writel(qts, 0x48000814, 0x00000010); +} + +static void lower_gpio_pin_lat_b(QTestState *qts) +{ + /* Configure output mode for pin PC4 */ + qtest_writel(qts, 0x48000800, 0xFFFFFDFF); + /* Write 0 in ODR for PC4 */ + qtest_writel(qts, 0x48000814, 0x00000000); +} + +static void rise_gpio_pin_rst_b(QTestState *qts) +{ + /* Configure output mode for pin PC3 */ + qtest_writel(qts, 0x48000800, 0xFFFFFF7F); + /* Write 1 in ODR for PC3 */ + qtest_writel(qts, 0x48000814, 0x00000008); +} + +static void lower_gpio_pin_rst_b(QTestState *qts) +{ + /* Configure output mode for pin PC3 */ + qtest_writel(qts, 0x48000800, 0xFFFFFF7F); + /* Write 0 in ODR for PC3 */ + qtest_writel(qts, 0x48000814, 0x00000000); +} + +static void rise_gpio_pin_sin(QTestState *qts) +{ + /* Configure output mode for pin PA4 */ + qtest_writel(qts, 0x48000000, 0xFFFFFDFF); + /* Write 1 in ODR for PA4 */ + qtest_writel(qts, 0x48000014, 0x00000010); +} + +static void lower_gpio_pin_sin(QTestState *qts) +{ + /* Configure output mode for pin PA4 */ + qtest_writel(qts, 0x48000000, 0xFFFFFDFF); + /* Write 0 in ODR for PA4 */ + qtest_writel(qts, 0x48000014, 0x00000000); +} + +static void test_dm163_bank(const void *opaque) +{ + const unsigned bank = (uintptr_t) opaque; + const int width = bank ? 192 : 144; + + QTestState *qts = qtest_initf("-M b-l475e-iot01a"); + qtest_irq_intercept_out_named(qts, DEVICE_NAME, "sout"); + GPIO_OUT(RST_B, 1); + GPIO_OUT(EN_B, 0); + GPIO_OUT(DCK, 0); + GPIO_OUT(SELBK, bank); + GPIO_OUT(LAT_B, 1); + + /* Fill bank with zeroes */ + GPIO_OUT(SIN, 0); + for (int i = 0; i < width; i++) { + GPIO_PULSE(DCK); + } + /* Fill bank with ones, check that we get the previous zeroes */ + GPIO_OUT(SIN, 1); + for (int i = 0; i < width; i++) { + GPIO_PULSE(DCK); + g_assert(!qtest_get_irq(qts, 0)); + } + + /* Pulse one more bit in the bank, check that we get a one */ + GPIO_PULSE(DCK); + g_assert(qtest_get_irq(qts, 0)); + + qtest_quit(qts); +} + +static void test_dm163_gpio_connection(void) +{ + QTestState *qts = qtest_init("-M b-l475e-iot01a"); + qtest_irq_intercept_in(qts, DEVICE_NAME); + + g_assert_false(qtest_get_irq(qts, SIN)); + g_assert_false(qtest_get_irq(qts, DCK)); + g_assert_false(qtest_get_irq(qts, RST_B)); + g_assert_false(qtest_get_irq(qts, LAT_B)); + g_assert_false(qtest_get_irq(qts, SELBK)); + + rise_gpio_pin_dck(qts); + g_assert_true(qtest_get_irq(qts, DCK)); + lower_gpio_pin_dck(qts); + g_assert_false(qtest_get_irq(qts, DCK)); + + rise_gpio_pin_lat_b(qts); + g_assert_true(qtest_get_irq(qts, LAT_B)); + lower_gpio_pin_lat_b(qts); + g_assert_false(qtest_get_irq(qts, LAT_B)); + + rise_gpio_pin_selbk(qts); + g_assert_true(qtest_get_irq(qts, SELBK)); + lower_gpio_pin_selbk(qts); + g_assert_false(qtest_get_irq(qts, SELBK)); + + rise_gpio_pin_rst_b(qts); + g_assert_true(qtest_get_irq(qts, RST_B)); + lower_gpio_pin_rst_b(qts); + g_assert_false(qtest_get_irq(qts, RST_B)); + + rise_gpio_pin_sin(qts); + g_assert_true(qtest_get_irq(qts, SIN)); + lower_gpio_pin_sin(qts); + g_assert_false(qtest_get_irq(qts, SIN)); + + g_assert_false(qtest_get_irq(qts, DCK)); + g_assert_false(qtest_get_irq(qts, LAT_B)); + g_assert_false(qtest_get_irq(qts, SELBK)); + g_assert_false(qtest_get_irq(qts, RST_B)); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + qtest_add_data_func("/dm163/bank0", (void *)0, test_dm163_bank); + qtest_add_data_func("/dm163/bank1", (void *)1, test_dm163_bank); + qtest_add_func("/dm163/gpio_connection", test_dm163_gpio_connection); + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index b128fa5a4bd..6f2f594aceb 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -224,6 +224,8 @@ qtests_arm = \ (config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : []) + \ (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') ? qtests_stm32l4x5 : []) + \ (config_all_devices.has_key('CONFIG_FSI_APB2OPB_ASPEED') ? ['aspeed_fsi-test'] : []) + \ + (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') and + config_all_devices.has_key('CONFIG_DM163')? ['dm163-test'] : []) + \ ['arm-cpu-features', 'boot-serial-test']