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([178.197.223.16]) by smtp.gmail.com with ESMTPSA id bd13-20020a05600c1f0d00b0041c012ca327sm9048194wmb.45.2024.05.04.05.06.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 May 2024 05:06:27 -0700 (PDT) From: Krzysztof Kozlowski To: Michael Turquette , Stephen Boyd Cc: Krzysztof Kozlowski , Chanwoo Choi , linux-clk@vger.kernel.org, Sylwester Nawrocki , Alim Akhtar , Peter Griffin , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [GIT PULL] clk: samsung: drivers for v6.10 Date: Sat, 4 May 2024 14:06:22 +0200 Message-ID: <20240504120624.6574-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The following changes since commit 4cece764965020c22cff7665b18a012006359095: Linux 6.9-rc1 (2024-03-24 14:10:05 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-clk-6.10 for you to fetch changes up to 6b32d7474e9b833dc7fadc1b4d4f08af9bd87fde: clk: samsung: gs101: mark some apm UASC and XIU clocks critical (2024-05-03 10:34:34 +0200) ---------------------------------------------------------------- Samsung SoC clock drivers changes for 6.10 1. Allow choice of manual or firmware-driven control over PLLs, needed to fully implement CPU clock controllers on Exynos850. 2. Correct PLL clock IDs on ExynosAutov9. 3. Google GS101: - Propagate certain clock rates to allow setting proper SPI clock rates. - Add HSI0 and HSI2 clock controllers. - Mark certain clocks critical. 4. Convert old S3C64xx clock controller bindings to DT schema. ---------------------------------------------------------------- André Draszik (3): dt-bindings: clock: google,gs101-clock: add HSI0 clock management unit clk: samsung: gs101: add support for cmu_hsi0 clk: samsung: gs101: mark some apm UASC and XIU clocks critical Jaewon Kim (1): clk: samsung: exynosautov9: fix wrong pll clock id value Krzysztof Kozlowski (2): dt-bindings: clock: samsung,s3c6400-clock: convert to DT Schema Merge branch 'for-v6.10/clk-gs101-bindings' into next/clk Peter Griffin (2): dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit clk: samsung: gs101: add support for cmu_hsi2 Sam Protsenko (2): clk: samsung: Implement manual PLL control for ARM64 SoCs clk: samsung: exynos850: Add CMU_CPUCL0 and CMU_CPUCL1 Tudor Ambarus (2): clk: samsung: gs101: propagate PERIC0 USI SPI clock rate clk: samsung: gs101: propagate PERIC1 USI SPI clock rate .../bindings/clock/google,gs101-clock.yaml | 55 +- .../bindings/clock/samsung,s3c6400-clock.yaml | 57 + .../bindings/clock/samsung,s3c64xx-clock.txt | 76 -- drivers/clk/samsung/clk-exynos-arm64.c | 56 +- drivers/clk/samsung/clk-exynos850.c | 440 ++++++- drivers/clk/samsung/clk-exynosautov9.c | 8 +- drivers/clk/samsung/clk-gs101.c | 1207 ++++++++++++++++++-- drivers/clk/samsung/clk.h | 15 +- include/dt-bindings/clock/google,gs101.h | 116 ++ 9 files changed, 1822 insertions(+), 208 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/samsung,s3c6400-clock.yaml delete mode 100644 Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt