From patchwork Thu May 9 16:26:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 795919 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC73A16F90B for ; Thu, 9 May 2024 16:27:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715272049; cv=none; b=ala5NNpIVhkxIQEl0VvPUYZqUdXKhErAHtgnznuZcjDGfSfA7TsPjJTHoHLDcMrHhGarYwQ9RoXmFa+JK27CW3Rcu46Jyzga3l9K6K560Pk7MujsqgzwJtb5aDVn0kOOjRNmlDBKKEdp6Z/Y6+WVKa12JcOq8rxbkoZe4B5deuM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715272049; c=relaxed/simple; bh=txdYUVokTSzAJWgps5DIN7AP0OOCMWGT5bqowv6DVAA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=N35un3U7szU/unOhgKEsYj8/Uz0LftVLzmpLqq9R+XlENHlXN+XaaNDu7TjMyQ2GA6oUjs1ZEFAb7PveNvXPmT9rW1hpKbpYn4KVxE8RpJ5xHj32E228rf4uEAQjjMbiOEb+8TticJWS3Am7fLAKc/dFM50KGyhSYGoTC0dOsCM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=En9K9tMx; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="En9K9tMx" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-1ee38966529so15744125ad.1 for ; Thu, 09 May 2024 09:27:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1715272046; x=1715876846; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=F/faDAFpSR0nEREgruz48ieW2Rr4UgJ9rT3PHGQFx6A=; b=En9K9tMxV+BgA5qJDmFpFJMxYnWGmi242mUodDISytkRNITJhg/nH9oEsEDmlWsZer OV8/bEj3mJ6PFHe1ZjSwa6Nh+g4lVmm+iOy5LYOUpTRPoX+y4cPfcSLCV+6hTewRVcYV tkQNEdk0bOZEZKPLZ/AHpBXIBvNjybM71JouBhaRrAO4Ht2Fgv/O1FX0bW9uHpNLWQsW AjsVIZuJ7wg/jgKdxMI8euB+Cl9680NYOu8Q1mT5/k/rVLh4lcYGHf7NrcBxoX6JTpw/ /5Pyvz917i9S/MuZIbqZHVfZSeMIEeDzxAGpT83zeI9EM9uBM3+8Pze//UstNaeVEXEQ i/ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715272046; x=1715876846; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F/faDAFpSR0nEREgruz48ieW2Rr4UgJ9rT3PHGQFx6A=; b=blv16mOCMXNrL5Nec0/udZtsOTQXocg1h+A63gkQOuU96iuFOuTI7guZWFbPZJ32bU K6Z9UwQJ8gAZ8xcv0e5CRP3RaifZ0u7zOHXklWHV7lE5x00oLbQhNLPhrEofjYqrsXzm c+DO2bNHAZaBMe+glfVYYexWSzoGbn3SbESUdzwOWgHxaMzlzxKEQVx3sMUWh28ou1sz YbEnHaJQ/M94nRYLtL+5nCEfCifqxgL+09BO9fgzl6schzJszMj3+WArNTExDkp+yTR8 rvc0oYTJVyMZXmYXpKIcfgrukiX/NBJDYw7Cn0rsoG4vnx6ryjEGBWI6HmXil1EaLSJi gnWQ== X-Forwarded-Encrypted: i=1; AJvYcCUzL7Yn1jQwQzLXlBfmYTCZ7jRoCYV5tDpFREafA7be0xSZCjOueJrYMt/w+8X+6ZtPyfe43SePMEhM1cJpMJOhYol535EAgP9HHJOPCnxA X-Gm-Message-State: AOJu0YzrPLCNVBgToFzJd7MicP91hTRW4VwMcZVlBILLwdAbztCF1Mfz rhLYiqNPkUA/q3XIMDybqI6omncpg/UgYbG0/XctiKtcjLyJxVzdjEBZ838pioE= X-Google-Smtp-Source: AGHT+IHRJN0hklVkmHeffKwUUkj9zkJwCxFOEPyg5vihbQBuEXUImJTw4YLdpfC/uaaO6wRigNHbew== X-Received: by 2002:a17:902:e74f:b0:1eb:7162:82c7 with SMTP id d9443c01a7336-1ef42f74f9amr2694775ad.18.1715272046337; Thu, 09 May 2024 09:27:26 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0c13805asm16210285ad.264.2024.05.09.09.27.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 09:27:26 -0700 (PDT) From: Andy Chiu Date: Fri, 10 May 2024 00:26:51 +0800 Subject: [PATCH v5 1/8] riscv: vector: add a comment when calling riscv_setup_vsize() Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240510-zve-detection-v5-1-0711bdd26c12@sifive.com> References: <20240510-zve-detection-v5-0-0711bdd26c12@sifive.com> In-Reply-To: <20240510-zve-detection-v5-0-0711bdd26c12@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Heiko Stuebner , Andy Chiu , Guo Ren , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Vincent Chen , Greentime Hu , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org X-Mailer: b4 0.13-dev-a684c The function would fail when it detects the calling hart's vlen doesn't match the first one's. The boot hart is the first hart calling this function during riscv_fill_hwcap, so it is impossible to fail here. Add a comment about this behavior. Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley --- Changelog v2, v5: - update the comment (Conor) --- arch/riscv/kernel/cpufeature.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3ed2359eae35..15ffda1968d8 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -683,6 +683,9 @@ void __init riscv_fill_hwcap(void) } if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + /* + * This cannot fail when called on the boot hart + */ riscv_v_setup_vsize(); /* * ISA string in device tree might have 'v' flag, but From patchwork Thu May 9 16:26:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 796708 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35EBE17084F for ; Thu, 9 May 2024 16:27:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715272052; cv=none; b=tEpO+lGyMB0ZbEvDr0qQWwo+E7P9Y+b8JrS+7KhcEkQ1JswT3rnjUo+d5yS2jOf7Piut3J/E4ja8mFks52CerDOdsRtg4lHqohceIjhk1FQURadCrg6r7LNZEKYGEw6XnMzw9oliYmqJlPVKub1s1T06vOZYI2kc3y9ninCJyPQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715272052; c=relaxed/simple; bh=j77Tw75idPqnKN46bj9iqg1hk2k8cqdua4UmgD7kwl8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NL63J/w3k7sS3K24YlYHDKUosJuF/VFi3IsxJCJcxiKRELM6ZTFHjDYXdoCdcgm8MqSodUvNvZqTmvjaKsnygRzaekT2Cv52/r+rzt8l2GnKz01Bs4I5TTAMNvsv8AyKcVZj/FK7PXiLEkcuKRwf/UVP5AYwU1wBpCDzLgKeWxw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=l9+fwEGr; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="l9+fwEGr" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-1edc696df2bso8501615ad.0 for ; Thu, 09 May 2024 09:27:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1715272050; x=1715876850; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=xsGZj+6+RwBmlu/KXoHPz6YMlsBFjDj3jnnuVWHIhdk=; b=l9+fwEGrZxbJroim7VJZfIEUiQJdKsmrbfmw2qEYCUXgoERrwgd4doU3URaW8qevGq 5qY7hF8x25/GX8e0srVmPbOHcE27NblQ5gX1xOazAR2ATLThlBK9pdEtYj3NaDn7lhAh eTULG5KrwcHpKOre6melkYigK5ml+l33a5cBo+Ewja+miDuWu8FbSoi2Ii02jX3cImLF Z7tppiJQ5me1kjWP9CNojvR+TFBJg2Q2XGuo8YgOCmdMF8K+UxoiAso32MyxkJXLPylz JcMJOvfdnoG6gr77822ZAugQSPnYJhOe5amHr+bYV02+NQD9uQIL/zIB+F+/dTEEx6jm cr+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715272050; x=1715876850; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xsGZj+6+RwBmlu/KXoHPz6YMlsBFjDj3jnnuVWHIhdk=; b=kW9pjV7FvooLgJpDKjP1QRaj79Cb7k4juFTR6Msd0MxvH42xiGAsPtBaFxhotcjMw2 Ba30sVUZqE03PNPvjp4FAbTx4qewMvbWaRmG/1xZ5EsoN6ON/2ygahuTMmwS4f8qQqED 55E/XXWFB9k35UkEUXoP5uWRkwkYtKegS3V104L8BA23zqa2SZl6OdZev23CHJh5YFLp aiJicXYd9tMjSIPcSQuxYREd3DyPL0Xu5iY8TqbI3fcnak1VK5UNliHnB7SipGQx02ta eMrXlEp13hxwkNHjMup3kjFDbGK7WjkyZ0SXiRovI+kwG4PoS6AIFYsWZULvFy5blgkF dRJw== X-Forwarded-Encrypted: i=1; AJvYcCV67BZISjtPwcUe0h9XTlZBaayE0mmc7BEyB/+jP3uov/kRTAuqpHci8THjSqlHiyx0UVH9HT3MqFHJsB7Yx7cfOo39VIgBF/5UuI2YUzCi X-Gm-Message-State: AOJu0YzfLDy6T5YUgXT9/GnlpmEzHrySn/+GdW/s6dE0C19kDDgrK01F /uOFZk9AzciBstTVbkMOQ4CiT9tjMcdm7OT2BIXlwn0396g8R1JTm08X5XpXrG8= X-Google-Smtp-Source: AGHT+IHfn6hT/473i2wtO2K43xZtY/ybBEPEsMcrOoIPQowXqA7gpNfiBN0DjkayLmip8ShtXDqthA== X-Received: by 2002:a17:902:e541:b0:1eb:1af8:309f with SMTP id d9443c01a7336-1ef43d13820mr1827245ad.4.1715272050172; Thu, 09 May 2024 09:27:30 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0c13805asm16210285ad.264.2024.05.09.09.27.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 09:27:29 -0700 (PDT) From: Andy Chiu Date: Fri, 10 May 2024 00:26:52 +0800 Subject: [PATCH v5 2/8] riscv: smp: fail booting up smp if inconsistent vlen is detected Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240510-zve-detection-v5-2-0711bdd26c12@sifive.com> References: <20240510-zve-detection-v5-0-0711bdd26c12@sifive.com> In-Reply-To: <20240510-zve-detection-v5-0-0711bdd26c12@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Heiko Stuebner , Andy Chiu , Guo Ren , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Vincent Chen , Greentime Hu , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Yunhui Cui X-Mailer: b4 0.13-dev-a684c Currently we only support Vector for SMP platforms, that is, all SMP cores have the same vlenb. If we happen to detect a mismatching vlen, it is better to just fail bootting it up to prevent further race/scheduling issues. Also, move .Lsecondary_park forward and chage `tail smp_callin` into a regular call in the early assembly. So a core would be parked right after a return from smp_callin. Note that a successful smp_callin does not return. Fixes: 7017858eb2d7 ("riscv: Introduce riscv_v_vsize to record size of Vector context") Reported-by: Conor Dooley Closes: https://lore.kernel.org/linux-riscv/20240228-vicinity-cornstalk-4b8eb5fe5730@spud/ Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley Reviewed-by: Yunhui Cui --- Changelog v4: - update comment also in the assembly code (Yunhui) Changelog v2: - update commit message to explain asm code change (Conor) --- arch/riscv/kernel/head.S | 19 ++++++++++++------- arch/riscv/kernel/smpboot.c | 14 +++++++++----- 2 files changed, 21 insertions(+), 12 deletions(-) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 4236a69c35cb..a00f7523cb91 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -165,9 +165,20 @@ secondary_start_sbi: #endif call .Lsetup_trap_vector scs_load_current - tail smp_callin + call smp_callin #endif /* CONFIG_SMP */ +.align 2 +.Lsecondary_park: + /* + * Park this hart if we: + * - have too many harts on CONFIG_RISCV_BOOT_SPINWAIT + * - receive an early trap, before setup_trap_vector finished + * - fail in smp_callin(), as a successful one wouldn't return + */ + wfi + j .Lsecondary_park + .align 2 .Lsetup_trap_vector: /* Set trap vector to exception handler */ @@ -181,12 +192,6 @@ secondary_start_sbi: csrw CSR_SCRATCH, zero ret -.align 2 -.Lsecondary_park: - /* We lack SMP support or have too many harts, so park this hart */ - wfi - j .Lsecondary_park - SYM_CODE_END(_start) SYM_CODE_START(_start_kernel) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index d41090fc3203..673437ccc13d 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -214,6 +214,15 @@ asmlinkage __visible void smp_callin(void) struct mm_struct *mm = &init_mm; unsigned int curr_cpuid = smp_processor_id(); + if (has_vector()) { + /* + * Return as early as possible so the hart with a mismatching + * vlen won't boot. + */ + if (riscv_v_setup_vsize()) + return; + } + /* All kernel threads share the same mm context. */ mmgrab(mm); current->active_mm = mm; @@ -226,11 +235,6 @@ asmlinkage __visible void smp_callin(void) numa_add_cpu(curr_cpuid); set_cpu_online(curr_cpuid, 1); - if (has_vector()) { - if (riscv_v_setup_vsize()) - elf_hwcap &= ~COMPAT_HWCAP_ISA_V; - } - riscv_user_isa_enable(); /* From patchwork Thu May 9 16:26:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 795918 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78AC517085A for ; Thu, 9 May 2024 16:27:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715272056; cv=none; b=iFcbcWu1/xMQ+fsR3I1H9aVfyOoAqofAT0otnhSEvEbU7BqSiPz/4EH/Y4TtnnsW5y5N8pNSspaCvaeaGLhPErer+2EXxVt+4rU9LBtHGreg+am5pvdyhkmxw9srd5F/BSMhI1/WveG53voEBEV9E8CMufqhOoKN8DTGG+qSIhc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715272056; c=relaxed/simple; bh=bRdldBcR63JhBiYgvb0j6aaFVJpCttTWpBzzpwiAVFE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EccjEUvfhtXgoXYBTdyr/vWMOIUAvK17FF4ewAhmImbpVcvueYILt9E1v4PO1+3tExdg7V+kOzspOaq3su0dqSBE+jHoK6CqdXzRLQPNBryy//jiFLm5StDhH4PfHjzCLc7JCGwQx2CXvcjV6SQN6Zzl212wp8J/5/aRtbDsVD0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=GBmug3Rs; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="GBmug3Rs" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-1ec41d82b8bso9230275ad.2 for ; Thu, 09 May 2024 09:27:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1715272054; x=1715876854; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hrVtT3wUj2Ro2LlZ8rt/5kKYI6Cl/lb7mj3BLkp83qk=; b=GBmug3RsgN9C0pFjOHp1E1ldNsaVhtGlliA2BfHmjYkdiVq/lEEELtsvx5+iFKM+U/ xeqJZ3oL2xd+VofCUTUUO5oodWTLppmjoGRHSiuyyLgtRfqXxxsmQXC8f1AQi7Pt+DEb TYaLDubHtT+qJmVmsnvtHKjpNJY//QAmcycSh3shA/rUXcQuO+fe0QPnIIA8oltesOjM FLVGikc8DCEBIDDtuYfwr4+b1VdnXih0X+JynU1JOBKZOZZrGDoAxCRrc5OGCqykj/ng c/rLlHkwDF9H34PzPAa0MP7Qmtmg+B5MLSRnZwGoAXHXdBgEg+Lp83+PGNpebDIGnOYW JiHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715272054; x=1715876854; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hrVtT3wUj2Ro2LlZ8rt/5kKYI6Cl/lb7mj3BLkp83qk=; b=voMyvVyLvZdqDvdRrKmbgxCvoE7sVlh75ZLBK0hJlOIYmtprBLfmptQ4p/22tGfeMq M7wGnszxmGECTtRosUgvPq30qX4a+89Cg5A5mLL3w/EyBQYxnmU0KlEWIj3JfSe5gKKM KnmKCu87hU1Zdhf+75llvIOpy6b3DMsjFvD7c8MKFqzAZ1PJ+uBj+H5As9f0nWVfM29y cN1Gx6A9copM8IJS6cJD65B4s4ObBt3hWs2OoOtTbuiukvcI7u+wvJz+KRjV5U3+46YL /x2ZMtkoDdqAgf3+mnTgVbDeA/1kWs2ThRMD6G42hPRM2rGxAyY/CzL9rL7NQwDgehzc FmyA== X-Forwarded-Encrypted: i=1; AJvYcCW8ZQUgrbtjPx8yBRSOGyUAxAM9ynBe2LUF3ztded892ESe2vg+8fjOmkSmLudmT4GjXkJB2iQIQ+5UHeeJ1vcOTrf0+Nncc1oRY0sRYkge X-Gm-Message-State: AOJu0Yw+hkvLxXQUj6IcHe2d+oy2E9kklGkXv2yndtjMxblCR2y3YsUq sI155K6EL0QfvNhMwXwr80C8AVM8A7v/KTsBVVyjQwk4SMU0Idk+Z48JjEOlbOY= X-Google-Smtp-Source: AGHT+IF8PgRVZZ0FHnW63FE7rtPOWp30TN+TCPvlMDVR+j+74ajw2NLtOZVqw2pXCxjO30nvabMrkw== X-Received: by 2002:a17:902:c3c5:b0:1ec:e3c2:790e with SMTP id d9443c01a7336-1ef43d2967cmr1810595ad.19.1715272053741; Thu, 09 May 2024 09:27:33 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0c13805asm16210285ad.264.2024.05.09.09.27.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 09:27:33 -0700 (PDT) From: Andy Chiu Date: Fri, 10 May 2024 00:26:53 +0800 Subject: [PATCH v5 3/8] riscv: cpufeature: call match_isa_ext() for single-letter extensions Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240510-zve-detection-v5-3-0711bdd26c12@sifive.com> References: <20240510-zve-detection-v5-0-0711bdd26c12@sifive.com> In-Reply-To: <20240510-zve-detection-v5-0-0711bdd26c12@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Heiko Stuebner , Andy Chiu , Guo Ren , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Vincent Chen , Greentime Hu , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org X-Mailer: b4 0.13-dev-a684c Single-letter extensions may also imply multiple subextensions. For example, Vector extension implies zve64d, and zve64d implies zve64f. Extension parsing for "riscv,isa-extensions" has the ability to resolve the dependency by calling match_isa_ext(). This patch makes deprecated parser call the same function for single letter extensions. Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley --- Changelog v3: - Remove set_bit for single-letter extensions as they are all checked in match_isa_ext. (Clément) --- arch/riscv/kernel/cpufeature.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 15ffda1968d8..4bfc13209938 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -468,16 +468,15 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc if (unlikely(ext_err)) continue; + + for (int i = 0; i < riscv_isa_ext_count; i++) + match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo); + if (!ext_long) { int nr = tolower(*ext) - 'a'; - if (riscv_isa_extension_check(nr)) { + if (riscv_isa_extension_check(nr)) *this_hwcap |= isa2hwcap[nr]; - set_bit(nr, isainfo->isa); - } - } else { - for (int i = 0; i < riscv_isa_ext_count; i++) - match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo); } } } From patchwork Thu May 9 16:26:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 796707 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26E601708A4 for ; Thu, 9 May 2024 16:27:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715272059; cv=none; b=oag/VW4fRJLEJ+dsxZvhOtiaB+iv2OdjW9QHASvn66MtmIG24y+46JFEqMqcNjKPhFfS94INzfmuc6GsRd4NhNdWmfeOye/9qpenedqj/QEdIZRTRwoAU0aoOABfUnvjvF/NeJeZNae7QQo5JHngVEc3jzNO9EbDRqoylrjYiRM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715272059; c=relaxed/simple; bh=h9e60qU951Qvm2FC7p6XzmI4LIb1DbNk3veMfbQk7y4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iLGg+qkIczfaKeFra9bcSVqVBdom0fWBiXee6hvgU0OzmQUQbMLmuptf+4CQGiXqTKMuDfu07HO2AQM8fORjJl+zHtklh6E5s08CBwQp3jqODX8vugwLtfSz/QJS6gQt9z8GwVJUtsoPFWIywVAYF+uIi56EMsomVGfuvoy1ZeQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=Cst79pxW; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="Cst79pxW" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-1e50a04c317so5837805ad.1 for ; Thu, 09 May 2024 09:27:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1715272057; x=1715876857; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=jlKJTA+y4FZTs32pZYAJnhXlsU7CxhYFnIn7J/LCVc0=; b=Cst79pxWu/gQhJd1uXEapfQXn3XSi7IS4eVFvLGiPkPVtf6VOuvr/EE5DoFUxY4MN5 UrPcyAvBF+Tj9hcDEB/efeMpNpsjpuc5XCifdKoQ66Aydp4qvnIcO5Jm03LDdhafyLlb k8euHAmrI17GpKcuTdF5eBQWdE7UO7Md+IM5OSbZ/IttepaODSBvfkoNIl1jst7TXR3w dwQ3UgiQvSCCBQP289ToC3QtCI1lK6M1sJoh/sfHVwmJMtIVB7kQbrGtzAnqhjjR3Ehl ik3JZrFULotwcawp9mfSB3KM+N+u6wBKWYk5QpUao2IFs090AQrFv6gu/5LNjNN+Y0y1 TMSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715272057; x=1715876857; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jlKJTA+y4FZTs32pZYAJnhXlsU7CxhYFnIn7J/LCVc0=; b=mUIdb0MwSRmjEqeINdgctU5S24p6VzozYJllYn2IgHtRiXU4swH/C00E/TANVU0whX 9BGPTGIfPWXAr8zw8vng4zDKIpYbD9/Q34uoo8WcrKmq4C8j9SA0agc+1exHXD/awBgg OaPeahiKuxVTgIHuLoMgh7PUUjHTuWXxVAOLtXM1x8s7HPwlaJOzrdekBoB0vPRNldLl S/o2llk+3Xt2qVUQKu5M8JP0SQJHLaePfa7juBIF8kL2DB8C7Edd9rQlR6l4THN4qstD AowGrfcq4YkncCPev8ln6ovif/IoZXPFsP4xWVTj0E/B7gGpZ3g+VQzjlNUdJo1I50xO nNIQ== X-Forwarded-Encrypted: i=1; AJvYcCUL5XPU7c0rfJW0zGEDU6MNMqiq0gbJXsk5Tr5R7k6vuPpK+4KbUnDDr7rk63RQqumei/xwzfm83wWYKcuo7xZfQSBJ0HeF9a/2z/XFHBFa X-Gm-Message-State: AOJu0YyriFphmwkAPiO2UThK+gJlT0i5+QMHftUDrmngj93bAzOjKzUi G2tBgFQYk4H1O6vYeSEteWaHK7ql0OKmD83wPW0SyBLa405b5CHILavfDqWF9ZQ= X-Google-Smtp-Source: AGHT+IEszGbwB/vNXrttRGOidBoOwpuhaJiBy+bYw1u/tAahtS9W1vF9JRL7sPHMpNOzMB5IXCQqvg== X-Received: by 2002:a17:902:c086:b0:1e4:8c64:33a2 with SMTP id d9443c01a7336-1ef44059be4mr1058755ad.68.1715272057380; Thu, 09 May 2024 09:27:37 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0c13805asm16210285ad.264.2024.05.09.09.27.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 09:27:37 -0700 (PDT) From: Andy Chiu Date: Fri, 10 May 2024 00:26:54 +0800 Subject: [PATCH v5 4/8] dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240510-zve-detection-v5-4-0711bdd26c12@sifive.com> References: <20240510-zve-detection-v5-0-0711bdd26c12@sifive.com> In-Reply-To: <20240510-zve-detection-v5-0-0711bdd26c12@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Heiko Stuebner , Andy Chiu , Guo Ren , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Vincent Chen , Greentime Hu , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org X-Mailer: b4 0.13-dev-a684c Add description for Zve32x Zve32f Zve64x Zve64f Zve64d ISA extensions. Signed-off-by: Andy Chiu Acked-by: Conor Dooley --- Changelog v5: - Reorder this patch prior than the first patch that uses them. (Conor) Changelog v3: - Correct extension names and their order (Stefan) Changelog v2: - new patch since v2 --- .../devicetree/bindings/riscv/extensions.yaml | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 468c646247aa..cfed80ad5540 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -381,6 +381,36 @@ properties: instructions, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + - const: zve32f + description: + The standard Zve32f extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve32x + description: + The standard Zve32x extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve64d + description: + The standard Zve64d extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve64f + description: + The standard Zve64f extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve64x + description: + The standard Zve64x extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + - const: zvfh description: The standard Zvfh extension for vectored half-precision From patchwork Thu May 9 16:26:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 795917 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0B4F171088 for ; Thu, 9 May 2024 16:27:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715272063; cv=none; b=BYZ9712MCRcXroN9e4W2ihfjXau44ulhwsVxnzA5Ty2c1nqrusSZuLRC6blxZE90kmBB16D/ox4jULBykZIqXeWRw1rcxJGHvgWUDd3FOS0t+Cwa8pLMj+1H3+ceW9cf+mq4xNkq67YThyZbuBoFoVAIvpNDGlY6kLbBO9FvOXU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715272063; c=relaxed/simple; bh=knlwHNZwQmzD4oaulGiVep3QJpqnscPRswiG7/j0Dgg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bLvIMK4GHab5SaytJepkYvnheqF5+gnebwAQ0XeaOZsNx3Sf+daTWB0I8jfc/PN+bv4v42Qc2ssaUvwWbUvkg6WoGDZwpjIwREjw+rro9B1LFu8ALIC7xaEek+eysleNu06zt8hOIKEZIWrJ+eGqCszCEuqadr19jnKpd7hoiKU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=TLNZYiA3; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="TLNZYiA3" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-1ec486198b6so8471485ad.1 for ; Thu, 09 May 2024 09:27:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1715272061; x=1715876861; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=XNkHbY9oNilft+2PQdFQmYDad5FfREv7NAdRkMrTsLg=; b=TLNZYiA3a0ybPAS0ODahejZjLGgR9pMJciNoI2O02C2K16sRcIIk/aPgJ3qFowyr+c nSBKcxiQ7KDEH83XLlhWmBCt51TfAkiDqiigZgUTK5serA1X+AoOd/hGAbYIUf3n/RvO Kn9uy8GDkWhBoubbWr0iHxUqUTnpyRMpo7ZEoS01hFIjsuiA8BzWKzvhKdFtYhPdB3Bc ZglhiNeYtC3jB6HpwOg0dIvIGCjCeipL5hwBF7Ifu50Scu7WdtqlZ3H0C2/ioXD7npUF THiqsTh1c997d3aWqs0THjB53JjKn5aCt+J9u1fbZd/qDYxrubvfxWoiiVZ1KEGjwqI6 jyaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715272061; x=1715876861; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XNkHbY9oNilft+2PQdFQmYDad5FfREv7NAdRkMrTsLg=; b=YLF2XG/PYUtklNj+JIevE7ltwr+K33AJAUmAkXJCGtWdqiI60R6w6Uj4YEHfAtv3nq OTKDbhF1OwxeThdbRPectFDHctuuXe9B2PbMlM/rBzldtyQiMHLuisjbGnTmiBCrPMr4 9/lSPtIRQsMD3jEEw1rKqB1MTQ0qkFj8TnsmwjjX8DLmtLwtfLVv0sz+sL84PVAbLweA v903/bhza8JCy+w4yj20Fnyhi6F01f1X+XaNDv7iGWvztlz44Z34cp6LqqCUxdPWcwdF e7MJqQpq823tnA2tYCYWWWtIvjeVoEG5e95qd+wCopenkHT47ZzZVrUoe1mSIz1tPJP0 XP1w== X-Forwarded-Encrypted: i=1; AJvYcCVYUOUEL1EkTR1SJTVMgjO/cVDCGRBIPOydKjeevCFv0tiSPkyZz6eWCT2jrJzWEuYgnlSQ4LDBi7kMb9v5F+ueQxyE3wyid04Iu04rr09n X-Gm-Message-State: AOJu0YwcyHi5D9hBwl8x9UoLRY5KnajcYRBpfgsfljsz0L6mUbtWDCIh esMRNhf77bnd9RS2mTX5l0LdQQ57e7ChTdbmIaU92JQ5y5gX0qyHVY7LNJy6W+8= X-Google-Smtp-Source: AGHT+IGUu1uPaO5nrqJvbHdXDLkvUWrWrbX5e2xStsjIzWenVBJGkFP5i2uTWH7PLE8vnnAsdqvMPA== X-Received: by 2002:a17:903:110f:b0:1ea:b125:81a2 with SMTP id d9443c01a7336-1ef44161e50mr1676745ad.53.1715272061063; Thu, 09 May 2024 09:27:41 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0c13805asm16210285ad.264.2024.05.09.09.27.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 09:27:40 -0700 (PDT) From: Andy Chiu Date: Fri, 10 May 2024 00:26:55 +0800 Subject: [PATCH v5 5/8] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240510-zve-detection-v5-5-0711bdd26c12@sifive.com> References: <20240510-zve-detection-v5-0-0711bdd26c12@sifive.com> In-Reply-To: <20240510-zve-detection-v5-0-0711bdd26c12@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Heiko Stuebner , Andy Chiu , Guo Ren , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Vincent Chen , Greentime Hu , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org X-Mailer: b4 0.13-dev-a684c Multiple Vector subextensions are added. Also, the patch takes care of the dependencies of Vector subextensions by macro expansions. So, if some "embedded" platform only reports "zve64f" on the ISA string, the parser is able to expand it to zve32x zve32f zve64x and zve64f. Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley --- Changelog v5: - Remove ZVE32F_IMPLY_LIST as ZVE32F only implies ZVE32X (Conor) - Add a list for V as it the imply list for ZVE64D does not include ZVE64D. Changelog v3: - renumber RISCV_ISA_EXT_ZVE* to rebase on top of 6.9 - alphabetically sort added extensions (Clément) Changelog v2: - remove the extension itself from its isa_exts[] list (Clément) - use riscv_zve64d_exts for v's extension list (Samuel) --- arch/riscv/include/asm/hwcap.h | 5 +++++ arch/riscv/kernel/cpufeature.c | 41 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 45 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e17d0078a651..f64d4e98e67c 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,11 @@ #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 +#define RISCV_ISA_EXT_ZVE32X 75 +#define RISCV_ISA_EXT_ZVE32F 76 +#define RISCV_ISA_EXT_ZVE64X 77 +#define RISCV_ISA_EXT_ZVE64F 78 +#define RISCV_ISA_EXT_ZVE64D 79 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 4bfc13209938..ad3e613ee30f 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -188,6 +188,40 @@ static const unsigned int riscv_zvbb_exts[] = { RISCV_ISA_EXT_ZVKB }; +#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST \ + RISCV_ISA_EXT_ZVE64X, \ + RISCV_ISA_EXT_ZVE32F, \ + RISCV_ISA_EXT_ZVE32X + +#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST \ + RISCV_ISA_EXT_ZVE64F, \ + RISCV_ISA_EXT_ZVE64F_IMPLY_LIST + +#define RISCV_ISA_EXT_V_IMPLY_LIST \ + RISCV_ISA_EXT_ZVE64D, \ + RISCV_ISA_EXT_ZVE64D_IMPLY_LIST + +static const unsigned int riscv_zve32f_exts[] = { + RISCV_ISA_EXT_ZVE32X +}; + +static const unsigned int riscv_zve64f_exts[] = { + RISCV_ISA_EXT_ZVE64F_IMPLY_LIST +}; + +static const unsigned int riscv_zve64d_exts[] = { + RISCV_ISA_EXT_ZVE64D_IMPLY_LIST +}; + +static const unsigned int riscv_v_exts[] = { + RISCV_ISA_EXT_V_IMPLY_LIST +}; + +static const unsigned int riscv_zve64x_exts[] = { + RISCV_ISA_EXT_ZVE32X, + RISCV_ISA_EXT_ZVE64X +}; + /* * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V * privileged ISA, the existence of the CSRs is implied by any extension which @@ -245,7 +279,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c), - __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v), + __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts), __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), __RISCV_ISA_EXT_SUPERSET(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts), __RISCV_ISA_EXT_SUPERSET(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts), @@ -280,6 +314,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO), __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts), __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), + __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts), + __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X), + __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts), + __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts), + __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts), __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), From patchwork Thu May 9 16:26:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 796706 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7476017109B for ; Thu, 9 May 2024 16:27:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715272067; cv=none; b=Ks44esySbIqUgTPYH6Jyb3WokmBB+S1cu58RssqzCbS3EENuYduJpBCnTKmMrrpRDq142T+b+ZA20NhtGsNf8M2w5OCHrnUUG/H76TTojh844Ya1hVgZ5MRdkZcr91wmYKL62AUz1VlRjGeeFc3xd80EZ71sJdLWrG2ZiXKA+Xs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715272067; c=relaxed/simple; bh=d+mYI6dxJIL04rhk4/n1dO8Ggk9e997Ohv38lDy0jX4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BvIaVft/+hvmdh92b6GQyEbnWOBKV0DAxRcWhHEEcJtmPetPevpEoDRdlggqFaTCjXnxTSYdmPI2U2n2rRkY2ezsGfieiK1XdmstJL+wYHDPHBra3CLtFZxpDqhz0fYlcck5tDi4lGk+ECezLOdsj4IuLuNfLaCzxQrboeQbdKM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=bQBAA0Gr; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="bQBAA0Gr" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-1ec4b2400b6so9533655ad.3 for ; Thu, 09 May 2024 09:27:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1715272065; x=1715876865; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gS0Jn2CNRETSxII8vxmdki1qJ+zipNSMB0uxD87mL7s=; b=bQBAA0Grvo0z+XwYjwzlQTRZHYD7MWnYzgFMDrylVER0VkgTN0EosniISsqOPYdmdq u0XnCbMYvSTG0XQlbKAnpaXT/H+P/aSaYQ/pFE7BhAjgsNRNWC5/iDxm3WhFIW4IwluS 7ElYIIUtnpZK/rWjxZ8Mub1KIMBO+5VEt+P8/COLfi59NahyfPFvxiMpyY06pFtqJUZX kZRVQW4PNJrSy7UKvdknU1VTjNCX7YQEFpQEog6gC1l6bPpimEXTr0Gm+l/VxaOdy5TR iibg6SOhgrZMtJPzqCpsf2hcRQhhM2oosq4ZeDBtTjfL+hRIHccyIQNhpcndms02L7V9 Dzmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715272065; x=1715876865; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gS0Jn2CNRETSxII8vxmdki1qJ+zipNSMB0uxD87mL7s=; b=Zgki8dLOydKdVxSLx0rwBE+IZhFhxM7FsTDB27bEtdr/Jhr85lBZaENrccw8mbUtH5 sHtNVki9IVtN51xRtEttBkNF4fhge13RX4kFyAdAiQQ/MfecMAygOlXr8mVJLThK3VjJ WPf5CwH2qWP1+9BLCTSQumqGNzR4nhxyouwW6lNnAsHHFTM0ovm/YMEXtAQnLPimsJEp lcLPLkE/AvJnMRHybEH3yhHSBaze0UeJiWyyt1yjURm+//FccLgj6yw2dResXUOMuM7o aRctob+EUIjMNTHy5w4RnHW31L+cHw3ztqjQgQPfw5yFFonktrV27ZOEoevVQLYCXSaL rGag== X-Forwarded-Encrypted: i=1; AJvYcCUOWUBc/B0ZMgq08TcgDL8MHx3wN9FpqPOZlaKrTVQUfhf2Leo4GgAXmI8tl2LXAHnk5/DPkTBMRDSZxWHBIAQQos5pwfWxNUVJ7ywR+7Pc X-Gm-Message-State: AOJu0YxwwXMyr/mXFsHEVFQnYG2qC6Zr/+N37tXj/mYiJz+2HZiU00SY 9+FxSWBvJFIayeUBFtw0NP+SLwEqgwTZl5CkPKKpMu4Zz6FOz6G40IzUdq2TGDM= X-Google-Smtp-Source: AGHT+IEcfNG5b+WnhP899fciFO7zYJT6fjTvSFp0///eZQlXzATxkTOr3r8djPCFfhzo/MtEAYsIKQ== X-Received: by 2002:a17:902:ea10:b0:1ea:2753:2b9f with SMTP id d9443c01a7336-1ef43d15560mr1959745ad.20.1715272064666; Thu, 09 May 2024 09:27:44 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0c13805asm16210285ad.264.2024.05.09.09.27.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 09:27:44 -0700 (PDT) From: Andy Chiu Date: Fri, 10 May 2024 00:26:56 +0800 Subject: [PATCH v5 6/8] riscv: hwprobe: add zve Vector subextensions into hwprobe interface Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240510-zve-detection-v5-6-0711bdd26c12@sifive.com> References: <20240510-zve-detection-v5-0-0711bdd26c12@sifive.com> In-Reply-To: <20240510-zve-detection-v5-0-0711bdd26c12@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Heiko Stuebner , Andy Chiu , Guo Ren , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Vincent Chen , Greentime Hu , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org X-Mailer: b4 0.13-dev-a684c The following Vector subextensions for "embedded" platforms are added into RISCV_HWPROBE_KEY_IMA_EXT_0: - ZVE32X - ZVE32F - ZVE64X - ZVE64F - ZVE64D Extensions ending with an X indicates that the platform doesn't have a vector FPU. Extensions ending with F/D mean that whether single (F) or double (D) precision vector operation is supported. The number 32 or 64 follows from ZVE tells the maximum element length. Signed-off-by: Andy Chiu Reviewed-by: Clément Léger --- Changelog v5: - Rebase thus add ZVE32X after RISCV_HWPROBE_EXT_ZICOND. Changelog v2: - zve* extensions in hwprobe depends on whether kernel supports v, so include them after has_vector(). Fix a typo. (Clément) --- Documentation/arch/riscv/hwprobe.rst | 15 +++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 5 +++++ arch/riscv/kernel/sys_hwprobe.c | 5 +++++ 3 files changed, 25 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 204cd4433af5..fc015b452ebf 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -192,6 +192,21 @@ The following keys are defined: supported as defined in the RISC-V ISA manual starting from commit d8ab5c78c207 ("Zihintpause is ratified"). + * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 31c570cbd1c5..6593aedb9d2b 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -60,6 +60,11 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) #define RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36) +#define RISCV_HWPROBE_EXT_ZVE32X (1ULL << 37) +#define RISCV_HWPROBE_EXT_ZVE32F (1ULL << 38) +#define RISCV_HWPROBE_EXT_ZVE64X (1ULL << 39) +#define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 40) +#define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 41) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index 969ef3d59dbe..35390b4a5a17 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -114,6 +114,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZIHINTPAUSE); if (has_vector()) { + EXT_KEY(ZVE32X); + EXT_KEY(ZVE32F); + EXT_KEY(ZVE64X); + EXT_KEY(ZVE64F); + EXT_KEY(ZVE64D); EXT_KEY(ZVBB); EXT_KEY(ZVBC); EXT_KEY(ZVKB); From patchwork Thu May 9 16:26:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 795916 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35690170844 for ; Thu, 9 May 2024 16:27:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715272071; cv=none; b=udKxm+xFnFhMWHaT4p6lBFuGNYMN+LG0tP6VW0jXxYq3/k9hGFsQWq3HvM/mYfwRVjvS67HFWDhTq2QhXxUIaB92QwWUMHH6H4ket89C4xeND8ZSC0+jp8/UwjRQniCiv37Dr9wbv971y+Yai0oUieD9qxFaNLNpd31QwAIOJ/M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715272071; c=relaxed/simple; bh=UA+sAfg7J53AaOM6Ue2Iy8Wh+lRWAucEd6oSKKm9RZo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ok7AMFHl9i8EQ9cj/aLAPUOkipFso62fAznqtzFeGaDFpEdCLJ8ymtKNStFgASXfLTkFuCLC0/IHenPfmD8Tnnn3wDVAuHFSVERkvKDA+rXecKCKGT7n7iKLC5wf1zi9avetaYeFdN1vVcFURaMt3nrEPfw3QsOoEmvVRE6y9GU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=AfQ3C+da; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="AfQ3C+da" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-1e9ffd3f96eso9075895ad.3 for ; Thu, 09 May 2024 09:27:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1715272068; x=1715876868; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1QNNwCwa8ku9/k6tpLOmcrT1B9BtNzaXfpTEHBEwtaA=; b=AfQ3C+dajL7pr/ynLdVlVUex0Lzk19OKwO4bxAmMwR7668gspZZD2qfqzPtQBr5wgE 1t9RPdQfarE+8Y32IZ4/QwG4btOLcBkEndm8cIRKf/3aCXGcdVv68GpscwVyaHlgvXcN zHhKi9OwQYEW+xVl1yZR1NBpSboIGB/WjYuLnEOFOQOQ6FJU8t5UpCdfCJVU3A+SCw3R fhw5T4SpfMxf1Y2BIRqMhc7Z15CUef1g2v3Ilt4VxkOLLhgtFnYz0jiXjgtgjIUdkMUm 90lolNbtzFyXJwcUFQJVDo8JotPoVpfBt1DDqeMWqf0dd+uX6T0Y+Snv+35lDTJzZ3Qv H+yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715272068; x=1715876868; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1QNNwCwa8ku9/k6tpLOmcrT1B9BtNzaXfpTEHBEwtaA=; b=WazWyYhgnLo+dnC66c8+zdKhzVnENBlkXomirZkc/mtwwKYZ+mbaIHqmCe890cF1hr Th+xc/uRU5DA2VZeAcM1dS+iHGfZBkC7TIfcXDp9uECF+qVPCLX8fsWlMUc4LVkfH4I6 20rOPXmTt6aSYw+iv4g1kkm3OX2+IvRywITRDIHRvZW9a6tuZnF/vSpxfJxK4jyPcKmU gs3EWUGOnS0IjXYCIs7VmtPchwgeCyJHZa2KWZreUJES3DRrq4l3qjj/VxCu5At6HF5g AloS1UX9GzojVn7AS6NvXLrxhk7Yuih0iS9IU8saS9rN1st19c829tIDaARjJ44su0i6 6iBw== X-Forwarded-Encrypted: i=1; AJvYcCXzPbKccLTTDrR8ZdQ8KFr4EfGqXvjb9pNG+9bg1KVwdAx37RzlGA0TR3ZFoi10XR3005cQv7OAX/izUicmk/KyH8Hzx+i6tZpoT2cXZr3y X-Gm-Message-State: AOJu0YzaVeWssDvw8HVh3JtvopjPo6x385cYx0/EuHMEwgV/lsmgKByO Uo8ukCWoL1IyAix6Tp6QLfdVp9Qs7bz3Kgb/9B1hGSQAjAuUI6MLHDqlqOvgWKQ= X-Google-Smtp-Source: AGHT+IF9YLscVKA/v48suhgFjgLq2LEgwRZmAvKPOqejEXCSJdkMF5M4ISIIbOi/4lCzoWr9myCmQQ== X-Received: by 2002:a17:903:228f:b0:1ed:36dc:a570 with SMTP id d9443c01a7336-1ef44050742mr1707285ad.49.1715272068499; Thu, 09 May 2024 09:27:48 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0c13805asm16210285ad.264.2024.05.09.09.27.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 09:27:48 -0700 (PDT) From: Andy Chiu Date: Fri, 10 May 2024 00:26:57 +0800 Subject: [PATCH v5 7/8] riscv: vector: adjust minimum Vector requirement to ZVE32X Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240510-zve-detection-v5-7-0711bdd26c12@sifive.com> References: <20240510-zve-detection-v5-0-0711bdd26c12@sifive.com> In-Reply-To: <20240510-zve-detection-v5-0-0711bdd26c12@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Heiko Stuebner , Andy Chiu , Guo Ren , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Vincent Chen , Greentime Hu , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Joel Granados X-Mailer: b4 0.13-dev-a684c Make has_vector() to check for ZVE32X. Every in-kernel usage of V that requires a more complicate version of V must then call out explicitly. Also, change riscv_v_first_use_handler(), and boot code that calls riscv_v_setup_vsize() to accept ZVE32X. Most kernel/user interfaces requires minimum of ZVE32X. Thus, programs compiled and run with ZVE32X should be supported by the kernel on most aspects. This includes context-switch, signal, ptrace, prctl, and hwprobe. One exception is that ELF_HWCAP returns 'V' only if full V is supported on the platform. This means that the system without a full V must not rely on ELF_HWCAP to tell whether it is allowable to execute Vector without first invoking a prctl() check. Signed-off-by: Andy Chiu Acked-by: Joel Granados --- Changelog v5: - Remove the paramerter from has_vector()'s prototype. Instead, make it check for ZVE32X only. Everything else should make additional alternative checks. (Conor) Changelog v4: - check static_assert for !CONFIG_RISCV_ISA_V case in has_vector. Changelog v2: - update the comment in hwprobe. --- arch/riscv/include/asm/vector.h | 10 +++++----- arch/riscv/kernel/cpufeature.c | 5 ++++- arch/riscv/kernel/sys_hwprobe.c | 6 +++++- arch/riscv/kernel/vector.c | 5 ++++- arch/riscv/lib/uaccess.S | 2 +- 5 files changed, 19 insertions(+), 9 deletions(-) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 731dcd0ed4de..be7d309cca8a 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -37,7 +37,7 @@ static inline u32 riscv_v_flags(void) static __always_inline bool has_vector(void) { - return riscv_has_extension_unlikely(RISCV_ISA_EXT_v); + return riscv_has_extension_unlikely(RISCV_ISA_EXT_ZVE32X); } static inline void __riscv_v_vstate_clean(struct pt_regs *regs) @@ -91,7 +91,7 @@ static __always_inline void __vstate_csr_restore(struct __riscv_v_ext_state *src { asm volatile ( ".option push\n\t" - ".option arch, +v\n\t" + ".option arch, +zve32x\n\t" "vsetvl x0, %2, %1\n\t" ".option pop\n\t" "csrw " __stringify(CSR_VSTART) ", %0\n\t" @@ -109,7 +109,7 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to, __vstate_csr_save(save_to); asm volatile ( ".option push\n\t" - ".option arch, +v\n\t" + ".option arch, +zve32x\n\t" "vsetvli %0, x0, e8, m8, ta, ma\n\t" "vse8.v v0, (%1)\n\t" "add %1, %1, %0\n\t" @@ -131,7 +131,7 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_ riscv_v_enable(); asm volatile ( ".option push\n\t" - ".option arch, +v\n\t" + ".option arch, +zve32x\n\t" "vsetvli %0, x0, e8, m8, ta, ma\n\t" "vle8.v v0, (%1)\n\t" "add %1, %1, %0\n\t" @@ -153,7 +153,7 @@ static inline void __riscv_v_vstate_discard(void) riscv_v_enable(); asm volatile ( ".option push\n\t" - ".option arch, +v\n\t" + ".option arch, +zve32x\n\t" "vsetvli %0, x0, e8, m8, ta, ma\n\t" "vmv.v.i v0, -1\n\t" "vmv.v.i v8, -1\n\t" diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index ad3e613ee30f..53be3365e302 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -720,11 +720,14 @@ void __init riscv_fill_hwcap(void) elf_hwcap &= ~COMPAT_HWCAP_ISA_F; } - if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X)) { /* * This cannot fail when called on the boot hart */ riscv_v_setup_vsize(); + } + + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { /* * ISA string in device tree might have 'v' flag, but * CONFIG_RISCV_ISA_V is disabled in kernel. diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index 35390b4a5a17..83fcc939df67 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -69,7 +69,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, if (riscv_isa_extension_available(NULL, c)) pair->value |= RISCV_HWPROBE_IMA_C; - if (has_vector()) + if (has_vector() && riscv_isa_extension_available(NULL, v)) pair->value |= RISCV_HWPROBE_IMA_V; /* @@ -113,6 +113,10 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZICOND); EXT_KEY(ZIHINTPAUSE); + /* + * All the following extensions must depend on the kernel + * support of V. + */ if (has_vector()) { EXT_KEY(ZVE32X); EXT_KEY(ZVE32F); diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 6727d1d3b8f2..682b3feee451 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -173,8 +173,11 @@ bool riscv_v_first_use_handler(struct pt_regs *regs) u32 __user *epc = (u32 __user *)regs->epc; u32 insn = (u32)regs->badaddr; + if (!has_vector()) + return false; + /* Do not handle if V is not supported, or disabled */ - if (!(ELF_HWCAP & COMPAT_HWCAP_ISA_V)) + if (!riscv_v_vstate_ctrl_user_allowed()) return false; /* If V has been enabled then it is not the first-use trap */ diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S index bc22c078aba8..bbe143bb32a0 100644 --- a/arch/riscv/lib/uaccess.S +++ b/arch/riscv/lib/uaccess.S @@ -14,7 +14,7 @@ SYM_FUNC_START(__asm_copy_to_user) #ifdef CONFIG_RISCV_ISA_V - ALTERNATIVE("j fallback_scalar_usercopy", "nop", 0, RISCV_ISA_EXT_v, CONFIG_RISCV_ISA_V) + ALTERNATIVE("j fallback_scalar_usercopy", "nop", 0, RISCV_ISA_EXT_ZVE32X, CONFIG_RISCV_ISA_V) REG_L t0, riscv_v_usercopy_threshold bltu a2, t0, fallback_scalar_usercopy tail enter_vector_usercopy From patchwork Thu May 9 16:26:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 796705 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67EFB171E6A for ; Thu, 9 May 2024 16:27:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715272076; cv=none; b=Go9SnO0F2Khp6T/MgeQWxcZiwGkXaqfPPn26Q4cSGMqRRqrtKrCDLvJPkMP/af4FGzyPAkdKjqCwRwDrqIRYV/xE/wbiSyNdColoEVEfAIwQkHnjzZmzQ6EtAh1RmwKhBYr/rmkiH2hpBG3bxcFRytT9uab33/subF3L1P6IH+U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715272076; c=relaxed/simple; bh=HTwXq4dfdPMm84nIH+ARCZR286B+TcB5da8GClM6ty0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tJNycWYb6JXnxyvHM+G0AeiBZygKGfQGtdTShAxxABpV3ZveOaA+ZE9g9xKAVSlYsnd6WcgllbwVjBSRB/VUM0bipY925XzCrL581h368+Tm5BFnAwwu65IGBmDBnoS/pWq2MMHdKn1p7+0+cg+eMEqlK7rKhPjAkPrGQKMVI4I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=PkueXnTt; arc=none smtp.client-ip=209.85.214.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="PkueXnTt" Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-1ed012c1afbso9231155ad.1 for ; Thu, 09 May 2024 09:27:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1715272073; x=1715876873; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=v6E6ZusRhlxuRh8LTz85NPr0A8l1rMIJWkDOWsfceGk=; b=PkueXnTtm40OBoZIeBuLVdEIXpBbAURfIsmrhwk1q1lNml4u0vSdJixASTgFqkW35d nRFySHk+EfISxgffazee+bex3NptjMArrgRSITxcmOiyX97SwBMW31bfEltSL+VE4CHd RU+TGy3fMQHVhmDeTT6mxXjsg4i+e2IZctDgCLtKRwNZzSexxdn2EPmfD8+4R6Pm7rje vuObQvQt9kMSJfdeY3vUpbl1JpjNSsMDaLCK7S1MxUHa/7Aq/oLFk8IG41VmspxbejnF 2oBI0dTJyFtLOGB4vQh/pdyacLhytWyGNSRmmg9Yfwut71Av0e7a2N4WUKzOcR3Yuugv GgkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715272073; x=1715876873; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v6E6ZusRhlxuRh8LTz85NPr0A8l1rMIJWkDOWsfceGk=; b=HApEfgZymvyBz8dhVzoIaSS/JzkdCgeeOEnnoHzx7hh5pne8uLrFTOWeW+7QH29qvh Er9lQTiPMUXv3SCusIJzRq9ffTqZ/pDW88dHX0nOLmqmf27hms8Tf1aAD+VQ54UDQs4T rciyTo8nBdBHntzYHCJxnfjPtaJzwJn0DGn5hI+dnIKgymnp5Pfx641IePJ6a99/k6bq 4W/aywVNWkBgdSr9+d5VRjyYn6CmL3c0pwxDbfUbhYC+r3UWU317/GK0ppBu/QM3HK9N S53ZMszV7i98pSdDuDJtivAJWKRBpoRXTpzw4GcmCRimxuBA/JNhe6rzO1QfHFsK6Uxw 0VFg== X-Forwarded-Encrypted: i=1; AJvYcCXS2ozup1+D18tpWeop3ZXcYO/jmmrNVRX1J4VVQUqkKDGPf3M2QjdHYrCgifcgTNpJoEsXd/vTHipD6dUqR/o0AtDxIowlGUABAFJ6nG53 X-Gm-Message-State: AOJu0Ywoi6UCo4Z6nwx1KuigupbHGDN/ajlotDU6B0ZIwGYLT51CkkKv n1oXSvCtt8rsnyNlXqu9jFtHRLAgLRyjXus1Moe4n0STIx8RftsitdpPOsdRZwrIsF1xg3MPsCf g1sw= X-Google-Smtp-Source: AGHT+IHxBUHRPrw0FqUS+OM/NY9GyC13nGox9W5GwUl+ZolYupUN16LsN4HIr69L69inYwc5kfUyjg== X-Received: by 2002:a17:903:2301:b0:1e4:6253:2f15 with SMTP id d9443c01a7336-1ef42f74cfdmr2685595ad.16.1715272072597; Thu, 09 May 2024 09:27:52 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0c13805asm16210285ad.264.2024.05.09.09.27.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 09:27:51 -0700 (PDT) From: Andy Chiu Date: Fri, 10 May 2024 00:26:58 +0800 Subject: [PATCH v5 8/8] selftest: run vector prctl test for ZVE32X Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240510-zve-detection-v5-8-0711bdd26c12@sifive.com> References: <20240510-zve-detection-v5-0-0711bdd26c12@sifive.com> In-Reply-To: <20240510-zve-detection-v5-0-0711bdd26c12@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Heiko Stuebner , Andy Chiu , Guo Ren , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Vincent Chen , Greentime Hu , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org X-Mailer: b4 0.13-dev-a684c The minimal requirement for running Vector subextension on Linux is ZVE32X. So change the test accordingly to run prctl as long as it find it. Signed-off-by: Andy Chiu --- Changelog v4: - new patch since v4 --- tools/testing/selftests/riscv/vector/vstate_prctl.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/riscv/vector/vstate_prctl.c b/tools/testing/selftests/riscv/vector/vstate_prctl.c index 27668fb3b6d0..895177f6bf4c 100644 --- a/tools/testing/selftests/riscv/vector/vstate_prctl.c +++ b/tools/testing/selftests/riscv/vector/vstate_prctl.c @@ -88,16 +88,16 @@ int main(void) return -2; } - if (!(pair.value & RISCV_HWPROBE_IMA_V)) { + if (!(pair.value & RISCV_HWPROBE_EXT_ZVE32X)) { rc = prctl(PR_RISCV_V_GET_CONTROL); if (rc != -1 || errno != EINVAL) { - ksft_test_result_fail("GET_CONTROL should fail on kernel/hw without V\n"); + ksft_test_result_fail("GET_CONTROL should fail on kernel/hw without ZVE32X\n"); return -3; } rc = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); if (rc != -1 || errno != EINVAL) { - ksft_test_result_fail("GET_CONTROL should fail on kernel/hw without V\n"); + ksft_test_result_fail("SET_CONTROL should fail on kernel/hw without ZVE32X\n"); return -4; }