From patchwork Thu Oct 17 13:23:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 176646 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp967094ill; Thu, 17 Oct 2019 06:59:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqzPfq+1mJDa9dVSh+meiaZG3OdpMGJ6lYdZufBTknvmMLh9dF3d4rjF4z0F810KVsgECOKn X-Received: by 2002:a37:67cb:: with SMTP id b194mr3397764qkc.238.1571320776171; Thu, 17 Oct 2019 06:59:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571320776; cv=none; d=google.com; s=arc-20160816; b=OGwLjdX1Y/y2Y1fv9Dm8QBWrGJGkjoNXmcTt919EUGOoloBkxlbz6EiekA8dGJHrvy gtWE1LM1LuehhvvnsLkHYMkefBCsNSuNjqIyzJddkAtZm+KasbSbEqEBUaLhqEcH+8+y cl4uCtPFWAd9OnQBlhCzynn1/o+AQ4KHp2JzxWJsC+pa9cfjTivZEjOoxzNatsvc+eHn ndP0tgFSI/JDStywzJRY42Y31TzEs76HICdLiYy0myFhGSbij0saSA0ldHPdjmz9eAS6 YRyscFmmbBrOJv5U4gekl7rVYi2uq9qJGMTEdtp/x4ngu8QH23ClMgKLeeoubTJUmQLp 9Kcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=AoRIF8ofQDbeGLT/YF+4ga2y/BWkoNekd0m2fWT6Bak=; b=R/hcFGeSHzaHUZhonhIv3+YKrBUcPnLcLSvFZHS1ag6oqj1CDR0TLxHUWk+mqrUh86 um5kP4t+//4Otx44kqcI4nskDF9OnwbYFJMFTthzzQoDGwLJWtRnl20CnpQM+okNZXQl LcCvHnxAmjvJVtA1ciE9VjzAgF/qUUzAgTgYV2oUC+ZJ9RxE3Ce93bQEeVC8BYMctmqD fL0ltl3xGjhTRnv9jTZa86uQr2YQXkkO7DZP16eK/5PfPgGsgG7jFFneweWXlPU+96DB 90SPlCI+Z7qVYc6avAtdj4aKMifrv4x3no6oHjlWbJz0w6am+pdKn3zqAJ/8eUbZ1Ehw 5W5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DSdLYlYe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t17si2239107qve.135.2019.10.17.06.59.36 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 17 Oct 2019 06:59:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DSdLYlYe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48632 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iL6JT-0001G3-3Z for patch@linaro.org; Thu, 17 Oct 2019 09:59:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35256) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iL5l1-00009E-Pr for qemu-devel@nongnu.org; Thu, 17 Oct 2019 09:24:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iL5l0-0000wL-Jc for qemu-devel@nongnu.org; Thu, 17 Oct 2019 09:23:59 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:36741) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iL5kz-0000vv-JM for qemu-devel@nongnu.org; Thu, 17 Oct 2019 09:23:57 -0400 Received: by mail-wr1-x444.google.com with SMTP id w18so1784297wrt.3 for ; Thu, 17 Oct 2019 06:23:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AoRIF8ofQDbeGLT/YF+4ga2y/BWkoNekd0m2fWT6Bak=; b=DSdLYlYePYGsQ7d48WwCcj5p2pP0d4ZKLNjl6g/zqByUaw38CU+VB5GX12D/O63zzu fiEUVMFhf6PcNa6nVuBcDugHbpZiVt9vLL/eNztvM5dg8ykewfB9C2lTfqb8+qTIlNJv DYNwGSsJWTiLcjDlzUcqjsuXIJf2hD74vlxv0M7WRfC7AVTkSFulqv7VSkZMfKkEH3GE HyyW//m7ukXTnIzutQ7tFp///EBqev7swFmByG86jnJyk8Xk3MScijSu6uD2YCd7nhXW O2XIggX3Od0gwnmiTAHUX4uMpIDLJ46rLnJQDkt6vfVNeKQkjL8HDcxiRPBFkTrDr507 sxvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AoRIF8ofQDbeGLT/YF+4ga2y/BWkoNekd0m2fWT6Bak=; b=g0sJ5slTri6ZnnWSzVXEZcacttjTfn6V6miAQPNX/HyJDQOTovAMb1shoGTPYbsjRm wvwBYUWaxojU0hYw0xa62aF2r4yPfW7nNj3yOHts3cfGbIHagziLeyKarXM2f03JNykD d52+SAfnE0plG7fg9x7dai2VtYCfNIxwT+ooxOa2LA5qUafX2VQCguZtxAQzh25vSwmw u/+ZFZaSZ1e6O/5BVvrRqBuJLi6/paASvNF7LZ3CgzwO/50WtmxMreiWsNBsaIeOKYzA ZG4WUdkjKGNFlEFhCgc/oMkgtE93b2n12X2skr4kfltmdjiw7iPZAcbSReWzjLehrcqA nhMQ== X-Gm-Message-State: APjAAAV5FyVNDYz7tB/IgXGF2P3RVSjQeGfL4eQNFA9BWcL4B+XcyL3E cqZHzYyxOxlpHxjq5lWdgxtMZcHS3Ww4HQ== X-Received: by 2002:a5d:51c3:: with SMTP id n3mr3073602wrv.5.1571318635719; Thu, 17 Oct 2019 06:23:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm2270302wrp.26.2019.10.17.06.23.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 06:23:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 1/2] hw/timer/grlib_gptimer.c: Switch to transaction-based ptimer API Date: Thu, 17 Oct 2019 14:23:50 +0100 Message-Id: <20191017132351.4762-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191017132351.4762-1-peter.maydell@linaro.org> References: <20191017132351.4762-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: KONRAD Frederic , Mark Cave-Ayland , Fabien Chouteau Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the grlib_gptimer code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell --- hw/timer/grlib_gptimer.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c index bb09268ea14..7a9371c0e30 100644 --- a/hw/timer/grlib_gptimer.c +++ b/hw/timer/grlib_gptimer.c @@ -29,7 +29,6 @@ #include "hw/irq.h" #include "hw/ptimer.h" #include "hw/qdev-properties.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "trace.h" @@ -63,7 +62,6 @@ typedef struct GPTimer GPTimer; typedef struct GPTimerUnit GPTimerUnit; struct GPTimer { - QEMUBH *bh; struct ptimer_state *ptimer; qemu_irq irq; @@ -93,6 +91,17 @@ struct GPTimerUnit { uint32_t config; }; +static void grlib_gptimer_tx_begin(GPTimer *timer) +{ + ptimer_transaction_begin(timer->ptimer); +} + +static void grlib_gptimer_tx_commit(GPTimer *timer) +{ + ptimer_transaction_commit(timer->ptimer); +} + +/* Must be called within grlib_gptimer_tx_begin/commit block */ static void grlib_gptimer_enable(GPTimer *timer) { assert(timer != NULL); @@ -115,6 +124,7 @@ static void grlib_gptimer_enable(GPTimer *timer) ptimer_run(timer->ptimer, 1); } +/* Must be called within grlib_gptimer_tx_begin/commit block */ static void grlib_gptimer_restart(GPTimer *timer) { assert(timer != NULL); @@ -141,7 +151,9 @@ static void grlib_gptimer_set_scaler(GPTimerUnit *unit, uint32_t scaler) trace_grlib_gptimer_set_scaler(scaler, value); for (i = 0; i < unit->nr_timers; i++) { + ptimer_transaction_begin(unit->timers[i].ptimer); ptimer_set_freq(unit->timers[i].ptimer, value); + ptimer_transaction_commit(unit->timers[i].ptimer); } } @@ -266,8 +278,10 @@ static void grlib_gptimer_write(void *opaque, hwaddr addr, switch (timer_addr) { case COUNTER_OFFSET: trace_grlib_gptimer_writel(id, addr, value); + grlib_gptimer_tx_begin(&unit->timers[id]); unit->timers[id].counter = value; grlib_gptimer_enable(&unit->timers[id]); + grlib_gptimer_tx_commit(&unit->timers[id]); return; case COUNTER_RELOAD_OFFSET: @@ -291,6 +305,7 @@ static void grlib_gptimer_write(void *opaque, hwaddr addr, /* gptimer_restart calls gptimer_enable, so if "enable" and "load" bits are present, we just have to call restart. */ + grlib_gptimer_tx_begin(&unit->timers[id]); if (value & GPTIMER_LOAD) { grlib_gptimer_restart(&unit->timers[id]); } else if (value & GPTIMER_ENABLE) { @@ -301,6 +316,7 @@ static void grlib_gptimer_write(void *opaque, hwaddr addr, value &= ~(GPTIMER_LOAD & GPTIMER_DEBUG_HALT); unit->timers[id].config = value; + grlib_gptimer_tx_commit(&unit->timers[id]); return; default: @@ -344,9 +360,11 @@ static void grlib_gptimer_reset(DeviceState *d) timer->counter = 0; timer->reload = 0; timer->config = 0; + ptimer_transaction_begin(timer->ptimer); ptimer_stop(timer->ptimer); ptimer_set_count(timer->ptimer, 0); ptimer_set_freq(timer->ptimer, unit->freq_hz); + ptimer_transaction_commit(timer->ptimer); } } @@ -365,14 +383,16 @@ static void grlib_gptimer_realize(DeviceState *dev, Error **errp) GPTimer *timer = &unit->timers[i]; timer->unit = unit; - timer->bh = qemu_bh_new(grlib_gptimer_hit, timer); - timer->ptimer = ptimer_init_with_bh(timer->bh, PTIMER_POLICY_DEFAULT); + timer->ptimer = ptimer_init(grlib_gptimer_hit, timer, + PTIMER_POLICY_DEFAULT); timer->id = i; /* One IRQ line for each timer */ sysbus_init_irq(sbd, &timer->irq); + ptimer_transaction_begin(timer->ptimer); ptimer_set_freq(timer->ptimer, unit->freq_hz); + ptimer_transaction_commit(timer->ptimer); } memory_region_init_io(&unit->iomem, OBJECT(unit), &grlib_gptimer_ops, From patchwork Thu Oct 17 13:23:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 176632 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp955153ill; Thu, 17 Oct 2019 06:49:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqxMcTDz1hw+QM1zH5nzfM+CyI89Jeekui7ANq3Lh4oqu6hcXK33i+MlfvFN2BPhGwueRR0+ X-Received: by 2002:ad4:4bd1:: with SMTP id l17mr3788758qvw.58.1571320178730; Thu, 17 Oct 2019 06:49:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571320178; cv=none; d=google.com; s=arc-20160816; b=du4yaHNEmzzBMeR13J1ZKhRzzOZAyAmhR9Z1XoKExFDjjbW8cvilwfwvVVb2bbyltx /6TvxfaiFWXE3qU2yvaKQpUV1Sukiws1ZdDHOeEG4Z7eF0bGIZzEn+6OfUE2bbQR5p1x r+85F7cow3goqz9qiGX8COcu7BwN0Rr6efW+elPp3jDX7M5XzZS8nafXoFcI1w0dYjnL qyzrGWQGbycCGsUiCh/45ifaSbyEerGumZ+bVPu7AHBEhx7lb7MeztFN8N2bb4Ft0biR XFhrPeNGO+c0H3nbqQOBHrFKSFS9rAme/HLz5zUsbqMfVhhu1cbn7+d3vVYu2oCOQlER wacA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ubzqTky8oXQWHb54LycWqoQN2mw2t/0StAg0pETjdLY=; b=t6TDq7naxmgpTXMKLn0IHjbhivqYpTFE2yXDVlBAVbT3X9m6MrlQG4WnAn8VKTRd1S swnqu/ixJx+9ZbEe0nguLEP5+aAyRBtCDcnDnRSScIkmKWSeedgs67icE+mPX5NCgJZV AYRpMIcJmZlNMmJXz+oxZzYYCfzafu+WB53NFw2Zf1tZ8d8Ba01+E4z9rA0MTl6KThtx DfU9s6H8P3E4fJqi9iz6wKO0/9M63cAD84b4cLeevkvaP1YAxvpuzvBglrFwQK6o4J83 rWUVV6bqwrOBbzprcIDYcT4KLEjSP4ZSnnatN0cufRMQ4/EUSgdNJj/JvYuWOHAdyBWn e46A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZuyvpQ1h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a126si2075395qkd.243.2019.10.17.06.49.38 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 17 Oct 2019 06:49:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZuyvpQ1h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48352 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iL69p-0004nR-Ln for patch@linaro.org; Thu, 17 Oct 2019 09:49:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35263) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iL5l2-00009G-GU for qemu-devel@nongnu.org; Thu, 17 Oct 2019 09:24:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iL5l1-0000wT-8q for qemu-devel@nongnu.org; Thu, 17 Oct 2019 09:24:00 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:40169) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iL5l1-0000wB-2K for qemu-devel@nongnu.org; Thu, 17 Oct 2019 09:23:59 -0400 Received: by mail-wr1-x443.google.com with SMTP id o28so2338618wro.7 for ; Thu, 17 Oct 2019 06:23:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ubzqTky8oXQWHb54LycWqoQN2mw2t/0StAg0pETjdLY=; b=ZuyvpQ1hTrRZAMvlys+wfq5OXOBcOObZwbCwFYv0rkDnqE6Ntag9SCmiisciiJKqUT w0C7qAPuo3OiLPtBtI3eRn6xGIj7fD3OKqN2PnNRzPEgr6UX67f09lnG+PGLTHzKMdHA XlcxZGkidzGBycEALG0uixAkQyCBiFGs5nJAAt6fBTWlCwqSZlyY1WGvDErJgBlQ4BB+ WRRbaEr686VOUAGWHp3yuDV4NEAyHQRRzdUC68LQftybKm66el1tHwlNahNC0Y06kX2Z xUaizJx0CHo89yTjeJ/Q26VgNyvAZCyI39LsduZkdob38tEUxj1xqFgYu2mH/apxJaTC sOeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ubzqTky8oXQWHb54LycWqoQN2mw2t/0StAg0pETjdLY=; b=GJ4gq38t/Jq4d/kgKsjfkJyx33kQGclMkm6VH0vDB7/LYysg5mDVETvDmy46oc7d2D 3VBh4/oSR/dYxSh5AnSqH2QoKNHWybcsh1YyCVnez5C1BS5aXGSPpfylWdQ3kdPb4XQ3 eqaipd16ha7CyS9VK8c0+AsuyL4hGXRbbRucJNCfmOQoaRSfolul4Zqiwi4uJKksuXWw ILUZ051MffnCRcsOnKUnDFsM1egbyKX0/AAjHqKwE1rA+8uCdtLfRIkz2+N27MYAIbQJ 7EV1DxACPZP4zbupjCj7jRPWkB+01Dy2o39j0hWHuUQZsReDFJ6PxwD9QkRqH+DiqhE3 Hinw== X-Gm-Message-State: APjAAAWDM0aQv0pAWenrS34ls3DpfRiFDQRGguKyTtZmxOZ9pyVlCOMC zczoHd/QmM+I6FJKjrINNcI4DTyGpL/9Ag== X-Received: by 2002:adf:92a5:: with SMTP id 34mr2863485wrn.337.1571318637031; Thu, 17 Oct 2019 06:23:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id z9sm2270302wrp.26.2019.10.17.06.23.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 06:23:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 2/2] hw/timer/slavio_timer.c: Switch to transaction-based ptimer API Date: Thu, 17 Oct 2019 14:23:51 +0100 Message-Id: <20191017132351.4762-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191017132351.4762-1-peter.maydell@linaro.org> References: <20191017132351.4762-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: KONRAD Frederic , Mark Cave-Ayland , Fabien Chouteau Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the slavio_timer code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell --- hw/timer/slavio_timer.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/timer/slavio_timer.c b/hw/timer/slavio_timer.c index 692d213897d..0e2efe6fe89 100644 --- a/hw/timer/slavio_timer.c +++ b/hw/timer/slavio_timer.c @@ -30,7 +30,6 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "trace.h" -#include "qemu/main-loop.h" #include "qemu/module.h" /* @@ -213,6 +212,7 @@ static void slavio_timer_mem_writel(void *opaque, hwaddr addr, saddr = addr >> 2; switch (saddr) { case TIMER_LIMIT: + ptimer_transaction_begin(t->timer); if (slavio_timer_is_user(tc)) { uint64_t count; @@ -236,6 +236,7 @@ static void slavio_timer_mem_writel(void *opaque, hwaddr addr, } } } + ptimer_transaction_commit(t->timer); break; case TIMER_COUNTER: if (slavio_timer_is_user(tc)) { @@ -247,7 +248,9 @@ static void slavio_timer_mem_writel(void *opaque, hwaddr addr, t->reached = 0; count = ((uint64_t)t->counthigh) << 32 | t->count; trace_slavio_timer_mem_writel_limit(timer_index, count); + ptimer_transaction_begin(t->timer); ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); + ptimer_transaction_commit(t->timer); } else { trace_slavio_timer_mem_writel_counter_invalid(); } @@ -255,13 +258,16 @@ static void slavio_timer_mem_writel(void *opaque, hwaddr addr, case TIMER_COUNTER_NORST: // set limit without resetting counter t->limit = val & TIMER_MAX_COUNT32; + ptimer_transaction_begin(t->timer); if (t->limit == 0) { /* free-run */ ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0); } else { ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0); } + ptimer_transaction_commit(t->timer); break; case TIMER_STATUS: + ptimer_transaction_begin(t->timer); if (slavio_timer_is_user(tc)) { // start/stop user counter if (val & 1) { @@ -273,6 +279,7 @@ static void slavio_timer_mem_writel(void *opaque, hwaddr addr, } } t->run = val & 1; + ptimer_transaction_commit(t->timer); break; case TIMER_MODE: if (timer_index == 0) { @@ -282,6 +289,7 @@ static void slavio_timer_mem_writel(void *opaque, hwaddr addr, unsigned int processor = 1 << i; CPUTimerState *curr_timer = &s->cputimer[i + 1]; + ptimer_transaction_begin(curr_timer->timer); // check for a change in timer mode for this processor if ((val & processor) != (s->cputimer_mode & processor)) { if (val & processor) { // counter -> user timer @@ -308,6 +316,7 @@ static void slavio_timer_mem_writel(void *opaque, hwaddr addr, trace_slavio_timer_mem_writel_mode_counter(timer_index); } } + ptimer_transaction_commit(curr_timer->timer); } } else { trace_slavio_timer_mem_writel_mode_invalid(); @@ -367,10 +376,12 @@ static void slavio_timer_reset(DeviceState *d) curr_timer->count = 0; curr_timer->reached = 0; if (i <= s->num_cpus) { + ptimer_transaction_begin(curr_timer->timer); ptimer_set_limit(curr_timer->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); ptimer_run(curr_timer->timer, 0); curr_timer->run = 1; + ptimer_transaction_commit(curr_timer->timer); } } s->cputimer_mode = 0; @@ -380,7 +391,6 @@ static void slavio_timer_init(Object *obj) { SLAVIO_TIMERState *s = SLAVIO_TIMER(obj); SysBusDevice *dev = SYS_BUS_DEVICE(obj); - QEMUBH *bh; unsigned int i; TimerContext *tc; @@ -392,9 +402,11 @@ static void slavio_timer_init(Object *obj) tc->s = s; tc->timer_index = i; - bh = qemu_bh_new(slavio_timer_irq, tc); - s->cputimer[i].timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); + s->cputimer[i].timer = ptimer_init(slavio_timer_irq, tc, + PTIMER_POLICY_DEFAULT); + ptimer_transaction_begin(s->cputimer[i].timer); ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD); + ptimer_transaction_commit(s->cputimer[i].timer); size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE; snprintf(timer_name, sizeof(timer_name), "timer-%i", i);