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[209.51.188.17]) by mx.google.com with ESMTPS id z124si2038596qka.1.2019.10.17.07.03.28 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 17 Oct 2019 07:03:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lRqagTtB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48704 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iL6ND-0005uZ-5J for patch@linaro.org; Thu, 17 Oct 2019 10:03:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36115) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iL5q3-0006i3-81 for qemu-devel@nongnu.org; Thu, 17 Oct 2019 09:29:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iL5q2-0002Ya-0Q for qemu-devel@nongnu.org; Thu, 17 Oct 2019 09:29:11 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:54153) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iL5q1-0002YN-Qr for qemu-devel@nongnu.org; Thu, 17 Oct 2019 09:29:09 -0400 Received: by mail-wm1-x343.google.com with SMTP id i16so2577612wmd.3 for ; Thu, 17 Oct 2019 06:29:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e2Ij4RQysVJcdo+i7dvWapjtIXrPIwRATrfBcMlAk+I=; b=lRqagTtBFoxIc0/CA2ni0W+tWpGc03zj4lnjzYXwmZIFfPoTGUm8FFp06jsLNojK/Q yRHK6ku3OZbhF6slx4KWmzBUfV6nCybuJja64uhSI08wFFgdGbgJfJUZgPQEcsKmoIVf va+rqB4fve1TjOL5F4rvMJIupVfof+hbCd8f+5e8AR+bTuxrTvEv40+PsCO6efrMuOXC x+mLy5PsTShOIsGL8Iadq67hq9eU2UtFFzMknfEmbnQnPgQTcYqqiauxd+3g1glptDTy tPSXH+S6WpqeY26qx0mtGlKS36raKvz1fRYoapdAcrC/Rz+CyklEVuvdsEqBBdIMF6R3 daPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e2Ij4RQysVJcdo+i7dvWapjtIXrPIwRATrfBcMlAk+I=; b=ulijadOVMq12mu1LOuW/eoUVkQpNKisIl1liKyosFk1MTR+g1tbPlQVJAYKZN3vijR AD6J42zhir+1PzrB9U/KRyyLR5/utWhUcQDaefssomWRn301L39wkYbDZ2hJr6HmmcVi QdBOJnavn4JcWK1Qv678DPvGDmLs408VE5p7dfoUb8spxYZ6UEoNgNqFkcjB1rzqHowL a8mhNJ5wxl0U/xDwS73YVp9GHlTtRwV6aXSFVd8+FSGNovRXhrZtYXAIO5IrpTp/jtmi FzspkJdtdh3gVFU68LZh5R5gPSuiATDhpYtgFQlLRGJmFTUgK+vch+fF4LNzjlB6YNBL kuSg== X-Gm-Message-State: APjAAAUOydS7kyEqAXPVUwm03oHrkKlKdibg95cPH/a2nFStsK8rq3k+ AYdQ88v7Ls88qh9lAJgM6LEqNS4dKsw0Gw== X-Received: by 2002:a1c:5408:: with SMTP id i8mr2908630wmb.149.1571318948583; Thu, 17 Oct 2019 06:29:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n15sm2703392wrw.47.2019.10.17.06.29.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 06:29:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 1/8] hw/timer/puv3_ost.c: Switch to transaction-based ptimer API Date: Thu, 17 Oct 2019 14:28:58 +0100 Message-Id: <20191017132905.5604-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191017132905.5604-1-peter.maydell@linaro.org> References: <20191017132905.5604-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , "Edgar E. Iglesias" , Michael Walle , Guan Xuetao , Magnus Damm Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the puv3_ost code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell --- hw/timer/puv3_ost.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/timer/puv3_ost.c b/hw/timer/puv3_ost.c index 0898da5ce97..697519593bb 100644 --- a/hw/timer/puv3_ost.c +++ b/hw/timer/puv3_ost.c @@ -13,7 +13,6 @@ #include "hw/sysbus.h" #include "hw/irq.h" #include "hw/ptimer.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #undef DEBUG_PUV3 @@ -27,7 +26,6 @@ typedef struct PUV3OSTState { SysBusDevice parent_obj; MemoryRegion iomem; - QEMUBH *bh; qemu_irq irq; ptimer_state *ptimer; @@ -68,6 +66,7 @@ static void puv3_ost_write(void *opaque, hwaddr offset, DPRINTF("offset 0x%x, value 0x%x\n", offset, value); switch (offset) { case 0x00: /* Match Register 0 */ + ptimer_transaction_begin(s->ptimer); s->reg_OSMR0 = value; if (s->reg_OSMR0 > s->reg_OSCR) { ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR); @@ -76,6 +75,7 @@ static void puv3_ost_write(void *opaque, hwaddr offset, (0xffffffff - s->reg_OSCR)); } ptimer_run(s->ptimer, 2); + ptimer_transaction_commit(s->ptimer); break; case 0x14: /* Status Register */ assert(value == 0); @@ -128,9 +128,10 @@ static void puv3_ost_realize(DeviceState *dev, Error **errp) sysbus_init_irq(sbd, &s->irq); - s->bh = qemu_bh_new(puv3_ost_tick, s); - s->ptimer = ptimer_init_with_bh(s->bh, PTIMER_POLICY_DEFAULT); + s->ptimer = ptimer_init(puv3_ost_tick, s, PTIMER_POLICY_DEFAULT); + ptimer_transaction_begin(s->ptimer); ptimer_set_freq(s->ptimer, 50 * 1000 * 1000); + ptimer_transaction_commit(s->ptimer); memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost", PUV3_REGS_OFFSET); From patchwork Thu Oct 17 13:28:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 176630 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp952677ill; Thu, 17 Oct 2019 06:47:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqybPUJoC2yvCouIfht14GwbglU29vEOVTAeZITKOHVXTMq3MyuOj2O2HL7PAM3Vv1asjCYc X-Received: by 2002:a17:906:7c57:: with SMTP id g23mr3572204ejp.116.1571320060497; Thu, 17 Oct 2019 06:47:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571320060; cv=none; d=google.com; s=arc-20160816; b=pxpeMCjpnnjubhGER7Nt6eMZ+WcHIQVeLJdcV5n8ierl+aM7XAiZL9lqF0ttOXLMmy qi5Bnzzj/1lX29JkINNPrK/p/wfeTSGolZUXYXYyDrXxF0K3Yt/iIU76AQ+cJ2EMbKY1 /kSqNYFhPJGqdk8Kp2tyV1I3FxgzNoM0+xHRgE0Ksy5ty1J8ufA+VB38f9w+iavqwsqt i4J5rbBYxzwWjA3sJIKYJoRxacZL/4jtcf3NwyprgcIDHFEhI6xoRtZv/v09IgNDUbDB 1bpq/hH5MIwSzrCsm4IoeDQDWydbjABDccv1ztqrySmZKmm1nkGiNgdY5EFzUYVWvsTu fqZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RWVTerfEod6JXDvGIgZLZLZ8haab8EF7a9UHu0kP8E4=; b=ksDiXmVZky/wemFyjceL0pyc0XSq3/OC9RKkfo3oPvuyjpmuBaoFc0ELQktfx93i/P LLzf/J9JmiUOMB+hd4dFQGWBmaU7Q+QoJnSuO10aTOJ9uLRmaZMRjdM2nJk41JXHsFgJ pGQyrjmU5LAH1c7vvsONDnr1ZFKuL29iNDA79JSrRgux8O+aSVndC50LQv7co68JVVOt fRwPF43rP7sG+ugooDgCkwIZTsvQjTg5iBJVC3HQKJKzmdH53KXUBi57SlPreoYmWotj MZDpYdIfTFnDUE5htEwv21+Ll98hToGI9bWTIX66sS74VyjfANRiZqLJOgd3mQMD0fXk UCKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nlX+7Bwn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n15sm2703392wrw.47.2019.10.17.06.29.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 06:29:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 2/8] hw/timer/sh_timer: Switch to transaction-based ptimer API Date: Thu, 17 Oct 2019 14:28:59 +0100 Message-Id: <20191017132905.5604-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191017132905.5604-1-peter.maydell@linaro.org> References: <20191017132905.5604-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , "Edgar E. Iglesias" , Michael Walle , Guan Xuetao , Magnus Damm Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the sh_timer code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell --- hw/timer/sh_timer.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 48a81b4dc79..13c4051808f 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -13,7 +13,6 @@ #include "hw/irq.h" #include "hw/sh4/sh.h" #include "qemu/timer.h" -#include "qemu/main-loop.h" #include "hw/ptimer.h" //#define DEBUG_TIMER @@ -91,13 +90,18 @@ static void sh_timer_write(void *opaque, hwaddr offset, switch (offset >> 2) { case OFFSET_TCOR: s->tcor = value; + ptimer_transaction_begin(s->timer); ptimer_set_limit(s->timer, s->tcor, 0); + ptimer_transaction_commit(s->timer); break; case OFFSET_TCNT: s->tcnt = value; + ptimer_transaction_begin(s->timer); ptimer_set_count(s->timer, s->tcnt); + ptimer_transaction_commit(s->timer); break; case OFFSET_TCR: + ptimer_transaction_begin(s->timer); if (s->enabled) { /* Pause the timer if it is running. This may cause some inaccuracy dure to rounding, but avoids a whole lot of other @@ -148,6 +152,7 @@ static void sh_timer_write(void *opaque, hwaddr offset, /* Restart the timer if still enabled. */ ptimer_run(s->timer, 0); } + ptimer_transaction_commit(s->timer); break; case OFFSET_TCPR: if (s->feat & TIMER_FEAT_CAPT) { @@ -168,12 +173,14 @@ static void sh_timer_start_stop(void *opaque, int enable) printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled); #endif + ptimer_transaction_begin(s->timer); if (s->enabled && !enable) { ptimer_stop(s->timer); } if (!s->enabled && enable) { ptimer_run(s->timer, 0); } + ptimer_transaction_commit(s->timer); s->enabled = !!enable; #ifdef DEBUG_TIMER @@ -191,7 +198,6 @@ static void sh_timer_tick(void *opaque) static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) { sh_timer_state *s; - QEMUBH *bh; s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state)); s->freq = freq; @@ -203,8 +209,7 @@ static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) s->enabled = 0; s->irq = irq; - bh = qemu_bh_new(sh_timer_tick, s); - s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); + s->timer = ptimer_init(sh_timer_tick, s, PTIMER_POLICY_DEFAULT); sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor); sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt); From patchwork Thu Oct 17 13:29:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 176659 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp998613ill; Thu, 17 Oct 2019 07:21:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqxAHYIkWbLSBI5/pw5tlYi9rtsjM2XErU4vgGUJtfGvelZdaKlcHATd7xPHOgx37WrDGS4i X-Received: by 2002:a37:4995:: with SMTP id w143mr3453297qka.462.1571322074917; Thu, 17 Oct 2019 07:21:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571322074; cv=none; d=google.com; s=arc-20160816; b=LmHnLrHHh/t/q1rBfgmREyXSuLkm07i69biTyMDz7xwgD/mflAAmwDwyAfb1d/6cGc 8AfuQj/RSnWEO4KwQV7uQkKbVSxzS4P+s7psbAztjGE+vbTvoVrQuZGxpcr4L8w9KsPK inTmLsuaA1m45KfKfyWEtlgHJMx8jRf+f6VJrYUL+0C2WQuQHCWcKf3bUF1YSpVTk3qJ M2u7nuLBUYBPLH2r5FGLgUrp/CqTyJXC06bjgmoSzY/lB7zI83jKwcd4fn2lSz7EQ+LO mazArr+skGZjinxMtcQcoGHFJb05WvAiO6Nbxc03A12wNXKej8H1E97Gv8cYCKJgtmul sgIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=03WlCBecLigWxgy0uEAlie3BbhfPPehObmaYLG7brlM=; b=Hv3cJXUafWFGilqT7GUW89gcvfAnpNVulLZAUbfPpzH7kHtzZHxFzk2XdnCRwCwrQa q4wqXUA9HelMx4Jj8q5Y9Ia+pIdNlTwAgK66znvnyEJIsKGqQ52KCggE7cmCQY815Xgs rsp4sd91ayxTE6b/E8jV0qY6VHbDhy4sV3g0T09vter3+aHAlgSngtjig3JN4+1zenoF rIrzgzkR7FZ2Hsd1/N01f6mwkzFYx9jWP1ADkEYjdaXUBtu6kRqgp4iYuSOCWxZk8isC yl+bbdNkcUrvhaijFEqbm7s3R1+sdGhICz4dsGrtNv56NqpSKub0fsuQM9bDZnRWOm2U GfmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Xz5gXCHq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n15sm2703392wrw.47.2019.10.17.06.29.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 06:29:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 3/8] hw/timer/lm32_timer: Switch to transaction-based ptimer API Date: Thu, 17 Oct 2019 14:29:00 +0100 Message-Id: <20191017132905.5604-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191017132905.5604-1-peter.maydell@linaro.org> References: <20191017132905.5604-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , "Edgar E. Iglesias" , Michael Walle , Guan Xuetao , Magnus Damm Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the lm32_timer code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the ytimer. Signed-off-by: Peter Maydell --- hw/timer/lm32_timer.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/timer/lm32_timer.c b/hw/timer/lm32_timer.c index fabde760b2d..3fdecd09fe2 100644 --- a/hw/timer/lm32_timer.c +++ b/hw/timer/lm32_timer.c @@ -30,7 +30,6 @@ #include "hw/ptimer.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #define DEFAULT_FREQUENCY (50*1000000) @@ -63,7 +62,6 @@ struct LM32TimerState { MemoryRegion iomem; - QEMUBH *bh; ptimer_state *ptimer; qemu_irq irq; @@ -119,6 +117,7 @@ static void timer_write(void *opaque, hwaddr addr, s->regs[R_SR] &= ~SR_TO; break; case R_CR: + ptimer_transaction_begin(s->ptimer); s->regs[R_CR] = value; if (s->regs[R_CR] & CR_START) { ptimer_run(s->ptimer, 1); @@ -126,10 +125,13 @@ static void timer_write(void *opaque, hwaddr addr, if (s->regs[R_CR] & CR_STOP) { ptimer_stop(s->ptimer); } + ptimer_transaction_commit(s->ptimer); break; case R_PERIOD: s->regs[R_PERIOD] = value; + ptimer_transaction_begin(s->ptimer); ptimer_set_count(s->ptimer, value); + ptimer_transaction_commit(s->ptimer); break; case R_SNAPSHOT: error_report("lm32_timer: write access to read only register 0x" @@ -176,7 +178,9 @@ static void timer_reset(DeviceState *d) for (i = 0; i < R_MAX; i++) { s->regs[i] = 0; } + ptimer_transaction_begin(s->ptimer); ptimer_stop(s->ptimer); + ptimer_transaction_commit(s->ptimer); } static void lm32_timer_init(Object *obj) @@ -195,10 +199,11 @@ static void lm32_timer_realize(DeviceState *dev, Error **errp) { LM32TimerState *s = LM32_TIMER(dev); - s->bh = qemu_bh_new(timer_hit, s); - s->ptimer = ptimer_init_with_bh(s->bh, PTIMER_POLICY_DEFAULT); + s->ptimer = ptimer_init(timer_hit, s, PTIMER_POLICY_DEFAULT); + ptimer_transaction_begin(s->ptimer); ptimer_set_freq(s->ptimer, s->freq_hz); + ptimer_transaction_commit(s->ptimer); } static const VMStateDescription vmstate_lm32_timer = { From patchwork Thu Oct 17 13:29:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 176633 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp956976ill; Thu, 17 Oct 2019 06:51:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqy1EFV/TmBA58tTR2GKbPW8JJ8llOBetxdGlJpRY2vKs13gWV64KKIJa/+zk05dXOn8+eFJ X-Received: by 2002:a17:906:4a97:: with SMTP id x23mr3473545eju.218.1571320264364; Thu, 17 Oct 2019 06:51:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571320264; cv=none; d=google.com; s=arc-20160816; b=z5/wuG+ED4IVNq8c1JtUmHPTGBfs9l3F7WV798tkIRbBl2r6kiSt79vPNCNtejmUsa QkuwuOO94Y3JP9h9qoCtiXXF+o7vBSwJyTRHAnVG10bl//JICfgQedIYBDs00LkPfGzf hK5raPz3paWCWToDMFsNTWySHkYZK8Ww15kTLLrwA9eQy7S+kmffLuyAQj6H/Stt8BUk HZAMj+Vm7ieZRnHm8H0lePizHt6o2ooFhrccHvMaKlqg3jHx/hOP2ZHakpilNeFnQZNA Zs8aKlC/bia53y0FTgob92Iksaq2w8TGF8P4m/WIjPM8dyQHu+ntammcGZ7HxMSTvAuc Jr6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4DYhYWIpkNTGZF6Z7QvCMAVE0Xe2dndRrS+aQ9kDVJU=; b=vrZtsET7AZw865EQKVYmEBVpZYYsdrnNBO+1fitBjgPNBvQuz5TkuzgCC0ZOZo8uvf B2gPyYr8oAMKSsHGn5RHZ14akvHTkO8cSPt5DZmGSux5SvgH2T0XS9h+R4staOCiPm3O nt3k8LefaHvjS1pBC2B/1o2w3kGzHzSyz0F8eGGTpv0FSQsk2Xitx7uLTv9YeRdDnlVC A5aAlIRB4kwowSWeX5hQZZjsZDwGoorG/6Dj5ZrX/UmnFxKQgCL+TssVPz6N7DtfzZTr 9WQHjArdmdpx7TrEzJvDwpin4GzlskuvCSiIWs/ilU5IWS6Qz0og9m9Pd9PtduFQTd0x 9JiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JpIAGpxL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n15sm2703392wrw.47.2019.10.17.06.29.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 06:29:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 4/8] hw/watchdog/milkymist-sysctl.c: Switch to transaction-based ptimer API Date: Thu, 17 Oct 2019 14:29:01 +0100 Message-Id: <20191017132905.5604-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191017132905.5604-1-peter.maydell@linaro.org> References: <20191017132905.5604-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , "Edgar E. Iglesias" , Michael Walle , Guan Xuetao , Magnus Damm Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the milkymist-sysctl code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell --- hw/timer/milkymist-sysctl.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/timer/milkymist-sysctl.c b/hw/timer/milkymist-sysctl.c index 5193c038501..66f86541114 100644 --- a/hw/timer/milkymist-sysctl.c +++ b/hw/timer/milkymist-sysctl.c @@ -31,7 +31,6 @@ #include "hw/ptimer.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" -#include "qemu/main-loop.h" #include "qemu/module.h" enum { @@ -71,8 +70,6 @@ struct MilkymistSysctlState { MemoryRegion regs_region; - QEMUBH *bh0; - QEMUBH *bh1; ptimer_state *ptimer0; ptimer_state *ptimer1; @@ -161,14 +158,19 @@ static void sysctl_write(void *opaque, hwaddr addr, uint64_t value, s->regs[addr] = value; break; case R_TIMER0_COMPARE: + ptimer_transaction_begin(s->ptimer0); ptimer_set_limit(s->ptimer0, value, 0); s->regs[addr] = value; + ptimer_transaction_commit(s->ptimer0); break; case R_TIMER1_COMPARE: + ptimer_transaction_begin(s->ptimer1); ptimer_set_limit(s->ptimer1, value, 0); s->regs[addr] = value; + ptimer_transaction_commit(s->ptimer1); break; case R_TIMER0_CONTROL: + ptimer_transaction_begin(s->ptimer0); s->regs[addr] = value; if (s->regs[R_TIMER0_CONTROL] & CTRL_ENABLE) { trace_milkymist_sysctl_start_timer0(); @@ -179,8 +181,10 @@ static void sysctl_write(void *opaque, hwaddr addr, uint64_t value, trace_milkymist_sysctl_stop_timer0(); ptimer_stop(s->ptimer0); } + ptimer_transaction_commit(s->ptimer0); break; case R_TIMER1_CONTROL: + ptimer_transaction_begin(s->ptimer0); s->regs[addr] = value; if (s->regs[R_TIMER1_CONTROL] & CTRL_ENABLE) { trace_milkymist_sysctl_start_timer1(); @@ -191,6 +195,7 @@ static void sysctl_write(void *opaque, hwaddr addr, uint64_t value, trace_milkymist_sysctl_stop_timer1(); ptimer_stop(s->ptimer1); } + ptimer_transaction_commit(s->ptimer0); break; case R_ICAP: sysctl_icap_write(s, value); @@ -263,8 +268,12 @@ static void milkymist_sysctl_reset(DeviceState *d) s->regs[i] = 0; } + ptimer_transaction_begin(s->ptimer0); ptimer_stop(s->ptimer0); + ptimer_transaction_commit(s->ptimer0); + ptimer_transaction_begin(s->ptimer1); ptimer_stop(s->ptimer1); + ptimer_transaction_commit(s->ptimer1); /* defaults */ s->regs[R_ICAP] = ICAP_READY; @@ -292,13 +301,15 @@ static void milkymist_sysctl_realize(DeviceState *dev, Error **errp) { MilkymistSysctlState *s = MILKYMIST_SYSCTL(dev); - s->bh0 = qemu_bh_new(timer0_hit, s); - s->bh1 = qemu_bh_new(timer1_hit, s); - s->ptimer0 = ptimer_init_with_bh(s->bh0, PTIMER_POLICY_DEFAULT); - s->ptimer1 = ptimer_init_with_bh(s->bh1, PTIMER_POLICY_DEFAULT); + s->ptimer0 = ptimer_init(timer0_hit, s, PTIMER_POLICY_DEFAULT); + s->ptimer1 = ptimer_init(timer1_hit, s, PTIMER_POLICY_DEFAULT); + ptimer_transaction_begin(s->ptimer0); ptimer_set_freq(s->ptimer0, s->freq_hz); + ptimer_transaction_commit(s->ptimer0); + ptimer_transaction_begin(s->ptimer1); ptimer_set_freq(s->ptimer1, s->freq_hz); + ptimer_transaction_commit(s->ptimer1); } static const VMStateDescription vmstate_milkymist_sysctl = { From patchwork Thu Oct 17 13:29:02 2019 Content-Type: text/plain; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n15sm2703392wrw.47.2019.10.17.06.29.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 06:29:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 5/8] hw/timer/altera_timer.c: Switch to transaction-based ptimer API Date: Thu, 17 Oct 2019 14:29:02 +0100 Message-Id: <20191017132905.5604-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191017132905.5604-1-peter.maydell@linaro.org> References: <20191017132905.5604-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , "Edgar E. Iglesias" , Michael Walle , Guan Xuetao , Magnus Damm Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the altera_timer code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell --- hw/timer/altera_timer.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/timer/altera_timer.c b/hw/timer/altera_timer.c index ee32e0ec1ff..79fc381252d 100644 --- a/hw/timer/altera_timer.c +++ b/hw/timer/altera_timer.c @@ -19,7 +19,6 @@ */ #include "qemu/osdep.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "qapi/error.h" @@ -53,7 +52,6 @@ typedef struct AlteraTimer { MemoryRegion mmio; qemu_irq irq; uint32_t freq_hz; - QEMUBH *bh; ptimer_state *ptimer; uint32_t regs[R_MAX]; } AlteraTimer; @@ -105,6 +103,7 @@ static void timer_write(void *opaque, hwaddr addr, break; case R_CONTROL: + ptimer_transaction_begin(t->ptimer); t->regs[R_CONTROL] = value & (CONTROL_ITO | CONTROL_CONT); if ((value & CONTROL_START) && !(t->regs[R_STATUS] & STATUS_RUN)) { @@ -115,10 +114,12 @@ static void timer_write(void *opaque, hwaddr addr, ptimer_stop(t->ptimer); t->regs[R_STATUS] &= ~STATUS_RUN; } + ptimer_transaction_commit(t->ptimer); break; case R_PERIODL: case R_PERIODH: + ptimer_transaction_begin(t->ptimer); t->regs[addr] = value & 0xFFFF; if (t->regs[R_STATUS] & STATUS_RUN) { ptimer_stop(t->ptimer); @@ -126,6 +127,7 @@ static void timer_write(void *opaque, hwaddr addr, } tvalue = (t->regs[R_PERIODH] << 16) | t->regs[R_PERIODL]; ptimer_set_limit(t->ptimer, tvalue + 1, 1); + ptimer_transaction_commit(t->ptimer); break; case R_SNAPL: @@ -183,9 +185,10 @@ static void altera_timer_realize(DeviceState *dev, Error **errp) return; } - t->bh = qemu_bh_new(timer_hit, t); - t->ptimer = ptimer_init_with_bh(t->bh, PTIMER_POLICY_DEFAULT); + t->ptimer = ptimer_init(timer_hit, t, PTIMER_POLICY_DEFAULT); + ptimer_transaction_begin(t->ptimer); ptimer_set_freq(t->ptimer, t->freq_hz); + ptimer_transaction_commit(t->ptimer); memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_ALTERA_TIMER, R_MAX * sizeof(uint32_t)); @@ -204,8 +207,10 @@ static void altera_timer_reset(DeviceState *dev) { AlteraTimer *t = ALTERA_TIMER(dev); + ptimer_transaction_begin(t->ptimer); ptimer_stop(t->ptimer); ptimer_set_limit(t->ptimer, 0xffffffff, 1); + ptimer_transaction_commit(t->ptimer); memset(t->regs, 0, sizeof(t->regs)); } From patchwork Thu Oct 17 13:29:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 176652 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp979493ill; Thu, 17 Oct 2019 07:07:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqxTNtX8JziC7vwqCd6QyfEA6T5s2rz5OaOZVqh3xbml5ONntHjtZRImPJEUPyW6Djgmq2d0 X-Received: by 2002:a0c:f8cd:: with SMTP id h13mr3973945qvo.53.1571321267200; Thu, 17 Oct 2019 07:07:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571321267; cv=none; d=google.com; s=arc-20160816; b=WYY4xhfaRWqIe8QpPWQGRWSvODfkaWG2QSCVrT0bAQjoi7x19mrm9nLwQG/1YBQL4i ZmrI1IJnJ1skBbFBi544/aK2C5Ms3UH8VXH1iKP5YDNno0y38ME6Uj1bkEvF3p7k5SWm BuVNEWeg4Rdovrmi/8cCTjLUYcejZSfOJVaeNKKSwWCEN9DGFM3itCizvCjbNigHisHJ Ot0nddcJ3LP8hJUkUCIbxZ4brER8mJQy8KAluL0sBHV6NYFHXatYiSi/voC6tSwMoKss 0Hc3BL/whWaVoQ+fDPM/XocECiXO9d+KdzHBURVvN8uKrgkwSUuX5Kk7tBqcK8jHWucK QzJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=2N8pR3XdK7iKpoiyLDAZ/80MgScv3T2YbJfwoAS7T38=; b=CCz/CnlTwoa/3fQIJ0yu6qfWHl7Jlxny+9SJDwQ50BAXyuWxRi1+KhVCuWoECQEQhm YpVij/EJJaOnIxoT4qJthKBBzgsXcQQMt5oBv495ZsssI1fSguF3iTxtTriLu53tNVMC 5R9fjVDfyAFb7474P5oMA5W7ZBEt3zOiSDDoj2Wwx0XnJhN94MaryWn08gOTXaWBLuv8 jIkAe1beXbXhBSIbnccDZ7/LXhw1hYKMqyRqeiDJtJdNklCP5QRQNs4fBrnxhlYKuUn1 jQ+eKDUg1CZ8yKPKalWdQwrabypJEVwd7SKCgHb9EgCSxTKc6V4SmGs4cmm1If7MXqPF l2gA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NHrxN4io; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n15sm2703392wrw.47.2019.10.17.06.29.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 06:29:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 6/8] hw/watchdog/etraxfs_timer.c: Switch to transaction-based ptimer API Date: Thu, 17 Oct 2019 14:29:03 +0100 Message-Id: <20191017132905.5604-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191017132905.5604-1-peter.maydell@linaro.org> References: <20191017132905.5604-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , "Edgar E. Iglesias" , Michael Walle , Guan Xuetao , Magnus Damm Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the etraxfs_timer code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell --- hw/timer/etraxfs_timer.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c index ab27fe1895b..afe3d30a8ea 100644 --- a/hw/timer/etraxfs_timer.c +++ b/hw/timer/etraxfs_timer.c @@ -26,7 +26,6 @@ #include "hw/sysbus.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "qemu/timer.h" #include "hw/irq.h" @@ -59,9 +58,6 @@ typedef struct ETRAXTimerState { qemu_irq irq; qemu_irq nmi; - QEMUBH *bh_t0; - QEMUBH *bh_t1; - QEMUBH *bh_wd; ptimer_state *ptimer_t0; ptimer_state *ptimer_t1; ptimer_state *ptimer_wd; @@ -155,6 +151,7 @@ static void update_ctrl(ETRAXTimerState *t, int tnum) } D(printf ("freq_hz=%d div=%d\n", freq_hz, div)); + ptimer_transaction_begin(timer); ptimer_set_freq(timer, freq_hz); ptimer_set_limit(timer, div, 0); @@ -176,6 +173,7 @@ static void update_ctrl(ETRAXTimerState *t, int tnum) abort(); break; } + ptimer_transaction_commit(timer); } static void timer_update_irq(ETRAXTimerState *t) @@ -240,6 +238,7 @@ static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value) t->wd_hits = 0; + ptimer_transaction_begin(t->ptimer_wd); ptimer_set_freq(t->ptimer_wd, 760); if (wd_cnt == 0) wd_cnt = 256; @@ -250,6 +249,7 @@ static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value) ptimer_stop(t->ptimer_wd); t->rw_wd_ctrl = value; + ptimer_transaction_commit(t->ptimer_wd); } static void @@ -311,9 +311,15 @@ static void etraxfs_timer_reset(void *opaque) { ETRAXTimerState *t = opaque; + ptimer_transaction_begin(t->ptimer_t0); ptimer_stop(t->ptimer_t0); + ptimer_transaction_commit(t->ptimer_t0); + ptimer_transaction_begin(t->ptimer_t1); ptimer_stop(t->ptimer_t1); + ptimer_transaction_commit(t->ptimer_t1); + ptimer_transaction_begin(t->ptimer_wd); ptimer_stop(t->ptimer_wd); + ptimer_transaction_commit(t->ptimer_wd); t->rw_wd_ctrl = 0; t->r_intr = 0; t->rw_intr_mask = 0; @@ -325,12 +331,9 @@ static void etraxfs_timer_realize(DeviceState *dev, Error **errp) ETRAXTimerState *t = ETRAX_TIMER(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - t->bh_t0 = qemu_bh_new(timer0_hit, t); - t->bh_t1 = qemu_bh_new(timer1_hit, t); - t->bh_wd = qemu_bh_new(watchdog_hit, t); - t->ptimer_t0 = ptimer_init_with_bh(t->bh_t0, PTIMER_POLICY_DEFAULT); - t->ptimer_t1 = ptimer_init_with_bh(t->bh_t1, PTIMER_POLICY_DEFAULT); - t->ptimer_wd = ptimer_init_with_bh(t->bh_wd, PTIMER_POLICY_DEFAULT); + t->ptimer_t0 = ptimer_init(timer0_hit, t, PTIMER_POLICY_DEFAULT); + t->ptimer_t1 = ptimer_init(timer1_hit, t, PTIMER_POLICY_DEFAULT); + t->ptimer_wd = ptimer_init(watchdog_hit, t, PTIMER_POLICY_DEFAULT); sysbus_init_irq(sbd, &t->irq); sysbus_init_irq(sbd, &t->nmi); From patchwork Thu Oct 17 13:29:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 176655 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp984300ill; Thu, 17 Oct 2019 07:11:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqwJYoh5USKbzRwoD2GTT/QklF/M2QXguoZu8ZxxnMT6ApI6gCfwTZE75GAJf2aVtEKeJAAe X-Received: by 2002:aa7:cf12:: with SMTP id a18mr4044378edy.278.1571321473229; Thu, 17 Oct 2019 07:11:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571321473; cv=none; d=google.com; s=arc-20160816; b=SL5wgG8Qxn6W9pHezS5iWQMw9LQLXtXYsboGHds0kTZo0aVLFBrBUCB6C4qPpXpqHN 3jfEzEk8y5dGJdyPVwvMtfHj45GchLDQTrD36pMm9C8CVTh3JczZo2lRbm/FrgFmVzJ7 XA/9lPHfzPRmMcB/8A7TFxcNBx0OFlaCl9hOOc9hWl5f3Rs9d+EWZemCQzG5qc4DzTXU mHpEFn9Eqqf7iVwtkkLadnNN6dbJyVg4TNC09XtgAthS28uPQIa8oNxHmC8o8QbPC21f ITZHGnzex7J6mljzvJ6jVfcyZCGFKvP8TROH0LSbE6YFlhPRD6TkjefgWDUE/opqzgnq bBrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=e4PVQeNvPwVNwMTizB+ixtPW1GcJ8H+hxCE9Nf1uwZo=; b=PPYCP9ghVYa4vC6vd8HiycWeyqCpIWZBB8mDsgnq/2QExCvP9KTba9QSliSy3h4Cbz thZGjWMgFtTEoXZeTvZJ+hjOGOcnydFf1t80Oz8RjhDpoWA9BqJ0SixzD0PgbMC77OU+ yFFBKiwtAOg4FLc629AxAW5bxeSfjzm5xvgzkMYt6r06MkioavemDH1oQvpK45x/iUX2 tw2SOUtUVr21OQrxmQyRoy+cKnqAeKB/mYCO3u9HxMVbU0iInC7XVP2XExgXSfwgjiR6 Gn2wi5xYgpkaJrEAdarRrTOkctpjs2MKbWr+xYJvRKipYC9a8yJ/HZaxft21IvU034I1 B3ag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LTVhSUmr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n15sm2703392wrw.47.2019.10.17.06.29.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 06:29:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 7/8] hw/m68k/mcf5206.c: Switch to transaction-based ptimer API Date: Thu, 17 Oct 2019 14:29:04 +0100 Message-Id: <20191017132905.5604-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191017132905.5604-1-peter.maydell@linaro.org> References: <20191017132905.5604-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , "Edgar E. Iglesias" , Michael Walle , Guan Xuetao , Magnus Damm Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the mcf5206 code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell --- hw/m68k/mcf5206.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c index a49096367cb..c05401e0e50 100644 --- a/hw/m68k/mcf5206.c +++ b/hw/m68k/mcf5206.c @@ -8,7 +8,6 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "hw/hw.h" #include "hw/irq.h" @@ -57,6 +56,7 @@ static void m5206_timer_recalibrate(m5206_timer_state *s) int prescale; int mode; + ptimer_transaction_begin(s->timer); ptimer_stop(s->timer); if ((s->tmr & TMR_RST) == 0) @@ -78,6 +78,7 @@ static void m5206_timer_recalibrate(m5206_timer_state *s) ptimer_set_limit(s->timer, s->trr, 0); ptimer_run(s->timer, 0); + ptimer_transaction_commit(s->timer); } static void m5206_timer_trigger(void *opaque) @@ -123,7 +124,9 @@ static void m5206_timer_write(m5206_timer_state *s, uint32_t addr, uint32_t val) s->tcr = val; break; case 0xc: + ptimer_transaction_begin(s->timer); ptimer_set_count(s->timer, val); + ptimer_transaction_commit(s->timer); break; case 0x11: s->ter &= ~val; @@ -137,11 +140,9 @@ static void m5206_timer_write(m5206_timer_state *s, uint32_t addr, uint32_t val) static m5206_timer_state *m5206_timer_init(qemu_irq irq) { m5206_timer_state *s; - QEMUBH *bh; s = g_new0(m5206_timer_state, 1); - bh = qemu_bh_new(m5206_timer_trigger, s); - s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); + s->timer = ptimer_init(m5206_timer_trigger, s, PTIMER_POLICY_DEFAULT); s->irq = irq; m5206_timer_reset(s); return s; From patchwork Thu Oct 17 13:29:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 176660 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp999175ill; Thu, 17 Oct 2019 07:21:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqxQFIZ40SNNYP09R336atcnxZIYOAyLYOIbMUKQCXaUKlfdBxLbdmw6ZEHPMM0cVChwyA0r X-Received: by 2002:ad4:4431:: with SMTP id e17mr3995795qvt.78.1571322100514; Thu, 17 Oct 2019 07:21:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571322100; cv=none; d=google.com; s=arc-20160816; b=JvZ4HGa55eJgNiqoBBK7zIgmlgpz35hMGJ57ERtZOwtdGPCb2dLSmi7Qoh+N1Ykq54 N8wF1c0uxucJbMoB6d6hzcjYuIAdw6tK9sY9yIe1/9vh6AIQN8itK3NTMxq/IaKA7/pt KZb6UHJ6gBeX10URyj+qqdPmmJtTV4U0Sk1cynEkGCTC54FBMZ9XRgoUb852gcmkOgvD YOcYcGvqdE46AdDRLO/RbIe8oi/z4rbEx24L5lNZtEGiXf4A4bWl3gLBdXtN6nxWUcnt iM4vMJUe0FR13B/nlGuoAkFlTuIqkUw4i350Lt4Hfmzqs09snXUsEfPmRY7wJ10YGi1G yxww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ir767WHuQR1ReCBFZWeg1KIR738tHBrpLcvCZkSJv5k=; b=eKwO0EDi/eWw+C1m3LjFd7b71eSZdasmjJ6aYzbn8J+aGlQlYDNBxEQO/xXCkchDJE ltUNC7XFMV4Uvpcl5CLbfZnZLf0Zc/st2EyqmOVzf6Nqe7cTmD0uZQKWXYISCTjHMX5V YmImxpGrKe+YS6NGYmaM2w6r4wJDCrRDRFsmnB2JOl4JNICjSFp1Fp4B4plJRg7F7WLa tgKnw9QrzkHGkwZaMrD1qR9TmmJb2+/3nfsOGfs66c7voxvBQ4wbBGCxN2hdnnGQQwte umYSLCxVNut4oGMKhfjiTW8Ecm+coF6PcDoINT1q2FZ570iyjG53G/xJS4SinjBeZWcu K0JA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r8Oo1LfX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n15sm2703392wrw.47.2019.10.17.06.29.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 06:29:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 8/8] hw/m68k/mcf5208.c: Switch to transaction-based ptimer API Date: Thu, 17 Oct 2019 14:29:05 +0100 Message-Id: <20191017132905.5604-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191017132905.5604-1-peter.maydell@linaro.org> References: <20191017132905.5604-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , "Edgar E. Iglesias" , Michael Walle , Guan Xuetao , Magnus Damm Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the mcf5208 code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell --- hw/m68k/mcf5208.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Thomas Huth diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c index 34d34eba17c..158c5e4be75 100644 --- a/hw/m68k/mcf5208.c +++ b/hw/m68k/mcf5208.c @@ -9,7 +9,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qemu/error-report.h" -#include "qemu/main-loop.h" #include "qapi/error.h" #include "qemu-common.h" #include "cpu.h" @@ -79,6 +78,7 @@ static void m5208_timer_write(void *opaque, hwaddr offset, return; } + ptimer_transaction_begin(s->timer); if (s->pcsr & PCSR_EN) ptimer_stop(s->timer); @@ -94,8 +94,10 @@ static void m5208_timer_write(void *opaque, hwaddr offset, if (s->pcsr & PCSR_EN) ptimer_run(s->timer, 0); + ptimer_transaction_commit(s->timer); break; case 2: + ptimer_transaction_begin(s->timer); s->pmr = value; s->pcsr &= ~PCSR_PIF; if ((s->pcsr & PCSR_RLD) == 0) { @@ -104,6 +106,7 @@ static void m5208_timer_write(void *opaque, hwaddr offset, } else { ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW); } + ptimer_transaction_commit(s->timer); break; case 4: break; @@ -182,7 +185,6 @@ static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic) { MemoryRegion *iomem = g_new(MemoryRegion, 1); m5208_timer_state *s; - QEMUBH *bh; int i; /* SDRAMC. */ @@ -191,8 +193,7 @@ static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic) /* Timers. */ for (i = 0; i < 2; i++) { s = g_new0(m5208_timer_state, 1); - bh = qemu_bh_new(m5208_timer_trigger, s); - s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); + s->timer = ptimer_init(m5208_timer_trigger, s, PTIMER_POLICY_DEFAULT); memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s, "m5208-timer", 0x00004000); memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i,