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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 01/22] target/arm: Split out rebuild_hflags_common Date: Fri, 18 Oct 2019 10:44:10 -0700 Message-Id: <20191018174431.1784-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function to compute the values of the TBFLAG_ANY bits that will be cached. For now, the env->hflags variable is not used, and the results are fed back to cpu_get_tb_cpu_state. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 29 ++++++++++++++++++----------- target/arm/helper.c | 26 +++++++++++++++++++------- 2 files changed, 37 insertions(+), 18 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 297ad5e47a..ad79a6153b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -231,6 +231,9 @@ typedef struct CPUARMState { uint32_t pstate; uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ + /* Cached TBFLAGS state. See below for which bits are included. */ + uint32_t hflags; + /* Frequently accessed CPSR bits are stored separately for efficiency. This contains all the other bits. Use cpsr_{read,write} to access the whole CPSR. */ @@ -3140,15 +3143,18 @@ typedef ARMCPU ArchCPU; #include "exec/cpu-all.h" -/* Bit usage in the TB flags field: bit 31 indicates whether we are +/* + * Bit usage in the TB flags field: bit 31 indicates whether we are * in 32 or 64 bit mode. The meaning of the other bits depends on that. * We put flags which are shared between 32 and 64 bit mode at the top * of the word, and flags which apply to only one mode at the bottom. + * + * Unless otherwise noted, these bits are cached in env->hflags. */ FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) FIELD(TBFLAG_ANY, MMUIDX, 28, 3) FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) -FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) +FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */ /* Target EL if we take a floating-point-disabled exception */ FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) FIELD(TBFLAG_ANY, BE_DATA, 23, 1) @@ -3159,13 +3165,14 @@ FIELD(TBFLAG_ANY, BE_DATA, 23, 1) FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2) /* Bit usage when in AArch32 state: */ -FIELD(TBFLAG_A32, THUMB, 0, 1) -FIELD(TBFLAG_A32, VECLEN, 1, 3) -FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) +FIELD(TBFLAG_A32, THUMB, 0, 1) /* Not cached. */ +FIELD(TBFLAG_A32, VECLEN, 1, 3) /* Not cached. */ +FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) /* Not cached. */ /* * We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime. This shares the same bits as * VECSTRIDE, which is OK as no XScale CPU has VFP. + * Not cached, because VECLEN+VECSTRIDE are not cached. */ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) /* @@ -3174,15 +3181,15 @@ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) * the same thing as the current security state of the processor! */ FIELD(TBFLAG_A32, NS, 6, 1) -FIELD(TBFLAG_A32, VFPEN, 7, 1) -FIELD(TBFLAG_A32, CONDEXEC, 8, 8) +FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Not cached. */ +FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) /* For M profile only, set if FPCCR.LSPACT is set */ -FIELD(TBFLAG_A32, LSPACT, 18, 1) +FIELD(TBFLAG_A32, LSPACT, 18, 1) /* Not cached. */ /* For M profile only, set if we must create a new FP context */ -FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) +FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) /* Not cached. */ /* For M profile only, set if FPCCR.S does not match current security state */ -FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) +FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) /* Not cached. */ /* For M profile only, Handler (ie not Thread) mode */ FIELD(TBFLAG_A32, HANDLER, 21, 1) /* For M profile only, whether we should generate stack-limit checks */ @@ -3194,7 +3201,7 @@ FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) -FIELD(TBFLAG_A64, BTYPE, 10, 2) +FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ FIELD(TBFLAG_A64, TBID, 12, 2) static inline bool bswap_code(bool sctlr_b) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0d9a2d2ab7..8829d91ae1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11054,6 +11054,22 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) } #endif +static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, uint32_t flags) +{ + flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); + flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, + arm_to_core_mmu_idx(mmu_idx)); + + if (arm_cpu_data_is_big_endian(env)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + } + if (arm_singlestep_active(env)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); + } + return flags; +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -11145,7 +11161,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } - flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); + flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags); /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: @@ -11153,9 +11169,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * 0 x Inactive (the TB flag for SS is always 0) * 1 0 Active-pending * 1 1 Active-not-pending + * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. */ - if (arm_singlestep_active(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); + if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE)) { if (is_a64(env)) { if (env->pstate & PSTATE_SS) { flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); @@ -11166,10 +11182,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } } - if (arm_cpu_data_is_big_endian(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); - } - flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); if (arm_v7m_is_handler_mode(env)) { flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); From patchwork Fri Oct 18 17:44:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176919 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1183163ill; Fri, 18 Oct 2019 10:48:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqxjgNfX7bCJ5Yw5hT89YJtS75KRLJl0JlFzW/NOP8SKkVanOCCojx69upB3wmBptZXIeK6v X-Received: by 2002:a37:a755:: with SMTP id q82mr9931323qke.394.1571420912788; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 02/22] target/arm: Split out rebuild_hflags_a64 Date: Fri, 18 Oct 2019 10:44:11 -0700 Message-Id: <20191018174431.1784-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function to compute the values of the TBFLAG_A64 bits that will be cached. For now, the env->hflags variable is not used, and the results are fed back to cpu_get_tb_cpu_state. Note that not all BTI related flags are cached, so we have to test the BTI feature twice -- once for those bits moved out to rebuild_hflags_a64 and once for those bits that remain in cpu_get_tb_cpu_state. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 131 +++++++++++++++++++++++--------------------- 1 file changed, 69 insertions(+), 62 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 8829d91ae1..69da04786e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11070,6 +11070,71 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, return flags; } +static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, + ARMMMUIdx mmu_idx) +{ + ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); + ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); + uint32_t flags = 0; + uint64_t sctlr; + int tbii, tbid; + + flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); + + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + if (regime_el(env, stage1) < 2) { + ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); + tbid = (p1.tbi << 1) | p0.tbi; + tbii = tbid & ~((p1.tbid << 1) | p0.tbid); + } else { + tbid = p0.tbi; + tbii = tbid & !p0.tbid; + } + + flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); + flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); + + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { + int sve_el = sve_exception_el(env, el); + uint32_t zcr_len; + + /* + * If SVE is disabled, but FP is enabled, + * then the effective len is 0. + */ + if (sve_el != 0 && fp_el == 0) { + zcr_len = 0; + } else { + zcr_len = sve_zcr_len_for_el(env, el); + } + flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); + flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); + } + + sctlr = arm_sctlr(env, el); + + if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { + /* + * In order to save space in flags, we record only whether + * pauth is "inactive", meaning all insns are implemented as + * a nop, or "active" when some action must be performed. + * The decision of which action to take is left to a helper. + */ + if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { + flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); + } + } + + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { + /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ + if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { + flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); + } + } + + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -11079,67 +11144,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, uint32_t flags = 0; if (is_a64(env)) { - ARMCPU *cpu = env_archcpu(env); - uint64_t sctlr; - *pc = env->pc; - flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); - - /* Get control bits for tagged addresses. */ - { - ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); - ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); - int tbii, tbid; - - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - if (regime_el(env, stage1) < 2) { - ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); - tbid = (p1.tbi << 1) | p0.tbi; - tbii = tbid & ~((p1.tbid << 1) | p0.tbid); - } else { - tbid = p0.tbi; - tbii = tbid & !p0.tbid; - } - - flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); - flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); - } - - if (cpu_isar_feature(aa64_sve, cpu)) { - int sve_el = sve_exception_el(env, current_el); - uint32_t zcr_len; - - /* If SVE is disabled, but FP is enabled, - * then the effective len is 0. - */ - if (sve_el != 0 && fp_el == 0) { - zcr_len = 0; - } else { - zcr_len = sve_zcr_len_for_el(env, current_el); - } - flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); - flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); - } - - sctlr = arm_sctlr(env, current_el); - - if (cpu_isar_feature(aa64_pauth, cpu)) { - /* - * In order to save space in flags, we record only whether - * pauth is "inactive", meaning all insns are implemented as - * a nop, or "active" when some action must be performed. - * The decision of which action to take is left to a helper. - */ - if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { - flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); - } - } - - if (cpu_isar_feature(aa64_bti, cpu)) { - /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ - if (sctlr & (current_el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { - flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); - } + flags = rebuild_hflags_a64(env, current_el, fp_el, mmu_idx); + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } } else { @@ -11159,9 +11166,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); } - } - flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags); + flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags); + } /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: From patchwork Fri Oct 18 17:44:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176917 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1180210ill; Fri, 18 Oct 2019 10:45:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqyn+RWT3dl26ytmFc53Sp0LD5N06jWUIsYOJeJSUsREfwMrBlbAvOQmp5VSdrRNz2of4LsK X-Received: by 2002:a37:e503:: with SMTP id e3mr10131765qkg.491.1571420727507; Fri, 18 Oct 2019 10:45:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571420727; cv=none; d=google.com; s=arc-20160816; b=NCWCtsE/0dWhsDP7CqN4Q+B4GukP/6ArrrpToyiUHZPsK/EcFvAQm27FISxCQBj/Ih O0oS2CFWJ8P0pnrhhRMfI1R5Qv+i2bRSVIPNhkjsTm8BD4rK952OiHBzGO28FvZQ804J MU6iEZV8sFcO4AJC9VLGDa6cvQo/bxgSV6DW7nDTy3jZ+iqcKXRFeIxPmlQA9DxZR5Sr W6/CE6+rCQ2PCgeLmOeo1jQprgsEMkoXgdHN7nPsJU4P+Zw4IIEXNo4bvSaexQbbpsMP i4QLSNCGHhbY851Ercv5bYD2T9OujR8eUqoGMEk4qZGDBWTIX3r9psBHsJpSx5s+obQZ Ny3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+UgAJ6EhcwGdb7pezBRTrZ79eaC+NjRs0dqrTWfzTFo=; b=eUnFuKCH20i7ryU+dksq6g+SHBmX2R6mcNHvSx+mPYrc1grA5fRhlSD98vqDTP2iSV MT9iAgdHY8kLVYX8oouKMah+dlcwXObdfibW2CG8TCFY10jalQqqKMXmNe23SVHmT1Q8 KDRUp7GixG9ElXMwEKuQ1cmhE2CBvLrCb/pbU8+w1sk0JcPiiuiE43IW7l9KTWGhAkHw RMUghxq4yWrMx8WJjYENRvHe9Sz8TEOvkLRmN5wN+CZrmWGOcZp+opOfb+tP0e7+SS/i Bo64TJQs1HT3vgMq0eCbwi1oU7xxvu4QOe6CnFWMS0jRcE2eJidA0N5f3BeQ+ZeSHCFU 8FQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XlSNcfVE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 03/22] target/arm: Split out rebuild_hflags_common_32 Date: Fri, 18 Oct 2019 10:44:12 -0700 Message-Id: <20191018174431.1784-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function to compute the values of the TBFLAG_A32 bits that will be cached, and are used by all profiles. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 69da04786e..f05d042474 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11070,6 +11070,15 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, return flags; } +static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, uint32_t flags) +{ + flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); + flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); + + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); +} + static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { @@ -11141,7 +11150,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, ARMMMUIdx mmu_idx = arm_mmu_idx(env); int current_el = arm_current_el(env); int fp_el = fp_exception_el(env, current_el); - uint32_t flags = 0; + uint32_t flags; if (is_a64(env)) { *pc = env->pc; @@ -11151,12 +11160,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } else { *pc = env->regs[15]; + flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); - flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); - flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); @@ -11166,8 +11174,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); } - - flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags); } /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine From patchwork Fri Oct 18 17:44:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176928 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1193297ill; Fri, 18 Oct 2019 10:59:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqy6IPBQQ0CdqJg6qvbZMs1ywptMl4Hy2Me4n4O2UkbYtPdOEhOwnShCboWnbNPyhYi6Wwmg X-Received: by 2002:a0c:ecc5:: with SMTP id o5mr11206873qvq.19.1571421567041; Fri, 18 Oct 2019 10:59:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571421567; cv=none; d=google.com; s=arc-20160816; b=GpO7jTCyAXeg/xPF23jrQxg6adn2dPcvxLvY8gOiCb2/FcyVRf1YhIVprno9ICHDf1 Mlyw7u8GWDTI/g8qoZPt6KHdl5510qiWqALKS1BZeG9XfTCF/iqEy2L+AnGgabdDDB0e Wp831PUGxJU61ukQHasJ03ePfI3+gx/IFu1irmo8L9LBc6uWKD7RIaeWCHcyxJTPP0yX nURNqnrcQ3RTbAgflwH0ymGYBMlfxsjEASvS+CEAJvQPXw7JMJKqLsUVHfTjyUyDjytm B06yyLrbHuVMCPejxMyyaDAsajwDdYubFOnQdd4bhXkuWOmHH6x4Dpm+LVfRBDQIChcy 3M6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wk2rFtSmeyIzF6QnNFgZDZnR49h41R/PQfqDCLolPT8=; b=tj6YmBInMd2HsO0fBugjOFunomFXOxCW4FnPUAT8WaAIU6QuXpffCuZf8O5FiRZFeC XxTJn/yeXAoAjfKMcNlzvyYH4U24B9w9TddfsPvtM/dKdRtAnOov1IFTDZ5Tj+Q8zxyj zj3JLEcB6l2oWuSkSo5FjaAXnZMPsP3HCgM8tvAYH//XtVWhrWaQzxOTiUVlMxU3PN+u wJXsvn62gyn3A6+pQFkZuNh7BLL8Pdxxd72CMiFnxivPP/CZeNsTIWuyK1j9/7yIJy73 TACk1FjjEUkRH3NqVkJHDhfXYTGjzMhYgKmRMk+uu9sLnIqAIlwr9A2yRGsmLUriJVev heSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pan73PhX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t29si6370637qkt.77.2019.10.18.10.59.26 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 18 Oct 2019 10:59:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pan73PhX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iLWX8-0006HJ-0R for patch@linaro.org; Fri, 18 Oct 2019 13:59:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59145) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iLWIu-0006Su-AU for qemu-devel@nongnu.org; Fri, 18 Oct 2019 13:44:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iLWIr-0005OV-Mu for qemu-devel@nongnu.org; Fri, 18 Oct 2019 13:44:44 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:45045) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iLWIp-0005MN-Lg for qemu-devel@nongnu.org; Fri, 18 Oct 2019 13:44:40 -0400 Received: by mail-pf1-x443.google.com with SMTP id q21so4303166pfn.11 for ; Fri, 18 Oct 2019 10:44:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wk2rFtSmeyIzF6QnNFgZDZnR49h41R/PQfqDCLolPT8=; b=pan73PhXQV5z7gdX5CbXBk0Q7XbJeIfWLw5XQZxD1KJU6n0g+opRjZLEB0F1X7qa/K N0RwSUbCterjFa2wjt//ev4aC7x0heMSEIswoDQcxozmjtWy26NttRiR60HsWgrWoT/4 70JHBQg75hYuCGs1vXemUd4v2R0Mzs32ZGzjaX6cXLqXZGlHupex3O/71JX10niXWCxt 0X2jmhxxuu1xYo0IoUxcCTsMHQIE1FzDA1rVk189BCoFsetkECAg9yH8xZpRHmlQjZcX Qd3dcV0uxSlCgQc9/RPDpdDfqOsjyQID+6e1DeApnHxBTZoBvADOvfzyqgnwp/grMV9H F6Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wk2rFtSmeyIzF6QnNFgZDZnR49h41R/PQfqDCLolPT8=; b=HHYzv6xo76RapPpISdkOPLYT4XFWLkdY844SEE+4HMUPPLXzD2fbBWU30ptZFd6ljc DS3GEjpUvGv1YBOXIHVtY0Fek75JAwHPClvKIGluaEDAJ40jHjTDhxtN7wrdBqEmiIuQ u4JbAWpv1S/0GsBPb8/qRfUfr5LrpUUYlxOJ6PIVcaJJSlvf3P2VeFF1w8lKotcKaH8S yo0YTU1xOx96qVdNQF+27DWm3w+TSS8SUCiArDN5+4tE1d44IZc9uxv2rRjRTPAAVElb 0MRpcgHV5YqaFTXlYMo2RkfZ37i/5X5oGwEoboTDLF0nqRroAhmGQxuuHsWnTJ+EeXMM JIvQ== X-Gm-Message-State: APjAAAWmPVYv/bzxLJoXVXb5Y5tVwoa9ssvdrY0L55IkexTFPOpcb+c6 3NAlIsb7DM0bosObqj00wk9eP/5iL/8= X-Received: by 2002:aa7:9156:: with SMTP id 22mr8171150pfi.246.1571420677165; Fri, 18 Oct 2019 10:44:37 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 04/22] target/arm: Split arm_cpu_data_is_big_endian Date: Fri, 18 Oct 2019 10:44:13 -0700 Message-Id: <20191018174431.1784-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Set TBFLAG_ANY.BE_DATA in rebuild_hflags_common_32 and rebuild_hflags_a64 instead of rebuild_hflags_common, where we do not need to re-test is_a64() nor re-compute the various inputs. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 49 +++++++++++++++++++++++++++------------------ target/arm/helper.c | 16 +++++++++++---- 2 files changed, 42 insertions(+), 23 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ad79a6153b..4d961474ce 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3108,33 +3108,44 @@ static inline uint64_t arm_sctlr(CPUARMState *env, int el) } } +static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, + bool sctlr_b) +{ +#ifdef CONFIG_USER_ONLY + /* + * In system mode, BE32 is modelled in line with the + * architecture (as word-invariant big-endianness), where loads + * and stores are done little endian but from addresses which + * are adjusted by XORing with the appropriate constant. So the + * endianness to use for the raw data access is not affected by + * SCTLR.B. + * In user mode, however, we model BE32 as byte-invariant + * big-endianness (because user-only code cannot tell the + * difference), and so we need to use a data access endianness + * that depends on SCTLR.B. + */ + if (sctlr_b) { + return true; + } +#endif + /* In 32bit endianness is determined by looking at CPSR's E bit */ + return env->uncached_cpsr & CPSR_E; +} + +static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) +{ + return sctlr & (el ? SCTLR_EE : SCTLR_E0E); +} /* Return true if the processor is in big-endian mode. */ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) { - /* In 32bit endianness is determined by looking at CPSR's E bit */ if (!is_a64(env)) { - return -#ifdef CONFIG_USER_ONLY - /* In system mode, BE32 is modelled in line with the - * architecture (as word-invariant big-endianness), where loads - * and stores are done little endian but from addresses which - * are adjusted by XORing with the appropriate constant. So the - * endianness to use for the raw data access is not affected by - * SCTLR.B. - * In user mode, however, we model BE32 as byte-invariant - * big-endianness (because user-only code cannot tell the - * difference), and so we need to use a data access endianness - * that depends on SCTLR.B. - */ - arm_sctlr_b(env) || -#endif - ((env->uncached_cpsr & CPSR_E) ? 1 : 0); + return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); } else { int cur_el = arm_current_el(env); uint64_t sctlr = arm_sctlr(env, cur_el); - - return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0; + return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); } } diff --git a/target/arm/helper.c b/target/arm/helper.c index f05d042474..4c65476d93 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11061,9 +11061,6 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); - if (arm_cpu_data_is_big_endian(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); - } if (arm_singlestep_active(env)) { flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); } @@ -11073,7 +11070,14 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, uint32_t flags) { - flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); + bool sctlr_b = arm_sctlr_b(env); + + if (sctlr_b) { + flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, 1); + } + if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + } flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); return rebuild_hflags_common(env, fp_el, mmu_idx, flags); @@ -11122,6 +11126,10 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, sctlr = arm_sctlr(env, el); + if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + } + if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { /* * In order to save space in flags, we record only whether From patchwork Fri Oct 18 17:44:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176920 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1184322ill; Fri, 18 Oct 2019 10:49:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqy0I3j5mkwMoYmclAuPfJOwlpSzXlZv/KvJ6tzsy0A0YvsoscWmNNvASi2UvSDvGJX1znC0 X-Received: by 2002:aa7:d898:: with SMTP id u24mr10921186edq.74.1571420991077; Fri, 18 Oct 2019 10:49:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571420991; cv=none; d=google.com; s=arc-20160816; b=qsXx1oHmU2ZpVhk1tnZfkUelU3Up/PnXo5AwMGzyL4MaZJy02U5dZ+MjCdLneg+87/ NZme0yJtKW5WSSpwkPU0oCVmV4w1fA5drtSzrBIXeCUZkoSv0lI5YQpGh6AMiVa2YefP H6oVBjtD7BaJ/ZZXM0p2AJQqPbNpANZgRdyWxS33mYqdBYxNSMC7IfT5EPDQlirckjQw fi0Yt3dW6n4hsw+/qGctEYBeVh2FL3kh4muCRF8hKk8HpUZpzQjz2qRUlBsql8FtaVRT YFx+RX2mdreUSWGtLmo2EgcWmvlsVKDcgNXpIGlOY+OMc2FU3koPOp6aa1PmRHf/fCSi MdFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mDaUYtXyoxKyQ6YIW+CzLKUl72EI9Ve9jhEUulKMydM=; b=tjCQyHGn4nHJFVkazRKcRHVUK6fePsswhS1IG9TkOPX6+pK+6n7JIs2Tt3xUfauLSS hM/uqDWq8/vN4W7JEmr5hkSvWYJIzsS9eYFD7BsXsEeQIYfYIiE/ckHG8H82rePQkVq1 3OiaD23pI1w2K4rMiSHJhz8U82DXISeHnZsh/vLsZKqn1+tkqQfiDMDP2kxXk5hpWbcg wEG7JcsGxpPTdG9UVUfuHPdPlt2n3Upk6iNesTSPK4R+jE+jHlE8KDSVJNZ0IHhBBQrJ BisKPnMN9+AOX3/nlLAtV55HqqMVYi9TbIPLsmEiD0bXxGEY3aUXRUNdowbmpNk4Bfpx 4eXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kFYtkl62; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 05/22] target/arm: Split out rebuild_hflags_m32 Date: Fri, 18 Oct 2019 10:44:14 -0700 Message-Id: <20191018174431.1784-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function to compute the values of the TBFLAG_A32 bits that will be cached, and are used by M-profile. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 45 ++++++++++++++++++++++++++++++--------------- 1 file changed, 30 insertions(+), 15 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 4c65476d93..d4303420da 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11083,6 +11083,29 @@ static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } +static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx) +{ + uint32_t flags = 0; + + if (arm_v7m_is_handler_mode(env)) { + flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); + } + + /* + * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN + * is suppressing them because the requested execution priority + * is less than 0. + */ + if (arm_feature(env, ARM_FEATURE_V8) && + !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && + (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { + flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); + } + + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); +} + static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { @@ -11168,7 +11191,13 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } else { *pc = env->regs[15]; - flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); + + if (arm_feature(env, ARM_FEATURE_M)) { + flags = rebuild_hflags_m32(env, fp_el, mmu_idx); + } else { + flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); + } + flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); @@ -11204,20 +11233,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } - if (arm_v7m_is_handler_mode(env)) { - flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); - } - - /* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN is - * suppressing them because the requested execution priority is less than 0. - */ - if (arm_feature(env, ARM_FEATURE_V8) && - arm_feature(env, ARM_FEATURE_M) && - !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && - (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { - flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); - } - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) { flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); From patchwork Fri Oct 18 17:44:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176922 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1184987ill; Fri, 18 Oct 2019 10:50:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqxhv+bdQv4EIM8oPw9WjGnnbEtQzG/IjMBhbfZvigM+lrudkCMtconWKlrOlcUqiwvWj+Wo X-Received: by 2002:a17:906:85c5:: with SMTP id i5mr9812468ejy.222.1571421034433; Fri, 18 Oct 2019 10:50:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571421034; cv=none; d=google.com; s=arc-20160816; b=KgiP9KbwWwVJdxRTKdiT4sDAFszLaf28VmyOsdEe0aNQD1wQmyBoxPNms4q0QA3iYy K1ffJn5Z4NI4KXZDn+TUuOFegycoJh4orq+HHR65X/OKmg+1O6b3CMlvvDmUrSyT2IDi 9lEK0rH1F89cMnuoIHUAatzom66Qy7cx1LVNLk5iW1aqhB8aDGDR0tx0bQL6tqF4Hm7M 94mwNgUV8aWd7DRLuIpxctNkyjUJY18PUdEwF6/Qo05kdMSMpekGsMcCl+z4UVACeQn1 Cv6pu7JVjQR3H1ALhZpJWdYCJVkNydiPmyQsIUw2B1K91YRMCQTYJxWEqhEErGnDn9Rr cWgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=O5qTDR4/yunqOnDsae4ZjoUIG4TsLVXzaOK/t5hnYkI=; b=knwPsPCQRHyoizO5P+wAGDys2q9ETzPTJYy2YVdi32ZZgnbBorsZ17MYbh8p1JmSxc gXabFf7TyVOOddUYIDC/yRib1JOeloM7RxfY+wg+8nYOmrRES9ZuSEbe1kkVgSP5CgEq wTIPKjBXWMwdh/pSkocPoXuXwj3Lwp3g43lE0JkttEdlYm7HRndeJzwRL91i7inJMMZ3 YUysPuDQZuIlnHValfCFhveWhznPZZTuc0ZKd6m0KpuzqeNhQC1GKC6Iv1fYEGNRY6t3 FTUVqbiDR7u7a/IC32WqA0xC5hJgZr0tCnfk2ZWHH5SYfw/+HRlpOFv9fQ2ByGztqGml RLZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="a/O1Fjpn"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 06/22] target/arm: Reduce tests vs M-profile in cpu_get_tb_cpu_state Date: Fri, 18 Oct 2019 10:44:15 -0700 Message-Id: <20191018174431.1784-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Hoist the computation of some TBFLAG_A32 bits that only apply to M-profile under a single test for ARM_FEATURE_M. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 49 +++++++++++++++++++++------------------------ 1 file changed, 23 insertions(+), 26 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index d4303420da..296a4b2232 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11194,6 +11194,29 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (arm_feature(env, ARM_FEATURE_M)) { flags = rebuild_hflags_m32(env, fp_el, mmu_idx); + + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && + FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) + != env->v7m.secure) { + flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); + } + + if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && + (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || + (env->v7m.secure && + !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { + /* + * ASPEN is set, but FPCA/SFPA indicate that there is no + * active FP context; we must create a new FP context before + * executing any FP insn. + */ + flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1); + } + + bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; + if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { + flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); + } } else { flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); } @@ -11233,32 +11256,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && - FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) { - flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); - } - - if (arm_feature(env, ARM_FEATURE_M) && - (env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && - (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || - (env->v7m.secure && - !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { - /* - * ASPEN is set, but FPCA/SFPA indicate that there is no active - * FP context; we must create a new FP context before executing - * any FP insn. - */ - flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1); - } - - if (arm_feature(env, ARM_FEATURE_M)) { - bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; - - if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { - flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); - } - } - if (!arm_feature(env, ARM_FEATURE_M)) { int target_el = arm_debug_target_el(env); From patchwork Fri Oct 18 17:44:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176925 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1188851ill; Fri, 18 Oct 2019 10:54:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqzc+Ur+XRCrlC14+v4liqviySk5wWHHtxt+x0eVtiGMqzcz0R6/VwJvWo+lybiweRf9hAtM X-Received: by 2002:a05:620a:1678:: with SMTP id d24mr10219105qko.349.1571421271734; Fri, 18 Oct 2019 10:54:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571421271; cv=none; d=google.com; s=arc-20160816; b=Z3lgVKIZZhiNOQi9DeMiOssNT9zG62cwckviEfrw1/w8xc02E9sPpLeuu8jbyNkZkW ekePDI8Ff48rDbFIe3aYWRoPXUkT0ywN8FL872TFmmtOL3ZAZYCd0JZP0g0y9L9cBG54 +R9JgjUJzl1TSIdBVL65vjW9WigsgAP1a73o8GCNLcQUSX7ueXBAZFZFsirI4iFpcXH0 rCKLaf9Uo3Mf6GpYdMHDwAtnhlAsoMMldT8GOkNjX+HBbNn1z7eLsIxuZZyN7ggQ76gR M+by9nirazDjCObQnrJ2jQMBDVmFHBV89rpinp2ubQYbw9mal/04LkUUZkUC3iS3Oa3k Mv4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IBA+abtZ26hlRDDlZ8eTB3Pn4yNYwZChmFB+u2JQGOM=; b=R4pPaZVRPpwAb9vLIWDuENAwRX/xsliY9QN0/dA8VwNyfz7YXQtcgPlhQzwPE5v4tf iLSN/Hbsj6QTw53DDdrld+xJ1xwgii5JTKf/tmHp12ly3APAxvMwhj6MQwG7jt4zPg2R PjbLNEy84h+cypAtz/+DbgS6Aq/mxQ58iQA7/XG8s8DRxdWCJkPa+MZQ4X5dK6tURiEH WXt/WDPO1fPptzK5xqY9lrIJDaH19RdVQNj7kqOczo2l+3tpVS1eTtUte3rye3hwPU12 Pcujkfkz0rqfnZSadeLaCHIaqLAN63cZ2gfifva0ai17F/uz+1eewJd2cXZyZN5ta6Kq 9MxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CmQzsPrv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 07/22] target/arm: Split out rebuild_hflags_a32 Date: Fri, 18 Oct 2019 10:44:16 -0700 Message-Id: <20191018174431.1784-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently a trivial wrapper for rebuild_hflags_common_32. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 296a4b2232..d1cd54cc93 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11106,6 +11106,12 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } +static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx) +{ + return rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); +} + static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { @@ -11218,7 +11224,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); } } else { - flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); + flags = rebuild_hflags_a32(env, fp_el, mmu_idx); } flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); From patchwork Fri Oct 18 17:44:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176931 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1200719ill; Fri, 18 Oct 2019 11:05:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqwGDuHshdFk/EWT7hwz7kNylX+GWgWg0hntI3atgwvj2PmZ1c8lsaTfOOrWy6kPUc2KxmGF X-Received: by 2002:a37:491:: with SMTP id 139mr4011816qke.200.1571421907039; Fri, 18 Oct 2019 11:05:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571421907; cv=none; d=google.com; s=arc-20160816; b=aQcFoJfnn/eYi/wwLvA7aZ8YTIGmU1SYwVtXOI+m8BVLLppmrov2MqhVvo5CLZKrJa sgXP1tMq9oM2CLoCahL/VKTeHUswsaPx2QLQDR+bPA0ntP0mgWmwd5eRPwWWwSzua8wS TYOWtvVPmyvaNfjZswDJtapUOHF0Hg0Jz5rehXfduBVsd19cFb43TsfY7VOiysCkLFcV KFdEfiQDVknwpJqlAGkDMLMwzf9FsDxt6YIN62unq+TlB5EUMX3fV79rS5CtxoVsKVY+ 0oZbcPlPFrLIoQP1az982VPuTxeSCvl7QkLAGZMw54gJZmK8PO6FLg/0q/hvS6xcTZKl 9eOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EExBny+oAa/2RvpDTj0xViQxKJSM6o83jutlTagIpwU=; b=BP8sDIduJbILXZs9hayuWoh1HEa+63NyJ3md0rkn5i4HhtNmEguXEsPkc+zCoXbUov YeQRF3tsu8ycmk7yq7yR9yI8SzetAjjFbEuznWdN5jc1RLauOEyIyevoZ571AkNvQbT3 kpl7fi8lbNBwu1MqFQ2Sv5vmQbcAtYWjf+idTu2SaPQqLjdq9CtwqH5y0YROx53C1Q8K prhz8mt9XRsD6ErR1WB6gUK5AYZl5ZY1WAQEEGnJi0YhFKTCTnekH2IWpSNVEZ23s2JP 2Qc9EF2NtfyI/h6DHSbHOa09nv9bEJ08AytmzcEQfMPTrymYlPzZO+kj+t+J/NdPRNLt LS2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jqqk+gJi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 08/22] target/arm: Split out rebuild_hflags_aprofile Date: Fri, 18 Oct 2019 10:44:17 -0700 Message-Id: <20191018174431.1784-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function to compute the values of the TBFLAG_ANY bits that will be cached, and are used by A-profile. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index d1cd54cc93..ddd21edfcf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11106,18 +11106,28 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } +static uint32_t rebuild_hflags_aprofile(CPUARMState *env) +{ + int flags = 0; + + flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, + arm_debug_target_el(env)); + return flags; +} + static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { - return rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); + uint32_t flags = rebuild_hflags_aprofile(env); + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { + uint32_t flags = rebuild_hflags_aprofile(env); ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); - uint32_t flags = 0; uint64_t sctlr; int tbii, tbid; @@ -11262,12 +11272,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } - if (!arm_feature(env, ARM_FEATURE_M)) { - int target_el = arm_debug_target_el(env); - - flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, target_el); - } - *pflags = flags; *cs_base = 0; } From patchwork Fri Oct 18 17:44:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176923 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1185037ill; Fri, 18 Oct 2019 10:50:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqwCoPRYyvclaYSTXDMhYWGyzWtrVFOnnI/zyrE4G8UFdCgj/SrEg66DuHhlNVJufTo2iwLD X-Received: by 2002:a17:906:9aa:: with SMTP id q10mr9640054eje.93.1571421038772; Fri, 18 Oct 2019 10:50:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571421038; cv=none; d=google.com; s=arc-20160816; b=vBpzIdZpKnGfa+NYxlCTVwAMg344AFqTgqLCOKwAh35oAaabkXWk46AXm8144r+rrf vo6x0IkjdS8J2wFgi8mZROF11M8V/YnrKy+dDo/Md5hJYbYvHJxhXnUei8n7BPXJaJzj f7nySTITIF2d6SCb9SJElJ2ZmOddaaxQ5ezfyuz2lGRuMuFoblgDHlxBodzeH3iWdRl9 xVWy94/kNyFmLHbbMITK+i71CpzUoa+OwnsjLpatRkYDDPRkLfOGhjaCFT1mktXneEsr lnc/pwFBep7yZ8sGh0cxexnO8XQqGyW4NpcUdzlTK6xzn0u95VAnu7o+LC6GVg9EcFFE F34g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+w+DpqTaqyThsFD3h0g6qTaqlae+kRMVgywC4mwAkDA=; b=oCN3tIr/V8nmKsxt8XhnHPFru/Ac/dol8w2Af8vx93zlmk0RNSbTk0a7HCh+Du2B6Y TvScJmr+0YHqCNzy/fcUixjHu1RxPByfnHkSny5iYNrQJsG6itDEyaxZ5deG6PMnrFWT 4GPXWGPuDMwQPFsGz311kmtrO2CD6cEY/+R47bGs8irbdyxa5v157CfA99/P5lSWY8zX raVQCelmM8xzD8vu7kVp04k39k3CWxMl+pC7G5iF1MYS1Pz05RCDcAZ96kvAcIdWz6Hm Ra97935Z1iDyUv16HAiHSvS8R/Y09AyTwfYk3Aqw0b/aBsL+CpBbp4Ma1GxKAxdf+0Xo WEwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XRL03tO8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 09/22] target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state Date: Fri, 18 Oct 2019 10:44:18 -0700 Message-Id: <20191018174431.1784-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We do not need to compute any of these values for M-profile. Further, XSCALE_CPAR overlaps VECSTRIDE so obviously the two sets must be mutually exclusive. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index ddd21edfcf..e2a62cf19a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11235,21 +11235,28 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } else { flags = rebuild_hflags_a32(env, fp_el, mmu_idx); + + /* + * Note that XSCALE_CPAR shares bits with VECSTRIDE. + * Note that VECLEN+VECSTRIDE are RES0 for M-profile. + */ + if (arm_feature(env, ARM_FEATURE_XSCALE)) { + flags = FIELD_DP32(flags, TBFLAG_A32, + XSCALE_CPAR, env->cp15.c15_cpar); + } else { + flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, + env->vfp.vec_len); + flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, + env->vfp.vec_stride); + } } flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); - flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); - flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); } - /* Note that XSCALE_CPAR shares bits with VECSTRIDE */ - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - flags = FIELD_DP32(flags, TBFLAG_A32, - XSCALE_CPAR, env->cp15.c15_cpar); - } } /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine From patchwork Fri Oct 18 17:44:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176934 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1204283ill; Fri, 18 Oct 2019 11:08:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqyuoekMeCb52OX4a3ym3DsjLyD52r/YdRuL7SiUyj/k9FjFh9CjsUjUltWEGjYxcuaA9pnE X-Received: by 2002:ac8:741a:: with SMTP id p26mr4553150qtq.143.1571422080145; Fri, 18 Oct 2019 11:08:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571422080; cv=none; d=google.com; s=arc-20160816; b=DsK0sFsksL0jF0H9lUEM0eaPyWzCfU2eeM9EHlW+hcKHt3homa0mOqNveTv4N7HbZB JxqY8LXiZj5TRhHXWEwHvgZiY8huRprDoQ1kmqp85O367IDZwN7CD++7CQsqATCxzr4P se+WUPxcfJckd0aAWD5nZlepkS33zHJDezzwHcb0LSbsYg3doHKZnrljGr1uKVflOAIO cevZaiZbQOvkoOPZbPNxJGJ9guUIVZJVQddNTMm0kComjdFBcubP+WX6hoKbvIufnZGl nWbVukrSW1Ec0mquM8JCSq/KQTXLeGCcvf4i5/nckxJQSmLku9I4vIgJu3QJwaV5vmOO zVbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=v4LDoKiCDj8UEOXKdxGeWLogI6gqriKirwE9ruJcfe0=; b=dhsEJ/0yfj69rjpcgJAMhiMk6KFM8taKqKMmZMp/6yHdRPgDLfNYbjfmE64uizfnC/ /JfpkIKhq9PTMR+cbn5nm6PiWA4++XZHVYkbWcX43DUha9AZ4RzP8l8xoic869+V8x9O /db7LbjtAZyspA7Amw5vzICcKJtJ7wC9/j0eph4ooODSlORj5MCllDS5AeTL8ni/BQMB RSBLLYsiD7svM2Hjxh3dKvI3MWhLSCpWXs5900sWRbeuKWzvf51vKSUZ3rvn+N2sfVKF jeE95m9HSfJOxxfTo2i7dpqxZS7wTCZv1MEgsYSC2biZb8kB+1/RyoegHspOu3WaBMdj 0SGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pWIoIHOz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w7si6420258qvf.1.2019.10.18.11.08.00 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 18 Oct 2019 11:08:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pWIoIHOz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44644 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iLWfP-0006Bf-70 for patch@linaro.org; Fri, 18 Oct 2019 14:07:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59256) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iLWIx-0006Z0-1i for qemu-devel@nongnu.org; Fri, 18 Oct 2019 13:44:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iLWIv-0005Sv-SA for qemu-devel@nongnu.org; Fri, 18 Oct 2019 13:44:46 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:33113) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iLWIv-0005SG-N4 for qemu-devel@nongnu.org; Fri, 18 Oct 2019 13:44:45 -0400 Received: by mail-pg1-x544.google.com with SMTP id i76so3773056pgc.0 for ; Fri, 18 Oct 2019 10:44:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v4LDoKiCDj8UEOXKdxGeWLogI6gqriKirwE9ruJcfe0=; b=pWIoIHOzUUgQIGhlSzHdOdcPTYTWLBK97r2ZWl9k015vOd2yzVVP+iljAdQzhj4WBj el2sVOFN3Gxe2v1gpdI7NJrlWBsEvCZuegNIlLif6TVPt70MZpkCtOsYmv4mAl7Il+hV xZFZyk4eP5/ytJB6oC1coEAbB1yMSBYqOoX+Pb8Ck9Q7tzvc9xIalZtyB2eolkQq/XzB ZAWsZMOdGojYoCjCNRBoj4KEPRRBmuo7qQyCej+Ka6usaFP0NC4vUVqjWYtNKfGRmfLK iEGsBErXfpg6lrZzzTftIiNkSSRf8M2kmwSxILqxBPlDXBQee/aggExOmwN2Wuo2a1aY 9eAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v4LDoKiCDj8UEOXKdxGeWLogI6gqriKirwE9ruJcfe0=; b=EbV8N4XRdnQs9w60Eja+BC+g6DSihvDSf+LWDmYcPoEVewPC7eyfCxl5fn5624k60S 0BAI76JBqtU6PQeVUvsJzMfc+bYy1ucDIznWDvwB0jaqPx5kSPWkj/8aRricaXNxKkPb 3O/0b3aHtoXLbiF4WmHi8DQMR3vQNSciwj/H+TiCQVWQSx2soAs+QxmKXf/RUtDqcR2t jFoXVfdMC+tc0qESU61uGLsZNQCNQAqJ8vWYw8B1SwtgAcOEmgv9NSv9luB1BnHuPYHE 7rhMO1p9UimC7OZTVniBSUjXkRTE9k0ACsz9Hu74CJH27GmPGFeJ/MkoKvF0NFkKeSsa SQOQ== X-Gm-Message-State: APjAAAVAYVPQonJS7NduviscQtTGGwWycqM7Som9eZrzrNN6FZz6BFnt 89veoCD7dc+KgHRdxUGPy/PafAwCqAM= X-Received: by 2002:aa7:908b:: with SMTP id i11mr8245647pfa.186.1571420684462; Fri, 18 Oct 2019 10:44:44 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 10/22] target/arm: Simplify set of PSTATE_SS in cpu_get_tb_cpu_state Date: Fri, 18 Oct 2019 10:44:19 -0700 Message-Id: <20191018174431.1784-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Hoist the variable load for PSTATE into the existing test vs is_a64. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index e2a62cf19a..398e5f5d6d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11197,7 +11197,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, ARMMMUIdx mmu_idx = arm_mmu_idx(env); int current_el = arm_current_el(env); int fp_el = fp_exception_el(env, current_el); - uint32_t flags; + uint32_t flags, pstate_for_ss; if (is_a64(env)) { *pc = env->pc; @@ -11205,6 +11205,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } + pstate_for_ss = env->pstate; } else { *pc = env->regs[15]; @@ -11257,9 +11258,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); } + pstate_for_ss = env->uncached_cpsr; } - /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine + /* + * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: * SS_ACTIVE PSTATE.SS State * 0 x Inactive (the TB flag for SS is always 0) @@ -11267,16 +11270,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * 1 1 Active-not-pending * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. */ - if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE)) { - if (is_a64(env)) { - if (env->pstate & PSTATE_SS) { - flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); - } - } else { - if (env->uncached_cpsr & PSTATE_SS) { - flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); - } - } + if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) && + (pstate_for_ss & PSTATE_SS)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); } *pflags = flags; From patchwork Fri Oct 18 17:44:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176936 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1206754ill; Fri, 18 Oct 2019 11:10:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqyW7m8fRK7q8zLTqL/gC971j7WijbrHyP6tnWF/H2FFzhcxC2fM7NyI8jxkfeU8Fk9BQVJI X-Received: by 2002:aa7:c6d0:: with SMTP id b16mr11263688eds.108.1571422204497; Fri, 18 Oct 2019 11:10:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571422204; cv=none; d=google.com; s=arc-20160816; b=v87CzIMMRXQ8VRt3ATmej7SHdgsdwZBk0s9f3HmoG9vEtmC+MX1kttr/h0LL/g8Y6F RflQGfNxVQlV78FmT1HPbpAMfZ3XqdWIMqIlUjflXQCUTwCh7vjaALDXMQf7Jo8FwMp/ 2BAofCl07jOfki3bhwRYt+CAYjWrS4rxaS6R98js0/635GnRRrVIKbAorqeMaqkOUDSQ gPkuO0ZnwS5uBDdlLC1C2M37NIKsabT62fdcEZnCJqrGI8DNSZNy5TAwpEVn4yC44UIV QyB9UVkLgN82cOWPfHPAg2+KIGhKTq1OBO4vD9kVxh6oTAXlUCxmLVMCTq/YLC9e387h 9Fgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HNW+DKXClNFoWE5mAVnYOdmYoSifNB4F8oskeNBuM9U=; b=NEpDf3Tm956YReo80b7cR3XI7pcQRo9l9wKTaqU7NO7Tm2AMxdz3f+QNWgWb/GAFoF X9CwDbQnZEPJ52/l2hK26HhNyfZNwhRcUQbLA5R2KRaDm2FoJvpmflGgkTHzdEg0D6B2 e6H/l7mSrohWyPpwma5Fm+GBLy+5X4A+kOjvkc5XROl8sheaV1qtFk4zDO0W45Rm/Q/x 4YWz9ji0BOF8b9DLi8J3gE4+PB3rnBgGWUTY6e4/wmsbUJJ9fIlDilLDvEwur0x+ssEA bFzok7b7TihBkFJZxr9NEglrYp4Jk7Yw5Kf1/XUO/VtVFBbzEdqW/exk7OuLJ8O/f19Y X/0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=X5gHWOT2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 11/22] target/arm: Hoist computation of TBFLAG_A32.VFPEN Date: Fri, 18 Oct 2019 10:44:20 -0700 Message-Id: <20191018174431.1784-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There are 3 conditions that each enable this flag. M-profile always enables; A-profile with EL1 as AA64 always enables. Both of these conditions can easily be cached. The final condition relies on the FPEXC register which we are not prepared to cache. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 +- target/arm/helper.c | 14 ++++++++++---- 2 files changed, 11 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4d961474ce..9909ff89d4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3192,7 +3192,7 @@ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) * the same thing as the current security state of the processor! */ FIELD(TBFLAG_A32, NS, 6, 1) -FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Not cached. */ +FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) /* For M profile only, set if FPCCR.LSPACT is set */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 398e5f5d6d..89aa6fd933 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11088,6 +11088,9 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, { uint32_t flags = 0; + /* v8M always enables the fpu. */ + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + if (arm_v7m_is_handler_mode(env)) { flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); } @@ -11119,6 +11122,10 @@ static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { uint32_t flags = rebuild_hflags_aprofile(env); + + if (arm_el_is_aa64(env, 1)) { + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + } return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } @@ -11250,14 +11257,13 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); } + if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + } } flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); - if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) - || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { - flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); - } pstate_for_ss = env->uncached_cpsr; } From patchwork Fri Oct 18 17:44:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176924 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1188297ill; Fri, 18 Oct 2019 10:53:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqwE7bfxBEG8UMqkl6hhXHj4++DxBACYVcT5W89nNZEsU6o+CDbsUCLkdiPdaAGdQnbSeB6r X-Received: by 2002:ac8:44da:: with SMTP id b26mr11458215qto.299.1571421234042; Fri, 18 Oct 2019 10:53:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571421234; cv=none; d=google.com; s=arc-20160816; b=GsuN1Sl4i8Lu9mJdFGijC8+YPPWp1p4HHYw4Jnw+BS5TeTgIdC34niQeSIim9WmynI rNrhTkjX7O6tw1Z/bl7s4U3lXwCVH5W2bBaWxthT6wuuXYtIwSAQ2vBfbakXfnFsR/i6 fl6kC4Im7VsHzE+1SNGp1ewe747g11QXQOXg0WXQ2lWsESmRw4p8ihw2WOxo5Mhnp7kz PZ/OY1GSKItN78+Lglaaz23GASd/+bmQScdi34eYusYK8FSTaXVYvH7FNb3VJlAluxqK QUmW00MKv/oErz0DwpWZYDOR8V9p0Y5C+wjfNBG6NH8ZAvi99ZTmRz0Jj6exW7uXLJvu 0HWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PtanC1h+OlQIbLy4htGIe38tBGV1DOrNspWjSEGlJl4=; b=ol4Db6IMhKLsVaSzZ4tXhf29Y0rTkRI8ZiDcEctWegIBTjIOu5riDxdTauWg1z6Q6Z QaSWbYlKCHCqlzsYsJKF8bYVAQ6ql7MtMntRBanBBTMuux0HyLla2KAuTz/J1zUGJozT GXR6xKjxsXrA+JCavsaNAEra88kgkKhzOyhmhj6dhxrPY1BB1kKG2uRWCvIvGcPpep2e 6JRAGAoYCSjyDIG3dPrp9TMRBC6PamJV9f0Sq/CRktzYW+dcl6jvb/xgIkRBMzMMX4JX CAfrVlaa1hfkrs0kDBJVRwCKkbSssmfFYXNnpb1OwvfpmIF8xb5ujDE3LaarknopTYcZ Y85Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FPZScvTz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 12/22] target/arm: Add arm_rebuild_hflags Date: Fri, 18 Oct 2019 10:44:21 -0700 Message-Id: <20191018174431.1784-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function assumes nothing about the current state of the cpu, and writes the computed value to env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 ++++++ target/arm/helper.c | 30 ++++++++++++++++++++++-------- 2 files changed, 28 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9909ff89d4..d844ea21d8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3297,6 +3297,12 @@ void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque); +/** + * arm_rebuild_hflags: + * Rebuild the cached TBFLAGS for arbitrary changed processor state. + */ +void arm_rebuild_hflags(CPUARMState *env); + /** * aa32_vfp_dreg: * Return a pointer to the Dn register within env in 32-bit mode. diff --git a/target/arm/helper.c b/target/arm/helper.c index 89aa6fd933..85de96d071 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11198,17 +11198,35 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } +static uint32_t rebuild_hflags_internal(CPUARMState *env) +{ + int el = arm_current_el(env); + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx(env); + + if (is_a64(env)) { + return rebuild_hflags_a64(env, el, fp_el, mmu_idx); + } else if (arm_feature(env, ARM_FEATURE_M)) { + return rebuild_hflags_m32(env, fp_el, mmu_idx); + } else { + return rebuild_hflags_a32(env, fp_el, mmu_idx); + } +} + +void arm_rebuild_hflags(CPUARMState *env) +{ + env->hflags = rebuild_hflags_internal(env); +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - ARMMMUIdx mmu_idx = arm_mmu_idx(env); - int current_el = arm_current_el(env); - int fp_el = fp_exception_el(env, current_el); uint32_t flags, pstate_for_ss; + flags = rebuild_hflags_internal(env); + if (is_a64(env)) { *pc = env->pc; - flags = rebuild_hflags_a64(env, current_el, fp_el, mmu_idx); if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } @@ -11217,8 +11235,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, *pc = env->regs[15]; if (arm_feature(env, ARM_FEATURE_M)) { - flags = rebuild_hflags_m32(env, fp_el, mmu_idx); - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) { @@ -11242,8 +11258,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); } } else { - flags = rebuild_hflags_a32(env, fp_el, mmu_idx); - /* * Note that XSCALE_CPAR shares bits with VECSTRIDE. * Note that VECLEN+VECSTRIDE are RES0 for M-profile. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 13/22] target/arm: Split out arm_mmu_idx_el Date: Fri, 18 Oct 2019 10:44:22 -0700 Message-Id: <20191018174431.1784-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Avoid calling arm_current_el() twice. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/internals.h | 9 +++++++++ target/arm/helper.c | 12 +++++++----- 2 files changed, 16 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/target/arm/internals.h b/target/arm/internals.h index 232d963875..f5313dd3d4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -949,6 +949,15 @@ void arm_cpu_update_virq(ARMCPU *cpu); */ void arm_cpu_update_vfiq(ARMCPU *cpu); +/** + * arm_mmu_idx_el: + * @env: The cpu environment + * @el: The EL to use. + * + * Return the full ARMMMUIdx for the translation regime for EL. + */ +ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el); + /** * arm_mmu_idx: * @env: The cpu environment diff --git a/target/arm/helper.c b/target/arm/helper.c index 85de96d071..3f7d3f257d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11026,15 +11026,12 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) } #endif -ARMMMUIdx arm_mmu_idx(CPUARMState *env) +ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) { - int el; - if (arm_feature(env, ARM_FEATURE_M)) { return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } - el = arm_current_el(env); if (el < 2 && arm_is_secure_below_el3(env)) { return ARMMMUIdx_S1SE0 + el; } else { @@ -11042,6 +11039,11 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) } } +ARMMMUIdx arm_mmu_idx(CPUARMState *env) +{ + return arm_mmu_idx_el(env, arm_current_el(env)); +} + int cpu_mmu_index(CPUARMState *env, bool ifetch) { return arm_to_core_mmu_idx(arm_mmu_idx(env)); @@ -11202,7 +11204,7 @@ static uint32_t rebuild_hflags_internal(CPUARMState *env) { int el = arm_current_el(env); int fp_el = fp_exception_el(env, el); - ARMMMUIdx mmu_idx = arm_mmu_idx(env); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); if (is_a64(env)) { return rebuild_hflags_a64(env, el, fp_el, mmu_idx); From patchwork Fri Oct 18 17:44:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176937 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1207244ill; Fri, 18 Oct 2019 11:10:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqwtXswkb8KzveA/TfYc0qc+M6N2Xvk4/xPn7UZ5/ncb5YS189Nuk4JEJ1F3Pb7b1bxVKEes X-Received: by 2002:a17:906:3ec8:: with SMTP id d8mr10089993ejj.57.1571422226401; Fri, 18 Oct 2019 11:10:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571422226; cv=none; d=google.com; s=arc-20160816; b=hUZEODCPEC3D4oVT1o5VsSMict2s1opVMzYMsldSHlQy9hpXKjJAfBq5rwIRrISx5E nHp2R7YvjBai0Nbm0sY9iRcKjPI10FfjMmAlxv8Tu7Uav30MJSdtT4Kg/r+DXS5zpcB1 czVyTZU3usiOQ9JDyIu/O0a0NQ6avqpfst8AZ/OKu+vMPYLc/Uq08GokuBq4NiiW/B+s kjaVQ37Cyj766URzbfXNxm65Re/s95/23tfptixi/AYvyJkVStzbOW4gCqL9/5ieeyGa tbDUxTfosoIiBdfDW2gC5Ba5k2svyTlmThjja5cTjSTwLwCleuSevv5r3m2E+P+f2JNn xeUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bIwXZuVFcex8c2gsnRtwJL32LXPTCWgJCQzC/Gsa6O8=; b=R3hk8jAydzfiQ6m6CjzFcn1M4KovsvV4EQcYMrduhtm5t55S5OUyr/azEWSm9SD9sS bM1l6PjiKEtcUTOUPNJo79/kViOzFhg/829WDzt3xNNXUsDlioyqUHmPd1PoiixOqn5F AYKnl1MCXWgWrsVr0yeQjOC70xA+1kYtaMoLOjjTXd5RYmfCMbVCsPySssvWgCQQ5Rpi XThmNXFLAW1ivwffwWgPI+Rjjvg8IhU2Icq1qsh53i2BehBIhgirS2dC8eaQfRnV6HYT s7ghlkFM6Lr2tHbtq1pGCd2tp1qWKq3p9P8OWIB4XDV8xVLvEwvGOILVhbBow2f6H3uS dlEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SNMbParS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 14/22] target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state Date: Fri, 18 Oct 2019 10:44:23 -0700 Message-Id: <20191018174431.1784-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" By performing this store early, we avoid having to save and restore the register holding the address around any function calls. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 3f7d3f257d..37424e3d4d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11225,6 +11225,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, { uint32_t flags, pstate_for_ss; + *cs_base = 0; flags = rebuild_hflags_internal(env); if (is_a64(env)) { @@ -11298,7 +11299,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } *pflags = flags; - *cs_base = 0; } #ifdef TARGET_AARCH64 From patchwork Fri Oct 18 17:44:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176926 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1191142ill; Fri, 18 Oct 2019 10:57:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqyrJ3CiN5BX9Ca4ksavLQ3yy0lmmhqbpFkUFWkndMldGcdXHHI7qL2xbPhNOm+DFVfDqL2B X-Received: by 2002:a17:906:2408:: with SMTP id z8mr10149608eja.260.1571421423779; Fri, 18 Oct 2019 10:57:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571421423; cv=none; d=google.com; s=arc-20160816; b=xd/7oUL99SqaiBL5ZKbgG09CbEbGU99dUTwKml3aSl7AHbCBFepExjpwrNUUoV2nWz u4Cxu6+6f2/1XShux/AR9Amqu38noUxViaK14yBHo0hNFBeaSPC2bB0FRgD8s0FH2P0h y+67N/SFNVJJED4KEb3W5eUDlsEiuVqCr6eahXCF46vGvznRpkxnlJDJbceimTYidj6V OPFIFOPdYpIW/Sh/jpAv+7njbxIH2ybglanxmo+6hn2v0azm6TYQj/XLgcDAg/ZVvcMO //z3LISQmKNRv5eeDml9dEwKCY5z8AqK718Yqz0mYwy2eStaCMD/eBDzJ/kMaZcKpWq7 b/hg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ksJ29EsO4EC0RqRT/ptTGb/nh233vty3hFHL48/i7gI=; b=WgRm67watqcaxZ+TAYdRIA/uRL4lS7ln8yxnLUrT5Ch1iEmuKg6mvyyHd6shG417qn De6vz4gD1QwnkmPcTZ35+y7zBTCv6PypUId2w632q/8RuCJDFXzlF/uWDfeNQT7eGJDD qc905SOn1VtOBwmvim1t3wP4JVy8dfgRzLXYMV2XE5mURY8faqD7y3io5iURSBloEWTH DTyjgnjs9vdysFFY+nkk2+SanlVRn7EjgATtSpLlVvpDd53C2V+PL93YWh1lADAZ9gMK YRkFHe4LMM3GrSMUaKVZS+kBwP5qw5Lzev3p4sbvFUd05VtZkK8K1I8p3VEGXrG+iAAm BpBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hZHwdPeE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 15/22] target/arm: Add HELPER(rebuild_hflags_{a32, a64, m32}) Date: Fri, 18 Oct 2019 10:44:24 -0700 Message-Id: <20191018174431.1784-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This functions are given the mode and el state of the cpu and writes the computed value to env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.h | 4 ++++ target/arm/helper.c | 24 ++++++++++++++++++++++++ 2 files changed, 28 insertions(+) -- 2.17.1 diff --git a/target/arm/helper.h b/target/arm/helper.h index 1fb2cb5a77..3d4ec267a2 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -90,6 +90,10 @@ DEF_HELPER_4(msr_banked, void, env, i32, i32, i32) DEF_HELPER_2(get_user_reg, i32, env, i32) DEF_HELPER_3(set_user_reg, void, env, i32, i32) +DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int) +DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) +DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) + DEF_HELPER_1(vfp_get_fpscr, i32, env) DEF_HELPER_2(vfp_set_fpscr, void, env, i32) diff --git a/target/arm/helper.c b/target/arm/helper.c index 37424e3d4d..b2d701cf00 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11220,6 +11220,30 @@ void arm_rebuild_hflags(CPUARMState *env) env->hflags = rebuild_hflags_internal(env); } +void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) +{ + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + + env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); +} + +void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) +{ + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + + env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); +} + +void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) +{ + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + + env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx); +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { From patchwork Fri Oct 18 17:44:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176938 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1208852ill; Fri, 18 Oct 2019 11:11:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqzMr7BTlXAgPQMihQCdofKO6BIZpge1GenY4FbxgZ4bPY8kdzEUEikeVfBjUhYXJgvtP1Lb X-Received: by 2002:a17:906:55d1:: with SMTP id z17mr10001303ejp.300.1571422304637; Fri, 18 Oct 2019 11:11:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571422304; cv=none; d=google.com; s=arc-20160816; b=BRnPQwAF9CL5nXDCErT13CtbPZVCKLoz3qaBwYoTAdl3awND/y5yjLLRCnmvDUzH16 DvpTZjEYlEt4ceYK1trpkOAhD/EZAxn+Dtu9pSPN1/6UDX0Qa8zLpx48BODjWYg2Nbrs 2SvaZEcSzMNVLOfasdS0h1imaDYK2+xDWCKtOgMrmL/h7jTQSpR+R/R2SPejO/0DnIaY WWD4fv3br2MlQUMdr4RS9Yk+JH/ykEkjwv9+X25cekTYdILoTu+kxrGI4eo0xU7bV4/N vlXbxemygnROmvMzjpEPR/SNu6pYriSQr5RM4srpbMp94wTllteSEIHIs4apc+3Xx6OD o8rQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Lq3/b5OXsgTHbcSMFLOFHm3tF7v/Y0wC/PpxwPnfroE=; b=L0oFAxDDHA2JBpz+2aniXlRnIC7yC5EqQNSwWtJq9MiQHH+6kYIRJaBvCUhJLeLdtI bY5EgDhvrl+rkPouRfe2PnoykBlsB5fVST+IEwWZuow9AQyafA2kFxP17bA8130rndFu j1kStWrBsyAg+rmR1vU1yCPb4UGOaAvKBb2HYHD69Bk/g89VXgEZYYgXIjFQpzt5cZjR c3P6oxsAI6Nr5uO+Vpd0VBggMTdJXhzl4yN46bk29o+Neaw4gpR1pMU2eqztTyMH6L1G DrArthJm9IKz2g5N8qvT6xDxahhJJX0MWHqtQoftMtrVd5cYDtmMhdLtnU2Et6KDV3ev sgDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ztf1GH7v; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 16/22] target/arm: Rebuild hflags at EL changes Date: Fri, 18 Oct 2019 10:44:25 -0700 Message-Id: <20191018174431.1784-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Begin setting, but not relying upon, env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- linux-user/syscall.c | 1 + target/arm/cpu.c | 1 + target/arm/helper-a64.c | 3 +++ target/arm/helper.c | 2 ++ target/arm/machine.c | 1 + target/arm/op_helper.c | 1 + 6 files changed, 9 insertions(+) -- 2.17.1 diff --git a/linux-user/syscall.c b/linux-user/syscall.c index e2af3c1494..ebefd05140 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9982,6 +9982,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, aarch64_sve_narrow_vq(env, vq); } env->vfp.zcr_el[1] = vq - 1; + arm_rebuild_hflags(env); ret = vq * 16; } return ret; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 13813fb213..ab3e1a0361 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -406,6 +406,7 @@ static void arm_cpu_reset(CPUState *s) hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); + arm_rebuild_hflags(env); } bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index bca80bdc38..b4cd680fc4 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1025,6 +1025,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) } else { env->regs[15] = new_pc & ~0x3; } + helper_rebuild_hflags_a32(env, new_el); qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch32 EL%d PC 0x%" PRIx32 "\n", cur_el, new_el, env->regs[15]); @@ -1036,10 +1037,12 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) } aarch64_restore_sp(env, new_el); env->pc = new_pc; + helper_rebuild_hflags_a64(env, new_el); qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); } + /* * Note that cur_el can never be 0. If new_el is 0, then * el0_a64 is return_to_aa64, else el0_a64 is ignored. diff --git a/target/arm/helper.c b/target/arm/helper.c index b2d701cf00..aae7b62458 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7998,6 +7998,7 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->regs[14] = env->regs[15] + offset; } env->regs[15] = newpc; + arm_rebuild_hflags(env); } static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) @@ -8345,6 +8346,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 = 1; aarch64_restore_sp(env, new_el); + helper_rebuild_hflags_a64(env, new_el); env->pc = addr; diff --git a/target/arm/machine.c b/target/arm/machine.c index 5c36707a7c..eb28b2381b 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -756,6 +756,7 @@ static int cpu_post_load(void *opaque, int version_id) if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } + arm_rebuild_hflags(&cpu->env); return 0; } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 0fd4bd0238..ccc2cecb46 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -404,6 +404,7 @@ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) * state. Do the masking now. */ env->regs[15] &= (env->thumb ? ~1 : ~3); + arm_rebuild_hflags(env); qemu_mutex_lock_iothread(); arm_call_el_change_hook(env_archcpu(env)); From patchwork Fri Oct 18 17:44:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176933 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1201337ill; Fri, 18 Oct 2019 11:05:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqznjPFMigVoU5PMqERYp9tX4fh7FHc/nZNtRTOhfPk9xB/wzdTfvxEir6qDt47MAlGOZSsv X-Received: by 2002:a0c:c590:: with SMTP id a16mr11260833qvj.144.1571421933317; Fri, 18 Oct 2019 11:05:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571421933; cv=none; d=google.com; s=arc-20160816; b=xeGBUzCSuhgt8QSltraoulmA1qbsECLnZJ5VAvEI4gEA3SxHpDe8RuGYedNv76sL6E wnKjh1Jf8HVpu67YPFUC9lBWoIkwXRBnebz4sJJA2Uc+oos+YHEyaQ+m63whu2Pe9hwv KHE/ze1EjoeNtPaRYJTsOoXH9EiSEaQFgjHcSj0NHa+EYQDe8Md5QUA6aMeBth+cwwYz YuI5tn2FJdajINxTRSvHlJWH+i3NKDQ4UlHxsv16JMjuHH3FeEr7ZCg+ZxxxEs7pr/zP rLMeTezZGmDrOaRUM/oHzVAJke5M27fJ6gq5e10HE4a1ICl4nKD0by6RIP5RLkhhFn1J j84g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0mb3YwiZncjKHxGhu+AsTIpQEFeyLEnUoSMmhup1oAE=; b=vQcMYctxubHW5YsqhBVGhps6zrftcFHLVFie7RVKzhtesRYucwcVwJsMXig+qtl77D g0aGH82vTOqHmhSn6ND+0EedztlqxW6Zk+a+kcEVk49EbGfqPo2s2QNhYGHzyj32phW+ 6qt3b0R8is0phXynqz+aAflaNWIy5FBF6E9kWC9x9BeA+UJBuOMJ9aTh4BMx7YPblDtJ 9WPVNNL4fqNkHOXuclbi0V3bwiRVPyW5RvQJZoHvK7x1W5O3yXnDvgSQ+olDan8t6tBA hqQf1ob8xAHbBXzxdvXLBzb7rEU2VRzICkqXfwjaPqXPm77IGt8jE1zZwUaVmEyUDXyS TXSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Jwr7py+b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 17/22] target/arm: Rebuild hflags at MSR writes Date: Fri, 18 Oct 2019 10:44:26 -0700 Message-Id: <20191018174431.1784-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue setting, but not relying upon, env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 13 +++++++++++-- target/arm/translate.c | 28 +++++++++++++++++++++++----- 2 files changed, 34 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2d6cd09634..d4bebbe629 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1789,8 +1789,17 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ s->base.is_jmp = DISAS_UPDATE; - } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { - /* We default to ending the TB on a coprocessor register write, + } + if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { + /* + * A write to any coprocessor regiser that ends a TB + * must rebuild the hflags for the next TB. + */ + TCGv_i32 tcg_el = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, tcg_el); + tcg_temp_free_i32(tcg_el); + /* + * We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 698c594e8c..cb47cd9744 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6890,6 +6890,8 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) ri = get_arm_cp_reginfo(s->cp_regs, ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2)); if (ri) { + bool need_exit_tb; + /* Check access permissions */ if (!cp_access_ok(s->current_el, ri, isread)) { return 1; @@ -7068,14 +7070,30 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) } } - if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { - /* I/O operations must end the TB here (whether read or write) */ - gen_lookup_tb(s); - } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { - /* We default to ending the TB on a coprocessor register write, + /* I/O operations must end the TB here (whether read or write) */ + need_exit_tb = ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && + (ri->type & ARM_CP_IO)); + + if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { + /* + * A write to any coprocessor regiser that ends a TB + * must rebuild the hflags for the next TB. + */ + TCGv_i32 tcg_el = tcg_const_i32(s->current_el); + if (arm_dc_feature(s, ARM_FEATURE_M)) { + gen_helper_rebuild_hflags_m32(cpu_env, tcg_el); + } else { + gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + } + tcg_temp_free_i32(tcg_el); + /* + * We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ + need_exit_tb = true; + } + if (need_exit_tb) { gen_lookup_tb(s); } From patchwork Fri Oct 18 17:44:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176929 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1194424ill; Fri, 18 Oct 2019 11:00:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqzpQNeQ0i2IxVcW9+iNRiud69gWo50KC0M58A3v4VpFx+AzKyzmS3u+91bfKQSZiQPH1RIO X-Received: by 2002:ac8:5044:: with SMTP id h4mr11423397qtm.5.1571421627978; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 18/22] target/arm: Rebuild hflags at CPSR writes Date: Fri, 18 Oct 2019 10:44:27 -0700 Message-Id: <20191018174431.1784-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue setting, but not relying upon, env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/op_helper.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index ccc2cecb46..b529d6c1bf 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -224,6 +224,7 @@ uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift) void HELPER(setend)(CPUARMState *env) { env->uncached_cpsr ^= CPSR_E; + arm_rebuild_hflags(env); } /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped. @@ -387,6 +388,8 @@ uint32_t HELPER(cpsr_read)(CPUARMState *env) void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) { cpsr_write(env, val, mask, CPSRWriteByInstr); + /* TODO: Not all cpsr bits are relevant to hflags. */ + arm_rebuild_hflags(env); } /* Write the CPSR for a 32-bit exception return */ From patchwork Fri Oct 18 17:44:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176930 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1200493ill; Fri, 18 Oct 2019 11:04:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqxOtX1p3G5c1gE9CBQPbjhNtQfYzNTFtLXgsEbO5jIyEs3D0TzDXGDx4ZVm3OmI+e5Cf1ez X-Received: by 2002:a37:c41:: with SMTP id 62mr9613978qkm.445.1571421896326; Fri, 18 Oct 2019 11:04:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571421896; cv=none; d=google.com; s=arc-20160816; b=P1NyZdfy4x6+mKfRQ1w7u0omSNxB5p94f58b4dHnyNOAa3itszddBHRrEYFInVOhiE UV9pZMw/ezNvK6hFzW7rsT9VkThtn0n8vvX4tf4u4+nCDhsWDe/nQAkiKoswsSJcmPdS iqcB3KvqDB796MtoXCxp8GkuZnStuuwNWt4VcyCNrG7huvF2ZSHYdmmnL7tbFzhWKf1t RyoR6o9mjYBbuPRn7vNM9PLvzQFpCZQR40aZrLO/fxOikrFVCydiND9uBFu00HfGvZ1K 3qKZ/zj43YEbooxoGX5uVMluQtiIGCs7osakW8BmHOpBbFyHkjkpXMFGDHx2YdcQB4nu NKLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=4z2zPWedOviyKqg3qmIWn8g3R8jv2yS1u67ka41eHWc=; b=zGOPaNS7hTKVY8fHUJ5+rC38uv8qAht8hHDyC4Egsg0H3XwJmrfJyweVqf/L3oiUFt r0JpL5FT4sXn/Br8p13RFH+A11Z3egajfAIrEroJIBTw0MI+lxQiLL0YbLXVn2R14uN5 l4gC0qpPhynlGM38gjV9JXOp1KLGPsrdrrKMa2X9a3blp2rzAp1ELTsi0d/+3ijepHxE UPiFZD2Xt5nrC2pIkE+1JADQuz2fSYfwzhvNAlPnBj9zNDyT1apjyzRIDNT5v3+taDZB 0wMCfAG94DpfwUfExTr5PAFuWWGB4khoYzpt+vVZ3DuIqUjoEIWl4xI/pomeel0mMgG6 y9rw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nI0rWgGQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 19/22] target/arm: Rebuild hflags at Xscale SCTLR writes Date: Fri, 18 Oct 2019 10:44:28 -0700 Message-Id: <20191018174431.1784-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue setting, but not relying upon, env->hflags. Signed-off-by: Richard Henderson --- target/arm/helper.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index aae7b62458..c55783e540 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4174,6 +4174,16 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, /* ??? Lots of these bits are not implemented. */ /* This may enable/disable the MMU, so do a TLB flush. */ tlb_flush(CPU(cpu)); + + if (ri->type & ARM_CP_SUPPRESS_TB_END) { + /* + * Normally we would always end the TB on an SCTLR write; see the + * comment in ARMCPRegInfo sctlr initialization below for why Xscale + * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild + * of hflags from the translator, so do it here. + */ + arm_rebuild_hflags(env); + } } static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, From patchwork Fri Oct 18 17:44:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176939 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1211040ill; Fri, 18 Oct 2019 11:13:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqxg9EEclQvFMIHHHi3k+LFLB4fgaVavq1mjsKETgqtaqifva/dpDV5EkpGzEq5lrWkwNF2Q X-Received: by 2002:a37:4c2:: with SMTP id 185mr9475705qke.406.1571422417906; Fri, 18 Oct 2019 11:13:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571422417; cv=none; d=google.com; s=arc-20160816; b=CEkwqY54AsQkjkqsn/iyV96Op0v28u+2ebxbttIxH4cNG0Rz2wMzGeGcuJjSjnSMGM f/Vv5AxfyaFRxJkZUGjMyEpuLdT2TFYODvZelFpxDWstbMDq+PzM/7BWke7FavAnUUo1 kkgRhcuf6x9w1wOusqwA0P8pLbfPswjioCaQ9qtMGVLOOsPdy8T8YwdmSCSUTbg35n2N iyb6XNNS2nFYenDyixeTUfNGxdZWHVCT7as0w+5IOQubKu4Gh3wFLqwiBHsxtFc/VZ96 v977T6ljrBCwUsSe4uQVih8nWKMy4DF1Prp83MF+jtvzgnzKTIKFkbT1dFRRnVxHiyoE OB+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HGoDHAyFTg02BbCDc0SzUOS11VgHC5xQyCe+OvrFqFc=; b=tYX4SlTeoIe/w71O4tlV5TQdpgsyAvxaswHxc6sGKsynXegoby3RknvB9ENHba9IIi jRKv0yMp6iPZF4+92EgO6bItrqq3nu67zJQfD53Cp532lfjPiEGsccSZzH4taLLlRnec M0VksMftoSPX1cFjndvb91tA/t66tzC3lyhLop3r9wL9JDFwLtVNQll/ohqhRNcqR9Qb yWyA+aeI3eU0PanGaBcc+e6Uo/XXimFpo6hXoerTMxN/8A5yuQyFCmKfE7+11658fqOX 7l0eZSZb6JUAYK/k4ThZM4Wb/B2EGLf7Nr0sbNSCMhgnNgD6koOoJY+hB8eail7QDkuv E+eA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gH4ePKI0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 20/22] target/arm: Rebuild hflags for M-profile Date: Fri, 18 Oct 2019 10:44:29 -0700 Message-Id: <20191018174431.1784-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::432 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue setting, but not relying upon, env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v7: Add rebuilds for v7m_msr and nvic_writel to v7m.ccr. v8: Split nvic update to a new patch and generalize location. --- target/arm/m_helper.c | 6 ++++++ target/arm/translate.c | 5 ++++- 2 files changed, 10 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 27cd2f3f96..f2512e448e 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -494,6 +494,7 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) switch_v7m_security_state(env, dest & 1); env->thumb = 1; env->regs[15] = dest & ~1; + arm_rebuild_hflags(env); } void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) @@ -555,6 +556,7 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) switch_v7m_security_state(env, 0); env->thumb = 1; env->regs[15] = dest; + arm_rebuild_hflags(env); } static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode, @@ -895,6 +897,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, env->regs[14] = lr; env->regs[15] = addr & 0xfffffffe; env->thumb = addr & 1; + arm_rebuild_hflags(env); } static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, @@ -1765,6 +1768,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) /* Otherwise, we have a successful exception exit. */ arm_clear_exclusive(env); + arm_rebuild_hflags(env); qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); } @@ -1837,6 +1841,7 @@ static bool do_v7m_function_return(ARMCPU *cpu) xpsr_write(env, 0, XPSR_IT); env->thumb = newpc & 1; env->regs[15] = newpc & ~1; + arm_rebuild_hflags(env); qemu_log_mask(CPU_LOG_INT, "...function return successful\n"); return true; @@ -1959,6 +1964,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) switch_v7m_security_state(env, true); xpsr_write(env, 0, XPSR_IT); env->regs[15] += 4; + arm_rebuild_hflags(env); return true; gen_invep: diff --git a/target/arm/translate.c b/target/arm/translate.c index cb47cd9744..b3720cd59b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8325,7 +8325,7 @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a) static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) { - TCGv_i32 addr, reg; + TCGv_i32 addr, reg, el; if (!arm_dc_feature(s, ARM_FEATURE_M)) { return false; @@ -8335,6 +8335,9 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) gen_helper_v7m_msr(cpu_env, addr, reg); tcg_temp_free_i32(addr); tcg_temp_free_i32(reg); + el = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_m32(cpu_env, el); + tcg_temp_free_i32(el); gen_lookup_tb(s); return true; } From patchwork Fri Oct 18 17:44:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176932 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1201300ill; Fri, 18 Oct 2019 11:05:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqyw/Pv4+lC5cqExF9uSixrG0Wpcr/DWh71OVLqDyQShhIgFfhip4Fuu7MXSMAXTzu0Qa8Ku X-Received: by 2002:a37:4ed5:: with SMTP id c204mr9882687qkb.41.1571421931460; Fri, 18 Oct 2019 11:05:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571421931; cv=none; d=google.com; s=arc-20160816; b=T+FDITli5AU3OcNbrBqSp+KJR3/FDNqs7h4N8yDQPrc0HnqrVaENcc6X9w6hIxz7pL 6xITL4v4VE55twylgmx679T7SLuWTga34t7EZpCos8gpMEiGLJLVJbxXDOVTyw1srmpE VHTPWsTCewxXGxyTYd9bpLrVNQZoC9Mr57FqzxIk2iQWXGyTjCva5hGDIUpgjRtmfGg1 1dbbsust+8eGgZ4NItrPJhWz04Drq3M7BcxQiH6/Y8bH0M2SHls5mNEiCZg+4TfSpsfQ aJ7Of+HGXrUO5vSQTxc6DUFBLMp/o1LfM4Yzb/D5n5CcA43/+vrbmzQWqi0g5yuEymOM XlIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=X22okviioTNDt7zI04Hhn7/Ba9cdRHpUwnG0LrTV7qc=; b=rrbq4gVUNsmSog0TCtGqa/hNvn5zHjA2Fy0MM1EVj4XMAKp1THYrZyH/KyVX54E2PU yQ0E9XNc+w1YQsM/Uo1dZkcnilPJY5REcMkpoqoP+iEDYzjlZ4eSZcB/tZnfb3PMDtEw BBPWTc+N/CXZ5BUOYwukWK/B08OsUyWfis0s62dD0AD2uZ+8ZxRqeYQQ0RMxrXnGLwIr vaEOK0MXA0YfL38D/44u47sXHz0CYt3T+LT4pUmBM5ckmFyMgktiKmPuCRB7Yuj83RO5 K58dr6yidV4HekIBNa7UKol9BiwQEHoomtv0Vp44hQziop0VMJrCUPy4ZVc2CxkjoZ7T SQFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Uvo+O8B5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 21/22] target/arm: Rebuild hflags for M-profile NVIC Date: Fri, 18 Oct 2019 10:44:30 -0700 Message-Id: <20191018174431.1784-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue setting, but not relying upon, env->hflags. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson --- hw/intc/armv7m_nvic.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 8e93e51e81..e8c74f9eba 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2251,7 +2251,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, } } nvic_irq_update(s); - return MEMTX_OK; + goto exit_ok; case 0x200 ... 0x23f: /* NVIC Set pend */ /* the special logic in armv7m_nvic_set_pending() * is not needed since IRQs are never escalated @@ -2269,9 +2269,9 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, } } nvic_irq_update(s); - return MEMTX_OK; + goto exit_ok; case 0x300 ... 0x33f: /* NVIC Active */ - return MEMTX_OK; /* R/O */ + goto exit_ok; /* R/O */ case 0x400 ... 0x5ef: /* NVIC Priority */ startvec = (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ @@ -2281,10 +2281,10 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, } } nvic_irq_update(s); - return MEMTX_OK; + goto exit_ok; case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */ if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { - return MEMTX_OK; + goto exit_ok; } /* fall through */ case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */ @@ -2299,10 +2299,10 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, set_prio(s, hdlidx, sbank, newprio); } nvic_irq_update(s); - return MEMTX_OK; + goto exit_ok; case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */ if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { - return MEMTX_OK; + goto exit_ok; } /* All bits are W1C, so construct 32 bit value with 0s in * the parts not written by the access size @@ -2322,15 +2322,19 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, */ s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK); } - return MEMTX_OK; + goto exit_ok; } if (size == 4) { nvic_writel(s, offset, value, attrs); - return MEMTX_OK; + goto exit_ok; } qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad write of size %d at offset 0x%x\n", size, offset); /* This is UNPREDICTABLE; treat as RAZ/WI */ + + exit_ok: + /* Ensure any changes made are reflected in the cached hflags. */ + arm_rebuild_hflags(&s->cpu->env); return MEMTX_OK; } From patchwork Fri Oct 18 17:44:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176935 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1204968ill; Fri, 18 Oct 2019 11:08:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqyUOO45al4lXjy1oWyw4d+EyKcWh5o06RoPpba8JzIM2Fdk5mAA2NcH5EH3z/evtorkKy9C X-Received: by 2002:a50:c2c2:: with SMTP id u2mr11266540edf.133.1571422112198; Fri, 18 Oct 2019 11:08:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571422112; cv=none; d=google.com; s=arc-20160816; b=Qab8CPRyZvLx563Ztv4l9qawvacNfGuA+MGcYK8XNQe2MGl2px9R89j/vVcUs5T1AO Sn997ihS5sdyoHMkEANroSJz5LhcD8Vv+VpsEKxCu/w6AKoBbbsnYjb6C3PcIJgpOK5+ +BBoa0nbGYcVz6fGmLuIClIkg/TpRZyanq7NN2H649bfsjjqwAFbf/JRzj3Y/DpIzECK 7QS3hmbk70MaQbsefVcchKennic8ICco062XuwB8saTziz4BwW04V37kZes4tr2A66RP u4jxamQfbeLKc3e6Jt6+m6yfcyqipL+JMhyy0b0QJiv+UgAzTFYBF3jhabPo6cFn39dn wDKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xYzA79nlkAAXT+tYBTRBvIlOCILLFnnuEHFTBSl+bu8=; b=DsjGPR627vSyS9TzNiwuspaH9zoA2cDLQ/LzIlr6UXzf4ADrEIydo8QKElwqaGGpM8 cuxBoAxZM/ocxZ5DGwctLbM8m2Sjz7KDStq4e00nGr2Jqb4Hd1591Cx4RA1dC6TlVj3o rZXtwpkOvPkMWlCDP2hmlZDqk7paqrFJxMYQk23QeIbDABpjFbetzX7td9lQujK/YUXd lVv7yvzBTz3+Hbv6x7guIh5Lkq5Gbwil9YwtMAtKHK/WyCo+xFNWNMEsE3cq+++JnxRD VGod0Wz/gRbo8tmyiwj0gJvp7MUSNe3vWl7QL0Wv2/yQtRaaE7886RBFREvZtJYjMwJZ oe4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vSIDsLNq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d20sm7857534pfq.88.2019.10.18.10.44.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Oct 2019 10:44:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 22/22] target/arm: Rely on hflags correct in cpu_get_tb_cpu_state Date: Fri, 18 Oct 2019 10:44:31 -0700 Message-Id: <20191018174431.1784-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191018174431.1784-1-richard.henderson@linaro.org> References: <20191018174431.1784-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the payoff. >From perf record -g data of ubuntu 18 boot and shutdown: BEFORE: - 23.02% 2.82% qemu-system-aar [.] helper_lookup_tb_ptr - 20.22% helper_lookup_tb_ptr + 10.05% tb_htable_lookup - 9.13% cpu_get_tb_cpu_state 3.20% aa64_va_parameters_both 0.55% fp_exception_el - 11.66% 4.74% qemu-system-aar [.] cpu_get_tb_cpu_state - 6.96% cpu_get_tb_cpu_state 3.63% aa64_va_parameters_both 0.60% fp_exception_el 0.53% sve_exception_el AFTER: - 16.40% 3.40% qemu-system-aar [.] helper_lookup_tb_ptr - 13.03% helper_lookup_tb_ptr + 11.19% tb_htable_lookup 0.55% cpu_get_tb_cpu_state 0.98% 0.71% qemu-system-aar [.] cpu_get_tb_cpu_state 0.87% 0.24% qemu-system-aar [.] rebuild_hflags_a64 Before, helper_lookup_tb_ptr is the second hottest function in the application, consuming almost a quarter of the runtime. Within the entire execution, cpu_get_tb_cpu_state consumes about 12%. After, helper_lookup_tb_ptr has dropped to the fourth hottest function, with consumption dropping to a sixth of the runtime. Within the entire execution, cpu_get_tb_cpu_state has dropped below 1%, and the supporting function to rebuild hflags also consumes about 1%. Assertions are retained for --enable-debug-tcg. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v2: Retain asserts for future debugging. --- target/arm/helper.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index c55783e540..63815fc4cf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11259,12 +11259,15 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - uint32_t flags, pstate_for_ss; + uint32_t flags = env->hflags; + uint32_t pstate_for_ss; *cs_base = 0; - flags = rebuild_hflags_internal(env); +#ifdef CONFIG_DEBUG_TCG + assert(flags == rebuild_hflags_internal(env)); +#endif - if (is_a64(env)) { + if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) { *pc = env->pc; if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);