From patchwork Thu Jun 6 07:26:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 802216 Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EABD13C3D7 for ; Thu, 6 Jun 2024 07:27:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717658843; cv=none; b=dA4bMv8oM16YaDDjs8yoRKl8Gvsk5kmRT6HmbSmm8631eE9NrTAuf0yTcG16wiotRafvti0tca2jrFpBNysfVk2dH2snl6J8TTG+0a7KKzlBpRNvPPv+HQavIyhLiAuzLP8JZY8cImT//OULzYczCEZO8a/H+hOHev+sWXz5CcU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717658843; c=relaxed/simple; bh=XfhruISZ6W6R/LbDDvmS/1LRRcCdxW1e2vnybSWgY64=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cIeioOlfWp6s7JFjqgLu7Iut89r/FvqnKjpXEUQ+4L5cCD9rRdBVd7gGDa8NR29VJlfjKznq3U8wqu6bFMj0JYGDyglw69HNchnYvIrOhDkHK2lsEnitsRCyjC6MPhLtqTBYv6tk0FHfB53vWVnqGUzArny6atKEjF/hwdc9mHY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=T/SORt1d; arc=none smtp.client-ip=209.85.210.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="T/SORt1d" Received: by mail-pf1-f174.google.com with SMTP id d2e1a72fcca58-703ed5d37acso523491b3a.0 for ; Thu, 06 Jun 2024 00:27:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717658841; x=1718263641; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=rBwbkrCA0TqUNhFf1X74rV9wZuOSuStFGznhcPYGXFs=; b=T/SORt1dLRFmQtt4cyBNojEVpzJU7D1W/WDasxMJDmGeqHBYqbz5/btTFnq2/1pg5J nUgXm+OGQrnipBRTliyHuoKa+jL6Vy/fZOZIz0kgSHJPQPsnnjt2Xr2Yosonz07faTgi /px0XI6GMLuvI2DjMX1/E2BigmFUscbOREUOEUgUy1nv08S1cs187klU0cB5L8ORaHHX +rV3jGTNCjJb5qfqTKDqAzB5pHG9iO0ygtFm4RGU0Q6IiDK5NEGCgQjpKcjXfbKwXgvG ATTbNonQJ78fEnJ9m1yYno504PiZ9KtkxX+BZR7/LCZGhuQejU2xaGHD1+maEt7RljBf Ppww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717658841; x=1718263641; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rBwbkrCA0TqUNhFf1X74rV9wZuOSuStFGznhcPYGXFs=; b=Hdtu9kx+kxOVh3651GMuddur55pVqVlFUnROiDR9Wa2md9PPwPpDPaGVNdglIHXtE5 7btZ0TLae380BxNlRXsa7B4Y+O9/w5cncquPwNCIZtxrS/JCi56mHtl7ABU5JtVwN2Lo yKuppII7VlNLsOWn8FztNfysRSXnyvfmMlG4Mua8udzXah4pN+IV1sQpiQ2bCMGFOzLO S7/Qwt67JAu3V4WDkJjK8m14UqZH029ShaP1L5NaP5Pn0lzF1ATup8bBcRh07wOLRavJ VRt89CGAgjAFtWo8e81ym4SNdSJn6iWlXt4d2aSIhEW9xTCVKzel7LodNd5k4Xtg17uE zA7w== X-Gm-Message-State: AOJu0Yx+G+kjf4cQ+of683mqIHZ+B30848g5tS+r7e8i8gsjO6GNzW5O Hs2haev8ChV73aUlU68NnIetZ1mfTdHPVlE2TtY4S1g/5pT7jOR2W+wl0WqPSw== X-Google-Smtp-Source: AGHT+IFnIUwznqu9u6MYNsnelzJn1VgHUtykElhx3ssZeiNo68mnCPqGNdTRBVe2iI9ZvQRVR2Dx9A== X-Received: by 2002:a05:6a00:98a:b0:6e9:38d0:5019 with SMTP id d2e1a72fcca58-703e56fb190mr5742198b3a.0.1717658840683; Thu, 06 Jun 2024 00:27:20 -0700 (PDT) Received: from [127.0.1.1] ([120.60.142.92]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703fd494feasm566621b3a.100.2024.06.06.00.27.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 00:27:20 -0700 (PDT) From: Manivannan Sadhasivam Date: Thu, 06 Jun 2024 12:56:34 +0530 Subject: [PATCH 1/5] PCI: dwc: ep: Remove dw_pcie_ep_init_notify() wrapper Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240606-pci-deinit-v1-1-4395534520dc@linaro.org> References: <20240606-pci-deinit-v1-0-4395534520dc@linaro.org> In-Reply-To: <20240606-pci-deinit-v1-0-4395534520dc@linaro.org> To: Vignesh Raghavendra , Siddharth Vadapalli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson , Jingoo Han , Srikanth Thokala , Marek Vasut , Yoshihiro Shimoda , Thierry Reding , Jonathan Hunter , Kunihiko Hayashi , Masami Hiramatsu , Kishon Vijay Abraham I Cc: linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@axis.com, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-tegra@vger.kernel.org, mhi@lists.linux.dev, Niklas Cassel , Manivannan Sadhasivam , Bjorn Helgaas X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=8261; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=XfhruISZ6W6R/LbDDvmS/1LRRcCdxW1e2vnybSWgY64=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmYWTCd6OusAPWj8/EhofvKCGw0bb2fJ7CBP789 MUhRI4+ZwmJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZmFkwgAKCRBVnxHm/pHO 9UPbCACmpesgufNbd+/06XFOPPifCGFzoXuFNZvjloHcTt5jKhb91yQtvvslDVmrsSO7MPGXfNV sWYep9sTwAits18G98ywyuTzVz01h0PD/4W9QSTh+3n7svU3XY9LQy/1JOfxCJMQlsLhQTijMF6 HSJC65HnT3yTkO+pBo/AsQtv9uHgnqv3OD63v71cK1ofkiF1Gk7GQgp0buARc1SOYAQ7UyQ7ZWO V151SUoUGcqz0qzCJAZXQNBVsg5NmZ3bca4RsFWH77rv4NFm54xKjWT33Skf8Gs43Wz4NLrcrqc ZhIF2srA1GaMOp43xafLsUweSWlQI9flN6hMwWnek6Nmh2Ja X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 Currently dw_pcie_ep_init_notify() wrapper just calls pci_epc_init_notify() directly. So this wrapper provides no benefit to the glue drivers. So let's remove it and call pci_epc_init_notify() directly from glue drivers. Suggested-by: Bjorn Helgaas Signed-off-by: Manivannan Sadhasivam Reviewed-by: Frank Li Reviewed-by: Niklas Cassel --- drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- drivers/pci/controller/dwc/pci-imx6.c | 2 +- drivers/pci/controller/dwc/pci-keystone.c | 2 +- drivers/pci/controller/dwc/pci-layerscape-ep.c | 2 +- drivers/pci/controller/dwc/pcie-artpec6.c | 2 +- drivers/pci/controller/dwc/pcie-designware-ep.c | 12 ------------ drivers/pci/controller/dwc/pcie-designware-plat.c | 2 +- drivers/pci/controller/dwc/pcie-designware.h | 5 ----- drivers/pci/controller/dwc/pcie-keembay.c | 2 +- drivers/pci/controller/dwc/pcie-qcom-ep.c | 2 +- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +- drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- drivers/pci/controller/dwc/pcie-uniphier-ep.c | 2 +- 13 files changed, 11 insertions(+), 28 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index d2d17d37d3e0..e491d0ff3962 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -474,7 +474,7 @@ static int dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx, return ret; } - dw_pcie_ep_init_notify(ep); + pci_epc_init_notify(ep->epc); return 0; } diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 917c69edee1d..a876b8e6e741 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1131,7 +1131,7 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, return ret; } - dw_pcie_ep_init_notify(ep); + pci_epc_init_notify(ep->epc); /* Start LTSSM. */ imx6_pcie_ltssm_enable(dev); diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index d3a7d14ee685..ca1054f5c79a 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -1293,7 +1293,7 @@ static int ks_pcie_probe(struct platform_device *pdev) goto err_ep_init; } - dw_pcie_ep_init_notify(&pci->ep); + pci_epc_init_notify(pci->ep.epc); break; default: diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index 7dde6d5fa4d8..35bb481564c7 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -286,7 +286,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) return ret; } - dw_pcie_ep_init_notify(&pci->ep); + pci_epc_init_notify(pci->ep.epc); return ls_pcie_ep_interrupt_init(pcie, pdev); } diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c index a4630b92489b..dc8dd7f27b78 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -452,7 +452,7 @@ static int artpec6_pcie_probe(struct platform_device *pdev) return ret; } - dw_pcie_ep_init_notify(&pci->ep); + pci_epc_init_notify(pci->ep.epc); break; default: diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 47391d7d3a73..2e69f81baf99 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -27,18 +27,6 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) } EXPORT_SYMBOL_GPL(dw_pcie_ep_linkup); -/** - * dw_pcie_ep_init_notify - Notify EPF drivers about EPC initialization complete - * @ep: DWC EP device - */ -void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) -{ - struct pci_epc *epc = ep->epc; - - pci_epc_init_notify(epc); -} -EXPORT_SYMBOL_GPL(dw_pcie_ep_init_notify); - /** * dw_pcie_ep_get_func_from_ep - Get the struct dw_pcie_ep_func corresponding to * the endpoint function diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index 8490c5d6ff9f..771b9d9be077 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -154,7 +154,7 @@ static int dw_plat_pcie_probe(struct platform_device *pdev) dw_pcie_ep_deinit(&pci->ep); } - dw_pcie_ep_init_notify(&pci->ep); + pci_epc_init_notify(pci->ep.epc); break; default: diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index f8e5431a207b..49ae845a3662 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -670,7 +670,6 @@ static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, void dw_pcie_ep_linkup(struct dw_pcie_ep *ep); int dw_pcie_ep_init(struct dw_pcie_ep *ep); int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep); -void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep); void dw_pcie_ep_deinit(struct dw_pcie_ep *ep); void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep); int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no); @@ -698,10 +697,6 @@ static inline int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) return 0; } -static inline void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) -{ -} - static inline void dw_pcie_ep_deinit(struct dw_pcie_ep *ep) { } diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c index 98bbc83182b4..278205db60a2 100644 --- a/drivers/pci/controller/dwc/pcie-keembay.c +++ b/drivers/pci/controller/dwc/pcie-keembay.c @@ -442,7 +442,7 @@ static int keembay_pcie_probe(struct platform_device *pdev) return ret; } - dw_pcie_ep_init_notify(&pci->ep); + pci_epc_init_notify(pci->ep.epc); break; default: diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 1ecf602c225a..4d2d7457dcb3 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -482,7 +482,7 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) val &= ~PARF_MSTR_AXI_CLK_EN; writel_relaxed(val, pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL); - dw_pcie_ep_init_notify(&pcie_ep->pci.ep); + pci_epc_init_notify(pcie_ep->pci.ep.epc); /* Enable LTSSM */ val = readl_relaxed(pcie_ep->parf + PARF_LTSSM); diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c index cfeccc2f9ee1..237a6a8818de 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -437,7 +437,7 @@ static int rcar_gen4_add_dw_pcie_ep(struct rcar_gen4_pcie *rcar) rcar_gen4_pcie_ep_deinit(rcar); } - dw_pcie_ep_init_notify(ep); + pci_epc_init_notify(ep->epc); return ret; } diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 93f5433c5c55..432ed9d9a463 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1903,7 +1903,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) goto fail_init_complete; } - dw_pcie_ep_init_notify(ep); + pci_epc_init_notify(ep->epc); /* Program the private control to allow sending LTR upstream */ if (pcie->of_data->has_ltr_req_fix) { diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c index a2b844268e28..d6e73811216e 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c @@ -410,7 +410,7 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev) return ret; } - dw_pcie_ep_init_notify(&priv->pci.ep); + pci_epc_init_notify(priv->pci.ep.epc); return 0; } From patchwork Thu Jun 6 07:26:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 803164 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1849D13CA97 for ; Thu, 6 Jun 2024 07:27:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717658854; cv=none; b=abscQ9LnpO52sOAg/5px/oxns6rVHH38fE5LcKO/40x/OQuxBCV7HxYzO/sw8/TW6/Ch6D/n9bpaHXxAMm526Rh5VjCy0o4k6wDNIU9vsksulkr1HnLkWh2Dc7khYZux6AStjY6QHHad4GO5R4w/8ww7aQCOFKSlA7D6Gs8cR5k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717658854; c=relaxed/simple; bh=GbOYu+TwhG+hMHKPWYPlU9l5l4iVl79aA0bUKAASNCY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pdLo/S+igNRc+rAKV0E3YmSX+BE8A7yXFnywWAAn7cBvnQtM0M/t37GBLpovjGUFFDOeTzch0QgSvGkRiOm87nBRtyTgEfxRy4A6ROI6pDMHdFbaYpMqo4fUdLjdK+4mOAHjCEGymIjZ+yifhPOAZwpTMrpm6OzTWmxbT9/QLCM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=iWU0gejO; arc=none smtp.client-ip=209.85.210.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="iWU0gejO" Received: by mail-pf1-f169.google.com with SMTP id d2e1a72fcca58-7025b84c0daso528442b3a.2 for ; Thu, 06 Jun 2024 00:27:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717658850; x=1718263650; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4s6tIDIkxRPAkTqdlcJJCzh5RP/VyC6Pay0yvubVfws=; b=iWU0gejOfpdROnr7K+ngqXgqLRfQdcRJWB521UzeCNWcsmRYEProz+QV0BfjE/PKrw ViURNzi3HuFi9PJA7dGOMuRbjtyIW/4KrzONvHE6v04G3fyyDljbuLmpFbAj/Dhp3UQg DE4LF8dhybIqJEb8Tvu6KJeA8fjAtF97FIFS6LE7lM8/14t8YkhOqqLfidTh6TRvJu6/ 7OlvEaC/R/zR1utwxn+xMY/dF2XmJ6GDads0I6iTPAa29BE0khOedQ0IFI22oLaPfUog pjUCHnDo8fRj5lofjTdzSP3ALJjJh+j08bx4k3Xy7grxE1gFleA8dbtrbdbStq2frBGB l3AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717658850; x=1718263650; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4s6tIDIkxRPAkTqdlcJJCzh5RP/VyC6Pay0yvubVfws=; b=IKvaDoDKB4CISm3Zq2IYpOlteOi72cEzAaI/AV2verlb9v6gmoazVborITY60/Wwko HRbkcwC26tRobQQfOn6FJq690JjDI5p2lF6gbIwAFrkGkJa8AsDArhiGAh3lRYqx6yqg QwS20+uyf6HWSpK4Ul2Gm+Ohu8/rM1lZg/h9hH4P9prd90zT5KV0/nFHUXcdjbHiW+F+ Y6IMtbQD5yFN4mEzf9lcjOl65pTYABuKXwGOXvcHWh84Hx8exvFLriPaeek8Sic/5Nn9 d2uUGYNwLMkx3VuqvWoG3/lZgzBRyHWmtZq3+SzK1n+UM7fdIDxEhluQjftUemzlsic4 vaxQ== X-Gm-Message-State: AOJu0YzCWMMWpG/Na75v4FH8fwFu7RKuex33k7Go3OHpz9l7muPhj6wJ ZqfD5fHJDKpRCLi6HQanir1/WHryvmjnRe+t5dnygYRzis0mvCBewXiUKw2uLg== X-Google-Smtp-Source: AGHT+IGaiybGi6wCqyOqfW7h/JsBn0scowWpyUza0Yrm57kHbK5xdefouT9nQfmNiEsFANaf/ZRQSg== X-Received: by 2002:a05:6a21:329a:b0:1af:3715:80c8 with SMTP id adf61e73a8af0-1b2b70f893amr5554061637.46.1717658849988; Thu, 06 Jun 2024 00:27:29 -0700 (PDT) Received: from [127.0.1.1] ([120.60.142.92]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703fd494feasm566621b3a.100.2024.06.06.00.27.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 00:27:29 -0700 (PDT) From: Manivannan Sadhasivam Date: Thu, 06 Jun 2024 12:56:35 +0530 Subject: [PATCH 2/5] PCI: endpoint: Introduce 'epc_deinit' event and notify the EPF drivers Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240606-pci-deinit-v1-2-4395534520dc@linaro.org> References: <20240606-pci-deinit-v1-0-4395534520dc@linaro.org> In-Reply-To: <20240606-pci-deinit-v1-0-4395534520dc@linaro.org> To: Vignesh Raghavendra , Siddharth Vadapalli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson , Jingoo Han , Srikanth Thokala , Marek Vasut , Yoshihiro Shimoda , Thierry Reding , Jonathan Hunter , Kunihiko Hayashi , Masami Hiramatsu , Kishon Vijay Abraham I Cc: linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@axis.com, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-tegra@vger.kernel.org, mhi@lists.linux.dev, Niklas Cassel , Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=9560; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=GbOYu+TwhG+hMHKPWYPlU9l5l4iVl79aA0bUKAASNCY=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmYWTCfUyadm2FsfT89qYm970AY7lKnZuqPFOxN 5rQzJ3x5yOJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZmFkwgAKCRBVnxHm/pHO 9aD6B/9LE0t3lGEsKHXfOUpCw4cw1jDP5BxV1sJGlu1vOgp0Xka3RLQ5uhUlPtsjp6hb9MsvhXd 4JvJeI9wFxsz0eqjQuUIDnxtr9xrEBvJFLdpAECsRTlLBQIE5ePIh7rYsZvUn9gWiagsu8W/F+S l/iuFgHvtI12yumK+1N+5K5E3c4yUPjiZV9DllTZmwdQLtAf0o7BpHeWMhpdbcToZ26w62K31zv kJSnZXzIsK/B/OrwnCbLVh8Xdq0iK81iAiqHBHuscXRJWmW3HpFMzyetAlDmXIBC1gV2eoMBQ4P nzak2S/MZ7yZQtluW+e3mLZ24byLk56hZgRySSN6KoDL5ZJJ X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 As like the 'epc_init' event, that is used to signal the EPF drivers about the EPC initialization, let's introduce 'epc_deinit' event that is used to signal EPC deinitialization. The EPC deinitialization applies only when any sort of fundamental reset is supported by the endpoint controller as per the PCIe spec. Reference: PCIe Base spec v5.0, sections 4.2.4.9.1 and 6.6.1. Currently, some EPC drivers like pcie-qcom-ep and pcie-tegra194 support PERST# as the fundamental reset. So the 'deinit' event will be notified to the EPF drivers when PERST# assert happens in the above mentioned EPC drivers. The EPF drivers, on receiving the event through the epc_deinit() callback should reset the EPF state machine and also cleanup any configuration that got affected by the fundamental reset like BAR, DMA etc... This change also warrants skipping the cleanups in unbind() if already done in epc_deinit(). Reviewed-by: Niklas Cassel Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-ep.c | 1 - drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + drivers/pci/controller/dwc/pcie-tegra194.c | 1 + drivers/pci/endpoint/functions/pci-epf-mhi.c | 19 +++++++++++++++++++ drivers/pci/endpoint/functions/pci-epf-test.c | 17 +++++++++++++++-- drivers/pci/endpoint/pci-epc-core.c | 25 +++++++++++++++++++++++++ include/linux/pci-epc.h | 13 +++++++++++++ include/linux/pci-epf.h | 2 ++ 8 files changed, 76 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 2e69f81baf99..78d5fc72c9cb 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -620,7 +620,6 @@ void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep) struct dw_pcie *pci = to_dw_pcie_from_ep(ep); dw_pcie_edma_remove(pci); - ep->epc->init_complete = false; } EXPORT_SYMBOL_GPL(dw_pcie_ep_cleanup); diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 4d2d7457dcb3..2324e56c9bfc 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -507,6 +507,7 @@ static void qcom_pcie_perst_assert(struct dw_pcie *pci) return; } + pci_epc_deinit_notify(pci->ep.epc); dw_pcie_ep_cleanup(&pci->ep); qcom_pcie_disable_resources(pcie_ep); pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED; diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 432ed9d9a463..4ca7404246a3 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1715,6 +1715,7 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie) if (ret) dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret); + pci_epc_deinit_notify(pcie->pci.ep.epc); dw_pcie_ep_cleanup(&pcie->pci.ep); reset_control_assert(pcie->core_rst); diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c index 205c02953f25..5832989e55e8 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -764,6 +764,24 @@ static int pci_epf_mhi_epc_init(struct pci_epf *epf) return 0; } +static void pci_epf_mhi_epc_deinit(struct pci_epf *epf) +{ + struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); + const struct pci_epf_mhi_ep_info *info = epf_mhi->info; + struct pci_epf_bar *epf_bar = &epf->bar[info->bar_num]; + struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl; + struct pci_epc *epc = epf->epc; + + if (mhi_cntrl->mhi_dev) { + mhi_ep_power_down(mhi_cntrl); + if (info->flags & MHI_EPF_USE_DMA) + pci_epf_mhi_dma_deinit(epf_mhi); + mhi_ep_unregister_controller(mhi_cntrl); + } + + pci_epc_clear_bar(epc, epf->func_no, epf->vfunc_no, epf_bar); +} + static int pci_epf_mhi_link_up(struct pci_epf *epf) { struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); @@ -898,6 +916,7 @@ static void pci_epf_mhi_unbind(struct pci_epf *epf) static const struct pci_epc_event_ops pci_epf_mhi_event_ops = { .epc_init = pci_epf_mhi_epc_init, + .epc_deinit = pci_epf_mhi_epc_deinit, .link_up = pci_epf_mhi_link_up, .link_down = pci_epf_mhi_link_down, .bus_master_enable = pci_epf_mhi_bus_master_enable, diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index e771be7512a1..7c2ed6eae53a 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -782,6 +782,15 @@ static int pci_epf_test_epc_init(struct pci_epf *epf) return 0; } +static void pci_epf_test_epc_deinit(struct pci_epf *epf) +{ + struct pci_epf_test *epf_test = epf_get_drvdata(epf); + + cancel_delayed_work(&epf_test->cmd_handler); + pci_epf_test_clean_dma_chan(epf_test); + pci_epf_test_clear_bar(epf); +} + static int pci_epf_test_link_up(struct pci_epf *epf) { struct pci_epf_test *epf_test = epf_get_drvdata(epf); @@ -803,6 +812,7 @@ static int pci_epf_test_link_down(struct pci_epf *epf) static const struct pci_epc_event_ops pci_epf_test_event_ops = { .epc_init = pci_epf_test_epc_init, + .epc_deinit = pci_epf_test_epc_deinit, .link_up = pci_epf_test_link_up, .link_down = pci_epf_test_link_down, }; @@ -905,10 +915,13 @@ static int pci_epf_test_bind(struct pci_epf *epf) static void pci_epf_test_unbind(struct pci_epf *epf) { struct pci_epf_test *epf_test = epf_get_drvdata(epf); + struct pci_epc *epc = epf->epc; cancel_delayed_work(&epf_test->cmd_handler); - pci_epf_test_clean_dma_chan(epf_test); - pci_epf_test_clear_bar(epf); + if (epc->init_complete) { + pci_epf_test_clean_dma_chan(epf_test); + pci_epf_test_clear_bar(epf); + } pci_epf_test_free_space(epf); } diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 56b60330355d..47a91dcb07d7 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -774,6 +774,31 @@ void pci_epc_notify_pending_init(struct pci_epc *epc, struct pci_epf *epf) } EXPORT_SYMBOL_GPL(pci_epc_notify_pending_init); +/** + * pci_epc_deinit_notify() - Notify the EPF device about EPC deinitialization + * @epc: the EPC device whose deinitialization is completed + * + * Invoke to notify the EPF device that the EPC deinitialization is completed. + */ +void pci_epc_deinit_notify(struct pci_epc *epc) +{ + struct pci_epf *epf; + + if (IS_ERR_OR_NULL(epc)) + return; + + mutex_lock(&epc->list_lock); + list_for_each_entry(epf, &epc->pci_epf, list) { + mutex_lock(&epf->lock); + if (epf->event_ops && epf->event_ops->epc_deinit) + epf->event_ops->epc_deinit(epf); + mutex_unlock(&epf->lock); + } + epc->init_complete = false; + mutex_unlock(&epc->list_lock); +} +EXPORT_SYMBOL_GPL(pci_epc_deinit_notify); + /** * pci_epc_bus_master_enable_notify() - Notify the EPF device that the EPC * device has received the Bus Master diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 11115cd0fe5b..85bdf2adb760 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -197,6 +197,8 @@ struct pci_epc_features { #define to_pci_epc(device) container_of((device), struct pci_epc, dev) +#ifdef CONFIG_PCI_ENDPOINT + #define pci_epc_create(dev, ops) \ __pci_epc_create((dev), (ops), THIS_MODULE) #define devm_pci_epc_create(dev, ops) \ @@ -226,6 +228,7 @@ void pci_epc_linkup(struct pci_epc *epc); void pci_epc_linkdown(struct pci_epc *epc); void pci_epc_init_notify(struct pci_epc *epc); void pci_epc_notify_pending_init(struct pci_epc *epc, struct pci_epf *epf); +void pci_epc_deinit_notify(struct pci_epc *epc); void pci_epc_bus_master_enable_notify(struct pci_epc *epc); void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf, enum pci_epc_interface_type type); @@ -272,4 +275,14 @@ void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc, phys_addr_t *phys_addr, size_t size); void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr, void __iomem *virt_addr, size_t size); + +#else +static inline void pci_epc_init_notify(struct pci_epc *epc) +{ +} + +static inline void pci_epc_deinit_notify(struct pci_epc *epc) +{ +} +#endif /* CONFIG_PCI_ENDPOINT */ #endif /* __LINUX_PCI_EPC_H */ diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index dc759eb7157c..0639d4dc8986 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -71,12 +71,14 @@ struct pci_epf_ops { /** * struct pci_epc_event_ops - Callbacks for capturing the EPC events * @epc_init: Callback for the EPC initialization complete event + * @epc_deinit: Callback for the EPC deinitialization event * @link_up: Callback for the EPC link up event * @link_down: Callback for the EPC link down event * @bus_master_enable: Callback for the EPC Bus Master Enable event */ struct pci_epc_event_ops { int (*epc_init)(struct pci_epf *epf); + void (*epc_deinit)(struct pci_epf *epf); int (*link_up)(struct pci_epf *epf); int (*link_down)(struct pci_epf *epf); int (*bus_master_enable)(struct pci_epf *epf); From patchwork Thu Jun 6 07:26:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 802215 Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87EC213C8F0 for ; Thu, 6 Jun 2024 07:27:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717658862; cv=none; b=Vy/eMwrZHes1VDW8sqW9LjYpkgXBR4Tl6tr38R8wRqLHpK0wh6837YPYjJiC1Zltp5z54J1PHVD17mpgz0gix0qk2gSEMk4YEjpZtt6krKQSc5iqCMYTzEc+IsLkZ1OO5U8WLjM3GMHyhZanvLnM3/Y6ojMInH1nxrUYWcvCcw8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717658862; c=relaxed/simple; bh=CyPVVcJODJ2tCBdthwAVOus+8aJwJCp9nbRVeHHFCiQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fqc2pdWACA5PGLvk4CjW5howizBAHsEL7Vb+j424mgtr/ceAGQiLwa7fwyGUwvbbRTQN+izqsp6dQQ1SpTkbzOKMDAs2sY77cl5omoqZ58hGvXWj605fajnp/Sw72tUfneKfKAProYL00BcdrwJ/K9YmmfYHT0idNEkUXkMUH7g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ZnZ2gQ7N; arc=none smtp.client-ip=209.85.210.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ZnZ2gQ7N" Received: by mail-pf1-f176.google.com with SMTP id d2e1a72fcca58-7024cd9dd3dso517152b3a.3 for ; Thu, 06 Jun 2024 00:27:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717658860; x=1718263660; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Y7dQ9TfqMHdXG8LG6tUjAnjQ7RMaAYCpFAwKOPZMm9w=; b=ZnZ2gQ7N/w/LsBSIgAqLsQ8jkb29/AtxGee0JchkkpbBS6AznOfhNiWBdJdwxYWmrK U93v7xekrUf0wEu6V7mHXsajBJu3BWpCM9yrQs9TQgpOqK/yuda/aIQlShrrGHTKK70Y VXSac70sGx+PO8H7M3reQcyonmHgym1JmWOjxNhDjSVKx5qmxaXXkAnjGFW0OHwP2a9m KotbIJUTjx1a/AVAXliCqhLmOrmS410btPTJ0HTID4ZdyHK5dbnPI9FSa0Z8Hkzs2IIF P0f7erYbc9ChMTOd27HXb9bySFi6qH8wVxxk7EfWrtqesRpUAUZj9y5mbPrMsqVWpJRj V/9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717658860; x=1718263660; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y7dQ9TfqMHdXG8LG6tUjAnjQ7RMaAYCpFAwKOPZMm9w=; b=Z8IAUrVmhueys0D3Xy7q2H5CURLamHe7oKXQuvAJX7KHj3EGn8CkxH/NXXQK+VlATi 1RCk2so5sD7/Pcwe/KMAEz4avsKwkRf2XZCuQu9qpnHrQ3dCeq22ixieQY1LyC5v/DMi /47KnQNfpTliy0w2TIpDwB8LSjWaaUlucnIM2v1SO8hja1bqP+TDBppwddM48Ldd365z 9U/RT3BumQXvVn/nJ2ziAXQN+PmXK/WFuRZaO/9Mt9V6EDviYleLI/7DM6Cw60Go+QVl Ga4t1SIM8GYAXoAMT/oIF9EOa356cJxHpaBv5OHCgSM3YvwfUghMxiN2zMAQuK7pAW9u 1Z/A== X-Gm-Message-State: AOJu0YyrbLcf1+NjqVnMjwbbrJEk3f+E1LBgdUnDCinB663QnCqfNPro BDxzDeWneIPho07NMh1i1afVpZFjlcj6ZBYjfja4e77EvQFzGShaUmLRGvu7Uw== X-Google-Smtp-Source: AGHT+IEHiQ8WtwlFSj6EjFB6496Btx4UY0bPcJcqZ/rLzZcY0YY29ZVlXGd6vnqJZdPzzFq9RezUpw== X-Received: by 2002:a05:6a00:198d:b0:702:5b3f:6c1a with SMTP id d2e1a72fcca58-703e5a5d66amr5009435b3a.32.1717658859582; Thu, 06 Jun 2024 00:27:39 -0700 (PDT) Received: from [127.0.1.1] ([120.60.142.92]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703fd494feasm566621b3a.100.2024.06.06.00.27.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 00:27:39 -0700 (PDT) From: Manivannan Sadhasivam Date: Thu, 06 Jun 2024 12:56:36 +0530 Subject: [PATCH 3/5] PCI: dwc: ep: Add a generic dw_pcie_ep_linkdown() API to handle Link Down event Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240606-pci-deinit-v1-3-4395534520dc@linaro.org> References: <20240606-pci-deinit-v1-0-4395534520dc@linaro.org> In-Reply-To: <20240606-pci-deinit-v1-0-4395534520dc@linaro.org> To: Vignesh Raghavendra , Siddharth Vadapalli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson , Jingoo Han , Srikanth Thokala , Marek Vasut , Yoshihiro Shimoda , Thierry Reding , Jonathan Hunter , Kunihiko Hayashi , Masami Hiramatsu , Kishon Vijay Abraham I Cc: linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@axis.com, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-tegra@vger.kernel.org, mhi@lists.linux.dev, Niklas Cassel , Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=6883; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=CyPVVcJODJ2tCBdthwAVOus+8aJwJCp9nbRVeHHFCiQ=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmYWTC1tIEUprHWLU3EJbohGb4dhy/c74Ocfx/L gFMNksZJ96JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZmFkwgAKCRBVnxHm/pHO 9RqiB/wMM8Tt9y5MfBLY75mIEysw4v7tQX00FYGFLUMXPKf2oEKReZt+8J/fkmIfXEHWwiGONN2 uYmAwIdX2adk3LvRje/TCwo/ejcIJ2zykk0oss3oBr6t2GJXXIPuAKtNzISB4p2D3ey/Vjy/6xk 0Rtzznh3Wlz5rda3ypN/B5AEOGTLlzLQiqIYgn4iuPIgntiAE18mp0zhbiRpO4X/EwLyFSV7cwB X8XO5m6EKI1tkg6yVUJAsu4CJFSupVEEJbczhUSeXBVeFErpeyQeDM4ovmeHVXxvX+JHrTwPk+q eP90fxT0EFQCjKr/rr15hqsncrMBMRB74CQmXHyqxFRtrBCr X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 As per the PCIe base spec r5.0, section 5.2, Link Down event can happen under any of the following circumstances: 1. Fundamental/Hot reset 2. Link disable transmission by upstream component 3. Moving from L2/L3 to L0 In those cases, Link Down causes some non-sticky DWC registers to loose the state (like REBAR, etc...). So the drivers need to reinitialize them to function properly once the link comes back again. This is not a problem for drivers supporting PERST# IRQ, since they can reinitialize the registers in the PERST# IRQ callback. But for the drivers not supporting PERST#, there is no way they can reinitialize the registers other than relying on Link Down IRQ received when the link goes down. So let's add a DWC generic API dw_pcie_ep_linkdown() that reinitializes the non-sticky registers and also notifies the EPF drivers about link going down. This API can also be used by the drivers supporting PERST# to handle the scenario (2) mentioned above. NOTE: For the sake of code organization, move the dw_pcie_ep_linkup() definition just above dw_pcie_ep_linkdown(). Reviewed-by: Niklas Cassel Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-ep.c | 103 ++++++++++++++++-------- drivers/pci/controller/dwc/pcie-designware.h | 5 ++ 2 files changed, 73 insertions(+), 35 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 78d5fc72c9cb..09ad6f7b5095 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -15,18 +15,6 @@ #include #include -/** - * dw_pcie_ep_linkup - Notify EPF drivers about Link Up event - * @ep: DWC EP device - */ -void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) -{ - struct pci_epc *epc = ep->epc; - - pci_epc_linkup(epc); -} -EXPORT_SYMBOL_GPL(dw_pcie_ep_linkup); - /** * dw_pcie_ep_get_func_from_ep - Get the struct dw_pcie_ep_func corresponding to * the endpoint function @@ -661,6 +649,34 @@ static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) return 0; } +static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci) +{ + unsigned int offset; + unsigned int nbars; + u32 reg, i; + + offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); + + dw_pcie_dbi_ro_wr_en(pci); + + if (offset) { + reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> + PCI_REBAR_CTRL_NBAR_SHIFT; + + /* + * PCIe r6.0, sec 7.8.6.2 require us to support at least one + * size in the range from 1 MB to 512 GB. Advertise support + * for 1 MB BAR size only. + */ + for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) + dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0); + } + + dw_pcie_setup(pci); + dw_pcie_dbi_ro_wr_dis(pci); +} + /** * dw_pcie_ep_init_registers - Initialize DWC EP specific registers * @ep: DWC EP device @@ -675,13 +691,11 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) struct dw_pcie_ep_func *ep_func; struct device *dev = pci->dev; struct pci_epc *epc = ep->epc; - unsigned int offset, ptm_cap_base; - unsigned int nbars; + u32 ptm_cap_base, reg; u8 hdr_type; u8 func_no; - int i, ret; void *addr; - u32 reg; + int ret; hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE) & PCI_HEADER_TYPE_MASK; @@ -744,25 +758,8 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) if (ep->ops->init) ep->ops->init(ep); - offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); ptm_cap_base = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM); - dw_pcie_dbi_ro_wr_en(pci); - - if (offset) { - reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); - nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> - PCI_REBAR_CTRL_NBAR_SHIFT; - - /* - * PCIe r6.0, sec 7.8.6.2 require us to support at least one - * size in the range from 1 MB to 512 GB. Advertise support - * for 1 MB BAR size only. - */ - for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) - dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, BIT(4)); - } - /* * PTM responder capability can be disabled only after disabling * PTM root capability. @@ -779,8 +776,7 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) dw_pcie_dbi_ro_wr_dis(pci); } - dw_pcie_setup(pci); - dw_pcie_dbi_ro_wr_dis(pci); + dw_pcie_ep_init_non_sticky_registers(pci); return 0; @@ -791,6 +787,43 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) } EXPORT_SYMBOL_GPL(dw_pcie_ep_init_registers); +/** + * dw_pcie_ep_linkup - Notify EPF drivers about Link Up event + * @ep: DWC EP device + */ +void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) +{ + struct pci_epc *epc = ep->epc; + + pci_epc_linkup(epc); +} +EXPORT_SYMBOL_GPL(dw_pcie_ep_linkup); + +/** + * dw_pcie_ep_linkdown - Notify EPF drivers about Link Down event + * @ep: DWC EP device + * + * Non-sticky registers are also initialized before sending the notification to + * the EPF drivers. This is needed since the registers need to be initialized + * before the link comes back again. + */ +void dw_pcie_ep_linkdown(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct pci_epc *epc = ep->epc; + + /* + * Initialize the non-sticky DWC registers as they would've reset post + * Link Down. This is specifically needed for drivers not supporting + * PERST# as they have no way to reinitialize the registers before the + * link comes back again. + */ + dw_pcie_ep_init_non_sticky_registers(pci); + + pci_epc_linkdown(epc); +} +EXPORT_SYMBOL_GPL(dw_pcie_ep_linkdown); + /** * dw_pcie_ep_init - Initialize the endpoint device * @ep: DWC EP device diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 49ae845a3662..89f9046af7eb 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -668,6 +668,7 @@ static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, #ifdef CONFIG_PCIE_DW_EP void dw_pcie_ep_linkup(struct dw_pcie_ep *ep); +void dw_pcie_ep_linkdown(struct dw_pcie_ep *ep); int dw_pcie_ep_init(struct dw_pcie_ep *ep); int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep); void dw_pcie_ep_deinit(struct dw_pcie_ep *ep); @@ -687,6 +688,10 @@ static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) { } +static inline void dw_pcie_ep_linkdown(struct dw_pcie_ep *ep) +{ +} + static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep) { return 0; From patchwork Thu Jun 6 07:26:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 803163 Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 607B213C8F9 for ; Thu, 6 Jun 2024 07:27:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717658872; cv=none; b=K3v2hizRkUy92YTCjY0K1PdYiAX5x4fKq4A5KsrnVAQV5gRsOUnE1Sv5ZKlNJ76N5TaEMa1//2cVgxgU4VriyHIr7ApzPx+WyoSRC8XaHjVjYqRO7UGEI7P4qeQnx0W5fdLtLQu1KZ2PTtQZd9eTNMMljshw6bt80bKuAPrKxBo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717658872; c=relaxed/simple; bh=O5xFzhtcTVsPW2oRgvJYNIDWPOdCoxabhuVw8QIdZvA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tuC0Qq5ULLzVRfxyRStWrKhbJn1AdF/CAvbJhZaneTX6N0Cx+gtp6wphoKLW7xuVimBSvQOn80wijWAb3Wy6gjj0CGGD5/Vv0sy8qOMtlLAsbL6j8IygXyVFxyQejYDkb/rleSjaOKBYfxc0aqQ18nIUIGPfzwmcMJRwenku0L0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=znwwoQFb; arc=none smtp.client-ip=209.85.215.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="znwwoQFb" Received: by mail-pg1-f169.google.com with SMTP id 41be03b00d2f7-6818e31e5baso499821a12.1 for ; Thu, 06 Jun 2024 00:27:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717658869; x=1718263669; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kJExdlshI/LzGxmgV0APY0jbCwHbAgtoC/BDFnsN7OQ=; b=znwwoQFbtQ4wuD1IdNsfzQ7379LnvmYCXOqxvB7moAZTXqv16PZlygjo83KuJpsil/ YUsesmjL97zwB39o0/3IM31Gwz7V2b9l4CPX+X72bpz2iAZnWFwvGdkPTjuTh2Q4htLo 9gmu5IMPJllEx8d+2PM9ipUhGYGdm6ooxvEAhTAbnVvFcF4QrPSemvAna8FJ3mBu/Z72 3lYlO+nxI74z4hXw1ogGp2v/tp3QJRObMCMYpEPB+yJ60/51/CUr0U/mJMPoFP/pHfMI /cg4LvTiaYmLUfpKYRF7TtuF9EHIW0z4zDzhDxhwSPZD8HahC7xO1fEHuJumrq9cP+AB erfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717658870; x=1718263670; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kJExdlshI/LzGxmgV0APY0jbCwHbAgtoC/BDFnsN7OQ=; b=Tny95YZQCDaIRHwxCsuOx5PZhqgk7Avmm8ilRmhV8rR+xKh/Z4knWtmkiPkGnh8/sl FHKoNStESuJXGbvL98wWmfl8dDVrJXeknykAR0AR+LX/F3mLrNP3IDEQQGij+DEWWNZp n2IJAvUfQwqZLNcC7W8dmI9tduOu231b2agKdKTpibEkjZaRpIXes41Ii2+mFovEkvbE +SyMuYTZs/8tBy+MbxBnvXjDDM5V5prMmDmPtCCaDi+xClgxXQGk70AbUTL3YxzswpP7 jHzVXvL+mrprI6KmSPxoQSTKIPfgSzF625hAe8wFSl3h8B/9ajNvi8le72BY8YOkfSmX bZYQ== X-Gm-Message-State: AOJu0YxdXr5c1zvCWDlTOKNOXFwR3nwsD/9ysAi3Dp8h/CVDffeUEoFB HIWxNYoA39o/ngJz7SNrx1RAxqUb/g5VFlcTHjU2WtajnyjlD8g6DOgyHelveQ== X-Google-Smtp-Source: AGHT+IHE2oR5v0Why3yjnX38J4mrLlwOPGlZ2u6XUoxDRmSxOxrVfN+J6poCz9GXnIiql3GkZYmfXg== X-Received: by 2002:a05:6a21:6d96:b0:1b0:180b:218a with SMTP id adf61e73a8af0-1b2b73ade98mr4841566637.13.1717658869466; Thu, 06 Jun 2024 00:27:49 -0700 (PDT) Received: from [127.0.1.1] ([120.60.142.92]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703fd494feasm566621b3a.100.2024.06.06.00.27.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 00:27:49 -0700 (PDT) From: Manivannan Sadhasivam Date: Thu, 06 Jun 2024 12:56:37 +0530 Subject: [PATCH 4/5] PCI: qcom-ep: Use the generic dw_pcie_ep_linkdown() API to handle Link Down event Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240606-pci-deinit-v1-4-4395534520dc@linaro.org> References: <20240606-pci-deinit-v1-0-4395534520dc@linaro.org> In-Reply-To: <20240606-pci-deinit-v1-0-4395534520dc@linaro.org> To: Vignesh Raghavendra , Siddharth Vadapalli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson , Jingoo Han , Srikanth Thokala , Marek Vasut , Yoshihiro Shimoda , Thierry Reding , Jonathan Hunter , Kunihiko Hayashi , Masami Hiramatsu , Kishon Vijay Abraham I Cc: linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@axis.com, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-tegra@vger.kernel.org, mhi@lists.linux.dev, Niklas Cassel , Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1135; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=O5xFzhtcTVsPW2oRgvJYNIDWPOdCoxabhuVw8QIdZvA=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmYWTCDD3Zk89+yzevKC0hNBYDEyFsV6QzuZHsh tHaN4WUEIeJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZmFkwgAKCRBVnxHm/pHO 9R0cB/9bA9491NDevYfqU5Xd3giwVDoj11ZyiC+uOfmItJ2Mqg+LjY5yIgYgU2b5u9eza2+qgOi 4U0wQ++MHB3cRN8Qfi6FrDe0E+qa0KqH+kH+cY35umoGm8Zpgcx4MwJ/tMbjbEDe9tmPP6pdeeo aoRbCqLKiT7RwZIm/MH0OGPuFhv9nisV904RgEfR3gT+0Tpx3feFJWRFxSULskIjFCUOfubNx57 A8RoeX3+G02D4OkIxrJBn3o6BIPuD8zGx+pfD2AEwZMjJAUhWsHsYx8R5f50vb+7YNWV/GhNkbP dPojiLZWnG6HfXVSNGT8M7+Mr1QS3JOavCuJ4pGNZfPAW5uG X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 Now that the API is available, let's make use of it. It also handles the reinitialization of DWC non-sticky registers in addition to sending the notification to EPF drivers. Reviewed-by: Niklas Cassel Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 2324e56c9bfc..02a2a871a91f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -641,7 +641,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { dev_dbg(dev, "Received Linkdown event\n"); pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN; - pci_epc_linkdown(pci->ep.epc); + dw_pcie_ep_linkdown(&pci->ep); } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { dev_dbg(dev, "Received Bus Master Enable event\n"); pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED; From patchwork Thu Jun 6 07:26:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 802214 Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C50913AD1D for ; Thu, 6 Jun 2024 07:28:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717658883; cv=none; b=Zin9VzTlN2y2rHhxn2iFGY8BmzxCjWdWNIY1d/DXycejx70A7s752uHF3pRtZUhwsEvTmgENaSiF4LTTsbobWCzy5Drs9HuCS1nZ0uNC8YCbcS2SgfKzRhxL02oJ65wJv10LNQzCW7fsSPzbPvj4WlTaobI6HlyAiOLFvdEhBmE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717658883; c=relaxed/simple; bh=iTBLcuvewMpJ4faEaIFRB8NCV5eK2XvDog669bY6A04=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fBCjtqGppi+yauwcW3tM3sVJEep/jWpOSp+xroD8Cla4sQIEj0H7EpqWyXG9+Kji84lR1wv72LDEajZFe1jKblx6U0BZRb+FXw7DInewMy41PfatL6eo18vaMDt3RS/nB1VI/KhtNppTMjUecGyABeG6a10xCL4SjPO4O8PwkBk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=JG299hie; arc=none smtp.client-ip=209.85.210.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="JG299hie" Received: by mail-pf1-f173.google.com with SMTP id d2e1a72fcca58-70109d34a16so565355b3a.2 for ; Thu, 06 Jun 2024 00:28:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1717658880; x=1718263680; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=HPG+iYxST5I5DbJlxvzuCXfj8r8tlsuRAuVmKBt4I54=; b=JG299hiersRJmlMIlWaBGTlVNIzV0EWX2O/tXePH7FUUT+pXdYT0jQYYL+rWUW1wYn UfYawvH39ftOPgXSILc8y7MLfUmbJPYj1A2fcJsYNLjrkW90HTH6opOwqCqLOVQ6fFg9 5TgSfhQcthIlPAtrB1/GKIOrO73LXzkR9BJkpZNzfLBqpXdMfxgbztpq6/Mv2uh3KOH0 YcRwLDtWpnJx8cQYB0LwxuUdMsuKj0U6VYTl1gZs3J9tAKEFeTkiWfKpWKxwDA95gb9q HCuMqJy5tT1GvafFZZ0Zxpe1mvV8nzx8RTRfoUrEQp9iAXtGTZQO1CTApeK5ZYlKYMMW tTMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717658880; x=1718263680; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HPG+iYxST5I5DbJlxvzuCXfj8r8tlsuRAuVmKBt4I54=; b=hO3rsjR5VB5naXw4vHAZ/OqJZTwE4Bo592sdH+jDAQxNjqcNQwe1qwrOUL8ZjUN08p RTF8EPOVBPgbwRNd7c4eaIex1rkoeLMoNqfrbp7WZF5/tXBoNce85A7VUb5apRFaVcTr cAtY+9iFpVLhL71dxvmOyjQ04PSQxt+NLBfEaHfPp+aYtB4dmPNapf8syTwQ1YYDP52K uoaYmxIrOeP1Zo2uzZPFkAL7LSoZgdLvzWMQoTl2YJmp2a1U0R4qjK4QCFNbOE9Q4OpL yU1S+H4sR1biLoznt3zlSrD1PABDBkDbBxOHP/xb+yurMXpXTo5sF5EMfZ3fOq/fQ3Wc WmEw== X-Gm-Message-State: AOJu0Yx2XAZGLkwIn0o66nlume+o1Ik2qQ8s7Fc96+66BsYi6QVHs7M6 Bs1ZaL+ReGCtpVQUd5zpPTFNazZZCjpoSFQo5JZXsaFtvJSLJf+DuuXHcK0fzhX2N1SVfLbZIqM = X-Google-Smtp-Source: AGHT+IFcf9cgtatPK4aegB5pOtXP/U3r7+aHmKSySRB4gcmnkYTJLzQC9N/nujSZyq7rntRegQ9fyQ== X-Received: by 2002:a05:6a21:9994:b0:1b2:2893:4c30 with SMTP id adf61e73a8af0-1b2b75a28b6mr5554701637.43.1717658880331; Thu, 06 Jun 2024 00:28:00 -0700 (PDT) Received: from [127.0.1.1] ([120.60.142.92]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703fd494feasm566621b3a.100.2024.06.06.00.27.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 00:27:59 -0700 (PDT) From: Manivannan Sadhasivam Date: Thu, 06 Jun 2024 12:56:38 +0530 Subject: [PATCH 5/5] PCI: layerscape-ep: Use the generic dw_pcie_ep_linkdown() API to handle Link Down event Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240606-pci-deinit-v1-5-4395534520dc@linaro.org> References: <20240606-pci-deinit-v1-0-4395534520dc@linaro.org> In-Reply-To: <20240606-pci-deinit-v1-0-4395534520dc@linaro.org> To: Vignesh Raghavendra , Siddharth Vadapalli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson , Jingoo Han , Srikanth Thokala , Marek Vasut , Yoshihiro Shimoda , Thierry Reding , Jonathan Hunter , Kunihiko Hayashi , Masami Hiramatsu , Kishon Vijay Abraham I Cc: linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@axis.com, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-tegra@vger.kernel.org, mhi@lists.linux.dev, Niklas Cassel , Manivannan Sadhasivam , Bjorn Helgaas X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1130; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=iTBLcuvewMpJ4faEaIFRB8NCV5eK2XvDog669bY6A04=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmYWTDAWlDlC+iP821vFRRCpXr79KN0oimjGpwM 9zYQuHhq6WJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZmFkwwAKCRBVnxHm/pHO 9dUvB/4geNbdfN8AuZaua5Q6crO4wiBZbDIZpTUEWbj5cD3+PQgZdP2fszAcOMysVUd2LhEzvbX kN7XJZcOGcc8d4i5IFEjwKG/dbhVt/tdxFru22kORqs05rEFn8+aFrQwhtSGaYkYgqYgRfP5Y6W b7v2+d152TaxfMTEdc5KIpJ3NjqVYBYvg2Gm5ndnVM2TIBPLBmyqzyiXOFEURUukShXcXr+j5P5 wTPHtr9arU74ONCvNRavuhdpDxwvIoRgVqCiA2vDPG5DViOV2w7sRHoLC0PIvLJstIr0Gh5lZUc 0TbWhXew/SfM3kcXGjBTL99FKexWWdBkpH4rAOvlZ4HUiEBN X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 Now that the API is available, let's make use of it. It also handles the reinitialization of DWC non-sticky registers in addition to sending the notification to EPF drivers. Reported-by: Bjorn Helgaas Closes: https://lore.kernel.org/linux-pci/20240528195539.GA458945@bhelgaas/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Frank Li Reviewed-by: Niklas Cassel --- drivers/pci/controller/dwc/pci-layerscape-ep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index 35bb481564c7..a4a800699f89 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -104,7 +104,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) dev_dbg(pci->dev, "Link up\n"); } else if (val & PEX_PF0_PME_MES_DR_LDD) { dev_dbg(pci->dev, "Link down\n"); - pci_epc_linkdown(pci->ep.epc); + dw_pcie_ep_linkdown(&pci->ep); } else if (val & PEX_PF0_PME_MES_DR_HRD) { dev_dbg(pci->dev, "Hot reset\n"); }