From patchwork Tue Oct 22 13:30:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177161 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4874310ill; Tue, 22 Oct 2019 06:35:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqzwzu+uLrdg1EV9QTDde4jIonePFwj19SXA4nGMYhy36LhJghxRRxDj8jWQxjDmBhmQeI09 X-Received: by 2002:a17:906:bceb:: with SMTP id op11mr7119124ejb.197.1571751332734; Tue, 22 Oct 2019 06:35:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571751332; cv=none; d=google.com; s=arc-20160816; b=ml4wbkVFZWj1PyuHF9lz8ZlPnEFeuTTclvOpFaNp9E9DWyz+ZDTy/zsByxqmJiYTrX W4XKpCkcajE4Iq9WWYK3UMGhvloufJbd7AYpL4/329lq/5MzVLKd49IukM/cQdqDfapP m/uNHViD9RGiN28CDSrJDEOgO5wrt/2Ya82emEZZfGFo1VA6ROu+wkI99UZT7uv+cr21 nJT57pA5OtDkmOS6lgmVaAJCSArDPcB2paus68GSjZwh3V2fkrpSzuo+6+4QUUqVAw2D cYqNX4Epk8+w1foTgyYsTTGgZu2GYeQHFA3hzEBEq5RgDRekEYQ+mPOJAmqbrEyT8S7/ HvOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Tszmi8yysvRuCxwYylX4mScv+Q4hFjeHGWVpSd5q8fA=; b=kSGHR+gLcUvoXUK+cT2b0FkEr3n4pqxALnnga2QKuO9yo5ugKNGHGOJnT4nDrrZr9d NEVm5J6bDfD9S2dbX6Dr2Vwz1+z272Alav4P5her+9g2BjkAij7IQxKejDAFcdhs7LBp M5TngVV7EmWDqeSKj/D0esD51IeGMBKgs1ht6RwnablKM39ezU5wBxnahkCtrZUlpIad U+IlRpbX1UdafCxgw60FhCXgBLFcOmhnEsI66qNzs2I5yvolVbHoz2d8yRggtYL8HQrT yzYE36JYAnq93DWC8/Z2uRKIRTpgSR34T8yLX7AItl8wfSPke2jwaiOTbz3uCOwOFEdY ZdJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="VmRf/RQn"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r4si419387ejz.77.2019.10.22.06.35.32 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Oct 2019 06:35:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="VmRf/RQn"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57418 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iMuJu-0006Lr-LK for patch@linaro.org; Tue, 22 Oct 2019 09:35:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36555) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iMuGF-00022T-TO for qemu-devel@nongnu.org; Tue, 22 Oct 2019 09:31:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iMuGE-00017O-TT for qemu-devel@nongnu.org; Tue, 22 Oct 2019 09:31:43 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:55757) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iMuGE-00016z-NL for qemu-devel@nongnu.org; Tue, 22 Oct 2019 09:31:42 -0400 Received: by mail-wm1-x344.google.com with SMTP id g24so8122191wmh.5 for ; Tue, 22 Oct 2019 06:31:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Tszmi8yysvRuCxwYylX4mScv+Q4hFjeHGWVpSd5q8fA=; b=VmRf/RQnlFjM96sBtBuhhuo7eK2/nliOPO2lG0/lgEOZogm8B9k1WmE1mm2ZrKvhbI jxeFvOT31m1NFobO4qwvVYqaqyZ4ubiwSJrWmCfcrBQFzwQloEqgNnDGx7tI8SUtrjdw Ay2cQ8XEyMZ4ShfsvX1QwG7XX5+3HOfX9hFsyjkcp0ttSuR+NGg5ihVG+9kMR34STOTG o24PTgBxb6Chn7ZQE16mc/yatYXGuiK2eh5wZ2x8Azqh6hVWnhS0UPmJcGAVPD4TlXgv xC21xdZksFhjhdUBK19Tesc6Bb4Kn2twM+Sh9MIv9MBIFS5gfdSaWuHNkMI/U+MU/My2 Idlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Tszmi8yysvRuCxwYylX4mScv+Q4hFjeHGWVpSd5q8fA=; b=LF6eAGwg/X545HNSuhuHTzePHfyzFshrRP3icPc33lBqw+wV9h4I/GAIISP2uSUcsw tKunztF380TbI0iGlvMfiEftc8Q5brvR9xiB8SzCLy92mXsL9ab0Y30u54pUIlai2OZm HiEvTqIPvFCp/iFZrmWaWbcSPQDDaKDgKpBQXBr25oTYWBYfSzRiB1cMCiuvUm4+v6S5 /ge9lJ5SlrzwR1PwIHsCeSFdC1yBcYRo13MQcqAyk5utLqYr3BKGKQ0TLWd1D4MSglLz pQixPmKqD4MeZxNctnMDwk/vYhABQkDdoSnfbyaIqfQOxXVCvYnE3mMeACDWavnbCAiD HpmA== X-Gm-Message-State: APjAAAW+PvZrlrVXyad744ZmHD5HFeh0Zq8+CC9NxXvhjdpluu59BKsV PYCIrswYJAb7RTfXZKIES+vU8COhTaU= X-Received: by 2002:a1c:6a04:: with SMTP id f4mr3149513wmc.60.1571751101014; Tue, 22 Oct 2019 06:31:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.31.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:31:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/41] target/arm: Fix sign-extension for SMLAL* Date: Tue, 22 Oct 2019 14:30:54 +0100 Message-Id: <20191022133134.14487-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The 32-bit product should be sign-extended, not zero-extended. Fixes: ea96b374641b Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Laurent Desnogues Message-id: 20190912183058.17947-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 698c594e8ce..96340520ee2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8045,7 +8045,9 @@ static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, case 2: tl = load_reg(s, a->ra); th = load_reg(s, a->rd); - t1 = tcg_const_i32(0); + /* Sign-extend the 32-bit product to 64 bits. */ + t1 = tcg_temp_new_i32(); + tcg_gen_sari_i32(t1, t0, 31); tcg_gen_add2_i32(tl, th, tl, th, t0, t1); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); From patchwork Tue Oct 22 13:30:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177162 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4874513ill; Tue, 22 Oct 2019 06:35:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqwke18iIFX02zMuDRGMmtQ+PDYzhhi1ZqVBgLMCXpT4C5WBtVSN23lq+1c7x+3gk3GsPEKx X-Received: by 2002:a05:6402:160f:: with SMTP id f15mr30887414edv.142.1571751342664; Tue, 22 Oct 2019 06:35:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571751342; cv=none; d=google.com; s=arc-20160816; b=WfLN+8PPoe1Y9GxmCLCHCJctCAFOSV6kWkLWNNCHF9QaHFIOpm45Qdfk5stJVLCeJ2 gvM7SE6nfcPst+zFGIr0nPKkaZU774/C3ddIl8kwasd09qy7e1kOElc6q6yYFxLDFz6/ P7XJ+udzp19mWG53QbIBruRzQXBIfxFYLsqukoJpQ9vNWHbfEzjRV0Oc3eU4Oocx+hbb +eHJSC4D6VsJW3YyhXMe+J5sOVjGAKcn+faHr8YKcbUBmdr/JNQPXXs6l5qrOeLQ781Z aA7dCIYmeVbJ4LcmaRWtxANVHr1Mc+nEHL6V0G3S3rIxoTu9XWlo56J03pR4mrgcV5Wf hI0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GiGGoct5QT0NRciJUJZ8OfIOiz/gs+M8OMGCdLem8zI=; b=AABkeZcfu2MUp9D/BSjFCb4D4HYwb43nyj5GwPAA7xzBL03mIWKCdxHInynPJWzZFQ Hzahz/mKaO2qi7wzjsESxtqUAOLOWwzs1wSELQi+1P6vCyAYlmcWiYsy9g8BUnhErLm/ P+ZpiiOASjCT+KXcTlFPNgFHDmBYQEGUIX6Rdt1PaSkF+TrH5su/mQ3nDSklYwl2Ocr0 8V8kCT3O3SN+hU3B1WpnyYeKs6HM2md9jFKlp8O1RmiB3N9S/Tsk5mmKjfV/CVTHdHmH vrCzjXJh0b/kP+KuxgJ4tJvAVjv7YmGugS5QQjfa3/ZwbvWB3JjRuFvoCRuX4N5IPbux ZSHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kTThksGc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i5si12448622edj.107.2019.10.22.06.35.42 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Oct 2019 06:35:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kTThksGc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57422 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iMuK4-0006WI-Ky for patch@linaro.org; Tue, 22 Oct 2019 09:35:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36588) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iMuGK-00027r-8g for qemu-devel@nongnu.org; Tue, 22 Oct 2019 09:31:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iMuGI-00018s-QT for qemu-devel@nongnu.org; Tue, 22 Oct 2019 09:31:48 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:35259) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iMuGI-00018c-KI for qemu-devel@nongnu.org; Tue, 22 Oct 2019 09:31:46 -0400 Received: by mail-wm1-x32c.google.com with SMTP id v9so265176wml.0 for ; Tue, 22 Oct 2019 06:31:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=GiGGoct5QT0NRciJUJZ8OfIOiz/gs+M8OMGCdLem8zI=; b=kTThksGcOrvic9/PBkd9pcPAfj2nLPp2N6yEUZd5IcQ71yucX57/V5NRLEezGtUAW5 UYrsGERzSFHP/44fqkptoYtbpPituwjO6yf6j2ZfBS6/k42Oow5LjyMKGbAa9WWyogaX bx2d198S1cq3IApVjK/mYZcfiAXZpkqKqKnwNriIuCFyT0h/zYWaA0VeI7Yb7Bay31xr KlPWRcx2dx/Tq/rjsW63YyR31nnrsZO01AOzTzi3XoQQDEAlZQgoh5jlHeo1Mzv7cbX8 FqazRn4EgjcKv36IfT6H3RjQ4KfydGn4zWUPVxHN515YH+nqaDuNvWZtub6j3nZ927Jb xcvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GiGGoct5QT0NRciJUJZ8OfIOiz/gs+M8OMGCdLem8zI=; b=a2s5ZPU0/UA5E4XccMvcVL3b08Snkzr1CkPIpmx2Dq2NoDpH46Jx2QvKJ1lykCCCO8 LarTRufSrhHywkeKkMSCGYBPUtZv0pcw2wzN6VipBu3FegIHVrqPRtefo2rLe9fKK+7h b5qlFe0aOzvdSK6duMFloLdn1szsostaJB+EIQ3JsFH1wWOXzs4LO7ULvn1h4X9fzfAA h28bE+tQ6V945SsMZXv3ijDM9t91Sv6N7YrYZF1jyuqIrwhN517Eoov1YqEcy2Ydf5ph wP2nJHTBOZdZp+92pXlprOIUr/pZr8sTEdCFc21I9SHry7bOwsruD/KoE4LWyl3z+i/G snHw== X-Gm-Message-State: APjAAAWIwLmFZvPxPuDM3r3hgN5bWKPBYU/n6sVpxwPryWT3O9aAqeco LQQ0+DGhBY8ERvA6/Ake8oJbsH+9/nk= X-Received: by 2002:a1c:7d95:: with SMTP id y143mr3195982wmc.143.1571751103637; Tue, 22 Oct 2019 06:31:43 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.31.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:31:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/41] aspeed: Add an AST2600 eval board Date: Tue, 22 Oct 2019 14:30:55 +0100 Message-Id: <20191022133134.14487-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Define the board with 1 GiB of RAM but some boards can have up to 2 GiB. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Message-id: 20191016090745.15334-1-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/arm/aspeed.h | 1 + hw/arm/aspeed.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) -- 2.20.1 diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index 02073a6b4d6..f49bc7081e4 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -18,6 +18,7 @@ typedef struct AspeedBoardConfig { const char *desc; const char *soc_name; uint32_t hw_strap1; + uint32_t hw_strap2; const char *fmc_model; const char *spi_model; uint32_t num_cs; diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 52993f84b46..028191ff36f 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -88,6 +88,10 @@ struct AspeedBoardState { /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 +/* AST2600 evb hardware value */ +#define AST2600_EVB_HW_STRAP1 0x000000C0 +#define AST2600_EVB_HW_STRAP2 0x00000003 + /* * The max ram region is for firmwares that scan the address space * with load/store to guess how much RAM the SoC has. @@ -187,6 +191,8 @@ static void aspeed_board_init(MachineState *machine, &error_abort); object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1", &error_abort); + object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap2, "hw-strap2", + &error_abort); object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs", &error_abort); object_property_set_int(OBJECT(&bmc->soc), machine->smp.cpus, "num-cpus", @@ -308,6 +314,12 @@ static void ast2500_evb_i2c_init(AspeedBoardState *bmc) i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32); } +static void ast2600_evb_i2c_init(AspeedBoardState *bmc) +{ + /* Start with some devices on our I2C busses */ + ast2500_evb_i2c_init(bmc); +} + static void romulus_bmc_i2c_init(AspeedBoardState *bmc) { AspeedSoCState *soc = &bmc->soc; @@ -455,6 +467,17 @@ static const AspeedBoardConfig aspeed_boards[] = { .num_cs = 2, .i2c_init = witherspoon_bmc_i2c_init, .ram = 512 * MiB, + }, { + .name = MACHINE_TYPE_NAME("ast2600-evb"), + .desc = "Aspeed AST2600 EVB (Cortex A7)", + .soc_name = "ast2600-a0", + .hw_strap1 = AST2600_EVB_HW_STRAP1, + .hw_strap2 = AST2600_EVB_HW_STRAP2, + .fmc_model = "w25q512jv", + .spi_model = "mx66u51235f", + .num_cs = 1, + .i2c_init = ast2600_evb_i2c_init, + .ram = 1 * GiB, }, }; From patchwork Tue Oct 22 13:30:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177164 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4877429ill; Tue, 22 Oct 2019 06:38:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqzw2bouh2UioqhxX7YClJGTcCXswup9s62GPWOb1YqAXmX7F0hcRVPrrYM1AbrqkGimf2SI X-Received: by 2002:a05:620a:1222:: with SMTP id v2mr2921418qkj.156.1571751484383; Tue, 22 Oct 2019 06:38:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571751484; cv=none; d=google.com; s=arc-20160816; b=TXZZt/sOer2GfN7zE85fh7bix2X6thrtYyklmDiEgL5/VANrMONQJVRihRqS/DgFRw rNidtphlQyK2PVs/BVPVVY2o1ampQOcN/IU0rASVHSncSwdX5lAtybywT8uVO3u+x4OQ Ftcsrxq0DQ3lihGoNlQ85thy3mXIXk+fqX0gEtMPOR8uY/bIli1VW0oguh9RnKZHLNE6 NDATzz55ctFGiylwNPSnX6gfWE3cShuiUrdPtyE3i7A6DUIx4171sfHKIGORXha5DLyH qkjos14mNna0PbVhIi4Sbiz0GdMzPiQR5+M/ERG4lMH8iaJ564EcHI44BusPYrmjw/4W EJcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=y6cZwi7KnbEYaso3vcojBuwQDGlT+TuR2VSfnVl/yHw=; b=hxwwfkOCV56iBs4us6JE6HKZs1QefQu7ELDeZ3f9H7tuCRVb6I6+TAH3BLOkJBPSIs /33RswtS6p2rzYWyeqUj5WuMk8MO4hxY5lG7Oj3roVnLiXZOFdL+AhqL+ul71hXjkjnH A0vOxN07o7OZFaq2tuNNPlxJmd4r5WNEEvsZaoBm08ylh593Ay4Bnr8tX9J0KEkWiEYq f4irufbuKqsauRCLm5mC2YIUrUUHuDG2QaFGSs/sdPbobe46P0qFtNAgbLGD0mkGZjiQ RIRZ0B7FmsmnEDkrk3Zmf1RtobBvef79TualUFUiTuRRzk2aHo0N4yral3pIrAHBKSyL ZA0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Pu4HPBHE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.31.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:31:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/41] hw/timer/exynos4210_mct: Initialize ptimer before starting it Date: Tue, 22 Oct 2019 14:30:56 +0100 Message-Id: <20191022133134.14487-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Guenter Roeck When booting a recent Linux kernel, the qemu message "Timer with delta zero, disabling" is seen, apparently because a ptimer is started before being initialized. Fix the problem by initializing the offending ptimer before starting it. The bug is effectively harmless in the old QEMUBH setup because the sequence of events is: * the delta zero means the timer expires immediately * ptimer_reload() arranges for exynos4210_gfrc_event() to be called * ptimer_reload() notices the zero delta and disables the timer * later, the QEMUBH runs, and exynos4210_gfrc_event() correctly configures the timer and restarts it In the new transaction based API the bug is still harmless, but differences of when the callback function runs mean the message is not printed any more: * ptimer_run() does nothing as it's inside a transaction block * ptimer_transaction_commit() sees it has work to do and calls ptimer_reload() * the zero delta means the timer expires immediately * ptimer_reload() calls exynos4210_gfrc_event() directly * exynos4210_gfrc_event() configures the timer * the delta is no longer zero so ptimer_reload() doesn't complain (the zero-delta test is after the trigger-callback in the ptimer_reload() function) Regardless, the behaviour here was not intentional, and we should just program the ptimer correctly to start with. Signed-off-by: Guenter Roeck Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell Message-id: 20191018143149.9216-1-peter.maydell@linaro.org [PMM: Expansion/clarification of the commit message: the message is about a zero delta, not a zero period; added detail to the commit message of the analysis of what is happening and why the kernel boots even with the message; added note that the message goes away with the new ptimer API] Signed-off-by: Peter Maydell --- hw/timer/exynos4210_mct.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c index 72257584145..944120aea59 100644 --- a/hw/timer/exynos4210_mct.c +++ b/hw/timer/exynos4210_mct.c @@ -1254,7 +1254,7 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, /* Start FRC if transition from disabled to enabled */ if ((value & G_TCON_TIMER_ENABLE) > (old_val & G_TCON_TIMER_ENABLE)) { - exynos4210_gfrc_start(&s->g_timer); + exynos4210_gfrc_restart(s); } if ((value & G_TCON_TIMER_ENABLE) < (old_val & G_TCON_TIMER_ENABLE)) { From patchwork Tue Oct 22 13:30:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177159 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4873383ill; Tue, 22 Oct 2019 06:34:49 -0700 (PDT) X-Google-Smtp-Source: APXvYqzFKTmPQaxcH84UVP8oui2B+gtqQrOiEE9qvrDJEN9V2whR3ltMvvTESlxIwdu4UAhCheA7 X-Received: by 2002:a37:4c57:: with SMTP id z84mr2993865qka.208.1571751289604; Tue, 22 Oct 2019 06:34:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571751289; cv=none; d=google.com; s=arc-20160816; b=btOiSGqNlqubYMFOXIy0+TdRd88SuCStWd9B7FMQwsNQXjPER7rYJpEwmxzCkjtvXw 5euhM0R1scTjPeZwJHyTAd7soZnevDFbDATBiQ1Qliku8p/osV4G20b9/6KKszN4f6WL SK4gRsQzdJMbmqp4h8MjE9WhCv0on7Olb5kjgsQfsXF1JGWUZVkw20yXtbVlqJYsjYs0 1JMP0BdcrKqQ7E/CpEefnY0EAFpaMs6hrD9kLhFhWAPX3bNo2cFg2r9WxhTTSG4LOZ71 dIcpJ4Rkjiba6V6v1dbzkT79ya+1HHxZln7k2YErWwITPXroTcEoNQoWzG74cB0OjGAU UGtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RtZ6eDxdSnhFwcSQva9Dw3k0dUzdlcR17D7YwApDOzk=; b=rsvlfEvxlzYM4RCc13p3LeA9GBfDxWrW6eVs0z3heTaleUFkjwWJrkq5JD6Hfl86WD gu5lYS14wqtdX0OawOlvxQkCQTjm88x4v9cPjl/O8g7uCzpXwXh888sZSuGIfS6IYrzn QIN7uxDrjnGqTIcBQICEIz/OOgXaprmxOIAXU6AbNy6kypLfC2XCV1zXfHAw+pUs5qqO YmhTyuWjXHOAhwDcelunFs81xvpv7ZtEdDlbOVTCGq1xNol9e2PDHmnrjZG2fqPvRRgG jVXJWe8cVzZGmrqGnk0EC5MAzGCq6IHOmAg18PzGOCZsi3AenMbitY8sgjtFbiY4zc/M bZwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q5yOAHES; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.31.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:31:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/41] hw/timer/arm_mptimer.c: Undo accidental rename of arm_mptimer_init() Date: Tue, 22 Oct 2019 14:30:57 +0100 Message-Id: <20191022133134.14487-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In commit b01422622b we did an automated rename of the ptimer_init() function to ptimer_init_with_bh(). Unfortunately this caught the unrelated arm_mptimer_init() function. Undo that accidental renaming. Fixes: b01422622b7c7293196fdaf1dbb4f495af44ecf9 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20191017133331.5901-1-peter.maydell@linaro.org --- hw/timer/arm_mptimer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index fdf97d1800f..2bf11f788c3 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -237,7 +237,7 @@ static void arm_mptimer_reset(DeviceState *dev) } } -static void arm_mptimer_init_with_bh(Object *obj) +static void arm_mptimer_init(Object *obj) { ARMMPTimerState *s = ARM_MPTIMER(obj); @@ -319,7 +319,7 @@ static const TypeInfo arm_mptimer_info = { .name = TYPE_ARM_MPTIMER, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(ARMMPTimerState), - .instance_init = arm_mptimer_init_with_bh, + .instance_init = arm_mptimer_init, .class_init = arm_mptimer_class_init, }; From patchwork Tue Oct 22 13:30:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177165 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4877565ill; Tue, 22 Oct 2019 06:38:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqwX3HNXG4HKZfoU5DSCN8TWwcSXZ1GZcRxwZSGLOTAqk8gvt8VN7b1SpArPdJfyiIjbLUxb X-Received: by 2002:ac8:6783:: with SMTP id b3mr3335375qtp.25.1571751489303; Tue, 22 Oct 2019 06:38:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571751489; cv=none; d=google.com; s=arc-20160816; b=c6eD2tKJyoRDoDzgf+/LkVbXETsHGzorSR9ILeTk1rOXKjBhsVzQeo7hH+AiauGMiH R/To343nNWhzSRe4ENs8DsYlIjiIcUsifhp0ra8F/vKoOufUVCk1WX41u69H63TvkCc3 EKxpP/E2kVBeIxx5K+vtB/yl2/hptAMsvxoLXNCnbV7EBjpy0D2vi0u5QQPyKdS97Kda I23oMZEt8zMgKuJX8Bw4W/wyTRAGrO3JorOmUiM5KHaDwuPZu/idErcwtF1Zf61FptC1 CNB+LuvKRBPiD1SegN1LDfRKXbpZsv2ebXa1s+1MHOlReP3f9UfRxxquF3UNLM+c84AF q1XA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JUEy3Kpo6e4fixjUzNZTRmi2uqnm25sL1IZPSuv+MZM=; b=L02yuRVfRr6rZUir0YBOksNYnorocMqwq3GQld4SNuTkZlt3RMJ80GADd5vPKnkgAL ftc2fm1nsK+mQBskqAPT1RnV6BZIk80FcChRZm53S0EPvEXd0SqmNo0esU9XLeitnkNU JFARzh9sepqCagP3+d2zskJyuUoNDyXZ5e7vgjdGM1WYaGAtfO6QINbN1FJsb9OWQgjq b6BNTulofrr9paIRmkGyVoVeUnMD6n1NBpTWf0PplL3Df3yBLgTKWc13N73/bEDMyUpR bB3efqhEDtak/l2M41pitKL7iwB1loVmJhd5jc0d/UX5sjEKstoNhRcHK14V8VeA3cs8 eSvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RPmklUmD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.31.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:31:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/41] hw/timer/puv3_ost.c: Switch to transaction-based ptimer API Date: Tue, 22 Oct 2019 14:30:58 +0100 Message-Id: <20191022133134.14487-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the puv3_ost code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20191017132905.5604-2-peter.maydell@linaro.org --- hw/timer/puv3_ost.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/hw/timer/puv3_ost.c b/hw/timer/puv3_ost.c index 0898da5ce97..697519593bb 100644 --- a/hw/timer/puv3_ost.c +++ b/hw/timer/puv3_ost.c @@ -13,7 +13,6 @@ #include "hw/sysbus.h" #include "hw/irq.h" #include "hw/ptimer.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #undef DEBUG_PUV3 @@ -27,7 +26,6 @@ typedef struct PUV3OSTState { SysBusDevice parent_obj; MemoryRegion iomem; - QEMUBH *bh; qemu_irq irq; ptimer_state *ptimer; @@ -68,6 +66,7 @@ static void puv3_ost_write(void *opaque, hwaddr offset, DPRINTF("offset 0x%x, value 0x%x\n", offset, value); switch (offset) { case 0x00: /* Match Register 0 */ + ptimer_transaction_begin(s->ptimer); s->reg_OSMR0 = value; if (s->reg_OSMR0 > s->reg_OSCR) { ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR); @@ -76,6 +75,7 @@ static void puv3_ost_write(void *opaque, hwaddr offset, (0xffffffff - s->reg_OSCR)); } ptimer_run(s->ptimer, 2); + ptimer_transaction_commit(s->ptimer); break; case 0x14: /* Status Register */ assert(value == 0); @@ -128,9 +128,10 @@ static void puv3_ost_realize(DeviceState *dev, Error **errp) sysbus_init_irq(sbd, &s->irq); - s->bh = qemu_bh_new(puv3_ost_tick, s); - s->ptimer = ptimer_init_with_bh(s->bh, PTIMER_POLICY_DEFAULT); + s->ptimer = ptimer_init(puv3_ost_tick, s, PTIMER_POLICY_DEFAULT); + ptimer_transaction_begin(s->ptimer); ptimer_set_freq(s->ptimer, 50 * 1000 * 1000); + ptimer_transaction_commit(s->ptimer); memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost", PUV3_REGS_OFFSET); From patchwork Tue Oct 22 13:30:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177168 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4881183ill; Tue, 22 Oct 2019 06:40:58 -0700 (PDT) X-Google-Smtp-Source: APXvYqz0xWCp+uPVCcwzao+akOoGJdzGUGnUsxb8uJCqlcJV4GJZd18oGhs5OnyyERFfD4F3U9R/ X-Received: by 2002:aed:21f6:: with SMTP id m51mr3347494qtc.307.1571751658606; Tue, 22 Oct 2019 06:40:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571751658; cv=none; d=google.com; s=arc-20160816; b=GjMSV94r83Ztl7kd6Nc94IRZaKrS2OvgYElZ16AW1UseenBttZyntVKXzn/jdXOZXJ 8Tt44Gt36RCiAqnSC0z2NsjaiKmvOJ7vfPPgAtlG+Ek9TVMIP56ntKpT4LuASuR0CELf KFFVKtjnsAf7hba/BSvMgna8DHcl6ednTQvUZrJzG6yzr52SXIr1VBh2U3RqPucyIayN /zljqXoHslqDAXQRDKGOgvUFMKMjJXv/PjHwfy9PcSsy8sk5Gg4h/ScjX6qwJeLQMfWi mx2NSFn8m3Khb7ir/DhrGYQO5FyN160eehCfPgnEllw3j2dYvkq2ZwMuztdGsgfePWNS EssA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uDrLBjDpGth9A9xH8MMq1NWvBIh2l7Tya6vjM+QNwc0=; b=AZtHAjy4viwAxYNv6ALAuenIwJfUyTmYNFysOTi3+r3ptT/82ltJt1MfHMK2jxxLH2 fQt7eBZgsHHAv560aodRL0WPQZaFdrV0Un/arAjZbHJ80SZHM6Dx6Whzt4w7G3XXqkiX jhoAlMK/usKFKm+0Q/Ua4m6SkWDAO0RrZ0hS+QdvAAm9EDohtXJ7k4ruAWf0q5unOUpu 3JlGQLNua5QpY/G2vBhnsTMSq4/eZV3wsW42NcyVOkXKtWybeNjPAzu+zGpdKCd7WUy7 4w72rXS64g5ci+Y5Rs2Q0YgFHj7kapVKf10mkQpMUE5fs0+GR1hwcX4VXYy5sy4DSM1M g0zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pU9FpmRx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.31.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:31:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/41] hw/timer/sh_timer: Switch to transaction-based ptimer API Date: Tue, 22 Oct 2019 14:30:59 +0100 Message-Id: <20191022133134.14487-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the sh_timer code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20191017132905.5604-3-peter.maydell@linaro.org --- hw/timer/sh_timer.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 48a81b4dc79..13c4051808f 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -13,7 +13,6 @@ #include "hw/irq.h" #include "hw/sh4/sh.h" #include "qemu/timer.h" -#include "qemu/main-loop.h" #include "hw/ptimer.h" //#define DEBUG_TIMER @@ -91,13 +90,18 @@ static void sh_timer_write(void *opaque, hwaddr offset, switch (offset >> 2) { case OFFSET_TCOR: s->tcor = value; + ptimer_transaction_begin(s->timer); ptimer_set_limit(s->timer, s->tcor, 0); + ptimer_transaction_commit(s->timer); break; case OFFSET_TCNT: s->tcnt = value; + ptimer_transaction_begin(s->timer); ptimer_set_count(s->timer, s->tcnt); + ptimer_transaction_commit(s->timer); break; case OFFSET_TCR: + ptimer_transaction_begin(s->timer); if (s->enabled) { /* Pause the timer if it is running. This may cause some inaccuracy dure to rounding, but avoids a whole lot of other @@ -148,6 +152,7 @@ static void sh_timer_write(void *opaque, hwaddr offset, /* Restart the timer if still enabled. */ ptimer_run(s->timer, 0); } + ptimer_transaction_commit(s->timer); break; case OFFSET_TCPR: if (s->feat & TIMER_FEAT_CAPT) { @@ -168,12 +173,14 @@ static void sh_timer_start_stop(void *opaque, int enable) printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled); #endif + ptimer_transaction_begin(s->timer); if (s->enabled && !enable) { ptimer_stop(s->timer); } if (!s->enabled && enable) { ptimer_run(s->timer, 0); } + ptimer_transaction_commit(s->timer); s->enabled = !!enable; #ifdef DEBUG_TIMER @@ -191,7 +198,6 @@ static void sh_timer_tick(void *opaque) static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) { sh_timer_state *s; - QEMUBH *bh; s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state)); s->freq = freq; @@ -203,8 +209,7 @@ static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) s->enabled = 0; s->irq = irq; - bh = qemu_bh_new(sh_timer_tick, s); - s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); + s->timer = ptimer_init(sh_timer_tick, s, PTIMER_POLICY_DEFAULT); sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor); sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt); From patchwork Tue Oct 22 13:31:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177163 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4877315ill; Tue, 22 Oct 2019 06:38:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqx0+Vg7zMdPFOCT79ELOj/3oG+BXJ/2SG21Yd7ZqPwY4hRyIC4aIsBOR6OwG3aXSiEUrqaJ X-Received: by 2002:ac8:3475:: with SMTP id v50mr3355882qtb.105.1571751480159; Tue, 22 Oct 2019 06:38:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571751480; cv=none; d=google.com; s=arc-20160816; b=m9Kn9FJ7Bxg6QCKkVdSCH7yI+RLys7T0DpULKdlC+XZL9qVlECBUVW6W3kABt0ls5E 19MVx5rERGA2XMBvTbqf3vwMOsssM4UM8KbF1dHMqKBpO0OJTdj2ctVAW4RVLF7ccldg 5wEhre+oJKIwX1X3MLLiwCNtQOuS1Wac7z0ROYGbvnuHXKawzS/sV9oGQGEJ50jKpnJg wCx9sJp+I1vJ0Tt4aridyL6CwIqpk/UWYWdNe7EEAsRq3rXoF+UGNRaiRoeGjFaE0GJ5 T5lZif9UWo46ISW6xe9k7R8DST/sbmDOwBB9zA4zC9GdXrmGvpZ5mtsG+6wKHrpSm1kj kQrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=62R1pMICSQgalMj3UXUALVQERlO54EdusG7o+yE6TlY=; b=Kdhj/AO+QHWPMAPaBWFN04Tw+lIqlPw2hGXccJUQZze94nNbCR3j9FKtCOBEAwSquN e98dBX0+v4Tcqdp1sjSqZdmWbGZMlZxmozs62OYKg/r8HxEhjMydQ2wvgZgqck1WzSgF Ql+0BIBJtPqROGde4U5wGnr7AU+WoYEcVYXPwy1FQVcB6nun7moaoFZX1z3T8Q4PBsHh hxTEX7N0P+QP4+U1uf4wUYZjmfdVHegQZ7NcMbPbWdtD84FfIjGAann77tHFvbd03iaE RKio0yv/Dk8n1RALcff2tWDnSECdFLhrk4ZbgGDWA5CMfmU/lyp+rp5RFXllKAbJDQ6y QIAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Z4vb/i3R"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.31.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:31:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/41] hw/timer/lm32_timer: Switch to transaction-based ptimer API Date: Tue, 22 Oct 2019 14:31:00 +0100 Message-Id: <20191022133134.14487-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the lm32_timer code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the ytimer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20191017132905.5604-4-peter.maydell@linaro.org --- hw/timer/lm32_timer.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/hw/timer/lm32_timer.c b/hw/timer/lm32_timer.c index fabde760b2d..3fdecd09fe2 100644 --- a/hw/timer/lm32_timer.c +++ b/hw/timer/lm32_timer.c @@ -30,7 +30,6 @@ #include "hw/ptimer.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #define DEFAULT_FREQUENCY (50*1000000) @@ -63,7 +62,6 @@ struct LM32TimerState { MemoryRegion iomem; - QEMUBH *bh; ptimer_state *ptimer; qemu_irq irq; @@ -119,6 +117,7 @@ static void timer_write(void *opaque, hwaddr addr, s->regs[R_SR] &= ~SR_TO; break; case R_CR: + ptimer_transaction_begin(s->ptimer); s->regs[R_CR] = value; if (s->regs[R_CR] & CR_START) { ptimer_run(s->ptimer, 1); @@ -126,10 +125,13 @@ static void timer_write(void *opaque, hwaddr addr, if (s->regs[R_CR] & CR_STOP) { ptimer_stop(s->ptimer); } + ptimer_transaction_commit(s->ptimer); break; case R_PERIOD: s->regs[R_PERIOD] = value; + ptimer_transaction_begin(s->ptimer); ptimer_set_count(s->ptimer, value); + ptimer_transaction_commit(s->ptimer); break; case R_SNAPSHOT: error_report("lm32_timer: write access to read only register 0x" @@ -176,7 +178,9 @@ static void timer_reset(DeviceState *d) for (i = 0; i < R_MAX; i++) { s->regs[i] = 0; } + ptimer_transaction_begin(s->ptimer); ptimer_stop(s->ptimer); + ptimer_transaction_commit(s->ptimer); } static void lm32_timer_init(Object *obj) @@ -195,10 +199,11 @@ static void lm32_timer_realize(DeviceState *dev, Error **errp) { LM32TimerState *s = LM32_TIMER(dev); - s->bh = qemu_bh_new(timer_hit, s); - s->ptimer = ptimer_init_with_bh(s->bh, PTIMER_POLICY_DEFAULT); + s->ptimer = ptimer_init(timer_hit, s, PTIMER_POLICY_DEFAULT); + ptimer_transaction_begin(s->ptimer); ptimer_set_freq(s->ptimer, s->freq_hz); + ptimer_transaction_commit(s->ptimer); } static const VMStateDescription vmstate_lm32_timer = { From patchwork Tue Oct 22 13:31:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177169 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4881295ill; Tue, 22 Oct 2019 06:41:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqzNZNeCN2FU0/0lAA7RJ5yFfV39PYza3sTzvVq8r/6eRdlPGpOyz2ZNZizADL6KHew0Jgpg X-Received: by 2002:ac8:1408:: with SMTP id k8mr3273291qtj.327.1571751664369; Tue, 22 Oct 2019 06:41:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571751664; cv=none; d=google.com; s=arc-20160816; b=EASDj1Obq+v6Ck8Dr3e0D1ZYjlUONOtvlhrSEoRIEbXYQNE0anZjHqmoJ7v4HWgOYB lAKLspcHvZVqe0axNRyb4c/h38RxlpW3ij6iCwvJEsQ3qaOagm8OCPCxw8ZEq2SG9YXz jhohPNxyL9r65EG3ooxPgS1u0I6hO0oCxS53klnWhyXINwSHZWml7eaHaE/2KS/j0uey aw+7E1we6DS5anm3XZBpYATUTWTnLMZkFshx/7pgG3PEnO8S8ocP0b2tTe0Qu3Sdp5p0 PXX/LS1rLiyYqbT+9VP6FH49nDtkCAQnkMxqX3LHYhy4vXVy9j3xtBxJywVioK/yYpLs o3hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=S/QCyLDKmYi4qFNoLejQGFlQ6w8d+jjMc7szR08wghI=; b=wmOzWqxuW6UAAEZnM5UBPlb7rFCyKX7E372E7ffCoMwXlk7Q1XYvlryq1huLoYdQl1 GnPL9d1/eOd6kHHIlnLqwMmH2p1paTrPeWa5u9F8sF3unaxkRbIilHqEuwiXVZh60XjC EFAO81pnQDfHMpSb2I34FWS1YpxbOxBDDV6bYr+MI6C74gZnc4uVkhyhJHda/x1tnfSB zmT6PnxLNuEhr8Iy3OrxeWtnWqUVIzvpYcRgcPTQoTCEIaUHjIxmcBIpmtkCA76Z0myj FQPPQ5MItanKXpkJrZ+3lrr2Vh9zewbPn+yx3f9ICiJIb1kSgGmKEepAIhANc7zlmFOp N+TA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xRrPIVPZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.31.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:31:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/41] hw/timer/altera_timer.c: Switch to transaction-based ptimer API Date: Tue, 22 Oct 2019 14:31:01 +0100 Message-Id: <20191022133134.14487-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the altera_timer code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20191017132905.5604-6-peter.maydell@linaro.org --- hw/timer/altera_timer.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/hw/timer/altera_timer.c b/hw/timer/altera_timer.c index ee32e0ec1ff..79fc381252d 100644 --- a/hw/timer/altera_timer.c +++ b/hw/timer/altera_timer.c @@ -19,7 +19,6 @@ */ #include "qemu/osdep.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "qapi/error.h" @@ -53,7 +52,6 @@ typedef struct AlteraTimer { MemoryRegion mmio; qemu_irq irq; uint32_t freq_hz; - QEMUBH *bh; ptimer_state *ptimer; uint32_t regs[R_MAX]; } AlteraTimer; @@ -105,6 +103,7 @@ static void timer_write(void *opaque, hwaddr addr, break; case R_CONTROL: + ptimer_transaction_begin(t->ptimer); t->regs[R_CONTROL] = value & (CONTROL_ITO | CONTROL_CONT); if ((value & CONTROL_START) && !(t->regs[R_STATUS] & STATUS_RUN)) { @@ -115,10 +114,12 @@ static void timer_write(void *opaque, hwaddr addr, ptimer_stop(t->ptimer); t->regs[R_STATUS] &= ~STATUS_RUN; } + ptimer_transaction_commit(t->ptimer); break; case R_PERIODL: case R_PERIODH: + ptimer_transaction_begin(t->ptimer); t->regs[addr] = value & 0xFFFF; if (t->regs[R_STATUS] & STATUS_RUN) { ptimer_stop(t->ptimer); @@ -126,6 +127,7 @@ static void timer_write(void *opaque, hwaddr addr, } tvalue = (t->regs[R_PERIODH] << 16) | t->regs[R_PERIODL]; ptimer_set_limit(t->ptimer, tvalue + 1, 1); + ptimer_transaction_commit(t->ptimer); break; case R_SNAPL: @@ -183,9 +185,10 @@ static void altera_timer_realize(DeviceState *dev, Error **errp) return; } - t->bh = qemu_bh_new(timer_hit, t); - t->ptimer = ptimer_init_with_bh(t->bh, PTIMER_POLICY_DEFAULT); + t->ptimer = ptimer_init(timer_hit, t, PTIMER_POLICY_DEFAULT); + ptimer_transaction_begin(t->ptimer); ptimer_set_freq(t->ptimer, t->freq_hz); + ptimer_transaction_commit(t->ptimer); memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_ALTERA_TIMER, R_MAX * sizeof(uint32_t)); @@ -204,8 +207,10 @@ static void altera_timer_reset(DeviceState *dev) { AlteraTimer *t = ALTERA_TIMER(dev); + ptimer_transaction_begin(t->ptimer); ptimer_stop(t->ptimer); ptimer_set_limit(t->ptimer, 0xffffffff, 1); + ptimer_transaction_commit(t->ptimer); memset(t->regs, 0, sizeof(t->regs)); } From patchwork Tue Oct 22 13:31:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177166 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4879385ill; Tue, 22 Oct 2019 06:39:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqw6aSJmuPSMt5tS4dLk27qOSklJMTRn+BxgYkvVRKlfdwis1n3I+h8yDv32OKkHHwdlJV9l X-Received: by 2002:a05:620a:16cb:: with SMTP id a11mr3010790qkn.415.1571751571082; Tue, 22 Oct 2019 06:39:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571751571; cv=none; d=google.com; s=arc-20160816; b=KnfnteQ3sw4/cfh8duTAYnsZxjWNZ90mzhCeWVyPJISbms7ZSgvDyR19yEcVevxRV4 +ohPU03zDLmATNL6EbefS7tfOYqp/bm8ZOFM1jW2+TKVaLzt4oORmmK9ynEVu6wzb0fP Te1dTcIufu6j2xz67dr/AaNzEggWApn2vl4+7v4HuRWfZmVDqy3uU992EJjniFREU3ue uakkx1omb2kpvm7yeQYnW9CA+vQOF/7B7jEV25FbxLyyhwT4OQ3aM2b/s36RnOdvybE3 bF6c8mWZazYf9wCrBrE+hvTIjMn2l7+kK5kh2b0PARLg6QAd5Lki3VCgrQVhpW3MKO5c gGPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=c/CnNVHFORCd4oE1CaU05xljf7UHrrubl901brpFpx8=; b=IToKyJyY4gsDxemnp26IkeW5/ITdUBQSJJAzNpFjo9OBa5J2UWb+BB9wsgDCpQD3M9 yQw3aa9xfhZwWwTO9eEXZEiPeUsFd7NuWpnwEyRxKaU9cHMhfE3ao3dAKbeNimvmwXbi lcBkm2YGssv//G7oy+7GK+bhF+ktY73HYNAIbJZm8PD/mC7WjGXN1iWl5PO2vR6i/Hrg SQjh3aLa+aW2oXXt2RP8Cd7lFhKjLGbwQVIE6jOMAYC8nZBQDT3Az5Y6uWhnhDrt7m+y FeDpGTf6TkjqKdO4bvkqpm/oD5Cap/1ohJ8Z6VVYaNLCwJymZrjHcrrl+jDhNB8pCHqw cIww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bDjuAcZw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/41] hw/watchdog/etraxfs_timer.c: Switch to transaction-based ptimer API Date: Tue, 22 Oct 2019 14:31:02 +0100 Message-Id: <20191022133134.14487-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the etraxfs_timer code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20191017132905.5604-7-peter.maydell@linaro.org --- hw/timer/etraxfs_timer.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) -- 2.20.1 diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c index ab27fe1895b..afe3d30a8ea 100644 --- a/hw/timer/etraxfs_timer.c +++ b/hw/timer/etraxfs_timer.c @@ -26,7 +26,6 @@ #include "hw/sysbus.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" -#include "qemu/main-loop.h" #include "qemu/module.h" #include "qemu/timer.h" #include "hw/irq.h" @@ -59,9 +58,6 @@ typedef struct ETRAXTimerState { qemu_irq irq; qemu_irq nmi; - QEMUBH *bh_t0; - QEMUBH *bh_t1; - QEMUBH *bh_wd; ptimer_state *ptimer_t0; ptimer_state *ptimer_t1; ptimer_state *ptimer_wd; @@ -155,6 +151,7 @@ static void update_ctrl(ETRAXTimerState *t, int tnum) } D(printf ("freq_hz=%d div=%d\n", freq_hz, div)); + ptimer_transaction_begin(timer); ptimer_set_freq(timer, freq_hz); ptimer_set_limit(timer, div, 0); @@ -176,6 +173,7 @@ static void update_ctrl(ETRAXTimerState *t, int tnum) abort(); break; } + ptimer_transaction_commit(timer); } static void timer_update_irq(ETRAXTimerState *t) @@ -240,6 +238,7 @@ static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value) t->wd_hits = 0; + ptimer_transaction_begin(t->ptimer_wd); ptimer_set_freq(t->ptimer_wd, 760); if (wd_cnt == 0) wd_cnt = 256; @@ -250,6 +249,7 @@ static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value) ptimer_stop(t->ptimer_wd); t->rw_wd_ctrl = value; + ptimer_transaction_commit(t->ptimer_wd); } static void @@ -311,9 +311,15 @@ static void etraxfs_timer_reset(void *opaque) { ETRAXTimerState *t = opaque; + ptimer_transaction_begin(t->ptimer_t0); ptimer_stop(t->ptimer_t0); + ptimer_transaction_commit(t->ptimer_t0); + ptimer_transaction_begin(t->ptimer_t1); ptimer_stop(t->ptimer_t1); + ptimer_transaction_commit(t->ptimer_t1); + ptimer_transaction_begin(t->ptimer_wd); ptimer_stop(t->ptimer_wd); + ptimer_transaction_commit(t->ptimer_wd); t->rw_wd_ctrl = 0; t->r_intr = 0; t->rw_intr_mask = 0; @@ -325,12 +331,9 @@ static void etraxfs_timer_realize(DeviceState *dev, Error **errp) ETRAXTimerState *t = ETRAX_TIMER(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - t->bh_t0 = qemu_bh_new(timer0_hit, t); - t->bh_t1 = qemu_bh_new(timer1_hit, t); - t->bh_wd = qemu_bh_new(watchdog_hit, t); - t->ptimer_t0 = ptimer_init_with_bh(t->bh_t0, PTIMER_POLICY_DEFAULT); - t->ptimer_t1 = ptimer_init_with_bh(t->bh_t1, PTIMER_POLICY_DEFAULT); - t->ptimer_wd = ptimer_init_with_bh(t->bh_wd, PTIMER_POLICY_DEFAULT); + t->ptimer_t0 = ptimer_init(timer0_hit, t, PTIMER_POLICY_DEFAULT); + t->ptimer_t1 = ptimer_init(timer1_hit, t, PTIMER_POLICY_DEFAULT); + t->ptimer_wd = ptimer_init(watchdog_hit, t, PTIMER_POLICY_DEFAULT); sysbus_init_irq(sbd, &t->irq); sysbus_init_irq(sbd, &t->nmi); From patchwork Tue Oct 22 13:31:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177170 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4882240ill; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/41] hw/m68k/mcf5208.c: Switch to transaction-based ptimer API Date: Tue, 22 Oct 2019 14:31:03 +0100 Message-Id: <20191022133134.14487-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch the mcf5208 code away from bottom-half based ptimers to the new transaction-based ptimer API. This just requires adding begin/commit calls around the various places that modify the ptimer state, and using the new ptimer_init() function to create the timer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Thomas Huth Message-id: 20191017132905.5604-9-peter.maydell@linaro.org --- hw/m68k/mcf5208.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c index 34d34eba17c..158c5e4be75 100644 --- a/hw/m68k/mcf5208.c +++ b/hw/m68k/mcf5208.c @@ -9,7 +9,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qemu/error-report.h" -#include "qemu/main-loop.h" #include "qapi/error.h" #include "qemu-common.h" #include "cpu.h" @@ -79,6 +78,7 @@ static void m5208_timer_write(void *opaque, hwaddr offset, return; } + ptimer_transaction_begin(s->timer); if (s->pcsr & PCSR_EN) ptimer_stop(s->timer); @@ -94,8 +94,10 @@ static void m5208_timer_write(void *opaque, hwaddr offset, if (s->pcsr & PCSR_EN) ptimer_run(s->timer, 0); + ptimer_transaction_commit(s->timer); break; case 2: + ptimer_transaction_begin(s->timer); s->pmr = value; s->pcsr &= ~PCSR_PIF; if ((s->pcsr & PCSR_RLD) == 0) { @@ -104,6 +106,7 @@ static void m5208_timer_write(void *opaque, hwaddr offset, } else { ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW); } + ptimer_transaction_commit(s->timer); break; case 4: break; @@ -182,7 +185,6 @@ static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic) { MemoryRegion *iomem = g_new(MemoryRegion, 1); m5208_timer_state *s; - QEMUBH *bh; int i; /* SDRAMC. */ @@ -191,8 +193,7 @@ static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic) /* Timers. */ for (i = 0; i < 2; i++) { s = g_new0(m5208_timer_state, 1); - bh = qemu_bh_new(m5208_timer_trigger, s); - s->timer = ptimer_init_with_bh(bh, PTIMER_POLICY_DEFAULT); + s->timer = ptimer_init(m5208_timer_trigger, s, PTIMER_POLICY_DEFAULT); memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s, "m5208-timer", 0x00004000); memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i, From patchwork Tue Oct 22 13:31:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177171 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4884243ill; Tue, 22 Oct 2019 06:43:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqxpPHbGT2N5DrU6RVswd47AIC3A9QpCe0oCyXfp19VHRAGpuCEvlJXQe5tiLT+mGkWIzlf5 X-Received: by 2002:a0c:c1c3:: with SMTP id v3mr2418507qvh.46.1571751806114; Tue, 22 Oct 2019 06:43:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571751806; cv=none; d=google.com; s=arc-20160816; b=vXJyh+8f7+pL8uJ+Cg+pNZOaneF92hLePgxpPub5GFDWDJ6l7Ln9s6L0RxrfDk5152 qsUPjrmwmNThX32sViGpDaaElKMMKu5RSDEZO/JOxVJGupXWwaE87prdPVAGhDVhws+F 2K0bOdujaqBEfpDLy7zwCV2MfGR4RUl6Vrpb4m4ZxgeiC0OfriQS7X6a7Sqysatildcl Ls1khRPTHDTKc9ZC3K58JTGNd33TYaB/OiqSxisAEEB3wjIpwSI7Lc26hAaRNJ8c0oR4 p9onaM/JNlnggDgybTHrJTMF/fIr6xOPgun76ZiRzsFhgPhLadbFpFQC0TfKJ0eM0Qic Oidg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=emBzWLxUZK2MevrSuS1VObn1t11YZXLXP0lH9BsVSFU=; b=GzMIeno4Ek8Q3LlYSQA7613PWpO5YauIh39kjLo2qdls60af3iY1TS4NfX3YM/z37n 2WzxLpQB1i08RSJ15NSzLDoiCcltZE2JEDUzlOln4lMa4HGj8cKCr8nNQq/G9GNM1ZKq abw6mx9vHwYjcUJ9YlMGaxr+STxt9Hux0cJYTm7YjMYHHOxcNKtNq0mhh/khKwHPrP7E cshoWf5NrivTDAFoy2n+wX2xk0YFiAFCSlNo4XcC9LtgayNQMd9GaUzmB1iult8ctrb4 RmCG4N4D/MXN37CxCP/1SsKwOA4/B7YNT88n+N2Z9jJt3DeAPxvY5SSHSarvDA7KdAth OTfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BVHjo1Ol; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/41] target/arm: Split out rebuild_hflags_common Date: Tue, 22 Oct 2019 14:31:04 +0100 Message-Id: <20191022133134.14487-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Create a function to compute the values of the TBFLAG_ANY bits that will be cached. For now, the env->hflags variable is not used, and the results are fed back to cpu_get_tb_cpu_state. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 29 ++++++++++++++++++----------- target/arm/helper.c | 26 +++++++++++++++++++------- 2 files changed, 37 insertions(+), 18 deletions(-) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 297ad5e47ad..ad79a6153bb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -231,6 +231,9 @@ typedef struct CPUARMState { uint32_t pstate; uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ + /* Cached TBFLAGS state. See below for which bits are included. */ + uint32_t hflags; + /* Frequently accessed CPSR bits are stored separately for efficiency. This contains all the other bits. Use cpsr_{read,write} to access the whole CPSR. */ @@ -3140,15 +3143,18 @@ typedef ARMCPU ArchCPU; #include "exec/cpu-all.h" -/* Bit usage in the TB flags field: bit 31 indicates whether we are +/* + * Bit usage in the TB flags field: bit 31 indicates whether we are * in 32 or 64 bit mode. The meaning of the other bits depends on that. * We put flags which are shared between 32 and 64 bit mode at the top * of the word, and flags which apply to only one mode at the bottom. + * + * Unless otherwise noted, these bits are cached in env->hflags. */ FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) FIELD(TBFLAG_ANY, MMUIDX, 28, 3) FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) -FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) +FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */ /* Target EL if we take a floating-point-disabled exception */ FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) FIELD(TBFLAG_ANY, BE_DATA, 23, 1) @@ -3159,13 +3165,14 @@ FIELD(TBFLAG_ANY, BE_DATA, 23, 1) FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2) /* Bit usage when in AArch32 state: */ -FIELD(TBFLAG_A32, THUMB, 0, 1) -FIELD(TBFLAG_A32, VECLEN, 1, 3) -FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) +FIELD(TBFLAG_A32, THUMB, 0, 1) /* Not cached. */ +FIELD(TBFLAG_A32, VECLEN, 1, 3) /* Not cached. */ +FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) /* Not cached. */ /* * We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime. This shares the same bits as * VECSTRIDE, which is OK as no XScale CPU has VFP. + * Not cached, because VECLEN+VECSTRIDE are not cached. */ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) /* @@ -3174,15 +3181,15 @@ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) * the same thing as the current security state of the processor! */ FIELD(TBFLAG_A32, NS, 6, 1) -FIELD(TBFLAG_A32, VFPEN, 7, 1) -FIELD(TBFLAG_A32, CONDEXEC, 8, 8) +FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Not cached. */ +FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) /* For M profile only, set if FPCCR.LSPACT is set */ -FIELD(TBFLAG_A32, LSPACT, 18, 1) +FIELD(TBFLAG_A32, LSPACT, 18, 1) /* Not cached. */ /* For M profile only, set if we must create a new FP context */ -FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) +FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) /* Not cached. */ /* For M profile only, set if FPCCR.S does not match current security state */ -FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) +FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) /* Not cached. */ /* For M profile only, Handler (ie not Thread) mode */ FIELD(TBFLAG_A32, HANDLER, 21, 1) /* For M profile only, whether we should generate stack-limit checks */ @@ -3194,7 +3201,7 @@ FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) -FIELD(TBFLAG_A64, BTYPE, 10, 2) +FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ FIELD(TBFLAG_A64, TBID, 12, 2) static inline bool bswap_code(bool sctlr_b) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0d9a2d2ab74..8829d91ae1d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11054,6 +11054,22 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) } #endif +static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, uint32_t flags) +{ + flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); + flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, + arm_to_core_mmu_idx(mmu_idx)); + + if (arm_cpu_data_is_big_endian(env)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + } + if (arm_singlestep_active(env)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); + } + return flags; +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -11145,7 +11161,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } - flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); + flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags); /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: @@ -11153,9 +11169,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * 0 x Inactive (the TB flag for SS is always 0) * 1 0 Active-pending * 1 1 Active-not-pending + * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. */ - if (arm_singlestep_active(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); + if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE)) { if (is_a64(env)) { if (env->pstate & PSTATE_SS) { flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); @@ -11166,10 +11182,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } } - if (arm_cpu_data_is_big_endian(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); - } - flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); if (arm_v7m_is_handler_mode(env)) { flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); From patchwork Tue Oct 22 13:31:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177172 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4884734ill; Tue, 22 Oct 2019 06:43:49 -0700 (PDT) X-Google-Smtp-Source: APXvYqyWts5K/dfxz9cxDR1UIZ4VskyzNAmNSeMo53RttbxZ/g8lDRKL125PCR8vQzT+C0yE71CO X-Received: by 2002:ac8:22f1:: with SMTP id g46mr3406711qta.12.1571751828928; Tue, 22 Oct 2019 06:43:48 -0700 (PDT) ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/41] target/arm: Split out rebuild_hflags_a64 Date: Tue, 22 Oct 2019 14:31:05 +0100 Message-Id: <20191022133134.14487-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Create a function to compute the values of the TBFLAG_A64 bits that will be cached. For now, the env->hflags variable is not used, and the results are fed back to cpu_get_tb_cpu_state. Note that not all BTI related flags are cached, so we have to test the BTI feature twice -- once for those bits moved out to rebuild_hflags_a64 and once for those bits that remain in cpu_get_tb_cpu_state. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 131 +++++++++++++++++++++++--------------------- 1 file changed, 69 insertions(+), 62 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 8829d91ae1d..69da04786e8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11070,6 +11070,71 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, return flags; } +static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, + ARMMMUIdx mmu_idx) +{ + ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); + ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); + uint32_t flags = 0; + uint64_t sctlr; + int tbii, tbid; + + flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); + + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + if (regime_el(env, stage1) < 2) { + ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); + tbid = (p1.tbi << 1) | p0.tbi; + tbii = tbid & ~((p1.tbid << 1) | p0.tbid); + } else { + tbid = p0.tbi; + tbii = tbid & !p0.tbid; + } + + flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); + flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); + + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { + int sve_el = sve_exception_el(env, el); + uint32_t zcr_len; + + /* + * If SVE is disabled, but FP is enabled, + * then the effective len is 0. + */ + if (sve_el != 0 && fp_el == 0) { + zcr_len = 0; + } else { + zcr_len = sve_zcr_len_for_el(env, el); + } + flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); + flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); + } + + sctlr = arm_sctlr(env, el); + + if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { + /* + * In order to save space in flags, we record only whether + * pauth is "inactive", meaning all insns are implemented as + * a nop, or "active" when some action must be performed. + * The decision of which action to take is left to a helper. + */ + if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { + flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); + } + } + + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { + /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ + if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { + flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); + } + } + + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -11079,67 +11144,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, uint32_t flags = 0; if (is_a64(env)) { - ARMCPU *cpu = env_archcpu(env); - uint64_t sctlr; - *pc = env->pc; - flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); - - /* Get control bits for tagged addresses. */ - { - ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); - ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); - int tbii, tbid; - - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - if (regime_el(env, stage1) < 2) { - ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); - tbid = (p1.tbi << 1) | p0.tbi; - tbii = tbid & ~((p1.tbid << 1) | p0.tbid); - } else { - tbid = p0.tbi; - tbii = tbid & !p0.tbid; - } - - flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); - flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); - } - - if (cpu_isar_feature(aa64_sve, cpu)) { - int sve_el = sve_exception_el(env, current_el); - uint32_t zcr_len; - - /* If SVE is disabled, but FP is enabled, - * then the effective len is 0. - */ - if (sve_el != 0 && fp_el == 0) { - zcr_len = 0; - } else { - zcr_len = sve_zcr_len_for_el(env, current_el); - } - flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); - flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); - } - - sctlr = arm_sctlr(env, current_el); - - if (cpu_isar_feature(aa64_pauth, cpu)) { - /* - * In order to save space in flags, we record only whether - * pauth is "inactive", meaning all insns are implemented as - * a nop, or "active" when some action must be performed. - * The decision of which action to take is left to a helper. - */ - if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { - flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); - } - } - - if (cpu_isar_feature(aa64_bti, cpu)) { - /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ - if (sctlr & (current_el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { - flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); - } + flags = rebuild_hflags_a64(env, current_el, fp_el, mmu_idx); + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } } else { @@ -11159,9 +11166,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); } - } - flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags); + flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags); + } /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: From patchwork Tue Oct 22 13:31:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177177 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4890612ill; Tue, 22 Oct 2019 06:48:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqz1yE2a7qVIXhnhZljXC6Hb3ZQC3GNAkk+Zh2NIK5Hi2sakFzzMhSCiqb0QP5cz8jJlvdka X-Received: by 2002:a37:5b46:: with SMTP id p67mr3058044qkb.318.1571752115843; Tue, 22 Oct 2019 06:48:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571752115; cv=none; d=google.com; s=arc-20160816; b=cYmde2jBiTElRvcV5wQnGiGp+7UxuKZYku1dCCnU77Pf6OhiU191oGgaQJIRo192qG M6HYv5YizwJGBuuX/lqcSgZ1mxIu5pLOGZKls3lukJWlQ8VdYp0laqOoatzWJpHtlWey NkVnuzvjbEdgLel3zAm4b/dBbqObSlHXIvS+WsdXqhFhVwrEaxZL/2BEKTEkMw4LRinP cjLMV+Vzo3jmsg+/W8kIjlgW3aFhZXoLHeIEMrzyL1Bh+bREo1KKS0/acn+BONhhjcyB D2pYJjoEgNaeePcFt71GTTwVWv6XeW/2H5rdlj3+hxBIZds9scAg2/UvRx+WwUt7Rl4p tqZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qHBbFwWpTe9roVO0og+7rDfMnZMMxLAZ2erc0L9NCXQ=; b=sCbeAlSet5f71BwCRUnX2hyJq1IonXEGHEZ7vW2Tf90nsQQNtigHAsK+tjGVH5pOpq 6YeL7ezHQ2nDaWUlBozPIh0AQqLwmToJx8UkZThgJM5xjA73EAu1OImyqjUQ8HynkPfn 7jXqYeOB9RepATgLfPsLwxxRdl0qhYQQRqcN7IszgBwjSBI4P9jXqwsN27Yei3ZZNpkM /5Lg5UIYQo/AHYEz2yORg7UaPoLD56zj+VnVxf2x03IRbaoj8Q+cAkyaeV9umYg/NRrP 71ce2dbmLfO1jasUDqXF3dLH85GAJc8bva87sRkbDggwBjkoHJnjKVv86aaPmXv9l2IB B6ZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yzPCQ5Yq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/41] target/arm: Split out rebuild_hflags_common_32 Date: Tue, 22 Oct 2019 14:31:06 +0100 Message-Id: <20191022133134.14487-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Create a function to compute the values of the TBFLAG_A32 bits that will be cached, and are used by all profiles. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 69da04786e8..f05d0424745 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11070,6 +11070,15 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, return flags; } +static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, uint32_t flags) +{ + flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); + flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); + + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); +} + static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { @@ -11141,7 +11150,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, ARMMMUIdx mmu_idx = arm_mmu_idx(env); int current_el = arm_current_el(env); int fp_el = fp_exception_el(env, current_el); - uint32_t flags = 0; + uint32_t flags; if (is_a64(env)) { *pc = env->pc; @@ -11151,12 +11160,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } else { *pc = env->regs[15]; + flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); - flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); - flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); @@ -11166,8 +11174,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); } - - flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags); } /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine From patchwork Tue Oct 22 13:31:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177174 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4885560ill; Tue, 22 Oct 2019 06:44:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqwlsZS8m6A/GT4nVeltheUDzJkBLF4odXUDi/7JNIZi5jFbW8sYEUV194gTx//F7QE1sgFs X-Received: by 2002:a0c:c482:: with SMTP id u2mr3156215qvi.121.1571751866586; Tue, 22 Oct 2019 06:44:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571751866; cv=none; d=google.com; s=arc-20160816; b=m9ijGs/TWeIIc13ZWJJu5DpLkRu9wjJZLCVLgAkLHt39/8bHYW5xp0IwzrvPYYBss3 HM1aoMAz6L1twrDG2KACk1CE7A/uBf5pgUcycrr2Ga2WMLrOpn0e7aCTfzeBi0ofGUJM JnTsW/K9W+5Z/yMLEuhHEDgY/UUpT5JaQt4tTEy4/T6B37hQpl/7iac6jMBDhOMCzAoQ sym/oN047oHiFdQMSprpKUeqa5JgErk+H4uTcdkFmOeDHIyAqgOW6VTi3vkhUDdHiQo0 ymZNLYtH2+WJrYSm2cTNWryl2WFVzYXoZQX6Ff92V4WZEodxLqJ1cXNzeC6VqrmHD3CO 6uyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1/0uDc0DHGob6UAKtFOsK23bEJ5ERJbBTkT9fbpptos=; b=gCeM0vM9TiTuuVOMFmo8Nm+MFygEj+sBiUJNu4S5U+v29yjeR4+UZcd1Mk3RIZCzun ZgxAIHyu+KfeNJtvHg0g0Kl3IzqF9hL9okPbrviSspwex1sm5Dcb9ialtfoBndpNrzqW XTuLEWn8rTLiW8SluDOEZEA4zCuzpJCUURFNLKH5OCdPUPm4HqEhyfxd50XKertv13K7 TqJqpH/8bAGw9hPKB8MdeOK9MaywslvcAAwCaNIEXMSuQgIk01lBiqVusKOwHYDsOCh2 GeSPMfRy61x69gSd8SPV0U5JHCs4ijHjQ5YV1QdHtoWX4CqdgZrgaGls7kcXXfP4EtSS NG9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S0xTMDAR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/41] target/arm: Split arm_cpu_data_is_big_endian Date: Tue, 22 Oct 2019 14:31:07 +0100 Message-Id: <20191022133134.14487-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Set TBFLAG_ANY.BE_DATA in rebuild_hflags_common_32 and rebuild_hflags_a64 instead of rebuild_hflags_common, where we do not need to re-test is_a64() nor re-compute the various inputs. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 49 +++++++++++++++++++++++++++------------------ target/arm/helper.c | 16 +++++++++++---- 2 files changed, 42 insertions(+), 23 deletions(-) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ad79a6153bb..4d961474ce7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3108,33 +3108,44 @@ static inline uint64_t arm_sctlr(CPUARMState *env, int el) } } +static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, + bool sctlr_b) +{ +#ifdef CONFIG_USER_ONLY + /* + * In system mode, BE32 is modelled in line with the + * architecture (as word-invariant big-endianness), where loads + * and stores are done little endian but from addresses which + * are adjusted by XORing with the appropriate constant. So the + * endianness to use for the raw data access is not affected by + * SCTLR.B. + * In user mode, however, we model BE32 as byte-invariant + * big-endianness (because user-only code cannot tell the + * difference), and so we need to use a data access endianness + * that depends on SCTLR.B. + */ + if (sctlr_b) { + return true; + } +#endif + /* In 32bit endianness is determined by looking at CPSR's E bit */ + return env->uncached_cpsr & CPSR_E; +} + +static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) +{ + return sctlr & (el ? SCTLR_EE : SCTLR_E0E); +} /* Return true if the processor is in big-endian mode. */ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) { - /* In 32bit endianness is determined by looking at CPSR's E bit */ if (!is_a64(env)) { - return -#ifdef CONFIG_USER_ONLY - /* In system mode, BE32 is modelled in line with the - * architecture (as word-invariant big-endianness), where loads - * and stores are done little endian but from addresses which - * are adjusted by XORing with the appropriate constant. So the - * endianness to use for the raw data access is not affected by - * SCTLR.B. - * In user mode, however, we model BE32 as byte-invariant - * big-endianness (because user-only code cannot tell the - * difference), and so we need to use a data access endianness - * that depends on SCTLR.B. - */ - arm_sctlr_b(env) || -#endif - ((env->uncached_cpsr & CPSR_E) ? 1 : 0); + return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); } else { int cur_el = arm_current_el(env); uint64_t sctlr = arm_sctlr(env, cur_el); - - return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0; + return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); } } diff --git a/target/arm/helper.c b/target/arm/helper.c index f05d0424745..4c65476d936 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11061,9 +11061,6 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); - if (arm_cpu_data_is_big_endian(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); - } if (arm_singlestep_active(env)) { flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); } @@ -11073,7 +11070,14 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, uint32_t flags) { - flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); + bool sctlr_b = arm_sctlr_b(env); + + if (sctlr_b) { + flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, 1); + } + if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + } flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); return rebuild_hflags_common(env, fp_el, mmu_idx, flags); @@ -11122,6 +11126,10 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, sctlr = arm_sctlr(env, el); + if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + } + if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { /* * In order to save space in flags, we record only whether From patchwork Tue Oct 22 13:31:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177176 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4890240ill; Tue, 22 Oct 2019 06:48:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqyCifMibNAhobobsFi75biYH341M+Uiels4biElgGa99qVyIQ81NWSEfWWpVMih5UVK3+p+ X-Received: by 2002:a0c:c792:: with SMTP id k18mr3070398qvj.154.1571752096623; Tue, 22 Oct 2019 06:48:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571752096; cv=none; d=google.com; s=arc-20160816; b=Ss6u10rjC5BrF+6mtIoQY1GKhGo45b3hArDAlqO6a/QtYNVOuZS7dIoRlfvCriJZSQ Axy9ELMiHoecccK3DeqajhAADCOqvnFOv0NKicUVMmj8gYErh7o3s68P5cpRAYrNNdrb F7sSsFTi7WwaxImqRRvEUU1v7OTDQH6Zpv6hFU7Y0dQKCo4BvAaW3UssYKkYKJwxWd8H j+oXp8hp5LBAH8Sb12FZEUppo3GiJFABmU9I4ftwa9NhQ2MPwysfWoWkKRC7+wtoalaH Ev2xO6GZhk0PHNICRoxk4j+mSPhcKDeaAwqhD/t91ZwNE4DOeXbtBEqYtTRtcunygIaO koIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Cu6oVuHK3bWpUoid4fFJqnNglUadyF8qdViMi5V1xKs=; b=xPgeEsy+Y58GCiOp9pnobvDxYazrQ7zy43HjMdAMSOZ0yv+hYbjMlUy117cmV6sAn1 5f1+QF3phHWVUjbj1PNX653nfCg8p3Zzmvq+zaUY9MMdRyFUzzmZQskTNWYgUbRZmgAV aEkAUNsqv+i5F6uyRhtPnEwmr0zoiCPGbVpbCg2AT/gK4Z6isPmuJ3sYBWJ1KytZzWbh LDCjwB+HtnUPcKuuS2XVvScfaHkQ1SHaK3fYjZWuwockUc0xhP9Zh+paPSy2gExzRtRG n4vBbq/Ro6n1S3ttUWTlUyB/OHMjcLvF0vbZWTqL8GkEONATx/L1/roMISnQiMlLsWVj EFQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="LVn2di/B"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/41] target/arm: Split out rebuild_hflags_m32 Date: Tue, 22 Oct 2019 14:31:08 +0100 Message-Id: <20191022133134.14487-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Create a function to compute the values of the TBFLAG_A32 bits that will be cached, and are used by M-profile. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 45 ++++++++++++++++++++++++++++++--------------- 1 file changed, 30 insertions(+), 15 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 4c65476d936..d4303420daf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11083,6 +11083,29 @@ static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } +static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx) +{ + uint32_t flags = 0; + + if (arm_v7m_is_handler_mode(env)) { + flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); + } + + /* + * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN + * is suppressing them because the requested execution priority + * is less than 0. + */ + if (arm_feature(env, ARM_FEATURE_V8) && + !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && + (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { + flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); + } + + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); +} + static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { @@ -11168,7 +11191,13 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } else { *pc = env->regs[15]; - flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); + + if (arm_feature(env, ARM_FEATURE_M)) { + flags = rebuild_hflags_m32(env, fp_el, mmu_idx); + } else { + flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); + } + flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); @@ -11204,20 +11233,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } - if (arm_v7m_is_handler_mode(env)) { - flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); - } - - /* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN is - * suppressing them because the requested execution priority is less than 0. - */ - if (arm_feature(env, ARM_FEATURE_V8) && - arm_feature(env, ARM_FEATURE_M) && - !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && - (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { - flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); - } - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) { flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); From patchwork Tue Oct 22 13:31:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177167 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4881016ill; Tue, 22 Oct 2019 06:40:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqw3B3GVQ0SwiNZBBtBI6vd7pLV3wSNeMyFXJs14tDI7W2ertXqcqMgjTopy9zDI7M1qLhAM X-Received: by 2002:a37:7e05:: with SMTP id z5mr3123064qkc.296.1571751649339; Tue, 22 Oct 2019 06:40:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571751649; cv=none; d=google.com; s=arc-20160816; b=qdjk65l5P7hjX0m/nzWrYltRo9Zpu/KvxhM+83BDk2BMidszz8CNwC51WZGk2yh4V8 LVKq0NnUjh5wG82OzHKfzao7mtZwJhCYBAS5lIcLlX0OAUyDNchCyUhBnZl3KAALbZf6 nqU+4P0QTeEhojoCWaatpXSgD3n/FLHDGQLSUkn/yzu6tXjp/kvwa2ks15vr8gSu9Z6R APRK3iovnPe6V2naJgx0e7YipiR/WGFato02BX7Ia1Gsf8nsL3eL8pOKUZ5JUTHo85Ev 9EFqjWyWRpdFmwAq63cOIHVKV0TCS5MO8wLdMT2YKByVQkA8vI36EDQ9cYbmV4QA0Jx9 bKGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uSJ06sfOg2LD5tGvl0x+KI5+jg4UPMjf+ZwawjasdT0=; b=myUK21aZPxCABE2nYu/hNGzXStqxMiUzw3+suM9o1Q0hxNPmTI0+mGsZauJZWqEMbg aEvvMM2+WoOMgtYtVAt7kI+e4ozhKoBpcDoe4wmhWrDz9Ih4UlhL96howLTN9or19rJI 4nsKJHtLob4ib1JNn6Qw5sG308tSU4lpra+EbhBB/1ZqoIiRCwC5kpQsl7eAvOh21neI PuMxxa/BnTGRkwsEISHsdw5tPWeRrvU1rRXGtw1cjdbvwEVEeVWAlTWJmWExVKyPaW0t J44Jcxbhd8QGrFSMgGEX/XGNMjN04QuIdoF4maXLtKVDihpjmYb/V3Oz6Ysu1IKaa8+L e/ew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sG1Tj2K3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/41] target/arm: Reduce tests vs M-profile in cpu_get_tb_cpu_state Date: Tue, 22 Oct 2019 14:31:09 +0100 Message-Id: <20191022133134.14487-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Hoist the computation of some TBFLAG_A32 bits that only apply to M-profile under a single test for ARM_FEATURE_M. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 49 +++++++++++++++++++++------------------------ 1 file changed, 23 insertions(+), 26 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index d4303420daf..296a4b2232c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11194,6 +11194,29 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (arm_feature(env, ARM_FEATURE_M)) { flags = rebuild_hflags_m32(env, fp_el, mmu_idx); + + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && + FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) + != env->v7m.secure) { + flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); + } + + if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && + (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || + (env->v7m.secure && + !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { + /* + * ASPEN is set, but FPCA/SFPA indicate that there is no + * active FP context; we must create a new FP context before + * executing any FP insn. + */ + flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1); + } + + bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; + if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { + flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); + } } else { flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); } @@ -11233,32 +11256,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && - FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) { - flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); - } - - if (arm_feature(env, ARM_FEATURE_M) && - (env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && - (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || - (env->v7m.secure && - !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { - /* - * ASPEN is set, but FPCA/SFPA indicate that there is no active - * FP context; we must create a new FP context before executing - * any FP insn. - */ - flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1); - } - - if (arm_feature(env, ARM_FEATURE_M)) { - bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; - - if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { - flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); - } - } - if (!arm_feature(env, ARM_FEATURE_M)) { int target_el = arm_debug_target_el(env); From patchwork Tue Oct 22 13:31:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177173 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4885239ill; Tue, 22 Oct 2019 06:44:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqw4jXOVcOonI2Wqh9B6Nq6dD4C+N5t9/86zDc8DbeqN66p2VGTt7P4zP8Wzhv1MsMSmiLA9 X-Received: by 2002:a0c:fd63:: with SMTP id k3mr3111894qvs.185.1571751853625; Tue, 22 Oct 2019 06:44:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571751853; cv=none; d=google.com; s=arc-20160816; b=WetelUJLKPeUGj4QAVsNkhYRhNKKRHN2Tk8eLPtQWwCj1k1D55KN5HCAM2BJKemTez posHM9vphaO3fos/lKG7WkxuclsHoOB1zNf18fWNXeUTwfmUIGvin3z5QNPPl7BivHD7 Moaz8zPFeUdVZYquFf1Z6VoWKs8PWchB38GKmViWV5QzBneKlkwqkzZ3tSnOe/Zew+7y xxMvBm34cL2OxKJ570B0Q2g+z3iew8EfPPGcFAJOevETJFKr7HdNzvklbk/+Y2NB6bWO RV+6em4MdXpVZ9/kgUQUZKvST47/lpoCpHdz9Vl2ByeCjaESRNlUuPjzExLtk2pWANjn 3c9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=47L8tC+k0dqNep0IiM8o7WB4AEO/g2+8C4jrYkr9oDs=; b=qcJj3KEs9w9wOP7nUtpX0czgE+wHTWltMAlyK283l5PVgLxX8S2QntxqMP9k01rCte vWxLuA6uj8L5bWBiYeazDKfrSNsRNnu+AWW43OhdNYtrkrZoRH6Wla3GnvT26EV3TlBq kqUGKsz3M+0PERU5UQ9RY8Uul42Q/CBNidooprZG76fYhtv5iY03fzSM9WOJxPNeWYr7 V5kqIfx51XAyzDKMhZ11I2LeyaGS08v64Y/8quxLKwJdxF3zwcka7O1TUPfIOY2sG1rg IBHqvDuBIe5J9hYvfKY8BM0fnvJyLIfiNUyt5x0c6GG3vfYP4Mf5J/DJYmsk4ABXs+d6 05gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OEgkaEBv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/41] target/arm: Split out rebuild_hflags_a32 Date: Tue, 22 Oct 2019 14:31:10 +0100 Message-Id: <20191022133134.14487-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::432 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Currently a trivial wrapper for rebuild_hflags_common_32. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 296a4b2232c..d1cd54cc931 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11106,6 +11106,12 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } +static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx) +{ + return rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); +} + static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { @@ -11218,7 +11224,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); } } else { - flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); + flags = rebuild_hflags_a32(env, fp_el, mmu_idx); } flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); From patchwork Tue Oct 22 13:31:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177178 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4893923ill; Tue, 22 Oct 2019 06:51:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqy3JSBA31TXk9Tn3EhJE5Iy2CjB/nbljTkOLi7zhfQSvJz29TEu6w44+0/2gsKX3TRYKYuF X-Received: by 2002:a17:906:32cc:: with SMTP id k12mr17146218ejk.196.1571752283016; Tue, 22 Oct 2019 06:51:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571752283; cv=none; d=google.com; s=arc-20160816; b=U1rdMMa/eKGYK/4/ESzJauM3WICMBGV4Pq3BTw612KCIKLNNu2KzhuwLPh0/yH+SSC qyypQ5vat/4Ak7BN371zj8bEeOe442BviZ+dsz+Q1A5X3nPixWlXCS5yDbIzZyPvzbar dKCIv04Q4VVGQdAjhvVzrMxt1f0ix4VgXpPxLjkjTCl8SOSyWI+fFvZwpkmddddRvGnn JnFg57OfIBHl0d7O3M70DxVFM75a/GBedun1LKtfREy8jW/UgnqtBfOWuzgsfGJIySJH cTDSdrSItLgbO49dJBQq69poB+yeKssRs0fzpyU1XazyJd+nMX8NPTdtdP5Bj4zW+9Lt DKrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BWBhqaHT6GxtdOFufe6tBUWH35ddd8XEs+xAm5zDJYo=; b=k5pmO0Ln0EBvf7dxrl7wPuNRMKLo4NlDKKgkgGb0S782EP/S/WBlXrLpWu21Dyiso2 iAuA8bwM7CatE8691iutDR0//c9hLaUORKM/Pz8TL4OBDsx1PtoBR/8BhMws2XBYV0TZ Retd3HqaAoAoZgo/EDgT+UNiF7BKdG7AgwdxWpeUu7/WnZJolRO9178JhnF7wdNs+a4r OWQxxUnpVB5Jr7eqtDBcRMunWx/ahpeF/zZS5xP9MwbouQpFY4ZnluW8TdGnpH1t7Lzg YOeWTWtKKIBrQdZW2HAg/02Y6Xjyon6H0zzXEeNQbTKmMmdcl/tGHjVb3Dudyjcz1Jo/ v6WA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ChjA06Mj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/41] target/arm: Split out rebuild_hflags_aprofile Date: Tue, 22 Oct 2019 14:31:11 +0100 Message-Id: <20191022133134.14487-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Create a function to compute the values of the TBFLAG_ANY bits that will be cached, and are used by A-profile. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index d1cd54cc931..ddd21edfcf1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11106,18 +11106,28 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } +static uint32_t rebuild_hflags_aprofile(CPUARMState *env) +{ + int flags = 0; + + flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, + arm_debug_target_el(env)); + return flags; +} + static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { - return rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); + uint32_t flags = rebuild_hflags_aprofile(env); + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { + uint32_t flags = rebuild_hflags_aprofile(env); ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); - uint32_t flags = 0; uint64_t sctlr; int tbii, tbid; @@ -11262,12 +11272,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } - if (!arm_feature(env, ARM_FEATURE_M)) { - int target_el = arm_debug_target_el(env); - - flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, target_el); - } - *pflags = flags; *cs_base = 0; } From patchwork Tue Oct 22 13:31:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177184 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4896755ill; Tue, 22 Oct 2019 06:53:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqwXmNL2LXIsK5R1Y+LgR7q6iurUUFsZCSpt6kZd3Mz3P5c0YkdAydATf1are7xzat8zkoZs X-Received: by 2002:a05:620a:2099:: with SMTP id e25mr3121260qka.84.1571752437649; Tue, 22 Oct 2019 06:53:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571752437; cv=none; d=google.com; s=arc-20160816; b=tjbeWizS5ihYzQausBV9CJWo/nRSt1+jVSllG/ltGlS+WwEgvsc5SBERzvwVKxu78N PhILLel5rUaG77OwGTG5R53jCt5L+JRo8ZzZ6M0jOcbvijrjzTVEyWrlZMSHGgJ0MQEx VnsYLoV09mCgEWtTHFdic63+kSdkiA4hZq7hcPS2KAooP62J+qkkr2i+YlcWJQnrvRv2 qMIbkUcMdQ86MOd7oNGENUbMK6Y6EkhsnNu2beadT0RAY7+2d1NslsFNjWqnqFNWnFCK p1UZZp8rGVKepKxoHSmYsyD7rB37Np3lXZYXr9ZENZy5nVnjYww08XjD4InNTRfPUdI2 Q7bA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QWlvz9xoCtL9FPUpzDpAooVc9XHZ3LGO0EPWiVhUPtw=; b=nL40vkCA2MTnucA0I3KcDv7JQsCtKqiMLXjH0+oTnWtFBOzQYAAfDbrRrWD53+A9uc YnbIpaHhv+2MBPSKkZZ2PcuuZu3i4kjXMTmiySQGixnKFnUGZ6p1KSnqr+RyTwMhp+pj icUCJNT45vL0xoUR3xwshde3l7qa2XYelhNv0XweIUaeoTXxcdguX44ehEIYH1mZm9pz SQL+kxRCqrX12LjlcQl4h8LnA7BR2PZ0kQr5Wok9Def3iZ/Yemq4rlDEW4RnHLpBO9In CMbZacThWrtTGy5BK0i68cNmLJ+y/isbZ8fOqrQSSoQEzZfXHGLa4aZjzWLaQ0waFcSi dOBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l4uahlPp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/41] target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state Date: Tue, 22 Oct 2019 14:31:12 +0100 Message-Id: <20191022133134.14487-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson We do not need to compute any of these values for M-profile. Further, XSCALE_CPAR overlaps VECSTRIDE so obviously the two sets must be mutually exclusive. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index ddd21edfcf1..e2a62cf19a0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11235,21 +11235,28 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } else { flags = rebuild_hflags_a32(env, fp_el, mmu_idx); + + /* + * Note that XSCALE_CPAR shares bits with VECSTRIDE. + * Note that VECLEN+VECSTRIDE are RES0 for M-profile. + */ + if (arm_feature(env, ARM_FEATURE_XSCALE)) { + flags = FIELD_DP32(flags, TBFLAG_A32, + XSCALE_CPAR, env->cp15.c15_cpar); + } else { + flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, + env->vfp.vec_len); + flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, + env->vfp.vec_stride); + } } flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); - flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); - flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); } - /* Note that XSCALE_CPAR shares bits with VECSTRIDE */ - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - flags = FIELD_DP32(flags, TBFLAG_A32, - XSCALE_CPAR, env->cp15.c15_cpar); - } } /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine From patchwork Tue Oct 22 13:31:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177186 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4900986ill; Tue, 22 Oct 2019 06:57:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqygQu5rIH/nlox74RECCwBYYafYeBYiYvMRPAvBB6epi/+l+yUQvWrQAF+hswa4XFANhiqO X-Received: by 2002:a37:8dc6:: with SMTP id p189mr3019477qkd.132.1571752655666; Tue, 22 Oct 2019 06:57:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571752655; cv=none; d=google.com; s=arc-20160816; b=DztmQ9u/WdBdCpmRynP+yGcbqKRC1d5u4xwPsvt0YZX1rXjIX/sOBe2ko9AZjfZrXv nFUiNfhAboisxeK8JZSIpa6tKJwZsiqO1cpL6s/fKqFRfn9UT9Lq5DzL1SxJCSx8jogh oG/OG0VsTvEp7NDBmzVWuuUTHrDrXnYIyNcdTkKwtZvHwad58AZGQS+zDXYFbwngg4no vZPKa0OOn4sbKWHB12v7O1n0qHhhJxZ3OeRGNHLtBROkgixGrXfgJDuG2hOyRIbHTYej GYTC2yeJzRSuL4xxuK9JT8P+d9MB3vbDOk4GQU4WK/z/f5gMVbCbzjr4kB5v4WpKnkm1 q6zg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=c3SRR/5ATUh31uzJHoI/RZYESh8V+bDrSMsvPoCPz8M=; b=R8PzJ2NEqE7W74TIeSvNbzFVNBxMfSoePQsp8KtfI+hGFV+PTHE0oksa4A2WVnJlfk +SRdhum+KMv+VvGQ96sVW7FZuTX6tnJiq6p2ZjOjhFtWd4046sL5vnhylHdtnzFa0GDj kkO3W79YuzQb1oTXL7oe7/bRFlGZBMPt3Au83PHAuW5PqgJ4uy1nrC1e9rttMLkgqDyb pTFhn/ByZo/N1bLpLXe7BR/Ff47uRQ0rjik66AgLk1S2I8cGZIpMZXS50DxXZ8vY5dg5 7B5WgbHxf88xxf1VilAb3weiXvemP8+/wRWEqsENRHldPmPpAydfKWqIDhHNppGzLh0l iSgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZkQXPcgh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g20si17258326qte.192.2019.10.22.06.57.35 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Oct 2019 06:57:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZkQXPcgh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57854 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iMufH-0006lo-12 for patch@linaro.org; Tue, 22 Oct 2019 09:57:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36886) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iMuGz-0002u5-Fu for qemu-devel@nongnu.org; Tue, 22 Oct 2019 09:32:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iMuGy-0001Mx-6x for qemu-devel@nongnu.org; Tue, 22 Oct 2019 09:32:29 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:38588) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iMuGy-0001Mp-1J for qemu-devel@nongnu.org; Tue, 22 Oct 2019 09:32:28 -0400 Received: by mail-wm1-x344.google.com with SMTP id 3so16198538wmi.3 for ; Tue, 22 Oct 2019 06:32:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=c3SRR/5ATUh31uzJHoI/RZYESh8V+bDrSMsvPoCPz8M=; b=ZkQXPcghisdGtbOCRm8ZF4qlfwU+4gC+R+NKDq23QQcF7w0ujogPXGYyKTylCN+WrJ j6MoGxEmzS3QoeJD4Oid8t+2WwuKHupMv3VZP91qK8MuYPsh2xp7FvLRneYTkDkxDL5z keC54L1MHPXWf2aC4wgjc1MtpT5UO4BG27E3MbqSe33ISigZQVFPLppq9vtcQvnsystF NyN+UqchjsbOl9yBlbW4XWbB+fzZ6fXI9eDjeauq0bQ59R9WLc3DT2Ak04GqXkhm2C1e mI+1fxxelG3x2nGlMBlI3aFr22nrWbwZtsIjTOn5Qx+0UpzWU9+aRzHsQRSeBHMMYkrj ugGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c3SRR/5ATUh31uzJHoI/RZYESh8V+bDrSMsvPoCPz8M=; b=SXvdMcgWzrRTJ+4MhQSsJP+9JIjaTGBkPi4vUqNh5Pf/bmkoe6XBxsMVMaxIA4oN7D tDZMR5pifkANTzWh041OGHKlaJsakwxXLHuhEK9ddoT0ahJfzdIW900GdtqdRO/xrOR+ rtGzSXGEKFzftKu5jwwAzvycO5q6xoLh/fCLgtBHmmOp2OOB/O4DDNPIg+5UEiXjQg1W fEqtvZnQ3gmMewairFCnTGX2n51zyqw+u9tywLyAqxls6VigiRsSqqjZdeYyn+vcQRgy Fti+hcOVorOPAks71tiTY9E2V7sa0BhHl0mUkUclIUmrMybcOidzqeMNbnd2LPx/viXX r63w== X-Gm-Message-State: APjAAAX5Ubt4ISss2cy2VN1RFFBVUJofGHENvpxD23ad07ZcuwmAzsnq Y6pte5BvGNcP8akxDdwNvqQmlQ5AWos= X-Received: by 2002:a7b:c186:: with SMTP id y6mr3249584wmi.67.1571751146334; Tue, 22 Oct 2019 06:32:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/41] target/arm: Simplify set of PSTATE_SS in cpu_get_tb_cpu_state Date: Tue, 22 Oct 2019 14:31:13 +0100 Message-Id: <20191022133134.14487-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Hoist the variable load for PSTATE into the existing test vs is_a64. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index e2a62cf19a0..398e5f5d6df 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11197,7 +11197,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, ARMMMUIdx mmu_idx = arm_mmu_idx(env); int current_el = arm_current_el(env); int fp_el = fp_exception_el(env, current_el); - uint32_t flags; + uint32_t flags, pstate_for_ss; if (is_a64(env)) { *pc = env->pc; @@ -11205,6 +11205,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } + pstate_for_ss = env->pstate; } else { *pc = env->regs[15]; @@ -11257,9 +11258,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); } + pstate_for_ss = env->uncached_cpsr; } - /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine + /* + * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: * SS_ACTIVE PSTATE.SS State * 0 x Inactive (the TB flag for SS is always 0) @@ -11267,16 +11270,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * 1 1 Active-not-pending * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. */ - if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE)) { - if (is_a64(env)) { - if (env->pstate & PSTATE_SS) { - flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); - } - } else { - if (env->uncached_cpsr & PSTATE_SS) { - flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); - } - } + if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) && + (pstate_for_ss & PSTATE_SS)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); } *pflags = flags; From patchwork Tue Oct 22 13:31:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177182 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4896241ill; Tue, 22 Oct 2019 06:53:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqxfKtUQBopE90Z1CN9etbxxHxpApqYAgZ3VaHu0TkXuaO4UGKBRaFjTDc2m7MaxqvR2PQmA X-Received: by 2002:a17:906:1342:: with SMTP id x2mr27308035ejb.304.1571752411927; Tue, 22 Oct 2019 06:53:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571752411; cv=none; d=google.com; s=arc-20160816; b=MfId4lcNv86FdHhFY6j/IKpcZldlRTeIg+8Zlr0QRiw4+DVcKgwFVxRNGQfMpXe81v qTqQhjGXnWzfzlJnM4mR2dWD692D1V/HaxzU4p2PPrPeTumTd/ZVaQaDUTnmyk8TNiaD 7fgPCZwDdhukokor3mraoS061s+phHwPWUQLHvzqfWqEOqYNVhQ8xFHgEs7lJJFe4Z+e WRiMcWiSxbDwNwrcoCtXoje75cQe2BfZdlth2S6I7/U8wUWle3vbPUcBDLxAqaIv/KUw wwnd/Lc2oCpFeG5dSjbnCsMFXT4u8fSm1tBQhmpgoxxRNy6EZAbToEuSpQVbgoRJEZN9 S0bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wEiv9jObGn3UqQMFxdsZgzb1ZhvxcdW3kYhCEsFF/+g=; b=wTjtbLkNe7VUaQfNTL49NQAojFBNamddKMa6ZFvYXKOv4fufyH7PrekSM9guU8TYeP UjD4Eqwh6nuU0WS9U4yA4sgI4Cir7TeoGzLvqMjSoJUhIBhwx9hbS689EM4RFPpYkBhT 9gw41b/KdD//oGAK64We8JYHUpTWu/FkPvqX7kDM2nskOqDn4nhlBNlQRkO+1qM4P6yA BZZXTHPx3WXO53xImnv9XwDVeQTwuqE6a0JsTT20Rc3A1sRSWvySnsAZWaSJtMaZXkxf BePhmvCwLE2aP7i3QKXSCy3SH5vOmcLWRv7sx0eRkOdlA7vLmXdHjKuP48RMrpfhILo4 F7GA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zxyfLAh0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/41] target/arm: Hoist computation of TBFLAG_A32.VFPEN Date: Tue, 22 Oct 2019 14:31:14 +0100 Message-Id: <20191022133134.14487-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson There are 3 conditions that each enable this flag. M-profile always enables; A-profile with EL1 as AA64 always enables. Both of these conditions can easily be cached. The final condition relies on the FPEXC register which we are not prepared to cache. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- target/arm/helper.c | 14 ++++++++++---- 2 files changed, 11 insertions(+), 5 deletions(-) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4d961474ce7..9909ff89d4f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3192,7 +3192,7 @@ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) * the same thing as the current security state of the processor! */ FIELD(TBFLAG_A32, NS, 6, 1) -FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Not cached. */ +FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) /* For M profile only, set if FPCCR.LSPACT is set */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 398e5f5d6df..89aa6fd9339 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11088,6 +11088,9 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, { uint32_t flags = 0; + /* v8M always enables the fpu. */ + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + if (arm_v7m_is_handler_mode(env)) { flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); } @@ -11119,6 +11122,10 @@ static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { uint32_t flags = rebuild_hflags_aprofile(env); + + if (arm_el_is_aa64(env, 1)) { + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + } return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } @@ -11250,14 +11257,13 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); } + if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + } } flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); - if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) - || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { - flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); - } pstate_for_ss = env->uncached_cpsr; } From patchwork Tue Oct 22 13:31:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177183 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4896723ill; Tue, 22 Oct 2019 06:53:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqwSjWVWvLsmsYzuc66ONmx40TCEhFRCPaWVL2t8D4GjMOqmNy4l4KXx8X1L+tdi2U8cgAaP X-Received: by 2002:ac8:183:: with SMTP id x3mr3389387qtf.279.1571752436388; Tue, 22 Oct 2019 06:53:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571752436; cv=none; d=google.com; s=arc-20160816; b=CLa6XdUWodQxBajUx+DSCeRyIz6Twt9cffuGJF9rPgRJYYZFI41qVnVixP7lD3Yzfa 4Mga8/CRSucF7/1N1/S2izYHFxhNb2PWf5mk5fhZkv10wMOvi+ESk7TIDluJSOTyMbSO IRIhL0FlJ1t+INK2ga9r26wW4s+VU7ozqLsW3JNg1yRosOEchcNPTJIvhpbvmtKFvMdu pSgRYlB15ixHScs+rxz0s2CjkzBRi6qzlDe4OEUSd8ZdY8XSCFxcYrBpY0guUQ0DwKqv wlDAW4VJY4k6oA/MYAuOcq2gQL0wBLHo3d1cWZFDkXFug+7FPtbyAgBdYwvlba/7eBQY nS1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GSepKuBdExAvu93R1VSsheMCP0CVd7/15avmFDHul9k=; b=oJiMr8MNpecs9drllMsnxIQ81JtrwaBnz/RiCsKEuBpIEyGdliGVIVO1TVpOH/8BQh yEVywn0AAnfLL1ZsYl3cwsiU6InZtOpRIhl+MOh8fqSKekWacdU1mTtzlb9L8bArizsh PA3rXU7fyej/I/H4DPGuUc9n/jdPi+ZOAkLLDEZjDXy91cfxG96ezU75UYv+WFjGP9Ye I2S4yvNQ8o5ybQfHUF81Fcd4qE2o/Fr05ERs40VRYRM7bP8U/8bR66NC/KZxe898UBCa 5fwaiNnwap+U4Y9F09kcdl9Y34rLGhjdGCekY82C1bHncr6jsGTavraZ54tfExzrjd1n VpCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Cu3apOc5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/41] target/arm: Add arm_rebuild_hflags Date: Tue, 22 Oct 2019 14:31:15 +0100 Message-Id: <20191022133134.14487-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This function assumes nothing about the current state of the cpu, and writes the computed value to env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 6 ++++++ target/arm/helper.c | 30 ++++++++++++++++++++++-------- 2 files changed, 28 insertions(+), 8 deletions(-) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9909ff89d4f..d844ea21d8d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3297,6 +3297,12 @@ void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque); +/** + * arm_rebuild_hflags: + * Rebuild the cached TBFLAGS for arbitrary changed processor state. + */ +void arm_rebuild_hflags(CPUARMState *env); + /** * aa32_vfp_dreg: * Return a pointer to the Dn register within env in 32-bit mode. diff --git a/target/arm/helper.c b/target/arm/helper.c index 89aa6fd9339..85de96d071a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11198,17 +11198,35 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } +static uint32_t rebuild_hflags_internal(CPUARMState *env) +{ + int el = arm_current_el(env); + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx(env); + + if (is_a64(env)) { + return rebuild_hflags_a64(env, el, fp_el, mmu_idx); + } else if (arm_feature(env, ARM_FEATURE_M)) { + return rebuild_hflags_m32(env, fp_el, mmu_idx); + } else { + return rebuild_hflags_a32(env, fp_el, mmu_idx); + } +} + +void arm_rebuild_hflags(CPUARMState *env) +{ + env->hflags = rebuild_hflags_internal(env); +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - ARMMMUIdx mmu_idx = arm_mmu_idx(env); - int current_el = arm_current_el(env); - int fp_el = fp_exception_el(env, current_el); uint32_t flags, pstate_for_ss; + flags = rebuild_hflags_internal(env); + if (is_a64(env)) { *pc = env->pc; - flags = rebuild_hflags_a64(env, current_el, fp_el, mmu_idx); if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } @@ -11217,8 +11235,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, *pc = env->regs[15]; if (arm_feature(env, ARM_FEATURE_M)) { - flags = rebuild_hflags_m32(env, fp_el, mmu_idx); - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) { @@ -11242,8 +11258,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); } } else { - flags = rebuild_hflags_a32(env, fp_el, mmu_idx); - /* * Note that XSCALE_CPAR shares bits with VECSTRIDE. * Note that VECLEN+VECSTRIDE are RES0 for M-profile. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/41] target/arm: Split out arm_mmu_idx_el Date: Tue, 22 Oct 2019 14:31:16 +0100 Message-Id: <20191022133134.14487-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32f X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Avoid calling arm_current_el() twice. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 9 +++++++++ target/arm/helper.c | 12 +++++++----- 2 files changed, 16 insertions(+), 5 deletions(-) -- 2.20.1 diff --git a/target/arm/internals.h b/target/arm/internals.h index 232d9638753..f5313dd3d42 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -949,6 +949,15 @@ void arm_cpu_update_virq(ARMCPU *cpu); */ void arm_cpu_update_vfiq(ARMCPU *cpu); +/** + * arm_mmu_idx_el: + * @env: The cpu environment + * @el: The EL to use. + * + * Return the full ARMMMUIdx for the translation regime for EL. + */ +ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el); + /** * arm_mmu_idx: * @env: The cpu environment diff --git a/target/arm/helper.c b/target/arm/helper.c index 85de96d071a..3f7d3f257d8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11026,15 +11026,12 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) } #endif -ARMMMUIdx arm_mmu_idx(CPUARMState *env) +ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) { - int el; - if (arm_feature(env, ARM_FEATURE_M)) { return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } - el = arm_current_el(env); if (el < 2 && arm_is_secure_below_el3(env)) { return ARMMMUIdx_S1SE0 + el; } else { @@ -11042,6 +11039,11 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) } } +ARMMMUIdx arm_mmu_idx(CPUARMState *env) +{ + return arm_mmu_idx_el(env, arm_current_el(env)); +} + int cpu_mmu_index(CPUARMState *env, bool ifetch) { return arm_to_core_mmu_idx(arm_mmu_idx(env)); @@ -11202,7 +11204,7 @@ static uint32_t rebuild_hflags_internal(CPUARMState *env) { int el = arm_current_el(env); int fp_el = fp_exception_el(env, el); - ARMMMUIdx mmu_idx = arm_mmu_idx(env); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); if (is_a64(env)) { return rebuild_hflags_a64(env, el, fp_el, mmu_idx); From patchwork Tue Oct 22 13:31:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177190 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4903744ill; Tue, 22 Oct 2019 07:00:01 -0700 (PDT) X-Google-Smtp-Source: APXvYqwFbQGbP7Zf0khexWgQ9Za3vgnoKBvHdYa3YWTHPTP+izULOYPpARgxqSXoASCpDCcnwt0G X-Received: by 2002:ac8:2247:: with SMTP id p7mr3515435qtp.180.1571752801553; Tue, 22 Oct 2019 07:00:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571752801; cv=none; d=google.com; s=arc-20160816; b=StxtU3gUY5bQRKzmcwcvfuOiDuQh96XkbQ8PopNU/EgWr+bk0Y5/V1gfE1tAV6mUSS LVXuFja3BNGUPGhRFaDIKG6p44R3ensKW7ZZKJQIGNfr15Fq3qHhueUaA23ucr+TBwOT cXG1kq636Pzhb1D1WOt//Gec9m7NNaf4cXZP7Ewm/CcE7vvZuDpOFohSwJofLEaqyp4H jMrc157aRNDlsnVXSkZspAhtk9GVsnHx7jShRAsukiV+JDtbhdfkSKVL+e7YPtJ+4ojY OSMg9ObXoUOJdVY6yTHQWDiIfokXBwpCCRuQTRVlICQWmcptM1i3qmYAvBniUmNN7yPg m5/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XIcMLgLOy6AOjihetZxPEvZlo29WPIvHIy0xHe5Xspw=; b=yZOfJ4FpOstfAumq8FlXwoy8RCJQDJ835BofWoBKbaifuaB31E2LJ+JjbYXEYw+I/j dIuZag9wDCgtkYUdJMB8J2uzMPcraTfc5gZLrk9YhCb3Qu2s4beqkuAyVCHRoLB6+lki PKDgCUqo+XQjXId+vprvSMnZp1S3gjAlnnzqZ2g2tUJ6nz7J2iIYRbgjAGdcQwhTke1m C8/GWrs3aCqUZvn9PjOiPPLc78vZv0moWnS3wAiK7i0bM+J1GNQsUjYhPTx/ZtYBA53B lHqcrzntjKxrrDvZlNeH22ri2qzvO1VHyEgjYXQo6JlSkfoYB/38wXEMD5Ex03PRULoW msTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Cw0FXpfY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/41] target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state Date: Tue, 22 Oct 2019 14:31:17 +0100 Message-Id: <20191022133134.14487-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson By performing this store early, we avoid having to save and restore the register holding the address around any function calls. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 3f7d3f257d8..37424e3d4dd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11225,6 +11225,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, { uint32_t flags, pstate_for_ss; + *cs_base = 0; flags = rebuild_hflags_internal(env); if (is_a64(env)) { @@ -11298,7 +11299,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } *pflags = flags; - *cs_base = 0; } #ifdef TARGET_AARCH64 From patchwork Tue Oct 22 13:31:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177191 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4905472ill; Tue, 22 Oct 2019 07:01:10 -0700 (PDT) X-Google-Smtp-Source: APXvYqz10cgX45og93h+Xu3RWxWj9QOU3/++mTj32vd4u4pWBS6zvzXo0IKbYbIMCrHCciqZgFP7 X-Received: by 2002:a05:620a:2099:: with SMTP id e25mr3154382qka.84.1571752870408; Tue, 22 Oct 2019 07:01:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571752870; cv=none; d=google.com; s=arc-20160816; b=RCwNKn2rk9c0HVTeYeD8mnsLwuV0zrmH8fW+UrDvk3TJV63XBHTqs1oEoZ8UkZhpVT Bcey+PPvUnhwP6dky/jr4mv3pEc7Jz0G39kq9WCxyJYM88GtpzXKTlcwoYz8F5fY8HbS JAk/15jJpdPGc+fVBmXn10oEMyxSFybcbq0WZhlLzPMSFwpIK9eqTtbaUpFXSaNuOGxP A5zyP9c1EVjsElZi/1IgM2v5j7zzqvfujnRhNKl6L9r4t9VL1CxXoIp0HStA89aY+Kxg LbHiMEGuDOBmoBDET6ekl2uFuA3UJ0T1ONqx7QD78nCQXoa32ucKbeVAhIoBtfaTW2hr q+3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wnRZsm7NhaxxnhkKjePsOV7gMBnf+WiZW/Dfozs982c=; b=jwgXBE82LgWMzfCZLaD99OAjtMimkevfZh5paBvk0b9/+u6NAYDYQZ881ZB5fxPIH6 97/6HuUghsLL/kzo3MAGD0LKIBfNT6n3MOei4zP1NCr14RSztDfPsEB8P1l4b8NcsyvH YkaAoLFNmBuXYL4vEof8tGWyZD9LuDJ5IqGz1RBtCEyasWgtLevkI8u4syssI9jEs1H2 3UPb7zYaz+V56T05tjHYdsBiaLbFRfz2aYqrvMR9NGTn2CZLpjWa1w6iKhjkg5yV9Y2J irY5KLYUXq7VBHgOe8PNDHpc5Lol6dCQeZy/IVS9ObzvW3nVj9YYVWEqYIsw5HMwSxMS PWFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Y4VqBYqD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/41] target/arm: Add HELPER(rebuild_hflags_{a32, a64, m32}) Date: Tue, 22 Oct 2019 14:31:18 +0100 Message-Id: <20191022133134.14487-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::435 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This functions are given the mode and el state of the cpu and writes the computed value to env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.h | 4 ++++ target/arm/helper.c | 24 ++++++++++++++++++++++++ 2 files changed, 28 insertions(+) -- 2.20.1 diff --git a/target/arm/helper.h b/target/arm/helper.h index 1fb2cb5a777..3d4ec267a2c 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -90,6 +90,10 @@ DEF_HELPER_4(msr_banked, void, env, i32, i32, i32) DEF_HELPER_2(get_user_reg, i32, env, i32) DEF_HELPER_3(set_user_reg, void, env, i32, i32) +DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int) +DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) +DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) + DEF_HELPER_1(vfp_get_fpscr, i32, env) DEF_HELPER_2(vfp_set_fpscr, void, env, i32) diff --git a/target/arm/helper.c b/target/arm/helper.c index 37424e3d4dd..b2d701cf004 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11220,6 +11220,30 @@ void arm_rebuild_hflags(CPUARMState *env) env->hflags = rebuild_hflags_internal(env); } +void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) +{ + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + + env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); +} + +void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) +{ + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + + env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); +} + +void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) +{ + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + + env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx); +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { From patchwork Tue Oct 22 13:31:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177194 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4914335ill; Tue, 22 Oct 2019 07:06:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqz0xmkNllPRUByt9idQWSA7C2cq1cgdOQJGk4h1hRilUJj0x7fBk1zp/zs0XCTJS4Ta4qZr X-Received: by 2002:a37:6591:: with SMTP id z139mr3031195qkb.133.1571753210743; Tue, 22 Oct 2019 07:06:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571753210; cv=none; d=google.com; s=arc-20160816; b=qfOHGxkkHGy1JqF2SUd1Mhuvzfb34vbk6C01XFUYTXwaifHFafRnKCSzOk2AmUuiWe lzJNH0f82ZzNLQS57H49YataoXrbDkQ2C1JMfRs0p+6r1gSIIrygHk+Wo4sX2sCO4aKz 7AKqVpEucHdin8TtET02Z4NkeD43KalYGY2/znOmhCJFYOMCiSVfjmOqbCFT3cG1JKW9 r1GWP7HF6NHQ8JJ8LM6SC3nawZwichCzkjUtju82/3bGRGSqZI2O47zJVxyxKCMrDpFy RutNEHIqHVqCR2c2D7NuPn8PFk5CcJoXQ70/bUtpL+UjVYMuT3V5C4fLksZTykIuULuG YrfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xlxLXlWG2xF7OJitSg1PRqbCTnK1/cIa18eJM5Ccjb0=; b=Q2+dWz+U7/diWLs6iJW5pPilm63YwCOTX3hyU9E8la14YD1vJ8fWiyBMFAVQ/NaCuY TdRpMqm0DpGtZxntxSE0AuDfZsxMeCrEwJebmHt7ccmR70+YF8DW+wlyJenrKCM2/4X1 DgqLTbozncc77pPl8ifCNvPpl2ZcqRy6nVesI32eP5rtAnnyOVF7rSJeOzByr5jrU4RH Z9PC3dt1TGu0T7DSGJbFQKnzPzdt9oTttdHLUz+2qh6hH2UhYc+/p7s9C4/C5RyUYkgg YMBBa7hUhGyTJoAYquJ0iJXTLkAkvsma0ZyHCLjPxtTrTn67FeKICZFMIo4Ycbwn5qHr 1GpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="k4wZ9g5/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/41] target/arm: Rebuild hflags at EL changes Date: Tue, 22 Oct 2019 14:31:19 +0100 Message-Id: <20191022133134.14487-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::435 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Begin setting, but not relying upon, env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/syscall.c | 1 + target/arm/cpu.c | 1 + target/arm/helper-a64.c | 3 +++ target/arm/helper.c | 2 ++ target/arm/machine.c | 1 + target/arm/op_helper.c | 1 + 6 files changed, 9 insertions(+) -- 2.20.1 diff --git a/linux-user/syscall.c b/linux-user/syscall.c index f1ab81b9177..530c8433036 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9984,6 +9984,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, aarch64_sve_narrow_vq(env, vq); } env->vfp.zcr_el[1] = vq - 1; + arm_rebuild_hflags(env); ret = vq * 16; } return ret; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 13813fb2135..ab3e1a03616 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -406,6 +406,7 @@ static void arm_cpu_reset(CPUState *s) hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); + arm_rebuild_hflags(env); } bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index bca80bdc38b..b4cd680fc48 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1025,6 +1025,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) } else { env->regs[15] = new_pc & ~0x3; } + helper_rebuild_hflags_a32(env, new_el); qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch32 EL%d PC 0x%" PRIx32 "\n", cur_el, new_el, env->regs[15]); @@ -1036,10 +1037,12 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) } aarch64_restore_sp(env, new_el); env->pc = new_pc; + helper_rebuild_hflags_a64(env, new_el); qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); } + /* * Note that cur_el can never be 0. If new_el is 0, then * el0_a64 is return_to_aa64, else el0_a64 is ignored. diff --git a/target/arm/helper.c b/target/arm/helper.c index b2d701cf004..aae7b62458f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7998,6 +7998,7 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->regs[14] = env->regs[15] + offset; } env->regs[15] = newpc; + arm_rebuild_hflags(env); } static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) @@ -8345,6 +8346,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 = 1; aarch64_restore_sp(env, new_el); + helper_rebuild_hflags_a64(env, new_el); env->pc = addr; diff --git a/target/arm/machine.c b/target/arm/machine.c index 5c36707a7c9..eb28b2381bb 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -756,6 +756,7 @@ static int cpu_post_load(void *opaque, int version_id) if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } + arm_rebuild_hflags(&cpu->env); return 0; } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 0fd4bd02385..ccc2cecb467 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -404,6 +404,7 @@ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) * state. Do the masking now. */ env->regs[15] &= (env->thumb ? ~1 : ~3); + arm_rebuild_hflags(env); qemu_mutex_lock_iothread(); arm_call_el_change_hook(env_archcpu(env)); From patchwork Tue Oct 22 13:31:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177175 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4885776ill; Tue, 22 Oct 2019 06:44:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqxUyziUQrncKMLxKUCYG9yfVlb627gR28uNTqKsaRlX7OQCb9SHmUvnDsT/Z6sj+nBme87T X-Received: by 2002:a37:a690:: with SMTP id p138mr2943470qke.274.1571751876710; Tue, 22 Oct 2019 06:44:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571751876; cv=none; d=google.com; s=arc-20160816; b=piPLvbyRpmUBOy8LjAympJFa7Atzy1rMvmRH7Te+O6dFoyy3EImitWkgXTwVFgYUkG ZYHCrxdQ9siJOYSZ9Z3vIVdDi805WYGkNAv4iKQjaQJPv35a3RYo3P6ANDm2A9erNtHV q2r6WyVY4Zpae+/Ckut+mMyOnCE0iEYUdfwQpcrnwslCZWo/tBJEGqHpf8lylJV/T2n1 s3xLiJRPoTujoINwrDR1MbSeeCA9eUB8STO1AUrkEJ4h/UcLc3k4XhiqNuiTyL3GF8n1 nSxx4cbHKds4rN+Sctfbf+7OyqBg9icyI1/F+6lQP6ExQLP9xpJMobUGBaGRYYIFC5Yn hzWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SrVz8zV33u4/B/5UmvJ5uDPbu/uO8YsNIkly3MZVQcQ=; b=WOE/JipCkneYtl7wlDLvIRa8I3Qi37qFABhzHYKIRFOQ1dS29qq6v0nKuu6KSEo8Sg RtbhkHzRNk9frFLoCgj+QZrrPw6jdF31dMmWivdHIc7hA6aDb51NO96aqMIBcgJOFM+n np953hnAeOYvRkTILeN294A5uM6+52aMX9hIJWZb6JMkV1guTbL6OAmEvJf6H8wz73gh ifAvNB0UAocJqu4OPHAEa323qzCbQCteLw5FkO0T4kCVNVo0VQ+SZNm/hqnnxYKR+Gte fT8VodBLpbhqjZAav/l+f8OzVZcJBBLMoTlUfqo499LYYse0tdw2b5vrz7tqCjTgrBz4 KxUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QCSxk0TL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/41] target/arm: Rebuild hflags at MSR writes Date: Tue, 22 Oct 2019 14:31:20 +0100 Message-Id: <20191022133134.14487-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::433 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Continue setting, but not relying upon, env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 13 +++++++++++-- target/arm/translate.c | 28 +++++++++++++++++++++++----- 2 files changed, 34 insertions(+), 7 deletions(-) -- 2.20.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2d6cd09634c..d4bebbe6295 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1789,8 +1789,17 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ s->base.is_jmp = DISAS_UPDATE; - } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { - /* We default to ending the TB on a coprocessor register write, + } + if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { + /* + * A write to any coprocessor regiser that ends a TB + * must rebuild the hflags for the next TB. + */ + TCGv_i32 tcg_el = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, tcg_el); + tcg_temp_free_i32(tcg_el); + /* + * We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 96340520ee2..46a0bf51c95 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6890,6 +6890,8 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) ri = get_arm_cp_reginfo(s->cp_regs, ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2)); if (ri) { + bool need_exit_tb; + /* Check access permissions */ if (!cp_access_ok(s->current_el, ri, isread)) { return 1; @@ -7068,14 +7070,30 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) } } - if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { - /* I/O operations must end the TB here (whether read or write) */ - gen_lookup_tb(s); - } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { - /* We default to ending the TB on a coprocessor register write, + /* I/O operations must end the TB here (whether read or write) */ + need_exit_tb = ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && + (ri->type & ARM_CP_IO)); + + if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { + /* + * A write to any coprocessor regiser that ends a TB + * must rebuild the hflags for the next TB. + */ + TCGv_i32 tcg_el = tcg_const_i32(s->current_el); + if (arm_dc_feature(s, ARM_FEATURE_M)) { + gen_helper_rebuild_hflags_m32(cpu_env, tcg_el); + } else { + gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + } + tcg_temp_free_i32(tcg_el); + /* + * We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ + need_exit_tb = true; + } + if (need_exit_tb) { gen_lookup_tb(s); } From patchwork Tue Oct 22 13:31:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177180 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4895060ill; Tue, 22 Oct 2019 06:52:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqzgJfbZJnMX86ePEMPEXjtpMt1+v3lwSJZm5u4qLDdvEFJ6lW5erba3CDA6WmKherV8Bfvk X-Received: by 2002:a05:620a:74f:: with SMTP id i15mr3131149qki.265.1571752346685; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/41] target/arm: Rebuild hflags at CPSR writes Date: Tue, 22 Oct 2019 14:31:21 +0100 Message-Id: <20191022133134.14487-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::329 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Continue setting, but not relying upon, env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/op_helper.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.20.1 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index ccc2cecb467..b529d6c1bf7 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -224,6 +224,7 @@ uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift) void HELPER(setend)(CPUARMState *env) { env->uncached_cpsr ^= CPSR_E; + arm_rebuild_hflags(env); } /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped. @@ -387,6 +388,8 @@ uint32_t HELPER(cpsr_read)(CPUARMState *env) void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) { cpsr_write(env, val, mask, CPSRWriteByInstr); + /* TODO: Not all cpsr bits are relevant to hflags. */ + arm_rebuild_hflags(env); } /* Write the CPSR for a 32-bit exception return */ From patchwork Tue Oct 22 13:31:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177192 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4909876ill; Tue, 22 Oct 2019 07:03:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqw1jVmJfv6oJ0HONnXGheD9QAVJDeotC99SMV6Xm59DQgzAVbDW6rwQWIxHTf2TTCqp6kmi X-Received: by 2002:a17:906:6ad7:: with SMTP id q23mr26747488ejs.214.1571753030704; Tue, 22 Oct 2019 07:03:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571753030; cv=none; d=google.com; s=arc-20160816; b=GkquGi4aDAmTkV4+lqU5BjIa1mPIr9wJ2UZkS8N2FRBzhwl+YcPYVxC8iNRAKZKrNd bhe4/vdgKR0e0QDJGKwfsaMCYaZKxPXNJlu/+dGQ8BFxAyMVGWG+CyTdrgJiOWs7Hwd9 2NDLJaBN6SZHR1nJtHekVx79JHpkBohmRQ+BkmNRms7pFke9buPbXC5BJLVA+rsUd0JN dTXMau70+KChZLXP+bdm21D2xfIdgRXWbR7yyiqxQxRbbTs+d3IDm7Bdnzl6JnYr78+7 OP9yAsIzLCNviVX27uqeLi+KwZrRnLf2Hf8j5fK/gsRV6jm9XHTj3Ik/l+G9Jpjp5U5M xiSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=btuVklyn5jdYvmT5eZen6ynTwp3atEoaC3ET/0yyHkk=; b=carQIjAITAMSaaQJD6VlFfKQ9Dr7b7EK2clF/z4zM1MMfWlNbna8953S1hzzZCL5n1 PsxNP9vnAzr5JCqUMIRdjIkdhjoLkhjqBEVsP4u+l5vIquzEqyJ6I6u0o51OhRvyB3kc qiir5xHaLXhFEUrkRaRZcCkdcG8WmdOCt0CrYX9XFBi0ZSOULLyjTt5tFkPzPr3eUBEX EBhqbahrg7JgmYkMlthZD8oM0w5JIOK3kUSbZsBG9V+DcvD+eLZG96xzlDljVqFGwrP4 I7f5OoeTL/CjN74Zv2+v0Mmk12Ad8sSec5fvhkPjkdvrT2KX7usGiIRd1VVSuJhrHkhR ZkYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AAGS6PcH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/41] target/arm: Rebuild hflags at Xscale SCTLR writes Date: Tue, 22 Oct 2019 14:31:22 +0100 Message-Id: <20191022133134.14487-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Continue setting, but not relying upon, env->hflags. Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-20-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index aae7b62458f..c55783e5406 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4174,6 +4174,16 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, /* ??? Lots of these bits are not implemented. */ /* This may enable/disable the MMU, so do a TLB flush. */ tlb_flush(CPU(cpu)); + + if (ri->type & ARM_CP_SUPPRESS_TB_END) { + /* + * Normally we would always end the TB on an SCTLR write; see the + * comment in ARMCPRegInfo sctlr initialization below for why Xscale + * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild + * of hflags from the translator, so do it here. + */ + arm_rebuild_hflags(env); + } } static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, From patchwork Tue Oct 22 13:31:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177179 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4894739ill; Tue, 22 Oct 2019 06:52:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqwbb0qWbrvZxSyEbpxAW3sYw1M7giWyY3BSrx43zVclLuiE7OMfPvQBmCQQgmXIZYsDQ/+Z X-Received: by 2002:ad4:50a6:: with SMTP id d6mr3178851qvq.199.1571752328959; Tue, 22 Oct 2019 06:52:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571752328; cv=none; d=google.com; s=arc-20160816; b=DFIWd1u5u00Uoibu8XYGHmhXNXdVIfIZcqYCNBlWY5jTECnuzKNoEvFO13rplGwKF0 Lq1EG9WMFhj+KJEivDEbNsHe5n3fPbXsTF6XIBYmYH7Zq+ja5rGWpcDrnO++f+57WqrD r4r75GEiMjlhv0T1Puk3vaV/Erpb77XL75rq97rw1evSFRumzlYsptbnez4KnlgSRmsL DwOrBs1W3XkqSHqpfIp350xCDAhUm7uTqdIL06CUxNyarXquahtmlhsDYG4442tYQpYm poa5cnFEEseXOTjZzLMchDqKwT/5IUUA7UiF5/uhNmhDPoh41J9Z/2sg+YZxNQfYmh7y zWgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=10Ms0HjDWN7ux33iEvzUyQs1UaAMPIAPE/5GBQG8vsk=; b=vO3Zdi7Cf955KEJq9rWnVoncLRqapJNUfBmfEixg19an87hZ2n62LfATjUGkrfTTnl q6F0JrI4EoribsF05pTbjtroewbwHe5QenC9syMHDjn/+IB5Yhyq70PQKKcDMkHr8sC2 LguUF92SG6ZVEZ6z9luaZnYFEINwSB9aOrdrXGd5jfJoPDqqOaFRJSTBvR2Qir/W2mmY 7qbaRHqcU2ysUODprd7HYLbttzyFUyl0Pj6bU4ceEYSqcPSpgW4F92n2V6jAkCcqlAL6 8i6h7ZdJoIlSHtGkF2beH45WNxjacoK3gsrLHazsC6KWlKvHtLYGoMX44iY1klRaYC4S WOVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O8Q9LdAa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/41] target/arm: Rebuild hflags for M-profile Date: Tue, 22 Oct 2019 14:31:23 +0100 Message-Id: <20191022133134.14487-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::330 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Continue setting, but not relying upon, env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/m_helper.c | 6 ++++++ target/arm/translate.c | 5 ++++- 2 files changed, 10 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 27cd2f3f964..f2512e448e2 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -494,6 +494,7 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) switch_v7m_security_state(env, dest & 1); env->thumb = 1; env->regs[15] = dest & ~1; + arm_rebuild_hflags(env); } void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) @@ -555,6 +556,7 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) switch_v7m_security_state(env, 0); env->thumb = 1; env->regs[15] = dest; + arm_rebuild_hflags(env); } static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode, @@ -895,6 +897,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, env->regs[14] = lr; env->regs[15] = addr & 0xfffffffe; env->thumb = addr & 1; + arm_rebuild_hflags(env); } static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, @@ -1765,6 +1768,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) /* Otherwise, we have a successful exception exit. */ arm_clear_exclusive(env); + arm_rebuild_hflags(env); qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); } @@ -1837,6 +1841,7 @@ static bool do_v7m_function_return(ARMCPU *cpu) xpsr_write(env, 0, XPSR_IT); env->thumb = newpc & 1; env->regs[15] = newpc & ~1; + arm_rebuild_hflags(env); qemu_log_mask(CPU_LOG_INT, "...function return successful\n"); return true; @@ -1959,6 +1964,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) switch_v7m_security_state(env, true); xpsr_write(env, 0, XPSR_IT); env->regs[15] += 4; + arm_rebuild_hflags(env); return true; gen_invep: diff --git a/target/arm/translate.c b/target/arm/translate.c index 46a0bf51c95..2ea9da7637b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8327,7 +8327,7 @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a) static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) { - TCGv_i32 addr, reg; + TCGv_i32 addr, reg, el; if (!arm_dc_feature(s, ARM_FEATURE_M)) { return false; @@ -8337,6 +8337,9 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) gen_helper_v7m_msr(cpu_env, addr, reg); tcg_temp_free_i32(addr); tcg_temp_free_i32(reg); + el = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_m32(cpu_env, el); + tcg_temp_free_i32(el); gen_lookup_tb(s); return true; } From patchwork Tue Oct 22 13:31:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177193 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4914090ill; Tue, 22 Oct 2019 07:06:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqxB49TVvcBw4ziMmq/CIlM90hoNrvBEu59e2eL65wKSGZrlmd4oPMZzbNEvjjnMbPTHx+oo X-Received: by 2002:a37:8806:: with SMTP id k6mr3109547qkd.106.1571753201928; Tue, 22 Oct 2019 07:06:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571753201; cv=none; d=google.com; s=arc-20160816; b=wbjJ5BY/F0jaUhSF1DMgOufeDKfChquQR9rma9vb3yzlMGt4yl8eyRmsg/9nlAOmKz mFEkj1VBWDIRvU31aXTVkXvaE0ExCqZVX0somozx7NHq30u4ChAB6Gb6eqwyss+xPIZQ VqF2daz74z99bFE9HmRxhm7rOyWK/TYrCAqnUsK8VpyLp9r/VzWbUyaQCVv5UvbblKhf OiqN4E1yNrfbZgUfq5ecl0iFON/dt8jdO8eddEx70s4v8zhgmF6MMOLw4mzHcXDvnG8X NorQTzCGRlrGKp16IsOGj6QM0Q+eYFRmr8OFn0vtgOD7N5kVb8Ti9Kby4b3cIV2po1KT 5KOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=piAMQwhcAMpAuk7COCrPy9dKwgZFmvyHF81YOlRi688=; b=rofjHCaTeMxOTdssJb7Vm7Ik52fXUoTg4YBLINAuUmpz8ZHYTpzRSi/uaHbFp1Xj4b ecuuLqkiiljyn+9sZjpcvG6uQDCaTxeANOtpy2CYe4vfSspeoOEVrKYsuLe+2mb+hDH/ EyOvdWBPowrea7wBk3rkT80A2F1/K7L7YbP7DKLq032fZEF36ySAzcygNssxzeRwVSgY 2hIsVDUAdwiizf6u3NmcRnITY3tBOk5Myx7y9xhvMjbd1UEgw8vdIbN44YZinWlQ7mVU 9znJ3RWLYCkpndZGKWgkz3pgBO7Yf/tGRY3FUqS6IQqFI6d1upp9Wiy9X5upoMe1o4Ej dMxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lEJtwjdc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/41] target/arm: Rebuild hflags for M-profile NVIC Date: Tue, 22 Oct 2019 14:31:24 +0100 Message-Id: <20191022133134.14487-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Continue setting, but not relying upon, env->hflags. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-22-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) -- 2.20.1 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 8e93e51e815..e8c74f9ebaf 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2251,7 +2251,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, } } nvic_irq_update(s); - return MEMTX_OK; + goto exit_ok; case 0x200 ... 0x23f: /* NVIC Set pend */ /* the special logic in armv7m_nvic_set_pending() * is not needed since IRQs are never escalated @@ -2269,9 +2269,9 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, } } nvic_irq_update(s); - return MEMTX_OK; + goto exit_ok; case 0x300 ... 0x33f: /* NVIC Active */ - return MEMTX_OK; /* R/O */ + goto exit_ok; /* R/O */ case 0x400 ... 0x5ef: /* NVIC Priority */ startvec = (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ @@ -2281,10 +2281,10 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, } } nvic_irq_update(s); - return MEMTX_OK; + goto exit_ok; case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */ if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { - return MEMTX_OK; + goto exit_ok; } /* fall through */ case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */ @@ -2299,10 +2299,10 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, set_prio(s, hdlidx, sbank, newprio); } nvic_irq_update(s); - return MEMTX_OK; + goto exit_ok; case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */ if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { - return MEMTX_OK; + goto exit_ok; } /* All bits are W1C, so construct 32 bit value with 0s in * the parts not written by the access size @@ -2322,15 +2322,19 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, */ s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK); } - return MEMTX_OK; + goto exit_ok; } if (size == 4) { nvic_writel(s, offset, value, attrs); - return MEMTX_OK; + goto exit_ok; } qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad write of size %d at offset 0x%x\n", size, offset); /* This is UNPREDICTABLE; treat as RAZ/WI */ + + exit_ok: + /* Ensure any changes made are reflected in the cached hflags. */ + arm_rebuild_hflags(&s->cpu->env); return MEMTX_OK; } From patchwork Tue Oct 22 13:31:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177196 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp5796269ocf; Tue, 22 Oct 2019 07:09:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqwFmNHt4S9JWc1D7fMm8e7LLN1pYtZ8+cIvaFmEG80TtttUg1mFS+02wKsyGw5OGW1qUQYc X-Received: by 2002:aed:2f86:: with SMTP id m6mr3529441qtd.55.1571753370105; Tue, 22 Oct 2019 07:09:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571753370; cv=none; d=google.com; s=arc-20160816; b=LTio0cYOtP6ce7zDILJ9dFQDfbQB+lKrzhQR1OlQ1jsuBySkDy4W2OY8OmsJ+PjJ/2 om8ugpXLogfQprl2L4EPWZzPphBgZUqpY2hd8oZAGnRLUPJ7NFJGEbJ+v9Z1jZXCVuVh +jxvhxpUwa9JQPRv/ZMt0w7huHmQT3dmZeRXJpOCi+Eg7pnaSR5vifa8+g/R1Pcznbej 6hd45PKM62ROKFcGBpN18VcTkt3xRJXm2VRgWokAW/GgMVxMJ2dnL6uyH75Ll++e24pc 41jmUJbEiJ1+pDVi/Oyl2K76sNE9vE9HUA/PvpUWQSKkcuNjlZlhuilrtaSaAuSRJTZZ h5Vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bAJu0HC72frNdy2Inrafd6Q3Q7w56dol34p5z07V/hc=; b=b738rNDn7rsXiL5LVrxVT8PZzQsXLGPZ2vyFLizYNXAwztHPzIKceCIGog8/GldC/a Kt8FntqmSxAb/P5hzgQ5BcYTFFcM4tWV0ZyV2dHBrysmY9Mo1L3piQ9BzCXz2yfQJOpV zabF0s54yS1WuYJ7vyxckitQf5fVi1dtYryF3JX1fzswXjaXnd7z0tY8O1D1+k8xpb1i wc4CwnzdZbdGRl4fifUwkFsn67UXzPjOW4Uf0PW7/UHVQXWop5izHrfiRiY3qCEy4hbd bpamqkYo1+AJLwGWIO3wa5uBxQsh9aDc3wyk/GSm52RsNVTWUiVlkHlaO9OPBtImbawm Supw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Fx3oOz8h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/41] target/arm: Rely on hflags correct in cpu_get_tb_cpu_state Date: Tue, 22 Oct 2019 14:31:25 +0100 Message-Id: <20191022133134.14487-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This is the payoff. >From perf record -g data of ubuntu 18 boot and shutdown: BEFORE: - 23.02% 2.82% qemu-system-aar [.] helper_lookup_tb_ptr - 20.22% helper_lookup_tb_ptr + 10.05% tb_htable_lookup - 9.13% cpu_get_tb_cpu_state 3.20% aa64_va_parameters_both 0.55% fp_exception_el - 11.66% 4.74% qemu-system-aar [.] cpu_get_tb_cpu_state - 6.96% cpu_get_tb_cpu_state 3.63% aa64_va_parameters_both 0.60% fp_exception_el 0.53% sve_exception_el AFTER: - 16.40% 3.40% qemu-system-aar [.] helper_lookup_tb_ptr - 13.03% helper_lookup_tb_ptr + 11.19% tb_htable_lookup 0.55% cpu_get_tb_cpu_state 0.98% 0.71% qemu-system-aar [.] cpu_get_tb_cpu_state 0.87% 0.24% qemu-system-aar [.] rebuild_hflags_a64 Before, helper_lookup_tb_ptr is the second hottest function in the application, consuming almost a quarter of the runtime. Within the entire execution, cpu_get_tb_cpu_state consumes about 12%. After, helper_lookup_tb_ptr has dropped to the fourth hottest function, with consumption dropping to a sixth of the runtime. Within the entire execution, cpu_get_tb_cpu_state has dropped below 1%, and the supporting function to rebuild hflags also consumes about 1%. Assertions are retained for --enable-debug-tcg. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20191018174431.1784-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index c55783e5406..63815fc4cfc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11259,12 +11259,15 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - uint32_t flags, pstate_for_ss; + uint32_t flags = env->hflags; + uint32_t pstate_for_ss; *cs_base = 0; - flags = rebuild_hflags_internal(env); +#ifdef CONFIG_DEBUG_TCG + assert(flags == rebuild_hflags_internal(env)); +#endif - if (is_a64(env)) { + if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) { *pc = env->pc; if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); From patchwork Tue Oct 22 13:31:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177185 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4897674ill; Tue, 22 Oct 2019 06:54:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqzdJYNLqSXLpgS6bv9e3DZWKSfdluVtX1W7at5pcDME+eRxbeqHaIGbR0JGhQXUwKuD/72q X-Received: by 2002:ac8:1b45:: with SMTP id p5mr3236473qtk.330.1571752482283; Tue, 22 Oct 2019 06:54:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571752482; cv=none; d=google.com; s=arc-20160816; b=pe7RjECvo6xum6Q/062t3yxBWBwPcZwtDthf5ipSerCDTDTzkgQen8aEyRzkW0ctR6 eQc8VSYBhA7U1obu0gOBksAA+NsWAEkpEmFewbC8B+OyKO2bQjnXoeT5xyRGPsTflpSF rsDn46G62nGM+JVimVOpB8SfOC5e/m0P6dGMGDpaTkuppvpq9yNS8LnkVso1aIcrj/jm jcxWKkSlTcmHs3VThSl31BSN6p1WjWXRaFhgP9WPSH4EB7/0W1PIUbCvtasd8XtkX7Xp mDZMgiyp/SsQhqR+bZzz3imLN4CEd9msArCT5D5ekH4+M1DkEuHOZRtN5Ait+O/N4Chp OOwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5lY7u62vI3+XxTunjo9vzWs8Uh4wfjIbh9S8L0HAuyI=; b=n5J+B51UT1LY0o72hyIdC6L1Mz8xVYttNqWbot72xf3YqINc2bKf6EMdVAZb7B7gIx X9dQiyY/RZu38CziIaeE7/iwQwX7a4CHa2iqNE0pn0Nzt/LzNA+r9dTZJ10w8ou/tcg6 w+HkPbWgYD6c4w4mcvMyfMGimCj3U6PqVML3Eh8Oc5W77KdKP74j+c2I8D2ufwMUYEPO QRI+YYBjdCqZ72uxt5/lJtos+rrU32at1Px0siG7dZGGBaVKr2dbhReWCkSG/njrkxef ziYZRqi70/zpCIgkuwRE7IRZ5pjSX9q1zNhX06p3r8ByfyiMRzwLSkGCDz2va4QpXTSi cO2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YUpnIJVd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/41] hw/sd/sdhci: Add a comment to distinct the i.MX eSDHC functions Date: Tue, 22 Oct 2019 14:31:26 +0100 Message-Id: <20191022133134.14487-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé This file keeps the various QDev blocks separated by comments. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cleber Rosa Message-id: 20191005154748.21718-3-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/sd/sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index e08ec3e3985..82ec5c1b4a4 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1532,6 +1532,8 @@ static const TypeInfo sdhci_bus_info = { .class_init = sdhci_bus_class_init, }; +/* --- qdev i.MX eSDHC --- */ + static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) { SDHCIState *s = SYSBUS_SDHCI(opaque); @@ -1734,7 +1736,6 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) } } - static const MemoryRegionOps usdhc_mmio_ops = { .read = usdhc_read, .write = usdhc_write, From patchwork Tue Oct 22 13:31:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177195 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp5795980ocf; Tue, 22 Oct 2019 07:09:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqzcxPrfMj3GpumHbgr2uzNx+IEgKBCYDac4oohRiGmm8Sj8rk18j2/z8uEWmlSwbhCy5EiW X-Received: by 2002:ac8:2a83:: with SMTP id b3mr3536819qta.244.1571753359010; Tue, 22 Oct 2019 07:09:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571753359; cv=none; d=google.com; s=arc-20160816; b=B3Oxw3+H42aSGmziUmsLatXRaIBVL3huYH3ZTVnnRgOg+JyEsZZuo134gwaXkJp0zK 90XhRV3dGsVVFjBwURSosTEQ3WwCP0EsLZnzId0SbmqKqTfJp5JHXUWszhdKd6zIrKlz V4jDTFcvF8VNhjbLs2Rr+8OR3MNg1j/vLUVgmiSS+4GuzkajnaMRYXRyn133x0/LmjF8 eeigrWjsL/OxdtKkdK33pssdGBeBryNzKDxdeU0r3cHCKXl9Twc1mJ39VKlVy0jZvLWp OrUeospiMJzWcWv6XckMcRKpiWLwm+q5f0BXVfisY7UiwDZLA6CieAeADifDkUaP6GOK 9bMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VQV5FCBK+kBKKN7cw2HOegQIhSxfiRcO/BOW8D/eYOc=; b=uSXJyxk2oPK1Q42Ixhd6apvYA/os7T8R78i08GRgO9+bkb9kdYteQ6RFnomMUBWQmx 9MVmAuZ37RjreQX91EomNj/G+nbMX7luma+fTySmJxuxyW3bt06v8V6abu5xOkCZj4No BMLrnTNt1I0FCGlVr91NuOcUC8rsj0LbbZtWYkv6bBCFXYr5UjjtfU+/9omdFjepZSXu 8Y+DmCJO13YXhjHPacVF8iFnMIz8g5JDA7ShP8nP8jgWIxCHLScaXzodC10SOEnA+laq rGlmgn56Duhx5Kjrc9DDlu3iB9x6gPUVwgeTlFXIU4KopmJE2EWr1HwzUl8TevYf4CzQ Y0Fg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aa5dwVgz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/41] hw/sd/sdhci: Add dummy Samsung SDHCI controller Date: Tue, 22 Oct 2019 14:31:27 +0100 Message-Id: <20191022133134.14487-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé The Linux kernel access few S3C-specific registers [1] to set some clock. We don't care about this part for device emulation [2]. Add a dummy device to properly ignore these accesses, so we can focus on the important registers missing. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/mmc/host/sdhci-s3c-regs.h?h=cc014f3 [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/mmc/host/sdhci-s3c.c?h=v5.3#n263 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Krzysztof Kozlowski Message-id: 20191005154748.21718-4-f4bug@amsat.org Signed-off-by: Peter Maydell --- include/hw/sd/sdhci.h | 2 ++ hw/sd/sdhci.c | 65 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+) -- 2.20.1 diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index cbf415e43ab..c6868c96994 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -116,4 +116,6 @@ typedef struct SDHCIState { #define TYPE_IMX_USDHC "imx-usdhc" +#define TYPE_S3C_SDHCI "s3c-sdhci" + #endif /* SDHCI_H */ diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 82ec5c1b4a4..88404d0e9d5 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1761,11 +1761,76 @@ static const TypeInfo imx_usdhc_info = { .instance_init = imx_usdhc_init, }; +/* --- qdev Samsung s3c --- */ + +#define S3C_SDHCI_CONTROL2 0x80 +#define S3C_SDHCI_CONTROL3 0x84 +#define S3C_SDHCI_CONTROL4 0x8c + +static uint64_t sdhci_s3c_read(void *opaque, hwaddr offset, unsigned size) +{ + uint64_t ret; + + switch (offset) { + case S3C_SDHCI_CONTROL2: + case S3C_SDHCI_CONTROL3: + case S3C_SDHCI_CONTROL4: + /* ignore */ + ret = 0; + break; + default: + ret = sdhci_read(opaque, offset, size); + break; + } + + return ret; +} + +static void sdhci_s3c_write(void *opaque, hwaddr offset, uint64_t val, + unsigned size) +{ + switch (offset) { + case S3C_SDHCI_CONTROL2: + case S3C_SDHCI_CONTROL3: + case S3C_SDHCI_CONTROL4: + /* ignore */ + break; + default: + sdhci_write(opaque, offset, val, size); + break; + } +} + +static const MemoryRegionOps sdhci_s3c_mmio_ops = { + .read = sdhci_s3c_read, + .write = sdhci_s3c_write, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + .unaligned = false + }, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void sdhci_s3c_init(Object *obj) +{ + SDHCIState *s = SYSBUS_SDHCI(obj); + + s->io_ops = &sdhci_s3c_mmio_ops; +} + +static const TypeInfo sdhci_s3c_info = { + .name = TYPE_S3C_SDHCI , + .parent = TYPE_SYSBUS_SDHCI, + .instance_init = sdhci_s3c_init, +}; + static void sdhci_register_types(void) { type_register_static(&sdhci_sysbus_info); type_register_static(&sdhci_bus_info); type_register_static(&imx_usdhc_info); + type_register_static(&sdhci_s3c_info); } type_init(sdhci_register_types) From patchwork Tue Oct 22 13:31:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177181 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4895516ill; Tue, 22 Oct 2019 06:52:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqwCD2MpAHVUUhlM7PWc7aqkG+W0hQ2s4eKb6beTZbt/IkXeBWqbaephnoTLt0HF/3WOtzCm X-Received: by 2002:a0c:d2b4:: with SMTP id q49mr439607qvh.135.1571752371093; Tue, 22 Oct 2019 06:52:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571752371; cv=none; d=google.com; s=arc-20160816; b=cChMIGXiVtzUm6kNxbMGi2pjVAftMxH8iHTljhFvH4oMCsRMhf4el4TZ25uFLSL6pz qOxRkaGcSA9pqj58PDiJMhusYlk3ehxgnXfgnpiqX48bgdE51biXR4y2HswnuNzWuDTD W9n0qNcNP7HklhVexVCVs8DHWYFZW/QZvoBox62RkAOfBA7btL6huh9zuh+DK7Cwu/Ms L79d6WyNyQNaI2vMOXUFC4PV2bUT1BdBftF7J2v6rpPhfgbuaO8EK7m7RTe0KQwCNG2Q Pq7D7Kwny0WhjCIr5eMDA7RZEZ+VDWQJ/g5zYRX2aXj3YxhJ5VndKnpnmQUhRRpOHTFs 5SCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mHOfSzeg99iHQUMRCgLtiz+W3r24W00ST4fut/Vk9N4=; b=aCtMEn3OmXvu7WA9JWGLh1505njyE8d7p8+qS1ike02tphWr1EVrf4cifM61miIylr 9cuZRnYqlRYxpME0m3mdhoiUFVnUD8Tnde2A08wU+QfT8E49pzB3JjZrpjHHmBxZ+tDl TT0DIj+SWj3eqSqaSq2dgv1Bk7weEIpbpQwBZWrhagffHiLkm1oykCqRm/WiaiSfQodX uSDQ1cBsBz6uG/zowA+q0Fwb+4YZZ1i3QG/EQ5h2WOX2Il/5CVNki1jjyE1dIuPspw/7 EJlnc66VugRaCWXeN8vDnixvP989AWLAX5f3ve4S0dQLfu5XtQltfNvAJupJK8rI+VHF vOOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AeKXDNb+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/41] hw/arm/exynos4210: Use the Samsung s3c SDHCI controller Date: Tue, 22 Oct 2019 14:31:28 +0100 Message-Id: <20191022133134.14487-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé The Exynos SoC has specific SDHCI registers. Use the s3c SDHCI model which handle these specific registers. This silents the following "SDHC ... not implemented" warnings so we can focus on the important registers missing: $ qemu-system-arm ... -d unimp \ -append "... root=/dev/mmcblk0 rootfstype=ext4 rw rootwait" \ -drive file=linux-build-test/rootfs/arm/rootfs-armv5.ext2,if=sd,format=raw [...] [ 25.744858] sdhci: Secure Digital Host Controller Interface driver [ 25.745862] sdhci: Copyright(c) Pierre Ossman [ 25.783188] s3c-sdhci 12530000.sdhci: clock source 2: mmc_busclk.2 (12000000 Hz) SDHC rd_4b @0x80 not implemented SDHC wr_4b @0x80 <- 0x00000020 not implemented SDHC wr_4b @0x8c <- 0x00030000 not implemented SDHC rd_4b @0x80 not implemented SDHC wr_4b @0x80 <- 0xc0004100 not implemented SDHC wr_4b @0x84 <- 0x80808080 not implemented [ 26.013318] mmc0: SDHCI controller on samsung-hsmmc [12530000.sdhci] using ADMA [ 26.032318] Synopsys Designware Multimedia Card Interface Driver [ 42.024885] Waiting for root device /dev/mmcblk0... Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Krzysztof Kozlowski Message-id: 20191005154748.21718-5-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/arm/exynos4210.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index a9f8a5c8688..77fbe1baabc 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -405,7 +405,7 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) * public datasheet which is very similar (implementing * MMC Specification Version 4.0 being the only difference noted) */ - dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI); + dev = qdev_create(NULL, TYPE_S3C_SDHCI); qdev_prop_set_uint64(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES); qdev_init_nofail(dev); From patchwork Tue Oct 22 13:31:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177198 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp5801319ocf; Tue, 22 Oct 2019 07:13:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqw3PB7DeVObqHUmuFtJ7NhlOsOK00CIKkQXTRndpJ76S1ZMqBNcg/xzziK4d+60PgvuLgNf X-Received: by 2002:a37:7b44:: with SMTP id w65mr3136739qkc.409.1571753591379; Tue, 22 Oct 2019 07:13:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571753591; cv=none; d=google.com; s=arc-20160816; b=VxIMGkwJ9nBAMqPfxbt+UE+9ttQY9+EKXfT+opTn0wpiUBsqmCeiqtaw8OM+wcRmCb uR6PaDUy7FLvOC5IkjuFoKG+helXLkQHTHcM9MEM0rwvdw8UBngu6Gs+kv6TNAzg0hjr XTtzAM4ZG/rG0NnqGNr0MAn0ViMaVWhnvVOZzsyisORlhGKE2rpPyF4njPzIxSeHly6Z c2bbfW24U0N0Go0ALT5gT24u4+q2rcDIv5saRS/2jlOWFTOf8haPPwUZwqu0da0BcvPS 95eHo/EG9oZ4E5ka0mndLAS1pMg30B0+lMBs+6uwHBbAjAuBR46wukhNyruACD3Tbm8P AMMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Jd3gjjSWtiLGtLKohxwgc1UFQoof9TDDl8oztxXNFqQ=; b=TtO+w7DAjFLLcWgVhHuMre82DMhnP7tZf1qya5t/NdgkFiMb7VYh1QdH7cwp+o4DIe FERhB3r7NC992DjFS6YhYzlOXVQ/169kmh7734HxI1F4Ei3sjdjNK7GQN0pEi5nz0N8G 1j02NR7/dhoVrolgGYMC9sXYh9V5E0wfLivDQQMCKFmFtf6QZ0sh0uiZQZ/jZyWXFx2x YGMAvssZ7H2efrUDVWadaIcK7X7CVmBCwKIFmINIye94ONMONCgEybaFYr7YTHYflz7q Mjymi2MmtlefDx+5o29XtCw0w4i2HRFEUhqYT6fOercfNJJvKC+kjbns7Sw7TcGJ/sHr RUPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GwZdJvg5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:32:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/41] hw/arm/xilinx_zynq: Use the IEC binary prefix definitions Date: Tue, 22 Oct 2019 14:31:29 +0100 Message-Id: <20191022133134.14487-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé IEC binary prefixes ease code review: the unit is explicit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20191021190653.9511-2-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/arm/xilinx_zynq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index c14774e542c..3a0fa5b23f7 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -16,6 +16,7 @@ */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "qapi/error.h" #include "cpu.h" #include "hw/sysbus.h" @@ -194,7 +195,7 @@ static void zynq_init(MachineState *machine) memory_region_add_subregion(address_space_mem, 0, ext_ram); /* 256K of on-chip memory */ - memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10, + memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB, &error_fatal); memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); From patchwork Tue Oct 22 13:31:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177197 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp5796761ocf; Tue, 22 Oct 2019 07:09:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqyVP/0JR4PKUDpFezE9X9/htncshQAsgUNO5MY0TMDNTDRBN76nNfupegXZRI8dcjCcQ2Cb X-Received: by 2002:ac8:6890:: with SMTP id m16mr3505759qtq.227.1571753393108; Tue, 22 Oct 2019 07:09:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571753393; cv=none; d=google.com; s=arc-20160816; b=daqjUTbQ0BcuthUe0YznNpWgUc9GCMr3460+0JK3hMzHFNije/OzpM7D/IoQ4U5VcG z4CSLzcSyisDjhAu2wJuG8tUZ17kw+kZrPSSgXISikTlLzX4j2TFTwWC6wEK+tVe17uv TCeZQmDuPuMEXJWhhO1ccAq0sserS+DQHH4EHEc4urN264frSMHcy8r5qJc94pSD7uJ+ RZErQJKZLI4g6ZDz15XNDLP8zczjfNqRm7ts4UJ2Qt+KETtBYUmsYG5VFuUA3KkqLWtA 3yr+X5AsMqVPPNyOIwaXt1vJp3e4VBauWpqof2lsNAbGSoIWQDoJiQMO/NwRyORwLZGa E2RQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IoXcmOl+RMmkT7xPfub9s2J7YQU8S0ooN19xanzMCEA=; b=WFSUNm+Ykhow1iRYFG9tV2e1X01qpYiiFqhfgJjx4qkvgSR1diwTxI3VzQnoIOtOx5 0+ruf6EOQwJEqcn1qfcLirhVHQQRgFjExrmylKCNoSoCFXsEwWGNkBvAs1cLl74GicqZ l+87fEkIXv9mhABziL5wKizQE4pJ5r7bINsZlt59CaJWsP9k/iA3MSKTRJcIP61wTMOy WatCEDo4ciqeeCMDX8T+3NZf/uKI6ltjZ53YtUA/bwsZddda/C7qx8NyvA4BLojQzPX/ P9AqWQhd4QUiIERwAWBhsblkjiP6/bLV+HeIiTLqRWbVgnMPG51i3vJT/DIkNhILVA8B M1Xw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OmebtgvY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.32.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:33:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/41] hw/arm/mps2: Use the IEC binary prefix definitions Date: Tue, 22 Oct 2019 14:31:30 +0100 Message-Id: <20191022133134.14487-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé IEC binary prefixes ease code review: the unit is explicit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20191021190653.9511-3-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 3 ++- hw/arm/mps2.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 6b24aaacded..f8b620bcc65 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -38,6 +38,7 @@ */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/arm/boot.h" @@ -458,7 +459,7 @@ static void mps2tz_common_init(MachineState *machine) * call the 16MB our "system memory", as it's the largest lump. */ memory_region_allocate_system_memory(&mms->psram, - NULL, "mps.ram", 0x01000000); + NULL, "mps.ram", 16 * MiB); memory_region_add_subregion(system_memory, 0x80000000, &mms->psram); /* The overflow IRQs for all UARTs are ORed together. diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 10efff36b23..d002b126d39 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -23,6 +23,7 @@ */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/arm/boot.h" @@ -146,7 +147,7 @@ static void mps2_common_init(MachineState *machine) * zbt_boot_ctrl is always zero). */ memory_region_allocate_system_memory(&mms->psram, - NULL, "mps.ram", 0x1000000); + NULL, "mps.ram", 16 * MiB); memory_region_add_subregion(system_memory, 0x21000000, &mms->psram); switch (mmc->fpga_type) { From patchwork Tue Oct 22 13:31:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177189 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4902268ill; Tue, 22 Oct 2019 06:58:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqxlZ4rAg4gma68uucC/yHeWl5SYG6DCAZ3dhR8UTGK/nN9Gu7VYywAbfqqXI0wmQaX+UlI8 X-Received: by 2002:a05:6402:20c:: with SMTP id t12mr7509585edv.109.1571752721516; Tue, 22 Oct 2019 06:58:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571752721; cv=none; d=google.com; s=arc-20160816; b=QvY9xt6RwKSZw55NopibNL37QMfnKGWBTKEg91Ib1QW+FiqOI4vo2IoIrywwjaPNkK qqCcCX7breOep3+xmHOAfc+m+0TqnLR6qjEL4EuCn/sgraj4lgUnjCQOnUBXEkkVGZYf Zy+xRCquU2LfegZXYSmViAImOBFBPIMWsVZC0SIhIthmyeTY/dAolefZkZlB5Ai4R02A /or28dL5yu4R6dSQDIJH8mYtEAMh53aQlfCDFgBlHFwL8zehsohWe3VwZf9QlXSmuUWA G64q19twQ/Dla46Y8WV2FNXByT8U2g5XzRW7x0npQgtsqM4yOctLp5gLV8UVXfH4Ygo9 Rnog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bRVLYeRm52S1+mDtVEVVM44iNY6mCQd1H1UdrE+pTLs=; b=LQfYHn6zr4gbAa8zQJhliRd1THwIc1qVB2xYZ9UMpx0qzY0IMeoQwtTSnevia8U5jH Dueg///2IRIJQlanAVhtqg5pkbJLUHpod3KcUAsvoICg6GPz7txO9KipfMjbH8Mk8/M4 LN2UfVQBVaQwDybinU1s9Uby7JzpVQiQ/L8VA2ROD0Zo/qWUUXn0rjlujFA3ZwPYpImL OL4NDunGQ/IcUePQiSor3qt08gJd688cHVmBurKC0kqYQrIkF3nHHeSii0tZPyUqyVp3 3b207lz/tyF5/SP/nABdWsrp0HRlrZN+ZKsjKRbMHJtSXRE/mRQ4GZqmFKSGube3by80 45fw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LgDtlhSZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.33.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:33:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/41] hw/arm/collie: Create the RAM in the board Date: Tue, 22 Oct 2019 14:31:31 +0100 Message-Id: <20191022133134.14487-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé The SDRAM is incorrectly created in the SA1110 SoC. Move its creation in the board code, this will later allow the board to have the QOM ownership of the RAM. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20191021190653.9511-4-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/arm/strongarm.h | 4 +--- hw/arm/collie.c | 8 ++++++-- hw/arm/strongarm.c | 7 +------ 3 files changed, 8 insertions(+), 11 deletions(-) -- 2.20.1 diff --git a/hw/arm/strongarm.h b/hw/arm/strongarm.h index e98840b461a..192821f6aab 100644 --- a/hw/arm/strongarm.h +++ b/hw/arm/strongarm.h @@ -55,7 +55,6 @@ enum { typedef struct { ARMCPU *cpu; - MemoryRegion sdram; DeviceState *pic; DeviceState *gpio; DeviceState *ppc; @@ -63,7 +62,6 @@ typedef struct { SSIBus *ssp_bus; } StrongARMState; -StrongARMState *sa1110_init(MemoryRegion *sysmem, - unsigned int sdram_size, const char *rev); +StrongARMState *sa1110_init(const char *cpu_type); #endif diff --git a/hw/arm/collie.c b/hw/arm/collie.c index b1288ccea80..970a4405ccf 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -27,9 +27,13 @@ static void collie_init(MachineState *machine) { StrongARMState *s; DriveInfo *dinfo; - MemoryRegion *sysmem = get_system_memory(); + MemoryRegion *sdram = g_new(MemoryRegion, 1); - s = sa1110_init(sysmem, collie_binfo.ram_size, machine->cpu_type); + s = sa1110_init(machine->cpu_type); + + memory_region_allocate_system_memory(sdram, NULL, "strongarm.sdram", + collie_binfo.ram_size); + memory_region_add_subregion(get_system_memory(), SA_SDCS0, sdram); dinfo = drive_get(IF_PFLASH, 0, 0); pflash_cfi01_register(SA_CS0, "collie.fl1", 0x02000000, diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index dc65d88a657..6bee0349149 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -1586,8 +1586,7 @@ static const TypeInfo strongarm_ssp_info = { }; /* Main CPU functions */ -StrongARMState *sa1110_init(MemoryRegion *sysmem, - unsigned int sdram_size, const char *cpu_type) +StrongARMState *sa1110_init(const char *cpu_type) { StrongARMState *s; int i; @@ -1601,10 +1600,6 @@ StrongARMState *sa1110_init(MemoryRegion *sysmem, s->cpu = ARM_CPU(cpu_create(cpu_type)); - memory_region_allocate_system_memory(&s->sdram, NULL, "strongarm.sdram", - sdram_size); - memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram); - s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000, qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ), qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ), From patchwork Tue Oct 22 13:31:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177188 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4901986ill; Tue, 22 Oct 2019 06:58:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqxMZJBZUHzNL8FI6SwmCf671P5ZbTvK82fLq+mXdrgLZ/fqEv2A1b5qunwjA47F4+4+3Hp7 X-Received: by 2002:a50:cb85:: with SMTP id k5mr31128798edi.131.1571752707989; Tue, 22 Oct 2019 06:58:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571752707; cv=none; d=google.com; s=arc-20160816; b=zwxLbaEaWJW/KiNGoF/1ihUomycndUJgv4SfP1iJnS0FbmkO2OETAKI6Va9dlLSeXI m9B9frQuIIZpjtSzxhSWWWYuvCWYiwhPp+8hP0OU3DPpunrr9yyXqITeWvjNkmwnqoQ0 pj/HA3wQ4yeRzUwAX90I+IZxZCCzYH/GV/TS9a8pci3vYsSguJWJ7qrUDItOFERrDrnW ISJUmL2LHtRVQ8954LyvgKdSBujznWprelfGkenz3/IIGhAx95BFjNGU1KVTz7V4R2MI kk0+E8JrBuzh9OhZKUTNsbnIKDDgkwbYDLDVHQde2OKBtrQPsY9IeFp+kgwLmx/J+tiE N8eQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fMt1yXYtkl6zou9KhMTTPZc3Shey7XPrKQCkblw9TjE=; b=NON+wBhAh3T31HShfPETyJOEXxa8z/0Oj16S+kniYy6ij/lWYvHjIAWN3eGv23mL4a lH9xjsEHKwKw0+yLEQflqcr+rvJ/hidYU0QrPWG2SVt5yb1vhq/vJplXtq10rNSzO6xg D5f9g+RD7aKDrPpkdB6YAvRohpjYHAAQeAKFiXz+r4qitRm6CK3WpzHmk0dDYtJ31/dg +krHwkmAaTp4DhC4XHM6JDh9KMqTSg0PmzFxYHz1sf617e/WYrDAO31j5GZb8SssOa9h 4E+oALEz7pLWeIbts5S0A5DOAwbHxFv5ctg/PNxhkFnZaZMGjO1OxWkVo4GgRGIUyqk1 zE+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Tb8zhrNK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.33.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:33:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/41] hw/arm/omap2: Create the RAM in the board Date: Tue, 22 Oct 2019 14:31:32 +0100 Message-Id: <20191022133134.14487-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé The SDRAM is incorrectly created in the OMAP2420 SoC. Move its creation in the board code, this will later allow the board to have the QOM ownership of the RAM. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20191021190653.9511-5-philmd@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/omap.h | 4 +--- hw/arm/nseries.c | 10 +++++++--- hw/arm/omap2.c | 13 +++++-------- 3 files changed, 13 insertions(+), 14 deletions(-) -- 2.20.1 diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index 2fda9966484..763d8eab4fa 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -824,7 +824,6 @@ struct omap_mpu_state_s { MemoryRegion tap_iomem; MemoryRegion imif_ram; MemoryRegion emiff_ram; - MemoryRegion sdram; MemoryRegion sram; struct omap_dma_port_if_s { @@ -938,8 +937,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, const char *core); /* omap2.c */ -struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, - unsigned long sdram_size, +struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram, const char *core); uint32_t omap_badwidth_read8(void *opaque, hwaddr addr); diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c index a36971d39aa..7e361936a9d 100644 --- a/hw/arm/nseries.c +++ b/hw/arm/nseries.c @@ -47,6 +47,7 @@ /* Nokia N8x0 support */ struct n800_s { + MemoryRegion sdram; struct omap_mpu_state_s *mpu; struct rfbi_chip_s blizzard; @@ -1311,11 +1312,14 @@ static int n810_atag_setup(const struct arm_boot_info *info, void *p) static void n8x0_init(MachineState *machine, struct arm_boot_info *binfo, int model) { - MemoryRegion *sysmem = get_system_memory(); struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s)); - int sdram_size = binfo->ram_size; + uint64_t sdram_size = binfo->ram_size; - s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_type); + memory_region_allocate_system_memory(&s->sdram, NULL, "omap2.dram", + sdram_size); + memory_region_add_subregion(get_system_memory(), OMAP2_Q2_BASE, &s->sdram); + + s->mpu = omap2420_mpu_init(&s->sdram, machine->cpu_type); /* Setup peripherals * diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c index bd7ddff9831..457f152baca 100644 --- a/hw/arm/omap2.c +++ b/hw/arm/omap2.c @@ -22,6 +22,7 @@ #include "qemu/error-report.h" #include "qapi/error.h" #include "cpu.h" +#include "exec/address-spaces.h" #include "sysemu/blockdev.h" #include "sysemu/qtest.h" #include "sysemu/reset.h" @@ -2276,8 +2277,7 @@ static const struct dma_irq_map omap2_dma_irq_map[] = { { 0, OMAP_INT_24XX_SDMA_IRQ3 }, }; -struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, - unsigned long sdram_size, +struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram, const char *cpu_type) { struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1); @@ -2286,11 +2286,11 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, int i; SysBusDevice *busdev; struct omap_target_agent_s *ta; + MemoryRegion *sysmem = get_system_memory(); /* Core */ s->mpu_model = omap2420; s->cpu = ARM_CPU(cpu_create(cpu_type)); - s->sdram_size = sdram_size; s->sram_size = OMAP242X_SRAM_SIZE; s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0); @@ -2299,9 +2299,6 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, omap_clk_init(s); /* Memory-mapped stuff */ - memory_region_allocate_system_memory(&s->sdram, NULL, "omap2.dram", - s->sdram_size); - memory_region_add_subregion(sysmem, OMAP2_Q2_BASE, &s->sdram); memory_region_init_ram(&s->sram, NULL, "omap2.sram", s->sram_size, &error_fatal); memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram); @@ -2338,8 +2335,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, s->port->addr_valid = omap2_validate_addr; /* Register SDRAM and SRAM ports for fast DMA transfers. */ - soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sdram), - OMAP2_Q2_BASE, s->sdram_size); + soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(sdram), + OMAP2_Q2_BASE, memory_region_size(sdram)); soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sram), OMAP2_SRAM_BASE, s->sram_size); From patchwork Tue Oct 22 13:31:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177200 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp5809149ocf; Tue, 22 Oct 2019 07:19:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqwcsWdktFTlcCNSjjswt7/c1eC+oKUGum29NqzMs0gaM2zBik5Vk+ALvC5CcsBsp9LF9EHF X-Received: by 2002:a0c:ee49:: with SMTP id m9mr3406684qvs.118.1571753949380; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.33.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:33:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/41] hw/arm/omap1: Create the RAM in the board Date: Tue, 22 Oct 2019 14:31:33 +0100 Message-Id: <20191022133134.14487-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé The SDRAM is incorrectly created in the OMAP310 SoC. Move its creation in the board code, this will later allow the board to have the QOM ownership of the RAM. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20191021190653.9511-6-philmd@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/omap.h | 6 ++---- hw/arm/omap1.c | 12 +++++------- hw/arm/omap_sx1.c | 8 ++++++-- hw/arm/palm.c | 8 ++++++-- 4 files changed, 19 insertions(+), 15 deletions(-) -- 2.20.1 diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index 763d8eab4fa..f3aa6700361 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -823,7 +823,6 @@ struct omap_mpu_state_s { MemoryRegion mpui_io_iomem; MemoryRegion tap_iomem; MemoryRegion imif_ram; - MemoryRegion emiff_ram; MemoryRegion sram; struct omap_dma_port_if_s { @@ -835,7 +834,7 @@ struct omap_mpu_state_s { hwaddr addr); } port[__omap_dma_port_last]; - unsigned long sdram_size; + uint64_t sdram_size; unsigned long sram_size; /* MPUI-TIPB peripherals */ @@ -932,8 +931,7 @@ struct omap_mpu_state_s { }; /* omap1.c */ -struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, - unsigned long sdram_size, +struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram, const char *core); /* omap2.c */ diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 0400593805e..6ce038a4535 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -23,6 +23,7 @@ #include "qapi/error.h" #include "qemu-common.h" #include "cpu.h" +#include "exec/address-spaces.h" #include "hw/boards.h" #include "hw/hw.h" #include "hw/irq.h" @@ -3858,8 +3859,7 @@ static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr); } -struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, - unsigned long sdram_size, +struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram, const char *cpu_type) { int i; @@ -3867,11 +3867,12 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, qemu_irq dma_irqs[6]; DriveInfo *dinfo; SysBusDevice *busdev; + MemoryRegion *system_memory = get_system_memory(); /* Core */ s->mpu_model = omap310; s->cpu = ARM_CPU(cpu_create(cpu_type)); - s->sdram_size = sdram_size; + s->sdram_size = memory_region_size(dram); s->sram_size = OMAP15XX_SRAM_SIZE; s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0); @@ -3880,9 +3881,6 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, omap_clk_init(s); /* Memory-mapped stuff */ - memory_region_allocate_system_memory(&s->emiff_ram, NULL, "omap1.dram", - s->sdram_size); - memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram); memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size, &error_fatal); memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram); @@ -3925,7 +3923,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; /* Register SDRAM and SRAM DMA ports for fast transfers. */ - soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->emiff_ram), + soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(dram), OMAP_EMIFF_BASE, s->sdram_size); soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram), OMAP_IMIF_BASE, s->sram_size); diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index c071197be7f..be245714dbb 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -103,6 +103,7 @@ static void sx1_init(MachineState *machine, const int version) { struct omap_mpu_state_s *mpu; MemoryRegion *address_space = get_system_memory(); + MemoryRegion *dram = g_new(MemoryRegion, 1); MemoryRegion *flash = g_new(MemoryRegion, 1); MemoryRegion *cs = g_new(MemoryRegion, 4); static uint32_t cs0val = 0x00213090; @@ -118,8 +119,11 @@ static void sx1_init(MachineState *machine, const int version) flash_size = flash2_size; } - mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, - machine->cpu_type); + memory_region_allocate_system_memory(dram, NULL, "omap1.dram", + sx1_binfo.ram_size); + memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, dram); + + mpu = omap310_mpu_init(dram, machine->cpu_type); /* External Flash (EMIFS) */ memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size, diff --git a/hw/arm/palm.c b/hw/arm/palm.c index 02a3a82b9b5..72eca8cc556 100644 --- a/hw/arm/palm.c +++ b/hw/arm/palm.c @@ -190,16 +190,20 @@ static void palmte_init(MachineState *machine) MemoryRegion *address_space_mem = get_system_memory(); struct omap_mpu_state_s *mpu; int flash_size = 0x00800000; - int sdram_size = palmte_binfo.ram_size; static uint32_t cs0val = 0xffffffff; static uint32_t cs1val = 0x0000e1a0; static uint32_t cs2val = 0x0000e1a0; static uint32_t cs3val = 0xe1a0e1a0; int rom_size, rom_loaded = 0; + MemoryRegion *dram = g_new(MemoryRegion, 1); MemoryRegion *flash = g_new(MemoryRegion, 1); MemoryRegion *cs = g_new(MemoryRegion, 4); - mpu = omap310_mpu_init(address_space_mem, sdram_size, machine->cpu_type); + memory_region_allocate_system_memory(dram, NULL, "omap1.dram", + palmte_binfo.ram_size); + memory_region_add_subregion(address_space_mem, OMAP_EMIFF_BASE, dram); + + mpu = omap310_mpu_init(dram, machine->cpu_type); /* External Flash (EMIFS) */ memory_region_init_ram(flash, NULL, "palmte.flash", flash_size, From patchwork Tue Oct 22 13:31:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 177199 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp5801955ocf; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm20263856wma.1.2019.10.22.06.33.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 06:33:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 41/41] hw/arm/digic4: Inline digic4_board_setup_ram() function Date: Tue, 22 Oct 2019 14:31:34 +0100 Message-Id: <20191022133134.14487-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191022133134.14487-1-peter.maydell@linaro.org> References: <20191022133134.14487-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::333 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Having the RAM creation code in a separate function is not very helpful. Move this code directly inside the board_init() function, this will later allow the board to have the QOM ownership of the RAM. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20191021190653.9511-7-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/arm/digic_boards.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) -- 2.20.1 diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index 304e4d1a294..ef3fc2b6a5f 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -53,12 +53,6 @@ typedef struct DigicBoard { const char *rom1_def_filename; } DigicBoard; -static void digic4_board_setup_ram(DigicBoardState *s, hwaddr ram_size) -{ - memory_region_allocate_system_memory(&s->ram, NULL, "ram", ram_size); - memory_region_add_subregion(get_system_memory(), 0, &s->ram); -} - static void digic4_board_init(DigicBoard *board) { Error *err = NULL; @@ -72,7 +66,8 @@ static void digic4_board_init(DigicBoard *board) exit(1); } - digic4_board_setup_ram(s, board->ram_size); + memory_region_allocate_system_memory(&s->ram, NULL, "ram", board->ram_size); + memory_region_add_subregion(get_system_memory(), 0, &s->ram); if (board->add_rom0) { board->add_rom0(s, DIGIC4_ROM0_BASE, board->rom0_def_filename);